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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.4 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_eb_e.v,v $
// Revision 1.4 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No user `defines in this module
module inst_eb_e
//
// Generated Module inst_eb
//
(
p_mix_c_addr_12_0_gi,
p_mix_c_bus_in_31_0_gi,
p_mix_tmi_sbist_fail_12_10_go
);
// Generated Module Inputs:
input [12:0] p_mix_c_addr_12_0_gi;
input [31:0] p_mix_c_bus_in_31_0_gi;
// Generated Module Outputs:
output [2:0] p_mix_tmi_sbist_fail_12_10_go;
// Generated Wires:
wire [12:0] p_mix_c_addr_12_0_gi;
wire [31:0] p_mix_c_bus_in_31_0_gi;
wire [2:0] p_mix_tmi_sbist_fail_12_10_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
wire [12:0] tmi_sbist_fail; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign c_addr = p_mix_c_addr_12_0_gi; // __I_I_BUS_PORT
assign c_bus_in = p_mix_c_bus_in_31_0_gi; // __I_I_BUS_PORT
assign p_mix_tmi_sbist_fail_12_10_go[2:0] = tmi_sbist_fail[12:10]; // __I_O_SLICE_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba (
.c_addr_i(c_addr),
.c_bus_i(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.mbist_aci_fail_o(tmi_sbist_fail[10]),
.mbist_vcd_fail_o(tmi_sbist_fail[11])
);
// End of Generated Instance Port Map for inst_eba
// Generated Instance Port Map for inst_ebb
inst_ebb_e inst_ebb (
.c_addr_i(c_addr),
.c_bus_i(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.mbist_sum_fail_o(tmi_sbist_fail[12])
);
// End of Generated Instance Port Map for inst_ebb
// Generated Instance Port Map for inst_ebc
inst_ebc_e inst_ebc (
.c_addr(c_addr),
.c_bus_in(c_bus_in) // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
// End of Generated Instance Port Map for inst_ebc
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_gt_rx_valid_filter_7x.v
// Version : 1.10
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
module pcie_core_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
`timescale 1 ps / 1 ps
module system_wrapper
(AC_BCLK,
AC_MCLK,
AC_MUTE_N,
AC_PBLRC,
AC_RECLRC,
AC_SDATA_I,
AC_SDATA_O,
BLUE_O,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GREEN_O,
HDMI_CLK_N,
HDMI_CLK_P,
HDMI_D0_N,
HDMI_D0_P,
HDMI_D1_N,
HDMI_D1_P,
HDMI_D2_N,
HDMI_D2_P,
HDMI_OEN,
HSYNC_O,
RED_O,
VSYNC_O,
btns_4bits_tri_i,
iic_0_scl_io,
iic_0_sda_io,
leds_4bits_tri_o,
sws_4bits_tri_i);
output [0:0]AC_BCLK;
output AC_MCLK;
output [0:0]AC_MUTE_N;
output [0:0]AC_PBLRC;
output [0:0]AC_RECLRC;
input AC_SDATA_I;
output [0:0]AC_SDATA_O;
output [4:0]BLUE_O;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [5:0]GREEN_O;
output HDMI_CLK_N;
output HDMI_CLK_P;
output HDMI_D0_N;
output HDMI_D0_P;
output HDMI_D1_N;
output HDMI_D1_P;
output HDMI_D2_N;
output HDMI_D2_P;
output [0:0]HDMI_OEN;
output HSYNC_O;
output [4:0]RED_O;
output VSYNC_O;
input [3:0]btns_4bits_tri_i;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]leds_4bits_tri_o;
input [3:0]sws_4bits_tri_i;
wire [0:0]AC_BCLK;
wire AC_MCLK;
wire [0:0]AC_MUTE_N;
wire [0:0]AC_PBLRC;
wire [0:0]AC_RECLRC;
wire AC_SDATA_I;
wire [0:0]AC_SDATA_O;
wire [4:0]BLUE_O;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [5:0]GREEN_O;
wire HDMI_CLK_N;
wire HDMI_CLK_P;
wire HDMI_D0_N;
wire HDMI_D0_P;
wire HDMI_D1_N;
wire HDMI_D1_P;
wire HDMI_D2_N;
wire HDMI_D2_P;
wire [0:0]HDMI_OEN;
wire HSYNC_O;
wire [4:0]RED_O;
wire VSYNC_O;
wire [3:0]btns_4bits_tri_i;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]leds_4bits_tri_o;
wire [3:0]sws_4bits_tri_i;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
system system_i
(.AC_BCLK(AC_BCLK),
.AC_MCLK(AC_MCLK),
.AC_MUTE_N(AC_MUTE_N),
.AC_PBLRC(AC_PBLRC),
.AC_RECLRC(AC_RECLRC),
.AC_SDATA_I(AC_SDATA_I),
.AC_SDATA_O(AC_SDATA_O),
.BLUE_O(BLUE_O),
.BTNs_4Bits_tri_i(btns_4bits_tri_i),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GREEN_O(GREEN_O),
.HDMI_CLK_N(HDMI_CLK_N),
.HDMI_CLK_P(HDMI_CLK_P),
.HDMI_D0_N(HDMI_D0_N),
.HDMI_D0_P(HDMI_D0_P),
.HDMI_D1_N(HDMI_D1_N),
.HDMI_D1_P(HDMI_D1_P),
.HDMI_D2_N(HDMI_D2_N),
.HDMI_D2_P(HDMI_D2_P),
.HDMI_OEN(HDMI_OEN),
.HSYNC_O(HSYNC_O),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.LEDs_4Bits_tri_o(leds_4bits_tri_o),
.RED_O(RED_O),
.SWs_4Bits_tri_i(sws_4bits_tri_i),
.VSYNC_O(VSYNC_O));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:43 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/RAT_ControlUnit_0_0_sim_netlist.v
// Design : RAT_ControlUnit_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_ControlUnit_0_0,ControlUnit,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ControlUnit,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_ControlUnit_0_0
(CLK,
C,
Z,
INT,
RST,
OPCODE_HI_5,
OPCODE_LO_2,
PC_LD,
PC_INC,
PC_RESET,
PC_OE,
PC_MUX_SEL,
SP_LD,
SP_MUX_SEL,
SP_RESET,
RF_WR,
RF_WR_SEL,
RF_OE,
REG_IMMED_SEL,
ALU_SEL,
ALU_OPY_SEL,
SCR_WR,
SCR_OE,
SCR_ADDR_SEL,
C_FLAG_SEL,
C_FLAG_LD,
C_FLAG_SET,
C_FLAG_CLR,
SHAD_C_LD,
Z_FLAG_SEL,
Z_FLAG_LD,
Z_FLAG_SET,
Z_FLAG_CLR,
SHAD_Z_LD,
I_FLAG_SET,
I_FLAG_CLR,
IO_OE);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
input C;
input Z;
input INT;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST RST" *) input RST;
input [4:0]OPCODE_HI_5;
input [1:0]OPCODE_LO_2;
output PC_LD;
output PC_INC;
(* x_interface_info = "xilinx.com:signal:reset:1.0 PC_RESET RST" *) output PC_RESET;
output PC_OE;
output [1:0]PC_MUX_SEL;
output SP_LD;
output [1:0]SP_MUX_SEL;
(* x_interface_info = "xilinx.com:signal:reset:1.0 SP_RESET RST" *) output SP_RESET;
output RF_WR;
output [1:0]RF_WR_SEL;
output RF_OE;
output REG_IMMED_SEL;
output [3:0]ALU_SEL;
output ALU_OPY_SEL;
output SCR_WR;
output SCR_OE;
output [1:0]SCR_ADDR_SEL;
output C_FLAG_SEL;
output C_FLAG_LD;
output C_FLAG_SET;
output C_FLAG_CLR;
output SHAD_C_LD;
output Z_FLAG_SEL;
output Z_FLAG_LD;
output Z_FLAG_SET;
output Z_FLAG_CLR;
output SHAD_Z_LD;
output I_FLAG_SET;
output I_FLAG_CLR;
output IO_OE;
wire \<const0> ;
wire ALU_OPY_SEL;
wire [3:0]\^ALU_SEL ;
wire CLK;
wire INT;
wire IO_OE;
wire IO_OE_INST_0_i_1_n_0;
wire [4:0]OPCODE_HI_5;
wire [1:0]OPCODE_LO_2;
wire PC_INC;
wire PC_LD;
wire PC_LD_INST_0_i_1_n_0;
wire PC_OE;
wire PC_RESET;
wire RF_OE;
wire RF_OE_INST_0_i_1_n_0;
wire RF_WR;
wire [1:1]\^RF_WR_SEL ;
wire RST;
assign ALU_SEL[3:2] = \^ALU_SEL [3:2];
assign ALU_SEL[1] = \^ALU_SEL [2];
assign ALU_SEL[0] = \^ALU_SEL [0];
assign C_FLAG_CLR = \<const0> ;
assign C_FLAG_LD = \^ALU_SEL [0];
assign C_FLAG_SEL = \<const0> ;
assign C_FLAG_SET = \<const0> ;
assign I_FLAG_CLR = PC_OE;
assign I_FLAG_SET = \<const0> ;
assign PC_MUX_SEL[1] = PC_OE;
assign PC_MUX_SEL[0] = \<const0> ;
assign REG_IMMED_SEL = \<const0> ;
assign RF_WR_SEL[1] = \^RF_WR_SEL [1];
assign RF_WR_SEL[0] = \^RF_WR_SEL [1];
assign SCR_ADDR_SEL[1] = PC_OE;
assign SCR_ADDR_SEL[0] = PC_OE;
assign SCR_OE = \<const0> ;
assign SCR_WR = PC_OE;
assign SHAD_C_LD = \<const0> ;
assign SHAD_Z_LD = \<const0> ;
assign SP_LD = PC_OE;
assign SP_MUX_SEL[1] = PC_OE;
assign SP_MUX_SEL[0] = \<const0> ;
assign SP_RESET = PC_RESET;
assign Z_FLAG_CLR = \<const0> ;
assign Z_FLAG_LD = \^ALU_SEL [0];
assign Z_FLAG_SEL = \<const0> ;
assign Z_FLAG_SET = \<const0> ;
GND GND
(.G(\<const0> ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
IO_OE_INST_0_i_1
(.I0(OPCODE_HI_5[1]),
.I1(OPCODE_HI_5[4]),
.O(IO_OE_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0100))
PC_LD_INST_0_i_1
(.I0(OPCODE_HI_5[3]),
.I1(OPCODE_HI_5[0]),
.I2(OPCODE_HI_5[4]),
.I3(OPCODE_HI_5[2]),
.O(PC_LD_INST_0_i_1_n_0));
LUT2 #(
.INIT(4'h2))
RF_OE_INST_0_i_1
(.I0(OPCODE_LO_2[1]),
.I1(OPCODE_LO_2[0]),
.O(RF_OE_INST_0_i_1_n_0));
RAT_ControlUnit_0_0_ControlUnit U0
(.ALU_OPY_SEL(ALU_OPY_SEL),
.ALU_SEL({\^ALU_SEL [3:2],\^ALU_SEL [0]}),
.CLK(CLK),
.INT(INT),
.IO_OE(IO_OE),
.OPCODE_HI_5(OPCODE_HI_5),
.OPCODE_HI_5_2__s_port_(PC_LD_INST_0_i_1_n_0),
.\OPCODE_HI_5_4__s_port_] (IO_OE_INST_0_i_1_n_0),
.OPCODE_LO_2(OPCODE_LO_2),
.\OPCODE_LO_2_0__s_port_] (RF_OE_INST_0_i_1_n_0),
.PC_INC(PC_INC),
.PC_LD(PC_LD),
.PC_OE(PC_OE),
.PC_RESET(PC_RESET),
.RF_OE(RF_OE),
.RF_WR(RF_WR),
.RF_WR_SEL(\^RF_WR_SEL ),
.RST(RST));
endmodule
(* ORIG_REF_NAME = "ControlUnit" *)
module RAT_ControlUnit_0_0_ControlUnit
(ALU_OPY_SEL,
PC_RESET,
PC_OE,
IO_OE,
RF_OE,
RF_WR_SEL,
RF_WR,
ALU_SEL,
PC_LD,
PC_INC,
\OPCODE_HI_5_4__s_port_] ,
OPCODE_HI_5,
\OPCODE_LO_2_0__s_port_] ,
OPCODE_LO_2,
INT,
OPCODE_HI_5_2__s_port_,
CLK,
RST);
output ALU_OPY_SEL;
output PC_RESET;
output PC_OE;
output IO_OE;
output RF_OE;
output [0:0]RF_WR_SEL;
output RF_WR;
output [2:0]ALU_SEL;
output PC_LD;
output PC_INC;
input \OPCODE_HI_5_4__s_port_] ;
input [4:0]OPCODE_HI_5;
input \OPCODE_LO_2_0__s_port_] ;
input [1:0]OPCODE_LO_2;
input INT;
input OPCODE_HI_5_2__s_port_;
input CLK;
input RST;
wire ALU_OPY_SEL;
wire ALU_OPY_SEL_reg_i_1_n_0;
wire ALU_OPY_SEL_reg_i_2_n_0;
wire [2:0]ALU_SEL;
wire CLK;
wire INT;
wire IO_OE;
wire [1:0]NS;
wire [4:0]OPCODE_HI_5;
wire OPCODE_HI_5_2__s_net_1;
wire OPCODE_HI_5_4__s_net_1;
wire [1:0]OPCODE_LO_2;
wire OPCODE_LO_2_0__s_net_1;
wire PC_INC;
wire PC_LD;
wire PC_OE;
wire PC_RESET;
wire [1:0]PS;
wire RF_OE;
wire RF_WR;
wire RF_WR_INST_0_i_1_n_0;
wire RF_WR_INST_0_i_2_n_0;
wire [0:0]RF_WR_SEL;
wire \RF_WR_SEL[0]_INST_0_i_1_n_0 ;
wire RST;
assign OPCODE_HI_5_2__s_net_1 = OPCODE_HI_5_2__s_port_;
assign OPCODE_HI_5_4__s_net_1 = \OPCODE_HI_5_4__s_port_] ;
assign OPCODE_LO_2_0__s_net_1 = \OPCODE_LO_2_0__s_port_] ;
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0))
ALU_OPY_SEL_reg
(.CLR(1'b0),
.D(ALU_OPY_SEL_reg_i_1_n_0),
.G(ALU_OPY_SEL_reg_i_2_n_0),
.GE(1'b1),
.Q(ALU_OPY_SEL));
LUT5 #(
.INIT(32'h40000040))
ALU_OPY_SEL_reg_i_1
(.I0(OPCODE_HI_5[2]),
.I1(OPCODE_HI_5[1]),
.I2(OPCODE_HI_5[4]),
.I3(OPCODE_HI_5[0]),
.I4(OPCODE_HI_5[3]),
.O(ALU_OPY_SEL_reg_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
ALU_OPY_SEL_reg_i_2
(.I0(PS[1]),
.I1(PS[0]),
.O(ALU_OPY_SEL_reg_i_2_n_0));
LUT6 #(
.INIT(64'hFF000820AA000820))
\ALU_SEL[1]_INST_0
(.I0(RF_WR_INST_0_i_1_n_0),
.I1(OPCODE_LO_2[0]),
.I2(OPCODE_LO_2[1]),
.I3(OPCODE_HI_5[1]),
.I4(OPCODE_HI_5[4]),
.I5(RF_WR_INST_0_i_2_n_0),
.O(ALU_SEL[1]));
LUT6 #(
.INIT(64'hAAAA0C0000000000))
\ALU_SEL[3]_INST_0
(.I0(RF_WR_INST_0_i_2_n_0),
.I1(RF_WR_INST_0_i_1_n_0),
.I2(OPCODE_LO_2[1]),
.I3(OPCODE_LO_2[0]),
.I4(OPCODE_HI_5[4]),
.I5(OPCODE_HI_5[1]),
.O(ALU_SEL[2]));
LUT6 #(
.INIT(64'h0000000000080000))
IO_OE_INST_0
(.I0(OPCODE_HI_5_4__s_net_1),
.I1(OPCODE_HI_5[3]),
.I2(OPCODE_HI_5[0]),
.I3(OPCODE_HI_5[2]),
.I4(PS[1]),
.I5(PS[0]),
.O(IO_OE));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h8))
I_FLAG_CLR_INST_0
(.I0(PS[0]),
.I1(PS[1]),
.O(PC_OE));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
PC_INC_INST_0
(.I0(PS[0]),
.I1(PS[1]),
.O(PC_INC));
LUT6 #(
.INIT(64'hFFFF00000002FFFF))
PC_LD_INST_0
(.I0(OPCODE_HI_5_2__s_net_1),
.I1(OPCODE_LO_2[0]),
.I2(OPCODE_LO_2[1]),
.I3(OPCODE_HI_5[1]),
.I4(PS[1]),
.I5(PS[0]),
.O(PC_LD));
LUT2 #(
.INIT(4'hB))
\PS[0]_i_1
(.I0(PS[1]),
.I1(PS[0]),
.O(NS[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h2C))
\PS[1]_i_1
(.I0(INT),
.I1(PS[0]),
.I2(PS[1]),
.O(NS[1]));
FDCE \PS_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(RST),
.D(NS[0]),
.Q(PS[0]));
FDCE \PS_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(RST),
.D(NS[1]),
.Q(PS[1]));
LUT6 #(
.INIT(64'h3030000000001000))
RF_OE_INST_0
(.I0(OPCODE_HI_5[3]),
.I1(OPCODE_HI_5[0]),
.I2(\RF_WR_SEL[0]_INST_0_i_1_n_0 ),
.I3(OPCODE_LO_2_0__s_net_1),
.I4(OPCODE_HI_5[4]),
.I5(OPCODE_HI_5[1]),
.O(RF_OE));
LUT6 #(
.INIT(64'hFFFF028088880280))
RF_WR_INST_0
(.I0(RF_WR_INST_0_i_1_n_0),
.I1(OPCODE_HI_5[1]),
.I2(OPCODE_LO_2[0]),
.I3(OPCODE_LO_2[1]),
.I4(OPCODE_HI_5[4]),
.I5(RF_WR_INST_0_i_2_n_0),
.O(RF_WR));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000100))
RF_WR_INST_0_i_1
(.I0(OPCODE_HI_5[3]),
.I1(OPCODE_HI_5[0]),
.I2(OPCODE_HI_5[2]),
.I3(PS[1]),
.I4(PS[0]),
.O(RF_WR_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000800))
RF_WR_INST_0_i_2
(.I0(OPCODE_HI_5[3]),
.I1(OPCODE_HI_5[0]),
.I2(OPCODE_HI_5[2]),
.I3(PS[1]),
.I4(PS[0]),
.O(RF_WR_INST_0_i_2_n_0));
LUT5 #(
.INIT(32'h40000000))
\RF_WR_SEL[0]_INST_0
(.I0(OPCODE_HI_5[1]),
.I1(OPCODE_HI_5[4]),
.I2(\RF_WR_SEL[0]_INST_0_i_1_n_0 ),
.I3(OPCODE_HI_5[0]),
.I4(OPCODE_HI_5[3]),
.O(RF_WR_SEL));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\RF_WR_SEL[0]_INST_0_i_1
(.I0(PS[0]),
.I1(PS[1]),
.I2(OPCODE_HI_5[2]),
.O(\RF_WR_SEL[0]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h1))
SP_RESET_INST_0
(.I0(PS[0]),
.I1(PS[1]),
.O(PC_RESET));
LUT5 #(
.INIT(32'h80828080))
Z_FLAG_LD_INST_0
(.I0(RF_WR_INST_0_i_1_n_0),
.I1(OPCODE_HI_5[1]),
.I2(OPCODE_HI_5[4]),
.I3(OPCODE_LO_2[0]),
.I4(OPCODE_LO_2[1]),
.O(ALU_SEL[0]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/* pbkdfengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`define ICARUS // Comment this out when using the altera virtual_wire interface in ltcminer.v
`timescale 1ns/1ps
module pbkdfengine
(hash_clk, pbkdf_clk, data1, data2, data3, target, nonce_msb, nonce_out, golden_nonce_out, golden_nonce_match, loadnonce,
salsa_din, salsa_dout, salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift, hash_out);
input hash_clk; // Just drives shift register
input pbkdf_clk;
input [255:0] data1;
input [255:0] data2;
input [127:0] data3;
input [31:0] target;
input [3:0] nonce_msb;
output reg [31:0] nonce_out;
output reg [31:0] hash_out; // Hash value for nonce_out (ztex port)
output [31:0] golden_nonce_out;
output golden_nonce_match; // Strobe valid one cycle on a match (needed for serial comms)
input loadnonce; // Strobe loads nonce (used for serial interface)
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] salsa_dout;
output [SBITS-1:0] salsa_din;
input salsa_busy, salsa_result; // NB hash_clk domain
output salsa_reset;
output salsa_start;
output reg salsa_shift = 1'b0; // NB hash_clk domain
reg [4:0]resetcycles = 4'd0;
reg reset = 1'b0;
assign salsa_reset = reset; // Propagate reset to salsaengine
`ifdef WANTCYCLICRESET
reg [23:0]cycresetcount = 24'd0;
`endif
always @ (posedge pbkdf_clk)
begin
// Hard code a 31 cycle reset (NB assumes THREADS=16 in salsaengine, else we need more)
// NB hash_clk is faster than pbkdf_clk so the salsaengine will actually be initialised well before
// this period ends, but keep to 15 for now as simulation uses equal pbkdf and salsa clock speeds.
resetcycles <= resetcycles + 1'd1;
if (resetcycles == 0)
reset <= 1'b1;
if (resetcycles == 31)
begin
reset <= 1'b0;
resetcycles <= 31;
end
`ifdef WANTCYCLICRESET
// Cyclical reset every 2_500_000 clocks to ensure salsa pipeline does not drift out of sync
// This may be unneccessary if we reset every loadnonce
// Actually it seems to do more harm than good, so disabled
cycresetcount <= cycresetcount + 1'd1;
if (cycresetcount == 2_500_000) // 10 per second at 25MHz (adjust as neccessary)
begin
cycresetcount <= 24'd0;
resetcycles <= 5'd0;
end
`endif
// Reset on loadnonce (the hash results will be junk anyway since data changes, so no loss of shares)
if (loadnonce)
resetcycles <= 5'd0;
end
`ifndef ICARUS
reg [31:0] nonce_previous_load = 32'hffffffff; // See note in salsa mix FSM
`endif
`ifndef NOMULTICORE
`ifdef SIM
reg [27:0] nonce_cnt = 28'h318f; // Start point for simulation (NB also define SIM in serial.v)
`else
reg [27:0] nonce_cnt = 28'd0; // Multiple cores use different prefix
`endif
wire [31:0] nonce;
assign nonce = { nonce_msb, nonce_cnt };
`else
reg [31:0] nonce = 32'd0; // NB Initially loaded from data3[127:96], see salsa mix FSM
`endif
reg [31:0] nonce_sr = 32'd0; // Nonce is shifted to salsaengine for storage/retrieval (hash_clk domain)
reg [31:0] golden_nonce = 32'd0;
assign golden_nonce_out = golden_nonce;
reg golden_nonce_match = 1'b0;
reg [2:0] nonce_wait = 3'd0;
reg [255:0] rx_state;
reg [511:0] rx_input;
wire [255:0] tx_hash;
reg [255:0] khash = 256'd0; // Key hash (NB scrypt.c calls this ihash)
reg [255:0] ihash = 256'd0; // IPAD hash
reg [255:0] ohash = 256'd0; // OPAD hash
`ifdef SIM
reg [255:0] final_hash = 256'd0; // Just for DEBUG, only need top 32 bits in live code.
`endif
reg [2:0] blockcnt = 3'd0; // Takes values 1..5 for block iteration
reg [1023:0] Xbuf = 1024'd0; // Shared input/output buffer and shift register (hash_clk domain)
reg [5:0] cnt = 6'd0;
wire feedback;
assign feedback = (cnt != 6'b0);
assign salsa_din = Xbuf[1023:1024-SBITS];
wire [1023:0] MixOutRewire; // Need to do endian conversion (see the generate below)
// MixOut is little-endian word format to match scrypt.c so convert back to big-endian
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] mix;
assign mix = Xbuf[`IDX(i)]; // NB MixOut now shares Xbuf since shifted in/out
assign MixOutRewire[`IDX(i)] = { mix[7:0], mix[15:8], mix[23:16], mix[31:24] };
end
endgenerate
// Interface control. This should be OK provided the threads remain evenly spaced (hence we reset on loadnonce)
reg SMixInRdy_state = 1'b0; // SMix input ready flag (set in SHA256, reset in SMIX)
reg SMixOutRdy_state = 1'b0; // SMix output ready flag (set in SMIX, reset in SHA256)
wire SMixInRdy;
wire SMixOutRdy;
reg Set_SMixInRdy = 1'b0;
reg Clr_SMixOutRdy = 1'b0;
wire Clr_SMixInRdy;
wire Set_SMixOutRdy;
reg [4:0]salsa_busy_d = 0; // Sync to pbkdf_clk domain
reg [4:0]salsa_result_d = 0;
always @ (posedge hash_clk)
begin
// Sync to pbkdf_clk domain
salsa_busy_d[0] <= salsa_busy;
if (salsa_busy & ~ salsa_busy_d[0])
salsa_busy_d[1] <= ~ salsa_busy_d[1]; // Toggle on busy going high
salsa_result_d[0] <= salsa_result;
if (salsa_result & ~ salsa_result_d[0])
salsa_result_d[1] <= ~ salsa_result_d[1]; // Toggle on result going high
end
always @ (posedge pbkdf_clk)
begin
salsa_busy_d[4:2] <= salsa_busy_d[3:1];
salsa_result_d[4:2] <= salsa_result_d[3:1];
if (Set_SMixInRdy)
SMixInRdy_state <= 1'b1;
if (Clr_SMixInRdy)
SMixInRdy_state <= 1'b0; // Clr overrides set
if (Set_SMixOutRdy)
SMixOutRdy_state <= 1'b1;
if (Clr_SMixOutRdy)
SMixOutRdy_state <= 1'b0; // Clr overrides set
// CARE there is a race with Set_SMixInRdy, Clr_SMixOutRdy which are set in the FSM
// Need to assert reset for several cycles to ensure consistency (acutally use 15 since salsaengine needs more)
if (reset)
begin // Reset takes priority
SMixInRdy_state <= 1'b0;
SMixOutRdy_state <= 1'b0;
end
end
assign Clr_SMixInRdy = SMixInRdy_state & (salsa_busy_d[3] ^ salsa_busy_d[4]); // Clear on transition to busy
assign Set_SMixOutRdy = ~SMixOutRdy_state & (salsa_result_d[3] ^ salsa_result_d[4]); // Set on transition to result
// Achieves identical timing to original version, but probably overkill
assign SMixInRdy = Clr_SMixInRdy ? 1'b0 : Set_SMixInRdy ? 1'b1 : SMixInRdy_state;
assign SMixOutRdy = Clr_SMixOutRdy ? 1'b0 : Set_SMixOutRdy ? 1'b1 : SMixOutRdy_state;
assign salsa_start = SMixInRdy;
// Clock crossing flags for shift register control (span pbkdf_clk, hash_clk domains)
reg [3:0]Xbuf_load_request = 1'b0;
reg [3:0]shift_request = 1'b0;
reg [3:0]shift_acknowledge = 1'b0;
// Controller FSM for PBKDF2_SHA256_80_128 (multiple hashes using the sha256_transform)
// Based on scrypt.c from cgminer (Colin Percival, ArtForz)
parameter S_IDLE=0,
S_H1= 1, S_H2= 2, S_H3= 3, S_H4= 4, S_H5= 5, S_H6= 6, // Initial hash of block header (khash)
S_I1= 7, S_I2= 8, S_I3= 9, S_I4=10, S_I5=11, S_I6=12, // IPAD hash (ihash)
S_O1=13, S_O2=14, S_O3=15, // OPAD hash (ohash)
S_B1=16, S_B2=17, S_B3=18, S_B4=19, S_B5=20, S_B6=21, // Iterate blocks
S_NONCE=22, S_SHIFT_IN=41, S_SHIFT_OUT=42, // Direction relative to salsa unit
// Final PBKDF2_SHA256_80_128_32 (reuses S_H1 to S_H6 for khash, alternatively could piplenine value)
S_R1=23, S_R2=24, S_R3=25, S_R4=26, S_R5=27, S_R6=28, // Final PBKDF2_SHA256_80_128_32
S_R7=29, S_R8=30, S_R9=31, S_R10=32, S_R11=33, S_R12=34,
S_R13=35, S_R14=36, S_R15=37, S_R16=38, S_R17=39, S_R18=40;
reg [5:0] state = S_IDLE;
reg mode = 0; // 0=PBKDF2_SHA256_80_128, 1=PBKDF2_SHA256_80_128_32
reg start_output = 0;
always @ (posedge pbkdf_clk)
begin
Set_SMixInRdy <= 1'b0; // Ugly hack, these are overriden below
Clr_SMixOutRdy <= 1'b0;
golden_nonce_match <= 1'b0; // Default to reset
shift_acknowledge[3:1] <= shift_acknowledge[2:0]; // Clock crossing
`ifdef ICARUS
if (loadnonce) // Separate clock domains means comparison is unsafe
`else
if (loadnonce || (nonce_previous_load != data3[127:96]))
`endif
begin
`ifdef NOMULTICORE
nonce <= data3[127:96]; // Supports loading of initial nonce for test purposes (potentially
// overriden by the increment below, but this occurs very rarely)
// This also gives a consistent start point when we send the first work
// packet (but ONLY the first one since its always zero) when using live data
// as we initialise nonce_previous_load to ffffffff
`else
nonce_cnt <= data3[123:96]; // The 4 msb of nonce are hardwired in MULTICORE mode, so test nonce
// needs to be <= 0fffffff and will only match in the 0 core
`endif
`ifndef ICARUS
nonce_previous_load <= data3[127:96];
`endif
end
if (reset == 1'b1)
begin
state <= S_IDLE;
start_output <= 1'b0;
end
else
begin
case (state)
S_IDLE: begin
if (SMixOutRdy & ~start_output)
begin
shift_request[0] <= ~shift_request[0]; // Request shifter to start
state <= S_SHIFT_OUT;
end
else
begin
if (start_output || // Process output
!SMixInRdy) // Process input unless already done
begin
start_output <= 1'b0;
mode <= 1'b0;
// Both cases use same initial calculaton of khash (its not worth trying to reuse previous khash
// for the second case as we're not constrained by SHA256 timing)
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { data2, data1 }; // Block header is passwd (used as key)
blockcnt <= 3'd1;
cnt <= 6'd0;
if (SMixOutRdy) // Give preference to output
mode <= 1'b1;
state <= S_H1;
end
end
end
// Hash the block header (result is khash)
S_H1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H2;
end
end
S_H2: begin // Sync hash
state <= S_H3;
end
S_H3: begin // Sync hash
rx_state <= tx_hash;
// Hash last 16 bytes of header including nonce and padded to 64 bytes with 1, zeros and length
// NB this sequence is used for both input and final PBKDF2_SHA256, hence switch nonce on mode
rx_input <= { 384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000,
mode ? nonce_sr : nonce, data3[95:0] };
state <= S_H4;
end
S_H4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_H5;
end
end
S_H5: begin // Sync hash
state <= S_H6;
end
S_H6: begin // Sync hash
khash <= tx_hash; // Save for OPAD hash
// Setup for IPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h3636363636363636363636363636363636363636363636363636363636363636 ,
tx_hash ^ 256'h3636363636363636363636363636363636363636363636363636363636363636 };
cnt <= 6'd0;
if (mode)
state <= S_R1;
else
state <= S_I1;
end
// IPAD hash
S_I1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I2;
end
end
S_I2: begin // Sync hash
state <= S_I3;
end
S_I3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { data2, data1 }; // Passwd (used as message)
state <= S_I4;
end
S_I4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_I5;
end
end
S_I5: begin // Sync hash
state <= S_I6;
end
S_I6: begin // Sync hash
ihash <= tx_hash; // Save result
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_O1;
end
// OPAD hash
S_O1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_O2;
end
end
S_O2: begin // Sync hash
state <= S_O3;
end
S_O3: begin // Sync hash
ohash <= tx_hash; // Save result
// Setup for block iteration
rx_state <= ihash;
// TODO hardwire top 29 bits of blockcnt as zero
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
// Block iteration (4 cycles)
S_B1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B2;
end
end
S_B2: begin // Sync hash
state <= S_B3;
end
S_B3: begin // Sync hash
rx_state <= ohash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, tx_hash };
state <= S_B4;
end
S_B4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_B5;
end
end
S_B5: begin // Sync hash
state <= S_B6;
end
S_B6: begin
khash <= tx_hash; // Save temporarily (for Xbuf)
Xbuf_load_request[0] <= ~Xbuf_load_request[0]; // NB also loads nonce_sr
if (blockcnt == 3'd5)
begin
nonce_wait <= 3'd7;
state <= S_NONCE;
end
else begin
// Setup for next block
rx_state <= ihash;
rx_input <= { 352'h000004a000000000000000000000000000000000000000000000000000000000000000000000000080000000,
29'd0, blockcnt, nonce, data3[95:0] }; // blockcnt is 3 bits, top 29 are hardcoded 0
blockcnt <= blockcnt + 1'd1; // Increment for next time
cnt <= 6'd0;
state <= S_B1;
end
end
S_NONCE: begin
// Need to delay a few clocks for Xbuf_load_request to complete
nonce_wait <= nonce_wait - 1'd1;
if (nonce_wait == 0)
begin
`ifndef NOMULTICORE
nonce_cnt <= nonce_cnt + 1'd1;
`else
nonce <= nonce + 1'd1;
`endif
shift_request[0] <= ~shift_request[0];
state <= S_SHIFT_IN;
end
end
S_SHIFT_IN: begin // Shifting from PBKDF2_SHA256 to salsa
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
Set_SMixInRdy <= 1'd1; // Flag salsa to start
state <= S_IDLE;
end
end
S_SHIFT_OUT: begin // Shifting from salsa to PBKDF2_SHA256
if (shift_acknowledge[3] != shift_acknowledge[2])
begin
start_output <= 1'd1; // Flag self to start
state <= S_IDLE;
end
end
// Final PBKDF2_SHA256_80_128_32 NB Entered from S_H6 via mode flag
// Similar to S_I0 but using MixOut as salt and finalblk padding
S_R1: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R2;
end
end
S_R2: begin // Sync hash
state <= S_R3;
end
S_R3: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[511:0]; // Salt (first block)
state <= S_R4;
end
S_R4: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R5;
end
end
S_R5: begin // Sync hash
state <= S_R6;
end
S_R6: begin // Sync hash
rx_state <= tx_hash;
rx_input <= MixOutRewire[1023:512]; // Salt (second block)
state <= S_R7;
end
S_R7: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R8;
end
end
S_R8: begin // Sync hash
state <= S_R9;
end
S_R9: begin // Sync hash
rx_state <= tx_hash;
// Final padding
rx_input <= 512'h00000620000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000000000000001;
state <= S_R10;
end
S_R10: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R11;
end
end
S_R11: begin // Sync hash
state <= S_R12;
end
S_R12: begin // Sync hash
ihash <= tx_hash; // Save (reuse ihash)
// Setup for OPAD hash
rx_state <= 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
rx_input <= { 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c ,
khash ^ 256'h5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c5c };
cnt <= 6'd0;
state <= S_R13;
end
S_R13: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R14;
end
end
S_R14: begin // Sync hash
state <= S_R15;
end
S_R15: begin // Sync hash
rx_state <= tx_hash;
rx_input <= { 256'h0000030000000000000000000000000000000000000000000000000080000000, ihash };
state <= S_R16;
end
S_R16: begin // Waiting for result
cnt <= cnt + 6'd1;
if (cnt == 6'd63)
begin
cnt <= 6'd0;
state <= S_R17;
end
end
S_R17: begin // Sync hash
state <= S_R18;
end
S_R18: begin // Sync hash
// Check for golden nonce in tx_hash
`ifdef SIM
final_hash <= tx_hash; // For debug
`endif
nonce_out <= nonce_sr; // Ztex port
hash_out <= tx_hash[255:224];
// Could optimise target calc ...
if ( { tx_hash[231:224], tx_hash[239:232], tx_hash[247:240], tx_hash[255:248] } < target)
begin
golden_nonce <= nonce_sr;
golden_nonce_match <= 1'b1; // Set flag (for one cycle only, see default at top)
end
state <= S_IDLE;
mode <= 1'b0;
// SMixOutRdy <= 1'b0; // Original version
Clr_SMixOutRdy <= 1'b1; // Ugly hack
end
endcase
end
end
// Shift register control - NB hash_clk domain
reg [10:0]shift_count = 11'd0; // hash_clk domain
always @ (posedge hash_clk)
begin
if (reset)
begin
salsa_shift <= 1'b0;
shift_count <= 11'd0;
end
// Clock crossing logic
Xbuf_load_request[3:1] <= Xbuf_load_request[2:0];
if (Xbuf_load_request[3] != Xbuf_load_request[2])
begin
// Shift output into X buffer from MSB->LSB
Xbuf[255:0] <= Xbuf[511:256];
Xbuf[511:256] <= Xbuf[767:512];
Xbuf[767:512] <= Xbuf[1023:768];
Xbuf[1023:768] <= khash;
nonce_sr <= nonce; // Loaded several times, but of no consequence
end
shift_request[3:1] <= shift_request[2:0];
if (shift_request[3] != shift_request[2])
begin
salsa_shift <= 1'b1;
end
if (salsa_shift)
begin
shift_count <= shift_count + 1'b1;
Xbuf <= { Xbuf[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], salsa_dout };
end
if (shift_count == (1024+32)/SBITS-1)
begin
shift_acknowledge[0] = ~shift_acknowledge[0];
shift_count <= 0;
salsa_shift <= 0;
end
end
// Using LOOP=64 to simplify timing (needs slightly modified version of original sha256_transform.v)
// since pipelining is inappropriate for ltc (we need to rehash same data several times in succession)
sha256_transform # (.LOOP(64)) sha256_blk (
.clk(pbkdf_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(rx_state),
.rx_input(rx_input),
.tx_hash(tx_hash)
);
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/18 15:20:50
// Design Name: CONTROL_UNIT
// Module Name: CONTROL_UNIT
// Project Name: MISP_CPU
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CONTROL_UNIT(
input[5:0] op,func,
input z,
output wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem,
output[3:0] aluc,
output[1:0] pcsource
);
parameter cmd_add = 6'b100000;
parameter cmd_sub = 6'b100010;
parameter cmd_and = 6'b100100;
parameter cmd_or = 6'b100101;
parameter cmd_xor = 6'b100110;
parameter cmd_sll = 6'b000000;
parameter cmd_srl = 6'b000010;
parameter cmd_sra = 6'b000011;
parameter cmd_jr = 6'b001000;
parameter cmd_addi = 6'b001000;
parameter cmd_andi = 6'b001100;
parameter cmd_ori = 6'b001101;
parameter cmd_xori = 6'b001110;
parameter cmd_lw = 6'b100011;
parameter cmd_sw = 6'b101011;
parameter cmd_beq = 6'b000100;
parameter cmd_bne = 6'b000101;
parameter cmd_lui = 6'b001111;
parameter cmd_j = 6'b000010;
parameter cmd_jal = 6'b000011;
reg[13:0] cmd_out;
always @(*) begin
case (op)
6'b0 : begin
case (func)
cmd_add : cmd_out <= 14'b10000000000000;
cmd_sub : cmd_out <= 14'b10000000100000;
cmd_and : cmd_out <= 14'b10000000001000;
cmd_or : cmd_out <= 14'b10000000101000;
cmd_xor : cmd_out <= 14'b10000000010000;
cmd_sll : cmd_out <= 14'b10001000011000;
cmd_srl : cmd_out <= 14'b10001000111000;
cmd_sra : cmd_out <= 14'b10001001111000;
cmd_jr : cmd_out <= 14'b00000000000010;
default : cmd_out <= 14'b00000000000000;
endcase
end
cmd_addi : cmd_out <= 14'b11000110000000;
cmd_andi : cmd_out <= 14'b11000100001000;
cmd_ori : cmd_out <= 14'b11000100101000;
cmd_xori : cmd_out <= 14'b11000100010000;
cmd_lw : cmd_out <= 14'b11010110000000;
cmd_sw : cmd_out <= 14'b00000110000100;
cmd_beq : cmd_out <= {13'b0000001001000,z};
cmd_bne : cmd_out <= {13'b0000001001000,~z};
cmd_lui : cmd_out <= 14'b11000100110000;
cmd_j : cmd_out <= 14'b00000000000011;
cmd_jal : cmd_out <= 14'b10100000000011;
default : cmd_out <= 14'b00000000000000;
endcase
end
assign wreg = cmd_out[13];
assign regrt = cmd_out[12];
assign jal = cmd_out[11];
assign m2reg = cmd_out[10];
assign shfit = cmd_out[9];
assign aluimm = cmd_out[8];
assign sext = cmd_out[7];
assign aluc = cmd_out[6:3];
assign wmem = cmd_out[2];
assign pcsource = cmd_out[1:0];
endmodule |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file rom_8x2k_lo.v when simulating
// the core, rom_8x2k_lo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module rom_8x2k_lo(
addr,
clk,
din,
dout,
en,
we);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom_8x2k_lo is "black_box"
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
fastclk, clk
);
`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
`define posstyle posedge
`define negstyle negedge
`else
`define posstyle
`define negstyle
`endif
input fastclk;
input clk;
reg [7:0] data;
reg [7:0] data_a;
reg [7:0] data_a_a;
reg [7:0] data_a_b;
reg [7:0] data_b;
reg [7:0] data_b_a;
reg [7:0] data_b_b;
reg [8*6-1:0] check [100:0];
wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
initial begin
check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
end
// verilator lint_off COMBDLY
// verilator lint_off LATCH
always @ (`posstyle clk /*AS*/ or data) begin
if (clk) begin
data_a <= data + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_a) begin
if (clk) begin
data_a_a <= data_a + 8'd1;
end
end
always @ (`posstyle clk /*AS*/ or data_b) begin
if (clk) begin
data_b_a <= data_b + 8'd1;
end
end
always @ (`negstyle clk /*AS*/ or data or data_a) begin
if (~clk) begin
data_b <= data + 8'd1;
data_a_b <= data_a + 8'd1;
data_b_b <= data_b + 8'd1;
end
end
integer cyc; initial cyc = 0;
always @ (posedge fastclk) begin
cyc <= cyc+1;
`ifdef TEST_VERBOSE
$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
`endif
if (cyc>=19 && cyc<36) begin
if (compare !== check[cyc]) begin
$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
$stop;
end
end
if (cyc == 10) begin
data <= 8'd12;
end
if (cyc == 20) begin
data <= 8'd20;
end
if (cyc == 30) begin
data <= 8'd30;
end
if (cyc == 40) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Altera_UP_Video_In_Dual_Clock_FIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_up_video_dual_clock_fifo (
// Inputs
wrclk,
wrreq,
data,
rdclk,
rdreq,
// Outputs
wrusedw,
wrfull,
q,
rdusedw,
rdempty
);
parameter DW = 18;
input wrclk;
input wrreq;
input [(DW-1):0] data;
input rdclk;
input rdreq;
output [6:0] wrusedw;
output wrfull;
output [(DW-1):0] q;
output [6:0] rdusedw;
output rdempty;
dcfifo dcfifo_component (
// Inputs
.wrclk (wrclk),
.wrreq (wrreq),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (q),
.rdusedw (rdusedw),
.rdempty (rdempty)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = DW,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL data[25..0]
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL q[25..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
input clk;
m3 m3_inst (.clk(clk));
defparam m3_inst.FROMDEFP = 19;
defparam m3_inst.P2 = 2;
//defparam m3_inst.P3 = PAR;
defparam m3_inst.P3 = 3;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m3
(/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam LOC = 13;
parameter UNCH = 99;
parameter P1 = 10;
parameter P2 = 20;
parameter P3 = 30;
parameter FROMDEFP = 11;
initial begin
$display("%x %x %x",P1,P2,P3);
end
always @ (posedge clk) begin
if (UNCH !== 99) $stop;
if (P1 !== 10) $stop;
if (P2 !== 2) $stop;
if (P3 !== 3) $stop;
if (FROMDEFP !== 19) $stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_PP_BLACKBOX_V
|
`timescale 1s/1s
module test(outp, outm, outl, in);
output outp, outm, outl;
input in;
// Check a primitive.
assign #1 outp = ~in;
// Check a multiplexer.
assign #1 outm = in ? in : 1'b0;
// Check a LPM.
assign #1 outl = in === 1'b1;
endmodule
// This is not exactly the same as the original code, but it is effectively
// the same and should test the same things that were failing.
`timescale 1ns/100ps
module top;
reg in, passed;
wire outp, outm, outl;
test dut(outp, outm, outl, in);
initial begin
passed = 1'b1;
#1100000000;
if (outp !== 1'bx) begin
$display("Failed initial prim. check, expected 1'bx, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'bx) begin
$display("Failed initial mux. check, expected 1'bx, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b0) begin
$display("Failed initial LPM check, expected 1'b0, got %b.", outl);
passed = 1'b0;
end
in = 0;
#1100000000;
if (outp !== 1'b1) begin
$display("Failed in=0 prim. check, expected 1'b1, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'b0) begin
$display("Failed in=0 mux. check, expected 1'b0, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b0) begin
$display("Failed in=0 LPM check, expected 1'b0, got %b.", outl);
passed = 1'b0;
end
in = 1;
#1100000000;
if (outp !== 1'b0) begin
$display("Failed in=1 prim. check, expected 1'b0, got %b.", outp);
passed = 1'b0;
end
if (outm !== 1'b1) begin
$display("Failed in=1 mux. check, expected 1'b1, got %b.", outm);
passed = 1'b0;
end
if (outl !== 1'b1) begin
$display("Failed in=1 LPM check, expected 1'b1, got %b.", outl);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 5.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [31:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [31:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 32'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0, 8'd0};
shift_amount_c1 <= 9'd158 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0, 7'd0};
shift_amount_c1 <= 9'd157 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [34:0] extended_mantissa_c2;
reg [4:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 35'dx;
shift_amount_c2 <= 5'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[4:0]) & {5{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {32'hffffffff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {32'h7fffffff + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 32'h7fffffff + sign_c1 : 32'hffffffff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:6])
begin
// Shift by more than 64+
sign_c2 <= sign_c1 & (|man_c1[31:8]);
extended_mantissa_c2 <= {34'd0, |man_c1[31:8]};
end
else if (|shift_amount_c1[5])
begin
// Shift by 32+
extended_mantissa_c2 <= {32'd0, man_c1[31:30], |man_c1[29:8]};
end
else
extended_mantissa_c2 <= {man_c1, 3'd0};
end
end
// STAGE 3
reg [34:0] extended_mantissa_c3;
reg [2:0] shift_amount_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
shift_amount_c3 <= 3'dx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
shift_amount_c3 <= shift_amount_c2[2:0];
case (shift_amount_c2[4:3])
2'b11: extended_mantissa_c3 <= {24'd0, extended_mantissa_c2[34:25], |extended_mantissa_c2[24:0]};
2'b10: extended_mantissa_c3 <= {16'd0, extended_mantissa_c2[34:17], |extended_mantissa_c2[16:0]};
2'b01: extended_mantissa_c3 <= {8'd0, extended_mantissa_c2[34:9], |extended_mantissa_c2[8:0]};
2'b00: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [34:0] extended_mantissa_c4;
reg sign_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c4 <= 35'dx;
sign_c4 <= 1'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
sign_c4 <= sign_c3;
case (shift_amount_c3)
3'b111: extended_mantissa_c4 <= {7'd0, extended_mantissa_c3[34:8], |extended_mantissa_c3[7:0]};
3'b110: extended_mantissa_c4 <= {6'd0, extended_mantissa_c3[34:7], |extended_mantissa_c3[6:0]};
3'b101: extended_mantissa_c4 <= {5'd0, extended_mantissa_c3[34:6], |extended_mantissa_c3[5:0]};
3'b100: extended_mantissa_c4 <= {4'd0, extended_mantissa_c3[34:5], |extended_mantissa_c3[4:0]};
3'b011: extended_mantissa_c4 <= {3'd0, extended_mantissa_c3[34:4], |extended_mantissa_c3[3:0]};
3'b010: extended_mantissa_c4 <= {2'd0, extended_mantissa_c3[34:3], |extended_mantissa_c3[2:0]};
3'b001: extended_mantissa_c4 <= {1'd0, extended_mantissa_c3[34:2], |extended_mantissa_c3[1:0]};
3'b000: extended_mantissa_c4 <= extended_mantissa_c3;
endcase
end
end
// STAGE 5
reg [32:0] result_c5;
reg valid_c5;
wire stall_c5;
wire enable_c5 = (HIGH_CAPACITY == 1) ? (~valid_c5 | ~stall_c5) : enable;
assign stall_c4 = valid_c5 & stall_c5;
assign stall_c5 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c5 <= 33'dx;
valid_c5 <= 1'b0;
end
else if (enable_c5)
begin
valid_c5 <= valid_c4;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c5 <= ({33{sign_c4}} ^ ({1'b0, extended_mantissa_c4[34:3]})) + {1'b0, sign_c4};
end
else
begin
result_c5 <= (sign_c4) ? 33'd0 : {1'b0, extended_mantissa_c4[34:3]};
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c4[2:0])
begin
if (UNSIGNED == 0)
begin
result_c5 <= (sign_c4) ? (({33{sign_c4}} ^ (extended_mantissa_c4[34:3] + 1'b1)) + 1'b1) : extended_mantissa_c4[34:3];
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c4[2:0])
begin
if (UNSIGNED == 0)
begin
result_c5 <= (sign_c4) ? (({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + 1'b1) : (extended_mantissa_c4[34:3] + 1'b1);
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c4[2])
begin
if (UNSIGNED == 0)
begin
result_c5 <= ({33{sign_c4}} ^ (extended_mantissa_c4[34:3] + 1'b1)) + sign_c4;
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
default:
begin // 0 and default are round to nearest even
if (UNSIGNED == 0)
begin
if ((extended_mantissa_c4[3:0] == 4'hc) | (extended_mantissa_c4[2] & (|extended_mantissa_c4[1:0])))
result_c5 <= ({33{sign_c4}} ^ {1'b0, extended_mantissa_c4[34:3]}) + {1'b0,~sign_c4};
else
result_c5 <= ({33{sign_c4}} ^ {1'b0, extended_mantissa_c4[34:3]}) + sign_c4;
end
else
begin
if ((extended_mantissa_c4[3:0] == 4'hc) | (extended_mantissa_c4[2] & (|extended_mantissa_c4[1:0])))
result_c5 <= (sign_c4) ? 33'd0 : {1'b0, extended_mantissa_c4[34:3]} + 1'b1;
else
result_c5 <= {33{~sign_c4}} & {1'b0, extended_mantissa_c4[34:3]};
end
end
endcase
end
end
assign result = (UNSIGNED == 1) ? ({32{result_c5[32]}} | result_c5[31:0]) : ((result_c5[32] ^ result_c5[31]) ? {result_c5[32], {31{~result_c5[32]}}} : result_c5[31:0]);
assign valid_out = valid_c5;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: rd_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module has all the timing control for generating "compare data"
// to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_rd_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6"
parameter MEM_TYPE = "DDR3",
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
input mode_load_i,
input [3:0] vio_instr_mode_value,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
output reg cmd_start_o,
// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
output user_bl_cnt_is_1_o,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
// connect from mcb_rd_empty when used as rd_data_gen in sp6
// connect from rd_data_valid in v6
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
output [31:0] tg_st_addr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
);
//
wire [31:0] prbs_data;
reg cmd_start;
reg [31:0] adata;
reg [31:0] hdata;
reg [31:0] ndata;
reg [31:0] w1data;
reg [NUM_DQ_PINS*4-1:0] v6_w1data;
reg [31:0] w0data;
reg [DWIDTH-1:0] data;
reg cmd_rdy;
reg [BL_WIDTH:0]user_burst_cnt;
reg [31:0] w3data;
reg prefetch;
assign data_port_fifo_rdy = data_rdy_i;
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if (data_port_fifo_rdy)
if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6")
|| (user_burst_cnt == 2 && FAMILY == "VIRTEX6")
)
user_bl_cnt_is_1 <= #TCQ 1'b1;
else
user_bl_cnt_is_1 <= #TCQ 1'b0;
end
//reg cmd_start_b;
always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch)
begin
cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i };
end
else if(data_port_fifo_rdy)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <= #TCQ 'd0;
end
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
//data_valid_o logic
always @( posedge clk_i)
begin
if ( rst_i[0] )
prefetch <= #TCQ 1'b1;
else if (data_port_fifo_rdy || cmd_start)
prefetch <= #TCQ 1'b0;
else if (user_burst_cnt == 0 && ~data_port_fifo_rdy)
prefetch <= #TCQ 1'b1;
end
assign cmd_rdy_o = cmd_rdy ;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch ))
cmd_rdy <= #TCQ 1'b0;
else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) ||
(data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 ))
cmd_rdy <= #TCQ 1'b1;
end
always @ (data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
data_valid_o = data_port_fifo_rdy;
else
data_valid_o = data_port_fifo_rdy;
/*
generate
if (FAMILY == "SPARTAN6")
begin : SP6_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
end
endgenerate*/
//generate
//if (FAMILY == "VIRTEX6")
//begin : V_DGEN
mig_7series_v1_9_s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.tg_st_addr_o (tg_st_addr_o),
.data_mask_o (),
.bram_rd_valid_o ()
);
//end
//endgenerate
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module main(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
input [15:0] din;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
wire[15:0] EPP_dataword = {EPP_datain, lowbyte};
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) vel0 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd3) vel1 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd5) vel2 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd7) vel3 <= EPP_dataword[F:0];
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[5:0], lowbyte };
end
else if(addr_reg[3:0] == 4'd11) begin
tap <= lowbyte[7:6];
steptime <= lowbyte[T-1:0];
Spolarity <= EPP_datain[7];
// EPP_datain[6] is do_enable_wdt
dirtime <= EPP_datain[T-1:0];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= pos0;
else if(addr_reg[4:2] == 3'd1) data_buf <= pos1;
else if(addr_reg[4:2] == 3'd2) data_buf <= pos2;
else if(addr_reg[4:2] == 3'd3) data_buf <= pos3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= din;
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
// assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
// assign led = do_tristate ? 1'BZ : (real_step[0] ^ real_dir[0]);
assign led = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign nConfig = epp_nReset; // 1'b1;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision
///////////////////////////////////////////////////////////////////////////////
module IDDR #(
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE",
parameter INIT_Q1 = 1'b0,
parameter INIT_Q2 = 1'b0,
parameter SRTYPE = "SYNC"
) (
output Q1,
output Q2,
input C,
input CE,
input D,
input R,
input S
);
reg q1_out = INIT_Q1, q2_out = INIT_Q2;
reg q1_out_int, q2_out_int;
reg q1_out_pipelined, q2_out_same_edge_int;
wire c_in;
wire ce_in;
wire d_in;
wire gsr_in;
wire r_in;
wire s_in;
buf buf_c(c_in, C);
buf buf_ce(ce_in, CE);
buf buf_d(d_in, D);
buf buf_q1(Q1, q1_out);
buf buf_q2(Q2, q2_out);
buf buf_r(r_in, R);
buf buf_s(s_in, S);
initial begin
if((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2);
$finish;
end
if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end
always @(r_in, s_in) begin
if(r_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b0;
assign q1_out_pipelined = 1'b0;
assign q2_out_same_edge_int = 1'b0;
assign q2_out_int = 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin
assign q1_out_int = 1'b1;
assign q1_out_pipelined = 1'b1;
assign q2_out_same_edge_int = 1'b1;
assign q2_out_int = 1'b1;
end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end else if(r_in == 1'b0 && s_in == 1'b0) begin
deassign q1_out_int;
deassign q1_out_pipelined;
deassign q2_out_same_edge_int;
deassign q2_out_int;
end
end
always @(posedge c_in) begin
if(r_in == 1'b1) begin
q1_out_int <= 1'b0;
q1_out_pipelined <= 1'b0;
q2_out_same_edge_int <= 1'b0;
end else if(r_in == 1'b0 && s_in == 1'b1) begin
q1_out_int <= 1'b1;
q1_out_pipelined <= 1'b1;
q2_out_same_edge_int <= 1'b1;
end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin
q1_out_int <= d_in;
q1_out_pipelined <= q1_out_int;
q2_out_same_edge_int <= q2_out_int;
end
end
always @(negedge c_in) begin
if(r_in == 1'b1)
q2_out_int <= 1'b0;
else if(r_in == 1'b0 && s_in == 1'b1)
q2_out_int <= 1'b1;
else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0)
q2_out_int <= d_in;
end
always @(c_in, q1_out_int, q2_out_int, q2_out_same_edge_int, q1_out_pipelined) begin
case(DDR_CLK_EDGE)
"OPPOSITE_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_int;
end
"SAME_EDGE" : begin
q1_out <= q1_out_int;
q2_out <= q2_out_same_edge_int;
end
"SAME_EDGE_PIPELINED" : begin
q1_out <= q1_out_pipelined;
q2_out <= q2_out_same_edge_int;
end
default: begin
$display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE);
$finish;
end
endcase
end
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 19:57:00
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sinpi_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sinpi_s5 inst(
.en (enable),
.clk (clock),
.a (dataa),
.q (sub_wire0),
.areset(1'b0));
endmodule
|
`include "../src/fsctl.v"
module test_fsctl();
parameter integer C_SPEED_DATA_WIDTH = 16;
parameter integer C_REG_IDX_WIDTH = 8;
reg clk;
reg resetn;
reg wr_en;
reg[C_REG_IDX_WIDTH-1:0] wr_addr = 0;
reg[31:0] wr_data;
reg o_clk;
reg o_resetn;
wire br0_init;
wire br0_wr_en;
wire [C_SPEED_DATA_WIDTH-1:0] br0_data;
reg motor0_zpsign;
fsctl # (
.C_REG_IDX_WIDTH(C_REG_IDX_WIDTH),
.C_SPEED_DATA_WIDTH(C_SPEED_DATA_WIDTH)
) fsctl_inst (
.clk(clk),
.resetn(resetn),
.wr_en(wr_en),
.wr_addr(wr_addr),
.wr_data(wr_data),
.o_clk(o_clk),
.o_resetn(o_resetn),
.br0_init(br0_init),
.br0_wr_en(br0_wr_en),
.br0_data(br0_data),
.motor0_zpsign(motor0_zpsign)
);
initial begin
clk <= 1'b1;
forever #4 clk <= ~clk;
end
initial begin
o_clk <= 1'b1;
repeat (1) #1 o_clk <= 1'b1;
forever #1 o_clk <= ~o_clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
initial begin
o_resetn <= 1'b0;
repeat (5) #2 o_resetn <= 1'b0;
forever #2 o_resetn <= 1'b1;
end
reg[31:0] datacnt;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
wr_en <= 0;
wr_addr <= 0;
wr_data <= 0;
datacnt <= 0;
end
else if (br0_init == 0) begin
if (datacnt == 0) begin
wr_en <= 1;
wr_addr <= 30;
wr_data <= 3;
end
else begin
wr_en <= 1;
wr_addr <= 34;
wr_data <= 32'hFFFFFFFF;
end
end
else if (br0_init == 1) begin
if (datacnt < 15) begin
if ({$random}%2 == 1) begin
wr_en <= 1;
wr_addr <= 31;
wr_data <= datacnt;
datacnt <= datacnt + 1;
end
else begin
wr_en <= 0;
end
end
else begin
wr_en <= 1;
wr_addr <= 30;
wr_data <= 0;
end
end
end
initial begin
motor0_zpsign <= 1'b0;
repeat (5) #2 motor0_zpsign <= 1'b0;
repeat (1000) #2 motor0_zpsign <= 1'b1;
end
endmodule
|
module exec_tb;
//wires
reg clk;
reg rst;
reg salu_wr_exec_en, salu_wr_vcc_en, salu_rd_en, salu_wr_m0_en, salu_wr_scc_en,
salu_wr_scc_value, simd0_rd_en, simd1_rd_en, simd2_rd_en, simd3_rd_en,
simd0_vcc_wr_en, simd1_vcc_wr_en, simd2_vcc_wr_en, simd3_vcc_wr_en,
simf0_rd_en, simf1_rd_en, simf2_rd_en, simf3_rd_en, simf0_vcc_wr_en,
simf1_vcc_wr_en, simf2_vcc_wr_en, simf3_vcc_wr_en, fetch_init_wf_en;
reg [5:0] lsu_rd_wfid, salu_wr_wfid, salu_rd_wfid, simd0_rd_wfid, simd1_rd_wfid,
simd2_rd_wfid, simd3_rd_wfid, simd0_vcc_wr_wfid, simd1_vcc_wr_wfid,
simd2_vcc_wr_wfid, simd3_vcc_wr_wfid, simf0_rd_wfid, simf1_rd_wfid,
simf2_rd_wfid, simf3_rd_wfid, simf0_vcc_wr_wfid, simf1_vcc_wr_wfid,
simf2_vcc_wr_wfid, simf3_vcc_wr_wfid, fetch_init_wf_id;
reg [15:0] rfa_select_fu;
reg [31:0] salu_wr_m0_value;
reg [63:0] salu_wr_exec_value, salu_wr_vcc_value, simd0_vcc_value,
simd1_vcc_value, simd2_vcc_value, simd3_vcc_value, simf0_vcc_value,
simf1_vcc_value, simf2_vcc_value, simf3_vcc_value, fetch_init_value;
wire simd_rd_scc_value, simf_rd_scc_value, salu_rd_scc_value, issue_salu_wr_vcc_en,
issue_salu_wr_exec_en, issue_salu_wr_m0_en, issue_salu_wr_scc_en, issue_valu_wr_vcc_en;
wire [5:0] issue_salu_wr_vcc_wfid, issue_valu_wr_vcc_wfid;
wire [31:0] lsu_rd_m0_value, simd_rd_m0_value, simf_rd_m0_value, salu_rd_m0_value;
wire [63:0] lsu_exec_value, simd_rd_exec_value, simd_rd_vcc_value,
simf_rd_exec_value, simf_rd_vcc_value, salu_rd_exec_value, salu_rd_vcc_value;
//instantiation of dut
exec exec0(
.lsu_rd_wfid(lsu_rd_wfid),
.salu_wr_exec_en(salu_wr_exec_en),
.salu_wr_vcc_en(salu_wr_vcc_en),
.salu_wr_exec_value(salu_wr_exec_value),
.salu_wr_vcc_value(salu_wr_vcc_value),
.salu_wr_wfid(salu_wr_wfid),
.salu_rd_en(salu_rd_en),
.salu_rd_wfid(salu_rd_wfid),
.salu_wr_m0_en(salu_wr_m0_en),
.salu_wr_m0_value(salu_wr_m0_value),
.salu_wr_scc_en(salu_wr_scc_en),
.salu_wr_scc_value(salu_wr_scc_value),
.simd0_rd_wfid(simd0_rd_wfid),
.simd1_rd_wfid(simd1_rd_wfid),
.simd2_rd_wfid(simd2_rd_wfid),
.simd3_rd_wfid(simd3_rd_wfid),
.simd0_rd_en(simd0_rd_en),
.simd1_rd_en(simd1_rd_en),
.simd2_rd_en(simd2_rd_en),
.simd3_rd_en(simd3_rd_en),
.simd0_vcc_wr_wfid(simd0_vcc_wr_wfid),
.simd1_vcc_wr_wfid(simd1_vcc_wr_wfid),
.simd2_vcc_wr_wfid(simd2_vcc_wr_wfid),
.simd3_vcc_wr_wfid(simd3_vcc_wr_wfid),
.simd0_vcc_wr_en(simd0_vcc_wr_en),
.simd1_vcc_wr_en(simd1_vcc_wr_en),
.simd2_vcc_wr_en(simd2_vcc_wr_en),
.simd3_vcc_wr_en(simd3_vcc_wr_en),
.simd0_vcc_value(simd0_vcc_value),
.simd1_vcc_value(simd1_vcc_value),
.simd2_vcc_value(simd2_vcc_value),
.simd3_vcc_value(simd3_vcc_value),
.simf0_rd_wfid(simf0_rd_wfid),
.simf1_rd_wfid(simf1_rd_wfid),
.simf2_rd_wfid(simf2_rd_wfid),
.simf3_rd_wfid(simf3_rd_wfid),
.simf0_rd_en(simf0_rd_en),
.simf1_rd_en(simf1_rd_en),
.simf2_rd_en(simf2_rd_en),
.simf3_rd_en(simf3_rd_en),
.simf0_vcc_wr_wfid(simf0_vcc_wr_wfid),
.simf1_vcc_wr_wfid(simf1_vcc_wr_wfid),
.simf2_vcc_wr_wfid(simf2_vcc_wr_wfid),
.simf3_vcc_wr_wfid(simf3_vcc_wr_wfid),
.simf0_vcc_wr_en(simf0_vcc_wr_en),
.simf1_vcc_wr_en(simf1_vcc_wr_en),
.simf2_vcc_wr_en(simf2_vcc_wr_en),
.simf3_vcc_wr_en(simf3_vcc_wr_en),
.simf0_vcc_value(simf0_vcc_value),
.simf1_vcc_value(simf1_vcc_value),
.simf2_vcc_value(simf2_vcc_value),
.simf3_vcc_value(simf3_vcc_value),
.fetch_init_wf_en(fetch_init_wf_en),
.fetch_init_wf_id(fetch_init_wf_id),
.fetch_init_value(fetch_init_value),
.rfa_select_fu(rfa_select_fu),
.lsu_exec_value(lsu_exec_value),
.lsu_rd_m0_value(lsu_rd_m0_value),
.simd_rd_exec_value(simd_rd_exec_value),
.simd_rd_vcc_value(simd_rd_vcc_value),
.simd_rd_m0_value(simd_rd_m0_value),
.simd_rd_scc_value(simd_rd_scc_value),
.simf_rd_exec_value(simf_rd_exec_value),
.simf_rd_vcc_value(simf_rd_vcc_value),
.simf_rd_m0_value(simf_rd_m0_value),
.simf_rd_scc_value(simf_rd_scc_value),
.salu_rd_exec_value(salu_rd_exec_value),
.salu_rd_vcc_value(salu_rd_vcc_value),
.salu_rd_m0_value(salu_rd_m0_value),
.salu_rd_scc_value(salu_rd_scc_value),
.issue_salu_wr_vcc_wfid(issue_salu_wr_vcc_wfid),
.issue_salu_wr_vcc_en(issue_salu_wr_vcc_en),
.issue_salu_wr_exec_en(issue_salu_wr_exec_en),
.issue_salu_wr_m0_en(issue_salu_wr_m0_en),
.issue_salu_wr_scc_en(issue_salu_wr_scc_en),
.issue_valu_wr_vcc_wfid(issue_valu_wr_vcc_wfid),
.issue_valu_wr_vcc_en(issue_valu_wr_vcc_en),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
fetch_init_wf_en = 1'b0;
fetch_init_wf_id = 6'b000000;
fetch_init_value = {64{1'b0}};
rfa_select_fu = 16'b0;
lsu_rd_wfid = 6'b000000;
salu_rd_en = 1'b0;
salu_rd_wfid = 6'b000000;
salu_wr_exec_en = 1'b0;
salu_wr_vcc_en = 1'b0;
salu_wr_scc_en = 1'b0;
salu_wr_m0_en = 1'b0;
salu_wr_wfid = 6'b000000;
salu_wr_exec_value = {64{1'b0}};
salu_wr_vcc_value = {64{1'b0}};
salu_wr_scc_value = 1'b0;
salu_wr_m0_value = {32{1'b0}};
simd0_rd_en = 1'b0;
simd1_rd_en = 1'b0;
simd2_rd_en = 1'b0;
simd3_rd_en = 1'b0;
simd0_rd_wfid = 6'b000000;
simd1_rd_wfid = 6'b000000;
simd2_rd_wfid = 6'b000000;
simd3_rd_wfid = 6'b000000;
simf0_rd_en = 1'b0;
simf1_rd_en = 1'b0;
simf2_rd_en = 1'b0;
simf3_rd_en = 1'b0;
simf0_rd_wfid = 6'b000000;
simf1_rd_wfid = 6'b000000;
simf2_rd_wfid = 6'b000000;
simf3_rd_wfid = 6'b000000;
simd0_vcc_wr_en = 1'b0;
simd1_vcc_wr_en = 1'b0;
simd2_vcc_wr_en = 1'b0;
simd3_vcc_wr_en = 1'b0;
simd0_vcc_wr_wfid = 6'b000000;
simd1_vcc_wr_wfid = 6'b000000;
simd2_vcc_wr_wfid = 6'b000000;
simd3_vcc_wr_wfid = 6'b000000;
simd0_vcc_value = {64{1'b0}};
simd1_vcc_value = {64{1'b0}};
simd2_vcc_value = {64{1'b0}};
simd3_vcc_value = {64{1'b0}};
simf0_vcc_wr_en = 1'b0;
simf1_vcc_wr_en = 1'b0;
simf2_vcc_wr_en = 1'b0;
simf3_vcc_wr_en = 1'b0;
simf0_vcc_wr_wfid = 6'b000000;
simf1_vcc_wr_wfid = 6'b000000;
simf2_vcc_wr_wfid = 6'b000000;
simf3_vcc_wr_wfid = 6'b000000;
simf0_vcc_value = {64{1'b0}};
simf1_vcc_value = {64{1'b0}};
simf2_vcc_value = {64{1'b0}};
simf3_vcc_value = {64{1'b0}};
#10 rst = 1'b0;
#2000;
$finish;
end
initial begin
#31;
#10
$display("Initializing exec value \n");
fetch_init_wf_en = 1'b1;
fetch_init_wf_id = 6'b000010;
fetch_init_value = {{58{1'b0}},6'b101101};
#10
fetch_init_wf_en = 1'b0;
#10
$display("Read from SIMD0 and LSU \n");
simd0_rd_en = 1'b1;
simd0_rd_wfid = 6'b000010;
lsu_rd_wfid = 6'b000010;
#10
$display("Read from SIMF2 and LSU \n");
simd0_rd_en = 1'b0;
simf2_rd_en = 1'b1;
simf2_rd_wfid = 6'b000010;
#10
$display("Write exec = 0..1001, vcc = 0..11011, scc = 1, m0 = 0..1101 from SALU \n");
salu_wr_exec_en = 1'b1;
salu_wr_vcc_en = 1'b1;
salu_wr_scc_en = 1'b1;
salu_wr_m0_en = 1'b1;
salu_wr_wfid = 6'b000010;
salu_wr_exec_value = {{58{1'b0}}, 6'b001001};
salu_wr_vcc_value = {{58{1'b0}}, 6'b011011};
salu_wr_scc_value = 1'b1;
salu_wr_m0_value = {{24{1'b0}}, 6'b001101};
#10
salu_wr_vcc_en = 1'b0;
salu_wr_exec_en = 1'b0;
salu_wr_scc_en = 1'b0;
salu_wr_m0_en = 1'b0;
$display("Write vcc = 0...0101 from SIMD1 \n");
rfa_select_fu = 16'd2;
simd1_vcc_wr_en = 1'b1;
simd1_vcc_wr_wfid = 6'b000010;
simd1_vcc_value = {{58{1'b0}}, 6'b000101};
#10
simd1_vcc_wr_en = 1'b0;
$display("Read from SALU \n");
simf2_rd_en = 1'b0;
salu_rd_en = 1'b1;
salu_rd_wfid = 6'b000010;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor($time, "\n \
issue_salu_wr_exec_en = %b \n \
issue_salu_wr_m0_en = %b \n \
issue_salu_wr_scc_en = %b \n \
issue_salu_wr_vcc_en = %b \n \
issue_salu_wr_vcc_wfid = %b \n \
issue_valu_wr_vcc_en = %b \n \
issue_valu_wr_vcc_wfid = %b \n \n\
lsu_exec_value = %b \n \
lsu_rd_m0_value = %b \n \n\
salu_rd_exec_value = %b \n \
salu_rd_m0_value = %b \n \
salu_rd_scc_value = %b \n \
salu_rd_vcc_value = %b \n \n \
simd_rd_exec_value = %b \n \
simd_rd_m0_value = %b \n \
simd_rd_scc_value = %b \n \
simd_rd_vcc_value = %b \n \
simf_rd_exec_value = %b \n \
simf_rd_m0_value = %b \n \
simf_rd_scc_value = %b \n \
simf_rd_vcc_value = %b \n \
",
issue_salu_wr_exec_en,
issue_salu_wr_m0_en,
issue_salu_wr_scc_en,
issue_salu_wr_vcc_en,
issue_salu_wr_vcc_wfid,
issue_valu_wr_vcc_en,
issue_valu_wr_vcc_wfid,
lsu_exec_value,
lsu_rd_m0_value,
salu_rd_exec_value,
salu_rd_m0_value,
salu_rd_scc_value,
salu_rd_vcc_value,
simd_rd_exec_value,
simd_rd_m0_value,
simd_rd_scc_value,
simd_rd_vcc_value,
simf_rd_exec_value,
simf_rd_m0_value,
simf_rd_scc_value,
simf_rd_vcc_value,
);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,exec_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
interface automodport_if
( input logic clk,
input logic rst_n
);
//----------------------------------------------------------------------------------------
// Group: Signals
logic req_val;
logic [63:0] req_dat;
logic req_credit;
logic [1:0] rsp_cmd;
logic [63:0] rsp_data;
logic rsp_credit;
logic in_pure;
logic out_pure;
logic manually_listed;
//----------------------------------------------------------------------------------------
// Group: Clocking blocks
clocking req_mon_cb @(posedge clk);
input rst_n;
input req_val;
input req_dat;
input req_credit;
input manually_listed;
endclocking : req_mon_cb
clocking rsp_drv_cb @(posedge clk);
input rst_n;
output rsp_cmd;
output rsp_data;
input rsp_credit;
endclocking : rsp_drv_cb
//----------------------------------------------------------------------------------------
// Group: Modports
modport req_mon_mp(clocking req_mon_cb);
modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
modport pure_mp(input in_pure, output out_pure);
//----------------------------------------------------------------------------------------
// Group: Methods
function void rsp_reset();
rsp_cmd = 2'b0;
rsp_data = 64'b0;
endfunction : rsp_reset
//----------------------------------------------------------------------------------------
// Group: Assertions
logic [1:0] cmd_m1;
always @(posedge clk) begin
cmd_m1 <= rsp_cmd;
if(rst_n) begin
if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
end
end
endinterface
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Power Management ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PM according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// - add support for dynamic clock gating ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_pm(
// RISC Internal Interface
clk, rst, pic_wakeup, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// Power Management Interface
pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input pic_wakeup; // Wakeup from the PIC
input spr_write; // SPR Read/Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
//
// Power Management Interface
//
input pm_cpustall; // Stall the CPU
output [3:0] pm_clksd; // Clock Slowdown factor
output pm_dc_gate; // Gate DCache clock
output pm_ic_gate; // Gate ICache clock
output pm_dmmu_gate; // Gate DMMU clock
output pm_immu_gate; // Gate IMMU clock
output pm_tt_gate; // Gate Tick Timer clock
output pm_cpu_gate; // Gate main RISC/CPU clock
output pm_wakeup; // Activate (de-gate) all clocks
output pm_lvolt; // Lower operating voltage
`ifdef OR1200_PM_IMPLEMENTED
//
// Power Management Register bits
//
reg [3:0] sdf; // Slow-down factor
reg dme; // Doze Mode Enable
reg sme; // Sleep Mode Enable
reg dcge; // Dynamic Clock Gating Enable
//
// Internal wires
//
wire pmr_sel; // PMR select
//
// PMR address decoder (partial decoder)
//
`ifdef OR1200_PM_PARTIAL_DECODING
assign pmr_sel = (spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) ? 1'b1 : 1'b0;
`else
assign pmr_sel = ((spr_addr[`OR1200_SPR_GROUP_BITS] == `OR1200_SPRGRP_PM) &&
(spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_PM_OFS_PMR)) ? 1'b1 : 1'b0;
`endif
//
// Write to PMR and also PMR[DME]/PMR[SME] reset when
// pic_wakeup is asserted
//
always @(posedge clk or posedge rst)
if (rst)
{dcge, sme, dme, sdf} <= 7'b0;
else if (pmr_sel && spr_write) begin
sdf <= #1 spr_dat_i[`OR1200_PM_PMR_SDF];
dme <= #1 spr_dat_i[`OR1200_PM_PMR_DME];
sme <= #1 spr_dat_i[`OR1200_PM_PMR_SME];
dcge <= #1 spr_dat_i[`OR1200_PM_PMR_DCGE];
end
else if (pic_wakeup) begin
dme <= #1 1'b0;
sme <= #1 1'b0;
end
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = sdf;
assign spr_dat_o[`OR1200_PM_PMR_DME] = dme;
assign spr_dat_o[`OR1200_PM_PMR_SME] = sme;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = dcge;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
//
// Generate pm_clksd
//
assign pm_clksd = sdf;
//
// Statically generate all clock gate outputs
// TODO: add dynamic clock gating feature
//
assign pm_cpu_gate = (dme | sme) & ~pic_wakeup;
assign pm_dc_gate = pm_cpu_gate;
assign pm_ic_gate = pm_cpu_gate;
assign pm_dmmu_gate = pm_cpu_gate;
assign pm_immu_gate = pm_cpu_gate;
assign pm_tt_gate = sme & ~pic_wakeup;
//
// Assert pm_wakeup when pic_wakeup is asserted
//
assign pm_wakeup = pic_wakeup;
//
// Assert pm_lvolt when pm_cpu_gate or pm_cpustall are asserted
//
assign pm_lvolt = pm_cpu_gate | pm_cpustall;
`else
//
// When PM is not implemented, drive all outputs as would when PM is disabled
//
assign pm_clksd = 4'b0;
assign pm_cpu_gate = 1'b0;
assign pm_dc_gate = 1'b0;
assign pm_ic_gate = 1'b0;
assign pm_dmmu_gate = 1'b0;
assign pm_immu_gate = 1'b0;
assign pm_tt_gate = 1'b0;
assign pm_wakeup = 1'b1;
assign pm_lvolt = 1'b0;
//
// Read PMR
//
`ifdef OR1200_PM_READREGS
assign spr_dat_o[`OR1200_PM_PMR_SDF] = 4'b0;
assign spr_dat_o[`OR1200_PM_PMR_DME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_SME] = 1'b0;
assign spr_dat_o[`OR1200_PM_PMR_DCGE] = 1'b0;
`ifdef OR1200_PM_UNUSED_ZERO
assign spr_dat_o[`OR1200_PM_PMR_UNUSED] = 25'b0;
`endif
`endif
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_2_V
`define SKY130_FD_SC_MS__HA_2_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_BLACKBOX_V
`define SKY130_FD_SC_MS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: phy_dly_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:02 $
// \ \ / \ Date Created: Mon Jun 30 2008
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Multiplexing for all DQ/DQS/Capture and resynchronization clock
// IODELAY elements
// Scope of this module:
// IODELAYs controlled:
// 1. DQ (rdlvl/writes)
// 2. DQS (wrlvl/phase detector)
// 3. Capture clock (rdlvl/phase detector)
// 4. Resync clock (rdlvl/phase detector)
// Functions performed:
// 1. Synchronization (from GCLK to BUFR domain)
// 2. Multi-rank IODELAY lookup (NOT YET SUPPORTED)
// NOTES:
// 1. Per-bit DQ control not yet supported
// 2. Multi-rank control not yet supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_dly_ctrl.v,v 1.1 2011/06/02 07:18:02 mishra Exp $
**$Date: 2011/06/02 07:18:02 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_dly_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_dly_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQ_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter RANK_WIDTH = 1, // # of ranks of DRAM
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter WRLVL = "ON", // Enable write leveling
parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter nDQS_COL0 = 4, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 4, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 32'h03020100, // DQS grps in col #1
parameter DQS_LOC_COL1 = 32'h07060504, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0, // DQS grps in col #4
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk,
input rst,
input [3:0] clk_rsync,
input [3:0] rst_rsync,
// Operation status, control signals
input wrlvl_done,
input [1:0] rdlvl_done,
input pd_cal_done,
input mc_data_sel,
input [RANK_WIDTH:0] mc_ioconfig,
input mc_ioconfig_en,
input [0:0] phy_ioconfig,
input phy_ioconfig_en,
input dqs_oe,
// DQ, DQS IODELAY controls for write leveling
input [5*DQS_WIDTH-1:0] dlyval_wrlvl_dqs,
input [5*DQS_WIDTH-1:0] dlyval_wrlvl_dq,
// Capture Clock / Resync Clock IODELAY controls for read leveling
input [DQS_WIDTH-1:0] dlyce_rdlvl_cpt,
input dlyinc_rdlvl_cpt,
input [3:0] dlyce_rdlvl_rsync,
input dlyinc_rdlvl_rsync,
input [5*DQS_WIDTH-1:0] dlyval_rdlvl_dq,
input [5*DQS_WIDTH-1:0] dlyval_rdlvl_dqs,
// Phase detector IODELAY control for DQS, Capture Clock
input [DQS_WIDTH-1:0] dlyce_pd_cpt,
input [DQS_WIDTH-1:0] dlyinc_pd_cpt,
input [5*DQS_WIDTH-1:0] dlyval_pd_dqs,
// IODELAY controls
output reg [5*DQS_WIDTH-1:0] dlyval_dqs,
output reg [5*DQS_WIDTH-1:0] dlyval_dq,
output dlyrst_cpt,
output [DQS_WIDTH-1:0] dlyce_cpt,
output [DQS_WIDTH-1:0] dlyinc_cpt,
output dlyrst_rsync,
output [3:0] dlyce_rsync,
output [3:0] dlyinc_rsync,
// Debug Port
input dbg_pd_off
);
reg [DQS_WIDTH-1:0] dlyce_cpt_mux;
reg [3:0] dlyce_rsync_mux;
reg [DQS_WIDTH-1:0] dlyinc_cpt_mux;
reg [3:0] dlyinc_rsync_mux;
reg dqs_oe_r;
reg dqs_wr;
wire [0:0] mux_ioconfig;
wire mux_ioconfig_en;
wire mux_rd_wr;
reg mux_rd_wr_last_r;
reg rd_wr_r;
reg [3:0] rd_wr_rsync_r;
reg [3:0] rd_wr_rsync_tmp_r;
reg [3:0] rd_wr_rsync_tmp_r1;
//***************************************************************************
// IODELAY RESET CONTROL:
// RST for IODELAY is used to control parallel loading of IODELAY (dlyval)
// For all IODELAYs where glitching of outputs is permitted, always assert
// RST (i.e. control logic can change outputs without worrying about
// synchronization of control bits causing output glitching). For all other
// IODELAYs (CPT, RSYNC), only assert RST when DLYVAL is stable
//***************************************************************************
assign dlyrst_cpt = rst;
assign dlyrst_rsync = rst;
//***************************************************************************
// IODELAY MUX CONTROL LOGIC AND CLOCK SYNCHRONIZATION
// This logic determines the main MUX control logic for selecting what gets
// fed to the IODELAY taps. Output signal is MUX_IOCFG = [0 for write, 1 for
// read]. This logic is in the CLK domain, and needs to be synchronized to
// each of the individual CLK_RSYNC[x] domains
//***************************************************************************
// Select between either MC or PHY control
assign mux_ioconfig = (mc_data_sel) ?
mc_ioconfig[RANK_WIDTH] :
phy_ioconfig;
assign mux_ioconfig_en = (mc_data_sel) ?
mc_ioconfig_en :
phy_ioconfig_en;
assign mux_rd_wr = mux_ioconfig[0];
always @(posedge clk)
dqs_oe_r <= #TCQ dqs_oe;
// Generate indication when write is occurring - necessary to prevent
// situation where a read request comes in on DFI before the current
// write has been completed on the DDR bus - in that case, the IODELAY
// value should remain at the write value until the write is completed
// on the DDR bus.
always @(dqs_oe or mux_rd_wr_last_r)
dqs_wr = mux_rd_wr_last_r | dqs_oe;
// Store value of MUX_IOCONFIG when enable(latch) signal asserted
always @(posedge clk)
if (mux_ioconfig_en)
mux_rd_wr_last_r <= #TCQ mux_rd_wr;
// New value of MUX_IOCONFIG gets reflected right away as soon as
// enable/latch signal is asserted. This signal indicates whether a
// write or read is occurring (1 = write, 0 = read). Add dependence on
// DQS_WR to account for pipelining - prevent read value from being
// loaded until previous write is finished
always @(posedge clk) begin
if (mux_ioconfig_en) begin
if ((dqs_wr)&& (DRAM_TYPE == "DDR3"))
rd_wr_r <= #TCQ 1'b1;
else
rd_wr_r <= #TCQ mux_rd_wr;
end else begin
if ((dqs_wr)&& (DRAM_TYPE == "DDR3"))
rd_wr_r <= #TCQ 1'b1;
else
rd_wr_r <= #TCQ mux_rd_wr;
end
end
// Synchronize MUX control to each of the individual clock domains
genvar r_i;
generate
for (r_i = 0; r_i < 4; r_i = r_i + 1) begin: gen_sync_rd_wr
if (DRAM_TYPE == "DDR2") begin : gen_cwl_ddr2
if (nCWL <= 3) begin: gen_cwl_ddr2_ls_4
// one less pipeline stage for cwl<= 3
always @(posedge clk_rsync[r_i]) begin
rd_wr_rsync_tmp_r[r_i] <= #TCQ rd_wr_r;
rd_wr_rsync_r[r_i] <= #TCQ rd_wr_rsync_tmp_r[r_i];
end
end else begin
always @(posedge clk_rsync[r_i]) begin:gen_cwl_ddr2_gt_3
rd_wr_rsync_tmp_r[r_i] <= #TCQ rd_wr_r;
rd_wr_rsync_tmp_r1[r_i] <= #TCQ rd_wr_rsync_tmp_r[r_i];
rd_wr_rsync_r[r_i] <= #TCQ rd_wr_rsync_tmp_r1[r_i];
end
end
end else if ((nCWL == 5) ||
((nCWL == 6) && (REG_CTRL == "ON"))) begin: gen_cwl_5_ddr3
// For CWL = 5, bypass one of the pipeline registers for speed
// purposes (need to load IODELAY value as soon as possible on write,
// time between IOCONFIG_EN and OSERDES.WC assertion is shorter than
// for all other CWL values. Rely on built in registers in IODELAY to
// reduce metastability?
// NOTE: 2nd case added where we consider the case of registered
// DIMM and an nCWL value (as passed to this module) of 6 to be
// the same case, because the actual CWL value = 5 (as programmed
// in the DRAM - see module phy_top for CWL_M adjustment) and more
// importantly, the controller (MC) treats the CWL as 5 for bus
// turnaround purposes, and on a WRITE->READ, it the extra clock
// cycle is needed to program the new value of the IODELAY before
// the read data is captured. Note that we may want to apply this
// case as well for DDR2 registered DIMMs as well
always @(posedge clk_rsync[r_i])
rd_wr_rsync_r[r_i] <= #TCQ rd_wr_r;
end else begin: gen_cwl_gt_5_ddr3
// Otherwise, use two pipeline stages in CLK_RSYNC domain to
// reduce metastability
always @(posedge clk_rsync[r_i]) begin
rd_wr_rsync_tmp_r[r_i] <= #TCQ rd_wr_r;
rd_wr_rsync_r[r_i] <= #TCQ rd_wr_rsync_tmp_r[r_i];
end
end
end
endgenerate
//***************************************************************************
// IODELAY CE/INC MUX LOGIC
// Increment/Enable MUX logic for Capture and Resynchronization clocks.
// No synchronization of these signals to another clock domain is
// required - the capture and resync clock IODELAY control ports are
// clocked by CLK
//***************************************************************************
always @(posedge clk) begin
if (!rdlvl_done[1]) begin
// If read leveling not completed, rdlvl logic has control of capture
// and resync clock adjustment IODELAYs
dlyce_cpt_mux <= #TCQ dlyce_rdlvl_cpt;
dlyinc_cpt_mux <= #TCQ {DQS_WIDTH{dlyinc_rdlvl_cpt}};
dlyce_rsync_mux <= #TCQ dlyce_rdlvl_rsync;
dlyinc_rsync_mux <= #TCQ {4{dlyinc_rdlvl_rsync}};
end else begin
if ((PHASE_DETECT == "OFF") ||
((DEBUG_PORT == "ON") && dbg_pd_off)) begin
// If read phase detector is off, give control of CPT/RSYNC IODELAY
// taps to the read leveling logic. Normally the read leveling logic
// will not be changing the IODELAY values after initial calibration.
// However, the debug port interface for changing the CPT/RSYNC
// tap values does go through the PHY_RDLVL module - if the user
// has this capability enabled, then that module will change the
// IODELAY tap values. Note that use of the debug interface to change
// the CPT/RSYNC tap values is limiting to changing the tap values
// only when the read phase detector is turned off - otherwise, if
// the read phase detector is on, it will simply "undo" any changes
// to the tap count made via the debug port interface
dlyce_cpt_mux <= #TCQ dlyce_rdlvl_cpt;
dlyinc_cpt_mux <= #TCQ {DQS_WIDTH{dlyinc_rdlvl_cpt}};
dlyce_rsync_mux <= #TCQ dlyce_rdlvl_rsync;
dlyinc_rsync_mux <= #TCQ {4{dlyinc_rdlvl_rsync}};
end else begin
// Else read phase detector has control of capture/rsync phases
dlyce_cpt_mux <= #TCQ dlyce_pd_cpt;
dlyinc_cpt_mux <= #TCQ dlyinc_pd_cpt;
// Phase detector does not control RSYNC - rely on RSYNC positioning
// to be able to handle entire possible range that phase detector can
// vary the capture clock IODELAY taps. In the future, we may want to
// change to allow phase detector to vary RSYNC taps, if there is
// insufficient margin to allow for a "static" scheme
dlyce_rsync_mux <= #TCQ 'b0;
dlyinc_rsync_mux <= #TCQ 'b0;
// COMMENTED - RSYNC clock is fixed
// dlyce_rsync_mux <= #TCQ {4{dlyce_pd_cpt[0]}};
// dlyinc_rsync_mux <= #TCQ {4{dlyinc_pd_cpt}};
end
end
end
assign dlyce_cpt = dlyce_cpt_mux;
assign dlyinc_cpt = dlyinc_cpt_mux;
assign dlyce_rsync = dlyce_rsync_mux;
assign dlyinc_rsync = dlyinc_rsync_mux;
//***************************************************************************
// SYNCHRONIZATION FOR CLK <-> CLK_RSYNC[X] DOMAINS
//***************************************************************************
//***************************************************************************
// BIT STEERING EQUATIONS:
// What follows are 4 generate loops - each of which handles "bit
// steering" for each of the I/O columns. The first loop is always
// instantited. The other 3 will only be instantiated depending on the
// number of I/O columns used
//***************************************************************************
generate
genvar c0_i;
if (nDQS_COL0 > 0) begin: gen_c0
for (c0_i = 0; c0_i < nDQS_COL0; c0_i = c0_i + 1) begin: gen_loop_c0
//*****************************************************************
// DQ/DQS DLYVAL MUX LOGIC
// This is the MUX logic to control the parallel load delay values for
// DQ and DQS IODELAYs. There are up to 4 MUX's, one for each
// CLK_RSYNC[x] clock domain. Each MUX can handle a variable amount
// of DQ/DQS IODELAYs depending on the particular user pin assignment
// (e.g. how many I/O columns are used, and the particular DQS groups
// assigned to each I/O column). The MUX select (S), and input lines
// (A,B) are configured:
// S: MUX_IO_CFG_RSYNC[x]
// A: value of DQ/DQS IODELAY from write leveling logic
// B: value of DQ/DQS IODELAY from read phase detector logic (DQS) or
// from read leveling logic (DQ). NOTE: The value of DQS may also
// depend on the read leveling logic with per-bit deskew support.
// This may require another level of MUX prior to this MUX
// The parallel signals from the 3 possible sources (wrlvl, rdlvl, read
// phase detector) are not synchronized to CLK_RSYNC< but also are not
// timing critical - i.e. the IODELAY output can glitch briefly.
// Therefore, there is no need to synchronize any of these sources
// prior to the MUX (although a MAXDELAY constraint to ensure these
// async paths aren't too long - they should be less than ~2 clock
// cycles) should be added
//*****************************************************************
always @ (posedge clk_rsync[0]) begin
if (rd_wr_rsync_r[0]) begin
// Load write IODELAY values
dlyval_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5]
<= #TCQ dlyval_wrlvl_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5];
// Write DQ IODELAY values are byte-wide only
dlyval_dq[5*(DQS_LOC_COL0[8*c0_i+:8])+:5]
<= #TCQ dlyval_wrlvl_dq[5*(DQS_LOC_COL0[8*c0_i+:8])+:5];
end else begin
// Load read IODELAY values
if ((PHASE_DETECT == "ON") && rdlvl_done[1]) begin
// Phase Detector has control
dlyval_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5]
<= #TCQ dlyval_pd_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5];
end else begin
// Read Leveling logic has control of DQS (used only if IODELAY
// taps are required for either per-bit or low freq calibration)
dlyval_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dqs[5*(DQS_LOC_COL0[8*c0_i+:8])+:5];
end
dlyval_dq[5*(DQS_LOC_COL0[8*c0_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dq[5*(DQS_LOC_COL0[8*c0_i+:8])+:5];
end
end
end
end
endgenerate
//*****************************************************************
// The next 3 cases are for the other 3 banks. Conditionally include
// only if multiple banks are supported. There's probably a better
// way of instantiating these 3 other cases without taking up so much
// space....
//*****************************************************************
// I/O COLUMN #2
generate
genvar c1_i;
if (nDQS_COL1 > 0) begin: gen_c1
for (c1_i = 0; c1_i < nDQS_COL1; c1_i = c1_i + 1) begin: gen_loop_c1
always @(posedge clk_rsync[1]) begin
if (rd_wr_rsync_r[1]) begin
dlyval_dqs[5*(DQS_LOC_COL1[8*c1_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dqs[5*(DQS_LOC_COL1[8*c1_i+7-:8])+:5];
dlyval_dq[5*(DQS_LOC_COL1[8*c1_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dq[5*(DQS_LOC_COL1[8*c1_i+:8])+:5];
end else begin
if ((PHASE_DETECT == "ON") && rdlvl_done[1]) begin
// Phase Detector has control
dlyval_dqs[5*(DQS_LOC_COL1[8*c1_i+:8])+:5]
<= #TCQ dlyval_pd_dqs[5*(DQS_LOC_COL1[8*c1_i+:8])+:5];
end else begin
// Read Leveling logic has control of DQS (used only if IODELAY
// taps are required for either per-bit or low freq calibration)
dlyval_dqs[5*(DQS_LOC_COL1[8*c1_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dqs[5*(DQS_LOC_COL1[8*c1_i+:8])+:5];
end
dlyval_dq[5*(DQS_LOC_COL1[8*c1_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dq[5*(DQS_LOC_COL1[8*c1_i+:8])+:5];
end
end
end
end
endgenerate
// I/O COLUMN #3
generate
genvar c2_i;
if (nDQS_COL2 > 0) begin: gen_c2
for (c2_i = 0; c2_i < nDQS_COL2; c2_i = c2_i + 1) begin: gen_loop_c2
always @(posedge clk_rsync[2]) begin
if (rd_wr_rsync_r[2]) begin
dlyval_dqs[5*(DQS_LOC_COL2[8*c2_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dqs[5*(DQS_LOC_COL2[8*c2_i+7-:8])+:5];
dlyval_dq[5*(DQS_LOC_COL2[8*c2_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dq[5*(DQS_LOC_COL2[8*c2_i+:8])+:5];
end else begin
if ((PHASE_DETECT == "ON") && rdlvl_done[1]) begin
// Phase Detector has control
dlyval_dqs[5*(DQS_LOC_COL2[8*c2_i+:8])+:5]
<= #TCQ dlyval_pd_dqs[5*(DQS_LOC_COL2[8*c2_i+:8])+:5];
end else begin
// Read Leveling logic has control of DQS (used only if IODELAY
// taps are required for either per-bit or low freq calibration)
dlyval_dqs[5*(DQS_LOC_COL2[8*c2_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dqs[5*(DQS_LOC_COL2[8*c2_i+:8])+:5];
end
dlyval_dq[5*(DQS_LOC_COL2[8*c2_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dq[5*(DQS_LOC_COL2[8*c2_i+:8])+:5];
end
end
end
end
endgenerate
// I/O COLUMN #4
generate
genvar c3_i;
if (nDQS_COL3 > 0) begin: gen_c3
for (c3_i = 0; c3_i < nDQS_COL3; c3_i = c3_i + 1) begin: gen_loop_c3
always @(posedge clk_rsync[3]) begin
if (rd_wr_rsync_r[3]) begin
dlyval_dqs[5*(DQS_LOC_COL3[8*c3_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dqs[5*(DQS_LOC_COL3[8*c3_i+7-:8])+:5];
dlyval_dq[5*(DQS_LOC_COL3[8*c3_i+7-:8])+:5]
<= #TCQ dlyval_wrlvl_dq[5*(DQS_LOC_COL3[8*c3_i+:8])+:5];
end else begin
if ((PHASE_DETECT == "ON") && rdlvl_done[1]) begin
// Phase Detector has control
dlyval_dqs[5*(DQS_LOC_COL3[8*c3_i+:8])+:5]
<= #TCQ dlyval_pd_dqs[5*(DQS_LOC_COL3[8*c3_i+:8])+:5];
end else begin
// Read Leveling logic has control of DQS (used only if IODELAY
// taps are required for either per-bit or low freq calibration)
dlyval_dqs[5*(DQS_LOC_COL3[8*c3_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dqs[5*(DQS_LOC_COL3[8*c3_i+:8])+:5];
end
dlyval_dq[5*(DQS_LOC_COL3[8*c3_i+:8])+:5]
<= #TCQ dlyval_rdlvl_dq[5*(DQS_LOC_COL3[8*c3_i+:8])+:5];
end
end
end
end
endgenerate
endmodule
|
`include "seeed_tft_defines.v"
module seeed_tft_command (
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output reg [7:0] o_cmd_data,
input i_enable,
input i_cmd_rs,
output reg o_cmd_finished,
//Physical Signals
output o_cmd_mode,
output reg o_write,
output reg o_read,
output reg [7:0] o_data_out,
input [7:0] i_data_in,
output reg o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam DELAY = 4'h1;
localparam FINISHED = 4'h2;
//Registers/Wires
reg [3:0] state;
reg [7:0] count;
//Submodules
//Asynchronous Logic
assign o_cmd_mode = i_cmd_rs;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_data_out_en <= 0;
o_data_out <= 0;
o_cmd_finished <= 0;
o_cmd_data <= 0;
o_write <= 0;
o_read <= 0;
count <= 0;
end
else begin
//Strobes
o_cmd_finished <= 0;
if (count < `DELAY_COUNT) begin
count <= count + 1;
end
//State Machine
case (state)
IDLE: begin
o_write <= 0;
o_read <= 0;
count <= `DELAY_COUNT;
o_data_out_en <= 0;
if (i_cmd_write_stb) begin
//Change the bus to an output
o_data_out_en <= 1;
//Put the data on the bus
o_data_out <= i_cmd_data;
o_write <= 1;
state <= DELAY;
count <= 0;
end
else if (i_cmd_read_stb) begin
//Change the bus to an input
o_data_out_en <= 0;
o_read <= 1;
state <= DELAY;
count <= 0;
end
end
DELAY: begin
if (count >= `DELAY_COUNT) begin
state <= FINISHED;
end
end
FINISHED: begin
o_write <= 0;
o_read <= 0;
if (!o_data_out_en) begin
//XXX: The appliction note doesn't describe how to explicitly read
//and the protocol is different from the 8080 MCU interface
o_cmd_data <= i_data_in;
end
o_cmd_finished <= 1;
state <= IDLE;
end
endcase
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: Sora_RCB_top
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Non-Posted Packet Generator wrapper file.
// Connects the NonPosted Packet Slicer and Non-Posted Packet Builder modules
// together
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang:
// add logic for TX descriptor request ----------- done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module non_posted_pkt_gen(
input clk,
input rst,
/// Jiansong: control signal for transfer recovering
`ifdef TF_RECOVERY
input transferstart,
`endif
//inputs from dma_ctrl_wrapper
input [63:0] dmaras,
input [31:0] dmarad,
input [31:0] dmarxs,
input rd_dma_start,
/// Jiansong: added for TX descriptor request
input rd_TX_des_start,
input [63:0] TX_des_addr,
//inputs from pcie block plus
input [2:0] read_req_size,
input [15:0] req_id,
//outputs to non posted header fifo
output non_posted_fifo_wren,
output [63:0] non_posted_fifo_data,
//in and outs to tag_generator
output tag_inc,
input tag_gnt,
input [7:0] tag_value,
//outputs to read_request_wrapper
output [4:0] tx_waddr,
output [31:0] tx_wdata,
output tx_we
);
//internal wrapper connections
wire [31:0] dmarad_reg;
wire [63:0] dmaras_reg;
wire [9:0] length;
wire ack,go; //handshake signals
wire isDes;
wire rd_dma_start_one;
wire rd_TX_des_start_one;
/// Jiansong: moved here from tx engine
rising_edge_detect rd_dma_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_dma_start),
.one_shot_out(rd_dma_start_one)
);
/// Jiansong: added for TX des request trigger
rising_edge_detect rd_TX_des_start_one_inst(
.clk(clk),
.rst(rst_reg),
.in(rd_TX_des_start),
.one_shot_out(rd_TX_des_start_one)
);
non_posted_pkt_slicer non_posted_pkt_slicer_inst(
.clk(clk),
.rst(rst),
/// Jiansong: control signal for transfer recovering
`ifdef TF_RECOVERY
.transferstart(transferstart),
`endif
//interface to dma_ctrl_wrapper
.rd_TX_des_start_one(rd_TX_des_start_one),/// Jiansong:
.TX_des_addr(TX_des_addr), /// added for TX des request
.isDes(isDes), ///
.rd_dma_start(rd_dma_start_one),
.dmarad(dmarad),
.dmarxs(dmarxs),
.dmaras(dmaras),
.read_req_size(read_req_size), //from pcie block
//interface to non_posted_pkt_builder
.ack(ack),
.go(go),
.dmarad_reg(dmarad_reg[31:0]),
.dmaras_reg(dmaras_reg[63:0]),
.length(length[9:0])
);
non_posted_pkt_builder non_posted_pkt_builder_inst(
.clk(clk),
.rst(rst),
.req_id(req_id[15:0]), //from pcie block
//interface to/from non_posted_pkt_slicer
.go(go),
.ack(ack),
.dmaras(dmaras_reg[63:0]),
.dmarad(dmarad_reg[31:0]),
.length(length[9:0]),
.isDes(isDes), /// Jiansong:
//interface to/from tag_generator
.tag_value(tag_value[7:0]),
.tag_gnt(tag_gnt),
.tag_inc(tag_inc),
//interface to/from a64_64_distram_np(non-posted header fifo)
.header_data_out(non_posted_fifo_data[63:0]),
.header_data_wren(non_posted_fifo_wren),
//interface to read_request_wrapper
.tx_waddr(tx_waddr[4:0]),
.tx_wdata(tx_wdata[31:0]),
.tx_we(tx_we)
);
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: FIFO_GENERATOR_V10_0.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_v10_0.vhd
* |
* +-fifo_generator_v10_0_bhv_ver_as
* |
* +-fifo_generator_v10_0_bhv_ver_ss
* |
* +-fifo_generator_v10_0_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v10_0
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Stream, 1: AXI Full, 2: AXI Lite
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [8-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [2-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [8-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [2-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [8-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [2-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [8-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [2-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [8-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [2-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [8-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [2-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [8-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [2-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [8-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [2-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
// Enable Distributed RAM Low latency FIFO for FWFT Built-in FIFO, otherwise use Distributed RAM
.C_FIFO_TYPE ((C_PRELOAD_LATENCY != 0 && C_MEMORY_TYPE == 4) ? 1 : C_IMPLEMENTATION_TYPE > 2 ? 2 : 0)
)
fifo_generator_v10_0_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (WR_DATA_COUNT),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR)
);
end endgenerate
localparam C_AXI_LEN_WIDTH = 8;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_LOCK_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 0) && (C_AXIS_TYPE == 0)) ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
generate if (C_INTERFACE_TYPE == 1 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
end
end
assign axi_rs_rst = rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_AXIS <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = ~axis_full;
assign axis_m_axis_tvalid = ~axis_empty;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 1)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam IS_AXI_FULL_WR_CH = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 1) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RD_CH = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 1) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WR_CH = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 2) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RD_CH = ((C_INTERFACE_TYPE == 1) && (C_AXI_TYPE == 2) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam AWID_OFFSET = C_AXI_TYPE == 1 ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE == 1 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE == 1 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE == 1 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE == 1 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE == 1 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = AWQOS_OFFSET - C_AXI_REGION_WIDTH;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = C_AXI_TYPE == 1 ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = C_AXI_TYPE == 1 ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_WACH <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_WDCH <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_SLAVE_CE == 1) ? wrch_we & S_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_MASTER_CE == 1) ? wrch_re & M_ACLK_EN : wrch_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_WRCH <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_wach_output
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
end endgenerate // axi_wdch_output
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, S_AXI_AWBURST,
S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, S_AXI_AWQOS, S_AXI_AWREGION,
S_AXI_AWUSER};
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : gwach_din2
assign wach_din = {S_AXI_AWID, S_AXI_AWADDR, S_AXI_AWLEN, S_AXI_AWSIZE, S_AXI_AWBURST,
S_AXI_AWLOCK, S_AXI_AWCACHE, S_AXI_AWPROT, S_AXI_AWQOS, S_AXI_AWREGION};
assign M_AXI_AWUSER = 0;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WUSER, S_AXI_WLAST};
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 0) begin : gwdch_din2
assign wdch_din = {S_AXI_WID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WLAST};
assign M_AXI_WUSER = 0;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din = {M_AXI_BID, M_AXI_BRESP, M_AXI_BUSER};
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : gwrch_din2
assign wrch_din = {M_AXI_BID, M_AXI_BRESP};
assign S_AXI_BUSER = 0;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = C_AXI_TYPE == 1 ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE == 1 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE == 1 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE == 1 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE == 1 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE == 1 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = ARQOS_OFFSET - C_AXI_REGION_WIDTH;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = C_AXI_TYPE == 1 ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_RACH <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_SLAVE_CE == 1) ? rdch_we & S_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_MASTER_CE == 1) ? rdch_re & M_ACLK_EN : rdch_re;
FIFO_GENERATOR_V10_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 2),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE_RDCH <= 6 ? 0 : 2), // CCBI
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v10_0_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v10_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_full_rach_output
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
end endgenerate // axi_full_rdch_output
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, S_AXI_ARBURST,
S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, S_AXI_ARQOS, S_AXI_ARREGION,
S_AXI_ARUSER};
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : grach_din2
assign rach_din = {S_AXI_ARID, S_AXI_ARADDR, S_AXI_ARLEN, S_AXI_ARSIZE, S_AXI_ARBURST,
S_AXI_ARLOCK, S_AXI_ARCACHE, S_AXI_ARPROT, S_AXI_ARQOS, S_AXI_ARREGION};
assign M_AXI_ARUSER = 0;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RUSER, M_AXI_RLAST};
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : grdch_din2
assign rdch_din = {M_AXI_RID, M_AXI_RDATA, M_AXI_RRESP, M_AXI_RLAST};
assign S_AXI_RUSER = 0;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //FIFO_GENERATOR_V10_0
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module FIFO_GENERATOR_V10_0_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex6", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
always @* rst_delayed <= #`TCQ RST ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
reg rd_rst_asreg_d1 = 0;
reg rd_rst_asreg_d2 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg rd_rst_d1 = 0;
reg wr_rst_asreg = 0;
reg wr_rst_asreg_d1 = 0;
reg wr_rst_asreg_d2 = 0;
reg wr_rst_reg = 0;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg rst_asreg_d1 = 0;
reg rst_asreg_d2 = 0;
reg rst_reg = 0;
wire rst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v10_0_bhv_ver_ss
#(
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v10_0_bhv_ver_as
#(
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v10_0_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v10_0_bhv_ver_as
#(
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v10_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (RAMVALID_P0_OUT),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= #`TCQ 1;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
if (srst_delayed && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v10_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end //block30
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
generate
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed;
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg;
wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1;
end
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= #`TCQ 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg;
rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1;
end
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= #`TCQ 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rst_asreg <= #`TCQ 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
rst_asreg_d1 <= #`TCQ rst_asreg;
rst_asreg_d2 <= #`TCQ rst_asreg_d1;
end
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= #`TCQ 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
end
endgenerate
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b0;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b0;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d4;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate
endmodule //FIFO_GENERATOR_V10_0_CONV_VER
module fifo_generator_v10_0_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v10_0_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v10_0_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
reg ram_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= #`TCQ 1'b1;
ALMOST_EMPTY <= #`TCQ 1'b1;
rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
valid_d1: valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= #`TCQ 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end
endgenerate
//Capture delayed version of dout
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW==1) begin : blockOF2
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF2
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v10_0_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v10_0_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
diff_pntr <= 0;
ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= #`TCQ 0;
ideal_prog_empty <= #`TCQ 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
// block memory has a synchronous reset
always @(posedge RD_CLK) begin : gen_fifo_blkmemdout
// make it consistent with the core.
if (rd_rst_i) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2)
err_type <= #`TCQ 0;
// BRAM resets synchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
end //always
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always
endmodule // fifo_generator_v10_0_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v10_0_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v10_0_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v10_0_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output FULL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
/***************************************************************************
* Parameters used as constants
**************************************************************************/
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DATA_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_HAS_SRST ? SRST : 0;
assign rst_i = C_HAS_RST ? RST : 0;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end endgenerate // blockVL20
// block memory has a synchronous reset
generate if (C_MEMORY_TYPE < 2) begin : gen_fifo_blkmemdout_emb
always @(posedge CLK) begin
// BRAM resets synchronously
// make it consistent with the core.
if ((rst_i || srst_i) && (C_USE_DOUT_RST == 1))
ideal_dout_d1 <= #`TCQ dout_reset_val;
end //always
end endgenerate // gen_fifo_blkmemdout_emb
reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ram_rd_en_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_i) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW==1) begin : blockOF20
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW==1) begin : blockUF20
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end endgenerate // blockUF20
/*************************************************************************
* Write and Read Logic
************************************************************************/
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign write_only = write_allow & ~read_allow;
assign write_only_q = write_allow_q & ~read_allow_q;
assign read_only = read_allow & ~write_allow;
assign read_only_q = read_allow_q & ~write_allow_q;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe = 0;
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
//-----------------------------------------------------------------------------
// Write the memory
//-----------------------------------------------------------------------------
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
//-----------------------------------------------------------------------------
// Read the memory for Non-low latency Block RAM FIFO
// For Block RAM FIFO, the reset and read are always synchronous
//-----------------------------------------------------------------------------
generate if (C_DOUT_WIDTH > 2) begin
always @* dout_tmp1 <= {dout_tmp[C_DOUT_WIDTH-1:2],~dout_tmp[1:0]};
end endgenerate // gnll_bm_dout
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_bm_dout
always@ (read_allow or rd_pntr or dout_tmp_q) dout_tmp <= (read_allow) ? memory[rd_pntr] : dout_tmp_q;
always @(posedge CLK) begin
if (RST_FULL_FF || srst_i) begin
if (C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
end else begin
if (read_allow) begin
if (ENABLE_ERR_INJECTION == 1) begin
if (dout_tmp[C_DATA_WIDTH-1]) begin
if (C_DOUT_WIDTH > 2)
ideal_dout <= #`TCQ dout_tmp1;
else if (C_DOUT_WIDTH == 2)
ideal_dout <= #`TCQ ~dout_tmp[1:0];
else
ideal_dout[0] <= #`TCQ dout_tmp[0];
err_type <= #`TCQ {dout_tmp[C_DATA_WIDTH-1],1'b0};
end else begin
ideal_dout <= #`TCQ dout_tmp[C_DOUT_WIDTH-1:0];
err_type <= #`TCQ {1'b0,dout_tmp[C_DATA_WIDTH-2]};
end
end else
ideal_dout <= #`TCQ memory[rd_pntr];
end
end
end
end endgenerate // gnll_bm_dout
//-----------------------------------------------------------------------------
// Read the memory for Non-low latency Distributed RAM FIFO
// For Distributed RAM FIFO, the reset can be asynchronous but read is always
// synchronous for Non-low latency FIFO
//-----------------------------------------------------------------------------
generate if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin : gnll_dm_dout
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF) begin
if (C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
end else begin
if (srst_i) begin
if (C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
end else if (read_allow) begin
ideal_dout <= #`TCQ memory[rd_pntr];
end
end
end
end endgenerate // gnll_dm_dout
//-----------------------------------------------------------------------------
// Read the memory for Low latency Distributed RAM FIFO
// This configuration does not support DOUT reset value and the read is always
// asynchronous
//-----------------------------------------------------------------------------
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) begin : reg_write_allow
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF) begin
write_allow_q <= 1'b0;
read_allow_q <= 1'b0;
diff_pntr <= 0;
diff_pntr_pe <= 0;
end else begin
if (srst_i) begin
write_allow_q <= #`TCQ 1'b0;
read_allow_q <= #`TCQ 1'b0;
diff_pntr <= #`TCQ 0;
diff_pntr_pe <= #`TCQ 0;
end else begin
write_allow_q <= #`TCQ write_allow;
read_allow_q <= #`TCQ read_allow;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr <= #`TCQ wr_pntr - rd_pntr + 1;
else
diff_pntr <= #`TCQ wr_pntr - rd_pntr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe <= #`TCQ wr_pntr - rd_pntr - 1;
else
diff_pntr_pe <= #`TCQ wr_pntr - rd_pntr;
end
end
end
end endgenerate // reg_write_allow
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
assign comp1 = (rd_pntr == (wr_pntr + 1'b1));
assign comp0 = (rd_pntr == wr_pntr);
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_i)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
assign ecomp1 = (wr_pntr == (rd_pntr + 1'b1));
assign ecomp0 = (wr_pntr == rd_pntr);
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
empty_i <= 1'b1;
else if (srst_i)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
ideal_wr_ack <= 1'b0;
else if (srst_i)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
ideal_valid <= 1'b0;
else if (srst_i)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
assign fcomp2 = (rd_pntr == (wr_pntr + 2'h2));
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_i)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
assign ecomp2 = (wr_pntr == (rd_pntr + 2'h2));
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_empty_i <= 1'b1;
else if (srst_i)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - 2 : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - 2 : // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_i)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_i)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - 2'h2 : // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_i)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else
prog_full_i <= #`TCQ 1'b0;
end else
prog_full_i <= #`TCQ prog_full_i;
end
end
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT - 2'h2) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE - 2'h2) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_i)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 : // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2 : // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
prog_empty_i <= 1'b1;
else begin
if (srst_i)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
prog_empty_i <= 1'b1;
else begin
if (srst_i)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH - 2'h2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
prog_empty_i <= 1'b1;
else begin
if (srst_i)
prog_empty_i <= #`TCQ 1'b1;
else if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2'h2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2'h2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
prog_empty_i <= 1'b1;
else begin
if (srst_i)
prog_empty_i <= #`TCQ 1'b1;
else if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v10_0_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v10_0_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input RD_CLK,
input RD_RST,
input SRST,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg read_data_valid_i;
wire ram_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
read_data_valid_i = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_HAS_SRST ? SRST : 0;
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_FIFO_TYPE != 2) begin : gnll_fifo
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN);
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
curr_state <= 1'b0;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
curr_state <= #`TCQ 1'b0;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
curr_state <= #`TCQ next_state;
ram_valid_i <= #`TCQ next_state;
end
end //always
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = ram_valid_i;
assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
// BRAM resets synchronously
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end else begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
endmodule
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v10_0_axic_reg_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
`include "../defined.vh"
module Mult
(
clk,
rst,
a,
b,
mult_func,
c_mult
);
input clk;
input rst;
input [31:0] a;
input [31:0] b;
input [3:0] mult_func;
output reg [31:0] c_mult;
reg[31:0] Hi,Lo;
reg write_Lo,write_Hi;
reg[2:0] comm;
wire signed[31:0] a_s,b_s;
assign a_s=a;
assign b_s=b;
always@(*)
begin
c_mult<=0;
write_Lo<=0;
write_Hi<=0;
comm<=0;
case(mult_func)
`MULT_NOTHING:
c_mult<=0;
`MULT_READ_LO:
c_mult<=Lo;
`MULT_READ_HI:
c_mult<=Hi;
`MULT_WRITE_LO:
write_Lo<=1;
`MULT_WRITE_HI:
write_Hi<=1;
`MULT_MULT:
comm<=1;
`MULT_SIGNED_MULT:
comm<=2;
`MULT_DIVIDE:
comm<=3;
`MULT_SIGNED_DIVIDE:
comm<=4;
endcase
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
Hi<=0;
Lo<=0;
end
else if(comm==0)
begin
if(write_Lo)
Lo<=a;
if(write_Hi)
Hi<=a;
end
else if(comm==1)//mult
{Hi,Lo}<=a*b;
else if(comm==2)//mult_signed
{Hi,Lo}<=a_s*b_s;
else if(comm==3)//div
begin
if(b!=32'b0)
begin
Lo<=32'b0;//FIXME: DIV is removed a/b;
Hi<=32'b0;//FIXME: DIV is removed a%b;
end
end
else if(comm==4)//div_signed
begin
if(b_s!=32'b0)
begin
Lo<=32'b0;//FIXME: DIV is removed a_s/b_s;
Hi<=32'b0;//FIXME: DIV is removed a_s%b_s;
end
end
end
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module addsub16 (
add_sub,
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input add_sub;
input [15:0] dataa;
input [15:0] datab;
input clock;
input aclr;
input clken;
output [15:0] result;
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/vga_sync/vga_sync.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Outputs HSYNC and VSYNC signals to control 640x480@60Hz VGA output. x/y outputs indicates the
* current {x, y} pixel position being displayed.
*
* Note: VSYNC/HSYNC signals are latched for stability, introducing a 1 CLK delay. The RGB
* generation circuit must be aware of this, and should latch its output as well.
***************************************************************************************************/
module vga_sync
(
input wire clk, // 100Mhz clock signal
input wire rst,
output wire hsync, // HSYNC VGA control output
output wire vsync, // VSYNC VGA control output
output wire en, // Indicates when RGB generation circuit should enable (x,y valid)
output wire [9:0] x, // Current X position being displayed
output wire [9:0] y, // Current Y position being displayed (top = 0)
output wire [9:0] x_next, // Next X position to be displayed next clock
output wire [9:0] y_next // Next Y position to be displayed
);
//
// VGA signal timing parameters. Taken from http://tinyvga.com/vga-timing/640x480@60Hz. Note
// that this circuit uses a 25MHz clock instead of specified 25.175MHz clock. Most displays can
// cope with this out of spec behavior.
//
localparam H_DISP = 640; // Number of displayable columns
localparam H_FP = 16; // Horizontal front porch in pixel clocks
localparam H_RT = 96; // Horizontal retrace (hsync pulse) in pixel clocks
localparam H_BP = 48; // Horizontal back porch in pixel clocks
localparam V_DISP = 480; // Number of displayable rows
localparam V_FP = 10; // Vertical front porch in lines
localparam V_RT = 2; // Vertical retrace (vsync pulse) in lines
localparam V_BP = 29; // Vertical back porch in lines
//localparam H_DISP = 4; // Number of displayable columns
//localparam H_FP = 10; // Horizontal front porch in pixel clocks
//localparam H_RT = 2; // Horizontal retrace (hsync pulse) in pixel clocks
//localparam H_BP = 20; // Horizontal back porch in pixel clocks
//localparam V_DISP = 2; // Number of displayable rows
//localparam V_FP = 1; // Vertical front porch in lines
/*
localparam V_RT = 3; // Vertical retrace (vsync pulse) in lines
localparam V_BP = 2; // Vertical back porch in lines
*/
// FF for mod-4 counter. Used to generate a 25MHz pixel enable signal.
reg [1:0] q_mod4_cnt;
reg [1:0] d_mod4_cnt;
// Horizontal and vertical counters. Used relative to timings specified in pixels or lines, above.
// Equivalent to x,y position when in the displayable region.
reg [9:0] q_hcnt, q_vcnt;
reg [9:0] d_hcnt, d_vcnt;
// Output signal FFs.
reg q_hsync, q_vsync, q_en;
reg d_hsync, d_vsync, d_en;
// FF update logic.
always @(posedge clk) begin
q_mod4_cnt <= d_mod4_cnt;
q_hcnt <= d_hcnt;
q_vcnt <= d_vcnt;
q_hsync <= d_hsync;
q_vsync <= d_vsync;
q_en <= d_en;
end
wire pix_pulse; // 1 clk tick per-pixel
wire line_pulse; // 1 clk tick per-line (reset to h-pos 0)
wire screen_pulse; // 1 clk tick per-screen (reset to v-pos 0)
assign pix_pulse = (q_mod4_cnt == 0);
assign line_pulse = pix_pulse && (q_hcnt == (H_DISP + H_FP + H_RT + H_BP - 1));
assign screen_pulse = line_pulse && (q_vcnt == (V_DISP + V_FP + V_RT + V_BP - 1));
// Assign output wires to appropriate FFs.
assign hsync = q_hsync;
assign vsync = q_vsync;
assign x = q_hcnt;
assign y = q_vcnt;
assign x_next = d_hcnt;
assign y_next = (y == (V_DISP + V_FP + V_RT + V_BP - 10'h001)) ? 10'h000 : (q_vcnt + 10'h001);
assign en = q_en;
always @ (*) begin
if (rst) begin
d_mod4_cnt = 2'b00;
d_hcnt = 9'h000;
d_vcnt = 9'h000;
d_hsync = 1'b0;
d_en = 1'b0;
end
else begin
d_mod4_cnt = q_mod4_cnt + 2'h1;
d_hcnt = (line_pulse) ? 10'h000 : ((pix_pulse) ? q_hcnt + 10'h001 : q_hcnt);
d_vcnt = (screen_pulse) ? 10'h000 : ((line_pulse) ? q_vcnt + 10'h001 : q_vcnt);
d_hsync = (q_hcnt >= (H_DISP + H_FP)) && (q_hcnt < (H_DISP + H_FP + H_RT));
d_vsync = (q_vcnt >= (V_DISP + V_FP)) && (q_vcnt < (V_DISP + V_FP + V_RT));
d_en = (q_hcnt < H_DISP) && (q_vcnt < V_DISP);
end
end
endmodule
|
// ghrd_10as066n2_avlmm_pr_freeze_bridge_1.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire mst_bridge_to_pr_read, // mst_bridge_to_pr.read
output wire mst_bridge_to_pr_waitrequest, // .waitrequest
input wire mst_bridge_to_pr_write, // .write
input wire [31:0] mst_bridge_to_pr_address, // .address
input wire [3:0] mst_bridge_to_pr_byteenable, // .byteenable
input wire [31:0] mst_bridge_to_pr_writedata, // .writedata
output wire [31:0] mst_bridge_to_pr_readdata, // .readdata
input wire [2:0] mst_bridge_to_pr_burstcount, // .burstcount
output wire mst_bridge_to_pr_readdatavalid, // .readdatavalid
input wire mst_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
input wire mst_bridge_to_pr_debugaccess, // .debugaccess
output wire [1:0] mst_bridge_to_pr_response, // .response
input wire mst_bridge_to_pr_lock, // .lock
output wire mst_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
output wire mst_bridge_to_sr_read, // mst_bridge_to_sr.read
input wire mst_bridge_to_sr_waitrequest, // .waitrequest
output wire mst_bridge_to_sr_write, // .write
output wire [31:0] mst_bridge_to_sr_address, // .address
output wire [3:0] mst_bridge_to_sr_byteenable, // .byteenable
output wire [31:0] mst_bridge_to_sr_writedata, // .writedata
input wire [31:0] mst_bridge_to_sr_readdata, // .readdata
output wire [2:0] mst_bridge_to_sr_burstcount, // .burstcount
input wire mst_bridge_to_sr_readdatavalid, // .readdatavalid
output wire mst_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
output wire mst_bridge_to_sr_debugaccess, // .debugaccess
input wire [1:0] mst_bridge_to_sr_response, // .response
output wire mst_bridge_to_sr_lock, // .lock
input wire mst_bridge_to_sr_writeresponsevalid, // .writeresponsevalid
input wire reset_n // reset_n.reset_n
);
ghrd_10as066n2_avlmm_pr_freeze_bridge_1_altera_avlmm_pr_freeze_bridge_171_yvsimhi #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0)
) avlmm_pr_freeze_bridge_1 (
.clock (clock), // input, width = 1, clock.clk
.freeze_conduit_freeze (freeze_conduit_freeze), // input, width = 1, freeze_conduit.freeze
.freeze_conduit_illegal_request (freeze_conduit_illegal_request), // output, width = 1, .illegal_request
.mst_bridge_to_pr_read (mst_bridge_to_pr_read), // input, width = 1, mst_bridge_to_pr.read
.mst_bridge_to_pr_waitrequest (mst_bridge_to_pr_waitrequest), // output, width = 1, .waitrequest
.mst_bridge_to_pr_write (mst_bridge_to_pr_write), // input, width = 1, .write
.mst_bridge_to_pr_address (mst_bridge_to_pr_address), // input, width = 32, .address
.mst_bridge_to_pr_byteenable (mst_bridge_to_pr_byteenable), // input, width = 4, .byteenable
.mst_bridge_to_pr_writedata (mst_bridge_to_pr_writedata), // input, width = 32, .writedata
.mst_bridge_to_pr_readdata (mst_bridge_to_pr_readdata), // output, width = 32, .readdata
.mst_bridge_to_pr_burstcount (mst_bridge_to_pr_burstcount), // input, width = 3, .burstcount
.mst_bridge_to_pr_readdatavalid (mst_bridge_to_pr_readdatavalid), // output, width = 1, .readdatavalid
.mst_bridge_to_pr_beginbursttransfer (mst_bridge_to_pr_beginbursttransfer), // input, width = 1, .beginbursttransfer
.mst_bridge_to_pr_debugaccess (mst_bridge_to_pr_debugaccess), // input, width = 1, .debugaccess
.mst_bridge_to_pr_response (mst_bridge_to_pr_response), // output, width = 2, .response
.mst_bridge_to_pr_lock (mst_bridge_to_pr_lock), // input, width = 1, .lock
.mst_bridge_to_pr_writeresponsevalid (mst_bridge_to_pr_writeresponsevalid), // output, width = 1, .writeresponsevalid
.mst_bridge_to_sr_read (mst_bridge_to_sr_read), // output, width = 1, mst_bridge_to_sr.read
.mst_bridge_to_sr_waitrequest (mst_bridge_to_sr_waitrequest), // input, width = 1, .waitrequest
.mst_bridge_to_sr_write (mst_bridge_to_sr_write), // output, width = 1, .write
.mst_bridge_to_sr_address (mst_bridge_to_sr_address), // output, width = 32, .address
.mst_bridge_to_sr_byteenable (mst_bridge_to_sr_byteenable), // output, width = 4, .byteenable
.mst_bridge_to_sr_writedata (mst_bridge_to_sr_writedata), // output, width = 32, .writedata
.mst_bridge_to_sr_readdata (mst_bridge_to_sr_readdata), // input, width = 32, .readdata
.mst_bridge_to_sr_burstcount (mst_bridge_to_sr_burstcount), // output, width = 3, .burstcount
.mst_bridge_to_sr_readdatavalid (mst_bridge_to_sr_readdatavalid), // input, width = 1, .readdatavalid
.mst_bridge_to_sr_beginbursttransfer (mst_bridge_to_sr_beginbursttransfer), // output, width = 1, .beginbursttransfer
.mst_bridge_to_sr_debugaccess (mst_bridge_to_sr_debugaccess), // output, width = 1, .debugaccess
.mst_bridge_to_sr_response (mst_bridge_to_sr_response), // input, width = 2, .response
.mst_bridge_to_sr_lock (mst_bridge_to_sr_lock), // output, width = 1, .lock
.mst_bridge_to_sr_writeresponsevalid (mst_bridge_to_sr_writeresponsevalid), // input, width = 1, .writeresponsevalid
.reset_n (reset_n) // input, width = 1, reset_n.reset_n
);
endmodule
|
module top;
reg pass;
integer result;
reg [3:0] expr;
initial begin
pass = 1'b1;
result = $countones(1'b0);
if (result != 0) begin
$display("FAILED: for 1'b0 expected a count of 0, got %d", result);
pass = 1'b0;
end
result = $countones(1'b1);
if (result != 1) begin
$display("FAILED: for 1'b1 expected a count of 1, got %d", result);
pass = 1'b0;
end
result = $countones(2'b01);
if (result != 1) begin
$display("FAILED: for 2'b01 expected a count of 1, got %d", result);
pass = 1'b0;
end
result = $countones(4'b0111);
if (result != 3) begin
$display("FAILED: for 4'b0111 expected a count of 3, got %d", result);
pass = 1'b0;
end
expr = 4'b1100;
result = $countones(expr);
if (result != 2) begin
$display("FAILED: for 4'b1100 expected a count of 2, got %d", result);
pass = 1'b0;
end
result = $countones(34'b1100000000000000000000000000000001);
if (result != 3) begin
$display("FAILED: for 34'1100000000000000000000000000000001 expected a count of 3, got %d", result);
pass = 1'b0;
end
result = $countones(34'b1111000000110000001100000011000000);
if (result != 10) begin
$display("FAILED: for 34'1111000000110000001100000011000000 expected a count of 10, got %d", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o31a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31A_FUNCTIONAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`ifdef TEST_VERBOSE
`define WRITE_VERBOSE(args) $write args
`else
`define WRITE_VERBOSE(args)
`endif
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
event e1;
event e2;
`ifndef IVERILOG
event ev [3:0];
`endif
int cyc;
int last_event;
always @(e1) begin
`WRITE_VERBOSE(("[%0t] e1\n", $time));
if (!e1.triggered) $stop;
last_event[1] = 1;
end
always @(e2) begin
`WRITE_VERBOSE(("[%0t] e2\n", $time));
last_event[2] = 1;
end
always @(posedge clk) begin
`WRITE_VERBOSE(("[%0t] cyc=%0d last_event=%5b\n", $time, cyc, last_event));
cyc <= cyc + 1;
if (cyc == 1) begin
// Check no initial trigger
if (last_event != 0) $stop;
end
//
else if (cyc == 10) begin
last_event = 0;
-> e1;
end
else if (cyc == 12) begin
if (last_event != 32'b10) $stop;
last_event = 0;
end
else if (cyc == 13) begin
// Check not still triggering
if (last_event != 0) $stop;
last_event = 0;
end
//
else if (cyc == 10) begin
last_event = 0;
->> e2;
end
else if (cyc == 12) begin
if (last_event != 32'b100) $stop;
last_event = 0;
end
else if (cyc == 13) begin
// Check not still triggering
if (last_event != 0) $stop;
last_event = 0;
end
//
else if (cyc == 99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// Check the power operator (run time).
module top;
reg pass;
integer res;
reg signed [31:0] l, r;
initial begin
pass = 1'b1;
// Check the constant ** with various arguments (table 5-6 1364-2005).
l = -3;
r = 'bx;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant -3**'bx, expected 'bx, got %0d", res);
pass = 1'b0;
end
l = -1;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant -1**'bx, expected 'bx, got %0d", res);
pass = 1'b0;
end
l = 0;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 0**'bx, expected 'bx, got %0d", res);
pass = 1'b0;
end
l = 1;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 1**'bx, expected 'bx, got %0d", res);
pass = 1'b0;
end
l = 3;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 3**'bx, expected 'bx, got %0d", res);
pass = 1'b0;
end
l = 'bx;
r=-3;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**-3, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=-2;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**-2, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=-1;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**-1, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=0;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**0, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=1;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**1, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=2;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**2, expected 'bx, got %0d", res);
pass = 1'b0;
end
r=3;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 'bx**3, expected 'bx, got %0d", res);
pass = 1'b0;
end
// Check the 1st line (rvalue is positive).
l=-3;
r=3;
res = l**r;
if (res !== -27) begin
$display("Failed: constant -3**3, expected -27, got %0d", res);
pass = 1'b0;
end
l=-3;
r=2;
res = l**r;
if (res !== 9) begin
$display("Failed: constant -3**2, expected 9, got %0d", res);
pass = 1'b0;
end
l=-1;
r=3;
res = l**r;
if (res !== -1) begin
$display("Failed: constant -1**3, expected -1, got %0d", res);
pass = 1'b0;
end
l=-1;
r=2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**2, expected 1, got %0d", res);
pass = 1'b0;
end
l=0;
r=3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 0**3, expected 0, got %0d", res);
pass = 1'b0;
end
l=0;
r=2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 0**2, expected 0, got %0d", res);
pass = 1'b0;
end
l=1;
r=3;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**3, expected 1, got %0d", res);
pass = 1'b0;
end
l=1;
r=2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**2, expected 1, got %0d", res);
pass = 1'b0;
end
l=3;
r=3;
res = l**r;
if (res !== 27) begin
$display("Failed: constant 3**3, expected 27, got %0d", res);
pass = 1'b0;
end
l=3;
r=2;
res = l**r;
if (res !== 9) begin
$display("Failed: constant 3**2, expected 9, got %0d", res);
pass = 1'b0;
end
// Check the 2nd line (rvalue is zero).
l=-3;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -3**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=-2;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -2**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=-1;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=0;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 0**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=1;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=2;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 2**0, expected 1, got %0d", res);
pass = 1'b0;
end
l=3;
r=0;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 3**0, expected 1, got %0d", res);
pass = 1'b0;
end
// Check the 3rd line (rvalue is negative).
l=-2;
r=-3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant -2**-3, expected 0, got %0d", res);
pass = 1'b0;
end
l=-2;
r=-2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant -2**-2, expected 0, got %0d", res);
pass = 1'b0;
end
l=-1;
r=-3;
res = l**r;
if (res !== -1) begin
$display("Failed: constant -1**-3, expected -1, got %0d", res);
pass = 1'b0;
end
l=-1;
r=-2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant -1**-2, expected 1, got %0d", res);
pass = 1'b0;
end
l=0;
r=-3;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 0**-3, expected 'bx, got %0d", res);
pass = 1'b0;
end
l=0;
r=-2;
res = l**r;
if (res !== 'bx) begin
$display("Failed: constant 0**-2, expected 'bx, got %0d", res);
pass = 1'b0;
end
l=1;
r=-3;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**-3, expected 1, got %0d", res);
pass = 1'b0;
end
l=1;
r=-2;
res = l**r;
if (res !== 1) begin
$display("Failed: constant 1**-2, expected 1, got %0d", res);
pass = 1'b0;
end
l=2;
r=-3;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 2**-3, expected 0, got %0d", res);
pass = 1'b0;
end
l=2;
r=-2;
res = l**r;
if (res !== 0) begin
$display("Failed: constant 2**-2, expected 0, got %0d", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
module adv3224 (
// avalon-bus
input clk,
input reset,
input avs_slave_write,
input avs_slave_read,
input [7:0]avs_slave_writedata,
output [7:0]avs_slave_readdata,
input [2:0]avs_slave_address,
// adv3224
output cps_reset_n,
output cps_ce_n,
output cps_update_n,
output cps_clk,
output cps_datain
);
//
// parameters
//
parameter divider = 5;
//
// regs / wires
//
reg [8:0]clk_counter;
reg div_clk;
reg clk_en;
reg [39:0]shift_buffer;
reg shift_busy;
reg [5:0]shift_counter;
reg [4:0]outputs[0:7];
//
// ip
//
assign cps_reset_n = !reset;
assign cps_ce_n = 0;
assign avs_slave_readdata = shift_busy;
assign cps_clk = clk_en ? div_clk : 1'b1;
assign cps_update_n = (!clk_en && shift_busy) ? !div_clk : 1'b1;
assign cps_datain = shift_buffer[39];
always @(posedge clk or posedge reset)
begin
if(reset)
begin
clk_counter <= 1;
div_clk <= 1;
clk_en <= 0;
shift_busy <= 0;
shift_counter <= 0;
outputs[0] <= 5'b00000;
outputs[1] <= 5'b00000;
outputs[2] <= 5'b00000;
outputs[3] <= 5'b00000;
outputs[4] <= 5'b00000;
outputs[5] <= 5'b00000;
outputs[6] <= 5'b00000;
outputs[7] <= 5'b00000;
end
else
begin // posedge clk
if(shift_busy)
begin
if(clk_counter == (divider/2))
begin
clk_counter <= 1;
div_clk <= !div_clk;
if(!div_clk)
begin
if(!clk_en)
begin
shift_busy <= 0;
end
else
begin
if(shift_counter == 39)
begin
clk_en <= 0;
end
else
begin
shift_counter <= shift_counter + 6'd1;
shift_buffer <= shift_buffer << 1;
end
end
end
end
else
begin
clk_counter = clk_counter + 9'd1;
end
end
else
begin
clk_counter <= 1;
shift_counter <= 0;
div_clk <= 1;
if(avs_slave_write)
begin
if(avs_slave_writedata[7])
begin
shift_buffer <= {outputs[7], outputs[6], outputs[5], outputs[4], outputs[3], outputs[2], outputs[1], outputs[0]};
shift_busy <= 1;
clk_en <= 1;
end
else
begin
outputs[avs_slave_address] <= {!avs_slave_writedata[4], avs_slave_writedata[3:0]};
end
end
end
end
end
endmodule |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
/* High level version of a small simple asynchronous transmitter/receiver
For documentation see the wiki pages. */
/*
MIT License
Copyright (c) 2016 Baard Nossum
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
////////////////////////////////////////////////////////////////////////////////
module uartICE40
# (parameter SUBDIV16 = 0, // Examine rx line 16 or 8 times per bit
ADJUSTSAMPLEPOINT = 0 // Set to 1 when bitrate*8/clk < 2 (SUBDIV16 = 0),
) ( // or bitrate*16/clk < 2 (for SUBDIV16 = 1).
input clk, // System clock
input bitxce, // High 1 clock cycle 8 or 16 times per bit
input load, // Time to transmit a byte. Load transmit buffer
input [7:0] d, // Byte to load into transmit buffer
input rxpin, // Connect to receive pin of uart
output txpin, // Connect to INVERTED transmit pin of uart
output txbusy, // Status of transmit. When high do not load
output bytercvd, //Status receive. True 1 clock cycle only
output [1:0] rxst, // Testbench need access to receive state machine
output [7:0] q // Received byte from serial receive/byte buffer
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire loadORtxce; // From rxtxdiv_i of rxtxdiv_m.v
wire rxce; // From rxtxdiv_i of rxtxdiv_m.v
// End of automatics
uarttx_m uarttx_i (/*AUTOINST*/
// Outputs
.txpin (txpin),
.txbusy (txbusy),
// Inputs
.clk (clk),
.load (load),
.loadORtxce (loadORtxce),
.d (d[7:0]));
uartrx_m uartrx_i (/*AUTOINST*/
// Outputs
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
.q (q[7:0]),
// Inputs
.clk (clk),
.rxce (rxce),
.rxpin (rxpin));
rxtxdiv_m #( .ADJUSTSAMPLEPOINT(ADJUSTSAMPLEPOINT),
.SUBDIV16(SUBDIV16))
rxtxdiv_i
(/*AUTOINST*/
// Outputs
.loadORtxce (loadORtxce),
.rxce (rxce),
// Inputs
.clk (clk),
.bitxce (bitxce),
.load (load),
.rxpin (rxpin),
.rxst (rxst[1:0]));
endmodule
////////////////////////////////////////////////////////////////////////////////
module uarttx_m
(input clk,load,loadORtxce,
input [7:0] d,
output reg txpin, txbusy
);
reg [9:0] a;
`ifdef SIMULATION
initial begin txbusy = 0; txpin = 0; a = 0; end
`endif
always @(posedge clk)
if ( loadORtxce ) begin
a[9:0] <= load ? ~{1'b0,d,1'b0} : {1'b0,a[9:1]};
txbusy <= load | |a[9:1];
txpin <= (load & txpin) | (!load & |a[9:1] & a[0]);
end
endmodule
////////////////////////////////////////////////////////////////////////////////
module uartrxsm_m
# ( parameter HUNT = 2'b00, GRCE = 2'b01, ARMD = 2'b10, RECV = 2'b11 )
(input clk,rxce,rxpin,lastbit,
output bytercvd,
output reg [1:0] rxst
);
reg [1:0] nxt;
`ifdef SIMULATION
initial rxst = 0;
`endif
always @(/*AS*/lastbit or rxce or rxpin or rxst) begin
casez ( {rxst,rxpin,lastbit,rxce} )
{HUNT,3'b1??} : nxt = HUNT;
{HUNT,3'b0?0} : nxt = HUNT;
{HUNT,3'b0?1} : nxt = ARMD;
{ARMD,3'b??0} : nxt = ARMD;
{ARMD,3'b0?1} : nxt = RECV;
{ARMD,3'b1?1} : nxt = HUNT; // False start bit.
{RECV,3'b??0} : nxt = RECV;
{RECV,3'b?01} : nxt = RECV;
{RECV,3'b?11} : nxt = GRCE;
{GRCE,3'b??0} : nxt = GRCE;
{GRCE,3'b0?1} : nxt = HUNT; // Stop bit wrong, reject byte.
{GRCE,3'b1?1} : nxt = HUNT; // Byte received
endcase
end
always @(posedge clk)
rxst <= nxt;
assign bytercvd = (rxst == GRCE) && rxpin && rxce;
endmodule
////////////////////////////////////////////////////////////////////////////////
module uartrx_m
# (parameter HUNT = 2'b00, GRCE = 2'b01, ARMD = 2'b10, RECV = 2'b11 )
(
input clk,rxce,rxpin,
output bytercvd,
output [1:0] rxst,
output reg [7:0] q
);
`ifdef SIMULATION
initial q = 0;
`endif
uartrxsm_m #(.HUNT(HUNT), .GRCE(GRCE), .ARMD(ARMD), .RECV(RECV))
rxsm(// Inputs
.lastbit( q[0] ),
/*AUTOINST*/
// Outputs
.bytercvd (bytercvd),
.rxst (rxst[1:0]),
// Inputs
.clk (clk),
.rxce (rxce),
.rxpin (rxpin));
always @(posedge clk)
if ( rxce )
q <= (rxst == ARMD) ? 8'h80 : (rxst == RECV) ? {rxpin,q[7:1]} : q;
endmodule
////////////////////////////////////////////////////////////////////////////////
module rxtxdiv_m
# (parameter HUNT = 2'b00, GRCE = 2'b01, ARMD = 2'b10, RECV = 2'b11,
SUBDIV16 = 0, ADJUSTSAMPLEPOINT = 0
)
(input clk,bitxce,load,rxpin,
input [1:0] rxst,
output loadORtxce,
output reg rxce
);
localparam rstval = SUBDIV16 ? (ADJUSTSAMPLEPOINT ? 4'b1001 : 4'b1000) :
(ADJUSTSAMPLEPOINT ? 3'b101 : 3'b100);
reg [2+SUBDIV16:0] txcnt,rxcnt;
`ifdef SIMULATION
initial txcnt = 0;
`endif
always @(posedge clk) begin
if ( bitxce ) begin
txcnt <= txcnt + 1;
rxcnt <= rxst == HUNT ? rstval : (rxcnt+1);
end
rxce <= ((rxst != HUNT) & (&rxcnt & bitxce) )
| ((rxst == HUNT | rxst == GRCE) & rxpin);
end
assign loadORtxce = (&txcnt & bitxce) | load;
endmodule
// Local Variables:
// verilog-library-directories:("." "./fromrefdesign/" )
// verilog-library-files:("../../../PROJ/iCE_simlib/iCE_simlib.v" )
// verilog-library-extensions:(".v" )
// End:
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 11:17:35
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <= 7) begin : GENSTOP
mult2 #(.SW(SW))
inst_mult (
.DatA(Data_A_i),
.DatB(Data_B_i),
.DatO(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW(SW/2)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW((SW/2)+1)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW((SW/2)+1)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW(SW/2+2)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
// DESCRIPTION::Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t;
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
typedef enum logic [1:0]
{ ZERO = 2'd0,
ONE = 2'd1,
TWO = 2'd2,
THREE = 2'd3,
XXX = 2'dx
} num_t;
function automatic logic is_odd;
input en;
input num_t number;
case (en)
1'b1: begin
unique if (number inside {ONE, THREE})
is_odd = 1'b1;
else if (number inside {ZERO, TWO})
is_odd = 1'b0;
else
is_odd = 1'bx;
end
1'b0: is_odd = 1'bx;
default: is_odd = 1'bx;
endcase
endfunction
initial begin
`checkh ((4'd4 inside {4'd1,4'd5}), 1'b0);
`checkh ((4'd4 inside {4'd1,4'd4}), 1'b1);
//
`checkh ((4'b1011 inside {4'b1001}), 1'b0);
`checkh ((4'b1011 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1xx1}), 1'b1); // Uses ==?
`checkh ((4'b1001 inside {4'b1??1}), 1'b1);
`ifndef VERILATOR
`checkh ((4'b1z11 inside {4'b11?1, 4'b1011}),1'bx);
`endif
// Range
`checkh ((4'd4 inside {[4'd5:4'd3], [4'd10:4'd8]}), 1'b0); // If left of colon < never matches
`checkh ((4'd3 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd4 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
`checkh ((4'd5 inside {[4'd1:4'd2], [4'd3:4'd5]}), 1'b1);
//
// Unsupported $ bound
//
// Unsupported if unpacked array, elements tranversed
//int unpackedarray [$] = '{8,9};
//( expr inside {2, 3, unpackedarray}) // { 2,3,8,9}
//
`checkh (is_odd(1'b1, ZERO), 1'd0);
`checkh (is_odd(1'b1, ONE), 1'd1);
`checkh (is_odd(1'b1, TWO), 1'd0);
`checkh (is_odd(1'b1, THREE),1'd1);
`ifndef VERILATOR
`checkh (is_odd(1'b1, XXX), 1'dx);
`endif
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_to_avm #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1
)
(
// AVM interface
output logic avm_enable,
output logic avm_read,
output logic avm_write,
output logic [DATA_W-1:0] avm_writedata,
output logic [BURSTCOUNT_W-1:0] avm_burstcount,
output logic [ADDRESS_W-1:0] avm_address,
output logic [BYTEENA_W-1:0] avm_byteenable,
input logic avm_waitrequest,
input logic avm_readdatavalid,
input logic [DATA_W-1:0] avm_readdata,
input logic avm_writeack, // not a true Avalon signal, so ignore this
// IC interface
input logic ic_arb_request,
input logic ic_arb_enable,
input logic ic_arb_read,
input logic ic_arb_write,
input logic [DATA_W-1:0] ic_arb_writedata,
input logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
input logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
input logic [BYTEENA_W-1:0] ic_arb_byteenable,
input logic [ID_W-1:0] ic_arb_id,
output logic ic_arb_stall,
output logic ic_wrp_ack,
output logic ic_rrp_datavalid,
output logic [DATA_W-1:0] ic_rrp_data
);
assign avm_read = ic_arb_read;
assign avm_write = ic_arb_write;
assign avm_writedata = ic_arb_writedata;
assign avm_burstcount = ic_arb_burstcount;
assign avm_address = {ic_arb_address, {$clog2(DATA_W / 8){1'b0}}};
assign avm_byteenable = ic_arb_byteenable;
assign ic_arb_stall = avm_waitrequest;
assign ic_rrp_datavalid = avm_readdatavalid;
assign ic_rrp_data = avm_readdata;
//assign ic_wrp_ack = avm_writeack;
assign ic_wrp_ack = avm_write & ~avm_waitrequest;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFRTP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_BLACKBOX_V
|
`timescale 1ns / 1ps
`include "cordic.vh"
// synopsys_ template
module cordic
#(
parameter DEC = 2, // decimal points
parameter FRAC = 14, // fraction points
parameter MOD = `MOD_CIR, // MOD = {`MOD_CIR=1,`MOD_LIN=0,`MOD_HYP=-1}
parameter DIR = `DIR_ROT // DIR = {`DIR_ROT=0, `DIR_VEC=1}
)
(
clk,
rst,
g_init,
e_init,
o,
terminate
);
localparam L = DEC + FRAC;
localparam ITER = FRAC + 1;
localparam LOG_ITER = $clog2(ITER);
input clk;
input rst;
input [2*L-1:0] g_init; // {x, y}
input [L-1:0] e_init; // {z}
output [3*L-1:0] o;
output terminate;
wire [L-1:0] a;
wire [L-1:0] b;
wire [L-1:0] c;
wire done;
assign terminate = done;
assign o = {a, b, c};
reg [L-1:0] xi;
reg [L-1:0] yi;
reg [L-1:0] zi;
reg [L-1:0] xd;
reg [L-1:0] yd;
reg [L-1:0] zd;
wire [L-1:0] xs;
wire [L-1:0] ys;
wire [L-1:0] xi_next;
wire [L-1:0] yi_next;
wire [L-1:0] zi_next;
reg [LOG_ITER:0] iter;
wire [L-1:0] alphai;
wire di;
wire [1:0] mu;
alpha_table
#(
.DEC(DEC),
.FRAC(FRAC),
.MOD(MOD)
)
_alpha_table
(
.iter(iter[LOG_ITER-1:0]),
.alphai(alphai)
);
generate
if(DIR==`DIR_ROT) begin :ROT
assign di = zi[L-1];
end else begin :VEC// if(DIR==`DIR_VEC)
assign di = xi[L-1]&yi[L-1];
end
endgenerate
// assign xs = (xi>>iter);
// assign ys = (yi>>iter);
barrel_shifter_left
#(
.N(L)
)
_barrel_shifter_left_1
(
.a(xi),
.shift(iter),
.o(xs)
);
barrel_shifter_left
#(
.N(L)
)
_barrel_shifter_left_2
(
.a(yi),
.shift(iter),
.o(ys)
);
always @(*) begin
if(di==0) begin // di == +1
yd = xs;
zd = -alphai;
if(MOD==`MOD_HYP) begin
xd = ys;
end else if(MOD==`MOD_LIN) begin
xd = 0;
end else begin //(MOD==`MOD_CIR)
xd = -ys;
end
end else begin // di == -1
yd = -xs;
zd = alphai;
if(MOD==`MOD_HYP) begin
xd = -ys;
end else if(MOD==`MOD_LIN) begin
xd = 0;
end else begin //(MOD==`MOD_CIR)
xd = ys;
end
end
end
/*
assign xi_next = xi + xd;
assign yi_next = yi + yd;
assign zi_next = zi + zd;
*/
ADD
#(
.N(L)
)
_ADD_1
(
.A(xi),
.B(xd),
.CI(1'b0),
.S(xi_next)
);
ADD
#(
.N(L)
)
_ADD_2
(
.A(yi),
.B(yd),
.CI(1'b0),
.S(yi_next)
);
ADD
#(
.N(L)
)
_ADD_3
(
.A(zi),
.B(zd),
.CI(1'b0),
.S(zi_next)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
xi <= g_init[2*L-1:L];
yi <= g_init[L-1:0];
zi <= e_init;
iter <= 0;
end else begin
if(iter < ITER) begin
iter <= iter + 1;
xi <= xi_next;
yi <= yi_next;
zi <= zi_next;
end
end
end
assign a = xi;
assign b = yi;
assign c = zi;
assign done = (iter == ITER);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always for (expr1;boolean_expr;expr2) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
begin
value1 = 0; // Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4'h1)
begin
$display("FAILED - 3.1.7D always for (1)") ;
value2 = 1;
end
#5 ;
if(value1 != 4'h2)
begin
$display("FAILED - 3.1.7D always for (2) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h3)
begin
$display("FAILED - 3.1.7D always for (3) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
$finish;
end
always for(value1 = 0; value1 <= 5; value1 = value1 + 1) #5 ;
endmodule
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire r1,r2;
wire a1,a2;
wire r,a;
two_phase_event_gen U_PORT1_EVENT_GEN (
.run(rst_async_n),
.req(r1),
.ack(a1)
);
two_phase_event_gen U_PORT2_EVENT_GEN (
.run(rst_async_n),
.req(r2),
.ack(a2)
);
and_r1_2ph U_ASYNC_AND(
// Input ports (req/ack)
.r1(r1),
.a1(a1),
.r2(r2),
.a2(a2),
// Output ports
.r(r),
.a(a),
.rstn(rst_async_n)
);
two_phase_slave U_SLAVE(.req(r), .ack(a));
// assign #55 a = r;
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
reg clk;
initial clk = 0;
always
#100 clk = ~clk;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#200000;
$display("-I- Done !");
$finish;
end
// four_phase_assertion U_CHECKER0(.req(r0),.ack(a0),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER1(.req(r1),.ack(a1),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER2(.req(r2),.ack(a2),.rstn(rst_async_n));
// just for debug
//assign input_port1_ongoing_req = r1 ^ a1;
//assign input_port2_ongoing_req = r2 ^ a2;
//assign output_port1_unstable = g1 ^ d1;
//assign output_port2_unstable = g2 ^ d2;
//
event error1;
event error2;
assign r1_qual = r1 & a1;
assign r2_qual = r2 & a2;
assign r_qual = r & a;
// If r rises, it is because of one of the incoming request
always@(posedge r)
if(! (r1 | r2)) ->error1;
initial begin
#1;
@(error1 or error2);
$display("-E error found in protocol");
#100;
$finish;
end
endmodule // tb
|
module PS_flops_wavepool_decode (
wave_instr_pc,
wave_instr_valid,
wave_instr,
wave_wfid,
wave_vgpr_base,
wave_sgpr_base,
wave_lds_base,
flopped_instr_pc,
flopped_instr_valid,
flopped_instr,
flopped_wfid,
flopped_vgpr_base,
flopped_sgpr_base,
flopped_lds_base,
clk,
rst
);
input clk;
input rst;
input [31:0] wave_instr_pc;
input wave_instr_valid;
input [31:0] wave_instr;
input [5:0] wave_wfid;
input [9:0] wave_vgpr_base;
input [8:0] wave_sgpr_base;
input [15:0] wave_lds_base;
output [31:0] flopped_instr_pc;
output flopped_instr_valid;
output [31:0] flopped_instr;
output [5:0] flopped_wfid;
output [9:0] flopped_vgpr_base;
output [8:0] flopped_sgpr_base;
output [15:0] flopped_lds_base;
dff flop_instr_pc [31:0] (.q(flopped_instr_pc), .d(wave_instr_pc), .clk(clk), .rst(rst));
dff flop_instr_valid (.q(flopped_instr_valid), .d(wave_instr_valid), .clk(clk), .rst(rst));
dff flop_instr [31:0] (.q(flopped_instr), .d(wave_instr), .clk(clk), .rst(rst));
dff flop_wfid [5:0] (.q(flopped_wfid), .d(wave_wfid), .clk(clk), .rst(rst));
dff flop_vgpr_base [9:0] (.q(flopped_vgpr_base), .d(wave_vgpr_base), .clk(clk), .rst(rst));
dff flop_sgpr_base [8:0] (.q(flopped_sgpr_base), .d(wave_sgpr_base), .clk(clk), .rst(rst));
dff flop_lds_base [15:0] (.q(flopped_lds_base), .d(wave_lds_base), .clk(clk), .rst(rst));
endmodule
|
`timescale 1 ps / 1 ps
module simple_io(
////////////HPS///////////////
output wire [9:0] memory_mem_a, // memory.mem_a
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire hps_emac1_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_emac1_TXD0, // .hps_io_emac1_TXD0
output wire hps_emac1_TXD1, // .hps_io_emac1_TXD1
output wire hps_emac1_TXD2, // .hps_io_emac1_TXD2
output wire hps_emac1_TXD3, // .hps_io_emac1_TXD3
input wire hps_emac1_RXD0, // .hps_io_emac1_RXD0
inout wire hps_emac1_MDIO, // .hps_io_emac1_MDIO
output wire hps_emac1_MDC, // .hps_io_emac1_MDC
input wire hps_emac1_RX_CTL, // .hps_io_emac1_RX_CTL
output wire hps_emac1_TX_CTL, // .hps_io_emac1_TX_CTL
input wire hps_emac1_RX_CLK, // .hps_io_emac1_RX_CLK
input wire hps_emac1_RXD1, // .hps_io_emac1_RXD1
input wire hps_emac1_RXD2, // .hps_io_emac1_RXD2
input wire hps_emac1_RXD3, // .hps_io_emac1_RXD3
inout wire hps_qspi_IO0, // .hps_io_qspi_IO0
inout wire hps_qspi_IO1, // .hps_io_qspi_IO1
inout wire hps_qspi_IO2, // .hps_io_qspi_IO2
inout wire hps_qspi_IO3, // .hps_io_qspi_IO3
output wire hps_qspi_SS0, // .hps_io_qspi_SS0
output wire hps_qspi_CLK, // .hps_io_qspi_CLK
inout wire hps_sdio_CMD, // .hps_io_sdio_CMD
inout wire hps_sdio_D0, // .hps_io_sdio_D0
inout wire hps_sdio_D1, // .hps_io_sdio_D1
output wire hps_sdio_CLK, // .hps_io_sdio_CLK
inout wire hps_sdio_D2, // .hps_io_sdio_D2
inout wire hps_sdio_D3, // .hps_io_sdio_D3
inout wire hps_usb1_D0, // .hps_io_usb1_D0
inout wire hps_usb1_D1, // .hps_io_usb1_D1
inout wire hps_usb1_D2, // .hps_io_usb1_D2
inout wire hps_usb1_D3, // .hps_io_usb1_D3
inout wire hps_usb1_D4, // .hps_io_usb1_D4
inout wire hps_usb1_D5, // .hps_io_usb1_D5
inout wire hps_usb1_D6, // .hps_io_usb1_D6
inout wire hps_usb1_D7, // .hps_io_usb1_D7
input wire hps_usb1_CLK, // .hps_io_usb1_CLK
output wire hps_usb1_STP, // .hps_io_usb1_STP
input wire hps_usb1_DIR, // .hps_io_usb1_DIR
input wire hps_usb1_NXT, // .hps_io_usb1_NXT
input wire hps_uart0_RX, // .hps_io_uart0_RX
output wire hps_uart0_TX, // .hps_io_uart0_TX
output wire hps_spim0_CLK, // .hps_io_spim0_inst_CLK
output wire hps_spim0_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_spim0_MISO, // .hps_io_spim0_inst_MISO
output wire hps_spim0_SS0, // .hps_io_spim0_inst_SS0
inout wire hps_LED0, // .hps_io_gpio_GPIO40
inout wire hps_LED1, // .hps_io_gpio_GPIO42
input wire hps_uart1_RX, // .hps_io_uart0_RX
output wire hps_uart1_TX, // .hps_io_uart0_TX
inout wire hps_sm_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_sm_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_i2c1_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_i2c1_SCL, // .hps_io_i2c1_inst_SCL
input wire hps_can1_RX, // .hps_io_can1_inst_RX
output wire hps_can1_TX, // .hps_io_can1_inst_TX
inout wire hps_GPIO0, // .hps_io_gpio_inst_GPIO48
inout wire hps_GPIO1, // .hps_io_gpio_inst_GPIO41
inout wire hps_GPIO2, // .hps_io_gpio_inst_GPIO43
inout wire hps_TP_INT, // .hps_io_gpio_inst_GPIO44
inout wire hps_RS485_EN, // .hps_io_gpio_inst_GPIO65
input wire clk_in, // clk.clk
input wire reset_n, // reset.reset_n,
////////////FPGA///////////////
output wire [3:0] led, // fpga_led_external_connection.export
input wire [3:0] slide_sw, // slide_sw_external_connection.export
input wire [3:0] key, // fpga_key_external_connection.export
input aud_adcdat,
inout aud_bclk,
inout aud_daclrck,
inout aud_adclrck,
output aud_xck,
output adu_dacdat,
output aud_mute,
inout fpga_sd_D0,
inout fpga_sd_D1,
inout fpga_sd_D2,
inout fpga_sd_D3,
inout fpga_sd_CMD,
output fpga_sd_CLK,
input irda_rxd,
output bell_pwm,
input temp_rxd,//
input hps_gsensor_int,//
output [7:0] vga_r_data,
output [7:0] vga_g_data,
output [7:0] vga_b_data,
output vga_blank,
output vga_sync,
output lcd_hsync,
output lcd_vsync,
output lcd_clk,
output lcd_de,
output lcd_pwm,
input hdmi_int,
//daughter card
output [3:0] fpga_gpio,
input fpga_clk_in0,
input fpga_clk_in1,
input [21:0] fpga_in,
output [21:0] fpga_out
//GXB
);
simple_system u0 (
.clk_clk (clk_in), // clk.clk
.reset_reset_n (reset_n), // reset.reset_n
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ck ( memory_mem_ck ), // .mem_ck
.memory_mem_ck_n ( memory_mem_ck_n ), // .mem_ck_n
.memory_mem_cke ( memory_mem_cke ), // .mem_cke
.memory_mem_cs_n ( memory_mem_cs_n ), // .mem_cs_n
.memory_mem_dq ( memory_mem_dq ), // .mem_dq
.memory_mem_dqs ( memory_mem_dqs ), // .mem_dqs
.memory_mem_dqs_n ( memory_mem_dqs_n ), // .mem_dqs_n
.memory_mem_dm ( memory_mem_dm ), // .mem_dm
.memory_oct_rzqin ( memory_oct_rzqin ), // .oct_rzqin
.hps_io_hps_io_emac1_inst_TX_CLK ( hps_emac1_TX_CLK ), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_hps_io_emac1_inst_TXD0 ( hps_emac1_TXD0 ), // .hps_io_emac1_inst_TXD0
.hps_io_hps_io_emac1_inst_TXD1 ( hps_emac1_TXD1 ), // .hps_io_emac1_inst_TXD1
.hps_io_hps_io_emac1_inst_TXD2 ( hps_emac1_TXD2 ), // .hps_io_emac1_inst_TXD2
.hps_io_hps_io_emac1_inst_TXD3 ( hps_emac1_TXD3 ), // .hps_io_emac1_inst_TXD3
.hps_io_hps_io_emac1_inst_RXD0 ( hps_emac1_RXD0 ), // .hps_io_emac1_inst_RXD0
.hps_io_hps_io_emac1_inst_MDIO ( hps_emac1_MDIO ), // .hps_io_emac1_inst_MDIO
.hps_io_hps_io_emac1_inst_MDC ( hps_emac1_MDC ), // .hps_io_emac1_inst_MDC
.hps_io_hps_io_emac1_inst_RX_CTL ( hps_emac1_RX_CTL ), // .hps_io_emac1_inst_RX_CTL
.hps_io_hps_io_emac1_inst_TX_CTL ( hps_emac1_TX_CTL ), // .hps_io_emac1_inst_TX_CTL
.hps_io_hps_io_emac1_inst_RX_CLK ( hps_emac1_RX_CLK ), // .hps_io_emac1_inst_RX_CLK
.hps_io_hps_io_emac1_inst_RXD1 ( hps_emac1_RXD1 ), // .hps_io_emac1_inst_RXD1
.hps_io_hps_io_emac1_inst_RXD2 ( hps_emac1_RXD2 ), // .hps_io_emac1_inst_RXD2
.hps_io_hps_io_emac1_inst_RXD3 ( hps_emac1_RXD3 ), // .hps_io_emac1_inst_RXD3
.hps_io_hps_io_qspi_inst_IO0 ( hps_qspi_IO0 ), // .hps_io_qspi_inst_IO0
.hps_io_hps_io_qspi_inst_IO1 ( hps_qspi_IO1 ), // .hps_io_qspi_inst_IO1
.hps_io_hps_io_qspi_inst_IO2 ( hps_qspi_IO2 ), // .hps_io_qspi_inst_IO2
.hps_io_hps_io_qspi_inst_IO3 ( hps_qspi_IO3 ), // .hps_io_qspi_inst_IO3
.hps_io_hps_io_qspi_inst_SS0 ( hps_qspi_SS0 ), // .hps_io_qspi_inst_SS0
.hps_io_hps_io_qspi_inst_CLK ( hps_qspi_CLK ), // .hps_io_qspi_inst_CLK
.hps_io_hps_io_sdio_inst_CMD ( hps_sdio_CMD ), // .hps_io_sdio_inst_CMD
.hps_io_hps_io_sdio_inst_D0 ( hps_sdio_D0 ), // .hps_io_sdio_inst_D0
.hps_io_hps_io_sdio_inst_D1 ( hps_sdio_D1 ), // .hps_io_sdio_inst_D1
.hps_io_hps_io_sdio_inst_CLK ( hps_sdio_CLK ), // .hps_io_sdio_inst_CLK
.hps_io_hps_io_sdio_inst_D2 ( hps_sdio_D2 ), // .hps_io_sdio_inst_D2
.hps_io_hps_io_sdio_inst_D3 ( hps_sdio_D3 ), // .hps_io_sdio_inst_D3
.hps_io_hps_io_usb1_inst_D0 ( hps_usb1_D0 ), // .hps_io_usb1_inst_D0
.hps_io_hps_io_usb1_inst_D1 ( hps_usb1_D1 ), // .hps_io_usb1_inst_D1
.hps_io_hps_io_usb1_inst_D2 ( hps_usb1_D2 ), // .hps_io_usb1_inst_D2
.hps_io_hps_io_usb1_inst_D3 ( hps_usb1_D3 ), // .hps_io_usb1_inst_D3
.hps_io_hps_io_usb1_inst_D4 ( hps_usb1_D4 ), // .hps_io_usb1_inst_D4
.hps_io_hps_io_usb1_inst_D5 ( hps_usb1_D5 ), // .hps_io_usb1_inst_D5
.hps_io_hps_io_usb1_inst_D6 ( hps_usb1_D6 ), // .hps_io_usb1_inst_D6
.hps_io_hps_io_usb1_inst_D7 ( hps_usb1_D7 ), // .hps_io_usb1_inst_D7
.hps_io_hps_io_usb1_inst_CLK ( hps_usb1_CLK ), // .hps_io_usb1_inst_CLK
.hps_io_hps_io_usb1_inst_STP ( hps_usb1_STP ), // .hps_io_usb1_inst_STP
.hps_io_hps_io_usb1_inst_DIR ( hps_usb1_DIR ), // .hps_io_usb1_inst_DIR
.hps_io_hps_io_usb1_inst_NXT ( hps_usb1_NXT ), // .hps_io_usb1_inst_NXT
.hps_io_hps_io_spim0_inst_CLK ( hps_spim0_CLK ), // .hps_io_spim0_inst_CLK
.hps_io_hps_io_spim0_inst_MOSI (hps_spim0_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_hps_io_spim0_inst_MISO (hps_spim0_MISO), // .hps_io_spim0_inst_MISO
.hps_io_hps_io_spim0_inst_SS0 (hps_spim0_SS0), // .hps_io_spim0_inst_SS0
.hps_io_hps_io_uart0_inst_RX ( hps_uart0_RX ), // .hps_io_uart0_inst_RX
.hps_io_hps_io_uart0_inst_TX ( hps_uart0_TX ), // .hps_io_uart0_inst_TX
.hps_io_hps_io_uart1_inst_RX ( hps_uart1_RX), // .hps_io_uart1_inst_RX
.hps_io_hps_io_uart1_inst_TX ( hps_uart1_TX), // .hps_io_uart1_inst_TX
.hps_io_hps_io_i2c0_inst_SDA (hps_sm_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_hps_io_i2c0_inst_SCL (hps_sm_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_hps_io_i2c1_inst_SDA (hps_i2c1_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_hps_io_i2c1_inst_SCL (hps_i2c1_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_hps_io_can1_inst_RX (hps_can1_RX), // .hps_io_can1_inst_RX
.hps_io_hps_io_can1_inst_TX (hps_can1_TX), // .hps_io_can1_inst_TX
.hps_io_hps_io_gpio_inst_GPIO40 ( hps_LED0 ), // .hps_io_gpio_inst_GPIO40
.hps_io_hps_io_gpio_inst_GPIO42 ( hps_LED1 ), // .hps_io_gpio_inst_GPIO42
.hps_io_hps_io_gpio_inst_GPIO48 (hps_GPIO0), // .hps_io_gpio_inst_GPIO48
.hps_io_hps_io_gpio_inst_GPIO41 (hps_GPIO1), // .hps_io_gpio_inst_GPIO41
.hps_io_hps_io_gpio_inst_GPIO43 (hps_GPIO2), // .hps_io_gpio_inst_GPIO43
.hps_io_hps_io_gpio_inst_GPIO44 (hps_TP_INT), // .hps_io_gpio_inst_GPIO44
.hps_io_hps_io_gpio_inst_GPIO65 (hps_RS485_EN), // .hps_io_gpio_inst_GPIO65
.fpga_led_external_connection_export ( led ), // fpga_led_external_connection.export
.slide_sw_external_connection_export ( slide_sw ), // slide_sw_external_connection.export
.fpga_key_external_connection_export ( key ) // fpga_key_external_connection.export
);
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 20:41:53 01/18/2012
// Design Name:
// Module Name: videoctl
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module video_counters(
input clk,
output reg video_vsync = 1,
output reg video_hsync = 1,
output video_on,
output reg [10:1] hpos = 0,
output reg [9:1] vpos = 0);
integer hcnt = 0, vcnt = 0;
reg video_von = 0, video_hon = 0;
assign video_on = video_von & video_hon;
always @(posedge video_hsync) begin
vcnt <= vcnt + 1;
vpos <= video_von?vpos + 1: 0;
case (vcnt)
2: video_vsync = 1;
31: video_von = 1;
511: video_von = 0;
521: begin vcnt <=0; video_vsync = 0; end
endcase
end
always @(posedge clk) begin
if (!video_hon) hcnt <= hcnt - 1;
else hpos <= hpos + 1;
if (hpos == 639) video_hon <= 0;
if (hpos == 640) begin
if (!hcnt) begin
hcnt <= 96;
video_hsync <= 0;
hpos <= 0;
end
end else if (!hcnt) begin
if (!video_hsync) begin
video_hsync <= 1;
hcnt <= 48;
end else if (!video_hon) begin
video_hon <= 1;
hcnt <= 16;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:42:38 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_rxeq_scan.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE Equalization Eye Scan Test Module for 7 Series Transceiver
// Version : 10.5
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- RXEQ Eye Scan Module ----------------------------------------------
module pcie_7x_v1_3_rxeq_scan
(
//---------- Input -------------------------------------
input RXEQSCAN_CLK,
input RXEQSCAN_RST_N,
input [ 2:0] RXEQSCAN_PRESET,
input RXEQSCAN_PRESET_VALID,
input [ 3:0] RXEQSCAN_TXPRESET,
input [17:0] RXEQSCAN_TXCOEFF,
input RXEQSCAN_NEW_TXCOEFF_REQ,
input [ 5:0] RXEQSCAN_FS,
input [ 5:0] RXEQSCAN_LF,
//---------- Output ------------------------------------
output RXEQSCAN_PRESET_DONE,
output [17:0] RXEQSCAN_NEW_TXCOEFF,
output RXEQSCAN_NEW_TXCOEFF_DONE,
output RXEQSCAN_LFFS_SEL,
output RXEQSCAN_ADAPT_DONE
);
//---------- Input Register ----------------------------
reg [ 2:0] preset_reg1;
reg preset_valid_reg1;
reg [ 3:0] txpreset_reg1;
reg [17:0] txcoeff_reg1;
reg new_txcoeff_req_reg1;
reg [ 5:0] fs_reg1;
reg [ 5:0] lf_reg1;
reg [ 2:0] preset_reg2;
reg preset_valid_reg2;
reg [ 3:0] txpreset_reg2;
reg [17:0] txcoeff_reg2;
reg new_txcoeff_req_reg2;
reg [ 5:0] fs_reg2;
reg [ 5:0] lf_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] lffs_sel_cnt = 2'd0;
reg [ 2:0] adapt_done_cnt = 3'd0;
//---------- Output Register ---------------------------
reg preset_done = 1'd0;
reg [17:0] new_txcoeff = 18'd0;
reg new_txcoeff_done = 1'd0;
reg lffs_sel = 1'd0;
reg adapt_done = 1'd0;
reg [ 2:0] fsm = 3'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 3'b001;
localparam FSM_PRESET = 3'b010;
localparam FSM_NEW_TXCOEFF_REQ = 3'b100;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= 3'd0;
preset_valid_reg1 <= 1'd0;
txpreset_reg1 <= 4'd0;
txcoeff_reg1 <= 18'd0;
new_txcoeff_req_reg1 <= 1'd0;
fs_reg1 <= 6'd0;
lf_reg1 <= 6'd0;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= 3'd0;
preset_valid_reg2 <= 1'd0;
txpreset_reg2 <= 4'd0;
txcoeff_reg2 <= 18'd0;
new_txcoeff_req_reg2 <= 1'd0;
fs_reg2 <= 6'd0;
lf_reg2 <= 6'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= RXEQSCAN_PRESET;
preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
txpreset_reg1 <= RXEQSCAN_TXPRESET;
txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
fs_reg1 <= RXEQSCAN_FS;
lf_reg1 <= RXEQSCAN_LF;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= preset_reg1;
preset_valid_reg2 <= preset_valid_reg1;
txpreset_reg2 <= txpreset_reg1;
txcoeff_reg2 <= txcoeff_reg1;
new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
fs_reg2 <= fs_reg1;
lf_reg2 <= lf_reg1;
end
end
//---------- Eye Scan ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= 2'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 3'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Process RXEQ Preset ---------------
if (preset_valid_reg2)
begin
fsm <= FSM_PRESET;
preset_done <= 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient --------
else if (new_txcoeff_req_reg2)
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
new_txcoeff <= txcoeff_reg2;
new_txcoeff_done <= 1'd1;
lffs_sel <= (lffs_sel_cnt == 2'd1);
lffs_sel_cnt <= (lffs_sel_cnt + 2'd1);
adapt_done <= (adapt_done_cnt == 3'd1);
adapt_done_cnt <= (adapt_done_cnt + 3'd1);
end
//---------- Default ---------------------------
else
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Process RXEQ Preset -------------------
FSM_PRESET :
begin
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
preset_done <= 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient ------------
FSM_NEW_TXCOEFF_REQ :
begin
fsm <= (!new_txcoeff_req_reg2) ? FSM_IDLE : FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd1;
lffs_sel <= lffs_sel;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= adapt_done;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= 2'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 3'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Output ----------------------------------------------
assign RXEQSCAN_PRESET_DONE = preset_done;
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
assign RXEQSCAN_LFFS_SEL = lffs_sel;
assign RXEQSCAN_ADAPT_DONE = adapt_done;
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
/********************************************/
/* generic_output.v */
/* A generic implementation of outputs */
/* (LEDs, ...) */
/* */
/* 2012, [email protected] */
/********************************************/
module generic_output #(
parameter OW = 1, // output width
parameter DS = 1'b0, // default (off) state
parameter DBG = 0 // debug output
)(
output wire [ OW-1:0] i
);
////////////////////////////////////////
// logic //
////////////////////////////////////////
reg [ OW-1:0] state_old = {OW{DS}};
always @ (i) begin
if (i != state_old) begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state_old, i);
state_old = #1 i;
end
end
////////////////////////////////////////
// tasks //
////////////////////////////////////////
//// read ////
task read;
output [ OW-1:0] data;
begin
data = state_old;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_SYMBOL_V
`define SKY130_FD_SC_MS__MAJ3_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:06:01 08/27/2015
// Design Name:
// Module Name: FPU_Add_Subtract_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function
//Add/Subtract Function Parameters
#(parameter W = 32, parameter EW = 8, parameter SW = 23, parameter SWR=26, parameter EWR = 5) //Single Precision */
//#(parameter W = 64, parameter EW = 11, parameter SW = 52, parameter SWR = 55, parameter EWR = 6) //-- Double Precision */
(
//FSM Signals
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
//Oper_Start_in signals
input wire [W-1:0] Data_X,
input wire [W-1:0] Data_Y,
input wire add_subt,
//Round signals signals
input wire [1:0] r_mode,
//OUTPUT SIGNALS
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
////////////op_start_in///////////////
wire FSM_op_start_in_load_a,FSM_op_start_in_load_b;
wire [W-2:0] DMP, DmP;
wire real_op;
wire sign_final_result;
///////////Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=DMP_o[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW-1:0] S_Oper_A_exp;
///////////Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=DmP_o[W-2:W-9/W-12]
//D1=LZA_output
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_load_diff, FSM_exp_operation_load_OU ,FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW-1:0] exp_oper_result;
///////////Mux S-> Barrel shifter shift_Value//////
//ctrl = FSM_selector_B;
//D0=exp_oper_result
//D1=LZA_output
wire [EWR-1:0] S_Shift_Value;
///////////Mux S-> Barrel shifter Data_in//////
wire FSM_selector_C;
//D0={1'b1,DmP [SW-1:0], 2'b0}
//D1={Add_Subt_Data_output}
wire [SWR-1:0]S_Data_Shift;
///////////Barrel_Shifter//////////////////////////
wire FSM_barrel_shifter_load, FSM_barrel_shifter_L_R, FSM_barrel_shifter_B_S;
//Shift_Value=S_Shift_Value
//Data_in=S_Data_Shift
wire [SWR-1:0] Sgf_normalized_result;
//////////Mux S-> Add_Subt_Sgf op//////////////////
wire FSM_selector_D;
//D0=real_op
//D1= 1'b0
wire S_A_S_op;
//////////Mux S-> Add_Subt_Sgf OPER A//////////////////
//wire FSM_selector_D
//D0={1'b1, DMP[SW-1:0], 2'b00}
//D1= Norm_Shift_Data
wire [SWR-1:0] S_A_S_Oper_A;
//////////Mux S-> Add_Subt_Sgf OPER B//////////////////
//wire FSM_selector_D
//D0= Norm_Shift_Data
//D1= SWR'd1;
wire [SWR-1:0] S_A_S_Oper_B;
/////////ADD_Subt_sgf///////////////////////////////////
wire FSM_Add_Subt_Sgf_load, add_overflow_flag;
//Add_Subt_i=S_A_S_op
//Oper_A_i=S_A_S_Oper_A
//Oper_B_i=S_A_S_Oper_B
wire [SWR-1:0] Add_Subt_result;
wire [SWR-1:0] A_S_P;
wire [SWR-1:1] A_S_C;
//FSM_C_o=add_overflow_flag
//////////LZA///////////////////////////////////////////
wire FSM_LZA_load;
//P_i=A_S_P
//C_i=A_S_C
//A_S_op_i=S_A_S_op
wire [EWR-1:0] LZA_output;
/////////Deco_round///////////////////////////////////////
//Data_i=Sgf_normalized_result
//Round_Type=r_mode
//Sign_Result_i=sign_final_result
wire round_flag;
////////Final_result//////////////////////////////////////
wire FSM_Final_Result_load;
///////////////////////////////////////////////////////////////////////////////////
wire rst_int;
//////////////////////////////////////////////////////////////////////////////////
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
wire selector_D;
///////////////////////////////////////FSM/////////////////////////////////////////
FSM_Add_Subtract FS_Module(
.clk(clk), //
.rst(rst), //
.rst_FSM(ack_FSM), //
.beg_FSM(beg_FSM), //
.zero_flag_i(zero_flag), //
.norm_iteration_i(FSM_selector_C), //
.add_overflow_i(add_overflow_flag), //
.round_i(round_flag), //
.load_1_o(FSM_op_start_in_load_a), //
.load_2_o(FSM_op_start_in_load_b), //
.load_3_o(FSM_exp_operation_load_diff), //
.load_8_o(FSM_exp_operation_load_OU),
.A_S_op_o(FSM_exp_operation_A_S), //
.load_4_o(FSM_barrel_shifter_load), //
.left_right_o(FSM_barrel_shifter_L_R), //
.bit_shift_o(FSM_barrel_shifter_B_S), //
.load_5_o(FSM_Add_Subt_Sgf_load), //
.load_6_o(FSM_LZA_load), //
.load_7_o(FSM_Final_Result_load), //
.ctrl_a_o(selector_A), //
.ctrl_b_o(selector_B), //
.ctrl_b_load_o(load_b),
.ctrl_c_o(selector_C), //
.ctrl_d_o(selector_D), //
.rst_int(rst_int), //
.ready(ready) //
);
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(1)) Sel_D ( //Selector_D register
.clk(clk),
.rst(rst_int),
.load(selector_D),
.D(1'b1),
.Q(FSM_selector_D)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
////////////////////////////////////////////////////////
//MODULES///////////////////////////
////////////////////Oper_Start_in//////////////////7
//This Module classify both operands
//in bigger and smaller magnitude, Calculate the result' Sign bit and calculate the real
//operation for the execution///////////////////////////////
Oper_Start_In #(.W(W)) Oper_Start_in_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_op_start_in_load_a),
.load_b_i(FSM_op_start_in_load_b),
.add_subt_i(add_subt),
.Data_X_i(Data_X),
.Data_Y_i(Data_Y),
.DMP_o(DMP),
.DmP_o(DmP),
.zero_flag_o(zero_flag),
.real_op_o(real_op),
.sign_final_result_o(sign_final_result)
);
///////////////////////////////////////////////////////////
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 (DMP[W-2:W-EW-1]),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-EWR-1:0] Exp_oper_B_D1;
wire [EW-1:0] Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (DmP[W-2:W-EW-1]),
.D1 ({Exp_oper_B_D1,LZA_output}),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 =3'd0;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 =5'd0;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation #(.EW(EW)) Exp_Operation_Module(
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_exp_operation_load_diff),
.load_b_i(FSM_exp_operation_load_OU),
.Data_A_i(S_Oper_A_exp),
.Data_B_i(S_Oper_B_exp),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
//////////Mux Barrel shifter shift_Value/////////////////
wire [EWR-1:0] Barrel_Shifter_S_V_D2;
Mux_3x1 #(.W(EWR)) Barrel_Shifter_S_V_mux(
.ctrl(FSM_selector_B),
.D0 (exp_oper_result[EWR-1:0]),
.D1 (LZA_output),
.D2 (Barrel_Shifter_S_V_D2),
.S (S_Shift_Value)
);
generate
case(EW)
8:begin
assign Barrel_Shifter_S_V_D2 = 5'd1;
end
default:begin
assign Barrel_Shifter_S_V_D2 = 6'd1;
end
endcase
endgenerate
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SWR)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 ({1'b1,DmP[SW-1:0],2'b00}),
.D1 (Add_Subt_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter #(.SWR(SWR),.EWR(EWR)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(S_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.Left_Right_i(FSM_barrel_shifter_L_R),
.Bit_Shift_i(FSM_barrel_shifter_B_S),
.N_mant_o(Sgf_normalized_result)
);
//////////Mux Add_Subt_Sgf op//////////////////
Multiplexer_AC #(.W(1)) Add_Sub_Sgf_op_mux(
.ctrl(FSM_selector_D),
.D0 (real_op),
.D1 (1'b0),
.S (S_A_S_op)
);
//////////Mux Add_Subt_Sgf oper A//////////////////
Multiplexer_AC #(.W(SWR)) Add_Sub_Sgf_Oper_A_mux(
.ctrl(FSM_selector_D),
.D0 ({1'b1,DMP[SW-1:0],2'b00}),
.D1 (Sgf_normalized_result),
.S (S_A_S_Oper_A)
);
//////////Mux Add_Subt_Sgf oper B//////////////////
wire [SWR-1:0] Add_Sub_Sgf_Oper_A_D1;
Multiplexer_AC #(.W(SWR)) Add_Sub_Sgf_Oper_B_mux(
.ctrl(FSM_selector_D),
.D0 (Sgf_normalized_result),
.D1 (Add_Sub_Sgf_Oper_A_D1),
.S (S_A_S_Oper_B)
);
generate
case (W)
32:begin
assign Add_Sub_Sgf_Oper_A_D1 = 26'd4;
end
default:begin
assign Add_Sub_Sgf_Oper_A_D1 =55'd4;
end
endcase
endgenerate
/////////ADD_Subt_sgf///////////////////////////////////
Add_Subt #(.SWR(SWR)) Add_Subt_Sgf_module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_Add_Subt_Sgf_load),
.Add_Sub_op_i(S_A_S_op),
.Data_A_i(S_A_S_Oper_A),
.PreData_B_i(S_A_S_Oper_B),
.Data_Result_o(Add_Subt_result),
//.P_o(A_S_P),
//.Cn_o(A_S_C),
.FSM_C_o(add_overflow_flag)
);
/*
//Test Comb LZA//
Test_comb_LZA #(.SWR(SWR)) comb(
.clk(clk),
.rst(rst),
.Op_A_i(S_A_S_Oper_A),
.Pre_Op_B_i(S_A_S_Oper_B),
.op(S_A_S_op), //Carry in
.Cn_o(A_S_C),
.P_o(A_S_P) //Propagate (for LZA)
);
//////////LZA///////////////////////////////////////////
LZA #(.SWR(SWR),.EWR(EWR)) Leading_Zero_Anticipator_Module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_LZA_load),
.P_i(A_S_P),
.C_i(A_S_C),
.A_S_op_i(S_A_S_op),
.Shift_Value_o(LZA_output)
);
*/
wire [SWR-1:0] Add_Subt_LZD;
assign Add_Subt_LZD = ~Add_Subt_result;
LZD #(.SWR(SWR),.EWR(EWR)) Leading_Zero_Detector_Module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_LZA_load),
.Add_subt_result_i(Add_Subt_LZD),
.Shift_Value_o(LZA_output)
);
/////////Deco_round///////////////////////////////////////
Round_Sgf_Dec Rounding_Decoder(
.Data_i(Sgf_normalized_result[1:0]),
.Round_Type_i(r_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(round_flag)
);
////////Final_result//////////////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_Final_Result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result),
.sgf_ieee_i(Sgf_normalized_result[SWR-2:2]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [3:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [3:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(posedge clk) app_raw_not_ecc_r1 <= #TCQ app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 7) begin : pass_wr_addr
always @(/*AS*/wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(/*AS*/wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r = #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 4);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_r1, app_wdf_data_r1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_r1, app_wdf_data_r1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_r1, app_wdf_data_r1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,
app_wdf_mask_r1, app_wdf_data_r1};
reg [4:0] rd_addr_r;
always @(posedge clk) rd_addr_r <= #TCQ {wr_data_addr, wr_data_offset};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data[((i*6)+4)+:2]),
.DOB(wr_buf_out_data[((i*6)+2)+:2]),
.DOC(wr_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_r),
.ADDRB(rd_addr_r),
.ADDRC(rd_addr_r),
.ADDRD(wb_wr_data_addr),
.WE(app_wdf_rdy_r_copy4),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [3:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = 4'b0;
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:4];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
// Full Adder rtl
module full_adder (a0, b0, c0, a1, b1, c_out, s_out, s2, s3);
// Inputs_top
input a0;
input b0;
input c0;
// End of inputs_top
// Outputs_top
output s1;
output c_out;
output s_out;
// End of outputs_top
// Wires
wire c1;
wire c2;
wire s1;
wire d1;
wire c3;
// Some assignments
assign carry_out = c1 | c2;
assign s_out = s1;
//assign d_out = d1;
// Instantiating two half-adders to make the circuit.
// Module instantiation
half_adder u1_half_adder (
// Inputs
.in_x(a0),
.in_y(b0),
// End of inputs
// Outputs
.out_sum(s0),
.out_carry(c1)
// End of outputs
);
// Module instantiation
half_adder u2_half_adder (
// Inputs
.in_x(s0),
.in_y(c0),
// End of inputs
// Outputs
.out_sum(s1),
.out_carry(c2)
// End of outputs
);
// Module instantiation
// Module instantiation
test2 test2 (
// Inputs
.in_1(d1),
.in_2(c3),
.in_3(b1),
// End of inputs
// Outputs
.out_1(s3)
// End of outputs
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_if/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_ARUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 16,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
// write request
wire write_ready;
wire write_valid;
wire [31:0] write_address;
wire [31:0] write_length;
wire [C_USER_DATA_WIDTH-1:0] write_data;
// read request
wire read_ready;
wire read_valid;
wire [31:0] read_address;
wire [31:0] read_length;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_samples_request_preprocessor
nfa_accept_samples_generic_hw_indices_samples_request_preprocessor #(
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) request_preprocessor (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.USER_dataout ( USER_dataout ),
.USER_address ( USER_address ),
.USER_size ( USER_size ),
.USER_req_din ( USER_req_din ),
.USER_req_full_n ( USER_req_full_n ),
.USER_req_write ( USER_req_write ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length )
);
// nfa_accept_samples_generic_hw_indices_samples_write
nfa_accept_samples_generic_hw_indices_samples_write #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_AWUSER_WIDTH ( C_AWUSER_WIDTH ),
.C_WUSER_WIDTH ( C_WUSER_WIDTH ),
.C_BUSER_WIDTH ( C_BUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_write (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.AWID ( AWID ),
.AWADDR ( AWADDR ),
.AWLEN ( AWLEN ),
.AWSIZE ( AWSIZE ),
.AWBURST ( AWBURST ),
.AWLOCK ( AWLOCK ),
.AWCACHE ( AWCACHE ),
.AWPROT ( AWPROT ),
.AWQOS ( AWQOS ),
.AWUSER ( AWUSER ),
.AWVALID ( AWVALID ),
.AWREADY ( AWREADY ),
.WDATA ( WDATA ),
.WSTRB ( WSTRB ),
.WLAST ( WLAST ),
.WUSER ( WUSER ),
.WVALID ( WVALID ),
.WREADY ( WREADY ),
.BID ( BID ),
.BRESP ( BRESP ),
.BUSER ( BUSER ),
.BVALID ( BVALID ),
.BREADY ( BREADY ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data )
);
// nfa_accept_samples_generic_hw_indices_samples_read
nfa_accept_samples_generic_hw_indices_samples_read #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_ARUSER_WIDTH ( C_ARUSER_WIDTH ),
.C_RUSER_WIDTH ( C_RUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_read (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.ARID ( ARID ),
.ARADDR ( ARADDR ),
.ARLEN ( ARLEN ),
.ARSIZE ( ARSIZE ),
.ARBURST ( ARBURST ),
.ARLOCK ( ARLOCK ),
.ARCACHE ( ARCACHE ),
.ARPROT ( ARPROT ),
.ARQOS ( ARQOS ),
.ARUSER ( ARUSER ),
.ARVALID ( ARVALID ),
.ARREADY ( ARREADY ),
.RID ( RID ),
.RDATA ( RDATA ),
.RRESP ( RRESP ),
.RLAST ( RLAST ),
.RUSER ( RUSER ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length ),
.USER_datain ( USER_datain ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.USER_rsp_read ( USER_rsp_read )
);
//------------------------Body---------------------------
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_request_preprocessor/*{{{*/
#(parameter
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// user ports
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
// write request
input wire write_ready,
output wire write_valid,
output wire [31:0] write_address,
output wire [31:0] write_length,
output wire [C_USER_DATA_WIDTH-1:0] write_data,
// read request
input wire read_ready,
output wire read_valid,
output wire [31:0] read_address,
output wire [31:0] read_length
);
//------------------------Parameter----------------------
localparam
REQUEST_WIDTH = 1 + 32 + 32 + C_USER_DATA_WIDTH,
MAX_REQUEST = 32;
//------------------------Local signal-------------------
// request fifo
wire req_empty_n;
wire req_full_n;
wire req_rdreq;
wire req_wrreq;
wire [REQUEST_WIDTH-1:0] req_data;
wire [REQUEST_WIDTH-1:0] req_q;
wire [31:0] tmp_size;
wire tmp_type; // 0 - read, 1 - write
wire [31:0] tmp_address; // start address of read/write request
wire [31:0] tmp_length; // length of read/write request
wire [C_USER_DATA_WIDTH-1:0] tmp_data; // data of write request
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_samples_fifo
nfa_accept_samples_generic_hw_indices_samples_fifo #(
.DATA_BITS ( REQUEST_WIDTH ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) req_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( req_empty_n ),
.full_n ( req_full_n ),
.rdreq ( req_rdreq ),
.wrreq ( req_wrreq ),
.q ( req_q ),
.data ( req_data )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++user ports+++++++++++++++++++++
assign USER_req_full_n = req_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
assign write_valid = req_empty_n & tmp_type;
assign write_address = tmp_address;
assign write_length = tmp_length;
assign write_data = tmp_data;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_valid = req_empty_n & ~tmp_type;
assign read_address = tmp_address;
assign read_length = tmp_length;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++request fifo+++++++++++++++++++
assign req_rdreq = (read_valid & read_ready) | (write_valid & write_ready);
assign req_wrreq = USER_req_write;
assign req_data = {USER_req_din, USER_address, tmp_size, USER_dataout};
assign tmp_size = (USER_size==1'b0)? 1'b1 : USER_size;
assign tmp_type = req_q[REQUEST_WIDTH-1];
assign tmp_address = req_q[C_USER_DATA_WIDTH+63:C_USER_DATA_WIDTH+32];
assign tmp_length = req_q[C_USER_DATA_WIDTH+31:C_USER_DATA_WIDTH];
assign tmp_data = req_q[C_USER_DATA_WIDTH-1:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_write/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// write request
output wire write_ready,
input wire write_valid,
input wire [31:0] write_address,
input wire [31:0] write_length,
input wire [C_USER_DATA_WIDTH-1:0] write_data
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_BYTES = USER_DATA_BYTES > BUS_DATA_BYTES?
USER_DATA_BYTES : BUS_DATA_BYTES,
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
DATA = 4'd3,
LOOP = 4'd4;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg enough_data;
reg [DATA_BUF_BYTES*8-1:0] data_buf;
reg [DATA_BUF_BYTES-1:0] data_valid;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
reg [BUS_ADDR_ALIGN-1:0] tmp_bytes;
reg [BUS_ADDR_ALIGN-1:0] head_bytes;
reg [BUS_ADDR_ALIGN-1:0] tail_bytes;
reg add_head;
reg add_tail;
reg first_beat;
reg last_beat;
// axi4 bus
wire [BUS_DATA_BYTES-1:0] wstrb0;
wire [BUS_DATA_BYTES-1:0] wstrb1;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (write_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (AWREADY)
next = DATA;
else
next = ADDR;
DATA:
if (WVALID && WREADY && loop_beats==1'b1)
next = LOOP;
else
next = DATA;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (write_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && AWREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
len_buf <= write_length - 1'b1;
else if (write_ready && write_valid)
len_buf <= len_buf - 1'b1;
end
// enough_data
always @(posedge ACLK) begin
if (state==IDLE && write_valid) begin
if (write_length == 1'b1)
enough_data <= 1'b1;
else
enough_data <= 1'b0;
end
else if (write_ready && write_valid && len_buf==1'b1)
enough_data <= 1'b1;
end
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : wide_to_narrow
assign wstrb0 = {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= write_data;
else if (WREADY & WVALID)
data_buf <= data_buf >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (write_ready & write_valid)
data_valid <= {DATA_BUF_BYTES{1'b1}};
else if (WREADY & WVALID)
data_valid <= data_valid >> BUS_DATA_BYTES;
end
// tmp_bytes, head_bytes, tail_bytes, add_head, add_tail
// first_beat, last_beat
always @(*) begin
// these signals are useless if user data width is
// greater than bus data width
tmp_bytes = 1'b0;
head_bytes = 1'b0;
tail_bytes = 1'b0;
add_head = 1'b0;
add_tail = 1'b0;
first_beat = 1'b0;
last_beat = 1'b0;
end
end
else begin : narrow_to_wide
assign wstrb0 = first_beat? {BUS_DATA_BYTES{1'b1}} << head_bytes : {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = last_beat? {BUS_DATA_BYTES{1'b1}} >> tail_bytes : {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= {write_data, data_buf} >> USER_DATA_WIDTH;
else if (state==DATA && add_tail)
data_buf <= data_buf >> (tail_bytes * 8);
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (WREADY & WVALID)
data_valid <= {USER_DATA_BYTES{write_ready & write_valid}} << (DATA_BUF_BYTES-USER_DATA_BYTES);
else if (write_ready & write_valid)
data_valid <= {{USER_DATA_BYTES{1'b1}}, data_valid} >> USER_DATA_BYTES;
else if (add_head)
data_valid <= (data_valid >> head_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> head_bytes);
else if (state==DATA && add_tail)
data_valid <= (data_valid >> tail_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> tail_bytes);
end
// tmp_bytes
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
tmp_bytes <= write_length[BUS_ADDR_ALIGN-1:0] << USER_ADDR_ALIGN;
end
// head_bytes
always @(posedge ACLK) begin
if (state==PREP)
head_bytes <= addr_buf[BUS_ADDR_ALIGN-1:0];
end
// tail_bytes
always @(posedge ACLK) begin
if (state==PREP)
tail_bytes <= BUS_DATA_BYTES - addr_buf[BUS_ADDR_ALIGN-1:0] - tmp_bytes;
end
// add_head
always @(posedge ACLK) begin
if (state==PREP)
add_head <= 1'b1;
else
add_head <= 1'b0;
end
// add_tail
always @(posedge ACLK) begin
if (write_ready && write_valid && (write_length== 1'b1 || len_buf==1'b1))
add_tail <= 1'b1;
else if (state==DATA)
add_tail <= 1'b0;
end
// first_beat
always @(posedge ACLK) begin
if (state==PREP)
first_beat <= 1'b1;
else if (WREADY & WVALID)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if ((state==PREP || state==LOOP) && total_beats==1'b1)
last_beat <= 1'b1;
else if (WREADY & WVALID) begin
if (total_beats==1'b0 && loop_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end
endgenerate
// total_beats
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
total_beats <= ((write_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && AWREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
else if (WVALID & WREADY)
loop_beats <= loop_beats - 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi4 bus+++++++++++++++++++++++
// write address channel
assign AWID = 1'b0;
assign AWADDR = addr_buf;
assign AWLEN = loop_beats - 1'b1;
assign AWSIZE = BUS_ADDR_ALIGN[2:0];
assign AWBURST = 2'b01;
assign AWLOCK = 2'b00;
assign AWCACHE = C_CACHE_VALUE;
assign AWPROT = C_PROT_VALUE;
assign AWQOS = 4'b0000;
assign AWUSER = C_USER_VALUE;
assign AWVALID = (state==ADDR);
// write data channel
assign WDATA = data_buf[BUS_DATA_WIDTH-1:0];
assign WSTRB = wstrb0 & wstrb1;
assign WLAST = WVALID & (loop_beats==1'b1);
assign WUSER = C_USER_VALUE;
assign WVALID = (state==DATA) & data_valid[0];
// write response channel
assign BREADY = 1'b1; // we don't handle write response
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
generate
if (USER_DATA_BYTES <= BUS_DATA_BYTES) begin : gen_write_ready_0
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(~data_valid[0] | WREADY));
end
else begin : gen_write_ready_1
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(data_valid[DATA_BUF_BYTES-1:BUS_DATA_BYTES]==1'b0) &
(~data_valid[0] | WREADY));
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_read/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_ARUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// read request
output wire read_ready,
input wire read_valid,
input wire [31:0] read_address,
input wire [31:0] read_length,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
LOOP = 4'd3;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
// data align
wire align_ready;
wire align_valid;
wire [31:0] align_beats;
wire [31:0] align_address;
wire [31:0] align_length;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_samples_read_data_align
nfa_accept_samples_generic_hw_indices_samples_read_data_align #(
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) data_align (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.RDATA ( RDATA ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.USER_datain ( USER_datain ),
.USER_rsp_read ( USER_rsp_read ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.align_ready ( align_ready ),
.align_valid ( align_valid ),
.align_beats ( align_beats ),
.align_address ( align_address ),
.align_length ( align_length )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (align_ready & read_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (ARREADY)
next = LOOP;
else
next = ADDR;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (read_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && ARREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
len_buf <= read_length;
end
// total_beats
always @(posedge ACLK) begin
if (read_ready & read_valid)
total_beats <= ((read_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && ARREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read address channel+++++++++++
assign ARID = 1'b0;
assign ARADDR = addr_buf;
assign ARLEN = loop_beats - 1'b1;
assign ARSIZE = BUS_ADDR_ALIGN[2:0];
assign ARBURST = 2'b01;
assign ARLOCK = 2'b00;
assign ARCACHE = C_CACHE_VALUE;
assign ARPROT = C_PROT_VALUE;
assign ARQOS = 4'b0000;
assign ARUSER = C_USER_VALUE;
assign ARVALID = (state==ADDR);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++data align+++++++++++++++++++++
assign align_valid = (state==PREP);
assign align_beats = total_beats;
assign align_address = addr_buf;
assign align_length = len_buf;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_ready = (state==IDLE) & align_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_read_data_align/*{{{*/
#(parameter
C_DATA_WIDTH = 32,
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read data channel
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read,
// data align
output wire align_ready,
input wire align_valid,
input wire [31:0] align_beats,
input wire [31:0] align_address,
input wire [31:0] align_length
);
//------------------------Parameter----------------------
localparam
DATA_FIFO_DEPTH = 32,
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_WIDTH = USER_DATA_WIDTH > BUS_DATA_WIDTH?
USER_DATA_WIDTH : BUS_DATA_WIDTH,
DATA_VALID_BITS = USER_DATA_BYTES > BUS_DATA_BYTES ?
USER_DATA_BYTES / BUS_DATA_BYTES :
BUS_DATA_BYTES / USER_DATA_BYTES;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg [DATA_BUF_WIDTH-1:0] data_buf;
reg [DATA_VALID_BITS-1:0] data_valid;
reg [31:0] total_beats;
reg ready_buf;
wire [BUS_DATA_WIDTH-1:0] rs0_data;
wire rs0_valid;
wire rs0_ready;
wire fifo_empty_n;
wire fifo_full_n;
wire fifo_rdreq;
wire fifo_wrreq;
wire [C_USER_DATA_WIDTH-1:0] fifo_q;
wire [C_USER_DATA_WIDTH-1:0] fifo_data;
wire fifo_push;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_indices_samples_reg_slice
nfa_accept_samples_generic_hw_indices_samples_reg_slice #(
.N ( BUS_DATA_WIDTH )
) rs0 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( RDATA ),
.s_valid ( RVALID ),
.s_ready ( RREADY ),
.m_data ( rs0_data ),
.m_valid ( rs0_valid ),
.m_ready ( rs0_ready )
);
// nfa_accept_samples_generic_hw_indices_samples_fifo
nfa_accept_samples_generic_hw_indices_samples_fifo #(
.DATA_BITS ( C_USER_DATA_WIDTH ),
.DEPTH ( DATA_FIFO_DEPTH ),
.DEPTH_BITS ( log2(DATA_FIFO_DEPTH) )
) data_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( fifo_empty_n ),
.full_n ( fifo_full_n ),
.rdreq ( fifo_rdreq ),
.wrreq ( fifo_wrreq ),
.q ( fifo_q ),
.data ( fifo_data )
);
// nfa_accept_samples_generic_hw_indices_samples_reg_slice
nfa_accept_samples_generic_hw_indices_samples_reg_slice #(
.N ( C_USER_DATA_WIDTH )
) rs1 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( fifo_q ),
.s_valid ( fifo_empty_n ),
.s_ready ( fifo_rdreq ),
.m_data ( USER_datain ),
.m_valid ( USER_rsp_empty_n ),
.m_ready ( USER_rsp_read )
);
//------------------------Body---------------------------
assign fifo_data = data_buf[C_USER_DATA_WIDTH-1:0];
assign fifo_wrreq = data_valid[0];
assign fifo_push = fifo_full_n & fifo_wrreq;
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : narrow_to_wide
/*
* user data width is greater than or equal to bus data width
* so all bytes of bus data are valid
*/
assign align_ready = 1'b1;
assign rs0_ready = ~align_valid & ready_buf & (~data_valid[0] | fifo_push);
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= {rs0_data, data_buf} >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (fifo_push)
data_valid <= (rs0_ready & rs0_valid) << (DATA_VALID_BITS-1);
else if (rs0_ready & rs0_valid)
data_valid <= {1'b1, data_valid} >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (~ARESETN)
total_beats <= 1'b0;
else if (align_valid)
total_beats <= total_beats + align_beats; // may overflow
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (align_valid)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
end // end of narrow_to_wide
else begin : wide_to_narrow
/*
* user data width is less than bus data width
* so we have to remove the padding bytes
*/
localparam
PADDING_BITS = log2(DATA_VALID_BITS),
MAX_REQUEST = 32,
DATA_BITS = PADDING_BITS * 2 + 32;
wire [31:0] end_address;
wire [PADDING_BITS-1:0] head_tmp;
wire [PADDING_BITS-1:0] tail_tmp;
reg [PADDING_BITS-1:0] head_padding;
reg [PADDING_BITS-1:0] tail_padding;
reg first_beat;
reg last_beat;
wire request_fifo_empty_n;
wire request_fifo_full_n;
wire request_fifo_rdreq;
wire request_fifo_wrreq;
wire [DATA_BITS-1:0] request_fifo_q;
wire [DATA_BITS-1:0] request_fifo_data;
// nfa_accept_samples_generic_hw_indices_samples_fifo
nfa_accept_samples_generic_hw_indices_samples_fifo #(
.DATA_BITS ( DATA_BITS ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) request_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( request_fifo_empty_n ),
.full_n ( request_fifo_full_n ),
.rdreq ( request_fifo_rdreq ),
.wrreq ( request_fifo_wrreq ),
.q ( request_fifo_q ),
.data ( request_fifo_data )
);
assign align_ready = request_fifo_full_n;
assign rs0_ready = ready_buf & (data_valid==1'b0 || (data_valid==1'b1 && fifo_push));
assign end_address = align_address + align_length * USER_DATA_BYTES;
assign head_tmp = align_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN];
assign tail_tmp = ~end_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN] + 1'b1;
assign request_fifo_rdreq = request_fifo_empty_n & ~ready_buf;
assign request_fifo_wrreq = align_valid;
assign request_fifo_data = {head_tmp, tail_tmp, align_beats};
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= rs0_data >> (first_beat? head_padding * USER_DATA_WIDTH : 0);
else if (fifo_push)
data_buf <= data_buf >> USER_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (rs0_ready & rs0_valid)
data_valid <= ({DATA_VALID_BITS{1'b1}} >> (last_beat? tail_padding : 0))
>> (first_beat? head_padding : 0);
else if (fifo_push)
data_valid <= data_valid >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (request_fifo_rdreq)
total_beats <= request_fifo_q[31:0];
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (request_fifo_rdreq)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
// head_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
head_padding <= request_fifo_q[31+PADDING_BITS*2:32+PADDING_BITS];
end
// tail_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
tail_padding <= request_fifo_q[31+PADDING_BITS:32];
end
// first_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq)
first_beat <= 1'b1;
else if (rs0_ready & rs0_valid)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq && request_fifo_q[31:0]==1'b1)
last_beat <= 1'b1;
else if (rs0_ready & rs0_valid) begin
if (total_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end // end of wide_to_narrow
endgenerate
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_fifo/*{{{*/
#(parameter
DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
)(
input wire sclk,
input wire reset_n,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output wire [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
reg [DEPTH_BITS-1:0] pout;
reg [DATA_BITS-1:0] mem[0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = empty_n & rdreq;
assign q = mem[pout];
// empty_n
always @(posedge sclk) begin
if (~reset_n)
empty_n <= 1'b0;
else if (push)
empty_n <= 1'b1;
else if (~push && pop && pout == 1'b0)
empty_n <= 1'b0;
end
// full_n
always @(posedge sclk) begin
if (~reset_n)
full_n <= 1'b1;
else if (rdreq)
full_n <= 1'b1;
else if (push && ~pop && pout == DEPTH - 2)
full_n <= 1'b0;
end
// pout
always @(posedge sclk) begin
if (~reset_n)
pout <= 1'b0;
else if (push & ~pop & empty_n)
pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0)
pout <= pout - 1'b1;
end
integer i;
always @(posedge sclk) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_indices_samples_reg_slice/*{{{*/
#(parameter
N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset_n,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [1:0] state;
reg [1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2)
data_p1 <= data_p2;
else
data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (~reset_n)
s_ready_t <= 1'b0;
else if (state == ZERO)
s_ready_t <= 1'b1;
else if (state == ONE && next == TWO)
s_ready_t <= 1'b0;
else if (state == TWO && next == ONE)
s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (~reset_n)
state <= ZERO;
else
state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready)
next = ONE;
else
next = ZERO;
ONE:
if (~s_valid & m_ready)
next = ZERO;
else if (s_valid & ~m_ready)
next = TWO;
else
next = ONE;
TWO:
if (m_ready)
next = ONE;
else
next = TWO;
default:
next = ZERO;
endcase
end
endmodule/*}}}*/
// vim:ts=4 sw=4 et fdm=marker:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_FUNCTIONAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
//
// This implements a 4096:1 mux via two stages of 64:1 muxing.
// change these two parameters to see the speed differences
//`define DATA_WIDTH 12
//`define MUX2_SIZE 32
`define DATA_WIDTH 2
`define MUX2_SIZE 8
// if you change these, then the testbench will break
`define ADDR_WIDTH 12
`define MUX1_SIZE 64
// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
// End of automatics
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
reg [`ADDR_WIDTH-1:0] addr;
// Mux: takes in addr and datai and outputs datao
mux4096 mux4096 (/*AUTOINST*/
// Outputs
.datao (datao[`DATA_WIDTH-1:0]),
// Inputs
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
.addr (addr[`ADDR_WIDTH-1:0]));
// calculate what the answer should be from datai. This is bit
// tricky given the way datai gets sliced. datai is in bit
// planes where all the LSBs are contiguous and then the next bit.
reg [`DATA_WIDTH-1:0] datao_check;
integer j;
always @(datai or addr) begin
for(j=0;j<`DATA_WIDTH;j=j+1) begin
/* verilator lint_off WIDTH */
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
/* verilator lint_on WIDTH */
end
end
// Run the test loop. This just increments the address
integer i, result;
always @ (posedge clk) begin
// initial the input data with random values
if (addr == 0) begin
result = 1;
datai = 0;
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
/* verilator lint_off WIDTH */
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
/* verilator lint_on WIDTH */
end
end
addr <= addr + 1;
if (datao_check != datao) begin
result = 0;
$stop;
end
$write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao);
// only run the first 10 addresses for now
if (addr > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module mux4096
(input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output [`DATA_WIDTH-1:0] datao
);
// DATA_WIDTH instantiations of mux4096_1bit
mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0]
(.addr(addr),
.datai(datai),
.datao(datao)
);
endmodule
module mux4096_1bit
(input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output datao
);
// address decoding
wire [3:0] A = (4'b1) << addr[1:0];
wire [3:0] B = (4'b1) << addr[3:2];
wire [3:0] C = (4'b1) << addr[5:4];
wire [3:0] D = (4'b1) << addr[7:6];
wire [3:0] E = (4'b1) << addr[9:8];
wire [3:0] F = (4'b1) << addr[11:10];
wire [`MUX2_SIZE-1:0] data0;
// DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64
// first stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0]
(.A(A),
.B(B),
.C(C),
.datai(datai),
.datao(data0));
// DATA_WIDTH*MUX2_SIZE instantiations of mux64
// second stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2
(.A(D),
.B(E),
.C(F),
.datai(data0),
.datao(datao));
endmodule
module mux64
#(parameter MUX_SIZE=64)
(input [3:0] A,
input [3:0] B,
input [3:0] C,
input [MUX_SIZE-1:0] datai,
output datao
);
wire [63:0] colSelA = { 16{ A[3:0] }};
wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}};
wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
wire [MUX_SIZE-1:0] data_bus;
// Note each of these becomes a separate wire.
//.colSelA(colSelA[MUX_SIZE-1:0]),
//.colSelB(colSelB[MUX_SIZE-1:0]),
//.colSelC(colSelC[MUX_SIZE-1:0]),
drv drv[MUX_SIZE-1:0]
(.colSelA(colSelA[MUX_SIZE-1:0]),
.colSelB(colSelB[MUX_SIZE-1:0]),
.colSelC(colSelC[MUX_SIZE-1:0]),
.datai(datai),
.datao(data_bus)
);
assign datao = |data_bus;
endmodule
module drv
(input colSelA,
input colSelB,
input colSelC,
input datai,
output datao
);
assign datao = colSelC & colSelB & colSelA & datai;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:19:08 12/01/2010
// Design Name:
// Module Name: sd_dma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sd_dma(
input [3:0] SD_DAT,
inout SD_CLK,
input CLK,
input SD_DMA_EN,
output SD_DMA_STATUS,
output SD_DMA_SRAM_WE,
output SD_DMA_NEXTADDR,
output [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_PARTIAL,
input [10:0] SD_DMA_PARTIAL_START,
input [10:0] SD_DMA_PARTIAL_END,
input SD_DMA_START_MID_BLOCK,
input SD_DMA_END_MID_BLOCK,
output [10:0] DBG_cyclecnt,
output [2:0] DBG_clkcnt
);
reg [10:0] SD_DMA_STARTr;
reg [10:0] SD_DMA_ENDr;
reg SD_DMA_PARTIALr;
always @(posedge CLK) SD_DMA_PARTIALr <= SD_DMA_PARTIAL;
reg SD_DMA_DONEr;
reg[1:0] SD_DMA_DONEr2;
initial begin
SD_DMA_DONEr2 = 2'b00;
SD_DMA_DONEr = 1'b0;
end
always @(posedge CLK) SD_DMA_DONEr2 <= {SD_DMA_DONEr2[0], SD_DMA_DONEr};
wire SD_DMA_DONE_rising = (SD_DMA_DONEr2[1:0] == 2'b01);
reg [1:0] SD_DMA_ENr;
initial SD_DMA_ENr = 2'b00;
always @(posedge CLK) SD_DMA_ENr <= {SD_DMA_ENr[0], SD_DMA_EN};
wire SD_DMA_EN_rising = (SD_DMA_ENr [1:0] == 2'b01);
reg SD_DMA_STATUSr;
assign SD_DMA_STATUS = SD_DMA_STATUSr;
// we need 1042 cycles (startbit + 1024 nibbles + 16 crc + stopbit)
reg [10:0] cyclecnt;
initial cyclecnt = 11'd0;
reg SD_DMA_SRAM_WEr;
initial SD_DMA_SRAM_WEr = 1'b1;
assign SD_DMA_SRAM_WE = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_SRAM_WEr : 1'b1;
reg SD_DMA_NEXTADDRr;
assign SD_DMA_NEXTADDR = (cyclecnt < 1025 && SD_DMA_STATUSr) ? SD_DMA_NEXTADDRr : 1'b0;
reg[7:0] SD_DMA_SRAM_DATAr;
assign SD_DMA_SRAM_DATA = SD_DMA_SRAM_DATAr;
// we have 4 internal cycles per SD clock, 8 per RAM byte write
reg [2:0] clkcnt;
initial clkcnt = 3'b000;
reg [1:0] SD_CLKr;
initial SD_CLKr = 3'b111;
always @(posedge CLK)
if(SD_DMA_EN_rising) SD_CLKr <= 3'b111;
else SD_CLKr <= {SD_CLKr[0], clkcnt[1]};
assign SD_CLK = SD_DMA_STATUSr ? SD_CLKr[1] : 1'bZ;
always @(posedge CLK) begin
if(SD_DMA_EN_rising) begin
SD_DMA_STATUSr <= 1'b1;
SD_DMA_STARTr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_START : 11'h0);
SD_DMA_ENDr <= (SD_DMA_PARTIALr ? SD_DMA_PARTIAL_END : 11'd1024);
end
else if (SD_DMA_DONE_rising) SD_DMA_STATUSr <= 1'b0;
end
always @(posedge CLK) begin
if(cyclecnt == 1042
|| ((SD_DMA_END_MID_BLOCK & SD_DMA_PARTIALr) && cyclecnt == SD_DMA_PARTIAL_END))
SD_DMA_DONEr <= 1;
else SD_DMA_DONEr <= 0;
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising || !SD_DMA_STATUSr) begin
clkcnt <= 0;
end else begin
if(SD_DMA_STATUSr) begin
clkcnt <= clkcnt + 1;
end
end
end
always @(posedge CLK) begin
if(SD_DMA_EN_rising)
cyclecnt <= (SD_DMA_PARTIALr && SD_DMA_START_MID_BLOCK) ? SD_DMA_PARTIAL_START : 0;
else if(!SD_DMA_STATUSr) cyclecnt <= 0;
else if(clkcnt[1:0] == 2'b10) cyclecnt <= cyclecnt + 1;
end
// we have 8 clk cycles to complete one RAM write
// (4 clk cycles per SD_CLK; 2 SD_CLK cycles per byte)
always @(posedge CLK) begin
if(SD_DMA_STATUSr) begin
case(clkcnt[2:0])
3'h0: begin
SD_DMA_SRAM_DATAr[7:4] <= SD_DAT;
if(cyclecnt>SD_DMA_STARTr && cyclecnt <= SD_DMA_ENDr) SD_DMA_NEXTADDRr <= 1'b1;
end
3'h1: begin
SD_DMA_NEXTADDRr <= 1'b0;
end
3'h2: if(cyclecnt>=SD_DMA_STARTr && cyclecnt < SD_DMA_ENDr) SD_DMA_SRAM_WEr <= 1'b0;
// 3'h3:
3'h4:
SD_DMA_SRAM_DATAr[3:0] <= SD_DAT;
// 3'h5:
// 3'h6:
3'h7:
SD_DMA_SRAM_WEr <= 1'b1;
endcase
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vinterp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx_q,
input [16:0] diff_cx_r,
input diff_cy_positive,
input [16:0] diff_cy_q,
input [16:0] diff_cy_r,
input diff_dx_positive,
input [16:0] diff_dx_q,
input [16:0] diff_dx_r,
input diff_dy_positive,
input [16:0] diff_dy_q,
input [16:0] diff_dy_r,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x,
output reg signed [11:0] y,
output signed [17:0] tsx,
output signed [17:0] tsy,
output signed [17:0] tex,
output signed [17:0] tey
);
reg load;
reg next_point;
always @(posedge sys_clk) begin
if(load)
x <= drx;
end
/* Interpolators */
tmu2_geninterp18 i_cx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ax),
.positive(diff_cx_positive),
.q(diff_cx_q),
.r(diff_cx_r),
.divisor({6'd0, dst_squareh}),
.o(tsx)
);
tmu2_geninterp18 i_cy(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ay),
.positive(diff_cy_positive),
.q(diff_cy_q),
.r(diff_cy_r),
.divisor({6'd0, dst_squareh}),
.o(tsy)
);
tmu2_geninterp18 i_bx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(bx),
.positive(diff_dx_positive),
.q(diff_dx_q),
.r(diff_dx_r),
.divisor({6'd0, dst_squareh}),
.o(tex)
);
tmu2_geninterp18 i_by(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(by),
.positive(diff_dy_positive),
.q(diff_dy_q),
.r(diff_dy_r),
.divisor({6'd0, dst_squareh}),
.o(tey)
);
/* y datapath */
always @(posedge sys_clk) begin
if(load)
y <= dry;
else if(next_point)
y <= y + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if(load)
remaining_points <= dst_squareh - 11'd1;
else if(next_point)
remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case(state)
IDLE: begin
if(pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if(pipe_ack_i) begin
if(last_point)
next_state = IDLE;
else
next_point = 1'b1;
end
end
endcase
end
endmodule
|
// AGrises.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
// grey <= (R*8'd30 + G*8'd59 + B*8'd11)/8'd100;
`timescale 1 ps / 1 ps
module AGrises (
input clk,
input rst,
output [DATA_WIDTH-1:0] data_fifo_out,
output data_valid_fifo_out,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out,
input wire [DATA_WIDTH-1:0] data_fifo_in,
output read_fifo_in,
input wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in,
input start,
output endf
);
parameter DATA_WIDTH=32;
parameter FIFO_DEPTH = 256;
parameter FIFO_DEPTH_LOG2 = 8;
reg [1:0] stages;
wire stages_init;
reg [1:0] run;
reg [14:0] grey_aux;
reg [7:0] grey;
reg [18:0] pixel_counter;
always @ (posedge clk or posedge rst) begin
if (rst == 1) begin
run <= 0;
end else begin
if (start == 1) begin
run <= 1;
end else begin
if (pixel_counter == 0) begin
run <= 2;
end
if (endf == 1) begin
run <= 0;
end
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
pixel_counter <= 384000;
end else begin
if (data_valid_fifo_out) begin
pixel_counter <= pixel_counter - 1;
end
end
end
always @ (posedge clk) begin
if (start == 1) begin
stages <= 0;
end else begin
if (stages_init == 1) begin
stages <= 1;
grey_aux = data_fifo_in[23:16]*8'd30 + data_fifo_in[15:8]*8'd59 + data_fifo_in[7:0]*8'd11;
grey = 8'd2 * grey_aux[14:8];
grey = grey + (grey_aux[14:8] / 8'd2);
end else begin
if (stages == 1) begin
stages <= 2;
grey = grey + (grey_aux[14:8] / 8'd19);
grey = grey + (grey_aux[7:0] / 8'd64);
end else begin
if (stages == 2) begin
stages <= 0;
end
end
end
end
end
assign stages_init = ((usedw_fifo_in > 32)|(pixel_counter < 33)) & (usedw_fifo_out < FIFO_DEPTH) & (run == 1) & (stages == 0);
assign read_fifo_in = (run == 1) & (stages == 1);
assign data_fifo_out = {8'd0,{3{grey}}};
assign data_valid_fifo_out = (run == 1) & (stages == 2);
assign endf = (run == 2);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_dqs_found_cal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_TB_V
`define SKY130_FD_SC_HS__A311O_TB_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 B1 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B1 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B1 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_TB_V
|
//-----------------------------------------------------------------------------
// system_axi_interconnect_1_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi_interconnect_1_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [0:0] S_AXI_ARESET_OUT_N;
output [1:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [0:0] S_AXI_ACLK;
input [11:0] S_AXI_AWID;
input [31:0] S_AXI_AWADDR;
input [7:0] S_AXI_AWLEN;
input [2:0] S_AXI_AWSIZE;
input [1:0] S_AXI_AWBURST;
input [1:0] S_AXI_AWLOCK;
input [3:0] S_AXI_AWCACHE;
input [2:0] S_AXI_AWPROT;
input [3:0] S_AXI_AWQOS;
input [0:0] S_AXI_AWUSER;
input [0:0] S_AXI_AWVALID;
output [0:0] S_AXI_AWREADY;
input [11:0] S_AXI_WID;
input [31:0] S_AXI_WDATA;
input [3:0] S_AXI_WSTRB;
input [0:0] S_AXI_WLAST;
input [0:0] S_AXI_WUSER;
input [0:0] S_AXI_WVALID;
output [0:0] S_AXI_WREADY;
output [11:0] S_AXI_BID;
output [1:0] S_AXI_BRESP;
output [0:0] S_AXI_BUSER;
output [0:0] S_AXI_BVALID;
input [0:0] S_AXI_BREADY;
input [11:0] S_AXI_ARID;
input [31:0] S_AXI_ARADDR;
input [7:0] S_AXI_ARLEN;
input [2:0] S_AXI_ARSIZE;
input [1:0] S_AXI_ARBURST;
input [1:0] S_AXI_ARLOCK;
input [3:0] S_AXI_ARCACHE;
input [2:0] S_AXI_ARPROT;
input [3:0] S_AXI_ARQOS;
input [0:0] S_AXI_ARUSER;
input [0:0] S_AXI_ARVALID;
output [0:0] S_AXI_ARREADY;
output [11:0] S_AXI_RID;
output [31:0] S_AXI_RDATA;
output [1:0] S_AXI_RRESP;
output [0:0] S_AXI_RLAST;
output [0:0] S_AXI_RUSER;
output [0:0] S_AXI_RVALID;
input [0:0] S_AXI_RREADY;
input [1:0] M_AXI_ACLK;
output [23:0] M_AXI_AWID;
output [63:0] M_AXI_AWADDR;
output [15:0] M_AXI_AWLEN;
output [5:0] M_AXI_AWSIZE;
output [3:0] M_AXI_AWBURST;
output [3:0] M_AXI_AWLOCK;
output [7:0] M_AXI_AWCACHE;
output [5:0] M_AXI_AWPROT;
output [7:0] M_AXI_AWREGION;
output [7:0] M_AXI_AWQOS;
output [1:0] M_AXI_AWUSER;
output [1:0] M_AXI_AWVALID;
input [1:0] M_AXI_AWREADY;
output [23:0] M_AXI_WID;
output [63:0] M_AXI_WDATA;
output [7:0] M_AXI_WSTRB;
output [1:0] M_AXI_WLAST;
output [1:0] M_AXI_WUSER;
output [1:0] M_AXI_WVALID;
input [1:0] M_AXI_WREADY;
input [23:0] M_AXI_BID;
input [3:0] M_AXI_BRESP;
input [1:0] M_AXI_BUSER;
input [1:0] M_AXI_BVALID;
output [1:0] M_AXI_BREADY;
output [23:0] M_AXI_ARID;
output [63:0] M_AXI_ARADDR;
output [15:0] M_AXI_ARLEN;
output [5:0] M_AXI_ARSIZE;
output [3:0] M_AXI_ARBURST;
output [3:0] M_AXI_ARLOCK;
output [7:0] M_AXI_ARCACHE;
output [5:0] M_AXI_ARPROT;
output [7:0] M_AXI_ARREGION;
output [7:0] M_AXI_ARQOS;
output [1:0] M_AXI_ARUSER;
output [1:0] M_AXI_ARVALID;
input [1:0] M_AXI_ARREADY;
input [23:0] M_AXI_RID;
input [63:0] M_AXI_RDATA;
input [3:0] M_AXI_RRESP;
input [1:0] M_AXI_RLAST;
input [1:0] M_AXI_RUSER;
input [1:0] M_AXI_RVALID;
output [1:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [34:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [34:0] DEBUG_SR_SC_AWADDRCONTROL;
output [15:0] DEBUG_SR_SC_BRESP;
output [31:0] DEBUG_SR_SC_RDATA;
output [16:0] DEBUG_SR_SC_RDATACONTROL;
output [31:0] DEBUG_SR_SC_WDATA;
output [6:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [34:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [34:0] DEBUG_SC_SF_AWADDRCONTROL;
output [15:0] DEBUG_SC_SF_BRESP;
output [31:0] DEBUG_SC_SF_RDATA;
output [16:0] DEBUG_SC_SF_RDATACONTROL;
output [31:0] DEBUG_SC_SF_WDATA;
output [6:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [34:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [34:0] DEBUG_SF_CB_AWADDRCONTROL;
output [15:0] DEBUG_SF_CB_BRESP;
output [31:0] DEBUG_SF_CB_RDATA;
output [16:0] DEBUG_SF_CB_RDATACONTROL;
output [31:0] DEBUG_SF_CB_WDATA;
output [6:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [34:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [34:0] DEBUG_CB_MF_AWADDRCONTROL;
output [15:0] DEBUG_CB_MF_BRESP;
output [31:0] DEBUG_CB_MF_RDATA;
output [16:0] DEBUG_CB_MF_RDATACONTROL;
output [31:0] DEBUG_CB_MF_WDATA;
output [6:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [34:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [34:0] DEBUG_MF_MC_AWADDRCONTROL;
output [15:0] DEBUG_MF_MC_BRESP;
output [31:0] DEBUG_MF_MC_RDATA;
output [16:0] DEBUG_MF_MC_RDATACONTROL;
output [31:0] DEBUG_MF_MC_WDATA;
output [6:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [34:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [34:0] DEBUG_MC_MP_AWADDRCONTROL;
output [15:0] DEBUG_MC_MP_BRESP;
output [31:0] DEBUG_MC_MP_RDATA;
output [16:0] DEBUG_MC_MP_RDATACONTROL;
output [31:0] DEBUG_MC_MP_WDATA;
output [6:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [34:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [34:0] DEBUG_MP_MR_AWADDRCONTROL;
output [15:0] DEBUG_MP_MR_BRESP;
output [31:0] DEBUG_MP_MR_RDATA;
output [16:0] DEBUG_MP_MR_RDATACONTROL;
output [31:0] DEBUG_MP_MR_WDATA;
output [6:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "zynq" ),
.C_NUM_SLAVE_SLOTS ( 1 ),
.C_NUM_MASTER_SLOTS ( 2 ),
.C_AXI_ID_WIDTH ( 12 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 32 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_INTERCONNECT_DATA_WIDTH ( 32 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200000002 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000043000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000075c00000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004300ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000075c0ffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 100000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 1 ),
.C_AXI_ARUSER_WIDTH ( 1 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111110 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 0 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 1 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi_interconnect_1 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_MNC_getFT for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_MNC_getFT
// Module Name: NPCG_Toggle_MNC_getFT
// File Name: NPCG_Toggle_MNC_getFT.v
//
// Version: v1.0.0
//
// Description: Get feature execution FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_MNC_N_init
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
iWaySelect ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CASelect ,
oPM_CAData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
input [NumberOfWays - 1:0] iWaySelect ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
// FSM Parameters/Wires/Regs
localparam N_i_FSM_BIT = 6; // NAND initialization
localparam N_i_RESET = 6'b00_0001;
localparam N_i_READY = 6'b00_0010;
localparam N_i_00001 = 6'b00_0100; // capture, CAL start
localparam N_i_00002 = 6'b00_1000; // CA data
localparam N_i_00003 = 6'b01_0000; // Timer start ready, Timer Loop
localparam N_i_00004 = 6'b10_0000; // wait for request done
reg [N_i_FSM_BIT-1:0] r_N_i_cur_state ;
reg [N_i_FSM_BIT-1:0] r_N_i_nxt_state ;
// Internal Wires/Regs
reg [4:0] rSourceID ;
reg rCMDReady ;
reg [NumberOfWays - 1:0] rWaySelect ;
wire wLastStep ;
reg [7:0] rPM_PCommand ;
reg [2:0] rPM_PCommandOption ;
reg [15:0] rPM_NumOfData ;
reg rPM_CASelect ;
reg [7:0] rPM_CAData ;
wire wPCGStart ;
wire wCapture ;
wire wPMReady ;
wire wCALReady ;
wire wCALStart ;
wire wCALDone ;
wire wTMReady ;
wire wTMStart ;
wire wTMDone ;
reg [3:0] rTM_counter ;
wire wTM_LoopDone ;
// Control Signals
// Flow Contorl
assign wPCGStart = (iOpcode[5:0] == 6'b101100) & (iTargetID[4:0] == 5'b00101) & iCMDValid;
assign wCapture = (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_READY);
assign wPMReady = (iPM_Ready[5:0] == 6'b111111);
assign wCALReady = wPMReady;
assign wCALStart = wCALReady & rPM_PCommand[3];
assign wCALDone = iPM_LastStep[3];
assign wTMReady = wPMReady;
assign wTMStart = wTMReady & rPM_PCommand[0];
assign wTMDone = iPM_LastStep[0];
assign wTM_LoopDone = (rTM_counter[3:0] == 4'd10);
assign wLastStep = wTMDone & wTM_LoopDone & (r_N_i_cur_state[N_i_FSM_BIT-1:0] == N_i_00004);
// FSM: read STatus
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
r_N_i_cur_state <= N_i_RESET;
end else begin
r_N_i_cur_state <= r_N_i_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (r_N_i_cur_state)
N_i_RESET: begin
r_N_i_nxt_state <= N_i_READY;
end
N_i_READY: begin
r_N_i_nxt_state <= (wPCGStart)? N_i_00001:N_i_READY;
end
N_i_00001: begin
r_N_i_nxt_state <= (wCALStart)? N_i_00002:N_i_00001;
end
N_i_00002: begin
r_N_i_nxt_state <= N_i_00003;
end
N_i_00003: begin
r_N_i_nxt_state <= (wTM_LoopDone)? N_i_00004:N_i_00003;
end
N_i_00004: begin
r_N_i_nxt_state <= (wLastStep)? N_i_READY:N_i_00004;
end
default:
r_N_i_nxt_state <= N_i_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end else begin
case (r_N_i_nxt_state)
N_i_RESET: begin
rSourceID[4:0] <= 0;
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_READY: begin
rSourceID[4:0] <= 0;
rCMDReady <= 1;
rWaySelect[NumberOfWays - 1:0] <= 0;
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00001: begin
rSourceID[4:0] <= (wCapture)? iSourceID[4:0]:rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= (wCapture)? iWaySelect[NumberOfWays - 1:0]:rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_1000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 15'h0000;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= 0;
end
N_i_00002: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 0;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 1'b0;
rPM_CAData[7:0] <= 8'hFF;
rTM_counter[3:0] <= 4'b0001;
end
N_i_00003: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0001;
rPM_PCommandOption[2:0] <= 3'b001; // CE on
rPM_NumOfData[15:0] <= 16'd50000; // real condition
//rPM_NumOfData[15:0] <= 16'd5; // test condition
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= (wTMDone)? (rTM_counter[3:0] + 1'b1):(rTM_counter[3:0]);
end
N_i_00004: begin
rSourceID[4:0] <= rSourceID[4:0];
rCMDReady <= 0;
rWaySelect[NumberOfWays - 1:0] <= rWaySelect[NumberOfWays - 1:0];
rPM_PCommand[7:0] <= 8'b0000_0000;
rPM_PCommandOption[2:0] <= 0;
rPM_NumOfData[15:0] <= 0;
rPM_CASelect <= 0;
rPM_CAData[7:0] <= 0;
rTM_counter[3:0] <= rTM_counter[3:0];
end
endcase
end
end
// Output
assign oCMDReady = rCMDReady;
assign oStart = wPCGStart;
assign oLastStep = wLastStep;
assign oPM_PCommand[7:0] = rPM_PCommand[7:0];
assign oPM_PCommandOption[2:0] = rPM_PCommandOption[2:0];
assign oPM_TargetWay[NumberOfWays - 1:0] = rWaySelect[NumberOfWays - 1:0];
assign oPM_NumOfData[15:0] = rPM_NumOfData[15:0];
assign oPM_CASelect = rPM_CASelect;
assign oPM_CAData[7:0] = rPM_CAData[7:0];
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
module my_dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
module my_dffr_p (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffr_p_2 (
input d1,
input d2,
clk,
clr,
output reg q1,
output reg q2
);
always @(posedge clk or posedge clr)
if (clr) begin
q1 <= 1'b0;
q2 <= 1'b0;
end else begin
q1 <= d1;
q2 <= d2;
end
endmodule
module my_dffr_n (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffre_p (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffre_n (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffs_p (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffs_n (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffse_p (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1'b1;
else if (en) q <= d;
endmodule
module my_dffse_n (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1'b1;
else if (en) q <= d;
endmodule
module my_dffn (
input d,
clk,
output reg q
);
initial q <= 1'b0;
always @(negedge clk) q <= d;
endmodule
module my_dffnr_p (
input d,
clk,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffnr_n (
input d,
clk,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffns_p (
input d,
clk,
pre,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffns_n (
input d,
clk,
pre,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffsr_ppp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_pnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_ppn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_pnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_npp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_nnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_npn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_nnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsre_ppp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_ppn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffs_clk_p (
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffs_clk_n (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:51:48 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_internoc_ni_axi_master_0_0_stub.v
// Design : DemoInterconnect_internoc_ni_axi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "interface_axi_master_v1_0,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(if00_data_in, if00_load_in, if00_data_out,
if00_load_out, if00_send_done, if00_send_busy, m00_axi_awaddr, m00_axi_awprot,
m00_axi_awvalid, m00_axi_awready, m00_axi_wdata, m00_axi_wstrb, m00_axi_wvalid,
m00_axi_wready, m00_axi_bresp, m00_axi_bvalid, m00_axi_bready, m00_axi_araddr,
m00_axi_arprot, m00_axi_arvalid, m00_axi_arready, m00_axi_rdata, m00_axi_rresp,
m00_axi_rvalid, m00_axi_rready, m00_axi_aclk, m00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="if00_data_in[7:0],if00_load_in,if00_data_out[7:0],if00_load_out,if00_send_done,if00_send_busy,m00_axi_awaddr[31:0],m00_axi_awprot[2:0],m00_axi_awvalid,m00_axi_awready,m00_axi_wdata[31:0],m00_axi_wstrb[3:0],m00_axi_wvalid,m00_axi_wready,m00_axi_bresp[1:0],m00_axi_bvalid,m00_axi_bready,m00_axi_araddr[31:0],m00_axi_arprot[2:0],m00_axi_arvalid,m00_axi_arready,m00_axi_rdata[31:0],m00_axi_rresp[1:0],m00_axi_rvalid,m00_axi_rready,m00_axi_aclk,m00_axi_aresetn" */;
input [7:0]if00_data_in;
input if00_load_in;
output [7:0]if00_data_out;
output if00_load_out;
input if00_send_done;
input if00_send_busy;
output [31:0]m00_axi_awaddr;
output [2:0]m00_axi_awprot;
output m00_axi_awvalid;
input m00_axi_awready;
output [31:0]m00_axi_wdata;
output [3:0]m00_axi_wstrb;
output m00_axi_wvalid;
input m00_axi_wready;
input [1:0]m00_axi_bresp;
input m00_axi_bvalid;
output m00_axi_bready;
output [31:0]m00_axi_araddr;
output [2:0]m00_axi_arprot;
output m00_axi_arvalid;
input m00_axi_arready;
input [31:0]m00_axi_rdata;
input [1:0]m00_axi_rresp;
input m00_axi_rvalid;
output m00_axi_rready;
input m00_axi_aclk;
input m00_axi_aresetn;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate casex/endcase - label w/ X no default
module main ();
reg error;
reg [2:0] val1,val2;
reg [2:0] result ;
always @( val1 or val2)
casex (val1 & val2 )
3'b000: result = 0;
3'b0x1: result = 1 ;
3'b010: result = 2;
endcase
initial
begin
error = 0;
val1 = 3'b0;
val2 = 3'b0;
if(result !=0)
begin
$display("FAILED casex 3.9C - label w/ x: ");
error = 1;
end
val1 = 3'b001;
val2 = 3'b011;
if(result !=1)
begin
$display("FAILED casex 3.9C - label w/ x: ");
error = 1;
end
val1 = 3'b111; // Should get no-action - expr = 3'b011
if(result !=1)
begin
$display("FAILED casex 3.9C - label w/ x ");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 4427 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w64,
w63,
w252,
w315,
w256,
w257,
w4112,
w4427;
assign w1 = i_data0;
assign w252 = w63 << 2;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w315 = w63 + w252;
assign w4112 = w257 << 4;
assign w4427 = w315 + w4112;
assign w63 = w64 - w1;
assign w64 = w1 << 6;
assign o_data0 = w4427;
//multiplier_block area estimate = 7125.14888406029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_dma # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
input pcie_rx_cmd_wr_en,
input [33:0] pcie_rx_cmd_wr_data,
output pcie_rx_cmd_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [P_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n
);
wire w_pcie_rx_cmd_rd_en;
wire [33:0] w_pcie_rx_cmd_rd_data;
wire w_pcie_rx_cmd_empty_n;
wire w_pcie_tag_alloc;
wire [7:0] w_pcie_alloc_tag;
wire [9:4] w_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_pcie_rx_fifo_full_n;
wire w_fifo_wr_en;
wire [8:0] w_fifo_wr_addr;
wire [127:0] w_fifo_wr_data;
wire [9:0] w_rear_full_addr;
wire [9:0] w_rear_addr;
pcie_rx_cmd_fifo
pcie_rx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_rx_cmd_wr_en),
.wr_data (pcie_rx_cmd_wr_data),
.full_n (pcie_rx_cmd_full_n),
.rd_en (w_pcie_rx_cmd_rd_en),
.rd_data (w_pcie_rx_cmd_rd_data),
.empty_n (w_pcie_rx_cmd_empty_n)
);
pcie_rx_fifo
pcie_rx_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_fifo_wr_en),
.wr_addr (w_fifo_wr_addr),
.wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr),
.alloc_len (w_pcie_tag_alloc_len),
.full_n (w_pcie_rx_fifo_full_n),
.rd_clk (dma_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_rx_fifo_rd_en),
.rd_data (pcie_rx_fifo_rd_data),
.free_en (pcie_rx_fifo_free_en),
.free_len (pcie_rx_fifo_free_len),
.empty_n (pcie_rx_fifo_empty_n)
);
pcie_rx_tag
pcie_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_dma_fifo_tag),
.cpld_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_fifo_tag_last (cpld_dma_fifo_tag_last),
.fifo_wr_en (w_fifo_wr_en),
.fifo_wr_addr (w_fifo_wr_addr),
.fifo_wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr)
);
pcie_rx_req # (
.P_PCIE_DATA_WIDTH (P_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_rx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_rd_en (w_pcie_rx_cmd_rd_en),
.pcie_rx_cmd_rd_data (w_pcie_rx_cmd_rd_data),
.pcie_rx_cmd_empty_n (w_pcie_rx_cmd_empty_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.pcie_rx_fifo_full_n (w_pcie_rx_fifo_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack)
);
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// one-way bidirectional connection:
// altera message_off 10665
module acl_ic_slave_endpoint
#(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
parameter integer PIPELINE_RETURN_PATHS = 1, // 0|1
parameter integer WRP_FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer RRP_FIFO_DEPTH = 1, // > 0 (don't care if SLAVE_FIXED_LATENCY > 0)
parameter integer RRP_USE_LL_FIFO = 1, // 0|1
parameter integer SLAVE_FIXED_LATENCY = 0, // 0=not fixed latency, >0=# fixed latency cycles
// if >0 effectively RRP_FIFO_DEPTH=SLAVE_FIXED_LATENCY+1
parameter integer SEPARATE_READ_WRITE_STALLS = 0 // 0|1
)
(
input logic clock,
input logic resetn,
// Arbitrated master.
acl_arb_intf m_intf,
// Slave.
acl_arb_intf s_intf,
input logic s_readdatavalid,
input logic [DATA_W-1:0] s_readdata,
input logic s_writeack,
// Write return path.
acl_ic_wrp_intf wrp_intf,
// Read return path.
acl_ic_rrp_intf rrp_intf
);
logic wrp_stall, rrp_stall;
generate
if( SEPARATE_READ_WRITE_STALLS == 0 )
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall | wrp_stall )
begin
s_intf.req.read = 1'b0;
s_intf.req.write = 1'b0;
end
// Stall signals.
m_intf.stall = s_intf.stall | rrp_stall | wrp_stall;
end
end
else
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall )
s_intf.req.read = 1'b0;
if( wrp_stall )
s_intf.req.write = 1'b0;
// Stall signals.
m_intf.stall = s_intf.stall;
if( m_intf.req.request & m_intf.req.read & rrp_stall )
m_intf.stall = 1'b1;
if( m_intf.req.request & m_intf.req.write & wrp_stall )
m_intf.stall = 1'b1;
end
end
endgenerate
// Write return path.
acl_ic_slave_wrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(WRP_FIFO_DEPTH),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
wrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.wrp_intf( wrp_intf ),
.s_writeack( s_writeack ),
.stall( wrp_stall )
);
// Read return path.
acl_ic_slave_rrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(RRP_FIFO_DEPTH),
.USE_LL_FIFO(RRP_USE_LL_FIFO),
.SLAVE_FIXED_LATENCY(SLAVE_FIXED_LATENCY),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
rrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.s_readdatavalid( s_readdatavalid ),
.s_readdata( s_readdata ),
.rrp_intf( rrp_intf ),
.stall( rrp_stall )
);
endmodule
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Data cache implementation
Copyright (C) 2012-2013
Stefan Kristiansson <[email protected]>
Stefan Wallentowitz <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_dcache
#(
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
parameter OPTION_DCACHE_SET_WIDTH = 9,
parameter OPTION_DCACHE_WAYS = 2,
parameter OPTION_DCACHE_LIMIT_WIDTH = 32,
parameter OPTION_DCACHE_SNOOP = "NONE"
)
(
input clk,
input rst,
input dc_dbus_err_i,
input dc_enable_i,
input dc_access_i,
output refill_o,
output refill_req_o,
output refill_done_o,
// CPU Interface
output cpu_err_o,
output cpu_ack_o,
output reg [OPTION_OPERAND_WIDTH-1:0] cpu_dat_o,
input [OPTION_OPERAND_WIDTH-1:0] cpu_dat_i,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i,
input cpu_req_i,
input cpu_we_i,
input [3:0] cpu_bsel_i,
input refill_allowed,
input [OPTION_OPERAND_WIDTH-1:0] wradr_i,
input [OPTION_OPERAND_WIDTH-1:0] wrdat_i,
input we_i,
// Snoop address
input [31:0] snoop_adr_i,
// Snoop event in this cycle
input snoop_valid_i,
// Whether the snoop hit. If so, there will be no tag memory write
// this cycle. The LSU may need to stall the pipeline.
output snoop_hit_o,
// SPR interface
input [15:0] spr_bus_addr_i,
input spr_bus_we_i,
input spr_bus_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
output spr_bus_ack_o
);
// States
localparam IDLE = 5'b00001;
localparam READ = 5'b00010;
localparam WRITE = 5'b00100;
localparam REFILL = 5'b01000;
localparam INVALIDATE = 5'b10000;
// Address space in bytes for a way
localparam WAY_WIDTH = OPTION_DCACHE_BLOCK_WIDTH + OPTION_DCACHE_SET_WIDTH;
/*
* Tag memory layout
* +---------------------------------------------------------+
* (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag |
* +---------------------------------------------------------+
*/
// The tag is the part left of the index
localparam TAG_WIDTH = (OPTION_DCACHE_LIMIT_WIDTH - WAY_WIDTH);
// The tag memory contains entries with OPTION_DCACHE_WAYS parts of
// each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag.
localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1;
localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1;
// Additionally, the tag memory entry contains an LRU value. The
// width of this is 0 for OPTION_DCACHE_LIMIT_WIDTH==1
localparam TAG_LRU_WIDTH = OPTION_DCACHE_WAYS*(OPTION_DCACHE_WAYS-1) >> 1;
// We have signals for the LRU which are not used for one way
// caches. To avoid signal width [-1:0] this generates [0:0]
// vectors for them, which are removed automatically then.
localparam TAG_LRU_WIDTH_BITS = (OPTION_DCACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1;
// Compute the total sum of the entry elements
localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_DCACHE_WAYS + TAG_LRU_WIDTH;
// For convenience we define the position of the LRU in the tag
// memory entries
localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1;
localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1;
// FSM state signals
reg [4:0] state;
wire idle;
wire read;
wire write;
wire refill;
reg [WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] invalidate_adr;
wire [31:0] next_refill_adr;
reg [31:0] way_wr_dat;
wire refill_done;
wire refill_hit;
reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid;
reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r;
wire invalidate;
// The index we read and write from tag memory
wire [OPTION_DCACHE_SET_WIDTH-1:0] tag_rindex;
reg [OPTION_DCACHE_SET_WIDTH-1:0] tag_windex;
// The data from the tag memory
wire [TAGMEM_WIDTH-1:0] tag_dout;
wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out;
wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_DCACHE_WAYS-1:0];
// The data to the tag memory
wire [TAGMEM_WIDTH-1:0] tag_din;
reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in;
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_DCACHE_WAYS-1:0];
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save[OPTION_DCACHE_WAYS-1:0];
// Whether to write to the tag memory in this cycle
reg tag_we;
// This is the tag we need to write to the tag memory during refill
wire [TAG_WIDTH-1:0] tag_wtag;
// This is the tag we check against
wire [TAG_WIDTH-1:0] tag_tag;
// Access to the way memories
wire [WAY_WIDTH-3:0] way_raddr[OPTION_DCACHE_WAYS-1:0];
wire [WAY_WIDTH-3:0] way_waddr[OPTION_DCACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_DCACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_DCACHE_WAYS-1:0];
reg [OPTION_DCACHE_WAYS-1:0] way_we;
// Does any way hit?
wire hit;
wire [OPTION_DCACHE_WAYS-1:0] way_hit;
// This is the least recently used value before access the memory.
// Those are one hot encoded.
wire [OPTION_DCACHE_WAYS-1:0] lru;
// Register that stores the LRU value from lru
reg [OPTION_DCACHE_WAYS-1:0] tag_save_lru;
// The access vector to update the LRU history is the way that has
// a hit or is refilled. It is also one-hot encoded.
reg [OPTION_DCACHE_WAYS-1:0] access;
// The current LRU history as read from tag memory and the update
// value after we accessed it to write back to tag memory.
wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history;
wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history;
// Intermediate signals to ease debugging
wire [TAG_WIDTH-1:0] check_way_tag [OPTION_DCACHE_WAYS-1:0];
wire check_way_match [OPTION_DCACHE_WAYS-1:0];
wire check_way_valid [OPTION_DCACHE_WAYS-1:0];
reg write_pending;
// Extract index to read from snooped address
wire [OPTION_DCACHE_SET_WIDTH-1:0] snoop_index;
assign snoop_index = snoop_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
// Register that is high one cycle after the actual snoop event to
// drive the comparison
reg snoop_check;
// Register that stores the tag for one cycle
reg [TAG_WIDTH-1:0] snoop_tag;
// Also store the index for one cycle, for the succeeding write access
reg [OPTION_DCACHE_SET_WIDTH-1:0] snoop_windex;
// Snoop tag memory interface
// Data out of tag memory
wire [TAGMEM_WIDTH-1:0] snoop_dout;
// Each ways information in the tag memory
wire [TAGMEM_WAY_WIDTH-1:0] snoop_way_out [OPTION_DCACHE_WAYS-1:0];
// Each ways tag in the tag memory
wire [TAG_WIDTH-1:0] snoop_check_way_tag [OPTION_DCACHE_WAYS-1:0];
// Whether the tag matches the snoop tag
wire snoop_check_way_match [OPTION_DCACHE_WAYS-1:0];
// Whether the tag is valid
wire snoop_check_way_valid [OPTION_DCACHE_WAYS-1:0];
// Whether the way hits
wire [OPTION_DCACHE_WAYS-1:0] snoop_way_hit;
// Whether any way hits
wire snoop_hit;
assign snoop_hit_o = (OPTION_DCACHE_SNOOP != "NONE") ? snoop_hit : 0;
genvar i;
assign cpu_ack_o = ((read | refill) & hit & !write_pending |
refill_hit) & cpu_req_i & !snoop_hit;
assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
assign tag_tag = cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
assign tag_wtag = wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
generate
if (OPTION_DCACHE_WAYS >= 2) begin
// Multiplex the LRU history from and to tag memory
assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in;
assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
end
for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : ways
assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2];
assign way_waddr[i] = write ? cpu_adr_match_i[WAY_WIDTH-1:2] :
wradr_i[WAY_WIDTH-1:2];
assign way_din[i] = way_wr_dat;
// compare stored tag with incoming tag and check valid bit
assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0];
assign check_way_match[i] = (check_way_tag[i] == tag_tag);
assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID];
assign way_hit[i] = check_way_valid[i] & check_way_match[i];
// Multiplex the way entries in the tag memory
assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i];
assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
if (OPTION_DCACHE_SNOOP != "NONE") begin
// The same for the snoop tag memory
assign snoop_way_out[i] = snoop_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
assign snoop_check_way_tag[i] = snoop_way_out[i][TAG_WIDTH-1:0];
assign snoop_check_way_match[i] = (snoop_check_way_tag[i] == snoop_tag);
assign snoop_check_way_valid[i] = snoop_way_out[i][TAGMEM_WAY_VALID];
assign snoop_way_hit[i] = snoop_check_way_valid[i] & snoop_check_way_match[i];
end
end
endgenerate
assign hit = |way_hit;
assign snoop_hit = (OPTION_DCACHE_SNOOP != "NONE") &
|snoop_way_hit & snoop_check;
integer w0;
always @(*) begin
cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}};
// Put correct way on the data port
for (w0 = 0; w0 < OPTION_DCACHE_WAYS; w0 = w0 + 1) begin
if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin
cpu_dat_o = way_dout[w0];
end
end
end
assign next_refill_adr = (OPTION_DCACHE_BLOCK_WIDTH == 5) ?
{wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte
{wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte
assign refill_done_o = refill_done;
assign refill_done = refill_valid[next_refill_adr[OPTION_DCACHE_BLOCK_WIDTH-1:2]];
assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] &
cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1:
OPTION_DCACHE_BLOCK_WIDTH] ==
wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1:
OPTION_DCACHE_BLOCK_WIDTH] &
refill & !write_pending;
assign idle = (state == IDLE);
assign refill = (state == REFILL);
assign read = (state == READ);
assign write = (state == WRITE);
assign refill_o = refill;
assign refill_req_o = read & cpu_req_i & !hit & !write_pending & refill_allowed | refill;
/*
* SPR bus interface
*/
// The SPR interface is used to invalidate the cache blocks. When
// an invalidation is started, the respective entry in the tag
// memory is cleared. When another transfer is in progress, the
// handling is delayed until it is possible to serve it.
//
// The invalidation is acknowledged to the SPR bus, but the cycle
// is terminated by the core. We therefore need to hold the
// invalidate acknowledgement. Meanwhile we continuously write the
// tag memory which is no problem.
// Net that signals an acknowledgement
reg invalidate_ack;
// An invalidate request is either a block flush or a block invalidate
assign invalidate = spr_bus_stb_i & spr_bus_we_i &
(spr_bus_addr_i == `OR1K_SPR_DCBFR_ADDR |
spr_bus_addr_i == `OR1K_SPR_DCBIR_ADDR);
// Acknowledge to the SPR bus.
assign spr_bus_ack_o = invalidate_ack;
/*
* Cache FSM
* Starts in IDLE.
* State changes between READ and WRITE happens cpu_we_i is asserted or not.
* cpu_we_i is in sync with cpu_adr_i, so that means that it's the
* *upcoming* write that it is indicating. It only toggles for one cycle,
* so if we are busy doing something else when this signal comes
* (i.e. refilling) we assert the write_pending signal.
* cpu_req_i is in sync with cpu_adr_match_i, so it can be used to
* determined if a cache hit should cause a refill or if a write should
* really be executed.
*/
integer w1;
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
state <= IDLE;
write_pending <= 0;
end else if(dc_dbus_err_i) begin
state <= IDLE;
write_pending <= 0;
end else begin
if (cpu_we_i)
write_pending <= 1;
else if (!cpu_req_i)
write_pending <= 0;
refill_valid_r <= refill_valid;
if (snoop_valid_i) begin
//
// If there is a snoop event, we need to store this
// information. This happens independent of whether we
// have a snoop tag memory or not.
//
snoop_check <= 1;
snoop_windex <= snoop_index;
snoop_tag <= snoop_adr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
end else begin
snoop_check <= 0;
end
case (state)
IDLE: begin
if (invalidate) begin
// If there is an invalidation request
//
// Store address in invalidate_adr that is muxed to the tag
// memory write address
invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
// Change to invalidate state that actually accesses
// the tag memory
state <= INVALIDATE;
end else if (cpu_we_i | write_pending)
state <= WRITE;
else if (cpu_req_i)
state <= READ;
end
READ: begin
if (dc_access_i | cpu_we_i & dc_enable_i) begin
if (!hit & cpu_req_i & !write_pending & refill_allowed) begin
refill_valid <= 0;
refill_valid_r <= 0;
// Store the LRU information for correct replacement
// on refill. Always one when only one way.
tag_save_lru <= (OPTION_DCACHE_WAYS==1) | lru;
for (w1 = 0; w1 < OPTION_DCACHE_WAYS; w1 = w1 + 1) begin
tag_way_save[w1] <= tag_way_out[w1];
end
state <= REFILL;
end else if (cpu_we_i | write_pending) begin
state <= WRITE;
end else if (invalidate) begin
state <= IDLE;
end
end else if (!dc_enable_i | invalidate) begin
state <= IDLE;
end
end
REFILL: begin
if (we_i) begin
refill_valid[wradr_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] <= 1;
if (refill_done)
state <= IDLE;
end
// Abort refill on snoop-hit
// TODO: only abort on snoop-hits to refill address
if (snoop_hit) begin
refill_valid <= 0;
refill_valid_r <= 0;
state <= IDLE;
end
end
WRITE: begin
if ((!dc_access_i | !cpu_req_i | !cpu_we_i) & !snoop_hit) begin
write_pending <= 0;
state <= READ;
end
end
INVALIDATE: begin
if (invalidate) begin
// Store address in invalidate_adr that is muxed to the tag
// memory write address
invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
state <= INVALIDATE;
end else begin
state <= IDLE;
end
end
default:
state <= IDLE;
endcase
end
end
//
// This is the combinational part of the state machine that
// interfaces the tag and way memories.
//
integer w2;
always @(*) begin
// Default is to keep data, don't write and don't access
tag_lru_in = tag_lru_out;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_out[w2];
end
tag_we = 1'b0;
way_we = {(OPTION_DCACHE_WAYS){1'b0}};
access = {(OPTION_DCACHE_WAYS){1'b0}};
way_wr_dat = wrdat_i;
// The default is (of course) not to acknowledge the invalidate
invalidate_ack = 1'b0;
if (snoop_hit) begin
// This is the write access
tag_we = 1'b1;
tag_windex = snoop_windex;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
if (snoop_way_hit[w2]) begin
tag_way_in[w2] = 0;
end else begin
tag_way_in[w2] = snoop_way_out[w2];
end
end
end else begin
//
// The tag mem is written during reads and writes to write
// the lru info and during refill and invalidate.
//
tag_windex = read | write ?
cpu_adr_match_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] :
(state == INVALIDATE) ? invalidate_adr :
wradr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
case (state)
IDLE: begin
//
// When idle we can always acknowledge the invalidate as it
// has the highest priority in handling. When something is
// changed on the state machine handling above this needs
// to be changed.
//
invalidate_ack = 1'b1;
end
READ: begin
if (hit) begin
//
// We got a hit. The LRU module gets the access
// information. Depending on this we update the LRU
// history in the tag.
//
access = way_hit;
// This is the updated LRU history after hit
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
WRITE: begin
way_wr_dat = cpu_dat_i;
if (hit & cpu_req_i) begin
/* Mux cache output with write data */
if (!cpu_bsel_i[3])
way_wr_dat[31:24] = cpu_dat_o[31:24];
if (!cpu_bsel_i[2])
way_wr_dat[23:16] = cpu_dat_o[23:16];
if (!cpu_bsel_i[1])
way_wr_dat[15:8] = cpu_dat_o[15:8];
if (!cpu_bsel_i[0])
way_wr_dat[7:0] = cpu_dat_o[7:0];
way_we = way_hit;
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
REFILL: begin
if (we_i) begin
//
// Write the data to the way that is replaced (which is
// the LRU)
//
way_we = tag_save_lru;
// Access pattern
access = tag_save_lru;
/* Invalidate the way on the first write */
if (refill_valid == 0) begin
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
if (tag_save_lru[w2]) begin
tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0;
end
end
tag_we = 1'b1;
end
//
// After refill update the tag memory entry of the
// filled way with the LRU history, the tag and set
// valid to 1.
//
if (refill_done) begin
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_save[w2];
if (tag_save_lru[w2]) begin
tag_way_in[w2] = { 1'b1, tag_wtag };
end
end
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
end
INVALIDATE: begin
invalidate_ack = 1'b1;
// Lazy invalidation, invalidate everything that matches tag address
tag_lru_in = 0;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = 0;
end
tag_we = 1'b1;
end
default: begin
end
endcase
end
end
generate
for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : way_memories
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(WAY_WIDTH-2),
.DATA_WIDTH(OPTION_OPERAND_WIDTH),
.ENABLE_BYPASS(1)
)
way_data_ram
(
// Outputs
.dout (way_dout[i]),
// Inputs
.clk (clk),
.raddr (way_raddr[i][WAY_WIDTH-3:0]),
.re (1'b1),
.waddr (way_waddr[i][WAY_WIDTH-3:0]),
.we (way_we[i]),
.din (way_din[i][31:0]));
end
if (OPTION_DCACHE_WAYS >= 2) begin : gen_u_lru
/* mor1kx_cache_lru AUTO_TEMPLATE(
.current (current_lru_history),
.update (next_lru_history),
.lru_pre (lru),
.lru_post (),
.access (access),
); */
mor1kx_cache_lru
#(.NUMWAYS(OPTION_DCACHE_WAYS))
u_lru(/*AUTOINST*/
// Outputs
.update (next_lru_history), // Templated
.lru_pre (lru), // Templated
.lru_post (), // Templated
// Inputs
.current (current_lru_history), // Templated
.access (access)); // Templated
end // if (OPTION_DCACHE_WAYS >= 2)
endgenerate
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH),
.DATA_WIDTH(TAGMEM_WIDTH),
.ENABLE_BYPASS(OPTION_DCACHE_SNOOP != "NONE")
)
tag_ram
(
// Outputs
.dout (tag_dout[TAGMEM_WIDTH-1:0]),
// Inputs
.clk (clk),
.raddr (tag_rindex),
.re (1'b1),
.waddr (tag_windex),
.we (tag_we),
.din (tag_din));
generate
if (OPTION_DCACHE_SNOOP != "NONE") begin
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH),
.DATA_WIDTH(TAGMEM_WIDTH),
.ENABLE_BYPASS(1)
)
snoop_tag_ram
(
// Outputs
.dout (snoop_dout[TAGMEM_WIDTH-1:0]),
// Inputs
.clk (clk),
.raddr (snoop_index),
.re (1'b1),
.waddr (tag_windex),
.we (tag_we),
.din (tag_din));
end
endgenerate
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Global Clock Buffer
// /___/ /\ Filename : BUFG.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFG (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_TB_V
`define SKY130_FD_SC_LP__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_lp__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_TB_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_FUNCTIONAL_V |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_reg_map.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
/*** WA for CR # 695818 ***/
`ifdef XILINX_SIMULATOR
`define XSIM_ISIM
`endif
`ifdef XILINX_ISIM
`define XSIM_ISIM
`endif
module processing_system7_bfm_v2_0_reg_map();
`include "processing_system7_bfm_v2_0_local_params.v"
/* Register definitions */
`include "processing_system7_bfm_v2_0_reg_params.v"
parameter mem_size = 32'h2000_0000; ///as the memory is implemented 4 byte wide
parameter xsim_mem_size = 32'h1000_0000; ///as the memory is implemented 4 byte wide 256 MB
`ifdef XSIM_ISIM
reg [data_width-1:0] reg_mem0 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
reg [data_width-1:0] reg_mem1 [0:(xsim_mem_size/mem_width)-1]; // 256MB mem
parameter addr_offset_bits = 26;
`else
reg /*sparse*/ [data_width-1:0] reg_mem [0:(mem_size/mem_width)-1]; // 512 MB needed for reg space
parameter addr_offset_bits = 27;
`endif
/* preload reset_values from file */
task automatic pre_load_rst_values;
input dummy;
begin
`include "processing_system7_bfm_v2_0_reg_init.v" /* This file has list of set_reset_data() calls to set the reset value for each register*/
end
endtask
/* writes the reset data into the reg memory */
task automatic set_reset_data;
input [addr_width-1:0] address;
input [data_width-1:0] data;
reg [addr_width-1:0] addr;
begin
addr = address >> 2;
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
14 : reg_mem0[addr[addr_offset_bits-1:0]] = data;
15 : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* writes the data into the reg memory */
task automatic set_data;
input [addr_width-1:0] addr;
input [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : reg_mem0[addr[addr_offset_bits-1:0]] = data;
6'h0F : reg_mem1[addr[addr_offset_bits-1:0]] = data;
endcase
`else
reg_mem[addr[addr_offset_bits-1:0]] = data;
`endif
end
endtask
/* get the read data from reg mem */
task automatic get_data;
input [addr_width-1:0] addr;
output [data_width-1:0] data;
begin
`ifdef XSIM_ISIM
case(addr[addr_width-1:addr_offset_bits])
6'h0E : data = reg_mem0[addr[addr_offset_bits-1:0]];
6'h0F : data = reg_mem1[addr[addr_offset_bits-1:0]];
endcase
`else
data = reg_mem[addr[addr_offset_bits-1:0]];
`endif
end
endtask
/* read chunk of registers */
task read_reg_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading Register Map starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits- data_width]);
if(no_of_bytes < mem_width ) begin
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - mem_width;
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
get_data(addr,temp_data[max_burst_bits-1 : max_burst_bits-data_width]);
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
get_data(addr,temp_rd_data);
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading Register Map starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
initial
begin
pre_load_rst_values(1);
end
endmodule
|
/////////////////////////////////////////////////////////////////////////
//
// pLIB
// D-FLIP-FLOPS
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// p_I_FD FD error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD (Q,D,C,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
defparam FD_z.INIT=INIT;
FD FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD FD error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD (Q,D,C,E);
parameter INIT = 1'b0;
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FD_1 FD_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD_1 FD_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC FDC error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC FDC error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC_1 FDC_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC_1 FDC_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE FDCE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE_1 FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE_1 FDCE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP FDCP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP FDCP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP_1 FDCP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP_1 FDCP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE FDCPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE FDCPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE_1 FDCPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE_1 FDCPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE FDE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE FDE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE_1 FDE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE_1 FDE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP FDP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP FDP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP_1 FDP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP_1 FDP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE FDPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE FDPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE_1 FDPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE_1 FDPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR FDR error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR FDR error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR (Q,D,C,R,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
defparam FD_z.INIT=INIT;
// Xilinx FD instance
FDR FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR_1 FDR_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR_1 FDR_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE FDRE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE FDRE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE (Q,D,C,R,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE_1 FDRE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE_1 FDRE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS FDRS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS_1 FDRS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS_1 FDRS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE FDRSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE_1 FDRSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE_1 FDRSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS FDS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS FDS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS_1 FDS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS_1 FDS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE FDSE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE FDSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE_1 FDSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
xor (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE_1 FDSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
xor (Q,Qtemp,E);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_gt_wrapper.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : gt_wrapper.v
// Description : GT Wrapper Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- GT Wrapper --------------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_gt_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 0, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lane
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
(
//---------- GT User Ports -----------------------------
input GT_MASTER,
input GT_GEN3,
input GT_RX_CONVERGE,
//---------- GT Clock Ports ----------------------------
input GT_GTREFCLK0,
input GT_QPLLCLK,
input GT_QPLLREFCLK,
input GT_TXUSRCLK,
input GT_RXUSRCLK,
input GT_TXUSRCLK2,
input GT_RXUSRCLK2,
input GT_OOBCLK,
input [ 1:0] GT_TXSYSCLKSEL,
input [ 1:0] GT_RXSYSCLKSEL,
input GT_CPLLPDREFCLK,
output GT_TXOUTCLK,
output GT_RXOUTCLK,
output GT_CPLLLOCK,
output GT_RXCDRLOCK,
//---------- GT Reset Ports ----------------------------
input GT_CPLLPD,
input GT_CPLLRESET,
input GT_TXUSERRDY,
input GT_RXUSERRDY,
input GT_RESETOVRD,
input GT_GTTXRESET,
input GT_GTRXRESET,
input GT_TXPMARESET,
input GT_RXPMARESET,
input GT_RXCDRRESET,
input GT_RXCDRFREQRESET,
input GT_RXDFELPMRESET,
input GT_EYESCANRESET,
input GT_TXPCSRESET,
input GT_RXPCSRESET,
input GT_RXBUFRESET,
output GT_EYESCANDATAERROR,
output GT_TXRESETDONE,
output GT_RXRESETDONE,
output GT_RXPMARESETDONE,
//---------- GT TX Data Ports --------------------------
input [31:0] GT_TXDATA,
input [ 3:0] GT_TXDATAK,
output GT_TXP,
output GT_TXN,
//---------- GT RX Data Ports --------------------------
input GT_RXN,
input GT_RXP,
output [31:0] GT_RXDATA,
output [ 3:0] GT_RXDATAK,
//---------- GT Command Ports --------------------------
input GT_TXDETECTRX,
input GT_TXELECIDLE,
input GT_TXCOMPLIANCE,
input GT_RXPOLARITY,
input [ 1:0] GT_TXPOWERDOWN,
input [ 1:0] GT_RXPOWERDOWN,
input [ 2:0] GT_TXRATE,
input [ 2:0] GT_RXRATE,
//---------- GT Electrical Command Ports ---------------
input [ 2:0] GT_TXMARGIN,
input GT_TXSWING,
input GT_TXDEEMPH,
input [ 4:0] GT_TXPRECURSOR,
input [ 6:0] GT_TXMAINCURSOR,
input [ 4:0] GT_TXPOSTCURSOR,
//---------- GT Status Ports ---------------------------
output GT_RXVALID,
output GT_PHYSTATUS,
output GT_RXELECIDLE,
output [ 2:0] GT_RXSTATUS,
output [ 2:0] GT_RXBUFSTATUS,
output GT_TXRATEDONE,
output GT_RXRATEDONE,
output [7:0] GT_RXDISPERR,
output [7:0] GT_RXNOTINTABLE,
//---------- GT DRP Ports ------------------------------
input GT_DRPCLK,
input [ 8:0] GT_DRPADDR,
input GT_DRPEN,
input [15:0] GT_DRPDI,
input GT_DRPWE,
output [15:0] GT_DRPDO,
output GT_DRPRDY,
//---------- GT TX Sync Ports --------------------------
input GT_TXPHALIGN,
input GT_TXPHALIGNEN,
input GT_TXPHINIT,
input GT_TXDLYBYPASS,
input GT_TXDLYSRESET,
input GT_TXDLYEN,
output GT_TXDLYSRESETDONE,
output GT_TXPHINITDONE,
output GT_TXPHALIGNDONE,
input GT_TXPHDLYRESET,
input GT_TXSYNCMODE, // GTH
input GT_TXSYNCIN, // GTH
input GT_TXSYNCALLIN, // GTH
output GT_TXSYNCOUT, // GTH
output GT_TXSYNCDONE, // GTH
//---------- GT RX Sync Ports --------------------------
input GT_RXPHALIGN,
input GT_RXPHALIGNEN,
input GT_RXDLYBYPASS,
input GT_RXDLYSRESET,
input GT_RXDLYEN,
input GT_RXDDIEN,
output GT_RXDLYSRESETDONE,
output GT_RXPHALIGNDONE,
input GT_RXSYNCMODE, // GTH
input GT_RXSYNCIN, // GTH
input GT_RXSYNCALLIN, // GTH
output GT_RXSYNCOUT, // GTH
output GT_RXSYNCDONE, // GTH
//---------- GT Comma Alignment Ports ------------------
input GT_RXSLIDE,
output GT_RXCOMMADET,
output [ 3:0] GT_RXCHARISCOMMA,
output GT_RXBYTEISALIGNED,
output GT_RXBYTEREALIGN,
//---------- GT Channel Bonding Ports ------------------
input GT_RXCHBONDEN,
input [ 4:0] GT_RXCHBONDI,
input [ 2:0] GT_RXCHBONDLEVEL,
input GT_RXCHBONDMASTER,
input GT_RXCHBONDSLAVE,
output GT_RXCHANISALIGNED,
output [ 4:0] GT_RXCHBONDO,
//---------- GT PRBS/Loopback Ports --------------------
input [ 2:0] GT_TXPRBSSEL,
input [ 2:0] GT_RXPRBSSEL,
input GT_TXPRBSFORCEERR,
input GT_RXPRBSCNTRESET,
input [ 2:0] GT_LOOPBACK,
output GT_RXPRBSERR,
//---------- GT Debug Ports ----------------------------
output [14:0] GT_DMONITOROUT
);
//---------- Internal Signals --------------------------
wire [ 2:0] txoutclksel;
wire [ 2:0] rxoutclksel;
wire [63:0] rxdata;
wire [ 7:0] rxdatak;
wire [ 7:0] rxchariscomma;
wire rxlpmen;
wire [14:0] dmonitorout;
wire dmonitorclk;
wire cpllpd;
wire cpllrst;
//---------- Select CPLL and Clock Dividers ------------
localparam CPLL_REFCLK_DIV = 1;
localparam CPLL_FBDIV_45 = 5;
localparam CPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 2 :
(PCIE_REFCLK_FREQ == 1) ? 4 : 5;
localparam OUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 4 : 2;
localparam CLK25_DIV = (PCIE_REFCLK_FREQ == 2) ? 10 :
(PCIE_REFCLK_FREQ == 1) ? 5 : 4;
//---------- Select IES vs. GES ------------------------
localparam CLKMUX_PD = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 1'd0 : 1'd1;
//---------- Select GTP CPLL configuration -------------
// PLL0/1_CFG[ 5:2] = CP1 : [ 8, 4, 2, 1] units
// PLL0/1_CFG[10:6] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (8/4=2) = 27'h01F0210 = 0000_0001_1111_0000_0010_0001_0000
// (9/3=3) = 27'h01F024C = 0000_0001_1111_0000_0010_0100_1100
// (8/3=2.67) = 27'h01F020C = 0000_0001_1111_0000_0010_0000_1100
// (7/3=2.33) = 27'h01F01CC = 0000_0001_1111_0000_0001_1100_1100
// (6/3=2) = 27'h01F018C = 0000_0001_1111_0000_0001_1000_1100
// (5/3=1.67) = 27'h01F014C = 0000_0001_1111_0000_0001_0100_1100
// (6/2=3) = 27'h01F0188 = 0000_0001_1111_0000_0001_1000_1000
//---------- Select GTX CPLL configuration -------------
// CPLL_CFG[ 5: 2] = CP1 : [ 8, 4, 2, 1] units
// CPLL_CFG[22:18] = CP2 : [16, 8, 4, 2, 1] units
// CP2/CP1 = 2 to 3
// (9/3=3) = 1010_0100_0000_0111_1100_1100
//------------------------------------------------------
localparam CPLL_CFG = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ? 24'hB407CC : 24'hA407CC;
//---------- Select TX XCLK ----------------------------
// TXOUT for TX Buffer Use
// TXUSR for TX Buffer Bypass
//------------------------------------------------------
localparam TX_XCLK_SEL = (PCIE_TXBUF_EN == "TRUE") ? "TXOUT" : "TXUSR";
//---------- Select TX Receiver Detection Configuration
localparam TX_RXDETECT_CFG = (PCIE_REFCLK_FREQ == 2) ? 14'd250 :
(PCIE_REFCLK_FREQ == 1) ? 14'd125 : 14'd100;
localparam TX_RXDETECT_REF = (((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) && (PCIE_SIM_MODE == "FALSE")) ? 3'b000 : 3'b011;
//---------- Select PCS_RSVD_ATTR ----------------------
// [0]: 1 = enable latch when bypassing TX buffer, 0 = disable latch when using TX buffer
// [1]: 1 = enable manual TX sync, 0 = enable auto TX sync
// [2]: 1 = enable manual RX sync, 0 = enable auto RX sync
// [3]: 1 = select external clock for OOB 0 = select reference clock for OOB
// [6]: 1 = enable DMON 0 = disable DMON
// [7]: 1 = filter stale TX[P/N] data when exiting TX electrical idle
// [8]: 1 = power up OOB 0 = power down OOB
//------------------------------------------------------
localparam OOBCLK_SEL = (PCIE_OOBCLK_MODE == 0) ? 1'd0 : 1'd1; // GTX
localparam RXOOB_CLK_CFG = (PCIE_OOBCLK_MODE == 0) ? "PMA" : "FABRIC"; // GTH/GTP
localparam PCS_RSVD_ATTR = ((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_USE_MODE == "1.0") && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd7} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd6} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd5} :
((PCIE_RXSYNC_MODE == 0) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd4} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd3} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 0) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd2} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "FALSE")) ? {44'h0000000001C, OOBCLK_SEL, 3'd1} :
((PCIE_RXSYNC_MODE == 1) && (PCIE_TXSYNC_MODE == 1) && (PCIE_TXBUF_EN == "TRUE" )) ? {44'h0000000001C, OOBCLK_SEL, 3'd0} : {44'h0000000001C, OOBCLK_SEL, 3'd7};
//---------- Select RXCDR_CFG --------------------------
//---------- GTX Note ----------------------------------
// For GTX PCIe Gen1/Gen2 with 8B/10B, the following CDR setting may provide more margin
// Async 72'h03_8000_23FF_1040_0020
// Sync: 72'h03_0000_23FF_1040_0020
//------------------------------------------------------
localparam RXCDR_CFG_GTX = ((PCIE_USE_MODE == "1.0") || (PCIE_USE_MODE == "1.1")) ?
((PCIE_ASYNC_EN == "TRUE") ? 72'b0000_0010_0000_0111_1111_1110_0010_0000_0110_0000_0010_0001_0001_0000_0000000000010000
: 72'h11_07FE_4060_0104_0000): // IES setting
((PCIE_ASYNC_EN == "TRUE") ? 72'h03_8000_23FF_1020_0020 //
: 72'h03_0000_23FF_1020_0020); // optimized for GES silicon
localparam RXCDR_CFG_GTH = (PCIE_USE_MODE == "2.0") ?
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0011_07FE_4060_2104_1010
: 83'h0_0011_07FE_4060_0104_1010): // Optimized for IES silicon
((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0020_07FE_2000_C208_8018
: 83'h0_0020_07FE_2000_C208_0018); // Optimized for 1.2 silicon
localparam RXCDR_CFG_GTP = ((PCIE_ASYNC_EN == "TRUE") ? 83'h0_0001_07FE_4060_2104_1010
: 83'h0_0001_07FE_4060_0104_1010); // Optimized for IES silicon
//---------- Select TX and RX Sync Mode ----------------
localparam TXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_OVRD = (PCIE_TXSYNC_MODE == 1) ? 1'd0 : 1'd1;
localparam TXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
localparam RXSYNC_MULTILANE = (PCIE_LANE == 1) ? 1'd0 : 1'd1;
//---------- Select Clock Correction Min and Max Latency
// CLK_COR_MIN_LAT = Larger of (2 * RXCHBONDLEVEL + 13) or (CHAN_BOND_MAX_SKEW + 11)
// = 13 when PCIE_LANE = 1
// CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + CLK_COR_SEQ_LEN + 1
// = CLK_COR_MIN_LAT + 2
//------------------------------------------------------
//---------- CLK_COR_MIN_LAT Look-up Table -------------
// Lane | One-Hop | Daisy-Chain | Binary-Tree
//------------------------------------------------------
// 0 | 13 | 13 | 13
// 1 | 15 to 18 | 15 to 18 | 15 to 18
// 2 | 15 to 18 | 17 to 18 | 15 to 18
// 3 | 15 to 18 | 19 | 17 to 18
// 4 | 15 to 18 | 21 | 17 to 18
// 5 | 15 to 18 | 23 | 19
// 6 | 15 to 18 | 25 | 19
// 7 | 15 to 18 | 27 | 21
//------------------------------------------------------
localparam CLK_COR_MIN_LAT = ((PCIE_LANE == 8) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 27 : 21) :
((PCIE_LANE == 7) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 25 : 19) :
((PCIE_LANE == 6) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 23 : 19) :
((PCIE_LANE == 5) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 21 : 18) :
((PCIE_LANE == 4) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 19 : 18) :
((PCIE_LANE == 3) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 2) && (PCIE_CHAN_BOND != 0) && (PCIE_CHAN_BOND_EN == "TRUE")) ? ((PCIE_CHAN_BOND == 1) ? 18 : 18) :
((PCIE_LANE == 1) || (PCIE_CHAN_BOND_EN == "FALSE")) ? 13 : 18;
localparam CLK_COR_MAX_LAT = CLK_COR_MIN_LAT + 2;
//---------- Simulation Speedup ------------------------
//localparam CFOK_CFG_GTH = (PCIE_SIM_MODE == "TRUE") ? 42'h240_0004_0F80 : 42'h248_0004_0E80; // [8] : 1 = Skip CFOK
//localparam CFOK_CFG_GTP = (PCIE_SIM_MODE == "TRUE") ? 43'h000_0000_0000 : 43'h000_0000_0100; // [2] : 1 = Skip CFOK
//---------- Select [TX/RX]OUTCLK ----------------------
assign txoutclksel = GT_MASTER ? 3'd3 : 3'd0;
assign rxoutclksel = ((PCIE_DEBUG_MODE == 1) || ((PCIE_ASYNC_EN == "TRUE") && GT_MASTER)) ? 3'd2 : 3'd0;
//---------- Select DFE vs. LPM ------------------------
// Gen1/2 = Use LPM by default. Option to use DFE.
// Gen3 = Use DFE by default. Option to use LPM.
//------------------------------------------------------
assign rxlpmen = GT_GEN3 ? ((PCIE_LPM_DFE_GEN3 == "LPM") ? 1'd1 : 1'd0) : ((PCIE_LPM_DFE == "LPM") ? 1'd1 : 1'd0);
//---------- Generate DMONITOR Clock Buffer for Debug ------
generate if (PCIE_DEBUG_MODE == 1)
begin : dmonitorclk_i
//---------- DMONITOR CLK ------------------------------
BUFG dmonitorclk_i
(
//---------- Input ---------------------------------
.I (dmonitorout[7]),
//---------- Output --------------------------------
.O (dmonitorclk)
);
end
else
begin : dmonitorclk_i_disable
assign dmonitorclk = 1'd0;
end
endgenerate
pcie_7x_0_core_top_gtx_cpllpd_ovrd cpllPDInst (
.i_ibufds_gte2(GT_CPLLPDREFCLK),
.o_cpllpd_ovrd(cpllpd),
.o_cpllreset_ovrd(cpllrst));
//---------- Select GTX or GTH or GTP ------------------------------------------
// Notes : Attributes that are commented out always use the GT default settings
//------------------------------------------------------------------------------
generate if (PCIE_GT_DEVICE == "GTP")
begin : gtp_channel
//---------- GTP Channel Module --------------------------------------------
GTPE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
//.TX_CLKMUX_EN ( 1'b1), // GTP rename
//.RX_CLKMUX_EN ( 1'b1), // GTP rename
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
//.OUTREFCLK_SEL_INV ( 2'b11), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME ( 5'b00001), //
.RXPCSRESET_TIME ( 5'b00001), //
.TXPMARESET_TIME ( 5'b00011), //
.RXPMARESET_TIME ( 5'b00011), // Optimized for sim
//.RXISCANRESET_TIME ( 5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for IES
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim
.TX_EIDLE_DEASSERT_DELAY ( 3'b010), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTP
//---------- Status Attributes -----------------------------------------
//.RX_SIG_VALID_DLY ( 4), // CHECK
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0100), // [8] : 1 = OOB power-up
//---------- PMA Attributes -------------------------------------------
//.CLK_COMMON_SWING ( 1'b0), // GTP new
//.PMA_RSV (32'd0), //
.PMA_RSV2 (32'h00002040), // Optimized for GES
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 ( 4'd0), // Changed from 15 to 4-bits
//.PMA_RSV5 ( 1'd0), // Changed from 4 to 1-bit
//.PMA_RSV6 ( 1'd0), // GTP new
//.PMA_RSV7 ( 1'd0), // GTP new
.RX_BIAS_CFG (16'h0F33), // Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Optimized for IES
//---------- TX PI ----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), //
//.TXPI_CFG1 ( 2'd0), //
//.TXPI_CFG2 ( 2'd0), //
//.TXPI_CFG3 ( 1'd0), //
//.TXPI_CFG4 ( 1'd0), //
//.TXPI_CFG5 ( 3'd000), //
//.TXPI_GREY_SEL ( 1'd0), //
//.TXPI_INVSTROBE_SEL ( 1'd0), //
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), //
//.TXPI_PPM_CFG ( 8'd0), //
//.TXPI_SYNFREQ_PPM ( 3'd0), //
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 ( 3'd0), // Changed from 3 to 2-bits, Optimized for IES
.RXPI_CFG1 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
.RXPI_CFG2 ( 1'd1), // Changed from 2 to 1-bits, Optimized for IES
//---------- CDR Attributes ---------------------------------------------
//.RXCDR_CFG (72'b0000_001000000_11111_11111_001000000_011_0000111_000_001000_010000_100000000000000), // CHECK
.RXCDR_CFG (RXCDR_CFG_GTP), // Optimized for IES
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001) CHECK
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
//.RXLPMRESET_TIME ( 7'b0001111), // GTP new
//.RXLPM_BIAS_STARTUP_DISABLE ( 1'b0), // GTP new
.RXLPM_CFG ( 4'b0110), // GTP new, optimized for IES
//.RXLPM_CFG1 ( 1'b0), // GTP new
//.RXLPM_CM_CFG ( 1'b0), // GTP new
.RXLPM_GC_CFG ( 9'b111100010), // GTP new, optimized for IES
.RXLPM_GC_CFG2 ( 3'b001), // GTP new, optimized for IES
//.RXLPM_HF_CFG (14'b00001111110000), //
.RXLPM_HF_CFG2 ( 5'b01010), // GTP new
//.RXLPM_HF_CFG3 ( 4'b0000), // GTP new
.RXLPM_HOLD_DURING_EIDLE ( 1'b1), // GTP new
.RXLPM_INCM_CFG ( 1'b1), // GTP new, optimized for IES
.RXLPM_IPCM_CFG ( 1'b0), // GTP new, optimized for IES
//.RXLPM_LF_CFG (18'b000000001111110000), //
.RXLPM_LF_CFG2 ( 5'b01010), // GTP new, optimized for IES
.RXLPM_OSINT_CFG ( 3'b100), // GTP new, optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // CHECK
.RXOSCALRESET_TIME (5'b00011), // Optimized for IES
.RXOSCALRESET_TIMEOUT (5'b00000), // Disable timeout, Optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'b0), //
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), //
//.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
.TXDLY_CFG (16'h001F), //
.TXDLY_LCFG ( 9'h030), //
.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), //
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), //
.TXSYNC_SKIP_DA (1'b0), //
//---------- RX Sync Attributes ----------------------------------------
.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
.RXDLY_CFG (16'h001F), //
.RXDLY_LCFG ( 9'h030), //
.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), //
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), //
.RXSYNC_SKIP_DA (1'b0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE (4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE ( 3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes ---------------------------------
.LOOPBACK_CFG ( 1'd0), // Enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes --------------------------------------
.TXOOB_CFG ( 1'd1), // Filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_PLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), //
.RX_DEBUG_CFG (14'h0000), // Optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
//---------- GTP -------------------------------------------------------
//.ACJTAG_DEBUG_MODE (1'd0), //
//.ACJTAG_MODE (1'd0), //
//.ACJTAG_RESET (1'd0), //
//.ADAPT_CFG0 (20'd0), //
.CFOK_CFG (43'h490_0004_0E80), // Changed from 42 to 43-bits, Optimized for IES
.CFOK_CFG2 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG3 ( 7'b010_0000), // Changed from 6 to 7-bits, Optimized for IES
.CFOK_CFG4 ( 1'd0), // GTP new, Optimized for IES
.CFOK_CFG5 ( 2'd0), // GTP new, Optimized for IES
.CFOK_CFG6 ( 4'd0) // GTP new, Optimized for IES
)
gtpe2_channel_i
(
//---------- Clock -----------------------------------------------------
.PLL0CLK (GT_QPLLCLK), //
.PLL1CLK (1'd0), //
.PLL0REFCLK (GT_QPLLREFCLK), //
.PLL1REFCLK (1'd0), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CLKRSVD0 (1'd0), //
.CLKRSVD1 (1'd0), //
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
//---------- Reset -----------------------------------------------------
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA (GT_TXDATA), //
.TXCHARISK (GT_TXDATAK), //
.GTPTXP (GT_TXP), // GTP
.GTPTXN (GT_TXN), // GTP
//---------- RX Data ---------------------------------------------------
.GTPRXP (GT_RXP), // GTP
.GTPRXN (GT_RXN), // GTP
.RXDATA (rxdata[31:0]), //
.RXCHARISK (rxdatak[3:0]), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({3'd0, GT_TXCOMPLIANCE}), // Changed from 8 to 4-bits
.TXCHARDISPVAL ( 4'd0), // Changed from 8 to 4-bits
.TXPOLARITY ( 1'b0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'b0), //
.RXRATEMODE (1'b0), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMRESET ( 1'd0), // GTP new
.RXLPMOSINTNTRLEN ( 1'd0), // GTP new
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFOVRDEN ( 1'd0), //
.PMARSVDIN0 ( 1'd0), // GTP new
.PMARSVDIN1 ( 1'd0), // GTP new
.PMARSVDIN2 ( 1'd0), // GTP new
.PMARSVDIN3 ( 1'd0), // GTP new
.PMARSVDIN4 ( 1'd0), // GTP new
.GTRSVD (16'd0), //
.PMARSVDOUT0 (), // GTP new
.PMARSVDOUT1 (), // GTP new
.DMONITOROUT (dmonitorout), // GTP 15-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'b0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), //
.TXPIPPMOVRDEN (1'd0), //
.TXPIPPMPD (1'd0), //
.TXPIPPMSEL (1'd0), //
.TXPIPPMSTEPSIZE (5'd0), //
.TXPISOPD (1'd0), // GTP new
//---------- DFE -------------------------------------------------------
.RXDFEXYDEN (1'd0), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // Optimized for IES
.RXOSOVRDEN (1'd0), // Optimized for IES
.RXOSINTEN (1'd1), // Optimized for IES
.RXOSINTHOLD (1'd0), // Optimized for IES
.RXOSINTNTRLEN (1'd0), // Optimized for IES
.RXOSINTOVRDEN (1'd0), // Optimized for IES
.RXOSINTPD (1'd0), // GTP new, Optimized for IES
.RXOSINTSTROBE (1'd0), // Optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // Optimized for IES
.RXOSINTCFG (4'b0010), // Optimized for IES
.RXOSINTID0 (4'd0), // Optimized for IES
.RXOSINTDONE (), //
.RXOSINTSTARTED (), //
.RXOSINTSTROBEDONE (), //
.RXOSINTSTROBESTARTED (), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'b0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), //
.TXSYNCIN (GT_TXSYNCIN), //
.TXSYNCALLIN (GT_TXSYNCALLIN), //
.TXSYNCDONE (GT_TXSYNCDONE), //
.TXSYNCOUT (GT_TXSYNCOUT), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), //
.RXSYNCIN (GT_RXSYNCIN), //
.RXSYNCALLIN (GT_RXSYNCALLIN), //
.RXSYNCDONE (GT_RXSYNCDONE), //
.RXSYNCOUT (GT_RXSYNCOUT), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN (1'd1), //
.RXMCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXPCOMMAALIGNEN (1'd1), // No Gen3 support in GTP
.RXSLIDE (GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma[3:0]), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI[3:0]), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO[3:0]), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (4'd0), //
.TX8B10BEN (1'b1), // No Gen3 support in GTP
.RX8B10BEN (1'b1), // No Gen3 support in GTP
.RXDISPERR (GT_RXDISPERR[3:0]), //
.RXNOTINTABLE (GT_RXNOTINTABLE[3:0]), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // Optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTP -------------------------------------------------------
.RXADAPTSELTEST (14'd0), //
.DMONFIFORESET ( 1'd0), //
.DMONITORCLK (dmonitorclk), //
.RXOSCALRESET ( 1'd0), //
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTP
.TXPMARESETDONE () //
);
assign GT_CPLLLOCK = 1'b0;
end
else if (PCIE_GT_DEVICE == "GTH")
begin : gth_channel
//---------- GTH Channel Module --------------------------------------------
GTHE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION ("2.0"), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD ( 1'b1), // GTH
.RX_CLKMUX_PD ( 1'b1), // GTH
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (29'h00A407CC), // Changed from 24 to 29-bits, Optimized for PCIe PLL BW
.CPLL_INIT_CFG (24'h00001E), // Optimized for IES
.CPLL_LOCK_CFG (16'h01E8), // Optimized for IES
//.USE_PCS_CLK_PHASE_SEL ( 1'd0) // GTH new
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//.RESET_POWERSAVE_DISABLE ( 1'd0), // GTH new
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_PRECHARGE_TIME (17'h00001), // GTH new, Optimized for sim
.TX_RXDETECT_REF ( 3'b011), //
.RX_CM_SEL ( 2'b11), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable, optimized for silicon
.RX_CM_TRIM ( 4'b1010), // Select 800mV, Changed from 3 to 4-bits, optimized for silicon
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), // Optimized for sim
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 6'b010100), // 6.0 dB, optimized for compliance, changed from 5 to 6-bits
.TX_DEEMPH1 ( 6'b001011), // 3.5 dB, optimized for compliance, changed from 5 to 6-bits
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (48'h0000_0000_0140), // [8] : 1 = OOB power-up, [6] : 1 = DMON enable, Optimized for IES
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00000080), // Optimized for IES
.PMA_RSV2 (32'h1C00000A), // Changed from 16 to 32-bits, Optimized for IES
//.PMA_RSV3 ( 2'h0), //
.PMA_RSV4 (15'h0008), // GTH new, Optimized for IES
//.PMA_RSV5 ( 4'h00), // GTH new
.RX_BIAS_CFG (24'h0C0010), // Changed from 12 to 24-bits, Optimized for IES
.TERM_RCAL_CFG (15'b100001000010000), // Changed from 5 to 15-bits, Optimized for IES
.TERM_RCAL_OVRD ( 3'b000), // Changed from 1 to 3-bits, Optimized for IES
//---------- TX PI -----------------------------------------------------
//.TXPI_CFG0 ( 2'd0), // GTH new
//.TXPI_CFG1 ( 2'd0), // GTH new
//.TXPI_CFG2 ( 2'd0), // GTH new
//.TXPI_CFG3 ( 1'd0), // GTH new
//.TXPI_CFG4 ( 1'd0), // GTH new
//.TXPI_CFG5 ( 3'b100), // GTH new
//.TXPI_GREY_SEL ( 1'd0), // GTH new
//.TXPI_INVSTROBE_SEL ( 1'd0), // GTH new
//.TXPI_PPMCLK_SEL ("TXUSRCLK2"), // GTH new
//.TXPI_PPM_CFG ( 8'd0), // GTH new
//.TXPI_SYNFREQ_PPM ( 3'd0), // GTH new
//---------- RX PI -----------------------------------------------------
.RXPI_CFG0 (2'b00), // GTH new
.RXPI_CFG1 (2'b11), // GTH new
.RXPI_CFG2 (2'b11), // GTH new
.RXPI_CFG3 (2'b11), // GTH new
.RXPI_CFG4 (1'b0), // GTH new
.RXPI_CFG5 (1'b0), // GTH new
.RXPI_CFG6 (3'b100), // GTH new
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTH), //
//.RXCDR_CFG (83'h0_0011_07FE_4060_0104_1010), // A. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_4060_2104_1010), // B. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, default, converted from GTX GES VnC,(2 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_0104_1010), // C. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-000ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0011_07FE_2060_2104_1010), // D. Changed from 72 to 83-bits, optimized for IES div1 (Gen2), +/-300ppm, converted from GTX GES recommended, (3 Gen1)
//.RXCDR_CFG (83'h0_0001_07FE_1060_0110_1010), // E. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0001_07FE_1060_2110_1010), // F. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, default, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_0110_1010), // G. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-000ppm, converted from GTX GES recommended, (3 Gen2)
//.RXCDR_CFG (83'h0_0011_07FE_1060_2110_1010), // H. Changed from 72 to 83-bits, optimized for IES div2 (Gen1), +/-300ppm, converted from GTX GES recommended, (2 Gen1)
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), // optimized for IES
//.RXCDRPHRESET_TIME ( 5'b00001), // optimized for IES
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h0200), // Optimized for IES
.RXLPM_LF_CFG (18'h09000), // Changed from 14 to 18-bits, Optimized for IES
//---------- DFE Attributes --------------------------------------------
.RXDFELPMRESET_TIME ( 7'h0F), // Optimized for IES
.RX_DFE_AGC_CFG0 ( 2'h0), // GTH new, optimized for IES
.RX_DFE_AGC_CFG1 ( 3'h4), // GTH new, optimized for IES, DFE
.RX_DFE_AGC_CFG2 ( 4'h0), // GTH new, optimized for IES
.RX_DFE_AGC_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_GAIN_CFG (23'h0020C0), // Optimized for IES
.RX_DFE_H2_CFG (12'h000), // Optimized for IES
.RX_DFE_H3_CFG (12'h040), // Optimized for IES
.RX_DFE_H4_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H5_CFG (11'h0E0), // Optimized for IES
.RX_DFE_H6_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_H7_CFG (11'h020), // GTH new, optimized for IES
.RX_DFE_KL_CFG (33'h000000310), // Changed from 13 to 33-bits, optimized for IES
.RX_DFE_KL_LPM_KH_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KH_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KH_OVRDEN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG0 ( 2'h2), // GTH new, optimized for IES, DFE
.RX_DFE_KL_LPM_KL_CFG1 ( 3'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_CFG2 ( 4'h2), // GTH new, optimized for IES
.RX_DFE_KL_LPM_KL_OVRDEN ( 1'b1), // GTH new, optimized for IES
.RX_DFE_LPM_CFG (16'h0080), // Optimized for IES
.RX_DFELPM_CFG0 ( 4'h6), // GTH new, optimized for IES
.RX_DFELPM_CFG1 ( 4'h0), // GTH new, optimized for IES
.RX_DFELPM_KLKH_AGC_STUP_EN ( 1'h1), // GTH new, optimized for IES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'h1), // PCIe use mode
.RX_DFE_ST_CFG (54'h00_C100_000C_003F), // GTH new, optimized for IES
.RX_DFE_UT_CFG (17'h03800), // Optimized for IES
.RX_DFE_VP_CFG (17'h03AA3), // Optimized for IES
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'h0080), // Optimized for IES
.A_RXOSCALRESET ( 1'd0), // GTH new, optimized for IES
.RXOSCALRESET_TIME ( 5'b00011), // GTH new, optimized for IES
.RXOSCALRESET_TIMEOUT ( 5'b00000), // GTH new, disable timeout, optimized for IES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CLK_PHASE_SEL ( 1'd0), // GTH new
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), // Optimized for IES
.ES_HORZ_OFFSET (12'h000), // Optimized for IES
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), // [19] : 1 = full range, 0 = half range
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
.TXSYNC_OVRD (TXSYNC_OVRD), // GTH new
.TXSYNC_MULTILANE (TXSYNC_MULTILANE), // GTH new
.TXSYNC_SKIP_DA (1'b0), // GTH new
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // [19] : 1 = full range, 0 = half range
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
.RXSYNC_OVRD (RXSYNC_OVRD), // GTH new
.RXSYNC_MULTILANE (RXSYNC_MULTILANE), // GTH new
.RXSYNC_SKIP_DA (1'b0), // GTH new
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.LOOPBACK_CFG ( 1'd1), // GTH new, enable latch when bypassing TX buffer, equivalent to GTX PCS_RSVD_ATTR[0]
.RXPRBS_ERR_LOOPBACK ( 1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
.TXOOB_CFG ( 1'd1), // GTH new, filter stale TX data when exiting TX electrical idle, equivalent to GTX PCS_RSVD_ATTR[7]
//.RXOOB_CFG ( 7'b0000110), //
.RXOOB_CLK_CFG (RXOOB_CLK_CFG), // GTH new
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 1011 = AGC
//.DMONITOR_CFG (24'h000AB1), // Optimized for debug; [7:4] : 0000 = CDR FSM
.RX_DEBUG_CFG (14'b00000011000000), // Changed from 12 to 14-bits, optimized for IES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0), //
//---------- GTH -------------------------------------------------------
//.ACJTAG_DEBUG_MODE ( 1'd0), // GTH new
//.ACJTAG_MODE ( 1'd0), // GTH new
//.ACJTAG_RESET ( 1'd0), // GTH new
.ADAPT_CFG0 (20'h00C10), // GTH new, optimized for IES
.CFOK_CFG (42'h248_0004_0E80), // GTH new, optimized for IES, [8] : 1 = Skip CFOK
.CFOK_CFG2 ( 6'b100000), // GTH new, optimized for IES
.CFOK_CFG3 ( 6'b100000) // GTH new, optimized for IES
)
gthe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD0 (1'd0), // GTH
.CLKRSVD1 (1'd0), // GTH
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (cpllpd | GT_CPLLPD), //
.CPLLRESET (cpllrst | GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTHTXP (GT_TXP), // GTH
.GTHTXN (GT_TXN), // GTH
//---------- RX Data ---------------------------------------------------
.GTHRXP (GT_RXP), // GTH
.GTHRXN (GT_RXN), // GTH
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'b0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
.TXRATEMODE (1'd0), // GTH
.RXRATEMODE (1'd0), // GTH
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1111), // Select 850mV
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), // ***
.RXLPMHFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), // Optimized for IES
.PMARSVDIN ( 5'd0), //
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout), // GTH 15-bits.
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'b0), //
.RXCDROVRDEN (1'd0), //
//---------- PI --------------------------------------------------------
.TXPIPPMEN (1'd0), // GTH new
.TXPIPPMOVRDEN (1'd0), // GTH new
.TXPIPPMPD (1'd0), // GTH new
.TXPIPPMSEL (1'd0), // GTH new
.TXPIPPMSTEPSIZE (5'd0), // GTH new
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFEAGCTRL (5'b10000), // GTH new, optimized for IES
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFETAP6HOLD (1'd0), // GTH new
.RXDFETAP6OVRDEN (1'd0), // GTH new
.RXDFETAP7HOLD (1'd0), // GTH new
.RXDFETAP7OVRDEN (1'd0), // GTH new
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFEAGCOVRDEN (rxlpmen), //
.RXDFELFHOLD (GT_RX_CONVERGE), // Set to 1 after convergence
.RXDFELFOVRDEN (1'd0), //
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd1), // Optimized for IES
.RXMONITORSEL (2'd0), //
.RXDFESLIDETAP (5'd0), // GTH new
.RXDFESLIDETAPID (6'd0), // GTH new
.RXDFESLIDETAPHOLD (1'd0), // GTH new
.RXDFESLIDETAPOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPINITOVRDEN (1'd0), // GTH new
.RXDFESLIDETAPONLYADAPTEN (1'd0), // GTH new
.RXDFESLIDETAPSTROBE (1'd0), // GTH new
.RXMONITOROUT (), //
.RXDFESLIDETAPSTARTED (), // GTH new
.RXDFESLIDETAPSTROBEDONE (), // GTH new
.RXDFESLIDETAPSTROBESTARTED (), // GTH new
.RXDFESTADAPTDONE (), // GTH new
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), // optimized for IES
.RXOSOVRDEN (1'd0), // optimized for IES
.RXOSINTEN (1'd1), // GTH new, optimized for IES
.RXOSINTHOLD (1'd0), // GTH new, optimized for IES
.RXOSINTNTRLEN (1'd0), // GTH new, optimized for IES
.RXOSINTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTSTROBE (1'd0), // GTH new, optimized for IES
.RXOSINTTESTOVRDEN (1'd0), // GTH new, optimized for IES
.RXOSINTCFG (4'b0110), // GTH new, optimized for IES
.RXOSINTID0 (4'b0000), // GTH new, optimized for IES
.RXOSCALRESET ( 1'd0), // GTH, optimized for IES
.RSOSINTDONE (), // GTH new
.RXOSINTSTARTED (), // GTH new
.RXOSINTSTROBEDONE (), // GTH new
.RXOSINTSTROBESTARTED (), // GTH new
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'b0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (GT_TXPHDLYRESET), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
.TXSYNCMODE (GT_TXSYNCMODE), // GTH
.TXSYNCIN (GT_TXSYNCIN), // GTH
.TXSYNCALLIN (GT_TXSYNCALLIN), // GTH
.TXSYNCDONE (GT_TXSYNCDONE), // GTH
.TXSYNCOUT (GT_TXSYNCOUT), // GTH
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
.RXSYNCMODE (GT_RXSYNCMODE), // GTH
.RXSYNCIN (GT_RXSYNCIN), // GTH
.RXSYNCALLIN (GT_RXSYNCALLIN), // GTH
.RXSYNCDONE (GT_RXSYNCDONE), // GTH
.RXSYNCOUT (GT_RXSYNCOUT), // GTH
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (GT_RXDISPERR), //
.RXNOTINTABLE (GT_RXNOTINTABLE), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS & Loopback -------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.SIGVALIDCLK (GT_OOBCLK), // GTH, optimized for debug
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
//---------- GTH -------------------------------------------------------
.RXADAPTSELTEST (14'd0), // GTH new
.DMONFIFORESET ( 1'd0), // GTH
.DMONITORCLK (dmonitorclk), // GTH, optimized for debug
//.DMONITORCLK (GT_DRPCLK), // GTH, optimized for debug
.RXPMARESETDONE (GT_RXPMARESETDONE), // GTH
.TXPMARESETDONE () // GTH
);
end
else
begin : gtx_channel
//---------- GTX Channel Module --------------------------------------------
GTXE2_CHANNEL #
(
//---------- Simulation Attributes -------------------------------------
.SIM_CPLLREFCLK_SEL (3'b001), //
.SIM_RESET_SPEEDUP (PCIE_SIM_SPEEDUP), //
.SIM_RECEIVER_DETECT_PASS ("TRUE"), //
.SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), //
.SIM_VERSION (PCIE_USE_MODE), //
//---------- Clock Attributes ------------------------------------------
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV), //
.CPLL_FBDIV_45 (CPLL_FBDIV_45), //
.CPLL_FBDIV (CPLL_FBDIV), //
.TXOUT_DIV (OUT_DIV), //
.RXOUT_DIV (OUT_DIV), //
.TX_CLK25_DIV (CLK25_DIV), //
.RX_CLK25_DIV (CLK25_DIV), //
.TX_CLKMUX_PD (CLKMUX_PD), // GTX
.RX_CLKMUX_PD (CLKMUX_PD), // GTX
.TX_XCLK_SEL (TX_XCLK_SEL), // TXOUT = use TX buffer, TXUSR = bypass TX buffer
.RX_XCLK_SEL ("RXREC"), // RXREC = use RX buffer, RXUSR = bypass RX buffer
.OUTREFCLK_SEL_INV ( 2'b11), //
.CPLL_CFG (CPLL_CFG), // Optimized for silicon
//.CPLL_INIT_CFG (24'h00001E), //
//.CPLL_LOCK_CFG (16'h01E8), //
//---------- Reset Attributes ------------------------------------------
.TXPCSRESET_TIME (5'b00001), //
.RXPCSRESET_TIME (5'b00001), //
.TXPMARESET_TIME (5'b00011), //
.RXPMARESET_TIME (5'b00011), // Optimized for sim and for DRP
//.RXISCANRESET_TIME (5'b00001), //
//---------- TX Data Attributes ----------------------------------------
.TX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.TX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- RX Data Attributes ----------------------------------------
.RX_DATA_WIDTH (20), // 2-byte external datawidth for Gen1/Gen2
.RX_INT_DATAWIDTH ( 0), // 2-byte internal datawidth for Gen1/Gen2
//---------- Command Attributes ----------------------------------------
.TX_RXDETECT_CFG (TX_RXDETECT_CFG), //
.TX_RXDETECT_REF (TX_RXDETECT_REF), //
.RX_CM_SEL ( 2'd3), // 0 = AVTT, 1 = GND, 2 = Float, 3 = Programmable
.RX_CM_TRIM ( 3'b010), // Select 800mV
.TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // Optimized for sim (3'd4)
.TX_EIDLE_DEASSERT_DELAY ( 3'b100), // Optimized for sim
//.PD_TRANS_TIME_FROM_P2 (12'h03C), //
.PD_TRANS_TIME_NONE_P2 ( 8'h09), //
//.PD_TRANS_TIME_TO_P2 ( 8'h64), //
//.TRANS_TIME_RATE ( 8'h0E), //
//---------- Electrical Command Attributes -----------------------------
.TX_DRIVE_MODE ("PIPE"), // Gen1/Gen2 = PIPE, Gen3 = PIPEGEN3
.TX_DEEMPH0 ( 5'b10100), // 6.0 dB
.TX_DEEMPH1 ( 5'b01011), // 3.5 dB
.TX_MARGIN_FULL_0 ( 7'b1001111), // 1000 mV
.TX_MARGIN_FULL_1 ( 7'b1001110), // 950 mV
.TX_MARGIN_FULL_2 ( 7'b1001101), // 900 mV
.TX_MARGIN_FULL_3 ( 7'b1001100), // 850 mV
.TX_MARGIN_FULL_4 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_0 ( 7'b1000101), // 500 mV
.TX_MARGIN_LOW_1 ( 7'b1000110), // 450 mV
.TX_MARGIN_LOW_2 ( 7'b1000011), // 400 mV
.TX_MARGIN_LOW_3 ( 7'b1000010), // 350 mV
.TX_MARGIN_LOW_4 ( 7'b1000000), // 250 mV
.TX_MAINCURSOR_SEL ( 1'b0), //
.TX_PREDRIVER_MODE ( 1'b0), // GTX
.TX_QPI_STATUS_EN ( 1'b0), //
//---------- Status Attributes -----------------------------------------
.RX_SIG_VALID_DLY (4), // Optimized for sim
//---------- DRP Attributes --------------------------------------------
//---------- PCS Attributes --------------------------------------------
.PCS_PCIE_EN ("TRUE"), // PCIe
.PCS_RSVD_ATTR (PCS_RSVD_ATTR), //
//---------- PMA Attributes --------------------------------------------
.PMA_RSV (32'h00018480), // Optimized for GES Gen1/Gen2
.PMA_RSV2 (16'h2050), // Optimized for silicon, [4] RX_CM_TRIM[4], [5] = 1 Enable Eye Scan
//.PMA_RSV3 ( 2'd0), //
//.PMA_RSV4 (32'd0), // GTX 3.0 new
.RX_BIAS_CFG (12'b000000000100), // Optimized for GES
//.TERM_RCAL_CFG ( 5'b10000), //
//.TERM_RCAL_OVRD ( 1'd0), //
//---------- CDR Attributes --------------------------------------------
.RXCDR_CFG (RXCDR_CFG_GTX), //
.RXCDR_LOCK_CFG ( 6'b010101), // [5:3] Window Refresh, [2:1] Window Size, [0] Enable Detection (sensitive lock = 6'b111001)
.RXCDR_HOLD_DURING_EIDLE ( 1'd1), // Hold RX CDR on electrical idle for Gen1/Gen2
.RXCDR_FR_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR frequency on electrical idle for Gen3
.RXCDR_PH_RESET_ON_EIDLE ( 1'd0), // Reset RX CDR phase on electrical idle for Gen3
//.RXCDRFREQRESET_TIME ( 5'b00001), //
//.RXCDRPHRESET_TIME ( 5'b00001), //
//---------- LPM Attributes --------------------------------------------
.RXLPM_HF_CFG (14'h00F0), // Optimized for silicon
.RXLPM_LF_CFG (14'h00F0), // Optimized for silicon
//---------- DFE Attributes --------------------------------------------
//.RXDFELPMRESET_TIME ( 7'b0001111), //
.RX_DFE_GAIN_CFG (23'h020FEA), // Optimized for GES, IES = 23'h001F0A
.RX_DFE_H2_CFG (12'b000000000000), // Optimized for GES
.RX_DFE_H3_CFG (12'b000001000000), // Optimized for GES
.RX_DFE_H4_CFG (11'b00011110000), // Optimized for GES
.RX_DFE_H5_CFG (11'b00011100000), // Optimized for GES
.RX_DFE_KL_CFG (13'b0000011111110), // Optimized for GES
.RX_DFE_KL_CFG2 (32'h3290D86C), // Optimized for GES, GTX new, CTLE 3 3 5, default = 32'h3010D90C
.RX_DFE_LPM_CFG (16'h0954), // Optimized for GES
.RX_DFE_LPM_HOLD_DURING_EIDLE ( 1'd1), // Optimized for PCIe
.RX_DFE_UT_CFG (17'b10001111000000000), // Optimized for GES, IES = 17'h08F00
.RX_DFE_VP_CFG (17'b00011111100000011), // Optimized for GES
.RX_DFE_XYD_CFG (13'h0000), // Optimized for 4.0
//---------- OS Attributes ---------------------------------------------
.RX_OS_CFG (13'b0000010000000), // Optimized for GES
//---------- Eye Scan Attributes ---------------------------------------
//.ES_CONTROL ( 6'd0), //
//.ES_ERRDET_EN ("FALSE"), //
.ES_EYE_SCAN_EN ("FALSE"), //
.ES_HORZ_OFFSET (12'd0), //
//.ES_PMA_CFG (10'd0), //
//.ES_PRESCALE ( 5'd0), //
//.ES_QUAL_MASK (80'd0), //
//.ES_QUALIFIER (80'd0), //
//.ES_SDATA_MASK (80'd0), //
//.ES_VERT_OFFSET ( 9'd0), //
//---------- TX Buffer Attributes --------------------------------------
.TXBUF_EN (PCIE_TXBUF_EN), //
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
//---------- RX Buffer Attributes --------------------------------------
.RXBUF_EN ("TRUE"), //
//.RX_BUFFER_CFG ( 6'd0), //
.RX_DEFER_RESET_BUF_EN ("TRUE"), //
.RXBUF_ADDR_MODE ("FULL"), //
.RXBUF_EIDLE_HI_CNT ( 4'd4), // Optimized for sim
.RXBUF_EIDLE_LO_CNT ( 4'd0), // Optimized for sim
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"), //
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"), //
.RXBUF_RESET_ON_EIDLE ("TRUE"), // PCIe
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), //
.RXBUF_THRESH_OVRD ("FALSE"), //
.RXBUF_THRESH_OVFLW (61), //
.RXBUF_THRESH_UNDFLW ( 4), //
//.RXBUFRESET_TIME ( 5'b00001), //
//---------- TX Sync Attributes ----------------------------------------
//.TXPH_CFG (16'h0780), //
.TXPH_MONITOR_SEL ( 5'd0), //
//.TXPHDLY_CFG (24'h084020), //
//.TXDLY_CFG (16'h001F), //
//.TXDLY_LCFG ( 9'h030), //
//.TXDLY_TAP_CFG (16'd0), //
//---------- RX Sync Attributes ----------------------------------------
//.RXPH_CFG (24'd0), //
.RXPH_MONITOR_SEL ( 5'd0), //
.RXPHDLY_CFG (24'h004020), // Optimized for sim
//.RXDLY_CFG (16'h001F), //
//.RXDLY_LCFG ( 9'h030), //
//.RXDLY_TAP_CFG (16'd0), //
.RX_DDI_SEL ( 6'd0), //
//---------- Comma Alignment Attributes --------------------------------
.ALIGN_COMMA_DOUBLE ("FALSE"), //
.ALIGN_COMMA_ENABLE (10'b1111111111), // PCIe
.ALIGN_COMMA_WORD ( 1), //
.ALIGN_MCOMMA_DET ("TRUE"), //
.ALIGN_MCOMMA_VALUE (10'b1010000011), //
.ALIGN_PCOMMA_DET ("TRUE"), //
.ALIGN_PCOMMA_VALUE (10'b0101111100), //
.DEC_MCOMMA_DETECT ("TRUE"), //
.DEC_PCOMMA_DETECT ("TRUE"), //
.DEC_VALID_COMMA_ONLY ("FALSE"), // PCIe
.SHOW_REALIGN_COMMA ("FALSE"), // PCIe
.RXSLIDE_AUTO_WAIT ( 7), //
.RXSLIDE_MODE ("PMA"), // PCIe
//---------- Channel Bonding Attributes --------------------------------
.CHAN_BOND_KEEP_ALIGN ("TRUE"), // PCIe
.CHAN_BOND_MAX_SKEW ( 7), //
.CHAN_BOND_SEQ_LEN ( 4), // PCIe
.CHAN_BOND_SEQ_1_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_1_1 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_2 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_3 (10'b0001001010), // D10.2 (4A) - TS1
.CHAN_BOND_SEQ_1_4 (10'b0110111100), // K28.5 (BC) - COM
.CHAN_BOND_SEQ_2_USE ("TRUE"), // PCIe
.CHAN_BOND_SEQ_2_ENABLE ( 4'b1111), //
.CHAN_BOND_SEQ_2_1 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_2 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_3 (10'b0001000101), // D5.2 (45) - TS2
.CHAN_BOND_SEQ_2_4 (10'b0110111100), // K28.5 (BC) - COM
.FTS_DESKEW_SEQ_ENABLE ( 4'b1111), //
.FTS_LANE_DESKEW_EN ("TRUE"), // PCIe
.FTS_LANE_DESKEW_CFG ( 4'b1111), //
//---------- Clock Correction Attributes -------------------------------
.CBCC_DATA_SOURCE_SEL ("DECODED"), //
.CLK_CORRECT_USE ("TRUE"), //
.CLK_COR_KEEP_IDLE ("TRUE"), // PCIe
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), //
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), //
.CLK_COR_PRECEDENCE ("TRUE"), //
.CLK_COR_REPEAT_WAIT ( 0), //
.CLK_COR_SEQ_LEN ( 1), //
.CLK_COR_SEQ_1_ENABLE ( 4'b1111), //
.CLK_COR_SEQ_1_1 (10'b0100011100), // K28.0 (1C) - SKP
.CLK_COR_SEQ_1_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_1_4 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_ENABLE ( 4'b0000), // Disabled
.CLK_COR_SEQ_2_USE ("FALSE"), //
.CLK_COR_SEQ_2_1 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_2 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_3 (10'b0000000000), // Disabled
.CLK_COR_SEQ_2_4 (10'b0000000000), // Disabled
//---------- 8b10b Attributes ------------------------------------------
.RX_DISPERR_SEQ_MATCH ("TRUE"), //
//---------- 64b/66b & 64b/67b Attributes ------------------------------
.GEARBOX_MODE (3'd0), //
.TXGEARBOX_EN ("FALSE"), //
.RXGEARBOX_EN ("FALSE"), //
//---------- PRBS & Loopback Attributes --------------------------------
.RXPRBS_ERR_LOOPBACK (1'd0), //
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"), //
//---------- OOB & SATA Attributes -------------------------------------
//.RXOOB_CFG ( 7'b0000110), //
//.SAS_MAX_COM (64), //
//.SAS_MIN_COM (36), //
//.SATA_BURST_SEQ_LEN ( 4'b1111), //
//.SATA_BURST_VAL ( 3'b100), //
//.SATA_CPLL_CFG ("VCO_3000MHZ"), //
//.SATA_EIDLE_VAL ( 3'b100), //
//.SATA_MAX_BURST ( 8), //
//.SATA_MAX_INIT (21), //
//.SATA_MAX_WAKE ( 7), //
//.SATA_MIN_BURST ( 4), //
//.SATA_MIN_INIT (12), //
//.SATA_MIN_WAKE ( 4), //
//---------- MISC ------------------------------------------------------
.DMONITOR_CFG (24'h000B01), // Optimized for debug
.RX_DEBUG_CFG (12'd0) // Optimized for GES
//.TST_RSV (32'd0), //
//.UCODEER_CLR ( 1'd0) //
)
gtxe2_channel_i
(
//---------- Clock -----------------------------------------------------
.GTGREFCLK (1'd0), //
.GTREFCLK0 (GT_GTREFCLK0), //
.GTREFCLK1 (1'd0), //
.GTNORTHREFCLK0 (1'd0), //
.GTNORTHREFCLK1 (1'd0), //
.GTSOUTHREFCLK0 (1'd0), //
.GTSOUTHREFCLK1 (1'd0), //
.QPLLCLK (GT_QPLLCLK), //
.QPLLREFCLK (GT_QPLLREFCLK), //
.TXUSRCLK (GT_TXUSRCLK), //
.RXUSRCLK (GT_RXUSRCLK), //
.TXUSRCLK2 (GT_TXUSRCLK2), //
.RXUSRCLK2 (GT_RXUSRCLK2), //
.TXSYSCLKSEL (GT_TXSYSCLKSEL), //
.RXSYSCLKSEL (GT_RXSYSCLKSEL), //
.TXOUTCLKSEL (txoutclksel), //
.RXOUTCLKSEL (rxoutclksel), //
.CPLLREFCLKSEL (3'd1), //
.CPLLLOCKDETCLK (1'd0), //
.CPLLLOCKEN (1'd1), //
.CLKRSVD ({2'd0, dmonitorclk, GT_OOBCLK}), // Optimized for debug
.TXOUTCLK (GT_TXOUTCLK), //
.RXOUTCLK (GT_RXOUTCLK), //
.TXOUTCLKFABRIC (), //
.RXOUTCLKFABRIC (), //
.TXOUTCLKPCS (), //
.RXOUTCLKPCS (), //
.CPLLLOCK (GT_CPLLLOCK), //
.CPLLREFCLKLOST (), //
.CPLLFBCLKLOST (), //
.RXCDRLOCK (GT_RXCDRLOCK), //
.GTREFCLKMONITOR (), //
//---------- Reset -----------------------------------------------------
.CPLLPD (cpllpd | GT_CPLLPD), //
.CPLLRESET (cpllrst | GT_CPLLRESET), //
.TXUSERRDY (GT_TXUSERRDY), //
.RXUSERRDY (GT_RXUSERRDY), //
.CFGRESET (1'd0), //
.GTRESETSEL (1'd0), //
.RESETOVRD (GT_RESETOVRD), //
.GTTXRESET (GT_GTTXRESET), //
.GTRXRESET (GT_GTRXRESET), //
.TXRESETDONE (GT_TXRESETDONE), //
.RXRESETDONE (GT_RXRESETDONE), //
//---------- TX Data ---------------------------------------------------
.TXDATA ({32'd0, GT_TXDATA}), //
.TXCHARISK ({ 4'd0, GT_TXDATAK}), //
.GTXTXP (GT_TXP), // GTX
.GTXTXN (GT_TXN), // GTX
//---------- RX Data ---------------------------------------------------
.GTXRXP (GT_RXP), // GTX
.GTXRXN (GT_RXN), // GTX
.RXDATA (rxdata), //
.RXCHARISK (rxdatak), //
//---------- Command ---------------------------------------------------
.TXDETECTRX (GT_TXDETECTRX), //
.TXPDELECIDLEMODE ( 1'd0), //
.RXELECIDLEMODE ( 2'd0), //
.TXELECIDLE (GT_TXELECIDLE), //
.TXCHARDISPMODE ({7'd0, GT_TXCOMPLIANCE}), //
.TXCHARDISPVAL ( 8'd0), //
.TXPOLARITY ( 1'b0), //
.RXPOLARITY (GT_RXPOLARITY), //
.TXPD (GT_TXPOWERDOWN), //
.RXPD (GT_RXPOWERDOWN), //
.TXRATE (GT_TXRATE), //
.RXRATE (GT_RXRATE), //
//---------- Electrical Command ----------------------------------------
.TXMARGIN (GT_TXMARGIN), //
.TXSWING (GT_TXSWING), //
.TXDEEMPH (GT_TXDEEMPH), //
.TXINHIBIT (1'd0), //
.TXBUFDIFFCTRL (3'b100), //
.TXDIFFCTRL (4'b1100), //
.TXPRECURSOR (GT_TXPRECURSOR), //
.TXPRECURSORINV (1'd0), //
.TXMAINCURSOR (GT_TXMAINCURSOR), //
.TXPOSTCURSOR (GT_TXPOSTCURSOR), //
.TXPOSTCURSORINV (1'd0), //
//---------- Status ----------------------------------------------------
.RXVALID (GT_RXVALID), //
.PHYSTATUS (GT_PHYSTATUS), //
.RXELECIDLE (GT_RXELECIDLE), //
.RXSTATUS (GT_RXSTATUS), //
.TXRATEDONE (GT_TXRATEDONE), //
.RXRATEDONE (GT_RXRATEDONE), //
//---------- DRP -------------------------------------------------------
.DRPCLK (GT_DRPCLK), //
.DRPADDR (GT_DRPADDR), //
.DRPEN (GT_DRPEN), //
.DRPDI (GT_DRPDI), //
.DRPWE (GT_DRPWE), //
.DRPDO (GT_DRPDO), //
.DRPRDY (GT_DRPRDY), //
//---------- PMA -------------------------------------------------------
.TXPMARESET (GT_TXPMARESET), //
.RXPMARESET (GT_RXPMARESET), //
.RXLPMEN (rxlpmen), //
.RXLPMHFHOLD ( 1'd0), //
.RXLPMHFOVRDEN ( 1'd0), //
.RXLPMLFHOLD ( 1'd0), //
.RXLPMLFKLOVRDEN ( 1'd0), //
.TXQPIBIASEN ( 1'd0), //
.TXQPISTRONGPDOWN ( 1'd0), //
.TXQPIWEAKPUP ( 1'd0), //
.RXQPIEN ( 1'd0), //
.PMARSVDIN ( 5'd0), //
.PMARSVDIN2 ( 5'd0), // GTX
.GTRSVD (16'd0), //
.TXQPISENP (), //
.TXQPISENN (), //
.RXQPISENP (), //
.RXQPISENN (), //
.DMONITOROUT (dmonitorout[7:0]), // GTX 8-bits
//---------- PCS -------------------------------------------------------
.TXPCSRESET (GT_TXPCSRESET), //
.RXPCSRESET (GT_RXPCSRESET), //
.PCSRSVDIN (16'd0), // [0]: 1 = TXRATE async, [1]: 1 = RXRATE async
.PCSRSVDIN2 ( 5'd0), //
.PCSRSVDOUT (), //
//---------- CDR -------------------------------------------------------
.RXCDRRESET (GT_RXCDRRESET), //
.RXCDRRESETRSV (1'd0), //
.RXCDRFREQRESET (GT_RXCDRFREQRESET), //
.RXCDRHOLD (1'b0), //
.RXCDROVRDEN (1'd0), //
//---------- DFE -------------------------------------------------------
.RXDFELPMRESET (GT_RXDFELPMRESET), //
.RXDFECM1EN (1'd0), //
.RXDFEVSEN (1'd0), //
.RXDFETAP2HOLD (1'd0), //
.RXDFETAP2OVRDEN (1'd0), //
.RXDFETAP3HOLD (1'd0), //
.RXDFETAP3OVRDEN (1'd0), //
.RXDFETAP4HOLD (1'd0), //
.RXDFETAP4OVRDEN (1'd0), //
.RXDFETAP5HOLD (1'd0), //
.RXDFETAP5OVRDEN (1'd0), //
.RXDFEAGCHOLD (GT_RX_CONVERGE), // Optimized for GES, Set to 1 after convergence
.RXDFEAGCOVRDEN (1'd0), //
.RXDFELFHOLD (1'd0), //
.RXDFELFOVRDEN (1'd1), // Optimized for GES
.RXDFEUTHOLD (1'd0), //
.RXDFEUTOVRDEN (1'd0), //
.RXDFEVPHOLD (1'd0), //
.RXDFEVPOVRDEN (1'd0), //
.RXDFEXYDEN (1'd0), //
.RXDFEXYDHOLD (1'd0), // GTX
.RXDFEXYDOVRDEN (1'd0), // GTX
.RXMONITORSEL (2'd0), //
.RXMONITOROUT (), //
//---------- OS --------------------------------------------------------
.RXOSHOLD (1'd0), //
.RXOSOVRDEN (1'd0), //
//---------- Eye Scan --------------------------------------------------
.EYESCANRESET (GT_EYESCANRESET), //
.EYESCANMODE (1'd0), //
.EYESCANTRIGGER (1'b0), //
.EYESCANDATAERROR (GT_EYESCANDATAERROR), //
//---------- TX Buffer -------------------------------------------------
.TXBUFSTATUS (), //
//---------- RX Buffer -------------------------------------------------
.RXBUFRESET (GT_RXBUFRESET), //
.RXBUFSTATUS (GT_RXBUFSTATUS), //
//---------- TX Sync ---------------------------------------------------
.TXPHDLYRESET (1'd0), //
.TXPHDLYTSTCLK (1'd0), //
.TXPHALIGN (GT_TXPHALIGN), //
.TXPHALIGNEN (GT_TXPHALIGNEN), //
.TXPHDLYPD (1'd0), //
.TXPHINIT (GT_TXPHINIT), //
.TXPHOVRDEN (1'd0), //
.TXDLYBYPASS (GT_TXDLYBYPASS), //
.TXDLYSRESET (GT_TXDLYSRESET), //
.TXDLYEN (GT_TXDLYEN), //
.TXDLYOVRDEN (1'd0), //
.TXDLYHOLD (1'd0), //
.TXDLYUPDOWN (1'd0), //
.TXPHALIGNDONE (GT_TXPHALIGNDONE), //
.TXPHINITDONE (GT_TXPHINITDONE), //
.TXDLYSRESETDONE (GT_TXDLYSRESETDONE), //
//---------- RX Sync ---------------------------------------------------
.RXPHDLYRESET (1'd0), //
.RXPHALIGN (GT_RXPHALIGN), //
.RXPHALIGNEN (GT_RXPHALIGNEN), //
.RXPHDLYPD (1'd0), //
.RXPHOVRDEN (1'd0), //
.RXDLYBYPASS (GT_RXDLYBYPASS), //
.RXDLYSRESET (GT_RXDLYSRESET), //
.RXDLYEN (GT_RXDLYEN), //
.RXDLYOVRDEN (1'd0), //
.RXDDIEN (GT_RXDDIEN), //
.RXPHALIGNDONE (GT_RXPHALIGNDONE), //
.RXPHMONITOR (), //
.RXPHSLIPMONITOR (), //
.RXDLYSRESETDONE (GT_RXDLYSRESETDONE), //
//---------- Comma Alignment -------------------------------------------
.RXCOMMADETEN ( 1'd1), //
.RXMCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXPCOMMAALIGNEN (!GT_GEN3), // 0 = disable comma alignment in Gen3
.RXSLIDE ( GT_RXSLIDE), //
.RXCOMMADET (GT_RXCOMMADET), //
.RXCHARISCOMMA (rxchariscomma), //
.RXBYTEISALIGNED (GT_RXBYTEISALIGNED), //
.RXBYTEREALIGN (GT_RXBYTEREALIGN), //
//---------- Channel Bonding -------------------------------------------
.RXCHBONDEN (GT_RXCHBONDEN), //
.RXCHBONDI (GT_RXCHBONDI), //
.RXCHBONDLEVEL (GT_RXCHBONDLEVEL), //
.RXCHBONDMASTER (GT_RXCHBONDMASTER), //
.RXCHBONDSLAVE (GT_RXCHBONDSLAVE), //
.RXCHANBONDSEQ (), //
.RXCHANISALIGNED (GT_RXCHANISALIGNED), //
.RXCHANREALIGN (), //
.RXCHBONDO (GT_RXCHBONDO), //
//---------- Clock Correction -----------------------------------------
.RXCLKCORCNT (), //
//---------- 8b10b -----------------------------------------------------
.TX8B10BBYPASS (8'd0), //
.TX8B10BEN (!GT_GEN3), // 0 = disable TX 8b10b in Gen3
.RX8B10BEN (!GT_GEN3), // 0 = disable RX 8b10b in Gen3
.RXDISPERR (GT_RXDISPERR), //
.RXNOTINTABLE (GT_RXNOTINTABLE), //
//---------- 64b/66b & 64b/67b -----------------------------------------
.TXHEADER (3'd0), //
.TXSEQUENCE (7'd0), //
.TXSTARTSEQ (1'd0), //
.RXGEARBOXSLIP (1'd0), //
.TXGEARBOXREADY (), //
.RXDATAVALID (), //
.RXHEADER (), //
.RXHEADERVALID (), //
.RXSTARTOFSEQ (), //
//---------- PRBS/Loopback ---------------------------------------------
.TXPRBSSEL (GT_TXPRBSSEL), //
.RXPRBSSEL (GT_RXPRBSSEL), //
.TXPRBSFORCEERR (GT_TXPRBSFORCEERR), //
.RXPRBSCNTRESET (GT_RXPRBSCNTRESET), //
.LOOPBACK (GT_LOOPBACK), //
.RXPRBSERR (GT_RXPRBSERR), //
//---------- OOB -------------------------------------------------------
.TXCOMINIT (1'd0), //
.TXCOMSAS (1'd0), //
.TXCOMWAKE (1'd0), //
.RXOOBRESET (1'd0), //
.TXCOMFINISH (), //
.RXCOMINITDET (), //
.RXCOMSASDET (), //
.RXCOMWAKEDET (), //
//---------- MISC ------------------------------------------------------
.SETERRSTATUS ( 1'd0), //
.TXDIFFPD ( 1'd0), //
.TXPISOPD ( 1'd0), //
.TSTIN (20'hFFFFF), //
.TSTOUT () // GTX
);
//---------- Default -------------------------------------------------------
assign dmonitorout[14:8] = 7'd0; // GTH GTP
assign GT_TXSYNCOUT = 1'd0; // GTH GTP
assign GT_TXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXSYNCOUT = 1'd0; // GTH GTP
assign GT_RXSYNCDONE = 1'd0; // GTH GTP
assign GT_RXPMARESETDONE = 1'd0; // GTH GTP
end
endgenerate
//---------- GT Wrapper Outputs ------------------------------------------------
assign GT_RXDATA = rxdata [31:0];
assign GT_RXDATAK = rxdatak[ 3:0];
assign GT_RXCHARISCOMMA = rxchariscomma[ 3:0];
assign GT_DMONITOROUT = dmonitorout;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:04:19 12/8/2013
// Design Name: Karpentium_Processor_III
// Module Name: C:/Documents and Settings/Administrator/My Documents/EE480/Karpentium_Processor_III/Karpentium_vtf.v
// Project Name: Karpentium_Processor_III
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Karpentium_Processor_III
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Karpentium_vtf;
// Inputs
reg clk;
reg clr;
reg [15:0] in;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
Karpentium_Processor_III uut (
.clk(clk),
.clr(clr),
.in(in),
.out(out)
);
//Internal Connections
wire [15:0]MEM [63:0];
wire [15:0]PM [63:0];
wire [15:0] dataBUS;
wire [15:0]accumulator;
wire [5:0] PC_IN;
wire [5:0] MAR_out;
wire [15:0] MDR;
wire [5:0] PC, MAR_in, MAR;
wire [1:0] c0;
wire [1:0] c4;
wire [2:0] c_line;
wire [7:0] en_line;
wire [4:0] s_line;
wire [5:0] curr_state,next_state;
wire [15:0] instr;
wire [3:0] opcode;
assign dataBUS = uut.dataBUS;
assign MAR_out = uut.MAR_out;
assign PC_IN = uut.PC.in;
assign opcode = uut.IR.instr[15:12];
assign instr = uut.IR.instr;
assign c0 = {uut.c0};
assign c_line = {uut.c3,uut.c2,uut.c1};
assign c4 = {uut.c4};
assign en_line = {uut.en7,uut.en6,uut.en5,uut.en4,uut.en3,uut.en2,uut.en1,uut.en0};
assign s_line = {uut.s2,uut.s1};
assign curr_state = uut.Controller.curr_state;
assign next_state = uut.Controller.next_state;
assign PC = uut.PC_out;
assign MDR = uut.MDR.data;
assign MAR_in = uut.MAR_in;
assign MAR = uut.MAR.out;
assign accumulator = uut.ALU.accumulator;
genvar i;
for(i=0;i<64;i=i+1) begin: Memory
assign MEM[i] = uut.RAM.MEM[i];
end
for(i=0;i<64;i=i+1) begin: PrograMEM
assign PM[i] = uut.PM.pdra[i];
end
initial begin
// Initialize Inputs
clk = 0;
clr = 1;
in = 0;
// Add stimulus here
#25 clr = 0;
end
always begin
#20 clk = ~clk;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tb_cmd_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:24 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: 7 Series
//Design Name: PRBS_Generator
//Purpose:
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_tg_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 10, // LFSR shift register length
parameter nCK_PER_CLK = 4 // output:internal clock freq ratio
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
output [2*nCK_PER_CLK-1:0] prbs_o, // generated address
// ReSeedcounter used to indicate when pseudo-PRBS sequence has reached
// the end of it's cycle. May not be needed, but for now included to
// maintain compatibility with current TG code
output [31:0] ReSeedcounter_o
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = (2**PRBS_WIDTH) / (2*nCK_PER_CLK);
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg [PRBS_WIDTH-1:0] lfsr_reg_r;
wire [PRBS_WIDTH-1:0] next_lfsr_reg;
reg [PRBS_WIDTH-1:0] reseed_cnt_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
genvar i;
//***************************************************************************
assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}}, reseed_cnt_r};
always @ (posedge clk_i)
if (rst_i)
reseed_cnt_r <= 'b0;
else if (clk_en_i)
if (reseed_cnt_r == {PRBS_WIDTH {1'b1}})
reseed_cnt_r <= 'b0;
else
reseed_cnt_r <= reseed_cnt_r + 1;
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
if (rst_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
// Load initial seed or update LFSR contents
always @(posedge clk_i)
if (rst_i)
lfsr_reg_r <= #TCQ prbs_seed_i;
else if (clk_en_i)
if (reseed_prbs_r)
lfsr_reg_r <= #TCQ prbs_seed_i;
else begin
lfsr_reg_r <= #TCQ next_lfsr_reg;
end
// Calculate next set of nCK_PER_CLK samplse for LFSR
// Basically we calculate all PRBS_WIDTH samples in parallel, rather
// than serially shifting the LFSR to determine future sample values.
// Shifting is possible, but requires multiple shift registers to be
// instantiated because the fabric clock frequency is running at a
// fraction of the output clock frequency
generate
if (PRBS_WIDTH == 8) begin: gen_next_lfsr_prbs8
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[7] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[5] ^
lfsr_reg_r[4] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[4] ^
lfsr_reg_r[3] ^ lfsr_reg_r[2]) ;
assign next_lfsr_reg[5] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[3] ^
lfsr_reg_r[2] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[2] ^
lfsr_reg_r[1] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[1] ^
lfsr_reg_r[0] ^ next_lfsr_reg[7]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[2] ^ lfsr_reg_r[0] ^
next_lfsr_reg[7] ^ next_lfsr_reg[6]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[1] ^ next_lfsr_reg[7] ^
next_lfsr_reg[6] ^ next_lfsr_reg[5]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[0] ^ next_lfsr_reg[6] ^
next_lfsr_reg[5] ^ next_lfsr_reg[4]);
end
end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign next_lfsr_reg[9] = lfsr_reg_r[5];
assign next_lfsr_reg[8] = lfsr_reg_r[4];
assign next_lfsr_reg[7] = lfsr_reg_r[3];
assign next_lfsr_reg[6] = lfsr_reg_r[2];
assign next_lfsr_reg[5] = lfsr_reg_r[1];
assign next_lfsr_reg[4] = lfsr_reg_r[0];
assign next_lfsr_reg[3] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign next_lfsr_reg[9] = lfsr_reg_r[1];
assign next_lfsr_reg[8] = lfsr_reg_r[0];
assign next_lfsr_reg[7] = ~(lfsr_reg_r[9] ^ lfsr_reg_r[6]);
assign next_lfsr_reg[6] = ~(lfsr_reg_r[8] ^ lfsr_reg_r[5]);
assign next_lfsr_reg[5] = ~(lfsr_reg_r[7] ^ lfsr_reg_r[4]);
assign next_lfsr_reg[4] = ~(lfsr_reg_r[6] ^ lfsr_reg_r[3]);
assign next_lfsr_reg[3] = ~(lfsr_reg_r[5] ^ lfsr_reg_r[2]);
assign next_lfsr_reg[2] = ~(lfsr_reg_r[4] ^ lfsr_reg_r[1]);
assign next_lfsr_reg[1] = ~(lfsr_reg_r[3] ^ lfsr_reg_r[0]);
assign next_lfsr_reg[0] = ~(lfsr_reg_r[2] ^ next_lfsr_reg[7]);
end
end
endgenerate
// Output highest (2*nCK_PER_CLK) taps of LFSR - note that the "earliest"
// tap is highest tap (e.g. for an 8-bit LFSR, tap[7] contains the first
// data sent out the shift register), therefore tap[PRBS_WIDTH-1] must be
// routed to bit[0] of the output, tap[PRBS_WIDTH-2] to bit[1] of the
// output, etc.
generate
for (i = 0; i < 2*nCK_PER_CLK; i = i + 1) begin: gen_prbs_transpose
assign prbs_o[i] = lfsr_reg_r[PRBS_WIDTH-1-i];
end
endgenerate
endmodule
|
// $Id: aeMB_regf.v,v 1.3 2007-11-10 16:39:38 sybreon Exp $
//
// AEMB REGISTER FILE
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <[email protected]>
//
// This file is part of AEMB.
//
// AEMB is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as
// published by the Free Software Foundation, either version 3 of the
// License, or (at your option) any later version.
//
// AEMB is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
// Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2007/11/09 20:51:52 sybreon
// Added GET/PUT support through a FSL bus.
//
// Revision 1.1 2007/11/02 03:25:41 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
// Code compatible with -O0/1/2/3/s generated code.
//
module aeMB_regf (/*AUTOARG*/
// Outputs
rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
// Inputs
rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
);
// INTERNAL
output [31:0] rREGA, rREGB;
output [31:0] rDWBDI;
input [5:0] rOPC;
input [4:0] rRA, rRB, rRW, rRD;
input [1:0] rMXDST;
input [31:2] rPCLNK;
input [31:0] rRESULT;
input [3:0] rDWBSEL;
input rBRA, rDLY;
// DATA WISHBONE
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
// FSL WISHBONE
output [31:0] fsl_dat_o;
input [31:0] fsl_dat_i;
// SYSTEM
input gclk, grst, gena;
// --- LOAD SIZER ----------------------------------------------
// Moves the data bytes around depending on the size of the
// operation.
wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
reg [31:0] rDWBDI;
reg [1:0] rSIZ;
always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
/* 51.2
case (rSIZ)
// FSL
2'o3: rDWBDI <= wFSLDI;
// 32'bit
2'o2: rDWBDI <= wDWBDI;
// 16'bit
2'o1: case (rRESULT[1])
1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
endcase // case (rRESULT[1])
// 8'bit
2'o0: case (rRESULT[1:0])
2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
endcase // case (rRESULT[1:0])
endcase // case (rSIZ)
*/
/* 50.6
case ({rSIZ, rRESULT[1:0]})
// FSL
4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
// 32'bit
4'h8: rDWBDI <= wDWBDI;
// 16'bit
4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 8'bit
4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
default: rDWBDI <= 32'hX;
endcase // case (rSIZ)
*/
// 52.0
case (rDWBSEL)
// 8'bit
4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
// 16'bit
4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
// 32'bit
4'hF: rDWBDI <= wDWBDI;
// FSL
4'h0: rDWBDI <= wFSLDI;
// Undefined
default: rDWBDI <= 32'hX;
endcase
end
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rSIZ <= 2'h0;
// End of automatics
end else if (gena) begin
rSIZ <= rOPC[1:0];
end
// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
// LUT RAM implementation is smaller and faster. R0 gets written
// during reset with 0x00 and doesn't change after.
reg [31:0] mARAM[0:31],
mBRAM[0:31],
mDRAM[0:31];
wire [31:0] rREGW = mDRAM[rRW];
wire [31:0] rREGD = mDRAM[rRD];
assign rREGA = mARAM[rRA];
assign rREGB = mBRAM[rRB];
wire fRDWE = |rRW;
reg [31:0] xWDAT;
always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
or rRESULT)
case (rMXDST)
2'o2: xWDAT <= rDWBDI;
2'o1: xWDAT <= {rPCLNK, 2'o0};
2'o0: xWDAT <= rRESULT;
2'o3: xWDAT <= rREGW; // No change
endcase // case (rMXDST)
always @(posedge gclk)
if (grst | fRDWE) begin
mARAM[rRW] <= xWDAT;
mBRAM[rRW] <= xWDAT;
mDRAM[rRW] <= xWDAT;
end
// --- STORE SIZER ---------------------------------------------
// Replicates the data bytes across depending on the size of the
// operation.
reg [31:0] rDWBDO, xDWBDO;
wire [31:0] xFSL;
wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
assign fsl_dat_o = rDWBDO;
assign xFSL = (fFFWD_M) ? rDWBDI :
(fFFWD_R) ? rRESULT :
rREGA;
wire [31:0] xDST;
wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
assign dwb_dat_o = rDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
case (rOPC[1:0])
// 8'bit
2'h0: xDWBDO <= {(4){xDST[7:0]}};
// 16'bit
2'h1: xDWBDO <= {(2){xDST[15:0]}};
// 32'bit
2'h2: xDWBDO <= xDST;
// FSL
2'h3: xDWBDO <= xFSL;
//default: xDWBDO <= 32'hX;
endcase // case (rOPC[1:0])
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDO <= 32'h0;
// End of automatics
end else if (gena) begin
rDWBDO <= #1 xDWBDO;
end
// --- SIMULATION ONLY ------------------------------------------
// Randomise memory to simulate real-world memory
// synopsys translate_off
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
mARAM[i] <= $random;
mBRAM[i] <= $random;
mDRAM[i] <= $random;
end
end
// synopsys translate_on
endmodule // aeMB_regf
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 2;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Harness
-- Description: Arnes para pruebas del modulo test_engine_network_core.
En particular, este arnes conecta todos los puertos de
la red con 'inyectores / receptores' de paquetes.
-- Dependencies: -- system.vh
-- Parameters:
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 11 de Diciembre 2015
*/
`include "system.vh"
module harness_TENC #(
parameter X_WIDTH = 5,
parameter Y_WIDTH = 5,
parameter PROC_CYCLES = 5
)
();
localparam CYCLE = 4;
localparam Tsetup = CYCLE * 0.2;
localparam Thold = CYCLE * 0.2;
reg clk;
reg reset;
// -- inports ----------------------------------------------- >>>>>
wire [0:(X_WIDTH * `CHANNEL_WIDTH)-1] xneg_inports;
wire [0: X_WIDTH-1] xneg_credits_outports;
wire [0:(X_WIDTH * `CHANNEL_WIDTH)-1] xpos_inports;
wire [0: X_WIDTH-1] xpos_credits_outports;
// -- outports ----------------------------------------------- >>>>>
wire [0:(X_WIDTH * `CHANNEL_WIDTH)-1] xneg_outports;
wire [0: X_WIDTH-1] xneg_credits_inports;
wire [0:(X_WIDTH * `CHANNEL_WIDTH)-1] xpos_outports;
wire [0: X_WIDTH-1] xpos_credits_inports;
// -- UUT -------------------------------------------------------- >>>>>
test_engine_network_core
#(
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH),
.PROC_CYCLES (PROC_CYCLES)
)
TENC_UUT
(
.clk (clk),
.reset (reset),
// -- rx :: channels ---------------------------------------- >>>>>
.xneg_inports_din (xneg_inports),
.xneg_credits_dout (xneg_credits_outports),
.xpos_inports_din (xpos_inports),
.xpos_credits_dout (xpos_credits_outports),
// -- tx :: channels ----------------------------------------- >>>>>
.xneg_outports_dout (xneg_outports),
.xneg_credits_din (xneg_credits_inports),
.xpos_outports_dout (xpos_outports),
.xpos_credits_din (xpos_credits_inports)
);
// -- Bus Behaivoral Model --------------------------------------- >>>>>
/*
-- Descripcion: Generacion de 'alimentadores / receptores' de
paquetes para cada puerto IO de la red. Cada
puerto de IO esta servido por los siguientes
modulos:
* packet_generator: Modulo de soporte.
Ofrece tasks para la generacion de
paquetes validos para la red.
Despues de la ejecucion de una rutina
de generacion de paquete, el resultado
puede ser accedido por medio de la
variable 'packet'.
* source: Modulo para el envio de paquetes.
Proporciona el servicio de interfaz para
la inyeccion de un paquete a la red.
Este modulo se encarga de la
descomposicion de un paquete en flits, y
el manejo del mecanismo de control de
flujo.
El modulo source interactua con la red
como si se tratase de otro nodo mas de la
red.
* sink: Modulo receptor de paquetes. Se
encarga de la recepcion de paquetes, asi
como de su descomposicion en flits y
campos de datos.
El modulo tambien lleva a cabo todas las
tareas relacionadas con el control de
flujo de datos, interactuando con la red
como si se tratase de otro nodo mas.
*/
genvar rows;
// -- xneg ports --------------------------------------------- >>>>>
generate
for (rows = 0; rows < Y_WIDTH; rows = rows + 1)
begin:xneg_ports
// -- Generador de paquetes ---------------------- >>>>>
packet_generator
#(
.PORT (`X_NEG),
.X_LOCAL (0),
.Y_LOCAL (rows + 1),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
packet_generator
();
// -- Inyector de paquetes ----------------------- >>>>>
source
#(
.Thold (Thold),
.PORT (`X_NEG),
.ID (rows)
)
source
(
.clk (clk),
.channel_out(xneg_inports [rows*`CHANNEL_WIDTH:(rows*`CHANNEL_WIDTH+`CHANNEL_WIDTH)-1]),
.credit_in (xneg_credits_outports [rows])
);
// -- Receptor de paquetes ----------------------- >>>>>
sink
#(
.Thold (Thold),
.PORT (`X_NEG),
.ID (rows)
)
sink
(
.clk (clk),
.channel_in (xneg_outports [rows*`CHANNEL_WIDTH:(rows*`CHANNEL_WIDTH+`CHANNEL_WIDTH)-1]),
.credit_out (xneg_credits_inports [rows])
);
end
endgenerate
// -- xpos ports --------------------------------------------- >>>>>
generate
for (rows = 0; rows < Y_WIDTH; rows = rows + 1)
begin:xpos_ports
// -- Generador de paquetes ---------------------- >>>>>
packet_generator
#(
.PORT (`X_POS),
.X_LOCAL (X_WIDTH + 1),
.Y_LOCAL (rows + 1),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
packet_generator
();
// -- Inyector de paquetes ----------------------- >>>>>
source
#(
.Thold (Thold),
.PORT (`X_POS),
.ID (rows)
)
source
(
.clk (clk),
.channel_out(xpos_inports [rows*`CHANNEL_WIDTH:(rows*`CHANNEL_WIDTH+`CHANNEL_WIDTH)-1]),
.credit_in (xpos_credits_outports [rows])
);
// -- Receptor de paquetes ----------------------- >>>>>
sink
#(
.Thold (Thold),
.PORT (`X_POS),
.ID (rows)
)
sink
(
.clk (clk),
.channel_in (xpos_outports [rows*`CHANNEL_WIDTH:(rows*`CHANNEL_WIDTH+`CHANNEL_WIDTH)-1]),
.credit_out (xpos_credits_inports [rows])
);
end
endgenerate
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2.0) clk = 1'b0;
#(CYCLE/2.0) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(10)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule // harness_TENC |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:49:47 2016
/////////////////////////////////////////////////////////////
module ACA_I_N32_Q8_DW01_add_J46_0 ( A, B, CI, SUM, CO );
input [8:0] A;
input [8:0] B;
output [8:0] SUM;
input CI;
output CO;
wire n35, n36, n37, n38, n39, n40, n41, n42, n43, n44;
NOR2X1TS U13 ( .A(A[6]), .B(B[6]), .Y(n42) );
NOR2X1TS U14 ( .A(A[4]), .B(B[4]), .Y(n39) );
OAI2BB2X2TS U15 ( .B0(n37), .B1(n36), .A0N(A[2]), .A1N(B[2]), .Y(n38) );
CLKAND2X2TS U16 ( .A(A[0]), .B(B[0]), .Y(n35) );
AOI222X1TS U17 ( .A0(B[1]), .A1(A[1]), .B0(B[1]), .B1(n35), .C0(A[1]), .C1(
n35), .Y(n37) );
NOR2X1TS U18 ( .A(A[2]), .B(B[2]), .Y(n36) );
AOI222X1TS U19 ( .A0(B[3]), .A1(A[3]), .B0(B[3]), .B1(n38), .C0(A[3]), .C1(
n38), .Y(n40) );
OAI2BB2X1TS U20 ( .B0(n40), .B1(n39), .A0N(A[4]), .A1N(B[4]), .Y(n41) );
AOI222X1TS U21 ( .A0(B[5]), .A1(A[5]), .B0(B[5]), .B1(n41), .C0(A[5]), .C1(
n41), .Y(n43) );
OAI2BB2X1TS U22 ( .B0(n43), .B1(n42), .A0N(A[6]), .A1N(B[6]), .Y(n44) );
CMPR32X2TS U23 ( .A(A[7]), .B(B[7]), .C(n44), .CO(SUM[8]), .S(SUM[7]) );
initial $sdf_annotate("ACA_I_N32_Q8_syn.sdf");
endmodule
module ACA_I_N32_Q8_DW01_add_J46_1 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44;
CLKAND2X2TS U13 ( .A(B[0]), .B(A[0]), .Y(n34) );
BUFX3TS U14 ( .A(A[1]), .Y(n33) );
BUFX3TS U15 ( .A(B[1]), .Y(n32) );
XOR2X1TS U16 ( .A(A[7]), .B(n44), .Y(SUM[7]) );
AOI222X2TS U17 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n36), .C0(A[2]), .C1(
n36), .Y(n38) );
OAI21X4TS U18 ( .A0(n33), .A1(n32), .B0(n34), .Y(n35) );
OAI2BB1X1TS U19 ( .A0N(n32), .A1N(n33), .B0(n35), .Y(n36) );
NOR2X1TS U20 ( .A(A[3]), .B(B[3]), .Y(n37) );
OAI2BB2X2TS U21 ( .B0(n38), .B1(n37), .A0N(A[3]), .A1N(B[3]), .Y(n39) );
AOI222X1TS U22 ( .A0(B[4]), .A1(A[4]), .B0(B[4]), .B1(n39), .C0(A[4]), .C1(
n39), .Y(n41) );
NOR2X1TS U23 ( .A(A[5]), .B(B[5]), .Y(n40) );
OAI2BB2X2TS U24 ( .B0(n41), .B1(n40), .A0N(A[5]), .A1N(B[5]), .Y(n42) );
AOI222X1TS U25 ( .A0(B[6]), .A1(A[6]), .B0(B[6]), .B1(n42), .C0(A[6]), .C1(
n42), .Y(n43) );
XNOR2X2TS U26 ( .A(n43), .B(B[7]), .Y(n44) );
initial $sdf_annotate("ACA_I_N32_Q8_syn.sdf");
endmodule
module ACA_I_N32_Q8_DW01_add_J46_2 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44;
CLKAND2X2TS U13 ( .A(B[0]), .B(A[0]), .Y(n34) );
XOR2X1TS U14 ( .A(A[7]), .B(n44), .Y(SUM[7]) );
AOI222X2TS U15 ( .A0(n32), .A1(n33), .B0(n32), .B1(n36), .C0(n33), .C1(n36),
.Y(n38) );
CLKBUFX2TS U16 ( .A(B[2]), .Y(n32) );
CLKBUFX2TS U17 ( .A(A[2]), .Y(n33) );
OAI21X4TS U18 ( .A0(A[1]), .A1(B[1]), .B0(n34), .Y(n35) );
OAI2BB1X1TS U19 ( .A0N(B[1]), .A1N(A[1]), .B0(n35), .Y(n36) );
NOR2X1TS U20 ( .A(A[3]), .B(B[3]), .Y(n37) );
OAI2BB2X2TS U21 ( .B0(n38), .B1(n37), .A0N(A[3]), .A1N(B[3]), .Y(n39) );
AOI222X1TS U22 ( .A0(B[4]), .A1(A[4]), .B0(B[4]), .B1(n39), .C0(A[4]), .C1(
n39), .Y(n41) );
NOR2X1TS U23 ( .A(A[5]), .B(B[5]), .Y(n40) );
OAI2BB2X2TS U24 ( .B0(n41), .B1(n40), .A0N(A[5]), .A1N(B[5]), .Y(n42) );
AOI222X1TS U25 ( .A0(B[6]), .A1(A[6]), .B0(B[6]), .B1(n42), .C0(A[6]), .C1(
n42), .Y(n43) );
XNOR2X2TS U26 ( .A(n43), .B(B[7]), .Y(n44) );
initial $sdf_annotate("ACA_I_N32_Q8_syn.sdf");
endmodule
module ACA_I_N32_Q8_DW01_add_J46_3 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44;
CLKAND2X2TS U13 ( .A(B[0]), .B(A[0]), .Y(n34) );
XOR2X1TS U14 ( .A(A[7]), .B(n44), .Y(SUM[7]) );
AOI222X2TS U15 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n36), .C0(A[2]), .C1(
n36), .Y(n38) );
CLKBUFX2TS U16 ( .A(B[3]), .Y(n32) );
CLKBUFX2TS U17 ( .A(A[3]), .Y(n33) );
OAI21X4TS U18 ( .A0(A[1]), .A1(B[1]), .B0(n34), .Y(n35) );
OAI2BB1X1TS U19 ( .A0N(B[1]), .A1N(A[1]), .B0(n35), .Y(n36) );
NOR2X1TS U20 ( .A(n33), .B(n32), .Y(n37) );
OAI2BB2X2TS U21 ( .B0(n38), .B1(n37), .A0N(n33), .A1N(n32), .Y(n39) );
AOI222X1TS U22 ( .A0(B[4]), .A1(A[4]), .B0(B[4]), .B1(n39), .C0(A[4]), .C1(
n39), .Y(n41) );
NOR2X1TS U23 ( .A(A[5]), .B(B[5]), .Y(n40) );
OAI2BB2X2TS U24 ( .B0(n41), .B1(n40), .A0N(A[5]), .A1N(B[5]), .Y(n42) );
AOI222X1TS U25 ( .A0(B[6]), .A1(A[6]), .B0(B[6]), .B1(n42), .C0(A[6]), .C1(
n42), .Y(n43) );
XNOR2X2TS U26 ( .A(n43), .B(B[7]), .Y(n44) );
initial $sdf_annotate("ACA_I_N32_Q8_syn.sdf");
endmodule
module ACA_I_N32_Q8 ( in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218,
SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4,
SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6,
SYNOPSYS_UNCONNECTED_7, SYNOPSYS_UNCONNECTED_8,
SYNOPSYS_UNCONNECTED_9, SYNOPSYS_UNCONNECTED_10,
SYNOPSYS_UNCONNECTED_11, SYNOPSYS_UNCONNECTED_12,
SYNOPSYS_UNCONNECTED_13, SYNOPSYS_UNCONNECTED_14,
SYNOPSYS_UNCONNECTED_15, SYNOPSYS_UNCONNECTED_16,
SYNOPSYS_UNCONNECTED_17, SYNOPSYS_UNCONNECTED_18,
SYNOPSYS_UNCONNECTED_19, SYNOPSYS_UNCONNECTED_20,
SYNOPSYS_UNCONNECTED_21, SYNOPSYS_UNCONNECTED_22,
SYNOPSYS_UNCONNECTED_23, SYNOPSYS_UNCONNECTED_24,
SYNOPSYS_UNCONNECTED_25, SYNOPSYS_UNCONNECTED_26,
SYNOPSYS_UNCONNECTED_27, SYNOPSYS_UNCONNECTED_28;
ACA_I_N32_Q8_DW01_add_J46_0 add_x_25 ( .A({1'b0, in1[31:27], n20, n26,
in1[24]}), .B({1'b0, in2[31:27], n18, n24, in2[24]}), .CI(1'b0), .SUM(
{res[32:31], SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4, SYNOPSYS_UNCONNECTED_5,
SYNOPSYS_UNCONNECTED_6, SYNOPSYS_UNCONNECTED_7}) );
ACA_I_N32_Q8_DW01_add_J46_1 add_x_24 ( .A({in1[30:26], n26, in1[24:23]}),
.B({in2[30:26], n24, in2[24:23]}), .CI(1'b0), .SUM({res[30],
SYNOPSYS_UNCONNECTED_8, SYNOPSYS_UNCONNECTED_9,
SYNOPSYS_UNCONNECTED_10, SYNOPSYS_UNCONNECTED_11,
SYNOPSYS_UNCONNECTED_12, SYNOPSYS_UNCONNECTED_13,
SYNOPSYS_UNCONNECTED_14}) );
ACA_I_N32_Q8_DW01_add_J46_2 add_x_23 ( .A({in1[29:27], n20, in1[25:22]}),
.B({in2[29:27], n18, in2[25:22]}), .CI(1'b0), .SUM({res[29],
SYNOPSYS_UNCONNECTED_15, SYNOPSYS_UNCONNECTED_16,
SYNOPSYS_UNCONNECTED_17, SYNOPSYS_UNCONNECTED_18,
SYNOPSYS_UNCONNECTED_19, SYNOPSYS_UNCONNECTED_20,
SYNOPSYS_UNCONNECTED_21}) );
ACA_I_N32_Q8_DW01_add_J46_3 add_x_22 ( .A(in1[28:21]), .B(in2[28:21]), .CI(
1'b0), .SUM({res[28], SYNOPSYS_UNCONNECTED_22, SYNOPSYS_UNCONNECTED_23,
SYNOPSYS_UNCONNECTED_24, SYNOPSYS_UNCONNECTED_25,
SYNOPSYS_UNCONNECTED_26, SYNOPSYS_UNCONNECTED_27,
SYNOPSYS_UNCONNECTED_28}) );
INVX2TS U2 ( .A(n38), .Y(n40) );
CLKAND2X2TS U3 ( .A(in2[16]), .B(in1[16]), .Y(n6) );
CLKAND2X2TS U4 ( .A(in2[17]), .B(in1[17]), .Y(n7) );
CLKAND2X2TS U5 ( .A(in2[18]), .B(in1[18]), .Y(n8) );
CLKAND2X2TS U6 ( .A(in2[15]), .B(in1[15]), .Y(n9) );
INVX3TS U7 ( .A(in2[20]), .Y(n33) );
CLKINVX6TS U8 ( .A(in1[20]), .Y(n38) );
OAI21X2TS U9 ( .A0(in1[14]), .A1(in2[14]), .B0(n4), .Y(n145) );
AND2X4TS U10 ( .A(n34), .B(n39), .Y(n2) );
AND2X4TS U11 ( .A(n32), .B(in1[19]), .Y(n3) );
INVX2TS U12 ( .A(in1[19]), .Y(n36) );
XOR2X1TS U13 ( .A(n30), .B(n171), .Y(res[22]) );
XOR2X1TS U14 ( .A(n11), .B(n189), .Y(res[24]) );
XOR2X1TS U15 ( .A(n28), .B(n180), .Y(res[23]) );
AOI222X2TS U16 ( .A0(n27), .A1(n28), .B0(n27), .B1(n187), .C0(n28), .C1(n187), .Y(n188) );
AOI222X2TS U17 ( .A0(n29), .A1(n30), .B0(n29), .B1(n178), .C0(n30), .C1(n178), .Y(n179) );
AOI222X2TS U18 ( .A0(n35), .A1(n16), .B0(n35), .B1(n169), .C0(n16), .C1(n169), .Y(n170) );
CLKAND2X2TS U19 ( .A(in2[4]), .B(in1[4]), .Y(n73) );
CLKAND2X2TS U20 ( .A(in2[6]), .B(in1[6]), .Y(n89) );
CLKAND2X2TS U21 ( .A(in2[7]), .B(in1[7]), .Y(n97) );
CLKAND2X2TS U22 ( .A(in2[9]), .B(in1[9]), .Y(n113) );
CLKAND2X2TS U23 ( .A(in2[3]), .B(in1[3]), .Y(n65) );
CLKAND2X2TS U24 ( .A(in2[12]), .B(in1[12]), .Y(n137) );
CLKAND2X2TS U25 ( .A(in2[11]), .B(in1[11]), .Y(n129) );
CLKAND2X2TS U26 ( .A(in2[2]), .B(in1[2]), .Y(n57) );
CLKAND2X2TS U27 ( .A(in2[5]), .B(in1[5]), .Y(n81) );
CLKAND2X2TS U28 ( .A(in2[8]), .B(in1[8]), .Y(n105) );
XOR2X2TS U29 ( .A(in1[27]), .B(n218), .Y(res[27]) );
XOR2X1TS U30 ( .A(n40), .B(n153), .Y(res[20]) );
XOR2X1TS U31 ( .A(n72), .B(n71), .Y(res[10]) );
XOR2X1TS U32 ( .A(n120), .B(n119), .Y(res[16]) );
XOR2X1TS U33 ( .A(n136), .B(n135), .Y(res[18]) );
XOR2X1TS U34 ( .A(n144), .B(n143), .Y(res[19]) );
XOR2X1TS U35 ( .A(n88), .B(n87), .Y(res[12]) );
XOR2X1TS U36 ( .A(n104), .B(n103), .Y(res[14]) );
XOR2X1TS U37 ( .A(n42), .B(n41), .Y(res[7]) );
XOR2X1TS U38 ( .A(n56), .B(n55), .Y(res[8]) );
XOR2X1TS U39 ( .A(n128), .B(n127), .Y(res[17]) );
XOR2X1TS U40 ( .A(n64), .B(n63), .Y(res[9]) );
XOR2X1TS U41 ( .A(n96), .B(n95), .Y(res[13]) );
XOR2X1TS U42 ( .A(n112), .B(n111), .Y(res[15]) );
XOR2X1TS U43 ( .A(n80), .B(n79), .Y(res[11]) );
AOI222X2TS U44 ( .A0(in2[17]), .A1(in1[17]), .B0(in2[17]), .B1(n149), .C0(
in1[17]), .C1(n149), .Y(n150) );
OAI21X2TS U45 ( .A0(n39), .A1(n34), .B0(n3), .Y(n199) );
INVX6TS U46 ( .A(n31), .Y(n32) );
INVX6TS U47 ( .A(n33), .Y(n34) );
INVX4TS U48 ( .A(n38), .Y(n39) );
INVX8TS U49 ( .A(in2[19]), .Y(n31) );
XOR2X1TS U50 ( .A(in1[7]), .B(in2[7]), .Y(n41) );
XOR2X1TS U51 ( .A(in1[10]), .B(in2[10]), .Y(n71) );
NOR2X1TS U52 ( .A(in1[16]), .B(in2[16]), .Y(n147) );
AOI222X2TS U53 ( .A0(in2[23]), .A1(in1[23]), .B0(in2[23]), .B1(n203), .C0(
in1[23]), .C1(n203), .Y(n205) );
OAI2BB2X2TS U54 ( .B0(n195), .B1(n211), .A0N(n28), .A1N(n27), .Y(n196) );
XOR2X1TS U55 ( .A(in1[25]), .B(n198), .Y(res[25]) );
AOI222X2TS U56 ( .A0(in2[24]), .A1(in1[24]), .B0(in2[24]), .B1(n213), .C0(
in1[24]), .C1(n213), .Y(n215) );
XNOR2X1TS U57 ( .A(n197), .B(in2[25]), .Y(n198) );
AOI222X2TS U58 ( .A0(n10), .A1(n11), .B0(in2[24]), .B1(n196), .C0(in1[24]),
.C1(n196), .Y(n197) );
CLKAND2X2TS U59 ( .A(in2[1]), .B(in1[1]), .Y(n49) );
CLKAND2X2TS U60 ( .A(in2[10]), .B(in1[10]), .Y(n121) );
XOR2X1TS U61 ( .A(in1[8]), .B(in2[8]), .Y(n55) );
XOR2X1TS U62 ( .A(in1[9]), .B(in2[9]), .Y(n63) );
XOR2X1TS U63 ( .A(in1[11]), .B(in2[11]), .Y(n79) );
XOR2X1TS U64 ( .A(in1[12]), .B(in2[12]), .Y(n87) );
XOR2X1TS U65 ( .A(in1[13]), .B(in2[13]), .Y(n95) );
XOR2X1TS U66 ( .A(in1[14]), .B(in2[14]), .Y(n103) );
XOR2X1TS U67 ( .A(in1[15]), .B(in2[15]), .Y(n111) );
XOR2X1TS U68 ( .A(n22), .B(n21), .Y(n119) );
XOR2X1TS U69 ( .A(n14), .B(n12), .Y(n127) );
XOR2X1TS U70 ( .A(n15), .B(n13), .Y(n135) );
XOR2X1TS U71 ( .A(n37), .B(in2[19]), .Y(n143) );
INVX2TS U72 ( .A(in2[25]), .Y(n23) );
INVX2TS U73 ( .A(in1[25]), .Y(n25) );
AND2X4TS U74 ( .A(in2[13]), .B(in1[13]), .Y(n4) );
AND2X4TS U75 ( .A(in2[14]), .B(in1[14]), .Y(n5) );
CLKBUFX2TS U76 ( .A(in2[24]), .Y(n10) );
CLKBUFX2TS U77 ( .A(in1[24]), .Y(n11) );
CLKBUFX2TS U78 ( .A(in2[17]), .Y(n12) );
CLKBUFX2TS U79 ( .A(in2[18]), .Y(n13) );
CLKBUFX2TS U80 ( .A(in1[17]), .Y(n14) );
CLKBUFX2TS U81 ( .A(in1[18]), .Y(n15) );
CLKBUFX2TS U82 ( .A(in1[21]), .Y(n16) );
INVX2TS U83 ( .A(in2[26]), .Y(n17) );
INVX2TS U84 ( .A(n17), .Y(n18) );
INVX2TS U85 ( .A(in1[26]), .Y(n19) );
INVX2TS U86 ( .A(n19), .Y(n20) );
CLKBUFX2TS U87 ( .A(in2[16]), .Y(n21) );
CLKBUFX2TS U88 ( .A(in1[16]), .Y(n22) );
OAI2BB2X1TS U89 ( .B0(n148), .B1(n147), .A0N(in1[16]), .A1N(in2[16]), .Y(
n149) );
INVX2TS U90 ( .A(n23), .Y(n24) );
INVX2TS U91 ( .A(n25), .Y(n26) );
CLKBUFX2TS U92 ( .A(in2[23]), .Y(n27) );
CLKBUFX2TS U93 ( .A(in1[23]), .Y(n28) );
CLKBUFX2TS U94 ( .A(in2[22]), .Y(n29) );
CLKBUFX2TS U95 ( .A(in1[22]), .Y(n30) );
CLKBUFX2TS U96 ( .A(in2[21]), .Y(n35) );
INVX2TS U97 ( .A(n36), .Y(n37) );
OAI2BB1X2TS U98 ( .A0N(in2[14]), .A1N(in1[14]), .B0(n145), .Y(n146) );
OAI2BB1X2TS U99 ( .A0N(n34), .A1N(n39), .B0(n199), .Y(n200) );
OAI2BB1X2TS U100 ( .A0N(in2[21]), .A1N(in1[21]), .B0(n209), .Y(n210) );
OAI2BB1X2TS U101 ( .A0N(in2[15]), .A1N(in1[15]), .B0(n154), .Y(n155) );
OAI2BB1X2TS U102 ( .A0N(in2[18]), .A1N(in1[18]), .B0(n181), .Y(n182) );
OAI21X2TS U103 ( .A0(in1[18]), .A1(in2[18]), .B0(n7), .Y(n181) );
OAI2BB1X2TS U104 ( .A0N(n32), .A1N(in1[19]), .B0(n190), .Y(n191) );
OAI21X2TS U105 ( .A0(in1[19]), .A1(n32), .B0(n8), .Y(n190) );
OAI2BB1X2TS U106 ( .A0N(in2[16]), .A1N(in1[16]), .B0(n163), .Y(n164) );
OAI21X2TS U107 ( .A0(in1[16]), .A1(in2[16]), .B0(n9), .Y(n163) );
OAI2BB1X2TS U108 ( .A0N(in2[17]), .A1N(in1[17]), .B0(n172), .Y(n173) );
OAI21X2TS U109 ( .A0(in1[17]), .A1(in2[17]), .B0(n6), .Y(n172) );
ADDHXLTS U110 ( .A(in2[0]), .B(in1[0]), .CO(n48), .S(res[0]) );
CMPR32X2TS U111 ( .A(in1[6]), .B(in2[6]), .C(n43), .CO(n42), .S(res[6]) );
CMPR32X2TS U112 ( .A(in1[5]), .B(in2[5]), .C(n44), .CO(n43), .S(res[5]) );
CMPR32X2TS U113 ( .A(in1[4]), .B(in2[4]), .C(n45), .CO(n44), .S(res[4]) );
CMPR32X2TS U114 ( .A(in1[3]), .B(in2[3]), .C(n46), .CO(n45), .S(res[3]) );
CMPR32X2TS U115 ( .A(in1[2]), .B(in2[2]), .C(n47), .CO(n46), .S(res[2]) );
CMPR32X2TS U116 ( .A(in1[1]), .B(in2[1]), .C(n48), .CO(n47), .S(res[1]) );
CMPR32X2TS U117 ( .A(in1[2]), .B(in2[2]), .C(n49), .CO(n50) );
CMPR32X2TS U118 ( .A(in1[3]), .B(in2[3]), .C(n50), .CO(n51) );
CMPR32X2TS U119 ( .A(in1[4]), .B(in2[4]), .C(n51), .CO(n52) );
CMPR32X2TS U120 ( .A(in1[5]), .B(in2[5]), .C(n52), .CO(n53) );
CMPR32X2TS U121 ( .A(in1[6]), .B(in2[6]), .C(n53), .CO(n54) );
CMPR32X2TS U122 ( .A(in1[7]), .B(in2[7]), .C(n54), .CO(n56) );
CMPR32X2TS U123 ( .A(in1[3]), .B(in2[3]), .C(n57), .CO(n58) );
CMPR32X2TS U124 ( .A(in1[4]), .B(in2[4]), .C(n58), .CO(n59) );
CMPR32X2TS U125 ( .A(in1[5]), .B(in2[5]), .C(n59), .CO(n60) );
CMPR32X2TS U126 ( .A(in1[6]), .B(in2[6]), .C(n60), .CO(n61) );
CMPR32X2TS U127 ( .A(in1[7]), .B(in2[7]), .C(n61), .CO(n62) );
CMPR32X2TS U128 ( .A(in1[8]), .B(in2[8]), .C(n62), .CO(n64) );
CMPR32X2TS U129 ( .A(in1[4]), .B(in2[4]), .C(n65), .CO(n66) );
CMPR32X2TS U130 ( .A(in1[5]), .B(in2[5]), .C(n66), .CO(n67) );
CMPR32X2TS U131 ( .A(in1[6]), .B(in2[6]), .C(n67), .CO(n68) );
CMPR32X2TS U132 ( .A(in1[7]), .B(in2[7]), .C(n68), .CO(n69) );
CMPR32X2TS U133 ( .A(in1[8]), .B(in2[8]), .C(n69), .CO(n70) );
CMPR32X2TS U134 ( .A(in1[9]), .B(in2[9]), .C(n70), .CO(n72) );
CMPR32X2TS U135 ( .A(in1[5]), .B(in2[5]), .C(n73), .CO(n74) );
CMPR32X2TS U136 ( .A(in1[6]), .B(in2[6]), .C(n74), .CO(n75) );
CMPR32X2TS U137 ( .A(in1[7]), .B(in2[7]), .C(n75), .CO(n76) );
CMPR32X2TS U138 ( .A(in1[8]), .B(in2[8]), .C(n76), .CO(n77) );
CMPR32X2TS U139 ( .A(in1[9]), .B(in2[9]), .C(n77), .CO(n78) );
CMPR32X2TS U140 ( .A(in1[10]), .B(in2[10]), .C(n78), .CO(n80) );
CMPR32X2TS U141 ( .A(in1[6]), .B(in2[6]), .C(n81), .CO(n82) );
CMPR32X2TS U142 ( .A(in1[7]), .B(in2[7]), .C(n82), .CO(n83) );
CMPR32X2TS U143 ( .A(in1[8]), .B(in2[8]), .C(n83), .CO(n84) );
CMPR32X2TS U144 ( .A(in1[9]), .B(in2[9]), .C(n84), .CO(n85) );
CMPR32X2TS U145 ( .A(in1[10]), .B(in2[10]), .C(n85), .CO(n86) );
CMPR32X2TS U146 ( .A(in1[11]), .B(in2[11]), .C(n86), .CO(n88) );
CMPR32X2TS U147 ( .A(in1[7]), .B(in2[7]), .C(n89), .CO(n90) );
CMPR32X2TS U148 ( .A(in1[8]), .B(in2[8]), .C(n90), .CO(n91) );
CMPR32X2TS U149 ( .A(in1[9]), .B(in2[9]), .C(n91), .CO(n92) );
CMPR32X2TS U150 ( .A(in1[10]), .B(in2[10]), .C(n92), .CO(n93) );
CMPR32X2TS U151 ( .A(in1[11]), .B(in2[11]), .C(n93), .CO(n94) );
CMPR32X2TS U152 ( .A(in1[12]), .B(in2[12]), .C(n94), .CO(n96) );
CMPR32X2TS U153 ( .A(in1[8]), .B(in2[8]), .C(n97), .CO(n98) );
CMPR32X2TS U154 ( .A(in1[9]), .B(in2[9]), .C(n98), .CO(n99) );
CMPR32X2TS U155 ( .A(in1[10]), .B(in2[10]), .C(n99), .CO(n100) );
CMPR32X2TS U156 ( .A(in1[11]), .B(in2[11]), .C(n100), .CO(n101) );
CMPR32X2TS U157 ( .A(in1[12]), .B(in2[12]), .C(n101), .CO(n102) );
CMPR32X2TS U158 ( .A(in1[13]), .B(in2[13]), .C(n102), .CO(n104) );
CMPR32X2TS U159 ( .A(in1[9]), .B(in2[9]), .C(n105), .CO(n106) );
CMPR32X2TS U160 ( .A(in1[10]), .B(in2[10]), .C(n106), .CO(n107) );
CMPR32X2TS U161 ( .A(in1[11]), .B(in2[11]), .C(n107), .CO(n108) );
CMPR32X2TS U162 ( .A(in1[12]), .B(in2[12]), .C(n108), .CO(n109) );
CMPR32X2TS U163 ( .A(in1[13]), .B(in2[13]), .C(n109), .CO(n110) );
CMPR32X2TS U164 ( .A(in1[14]), .B(in2[14]), .C(n110), .CO(n112) );
CMPR32X2TS U165 ( .A(in1[10]), .B(in2[10]), .C(n113), .CO(n114) );
CMPR32X2TS U166 ( .A(in1[11]), .B(in2[11]), .C(n114), .CO(n115) );
CMPR32X2TS U167 ( .A(in1[12]), .B(in2[12]), .C(n115), .CO(n116) );
CMPR32X2TS U168 ( .A(in1[13]), .B(in2[13]), .C(n116), .CO(n117) );
CMPR32X2TS U169 ( .A(in1[14]), .B(in2[14]), .C(n117), .CO(n118) );
CMPR32X2TS U170 ( .A(in1[15]), .B(in2[15]), .C(n118), .CO(n120) );
CMPR32X2TS U171 ( .A(in1[11]), .B(in2[11]), .C(n121), .CO(n122) );
CMPR32X2TS U172 ( .A(in1[12]), .B(in2[12]), .C(n122), .CO(n123) );
CMPR32X2TS U173 ( .A(in1[13]), .B(in2[13]), .C(n123), .CO(n124) );
CMPR32X2TS U174 ( .A(in1[14]), .B(in2[14]), .C(n124), .CO(n125) );
CMPR32X2TS U175 ( .A(in1[15]), .B(in2[15]), .C(n125), .CO(n126) );
CMPR32X2TS U176 ( .A(n22), .B(n21), .C(n126), .CO(n128) );
CMPR32X2TS U177 ( .A(in1[12]), .B(in2[12]), .C(n129), .CO(n130) );
CMPR32X2TS U178 ( .A(in1[13]), .B(in2[13]), .C(n130), .CO(n131) );
CMPR32X2TS U179 ( .A(in1[14]), .B(in2[14]), .C(n131), .CO(n132) );
CMPR32X2TS U180 ( .A(in1[15]), .B(in2[15]), .C(n132), .CO(n133) );
CMPR32X2TS U181 ( .A(in1[16]), .B(in2[16]), .C(n133), .CO(n134) );
CMPR32X2TS U182 ( .A(n14), .B(n12), .C(n134), .CO(n136) );
CMPR32X2TS U183 ( .A(in1[13]), .B(in2[13]), .C(n137), .CO(n138) );
CMPR32X2TS U184 ( .A(in1[14]), .B(in2[14]), .C(n138), .CO(n139) );
CMPR32X2TS U185 ( .A(in1[15]), .B(in2[15]), .C(n139), .CO(n140) );
CMPR32X2TS U186 ( .A(in1[16]), .B(in2[16]), .C(n140), .CO(n141) );
CMPR32X2TS U187 ( .A(n14), .B(n12), .C(n141), .CO(n142) );
CMPR32X2TS U188 ( .A(n15), .B(n13), .C(n142), .CO(n144) );
AOI222X1TS U189 ( .A0(in2[15]), .A1(in1[15]), .B0(in2[15]), .B1(n146), .C0(
in1[15]), .C1(n146), .Y(n148) );
NOR2X1TS U190 ( .A(in1[18]), .B(in2[18]), .Y(n165) );
OAI2BB2X1TS U191 ( .B0(n150), .B1(n165), .A0N(n15), .A1N(n13), .Y(n151) );
AOI222X1TS U192 ( .A0(in2[19]), .A1(n37), .B0(in2[19]), .B1(n151), .C0(n37),
.C1(n151), .Y(n152) );
XNOR2X2TS U193 ( .A(n152), .B(in2[20]), .Y(n153) );
OAI21X4TS U194 ( .A0(in1[15]), .A1(in2[15]), .B0(n5), .Y(n154) );
AOI222X1TS U195 ( .A0(in2[16]), .A1(in1[16]), .B0(in2[16]), .B1(n155), .C0(
in1[16]), .C1(n155), .Y(n157) );
NOR2X1TS U196 ( .A(in1[17]), .B(in2[17]), .Y(n156) );
OAI2BB2X2TS U197 ( .B0(n157), .B1(n156), .A0N(in1[17]), .A1N(in2[17]), .Y(
n158) );
AOI222X1TS U198 ( .A0(in2[18]), .A1(in1[18]), .B0(in2[18]), .B1(n158), .C0(
in1[18]), .C1(n158), .Y(n159) );
NOR2X1TS U199 ( .A(in1[19]), .B(n32), .Y(n174) );
OAI2BB2X1TS U200 ( .B0(n159), .B1(n174), .A0N(n37), .A1N(in2[19]), .Y(n160)
);
AOI222X1TS U201 ( .A0(in2[20]), .A1(n40), .B0(in2[20]), .B1(n160), .C0(n40),
.C1(n160), .Y(n161) );
XNOR2X2TS U202 ( .A(n161), .B(n35), .Y(n162) );
XOR2X1TS U203 ( .A(n16), .B(n162), .Y(res[21]) );
AOI222X1TS U204 ( .A0(in2[17]), .A1(in1[17]), .B0(in2[17]), .B1(n164), .C0(
in1[17]), .C1(n164), .Y(n166) );
OAI2BB2X2TS U205 ( .B0(n166), .B1(n165), .A0N(in1[18]), .A1N(in2[18]), .Y(
n167) );
AOI222X1TS U206 ( .A0(in2[19]), .A1(n37), .B0(in2[19]), .B1(n167), .C0(n37),
.C1(n167), .Y(n168) );
NOR2X1TS U207 ( .A(n39), .B(n34), .Y(n183) );
OAI2BB2X1TS U208 ( .B0(n168), .B1(n183), .A0N(n40), .A1N(in2[20]), .Y(n169)
);
XNOR2X2TS U209 ( .A(n170), .B(n29), .Y(n171) );
AOI222X1TS U210 ( .A0(in2[18]), .A1(in1[18]), .B0(in2[18]), .B1(n173), .C0(
in1[18]), .C1(n173), .Y(n175) );
OAI2BB2X2TS U211 ( .B0(n175), .B1(n174), .A0N(n37), .A1N(in2[19]), .Y(n176)
);
AOI222X1TS U212 ( .A0(in2[20]), .A1(n40), .B0(in2[20]), .B1(n176), .C0(n40),
.C1(n176), .Y(n177) );
NOR2X1TS U213 ( .A(in1[21]), .B(in2[21]), .Y(n192) );
OAI2BB2X1TS U214 ( .B0(n177), .B1(n192), .A0N(n16), .A1N(n35), .Y(n178) );
XNOR2X2TS U215 ( .A(n179), .B(n27), .Y(n180) );
AOI222X1TS U216 ( .A0(in2[19]), .A1(n37), .B0(in2[19]), .B1(n182), .C0(n37),
.C1(n182), .Y(n184) );
OAI2BB2X2TS U217 ( .B0(n184), .B1(n183), .A0N(n40), .A1N(in2[20]), .Y(n185)
);
AOI222X1TS U218 ( .A0(in2[21]), .A1(in1[21]), .B0(in2[21]), .B1(n185), .C0(
in1[21]), .C1(n185), .Y(n186) );
NOR2X1TS U219 ( .A(in1[22]), .B(in2[22]), .Y(n201) );
OAI2BB2X1TS U220 ( .B0(n186), .B1(n201), .A0N(n30), .A1N(n29), .Y(n187) );
XNOR2X2TS U221 ( .A(n188), .B(n10), .Y(n189) );
AOI222X1TS U222 ( .A0(in2[20]), .A1(n40), .B0(in2[20]), .B1(n191), .C0(n40),
.C1(n191), .Y(n193) );
OAI2BB2X2TS U223 ( .B0(n193), .B1(n192), .A0N(in1[21]), .A1N(in2[21]), .Y(
n194) );
AOI222X1TS U224 ( .A0(in2[22]), .A1(in1[22]), .B0(in2[22]), .B1(n194), .C0(
in1[22]), .C1(n194), .Y(n195) );
NOR2X1TS U225 ( .A(in1[23]), .B(in2[23]), .Y(n211) );
AOI222X1TS U226 ( .A0(in2[21]), .A1(in1[21]), .B0(in2[21]), .B1(n200), .C0(
in1[21]), .C1(n200), .Y(n202) );
OAI2BB2X1TS U227 ( .B0(n202), .B1(n201), .A0N(in1[22]), .A1N(in2[22]), .Y(
n203) );
NOR2X1TS U228 ( .A(in1[24]), .B(in2[24]), .Y(n204) );
OAI2BB2X2TS U229 ( .B0(n205), .B1(n204), .A0N(in1[24]), .A1N(in2[24]), .Y(
n206) );
AOI222X1TS U230 ( .A0(in2[25]), .A1(in1[25]), .B0(in2[25]), .B1(n206), .C0(
in1[25]), .C1(n206), .Y(n207) );
XNOR2X2TS U231 ( .A(n207), .B(n18), .Y(n208) );
XOR2X1TS U232 ( .A(n20), .B(n208), .Y(res[26]) );
OAI21X4TS U233 ( .A0(in1[21]), .A1(in2[21]), .B0(n2), .Y(n209) );
AOI222X1TS U234 ( .A0(in2[22]), .A1(in1[22]), .B0(in2[22]), .B1(n210), .C0(
in1[22]), .C1(n210), .Y(n212) );
OAI2BB2X1TS U235 ( .B0(n212), .B1(n211), .A0N(in1[23]), .A1N(in2[23]), .Y(
n213) );
NOR2X1TS U236 ( .A(in1[25]), .B(in2[25]), .Y(n214) );
OAI2BB2X2TS U237 ( .B0(n215), .B1(n214), .A0N(in1[25]), .A1N(in2[25]), .Y(
n216) );
AOI222X1TS U238 ( .A0(in2[26]), .A1(in1[26]), .B0(n18), .B1(n216), .C0(n20),
.C1(n216), .Y(n217) );
XNOR2X2TS U239 ( .A(n217), .B(in2[27]), .Y(n218) );
initial $sdf_annotate("ACA_I_N32_Q8_syn.sdf");
endmodule
|
// -----------------------------------------------------------------------
module uart(
input clk,
input send,
input [7:0] tx_byte,
output [7:0] rx_byte,
output tx_ready,
output rx_ready,
output txd,
input rxd
);
parameter baud;
parameter clk_speed;
localparam prescale = clk_speed/baud;
localparam width = $clog2(prescale+1);
localparam [width-1:0] period = prescale[width-1:0] - 1'b1;
uart_tx #(
.width(width),
.period(period)
) tx(
.clk(clk),
.d(tx_byte),
.txd(txd),
.send(send),
.ready(tx_ready)
);
uart_rx #(
.width(width),
.period(period)
) rx(
.clk(clk),
.d(rx_byte),
.rxd(rxd),
.ready(rx_ready)
);
endmodule
// -----------------------------------------------------------------------
module uart_tx(
input clk,
input [7:0] d,
input send,
output ready,
output txd
);
parameter width;
parameter period;
localparam TX_IDLE = 2'd0;
localparam TX_SEND = 2'd1;
localparam TX_WAIT = 2'd2;
reg [1:0] txstate = TX_IDLE;
reg [width-1:0] divcnt;
reg [3:0] bitcnt;
reg [0:10] txbuf = {11'b11111111111};
always @ (posedge clk) begin
ready <= 0;
case (txstate)
TX_IDLE:
if (send) begin
bitcnt <= 4'd10;
txbuf <= {1'b1, 1'b1, d, 1'b0};
divcnt <= period;
txstate <= TX_WAIT;
end
TX_SEND: begin
txbuf <= {1'b1, txbuf[0:9]};
divcnt <= period;
txstate <= TX_WAIT;
end
TX_WAIT:
if (divcnt != 0) begin
divcnt <= divcnt - 1'd1;
end else begin
if (bitcnt == 1) begin
ready <= 1;
txstate <= TX_IDLE;
end else begin
bitcnt <= bitcnt - 1'd1;
txstate <= TX_SEND;
end
end
endcase
end
assign txd = txbuf[10];
endmodule
// -----------------------------------------------------------------------
module uart_rx(
input clk,
output reg [7:0] d,
output ready,
input rxd
);
parameter width;
parameter period;
localparam halfperiod = period / 2;
localparam RX_IDLE = 2'd0;
localparam RX_START = 2'd1;
localparam RX_DATA = 2'd3;
reg [1:0] rxstate = RX_IDLE;
reg [width-1:0] divcnt;
reg [3:0] bitcnt;
reg [8:0] rxbuf;
always @ (posedge clk) begin
ready <= 0;
case (rxstate)
RX_IDLE:
if (!rxd) begin
divcnt <= period;
rxstate <= RX_START;
end
RX_START:
if (rxd) begin // RXD gone high during the first half of start bit
rxstate <= RX_IDLE;
end else if (divcnt > halfperiod) begin
divcnt <= divcnt - 1'd1;
end else begin
divcnt <= period;
bitcnt <= 4'd9;
rxstate <= RX_DATA;
end
RX_DATA:
if (bitcnt == 0) begin
rxstate <= RX_IDLE;
if (rxd) begin // RXD needs to be high @ stop bit for the frame to be OK
d <= rxbuf[7:0];
ready <= 1;
end
end else if (divcnt != 0) begin
divcnt <= divcnt - 1'd1;
end else begin
divcnt <= period;
bitcnt <= bitcnt - 1'd1;
rxbuf <= {rxd, rxbuf[8:1]};
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: fm_ram_1024w.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fm_ram_1024w (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [23:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "24576"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fm_ram_1024w_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// file: clk_gen.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____12.727______0.000______50.0______285.078____281.140
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_____________125____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v5_1,{component_name=clk_gen,use_phase_alignment=false,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_gen
(
// Clock in ports
input clk125,
// Clock out ports
output clk,
// Status and control signals
output clk_locked
);
clk_gen_clk_wiz inst
(
// Clock in ports
.clk125(clk125),
// Clock out ports
.clk(clk),
// Status and control signals
.clk_locked(clk_locked)
);
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (which mostly works), and
Scheme (a bit out of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
magic declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(** $Date: 2016-05-26 12:03:56 -0400 (Thu, 26 May 2016) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBP_LP_V
`define SKY130_FD_SC_LP__DLXBP_LP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_lp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxbp_lp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBP_LP_V
|
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