diff --git "a/training_data_no_parameters.json" "b/training_data_no_parameters.json" new file mode 100644--- /dev/null +++ "b/training_data_no_parameters.json" @@ -0,0 +1,1098 @@ +[ + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\nclass IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {\n require (numIds > 0)\n val idWidth = log2Up(numIds)\n\n val io = IO(new Bundle {\n val free = Flipped(Valid(UInt(idWidth.W)))\n val alloc = if (revocableSelect) Decoupled(UInt(idWidth.W)) else Irrevocable(UInt(idWidth.W))\n })\n\n // True indicates that the id is available\n val bitmap = RegInit(UInt(numIds.W), -1.S(numIds.W).asUInt)\n val select = RegInit(0.U(idWidth.W))\n val valid = RegInit(true.B)\n\n io.alloc.valid := (if (lateValid) bitmap.orR else valid)\n io.alloc.bits := (if (revocableSelect) PriorityEncoder(bitmap) else select)\n\n val taken = Mux(io.alloc.ready, UIntToOH(io.alloc.bits, numIds), 0.U)\n val allocated = Mux(io.free .valid, UIntToOH(io.free .bits, numIds), 0.U)\n val bitmap1 = (bitmap & ~taken) | allocated\n val select1 = PriorityEncoder(bitmap1)\n val valid1 = ( (bitmap.orR && !((PopCount(bitmap) === 1.U) && io.alloc.ready)) // bitmap not zero, and not allocating last bit\n || io.free.valid)\n\n // Clock gate the bitmap\n when (io.alloc.ready || io.free.valid) {\n bitmap := bitmap1\n valid := valid1\n }\n\n // Make select irrevocable\n when (io.alloc.ready || (!io.alloc.valid && io.free.valid)) {\n select := select1\n }\n\n // No double freeing\n assert (!io.free.valid || !(bitmap & ~taken)(io.free.bits))\n\n // pre-calculations for timing\n if (!lateValid) {\n assert (valid === bitmap.orR)\n }\n if (!revocableSelect) {\n when (io.alloc.valid && RegNext(io.alloc.ready || (!io.alloc.valid && io.free.valid))) {\n assert (select === PriorityEncoder(bitmap))\n }\n }\n}", + "response": "module IDPool(\n input clock,\n input reset,\n input io_free_valid,\n input [2:0] io_free_bits,\n input io_alloc_ready,\n output io_alloc_valid,\n output [2:0] io_alloc_bits\n);\n\n reg [7:0] bitmap;\n reg [2:0] select;\n reg valid;\n wire [7:0] taken = io_alloc_ready ? 8'h1 << select : 8'h0;\n wire [7:0] _GEN = {5'h0, io_free_bits};\n reg REG;\n wire [7:0] bitmap1 = bitmap & ~taken | (io_free_valid ? 8'h1 << _GEN : 8'h0);\n wire _GEN_1 = io_alloc_ready | ~valid & io_free_valid;\n always @(posedge clock) begin\n if (reset) begin\n bitmap <= 8'hFF;\n select <= 3'h0;\n valid <= 1'h1;\n end\n else begin\n if (io_alloc_ready | io_free_valid) begin\n bitmap <= bitmap1;\n valid <= (|bitmap) & ~({1'h0, {1'h0, {1'h0, bitmap[0]} + {1'h0, bitmap[1]}} + {1'h0, {1'h0, bitmap[2]} + {1'h0, bitmap[3]}}} + {1'h0, {1'h0, {1'h0, bitmap[4]} + {1'h0, bitmap[5]}} + {1'h0, {1'h0, bitmap[6]} + {1'h0, bitmap[7]}}} == 4'h1 & io_alloc_ready) | io_free_valid;\n end\n if (_GEN_1)\n select <= bitmap1[0] ? 3'h0 : bitmap1[1] ? 3'h1 : bitmap1[2] ? 3'h2 : bitmap1[3] ? 3'h3 : bitmap1[4] ? 3'h4 : bitmap1[5] ? 3'h5 : {2'h3, ~(bitmap1[6])};\n end\n REG <= _GEN_1;\n end\n assign io_alloc_valid = valid;\n assign io_alloc_bits = select;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module data_40x37(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [36:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [36:0] W0_data\n);\n\n reg [36:0] Memory[0:39];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 37'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", + "response": "module ClockCrossingReg_w32(\n input clock,\n input [31:0] io_d,\n output [31:0] io_q,\n input io_en\n);\n\n reg [31:0] cdc_reg;\n always @(posedge clock) begin\n if (io_en)\n cdc_reg <= io_d;\n end\n assign io_q = cdc_reg;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.reflect.DataMirror\nimport chisel3.internal.firrtl.KnownWidth\nimport chisel3.util.{Cat, Valid}\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\n/** Base JTAG shifter IO, viewed from input to shift register chain.\n * Can be chained together.\n */\nclass ShifterIO extends Bundle {\n val shift = Bool() // advance the scan chain on clock high\n val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB\n val capture = Bool() // high in the CaptureIR/DR state when this chain is selected\n val update = Bool() // high in the UpdateIR/DR state when this chain is selected\n\n /** Sets a output shifter IO's control signals from a input shifter IO's control signals.\n */\n def chainControlFrom(in: ShifterIO): Unit = {\n shift := in.shift\n capture := in.capture\n update := in.update\n }\n}\n\ntrait ChainIO extends Bundle {\n val chainIn = Input(new ShifterIO)\n val chainOut = Output(new ShifterIO)\n}\n\nclass Capture[+T <: Data](gen: T) extends Bundle {\n val bits = Input(gen) // data to capture, should be always valid\n val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge\n}\n\nobject Capture {\n def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)\n}\n\n/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain\n * IO.\n */\ntrait Chain extends Module {\n val io: ChainIO\n}\n\n/** One-element shift register, data register for bypass mode.\n *\n * Implements Clause 10.\n */\nclass JtagBypassChain(implicit val p: Parameters) extends Chain {\n class ModIO extends ChainIO\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val reg = Reg(Bool()) // 10.1.1a single shift register stage\n\n io.chainOut.data := reg\n\n property.cover(io.chainIn.capture, \"bypass_chain_capture\", \"JTAG; bypass_chain_capture; This Bypass Chain captured data\")\n\n when (io.chainIn.capture) {\n reg := false.B // 10.1.1b capture logic 0 on TCK rising\n } .elsewhen (io.chainIn.shift) {\n reg := io.chainIn.data\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject JtagBypassChain {\n def apply()(implicit p: Parameters) = new JtagBypassChain\n}\n\n/** Simple shift register with parallel capture only, for read-only data registers.\n *\n * Number of stages is the number of bits in gen, which must have a known width.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureChain_${gen.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(gen)\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val n = DataMirror.widthOf(gen) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $gen\"); -1 // TODO: remove -1 type hack\n }\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG; chain_capture; This Chain captured data\")\n \n when (io.chainIn.capture) {\n (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))\n io.capture.capture := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n } .otherwise {\n io.capture.capture := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureChain {\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)\n}\n\n/** Simple shift register with parallel capture and update. Useful for general instruction and data\n * scan registers.\n *\n * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have\n * known widths. If there is a width mismatch, the unused most significant bits will be zero.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(genCapture)\n val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val captureWidth = DataMirror.widthOf(genCapture) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genCapture\"); -1 // TODO: remove -1 type hack\n }\n val updateWidth = DataMirror.widthOf(genUpdate) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genUpdate\"); -1 // TODO: remove -1 type hack\n }\n val n = math.max(captureWidth, updateWidth)\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n val updateBits = Cat(regs.reverse)(updateWidth-1, 0)\n io.update.bits := updateBits.asTypeOf(io.update.bits)\n\n val captureBits = io.capture.bits.asUInt\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG;chain_capture; This Chain captured data\")\n property.cover(io.chainIn.capture, \"chain_update\", \"JTAG;chain_update; This Chain updated data\")\n\n when (io.chainIn.capture) {\n (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))\n (captureWidth until n) map (x => regs(x) := 0.U)\n io.capture.capture := true.B\n io.update.valid := false.B\n } .elsewhen (io.chainIn.update) {\n io.capture.capture := false.B\n io.update.valid := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n io.update.valid := false.B\n } .otherwise {\n io.capture.capture := false.B\n io.update.valid := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureUpdateChain {\n /** Capture-update chain with matching capture and update types.\n */\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)\n def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =\n new CaptureUpdateChain(genCapture, genUpdate)\n}", + "response": "module CaptureChain_JTAGIdcodeBundle(\n input clock,\n input reset,\n input io_chainIn_shift,\n input io_chainIn_data,\n input io_chainIn_capture,\n input io_chainIn_update,\n output io_chainOut_data\n);\n\n reg regs_0;\n reg regs_1;\n reg regs_2;\n reg regs_3;\n reg regs_4;\n reg regs_5;\n reg regs_6;\n reg regs_7;\n reg regs_8;\n reg regs_9;\n reg regs_10;\n reg regs_11;\n reg regs_12;\n reg regs_13;\n reg regs_14;\n reg regs_15;\n reg regs_16;\n reg regs_17;\n reg regs_18;\n reg regs_19;\n reg regs_20;\n reg regs_21;\n reg regs_22;\n reg regs_23;\n reg regs_24;\n reg regs_25;\n reg regs_26;\n reg regs_27;\n reg regs_28;\n reg regs_29;\n reg regs_30;\n reg regs_31;\n always @(posedge clock) begin\n if (io_chainIn_capture) begin\n regs_0 <= 1'h1;\n regs_1 <= 1'h0;\n regs_2 <= 1'h0;\n regs_3 <= 1'h0;\n regs_4 <= 1'h0;\n regs_5 <= 1'h0;\n regs_6 <= 1'h0;\n regs_7 <= 1'h0;\n regs_8 <= 1'h0;\n regs_9 <= 1'h0;\n regs_10 <= 1'h0;\n regs_11 <= 1'h0;\n regs_12 <= 1'h0;\n regs_13 <= 1'h0;\n regs_14 <= 1'h0;\n regs_15 <= 1'h0;\n regs_16 <= 1'h0;\n regs_17 <= 1'h0;\n regs_18 <= 1'h0;\n regs_19 <= 1'h0;\n regs_20 <= 1'h0;\n regs_21 <= 1'h0;\n regs_22 <= 1'h0;\n regs_23 <= 1'h0;\n regs_24 <= 1'h0;\n regs_25 <= 1'h0;\n regs_26 <= 1'h0;\n regs_27 <= 1'h0;\n regs_28 <= 1'h0;\n regs_29 <= 1'h0;\n regs_30 <= 1'h0;\n regs_31 <= 1'h0;\n end\n else if (io_chainIn_shift) begin\n regs_0 <= regs_1;\n regs_1 <= regs_2;\n regs_2 <= regs_3;\n regs_3 <= regs_4;\n regs_4 <= regs_5;\n regs_5 <= regs_6;\n regs_6 <= regs_7;\n regs_7 <= regs_8;\n regs_8 <= regs_9;\n regs_9 <= regs_10;\n regs_10 <= regs_11;\n regs_11 <= regs_12;\n regs_12 <= regs_13;\n regs_13 <= regs_14;\n regs_14 <= regs_15;\n regs_15 <= regs_16;\n regs_16 <= regs_17;\n regs_17 <= regs_18;\n regs_18 <= regs_19;\n regs_19 <= regs_20;\n regs_20 <= regs_21;\n regs_21 <= regs_22;\n regs_22 <= regs_23;\n regs_23 <= regs_24;\n regs_24 <= regs_25;\n regs_25 <= regs_26;\n regs_26 <= regs_27;\n regs_27 <= regs_28;\n regs_28 <= regs_29;\n regs_29 <= regs_30;\n regs_30 <= regs_31;\n regs_31 <= io_chainIn_data;\n end\n end\n assign io_chainOut_data = regs_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomLoopPredictorParams(\n nWays: Int = 4,\n threshold: Int = 7\n)\n\nclass LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tagSz = 10\n override val nSets = 16\n\n\n\n class LoopMeta extends Bundle {\n val s_cnt = UInt(10.W)\n }\n\n class LoopEntry extends Bundle {\n val tag = UInt(tagSz.W)\n val conf = UInt(3.W)\n val age = UInt(3.W)\n val p_cnt = UInt(10.W)\n val s_cnt = UInt(10.W)\n }\n\n class LoopBranchPredictorColumn extends Module {\n\n\n\n val io = IO(new Bundle {\n val f2_req_valid = Input(Bool())\n val f2_req_idx = Input(UInt())\n val f3_req_fire = Input(Bool())\n\n val f3_pred_in = Input(Bool())\n val f3_pred = Output(Bool())\n val f3_meta = Output(new LoopMeta)\n\n val update_mispredict = Input(Bool())\n val update_repair = Input(Bool())\n val update_idx = Input(UInt())\n val update_resolve_dir = Input(Bool())\n val update_meta = Input(new LoopMeta)\n })\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n\n val entries = Reg(Vec(nSets, new LoopEntry))\n val f2_entry = WireInit(entries(io.f2_req_idx))\n when (io.update_repair && io.update_idx === io.f2_req_idx) {\n f2_entry.s_cnt := io.update_meta.s_cnt\n } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) {\n f2_entry.s_cnt := 0.U\n }\n val f3_entry = RegNext(f2_entry)\n val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx),\n io.update_meta.s_cnt,\n f3_entry.s_cnt)\n val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)))\n\n io.f3_pred := io.f3_pred_in\n io.f3_meta.s_cnt := f3_scnt\n\n when (f3_entry.tag === f3_tag) {\n when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) {\n io.f3_pred := !io.f3_pred_in\n }\n }\n\n\n val f4_fire = RegNext(io.f3_req_fire)\n val f4_entry = RegNext(f3_entry)\n val f4_tag = RegNext(f3_tag)\n val f4_scnt = RegNext(f3_scnt)\n val f4_idx = RegNext(RegNext(io.f2_req_idx))\n\n\n when (f4_fire) {\n when (f4_entry.tag === f4_tag) {\n when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) {\n entries(f4_idx).age := 7.U\n entries(f4_idx).s_cnt := 0.U\n } .otherwise {\n entries(f4_idx).s_cnt := f4_scnt + 1.U\n entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U)\n }\n }\n }\n\n\n val entry = entries(io.update_idx)\n val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))\n val tag_match = entry.tag === tag\n val ctr_match = entry.p_cnt === io.update_meta.s_cnt\n val wentry = WireInit(entry)\n\n when (io.update_mispredict && !doing_reset) {\n\n // Learned, tag match -> decrement confidence\n when (entry.conf === 7.U && tag_match) {\n wentry.s_cnt := 0.U\n wentry.conf := 0.U\n\n // Learned, no tag match -> do nothing? Don't evict super-confident entries?\n } .elsewhen (entry.conf === 7.U && !tag_match) {\n\n // Confident, tag match, ctr_match -> increment confidence, reset counter\n } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) {\n wentry.conf := entry.conf + 1.U\n wentry.s_cnt := 0.U\n\n // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter\n } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) {\n wentry.conf := 0.U\n wentry.s_cnt := 0.U\n wentry.p_cnt := io.update_meta.s_cnt\n\n // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong\n } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) {\n wentry.tag := tag\n wentry.conf := 1.U\n wentry.s_cnt := 0.U\n wentry.p_cnt := io.update_meta.s_cnt\n\n // Confident, no tag match, age > 0 -> decrement age\n } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) {\n wentry.age := entry.age - 1.U\n\n // Unconfident, tag match, ctr match -> increment confidence\n } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) {\n wentry.conf := 1.U\n wentry.age := 7.U\n wentry.s_cnt := 0.U\n\n // Unconfident, tag match, no ctr match -> set previous counter\n } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) {\n wentry.p_cnt := io.update_meta.s_cnt\n wentry.age := 7.U\n wentry.s_cnt := 0.U\n\n // Unconfident, no tag match -> set previous counter and tag\n } .elsewhen (entry.conf === 0.U && !tag_match) {\n wentry.tag := tag\n wentry.conf := 1.U\n wentry.age := 7.U\n wentry.s_cnt := 0.U\n wentry.p_cnt := io.update_meta.s_cnt\n }\n\n entries(io.update_idx) := wentry\n } .elsewhen (io.update_repair && !doing_reset) {\n when (tag_match && !(f4_fire && io.update_idx === f4_idx)) {\n wentry.s_cnt := io.update_meta.s_cnt\n entries(io.update_idx) := wentry\n }\n }\n\n when (doing_reset) {\n entries(reset_idx) := (0.U).asTypeOf(new LoopEntry)\n }\n\n }\n\n\n val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) }\n val mems = Nil // TODO fix\n val f3_meta = Wire(Vec(bankWidth, new LoopMeta))\n override val metaSz = f3_meta.asUInt.getWidth\n\n val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta))\n\n for (w <- 0 until bankWidth) {\n columns(w).io.f2_req_valid := s2_valid\n columns(w).io.f2_req_idx := s2_idx\n columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire &&\n RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br))\n\n columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken\n io.resp.f3(w).taken := columns(w).io.f3_pred\n\n columns(w).io.update_mispredict := (s1_update.valid &&\n s1_update.bits.br_mask(w) &&\n s1_update.bits.is_mispredict_update &&\n s1_update.bits.cfi_mispredicted)\n columns(w).io.update_repair := (s1_update.valid &&\n s1_update.bits.br_mask(w) &&\n s1_update.bits.is_repair_update)\n columns(w).io.update_idx := s1_update_idx\n columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken\n columns(w).io.update_meta := update_meta(w)\n\n f3_meta(w) := columns(w).io.f3_meta\n }\n\n io.f3_meta := f3_meta.asUInt\n\n}", + "response": "module LoopBranchPredictorColumn(\n input clock,\n input reset,\n input [36:0] io_f2_req_idx,\n input io_f3_req_fire,\n input io_f3_pred_in,\n output io_f3_pred,\n output [9:0] io_f3_meta_s_cnt,\n input io_update_mispredict,\n input io_update_repair,\n input [36:0] io_update_idx,\n input [9:0] io_update_meta_s_cnt\n);\n\n reg doing_reset;\n reg [3:0] reset_idx;\n reg [9:0] entries_0_tag;\n reg [2:0] entries_0_conf;\n reg [2:0] entries_0_age;\n reg [9:0] entries_0_p_cnt;\n reg [9:0] entries_0_s_cnt;\n reg [9:0] entries_1_tag;\n reg [2:0] entries_1_conf;\n reg [2:0] entries_1_age;\n reg [9:0] entries_1_p_cnt;\n reg [9:0] entries_1_s_cnt;\n reg [9:0] entries_2_tag;\n reg [2:0] entries_2_conf;\n reg [2:0] entries_2_age;\n reg [9:0] entries_2_p_cnt;\n reg [9:0] entries_2_s_cnt;\n reg [9:0] entries_3_tag;\n reg [2:0] entries_3_conf;\n reg [2:0] entries_3_age;\n reg [9:0] entries_3_p_cnt;\n reg [9:0] entries_3_s_cnt;\n reg [9:0] entries_4_tag;\n reg [2:0] entries_4_conf;\n reg [2:0] entries_4_age;\n reg [9:0] entries_4_p_cnt;\n reg [9:0] entries_4_s_cnt;\n reg [9:0] entries_5_tag;\n reg [2:0] entries_5_conf;\n reg [2:0] entries_5_age;\n reg [9:0] entries_5_p_cnt;\n reg [9:0] entries_5_s_cnt;\n reg [9:0] entries_6_tag;\n reg [2:0] entries_6_conf;\n reg [2:0] entries_6_age;\n reg [9:0] entries_6_p_cnt;\n reg [9:0] entries_6_s_cnt;\n reg [9:0] entries_7_tag;\n reg [2:0] entries_7_conf;\n reg [2:0] entries_7_age;\n reg [9:0] entries_7_p_cnt;\n reg [9:0] entries_7_s_cnt;\n reg [9:0] entries_8_tag;\n reg [2:0] entries_8_conf;\n reg [2:0] entries_8_age;\n reg [9:0] entries_8_p_cnt;\n reg [9:0] entries_8_s_cnt;\n reg [9:0] entries_9_tag;\n reg [2:0] entries_9_conf;\n reg [2:0] entries_9_age;\n reg [9:0] entries_9_p_cnt;\n reg [9:0] entries_9_s_cnt;\n reg [9:0] entries_10_tag;\n reg [2:0] entries_10_conf;\n reg [2:0] entries_10_age;\n reg [9:0] entries_10_p_cnt;\n reg [9:0] entries_10_s_cnt;\n reg [9:0] entries_11_tag;\n reg [2:0] entries_11_conf;\n reg [2:0] entries_11_age;\n reg [9:0] entries_11_p_cnt;\n reg [9:0] entries_11_s_cnt;\n reg [9:0] entries_12_tag;\n reg [2:0] entries_12_conf;\n reg [2:0] entries_12_age;\n reg [9:0] entries_12_p_cnt;\n reg [9:0] entries_12_s_cnt;\n reg [9:0] entries_13_tag;\n reg [2:0] entries_13_conf;\n reg [2:0] entries_13_age;\n reg [9:0] entries_13_p_cnt;\n reg [9:0] entries_13_s_cnt;\n reg [9:0] entries_14_tag;\n reg [2:0] entries_14_conf;\n reg [2:0] entries_14_age;\n reg [9:0] entries_14_p_cnt;\n reg [9:0] entries_14_s_cnt;\n reg [9:0] entries_15_tag;\n reg [2:0] entries_15_conf;\n reg [2:0] entries_15_age;\n reg [9:0] entries_15_p_cnt;\n reg [9:0] entries_15_s_cnt;\n reg [9:0] f3_entry_tag;\n reg [2:0] f3_entry_conf;\n reg [2:0] f3_entry_age;\n reg [9:0] f3_entry_p_cnt;\n reg [9:0] f3_entry_s_cnt;\n reg [36:0] f3_scnt_REG;\n wire [9:0] f3_scnt = io_update_repair & io_update_idx == f3_scnt_REG ? io_update_meta_s_cnt : f3_entry_s_cnt;\n reg [9:0] f3_tag;\n reg f4_fire;\n reg [9:0] f4_entry_tag;\n reg [2:0] f4_entry_conf;\n reg [2:0] f4_entry_age;\n reg [9:0] f4_entry_p_cnt;\n reg [9:0] f4_tag;\n reg [9:0] f4_scnt;\n reg [36:0] f4_idx_REG;\n reg [36:0] f4_idx;\n wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}};\n wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}};\n wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}};\n wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}};\n wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}};\n wire _GEN_4 = io_update_idx == io_f2_req_idx;\n wire _GEN_5 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf);\n wire [9:0] _GEN_6 = _GEN_5 ? 10'h0 : f4_scnt + 10'h1;\n wire _GEN_7 = f4_fire & f4_entry_tag == f4_tag;\n wire [2:0] _GEN_8 = _GEN_5 | (&f4_entry_age) ? 3'h7 : f4_entry_age + 3'h1;\n wire [9:0] _GEN_9 = _GEN[io_update_idx[3:0]];\n wire [2:0] _GEN_10 = _GEN_0[io_update_idx[3:0]];\n wire [2:0] _GEN_11 = _GEN_1[io_update_idx[3:0]];\n wire [9:0] _GEN_12 = _GEN_2[io_update_idx[3:0]];\n wire [9:0] _GEN_13 = _GEN_3[io_update_idx[3:0]];\n wire tag_match = _GEN_9 == io_update_idx[13:4];\n wire ctr_match = _GEN_12 == io_update_meta_s_cnt;\n wire _GEN_14 = io_update_mispredict & ~doing_reset;\n wire _GEN_15 = (&_GEN_10) & tag_match;\n wire _GEN_16 = _GEN_9 != io_update_idx[13:4];\n wire _GEN_17 = (&_GEN_10) & _GEN_16;\n wire _GEN_18 = (|_GEN_10) & tag_match;\n wire _GEN_19 = _GEN_18 & ctr_match;\n wire [2:0] _wentry_conf_T = _GEN_10 + 3'h1;\n wire _GEN_20 = _GEN_12 != io_update_meta_s_cnt;\n wire _GEN_21 = _GEN_18 & _GEN_20;\n wire _GEN_22 = (|_GEN_10) & _GEN_16;\n wire _GEN_23 = _GEN_22 & ~(|_GEN_11);\n wire _GEN_24 = _GEN_22 & (|_GEN_11);\n wire [2:0] _wentry_age_T = _GEN_11 - 3'h1;\n wire _GEN_25 = ~(|_GEN_10) & tag_match;\n wire _GEN_26 = _GEN_25 & ctr_match;\n wire _GEN_27 = _GEN_25 & _GEN_20;\n wire _GEN_28 = ~(|_GEN_10) & _GEN_16;\n wire _GEN_29 = _GEN_26 | _GEN_27;\n wire _GEN_30 = _GEN_19 | _GEN_21;\n wire _GEN_31 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_30 | ~(_GEN_23 | ~(_GEN_24 | _GEN_29 | ~_GEN_28));\n wire _GEN_32 = _GEN_23 | ~(_GEN_24 | ~(_GEN_26 | ~(_GEN_27 | ~_GEN_28)));\n wire _GEN_33 = _GEN_27 | _GEN_28;\n wire _GEN_34 = _GEN_26 | _GEN_33;\n wire _GEN_35 = _GEN_21 | _GEN_23;\n wire _GEN_36 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | _GEN_35;\n wire _GEN_37 = _GEN_15 | ~(_GEN_17 | ~(_GEN_30 | _GEN_23 | ~(_GEN_24 | ~(_GEN_29 | _GEN_28))));\n wire _GEN_38 = ~_GEN_14 | _GEN_15 | _GEN_17 | _GEN_19 | ~(_GEN_35 | ~(_GEN_24 | _GEN_26 | ~_GEN_33));\n wire _GEN_39 = io_update_repair & ~doing_reset;\n wire _GEN_40 = tag_match & ~(f4_fire & io_update_idx == f4_idx);\n wire _GEN_41 = _GEN_39 & _GEN_40;\n wire _GEN_42 = _GEN_14 | _GEN_39 & _GEN_40;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 4'h0;\n end\n else begin\n doing_reset <= ~(&reset_idx) & doing_reset;\n reset_idx <= reset_idx + {3'h0, doing_reset};\n end\n if (doing_reset & reset_idx == 4'h0) begin\n entries_0_tag <= 10'h0;\n entries_0_conf <= 3'h0;\n entries_0_age <= 3'h0;\n entries_0_p_cnt <= 10'h0;\n entries_0_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h0) begin\n if (_GEN_31)\n entries_0_tag <= _GEN_9;\n else\n entries_0_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_0_conf <= 3'h0;\n else if (_GEN_17)\n entries_0_conf <= _GEN_10;\n else if (_GEN_19)\n entries_0_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_0_conf <= 3'h0;\n else if (_GEN_32)\n entries_0_conf <= 3'h1;\n else\n entries_0_conf <= _GEN_10;\n end\n else\n entries_0_conf <= _GEN_10;\n if (_GEN_36)\n entries_0_age <= _GEN_11;\n else if (_GEN_24)\n entries_0_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_0_age <= 3'h7;\n else\n entries_0_age <= _GEN_11;\n if (_GEN_38)\n entries_0_p_cnt <= _GEN_12;\n else\n entries_0_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_0_s_cnt <= 10'h0;\n else\n entries_0_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_0_s_cnt <= io_update_meta_s_cnt;\n else\n entries_0_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h0) begin\n entries_0_age <= _GEN_8;\n entries_0_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h1) begin\n entries_1_tag <= 10'h0;\n entries_1_conf <= 3'h0;\n entries_1_age <= 3'h0;\n entries_1_p_cnt <= 10'h0;\n entries_1_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h1) begin\n if (_GEN_31)\n entries_1_tag <= _GEN_9;\n else\n entries_1_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_1_conf <= 3'h0;\n else if (_GEN_17)\n entries_1_conf <= _GEN_10;\n else if (_GEN_19)\n entries_1_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_1_conf <= 3'h0;\n else if (_GEN_32)\n entries_1_conf <= 3'h1;\n else\n entries_1_conf <= _GEN_10;\n end\n else\n entries_1_conf <= _GEN_10;\n if (_GEN_36)\n entries_1_age <= _GEN_11;\n else if (_GEN_24)\n entries_1_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_1_age <= 3'h7;\n else\n entries_1_age <= _GEN_11;\n if (_GEN_38)\n entries_1_p_cnt <= _GEN_12;\n else\n entries_1_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_1_s_cnt <= 10'h0;\n else\n entries_1_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_1_s_cnt <= io_update_meta_s_cnt;\n else\n entries_1_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h1) begin\n entries_1_age <= _GEN_8;\n entries_1_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h2) begin\n entries_2_tag <= 10'h0;\n entries_2_conf <= 3'h0;\n entries_2_age <= 3'h0;\n entries_2_p_cnt <= 10'h0;\n entries_2_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h2) begin\n if (_GEN_31)\n entries_2_tag <= _GEN_9;\n else\n entries_2_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_2_conf <= 3'h0;\n else if (_GEN_17)\n entries_2_conf <= _GEN_10;\n else if (_GEN_19)\n entries_2_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_2_conf <= 3'h0;\n else if (_GEN_32)\n entries_2_conf <= 3'h1;\n else\n entries_2_conf <= _GEN_10;\n end\n else\n entries_2_conf <= _GEN_10;\n if (_GEN_36)\n entries_2_age <= _GEN_11;\n else if (_GEN_24)\n entries_2_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_2_age <= 3'h7;\n else\n entries_2_age <= _GEN_11;\n if (_GEN_38)\n entries_2_p_cnt <= _GEN_12;\n else\n entries_2_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_2_s_cnt <= 10'h0;\n else\n entries_2_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_2_s_cnt <= io_update_meta_s_cnt;\n else\n entries_2_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h2) begin\n entries_2_age <= _GEN_8;\n entries_2_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h3) begin\n entries_3_tag <= 10'h0;\n entries_3_conf <= 3'h0;\n entries_3_age <= 3'h0;\n entries_3_p_cnt <= 10'h0;\n entries_3_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h3) begin\n if (_GEN_31)\n entries_3_tag <= _GEN_9;\n else\n entries_3_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_3_conf <= 3'h0;\n else if (_GEN_17)\n entries_3_conf <= _GEN_10;\n else if (_GEN_19)\n entries_3_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_3_conf <= 3'h0;\n else if (_GEN_32)\n entries_3_conf <= 3'h1;\n else\n entries_3_conf <= _GEN_10;\n end\n else\n entries_3_conf <= _GEN_10;\n if (_GEN_36)\n entries_3_age <= _GEN_11;\n else if (_GEN_24)\n entries_3_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_3_age <= 3'h7;\n else\n entries_3_age <= _GEN_11;\n if (_GEN_38)\n entries_3_p_cnt <= _GEN_12;\n else\n entries_3_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_3_s_cnt <= 10'h0;\n else\n entries_3_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_3_s_cnt <= io_update_meta_s_cnt;\n else\n entries_3_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h3) begin\n entries_3_age <= _GEN_8;\n entries_3_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h4) begin\n entries_4_tag <= 10'h0;\n entries_4_conf <= 3'h0;\n entries_4_age <= 3'h0;\n entries_4_p_cnt <= 10'h0;\n entries_4_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h4) begin\n if (_GEN_31)\n entries_4_tag <= _GEN_9;\n else\n entries_4_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_4_conf <= 3'h0;\n else if (_GEN_17)\n entries_4_conf <= _GEN_10;\n else if (_GEN_19)\n entries_4_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_4_conf <= 3'h0;\n else if (_GEN_32)\n entries_4_conf <= 3'h1;\n else\n entries_4_conf <= _GEN_10;\n end\n else\n entries_4_conf <= _GEN_10;\n if (_GEN_36)\n entries_4_age <= _GEN_11;\n else if (_GEN_24)\n entries_4_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_4_age <= 3'h7;\n else\n entries_4_age <= _GEN_11;\n if (_GEN_38)\n entries_4_p_cnt <= _GEN_12;\n else\n entries_4_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_4_s_cnt <= 10'h0;\n else\n entries_4_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_4_s_cnt <= io_update_meta_s_cnt;\n else\n entries_4_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h4) begin\n entries_4_age <= _GEN_8;\n entries_4_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h5) begin\n entries_5_tag <= 10'h0;\n entries_5_conf <= 3'h0;\n entries_5_age <= 3'h0;\n entries_5_p_cnt <= 10'h0;\n entries_5_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h5) begin\n if (_GEN_31)\n entries_5_tag <= _GEN_9;\n else\n entries_5_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_5_conf <= 3'h0;\n else if (_GEN_17)\n entries_5_conf <= _GEN_10;\n else if (_GEN_19)\n entries_5_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_5_conf <= 3'h0;\n else if (_GEN_32)\n entries_5_conf <= 3'h1;\n else\n entries_5_conf <= _GEN_10;\n end\n else\n entries_5_conf <= _GEN_10;\n if (_GEN_36)\n entries_5_age <= _GEN_11;\n else if (_GEN_24)\n entries_5_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_5_age <= 3'h7;\n else\n entries_5_age <= _GEN_11;\n if (_GEN_38)\n entries_5_p_cnt <= _GEN_12;\n else\n entries_5_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_5_s_cnt <= 10'h0;\n else\n entries_5_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_5_s_cnt <= io_update_meta_s_cnt;\n else\n entries_5_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h5) begin\n entries_5_age <= _GEN_8;\n entries_5_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h6) begin\n entries_6_tag <= 10'h0;\n entries_6_conf <= 3'h0;\n entries_6_age <= 3'h0;\n entries_6_p_cnt <= 10'h0;\n entries_6_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h6) begin\n if (_GEN_31)\n entries_6_tag <= _GEN_9;\n else\n entries_6_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_6_conf <= 3'h0;\n else if (_GEN_17)\n entries_6_conf <= _GEN_10;\n else if (_GEN_19)\n entries_6_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_6_conf <= 3'h0;\n else if (_GEN_32)\n entries_6_conf <= 3'h1;\n else\n entries_6_conf <= _GEN_10;\n end\n else\n entries_6_conf <= _GEN_10;\n if (_GEN_36)\n entries_6_age <= _GEN_11;\n else if (_GEN_24)\n entries_6_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_6_age <= 3'h7;\n else\n entries_6_age <= _GEN_11;\n if (_GEN_38)\n entries_6_p_cnt <= _GEN_12;\n else\n entries_6_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_6_s_cnt <= 10'h0;\n else\n entries_6_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_6_s_cnt <= io_update_meta_s_cnt;\n else\n entries_6_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h6) begin\n entries_6_age <= _GEN_8;\n entries_6_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h7) begin\n entries_7_tag <= 10'h0;\n entries_7_conf <= 3'h0;\n entries_7_age <= 3'h0;\n entries_7_p_cnt <= 10'h0;\n entries_7_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h7) begin\n if (_GEN_31)\n entries_7_tag <= _GEN_9;\n else\n entries_7_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_7_conf <= 3'h0;\n else if (_GEN_17)\n entries_7_conf <= _GEN_10;\n else if (_GEN_19)\n entries_7_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_7_conf <= 3'h0;\n else if (_GEN_32)\n entries_7_conf <= 3'h1;\n else\n entries_7_conf <= _GEN_10;\n end\n else\n entries_7_conf <= _GEN_10;\n if (_GEN_36)\n entries_7_age <= _GEN_11;\n else if (_GEN_24)\n entries_7_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_7_age <= 3'h7;\n else\n entries_7_age <= _GEN_11;\n if (_GEN_38)\n entries_7_p_cnt <= _GEN_12;\n else\n entries_7_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_7_s_cnt <= 10'h0;\n else\n entries_7_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_7_s_cnt <= io_update_meta_s_cnt;\n else\n entries_7_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h7) begin\n entries_7_age <= _GEN_8;\n entries_7_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h8) begin\n entries_8_tag <= 10'h0;\n entries_8_conf <= 3'h0;\n entries_8_age <= 3'h0;\n entries_8_p_cnt <= 10'h0;\n entries_8_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h8) begin\n if (_GEN_31)\n entries_8_tag <= _GEN_9;\n else\n entries_8_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_8_conf <= 3'h0;\n else if (_GEN_17)\n entries_8_conf <= _GEN_10;\n else if (_GEN_19)\n entries_8_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_8_conf <= 3'h0;\n else if (_GEN_32)\n entries_8_conf <= 3'h1;\n else\n entries_8_conf <= _GEN_10;\n end\n else\n entries_8_conf <= _GEN_10;\n if (_GEN_36)\n entries_8_age <= _GEN_11;\n else if (_GEN_24)\n entries_8_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_8_age <= 3'h7;\n else\n entries_8_age <= _GEN_11;\n if (_GEN_38)\n entries_8_p_cnt <= _GEN_12;\n else\n entries_8_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_8_s_cnt <= 10'h0;\n else\n entries_8_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_8_s_cnt <= io_update_meta_s_cnt;\n else\n entries_8_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h8) begin\n entries_8_age <= _GEN_8;\n entries_8_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'h9) begin\n entries_9_tag <= 10'h0;\n entries_9_conf <= 3'h0;\n entries_9_age <= 3'h0;\n entries_9_p_cnt <= 10'h0;\n entries_9_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'h9) begin\n if (_GEN_31)\n entries_9_tag <= _GEN_9;\n else\n entries_9_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_9_conf <= 3'h0;\n else if (_GEN_17)\n entries_9_conf <= _GEN_10;\n else if (_GEN_19)\n entries_9_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_9_conf <= 3'h0;\n else if (_GEN_32)\n entries_9_conf <= 3'h1;\n else\n entries_9_conf <= _GEN_10;\n end\n else\n entries_9_conf <= _GEN_10;\n if (_GEN_36)\n entries_9_age <= _GEN_11;\n else if (_GEN_24)\n entries_9_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_9_age <= 3'h7;\n else\n entries_9_age <= _GEN_11;\n if (_GEN_38)\n entries_9_p_cnt <= _GEN_12;\n else\n entries_9_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_9_s_cnt <= 10'h0;\n else\n entries_9_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_9_s_cnt <= io_update_meta_s_cnt;\n else\n entries_9_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'h9) begin\n entries_9_age <= _GEN_8;\n entries_9_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'hA) begin\n entries_10_tag <= 10'h0;\n entries_10_conf <= 3'h0;\n entries_10_age <= 3'h0;\n entries_10_p_cnt <= 10'h0;\n entries_10_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'hA) begin\n if (_GEN_31)\n entries_10_tag <= _GEN_9;\n else\n entries_10_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_10_conf <= 3'h0;\n else if (_GEN_17)\n entries_10_conf <= _GEN_10;\n else if (_GEN_19)\n entries_10_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_10_conf <= 3'h0;\n else if (_GEN_32)\n entries_10_conf <= 3'h1;\n else\n entries_10_conf <= _GEN_10;\n end\n else\n entries_10_conf <= _GEN_10;\n if (_GEN_36)\n entries_10_age <= _GEN_11;\n else if (_GEN_24)\n entries_10_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_10_age <= 3'h7;\n else\n entries_10_age <= _GEN_11;\n if (_GEN_38)\n entries_10_p_cnt <= _GEN_12;\n else\n entries_10_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_10_s_cnt <= 10'h0;\n else\n entries_10_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_10_s_cnt <= io_update_meta_s_cnt;\n else\n entries_10_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'hA) begin\n entries_10_age <= _GEN_8;\n entries_10_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'hB) begin\n entries_11_tag <= 10'h0;\n entries_11_conf <= 3'h0;\n entries_11_age <= 3'h0;\n entries_11_p_cnt <= 10'h0;\n entries_11_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'hB) begin\n if (_GEN_31)\n entries_11_tag <= _GEN_9;\n else\n entries_11_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_11_conf <= 3'h0;\n else if (_GEN_17)\n entries_11_conf <= _GEN_10;\n else if (_GEN_19)\n entries_11_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_11_conf <= 3'h0;\n else if (_GEN_32)\n entries_11_conf <= 3'h1;\n else\n entries_11_conf <= _GEN_10;\n end\n else\n entries_11_conf <= _GEN_10;\n if (_GEN_36)\n entries_11_age <= _GEN_11;\n else if (_GEN_24)\n entries_11_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_11_age <= 3'h7;\n else\n entries_11_age <= _GEN_11;\n if (_GEN_38)\n entries_11_p_cnt <= _GEN_12;\n else\n entries_11_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_11_s_cnt <= 10'h0;\n else\n entries_11_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_11_s_cnt <= io_update_meta_s_cnt;\n else\n entries_11_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'hB) begin\n entries_11_age <= _GEN_8;\n entries_11_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'hC) begin\n entries_12_tag <= 10'h0;\n entries_12_conf <= 3'h0;\n entries_12_age <= 3'h0;\n entries_12_p_cnt <= 10'h0;\n entries_12_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'hC) begin\n if (_GEN_31)\n entries_12_tag <= _GEN_9;\n else\n entries_12_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_12_conf <= 3'h0;\n else if (_GEN_17)\n entries_12_conf <= _GEN_10;\n else if (_GEN_19)\n entries_12_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_12_conf <= 3'h0;\n else if (_GEN_32)\n entries_12_conf <= 3'h1;\n else\n entries_12_conf <= _GEN_10;\n end\n else\n entries_12_conf <= _GEN_10;\n if (_GEN_36)\n entries_12_age <= _GEN_11;\n else if (_GEN_24)\n entries_12_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_12_age <= 3'h7;\n else\n entries_12_age <= _GEN_11;\n if (_GEN_38)\n entries_12_p_cnt <= _GEN_12;\n else\n entries_12_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_12_s_cnt <= 10'h0;\n else\n entries_12_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_12_s_cnt <= io_update_meta_s_cnt;\n else\n entries_12_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'hC) begin\n entries_12_age <= _GEN_8;\n entries_12_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'hD) begin\n entries_13_tag <= 10'h0;\n entries_13_conf <= 3'h0;\n entries_13_age <= 3'h0;\n entries_13_p_cnt <= 10'h0;\n entries_13_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'hD) begin\n if (_GEN_31)\n entries_13_tag <= _GEN_9;\n else\n entries_13_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_13_conf <= 3'h0;\n else if (_GEN_17)\n entries_13_conf <= _GEN_10;\n else if (_GEN_19)\n entries_13_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_13_conf <= 3'h0;\n else if (_GEN_32)\n entries_13_conf <= 3'h1;\n else\n entries_13_conf <= _GEN_10;\n end\n else\n entries_13_conf <= _GEN_10;\n if (_GEN_36)\n entries_13_age <= _GEN_11;\n else if (_GEN_24)\n entries_13_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_13_age <= 3'h7;\n else\n entries_13_age <= _GEN_11;\n if (_GEN_38)\n entries_13_p_cnt <= _GEN_12;\n else\n entries_13_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_13_s_cnt <= 10'h0;\n else\n entries_13_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_13_s_cnt <= io_update_meta_s_cnt;\n else\n entries_13_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'hD) begin\n entries_13_age <= _GEN_8;\n entries_13_s_cnt <= _GEN_6;\n end\n if (doing_reset & reset_idx == 4'hE) begin\n entries_14_tag <= 10'h0;\n entries_14_conf <= 3'h0;\n entries_14_age <= 3'h0;\n entries_14_p_cnt <= 10'h0;\n entries_14_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & io_update_idx[3:0] == 4'hE) begin\n if (_GEN_31)\n entries_14_tag <= _GEN_9;\n else\n entries_14_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_14_conf <= 3'h0;\n else if (_GEN_17)\n entries_14_conf <= _GEN_10;\n else if (_GEN_19)\n entries_14_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_14_conf <= 3'h0;\n else if (_GEN_32)\n entries_14_conf <= 3'h1;\n else\n entries_14_conf <= _GEN_10;\n end\n else\n entries_14_conf <= _GEN_10;\n if (_GEN_36)\n entries_14_age <= _GEN_11;\n else if (_GEN_24)\n entries_14_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_14_age <= 3'h7;\n else\n entries_14_age <= _GEN_11;\n if (_GEN_38)\n entries_14_p_cnt <= _GEN_12;\n else\n entries_14_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_14_s_cnt <= 10'h0;\n else\n entries_14_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_14_s_cnt <= io_update_meta_s_cnt;\n else\n entries_14_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & f4_idx[3:0] == 4'hE) begin\n entries_14_age <= _GEN_8;\n entries_14_s_cnt <= _GEN_6;\n end\n if (doing_reset & (&reset_idx)) begin\n entries_15_tag <= 10'h0;\n entries_15_conf <= 3'h0;\n entries_15_age <= 3'h0;\n entries_15_p_cnt <= 10'h0;\n entries_15_s_cnt <= 10'h0;\n end\n else if (_GEN_42 & (&(io_update_idx[3:0]))) begin\n if (_GEN_31)\n entries_15_tag <= _GEN_9;\n else\n entries_15_tag <= io_update_idx[13:4];\n if (_GEN_14) begin\n if (_GEN_15)\n entries_15_conf <= 3'h0;\n else if (_GEN_17)\n entries_15_conf <= _GEN_10;\n else if (_GEN_19)\n entries_15_conf <= _wentry_conf_T;\n else if (_GEN_21)\n entries_15_conf <= 3'h0;\n else if (_GEN_32)\n entries_15_conf <= 3'h1;\n else\n entries_15_conf <= _GEN_10;\n end\n else\n entries_15_conf <= _GEN_10;\n if (_GEN_36)\n entries_15_age <= _GEN_11;\n else if (_GEN_24)\n entries_15_age <= _wentry_age_T;\n else if (_GEN_34)\n entries_15_age <= 3'h7;\n else\n entries_15_age <= _GEN_11;\n if (_GEN_38)\n entries_15_p_cnt <= _GEN_12;\n else\n entries_15_p_cnt <= io_update_meta_s_cnt;\n if (_GEN_14) begin\n if (_GEN_37)\n entries_15_s_cnt <= 10'h0;\n else\n entries_15_s_cnt <= _GEN_13;\n end\n else if (_GEN_41)\n entries_15_s_cnt <= io_update_meta_s_cnt;\n else\n entries_15_s_cnt <= _GEN_13;\n end\n else if (_GEN_7 & (&(f4_idx[3:0]))) begin\n entries_15_age <= _GEN_8;\n entries_15_s_cnt <= _GEN_6;\n end\n f3_entry_tag <= _GEN[io_f2_req_idx[3:0]];\n f3_entry_conf <= _GEN_0[io_f2_req_idx[3:0]];\n f3_entry_age <= _GEN_1[io_f2_req_idx[3:0]];\n f3_entry_p_cnt <= _GEN_2[io_f2_req_idx[3:0]];\n f3_entry_s_cnt <= io_update_repair & _GEN_4 ? io_update_meta_s_cnt : io_update_mispredict & _GEN_4 ? 10'h0 : _GEN_3[io_f2_req_idx[3:0]];\n f3_scnt_REG <= io_f2_req_idx;\n f3_tag <= io_f2_req_idx[13:4];\n f4_fire <= io_f3_req_fire;\n f4_entry_tag <= f3_entry_tag;\n f4_entry_conf <= f3_entry_conf;\n f4_entry_age <= f3_entry_age;\n f4_entry_p_cnt <= f3_entry_p_cnt;\n f4_tag <= f3_tag;\n f4_scnt <= f3_scnt;\n f4_idx_REG <= io_f2_req_idx;\n f4_idx <= f4_idx_REG;\n end\n assign io_f3_pred = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ^ io_f3_pred_in;\n assign io_f3_meta_s_cnt = f3_scnt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundRawFNToRecFN_e8_s24(\n input io_invalidExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [9:0] io_in_sExp,\n input [26:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [32:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 roundAnyRawFNToRecFN (\n .io_invalidExc (io_invalidExc),\n .io_in_isNaN (io_in_isNaN),\n .io_in_isInf (io_in_isInf),\n .io_in_isZero (io_in_isZero),\n .io_in_sign (io_in_sign),\n .io_in_sExp (io_in_sExp),\n .io_in_sig (io_in_sig),\n .io_roundingMode (io_roundingMode),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomBTBParams(\n nSets: Int = 128,\n nWays: Int = 2,\n offsetSz: Int = 13,\n extendedNSets: Int = 128\n)\n\n\nclass BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n override val nWays = params.nWays\n val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1\n val offsetSz = params.offsetSz\n val extendedNSets = params.extendedNSets\n\n require(isPow2(nSets))\n require(isPow2(extendedNSets) || extendedNSets == 0)\n require(extendedNSets <= nSets)\n require(extendedNSets >= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }\n val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n\n val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })\n val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })\n val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n\n for (w <- 0 until bankWidth) {\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := Mux(\n entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n for (w <- 0 until nWays) {\n when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {\n btb(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wbtb_mask).asBools\n )\n meta(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wmeta_mask).asBools\n )\n\n\n }\n }\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n\n}", + "response": "module ebtb(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [39:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [39:0] W0_data\n);\n\n ebtb_ext ebtb_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Register File (Abstract class and Synthesizable RegFile)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.ArrayBuffer\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * IO bundle for a register read port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = Input(UInt(addrWidth.W))\n val data = Output(UInt(dataWidth.W))\n}\n\n/**\n * IO bundle for the register write port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n}\n\n/**\n * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.\n */\nobject WritePort\n{\n def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)\n (implicit p: Parameters): Valid[RegisterFileWritePort] = {\n val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))\n\n wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype\n wport.bits.addr := enq.bits.uop.pdst\n wport.bits.data := enq.bits.data\n enq.ready := true.B\n wport\n }\n}\n\n/**\n * Register file abstract class\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nabstract class RegisterFile(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new BoomBundle {\n val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))\n val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))\n })\n\n private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)\n private val type_str = if (registerWidth == fLen+1) \"Floating Point\" else \"Integer\"\n override def toString: String = BoomCoreStringPrefix(\n \"==\" + type_str + \" Regfile==\",\n \"Num RF Read Ports : \" + numReadPorts,\n \"Num RF Write Ports : \" + numWritePorts,\n \"RF Cost (R+W)*(R+2W) : \" + rf_cost,\n \"Bypassable Units : \" + bypassableArray)\n}\n\n/**\n * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nclass RegisterFileSynthesizable(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean])\n (implicit p: Parameters)\n extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)\n{\n // --------------------------------------------------------------\n\n val regfile = Mem(numRegisters, UInt(registerWidth.W))\n\n // --------------------------------------------------------------\n // Read ports.\n\n val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))\n\n // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).\n val read_addrs = io.read_ports.map(p => RegNext(p.addr))\n\n for (i <- 0 until numReadPorts) {\n read_data(i) := regfile(read_addrs(i))\n }\n\n // --------------------------------------------------------------\n // Bypass out of the ALU's write ports.\n // We are assuming we cannot bypass a writer to a reader within the regfile memory\n // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.\n // But since these bypasses are expensive, and not all write ports need to bypass their data,\n // only perform the w->r bypass on a select number of write ports.\n\n require (bypassableArray.length == io.write_ports.length)\n\n if (bypassableArray.reduce(_||_)) {\n val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()\n io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }\n\n for (i <- 0 until numReadPorts) {\n val bypass_ens = bypassable_wports.map(x => x.valid &&\n x.bits.addr === read_addrs(i))\n\n val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))\n\n io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))\n }\n } else {\n for (i <- 0 until numReadPorts) {\n io.read_ports(i).data := read_data(i)\n }\n }\n\n // --------------------------------------------------------------\n // Write ports.\n\n for (wport <- io.write_ports) {\n when (wport.valid) {\n regfile(wport.bits.addr) := wport.bits.data\n }\n }\n\n // ensure there is only 1 writer per register (unless to preg0)\n if (numWritePorts > 1) {\n for (i <- 0 until (numWritePorts - 1)) {\n for (j <- (i + 1) until numWritePorts) {\n assert(!io.write_ports(i).valid ||\n !io.write_ports(j).valid ||\n (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||\n (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here\n \"[regfile] too many writers a register\")\n }\n }\n }\n}", + "response": "module regfile_48x65(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [64:0] R0_data,\n input [5:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [64:0] R1_data,\n input [5:0] R2_addr,\n input R2_en,\n input R2_clk,\n output [64:0] R2_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [64:0] W0_data,\n input [5:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [64:0] W1_data\n);\n\n reg [64:0] Memory[0:47];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 65'bx;\n assign R2_data = R2_en ? Memory[R2_addr] : 65'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of\nthe University of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.log2Up\n\nimport scala.math._\nimport consts._\n\nclass RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module\n{\n override def desiredName = s\"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}\"\n val io = IO(new Bundle {\n val in = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val signedOut = Input(Bool())\n val out = Output(Bits(intWidth.W))\n val intExceptionFlags = Output(Bits(3.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)\n\n val magGeOne = rawIn.sExp(expWidth)\n val posExp = rawIn.sExp(expWidth - 1, 0)\n val magJustBelowOne = !magGeOne && posExp.andR\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n /*------------------------------------------------------------------------\n | Assuming the input floating-point value is not a NaN, its magnitude is\n | at least 1, and it is not obviously so large as to lead to overflow,\n | convert its significand to fixed-point (i.e., with the binary point in a\n | fixed location). For a non-NaN input with a magnitude less than 1, this\n | expression contrives to ensure that the integer bits of 'alignedSig'\n | will all be zeros.\n *------------------------------------------------------------------------*/\n val shiftedSig =\n (magGeOne ## rawIn.sig(sigWidth - 2, 0))<<\n Mux(magGeOne,\n rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),\n 0.U\n )\n val alignedSig =\n (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR\n val unroundedInt = 0.U(intWidth.W) | alignedSig>>2\n\n val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)\n val roundIncr_near_even =\n (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||\n (magJustBelowOne && alignedSig(1, 0).orR)\n val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne\n val roundIncr =\n (roundingMode_near_even && roundIncr_near_even ) ||\n (roundingMode_near_maxMag && roundIncr_near_maxMag) ||\n ((roundingMode_min || roundingMode_odd) &&\n (rawIn.sign && common_inexact)) ||\n (roundingMode_max && (!rawIn.sign && common_inexact))\n val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)\n val roundedInt =\n Mux(roundIncr ^ rawIn.sign,\n complUnroundedInt + 1.U,\n complUnroundedInt\n ) | (roundingMode_odd && common_inexact)\n\n val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)\n//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM\n//*** 'unroundedInt'?:\n val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr\n val common_overflow =\n Mux(magGeOne,\n (posExp >= intWidth.U) ||\n Mux(io.signedOut, \n Mux(rawIn.sign,\n magGeOne_atOverflowEdge &&\n (unroundedInt(intWidth - 2, 0).orR || roundIncr),\n magGeOne_atOverflowEdge ||\n ((posExp === (intWidth - 2).U) && roundCarryBut2)\n ),\n rawIn.sign ||\n (magGeOne_atOverflowEdge &&\n unroundedInt(intWidth - 2) && roundCarryBut2)\n ),\n !io.signedOut && rawIn.sign && roundIncr\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val invalidExc = rawIn.isNaN || rawIn.isInf\n val overflow = !invalidExc && common_overflow\n val inexact = !invalidExc && !common_overflow && common_inexact\n\n val excSign = !rawIn.isNaN && rawIn.sign\n val excOut =\n Mux((io.signedOut === excSign),\n (BigInt(1)<<(intWidth - 1)).U,\n 0.U\n ) |\n Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)\n\n io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)\n io.intExceptionFlags := invalidExc ## overflow ## inexact\n}", + "response": "module RecFNToIN_e11_s53_i64(\n input [64:0] io_in,\n input [2:0] io_roundingMode,\n input io_signedOut,\n output [63:0] io_out,\n output [2:0] io_intExceptionFlags\n);\n\n wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61];\n wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));\n wire roundingMode_odd = io_roundingMode == 3'h6;\n wire [115:0] shiftedSig = {63'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[57:52] : 6'h0);\n wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};\n wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));\n wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | roundingMode_odd) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;\n wire [63:0] complUnroundedInt = {64{io_in[64]}} ^ shiftedSig[115:52];\n wire [63:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 64'h1 : complUnroundedInt;\n wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h3F;\n wire roundCarryBut2 = (&(shiftedSig[113:52])) & roundIncr;\n wire common_overflow = io_in[63] ? (|(io_in[62:58])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[114:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h3E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[114] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;\n wire invalidExc = rawIn_isNaN | (&(io_in[63:62])) & ~(io_in[61]);\n wire excSign = ~rawIn_isNaN & io_in[64];\n assign io_out = invalidExc | common_overflow ? {io_signedOut == excSign, {63{~excSign}}} : {_roundedInt_T_3[63:1], _roundedInt_T_3[0] | roundingMode_odd & common_inexact};\n assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile.FPConstants._\nimport freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket\nimport freechips.rocketchip.util.uintToBitPat\nimport boom.v3.common._\nimport boom.v3.util.{ImmGenRm, ImmGenTyp}\n\n/**\n * FP Decoder for the FPU\n *\n * TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?\n * most of these signals are already created, just need to be translated\n * to the Rocket FPU-speak\n */\nclass UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters\n{\n val io = IO(new Bundle {\n val uopc = Input(Bits(UOPC_SZ.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n // TODO change N,Y,X to BitPat(\"b1\"), BitPat(\"b0\"), and BitPat(\"b?\")\n val N = false.B\n val Y = true.B\n val X = false.B\n\n val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)\n\n val f_table: Array[(BitPat, List[BitPat])] =\n // Note: not all of these signals are used or necessary, but we're\n // constrained by the need to fit the rocket.FPU units' ctrl signals.\n // swap12 fma\n // | swap32 | div\n // | | typeTagIn | | sqrt\n // ldst | | | typeTagOut | | wflags\n // | wen | | | | from_int | | |\n // | | ren1 | | | | | to_int | | |\n // | | | ren2 | | | | | | fastpipe |\n // | | | | ren3 | | | | | | | | | |\n // | | | | | | | | | | | | | | | |\n Array(\n BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),\n BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),\n BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),\n\n BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),\n\n BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),\n\n BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),\n\n BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),\n\n BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),\n\n BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)\n )\n\n val d_table: Array[(BitPat, List[BitPat])] =\n Array(\n BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),\n BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),\n BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),\n BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),\n BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),\n\n BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),\n\n BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),\n\n BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),\n\n BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),\n\n BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),\n\n BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),\n\n BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)\n )\n\n// val insns = fLen match {\n// case 32 => f_table\n// case 64 => f_table ++ d_table\n// }\n val insns = f_table ++ d_table\n val decoder = rocket.DecodeLogic(io.uopc, default, insns)\n\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,\n s.div, s.sqrt, s.wflags)\n sigs zip decoder map {case(s,d) => s := d}\n s.vec := false.B\n}\n\n/**\n * FP fused multiple add decoder for the FPU\n */\nclass FMADecoder extends Module\n{\n val io = IO(new Bundle {\n val uopc = Input(UInt(UOPC_SZ.W))\n val cmd = Output(UInt(2.W))\n })\n\n val default: List[BitPat] = List(BitPat(\"b??\"))\n val table: Array[(BitPat, List[BitPat])] =\n Array(\n BitPat(uopFADD_S) -> List(BitPat(\"b00\")),\n BitPat(uopFSUB_S) -> List(BitPat(\"b01\")),\n BitPat(uopFMUL_S) -> List(BitPat(\"b00\")),\n BitPat(uopFMADD_S) -> List(BitPat(\"b00\")),\n BitPat(uopFMSUB_S) -> List(BitPat(\"b01\")),\n BitPat(uopFNMADD_S) -> List(BitPat(\"b11\")),\n BitPat(uopFNMSUB_S) -> List(BitPat(\"b10\")),\n BitPat(uopFADD_D) -> List(BitPat(\"b00\")),\n BitPat(uopFSUB_D) -> List(BitPat(\"b01\")),\n BitPat(uopFMUL_D) -> List(BitPat(\"b00\")),\n BitPat(uopFMADD_D) -> List(BitPat(\"b00\")),\n BitPat(uopFMSUB_D) -> List(BitPat(\"b01\")),\n BitPat(uopFNMADD_D) -> List(BitPat(\"b11\")),\n BitPat(uopFNMSUB_D) -> List(BitPat(\"b10\"))\n )\n\n val decoder = rocket.DecodeLogic(io.uopc, default, table)\n\n val (cmd: UInt) :: Nil = decoder\n io.cmd := cmd\n}\n\n/**\n * Bundle representing data to be sent to the FPU\n */\nclass FpuReq()(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val rs1_data = Bits(65.W)\n val rs2_data = Bits(65.W)\n val rs3_data = Bits(65.W)\n val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)\n}\n\n/**\n * FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)\n */\nclass FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(new ValidIO(new FpuReq))\n val resp = new ValidIO(new ExeUnitResp(65))\n })\n io.resp.bits := DontCare\n\n // all FP units are padded out to the same latency for easy scheduling of the write port\n val fpu_latency = dfmaLatency\n val io_req = io.req.bits\n\n val fp_decoder = Module(new UOPCodeFPUDecoder)\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n\n def fuInput(minT: Option[tile.FType]): tile.FPInput = {\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, minT)\n req.in2 := unbox(io_req.rs2_data, tag, minT)\n req.in3 := unbox(io_req.rs3_data, tag, minT)\n when (fp_ctrl.swap23) { req.in3 := req.in2 }\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below\n when (io_req.uop.uopc === uopFMV_X_W) {\n req.fmt := 0.U\n }\n\n val fma_decoder = Module(new FMADecoder)\n fma_decoder.io.uopc := io_req.uop.uopc\n req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))\n req\n }\n\n val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))\n dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)\n dfma.io.in.bits := fuInput(Some(dfma.t))\n\n val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))\n sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new tile.FPToInt)\n fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),\n fpiu.io.out.bits, fpu_latency-1)\n val fpiu_result = Wire(new tile.FPResult)\n fpiu_result.data := fpiu_out.bits.toint\n fpiu_result.exc := fpiu_out.bits.exc\n\n val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket\n fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits\n\n // Response (all FP units have been padded out to the same latency)\n io.resp.valid := fpiu_out.valid ||\n fpmu.io.out.valid ||\n sfma.io.out.valid ||\n dfma.io.out.valid\n val fpu_out_data =\n Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),\n Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),\n Mux(fpiu_out.valid, fpiu_result.data,\n box(fpmu.io.out.bits.data, fpmu_double))))\n\n val fpu_out_exc =\n Mux(dfma.io.out.valid, dfma.io.out.bits.exc,\n Mux(sfma.io.out.valid, sfma.io.out.bits.exc,\n Mux(fpiu_out.valid, fpiu_result.exc,\n fpmu.io.out.bits.exc)))\n\n io.resp.bits.data := fpu_out_data\n io.resp.bits.fflags.valid := io.resp.valid\n io.resp.bits.fflags.bits.flags := fpu_out_exc\n}", + "response": "module FMADecoder(\n input [6:0] io_uopc,\n output [1:0] io_cmd\n);\n\n wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);\n assign io_cmd = {|{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of\nthe University of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.log2Up\n\nimport scala.math._\nimport consts._\n\nclass RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module\n{\n override def desiredName = s\"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}\"\n val io = IO(new Bundle {\n val in = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val signedOut = Input(Bool())\n val out = Output(Bits(intWidth.W))\n val intExceptionFlags = Output(Bits(3.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)\n\n val magGeOne = rawIn.sExp(expWidth)\n val posExp = rawIn.sExp(expWidth - 1, 0)\n val magJustBelowOne = !magGeOne && posExp.andR\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n /*------------------------------------------------------------------------\n | Assuming the input floating-point value is not a NaN, its magnitude is\n | at least 1, and it is not obviously so large as to lead to overflow,\n | convert its significand to fixed-point (i.e., with the binary point in a\n | fixed location). For a non-NaN input with a magnitude less than 1, this\n | expression contrives to ensure that the integer bits of 'alignedSig'\n | will all be zeros.\n *------------------------------------------------------------------------*/\n val shiftedSig =\n (magGeOne ## rawIn.sig(sigWidth - 2, 0))<<\n Mux(magGeOne,\n rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),\n 0.U\n )\n val alignedSig =\n (shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR\n val unroundedInt = 0.U(intWidth.W) | alignedSig>>2\n\n val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)\n val roundIncr_near_even =\n (magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||\n (magJustBelowOne && alignedSig(1, 0).orR)\n val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne\n val roundIncr =\n (roundingMode_near_even && roundIncr_near_even ) ||\n (roundingMode_near_maxMag && roundIncr_near_maxMag) ||\n ((roundingMode_min || roundingMode_odd) &&\n (rawIn.sign && common_inexact)) ||\n (roundingMode_max && (!rawIn.sign && common_inexact))\n val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)\n val roundedInt =\n Mux(roundIncr ^ rawIn.sign,\n complUnroundedInt + 1.U,\n complUnroundedInt\n ) | (roundingMode_odd && common_inexact)\n\n val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)\n//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM\n//*** 'unroundedInt'?:\n val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr\n val common_overflow =\n Mux(magGeOne,\n (posExp >= intWidth.U) ||\n Mux(io.signedOut, \n Mux(rawIn.sign,\n magGeOne_atOverflowEdge &&\n (unroundedInt(intWidth - 2, 0).orR || roundIncr),\n magGeOne_atOverflowEdge ||\n ((posExp === (intWidth - 2).U) && roundCarryBut2)\n ),\n rawIn.sign ||\n (magGeOne_atOverflowEdge &&\n unroundedInt(intWidth - 2) && roundCarryBut2)\n ),\n !io.signedOut && rawIn.sign && roundIncr\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val invalidExc = rawIn.isNaN || rawIn.isInf\n val overflow = !invalidExc && common_overflow\n val inexact = !invalidExc && !common_overflow && common_inexact\n\n val excSign = !rawIn.isNaN && rawIn.sign\n val excOut =\n Mux((io.signedOut === excSign),\n (BigInt(1)<<(intWidth - 1)).U,\n 0.U\n ) |\n Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)\n\n io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)\n io.intExceptionFlags := invalidExc ## overflow ## inexact\n}", + "response": "module RecFNToIN_e11_s53_i32(\n input [64:0] io_in,\n input [2:0] io_roundingMode,\n input io_signedOut,\n output [2:0] io_intExceptionFlags\n);\n\n wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52]));\n wire [83:0] shiftedSig = {31'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[56:52] : 5'h0);\n wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], |(shiftedSig[50:0])};\n wire common_inexact = io_in[63] ? (|_roundIncr_near_even_T_6) : (|(io_in[63:61]));\n wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) | (&_roundIncr_near_even_T_6)) | magJustBelowOne & (|_roundIncr_near_even_T_6)) | io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] | magJustBelowOne) | (io_roundingMode == 3'h2 | io_roundingMode == 3'h6) & io_in[64] & common_inexact | io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact;\n wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h1F;\n wire roundCarryBut2 = (&(shiftedSig[81:52])) & roundIncr;\n wire common_overflow = io_in[63] ? (|(io_in[62:57])) | (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((|(shiftedSig[82:52])) | roundIncr) : magGeOne_atOverflowEdge | io_in[62:52] == 11'h1E & roundCarryBut2) : io_in[64] | magGeOne_atOverflowEdge & shiftedSig[82] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr;\n wire invalidExc = (&(io_in[63:62])) & io_in[61] | (&(io_in[63:62])) & ~(io_in[61]);\n assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable_1(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [10:0] table_MPORT_data_3;\n wire [10:0] table_MPORT_data_2;\n wire [10:0] table_MPORT_data_1;\n wire [10:0] table_MPORT_data_0;\n wire [43:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [6:0] reset_idx;\n wire [6:0] s1_hashed_idx = {io_f1_req_pc[9:7], io_f1_req_pc[6:3] ^ io_f1_req_ghist[3:0]};\n reg [6:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [18:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);\n wire [3:0] _GEN = io_update_pc[6:3] ^ io_update_hist[3:0];\n wire [6:0] update_idx = {io_update_pc[9:7], _GEN};\n wire [3:0] _GEN_0 = io_update_pc[13:10] ^ io_update_hist[3:0];\n wire [6:0] update_tag = {io_update_pc[16:14], _GEN_0};\n assign table_MPORT_data_0 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:14], _GEN_0, update_wdata_3_ctr};\n wire [6:0] _GEN_1 = {io_update_pc[9:7], _GEN};\n wire _GEN_2 = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN_2 & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN_2 & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN_2 & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN_2 & update_hi_wdata_3;\n wire [3:0] _GEN_3 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_4 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_4 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_4 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_4 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_4 & update_lo_wdata_3;\n reg [6:0] wrbypass_tags_0;\n reg [6:0] wrbypass_tags_1;\n reg [6:0] wrbypass_idxs_0;\n reg [6:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_6 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_7 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_8 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_6) ? 3'h7 : _GEN_6 + 3'h1) : _GEN_6 == 3'h0 ? 3'h0 : _GEN_6 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_7) ? 3'h7 : _GEN_7 + 3'h1) : _GEN_7 == 3'h0 ? 3'h0 : _GEN_7 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_8) ? 3'h7 : _GEN_8 + 3'h1) : _GEN_8 == 3'h0 ? 3'h0 : _GEN_8 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire _GEN_9 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_10 = ~_GEN_9 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_11 = ~_GEN_9 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 7'h0;\n clear_u_ctr <= 19'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 7'h7F & doing_reset;\n reset_idx <= reset_idx + {6'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;\n if (~_GEN_9 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= {io_f1_req_pc[16:14], io_f1_req_pc[13:10] ^ io_f1_req_ghist[3:0]};\n io_f3_resp_0_valid_REG <= _table_R0_data[10] & _table_R0_data[9:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[21] & _table_R0_data[20:14] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[13:11];\n io_f3_resp_2_valid_REG <= _table_R0_data[32] & _table_R0_data[31:25] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[24:22];\n io_f3_resp_3_valid_REG <= _table_R0_data[43] & _table_R0_data[42:36] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[35:33];\n if (_GEN_10) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_11) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_10) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_11) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_9) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us_0 hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : _GEN_1),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN_2 ? 4'hF : _GEN_3)\n );\n lo_us_0 lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : _GEN_1),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_4 ? 4'hF : _GEN_3)\n );\n table_0_0 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Fetch Target Queue (FTQ)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.\n//\n// TODO:\n// * reduce port counts.\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.util.{Str}\n\nimport boom.v3.common._\nimport boom.v3.exu._\nimport boom.v3.util._\n\n/**\n * FTQ Parameters used in configurations\n *\n * @param nEntries # of entries in the FTQ\n */\ncase class FtqParameters(\n nEntries: Int = 16\n)\n\n/**\n * Bundle to add to the FTQ RAM and to be used as the pass in IO\n */\nclass FTQBundle(implicit p: Parameters) extends BoomBundle\n with HasBoomFrontendParameters\n{\n // // TODO compress out high-order bits\n // val fetch_pc = UInt(vaddrBitsExtended.W)\n // IDX of instruction that was predicted taken, if any\n val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))\n // Was the CFI in this bundle found to be taken? or not\n val cfi_taken = Bool()\n // Was this CFI mispredicted by the branch prediction pipeline?\n val cfi_mispredicted = Bool()\n // What type of CFI was taken out of this bundle\n val cfi_type = UInt(CFI_SZ.W)\n // mask of branches which were visible in this fetch bundle\n val br_mask = UInt(fetchWidth.W)\n // This CFI is likely a CALL\n val cfi_is_call = Bool()\n // This CFI is likely a RET\n val cfi_is_ret = Bool()\n // Is the NPC after the CFI +4 or +2\n val cfi_npc_plus4 = Bool()\n // What was the top of the RAS that this bundle saw?\n val ras_top = UInt(vaddrBitsExtended.W)\n val ras_idx = UInt(log2Ceil(nRasEntries).W)\n\n // Which bank did this start from?\n val start_bank = UInt(1.W)\n\n // // Metadata for the branch predictor\n // val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))\n}\n\n/**\n * IO to provide a port for a FunctionalUnit to get the PC of an instruction.\n * And for JALRs, the PC of the next instruction.\n */\nclass GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle\n{\n val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))\n\n val entry = Output(new FTQBundle)\n val ghist = Output(new GlobalHistory)\n\n val pc = Output(UInt(vaddrBitsExtended.W))\n val com_pc = Output(UInt(vaddrBitsExtended.W))\n\n // the next_pc may not be valid (stalled or still being fetched)\n val next_val = Output(Bool())\n val next_pc = Output(UInt(vaddrBitsExtended.W))\n}\n\n/**\n * Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the\n * processor.\n *\n * @param num_entries # of entries in the FTQ\n */\nclass FetchTargetQueue(implicit p: Parameters) extends BoomModule\n with HasBoomCoreParameters\n with HasBoomFrontendParameters\n{\n val num_entries = ftqSz\n private val idx_sz = log2Ceil(num_entries)\n\n val io = IO(new BoomBundle {\n // Enqueue one entry for every fetch cycle.\n val enq = Flipped(Decoupled(new FetchBundle()))\n // Pass to FetchBuffer (newly fetched instructions).\n val enq_idx = Output(UInt(idx_sz.W))\n // ROB tells us the youngest committed ftq_idx to remove from FTQ.\n val deq = Flipped(Valid(UInt(idx_sz.W)))\n\n // Give PC info to BranchUnit.\n val get_ftq_pc = Vec(2, new GetPCFromFtqIO())\n\n\n // Used to regenerate PC for trace port stuff in FireSim\n // Don't tape this out, this blows up the FTQ\n val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))\n val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))\n\n val redirect = Input(Valid(UInt(idx_sz.W)))\n\n val brupdate = Input(new BrUpdateInfo)\n\n val bpdupdate = Output(Valid(new BranchPredictionUpdate))\n\n val ras_update = Output(Bool())\n val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))\n val ras_update_pc = Output(UInt(vaddrBitsExtended.W))\n\n })\n val bpd_ptr = RegInit(0.U(idx_sz.W))\n val deq_ptr = RegInit(0.U(idx_sz.W))\n val enq_ptr = RegInit(1.U(idx_sz.W))\n\n val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||\n (WrapInc(enq_ptr, num_entries) === bpd_ptr))\n\n\n val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))\n val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))\n val ram = Reg(Vec(num_entries, new FTQBundle))\n val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }\n val lhist = if (useLHist) {\n Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))\n } else {\n None\n }\n\n val do_enq = io.enq.fire\n\n\n // This register lets us initialize the ghist to 0\n val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))\n val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))\n val prev_pc = RegInit(0.U(vaddrBitsExtended.W))\n when (do_enq) {\n\n pcs(enq_ptr) := io.enq.bits.pc\n\n val new_entry = Wire(new FTQBundle)\n\n new_entry.cfi_idx := io.enq.bits.cfi_idx\n // Initially, if we see a CFI, it is assumed to be taken.\n // Branch resolutions may change this\n new_entry.cfi_taken := io.enq.bits.cfi_idx.valid\n new_entry.cfi_mispredicted := false.B\n new_entry.cfi_type := io.enq.bits.cfi_type\n new_entry.cfi_is_call := io.enq.bits.cfi_is_call\n new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret\n new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4\n new_entry.ras_top := io.enq.bits.ras_top\n new_entry.ras_idx := io.enq.bits.ghist.ras_idx\n new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask\n new_entry.start_bank := bank(io.enq.bits.pc)\n\n val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,\n io.enq.bits.ghist,\n prev_ghist.update(\n prev_entry.br_mask,\n prev_entry.cfi_taken,\n prev_entry.br_mask(prev_entry.cfi_idx.bits),\n prev_entry.cfi_idx.bits,\n prev_entry.cfi_idx.valid,\n prev_pc,\n prev_entry.cfi_is_call,\n prev_entry.cfi_is_ret\n )\n )\n\n lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))\n ghist.map( g => g.write(enq_ptr, new_ghist))\n meta.write(enq_ptr, io.enq.bits.bpd_meta)\n ram(enq_ptr) := new_entry\n\n prev_pc := io.enq.bits.pc\n prev_entry := new_entry\n prev_ghist := new_ghist\n\n enq_ptr := WrapInc(enq_ptr, num_entries)\n }\n\n io.enq_idx := enq_ptr\n\n io.bpdupdate.valid := false.B\n io.bpdupdate.bits := DontCare\n\n when (io.deq.valid) {\n deq_ptr := io.deq.bits\n }\n\n // This register avoids a spurious bpd update on the first fetch packet\n val first_empty = RegInit(true.B)\n\n // We can update the branch predictors when we know the target of the\n // CFI in this fetch bundle\n\n val ras_update = WireInit(false.B)\n val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))\n val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))\n io.ras_update := RegNext(ras_update)\n io.ras_update_pc := RegNext(ras_update_pc)\n io.ras_update_idx := RegNext(ras_update_idx)\n\n val bpd_update_mispredict = RegInit(false.B)\n val bpd_update_repair = RegInit(false.B)\n val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))\n\n val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,\n Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))\n val bpd_entry = RegNext(ram(bpd_idx))\n val bpd_ghist = ghist(0).read(bpd_idx, true.B)\n val bpd_lhist = if (useLHist) {\n lhist.get.read(bpd_idx, true.B)\n } else {\n VecInit(Seq.fill(nBanks) { 0.U })\n }\n val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs\n val bpd_pc = RegNext(pcs(bpd_idx))\n val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))\n\n when (io.redirect.valid) {\n bpd_update_mispredict := false.B\n bpd_update_repair := false.B\n } .elsewhen (RegNext(io.brupdate.b2.mispredict)) {\n bpd_update_mispredict := true.B\n bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)\n bpd_end_idx := RegNext(enq_ptr)\n } .elsewhen (bpd_update_mispredict) {\n bpd_update_mispredict := false.B\n bpd_update_repair := true.B\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {\n bpd_repair_pc := bpd_pc\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair) {\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||\n bpd_pc === bpd_repair_pc) {\n bpd_update_repair := false.B\n }\n\n }\n\n\n val do_commit_update = (!bpd_update_mispredict &&\n !bpd_update_repair &&\n bpd_ptr =/= deq_ptr &&\n enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&\n !io.brupdate.b2.mispredict &&\n !io.redirect.valid && !RegNext(io.redirect.valid))\n val do_mispredict_update = bpd_update_mispredict\n val do_repair_update = bpd_update_repair\n\n when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {\n val cfi_idx = bpd_entry.cfi_idx.bits\n val valid_repair = bpd_pc =/= bpd_repair_pc\n\n io.bpdupdate.valid := (!first_empty &&\n (bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&\n !(RegNext(do_repair_update) && !valid_repair))\n io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)\n io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)\n io.bpdupdate.bits.pc := bpd_pc\n io.bpdupdate.bits.btb_mispredicts := 0.U\n io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,\n MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)\n io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx\n io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted\n io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken\n io.bpdupdate.bits.target := bpd_target\n io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)\n io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR\n io.bpdupdate.bits.ghist := bpd_ghist\n io.bpdupdate.bits.lhist := bpd_lhist\n io.bpdupdate.bits.meta := bpd_meta\n\n first_empty := false.B\n }\n\n when (do_commit_update) {\n bpd_ptr := WrapInc(bpd_ptr, num_entries)\n }\n\n io.enq.ready := RegNext(!full || do_commit_update)\n\n val redirect_idx = io.redirect.bits\n val redirect_entry = ram(redirect_idx)\n val redirect_new_entry = WireInit(redirect_entry)\n\n when (io.redirect.valid) {\n enq_ptr := WrapInc(io.redirect.bits, num_entries)\n\n when (io.brupdate.b2.mispredict) {\n val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^\n Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)\n redirect_new_entry.cfi_idx.valid := true.B\n redirect_new_entry.cfi_idx.bits := new_cfi_idx\n redirect_new_entry.cfi_mispredicted := true.B\n redirect_new_entry.cfi_taken := io.brupdate.b2.taken\n redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx\n redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx\n }\n\n ras_update := true.B\n ras_update_pc := redirect_entry.ras_top\n ras_update_idx := redirect_entry.ras_idx\n\n } .elsewhen (RegNext(io.redirect.valid)) {\n prev_entry := RegNext(redirect_new_entry)\n prev_ghist := bpd_ghist\n prev_pc := bpd_pc\n\n ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)\n }\n\n //-------------------------------------------------------------\n // **** Core Read PCs ****\n //-------------------------------------------------------------\n\n for (i <- 0 until 2) {\n val idx = io.get_ftq_pc(i).ftq_idx\n val next_idx = WrapInc(idx, num_entries)\n val next_is_enq = (next_idx === enq_ptr) && io.enq.fire\n val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))\n val get_entry = ram(idx)\n val next_entry = ram(next_idx)\n io.get_ftq_pc(i).entry := RegNext(get_entry)\n if (i == 1)\n io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)\n else\n io.get_ftq_pc(i).ghist := DontCare\n io.get_ftq_pc(i).pc := RegNext(pcs(idx))\n io.get_ftq_pc(i).next_pc := RegNext(next_pc)\n io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)\n io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))\n }\n\n for (w <- 0 until coreWidth) {\n io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))\n }\n}", + "response": "module ghist_1(\n input [3:0] R0_addr,\n input R0_clk,\n output [71:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [71:0] W0_data\n);\n\n ghist_0_ext ghist_0_ext (\n .R0_addr (R0_addr),\n .R0_en (1'h1),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}\nimport freechips.rocketchip.util._\n\nimport ALU._\n\nclass MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {\n val fn = Bits(SZ_ALU_FN.W)\n val dw = Bits(SZ_DW.W)\n val in1 = Bits(dataBits.W)\n val in2 = Bits(dataBits.W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {\n val data = Bits(dataBits.W)\n val full_data = Bits((2*dataBits).W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {\n val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))\n val kill = Input(Bool())\n val resp = Decoupled(new MultiplierResp(dataBits, tagBits))\n}\n\ncase class MulDivParams(\n mulUnroll: Int = 1,\n divUnroll: Int = 1,\n mulEarlyOut: Boolean = false,\n divEarlyOut: Boolean = false,\n divEarlyOutGranularity: Int = 1\n)\n\nclass MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {\n private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)\n private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)\n def minLatency: Int = (minDivLatency ++ minMulLatency).min\n\n val io = IO(new MultiplierIO(width, log2Up(nXpr)))\n val w = io.req.bits.in1.getWidth\n val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll\n val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0\n \n val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)\n val state = RegInit(s_ready)\n \n val req = Reg(chiselTypeOf(io.req.bits))\n val count = Reg(UInt(log2Ceil(\n ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++\n (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))\n val neg_out = Reg(Bool())\n val isHi = Reg(Bool())\n val resHi = Reg(Bool())\n val divisor = Reg(Bits((w+1).W)) // div only needs w bits\n val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits\n\n val mulDecode = List(\n FN_MUL -> List(Y, N, X, X),\n FN_MULH -> List(Y, Y, Y, Y),\n FN_MULHU -> List(Y, Y, N, N),\n FN_MULHSU -> List(Y, Y, Y, N))\n val divDecode = List(\n FN_DIV -> List(N, N, Y, Y),\n FN_REM -> List(N, Y, Y, Y),\n FN_DIVU -> List(N, N, N, N),\n FN_REMU -> List(N, Y, N, N))\n val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(io.req.bits.fn, List(X, X, X, X),\n (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)\n\n require(w == 32 || w == 64)\n def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32\n\n def sext(x: Bits, halfW: Bool, signed: Bool) = {\n val sign = signed && Mux(halfW, x(w/2-1), x(w-1))\n val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))\n (Cat(hi, x(w/2-1,0)), sign)\n }\n val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)\n val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)\n \n val subtractor = remainder(2*w,w) - divisor\n val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))\n val negated_remainder = -result\n\n if (cfg.divUnroll != 0) when (state === s_neg_inputs) {\n when (remainder(w-1)) {\n remainder := negated_remainder\n }\n when (divisor(w-1)) {\n divisor := subtractor\n }\n state := s_div\n }\n if (cfg.divUnroll != 0) when (state === s_neg_output) {\n remainder := negated_remainder\n state := s_done_div\n resHi := false.B\n }\n if (cfg.mulUnroll != 0) when (state === s_mul) {\n val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))\n val mplierSign = remainder(w)\n val mplier = mulReg(mulw-1,0)\n val accum = mulReg(2*mulw,mulw).asSInt\n val mpcand = divisor.asSInt\n val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum\n val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))\n val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out\n\n val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)\n val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&\n !isHi && (mplier & ~eOutMask) === 0.U\n val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))\n val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))\n remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))\n\n count := count + 1.U\n when (eOut || count === (mulw/cfg.mulUnroll-1).U) {\n state := s_done_mul\n resHi := isHi\n }\n }\n if (cfg.divUnroll != 0) when (state === s_div) {\n val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>\n // the special case for iteration 0 is to save HW, not for correctness\n val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)\n val less = difference(w)\n Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)\n }.tail\n\n remainder := unrolls.last\n when (count === (w/cfg.divUnroll).U) {\n state := Mux(neg_out, s_neg_output, s_done_div)\n resHi := isHi\n if (w % cfg.divUnroll < cfg.divUnroll - 1)\n remainder := unrolls(w % cfg.divUnroll)\n }\n count := count + 1.U\n\n val divby0 = count === 0.U && !subtractor(w)\n if (cfg.divEarlyOut) {\n val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)\n val alignMask = ~((align-1).U(log2Ceil(w).W))\n val divisorMSB = Log2(divisor(w-1,0), w) & alignMask\n val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask\n val eOutPos = ~(dividendMSB - divisorMSB)\n val eOut = count === 0.U && !divby0 && eOutPos >= align.U\n when (eOut) {\n remainder := remainder(w-1,0) << eOutPos\n count := eOutPos >> log2Floor(cfg.divUnroll)\n }\n }\n when (divby0 && !isHi) { neg_out := false.B }\n }\n when (io.resp.fire || io.kill) {\n state := s_ready\n }\n when (io.req.fire) {\n state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))\n isHi := cmdHi\n resHi := false.B\n count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)\n neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)\n divisor := Cat(rhs_sign, rhs_in)\n remainder := lhs_in\n req := io.req.bits\n }\n\n val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)\n val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))\n val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))\n io.resp.bits.tag := req.tag\n\n io.resp.bits.data := Cat(hiOut, loOut)\n io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))\n io.resp.valid := (state === s_done_mul || state === s_done_div)\n io.req.ready := state === s_ready\n}\n\nclass PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {\n val io = IO(new Bundle {\n val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))\n val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))\n })\n\n val in = Pipe(io.req)\n\n val decode = List(\n FN_MUL -> List(N, X, X),\n FN_MULH -> List(Y, Y, Y),\n FN_MULHU -> List(Y, N, N),\n FN_MULHSU -> List(Y, Y, N))\n val cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)\n val cmdHalf = (width > 32).B && in.bits.dw === DW_32\n\n val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt\n val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt\n val prod = lhs * rhs\n val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))\n\n val resp = Pipe(in, latency-1)\n io.resp.valid := resp.valid\n io.resp.bits.tag := resp.bits.tag\n io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits\n io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt\n}", + "response": "module PipelinedMultiplier(\n input clock,\n input reset,\n input io_req_valid,\n input [4:0] io_req_bits_fn,\n input io_req_bits_dw,\n input [63:0] io_req_bits_in1,\n input [63:0] io_req_bits_in2,\n output [63:0] io_resp_bits_data\n);\n\n reg in_pipe_v;\n reg [4:0] in_pipe_b_fn;\n reg in_pipe_b_dw;\n reg [63:0] in_pipe_b_in1;\n reg [63:0] in_pipe_b_in2;\n reg io_resp_bits_data_pipe_v;\n reg [63:0] io_resp_bits_data_pipe_b;\n reg [63:0] io_resp_bits_data_pipe_pipe_b;\n wire [1:0] decoded_invInputs = ~(in_pipe_b_fn[1:0]);\n wire [127:0] prod = {{64{(|{decoded_invInputs[1], &{decoded_invInputs[0], in_pipe_b_fn[1]}}) & in_pipe_b_in1[63]}}, in_pipe_b_in1} * {{64{decoded_invInputs[1] & in_pipe_b_in2[63]}}, in_pipe_b_in2};\n always @(posedge clock) begin\n if (reset) begin\n in_pipe_v <= 1'h0;\n io_resp_bits_data_pipe_v <= 1'h0;\n end\n else begin\n in_pipe_v <= io_req_valid;\n io_resp_bits_data_pipe_v <= in_pipe_v;\n end\n if (io_req_valid) begin\n in_pipe_b_fn <= io_req_bits_fn;\n in_pipe_b_dw <= io_req_bits_dw;\n in_pipe_b_in1 <= io_req_bits_in1;\n in_pipe_b_in2 <= io_req_bits_in2;\n end\n if (in_pipe_v)\n io_resp_bits_data_pipe_b <= (|{in_pipe_b_fn[0], in_pipe_b_fn[1]}) ? prod[127:64] : in_pipe_b_dw ? prod[63:0] : {{32{prod[31]}}, prod[31:0]};\n if (io_resp_bits_data_pipe_v)\n io_resp_bits_data_pipe_pipe_b <= io_resp_bits_data_pipe_b;\n end\n assign io_resp_bits_data = io_resp_bits_data_pipe_pipe_b;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable_5(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [12:0] table_MPORT_data_3;\n wire [12:0] table_MPORT_data_2;\n wire [12:0] table_MPORT_data_1;\n wire [12:0] table_MPORT_data_0;\n wire [51:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [6:0] reset_idx;\n wire [6:0] _idx_history_T_7 = io_f1_req_ghist[6:0] ^ io_f1_req_ghist[13:7] ^ io_f1_req_ghist[20:14] ^ io_f1_req_ghist[27:21] ^ io_f1_req_ghist[34:28] ^ io_f1_req_ghist[41:35] ^ io_f1_req_ghist[48:42] ^ io_f1_req_ghist[55:49] ^ io_f1_req_ghist[62:56];\n wire [6:0] s1_hashed_idx = io_f1_req_pc[9:3] ^ {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ io_f1_req_ghist[63]};\n reg [8:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [18:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);\n wire [6:0] _idx_history_T_15 = io_update_hist[6:0] ^ io_update_hist[13:7] ^ io_update_hist[20:14] ^ io_update_hist[27:21] ^ io_update_hist[34:28] ^ io_update_hist[41:35] ^ io_update_hist[48:42] ^ io_update_hist[55:49] ^ io_update_hist[62:56];\n wire [6:0] update_idx = io_update_pc[9:3] ^ {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ io_update_hist[63]};\n wire [8:0] _tag_history_T_11 = io_update_hist[8:0] ^ io_update_hist[17:9] ^ io_update_hist[26:18] ^ io_update_hist[35:27] ^ io_update_hist[44:36] ^ io_update_hist[53:45] ^ io_update_hist[62:54];\n wire [8:0] update_tag = io_update_pc[18:10] ^ {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ io_update_hist[63]};\n assign table_MPORT_data_0 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_3_ctr};\n wire _GEN = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;\n wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_1 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;\n reg [8:0] wrbypass_tags_0;\n reg [8:0] wrbypass_tags_1;\n reg [6:0] wrbypass_idxs_0;\n reg [6:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire [8:0] _tag_history_T_5 = io_f1_req_ghist[8:0] ^ io_f1_req_ghist[17:9] ^ io_f1_req_ghist[26:18] ^ io_f1_req_ghist[35:27] ^ io_f1_req_ghist[44:36] ^ io_f1_req_ghist[53:45] ^ io_f1_req_ghist[62:54];\n wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 7'h0;\n clear_u_ctr <= 19'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 7'h7F & doing_reset;\n reset_idx <= reset_idx + {6'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;\n if (~_GEN_6 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= io_f1_req_pc[18:10] ^ {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ io_f1_req_ghist[63]};\n io_f3_resp_0_valid_REG <= _table_R0_data[12] & _table_R0_data[11:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[25] & _table_R0_data[24:16] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[15:13];\n io_f3_resp_2_valid_REG <= _table_R0_data[38] & _table_R0_data[37:29] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[28:26];\n io_f3_resp_3_valid_REG <= _table_R0_data[51] & _table_R0_data[50:42] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[41:39];\n if (_GEN_7) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_8) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_7) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_8) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_6) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us_4 hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN ? 4'hF : _GEN_0)\n );\n lo_us_4 lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_1 ? 4'hF : _GEN_0)\n );\n table_4 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable_4(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [12:0] table_MPORT_data_3;\n wire [12:0] table_MPORT_data_2;\n wire [12:0] table_MPORT_data_1;\n wire [12:0] table_MPORT_data_0;\n wire [51:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [6:0] reset_idx;\n wire [6:0] _idx_history_T_2 = io_f1_req_ghist[6:0] ^ io_f1_req_ghist[13:7] ^ io_f1_req_ghist[20:14] ^ io_f1_req_ghist[27:21];\n wire [6:0] s1_hashed_idx = io_f1_req_pc[9:3] ^ {_idx_history_T_2[6:4], _idx_history_T_2[3:0] ^ io_f1_req_ghist[31:28]};\n reg [8:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [18:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);\n wire [6:0] _idx_history_T_5 = io_update_hist[6:0] ^ io_update_hist[13:7] ^ io_update_hist[20:14] ^ io_update_hist[27:21];\n wire [6:0] update_idx = io_update_pc[9:3] ^ {_idx_history_T_5[6:4], _idx_history_T_5[3:0] ^ io_update_hist[31:28]};\n wire [8:0] _tag_history_T_3 = io_update_hist[8:0] ^ io_update_hist[17:9] ^ io_update_hist[26:18];\n wire [8:0] update_tag = io_update_pc[18:10] ^ {_tag_history_T_3[8:5], _tag_history_T_3[4:0] ^ io_update_hist[31:27]};\n assign table_MPORT_data_0 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 13'h0 : {1'h1, update_tag, update_wdata_3_ctr};\n wire _GEN = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;\n wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_1 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;\n reg [8:0] wrbypass_tags_0;\n reg [8:0] wrbypass_tags_1;\n reg [6:0] wrbypass_idxs_0;\n reg [6:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire [8:0] _tag_history_T_1 = io_f1_req_ghist[8:0] ^ io_f1_req_ghist[17:9] ^ io_f1_req_ghist[26:18];\n wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 7'h0;\n clear_u_ctr <= 19'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 7'h7F & doing_reset;\n reset_idx <= reset_idx + {6'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;\n if (~_GEN_6 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= io_f1_req_pc[18:10] ^ {_tag_history_T_1[8:5], _tag_history_T_1[4:0] ^ io_f1_req_ghist[31:27]};\n io_f3_resp_0_valid_REG <= _table_R0_data[12] & _table_R0_data[11:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[25] & _table_R0_data[24:16] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[15:13];\n io_f3_resp_2_valid_REG <= _table_R0_data[38] & _table_R0_data[37:29] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[28:26];\n io_f3_resp_3_valid_REG <= _table_R0_data[51] & _table_R0_data[50:42] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[41:39];\n if (_GEN_7) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_8) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_7) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_8) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_6) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us_3 hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN ? 4'hF : _GEN_0)\n );\n lo_us_3 lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_1 ? 4'hF : _GEN_0)\n );\n table_3 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module tail_40x6(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [5:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [5:0] R1_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:39];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// If regfile bypassing is disabled, then the functional unit must do its own\n// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)\n//\n// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}\n\nimport boom.v3.common._\nimport boom.v3.ifu._\nimport boom.v3.util._\n\n/**t\n * Functional unit constants\n */\nobject FUConstants\n{\n // bit mask, since a given execution pipeline may support multiple functional units\n val FUC_SZ = 10\n val FU_X = BitPat.dontCare(FUC_SZ)\n val FU_ALU = 1.U(FUC_SZ.W)\n val FU_JMP = 2.U(FUC_SZ.W)\n val FU_MEM = 4.U(FUC_SZ.W)\n val FU_MUL = 8.U(FUC_SZ.W)\n val FU_DIV = 16.U(FUC_SZ.W)\n val FU_CSR = 32.U(FUC_SZ.W)\n val FU_FPU = 64.U(FUC_SZ.W)\n val FU_FDV = 128.U(FUC_SZ.W)\n val FU_I2F = 256.U(FUC_SZ.W)\n val FU_F2I = 512.U(FUC_SZ.W)\n\n // FP stores generate data through FP F2I, and generate address through MemAddrCalc\n val FU_F2IMEM = 516.U(FUC_SZ.W)\n}\nimport FUConstants._\n\n/**\n * Class to tell the FUDecoders what units it needs to support\n *\n * @param alu support alu unit?\n * @param bru support br unit?\n * @param mem support mem unit?\n * @param muld support multiple div unit?\n * @param fpu support FP unit?\n * @param csr support csr writing unit?\n * @param fdiv support FP div unit?\n * @param ifpu support int to FP unit?\n */\nclass SupportedFuncUnits(\n val alu: Boolean = false,\n val jmp: Boolean = false,\n val mem: Boolean = false,\n val muld: Boolean = false,\n val fpu: Boolean = false,\n val csr: Boolean = false,\n val fdiv: Boolean = false,\n val ifpu: Boolean = false)\n{\n}\n\n\n/**\n * Bundle for signals sent to the functional unit\n *\n * @param dataWidth width of the data sent to the functional unit\n */\nclass FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val numOperands = 3\n\n val rs1_data = UInt(dataWidth.W)\n val rs2_data = UInt(dataWidth.W)\n val rs3_data = UInt(dataWidth.W) // only used for FMA units\n val pred_data = Bool()\n\n val kill = Bool() // kill everything\n}\n\n/**\n * Bundle for the signals sent out of the function unit\n *\n * @param dataWidth data sent from the functional unit\n */\nclass FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val predicated = Bool() // Was this response from a predicated-off instruction\n val data = UInt(dataWidth.W)\n val fflags = new ValidIO(new FFlagsResp)\n val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU\n val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU\n val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc\n}\n\n/**\n * Branch resolution information given from the branch unit\n */\nclass BrResolutionInfo(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp\n val valid = Bool()\n val mispredict = Bool()\n val taken = Bool() // which direction did the branch go?\n val cfi_type = UInt(CFI_SZ.W)\n\n // Info for recalculating the pc for this branch\n val pc_sel = UInt(2.W)\n\n val jalr_target = UInt(vaddrBitsExtended.W)\n val target_offset = SInt()\n}\n\nclass BrUpdateInfo(implicit p: Parameters) extends BoomBundle\n{\n // On the first cycle we get masks to kill registers\n val b1 = new BrUpdateMasks\n // On the second cycle we get indices to reset pointers\n val b2 = new BrResolutionInfo\n}\n\nclass BrUpdateMasks(implicit p: Parameters) extends BoomBundle\n{\n val resolve_mask = UInt(maxBrCount.W)\n val mispredict_mask = UInt(maxBrCount.W)\n}\n\n\n/**\n * Abstract top level functional unit class that wraps a lower level hand made functional unit\n *\n * @param isPipelined is the functional unit pipelined?\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class FunctionalUnit(\n val isPipelined: Boolean,\n val numStages: Int,\n val numBypassStages: Int,\n val dataWidth: Int,\n val isJmpUnit: Boolean = false,\n val isAluUnit: Boolean = false,\n val isMemAddrCalcUnit: Boolean = false,\n val needsFcsr: Boolean = false)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))\n\n val brupdate = Input(new BrUpdateInfo())\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n\n // only used by the fpu unit\n val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by branch unit\n val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null\n\n // only used by memaddr calc unit\n val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null\n\n })\n\n io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }\n\n io.resp.valid := false.B\n io.resp.bits := DontCare\n\n if (isJmpUnit) {\n io.get_ftq_pc.ftq_idx := DontCare\n }\n}\n\n/**\n * Abstract top level pipelined functional unit\n *\n * Note: this helps track which uops get killed while in intermediate stages,\n * but it is the job of the consumer to check for kills on the same cycle as consumption!!!\n *\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param earliestBypassStage first stage that you can start bypassing from\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class PipelinedFunctionalUnit(\n numStages: Int,\n numBypassStages: Int,\n earliestBypassStage: Int,\n dataWidth: Int,\n isJmpUnit: Boolean = false,\n isAluUnit: Boolean = false,\n isMemAddrCalcUnit: Boolean = false,\n needsFcsr: Boolean = false\n )(implicit p: Parameters) extends FunctionalUnit(\n isPipelined = true,\n numStages = numStages,\n numBypassStages = numBypassStages,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit,\n isAluUnit = isAluUnit,\n isMemAddrCalcUnit = isMemAddrCalcUnit,\n needsFcsr = needsFcsr)\n{\n // Pipelined functional unit is always ready.\n io.req.ready := true.B\n\n if (numStages > 0) {\n val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_uops = Reg(Vec(numStages, new MicroOp()))\n\n // handle incoming request\n r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill\n r_uops(0) := io.req.bits.uop\n r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n\n // handle middle of the pipeline\n for (i <- 1 until numStages) {\n r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill\n r_uops(i) := r_uops(i-1)\n r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))\n\n if (numBypassStages > 0) {\n io.bypass(i-1).bits.uop := r_uops(i-1)\n }\n }\n\n // handle outgoing (branch could still kill it)\n // consumer must also check for pipeline flushes (kills)\n io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := r_uops(numStages-1)\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))\n\n // bypassing (TODO allow bypass vector to have a different size from numStages)\n if (numBypassStages > 0 && earliestBypassStage == 0) {\n io.bypass(0).bits.uop := io.req.bits.uop\n\n for (i <- 1 until numBypassStages) {\n io.bypass(i).bits.uop := r_uops(i-1)\n }\n }\n } else {\n require (numStages == 0)\n // pass req straight through to response\n\n // valid doesn't check kill signals, let consumer deal with it.\n // The LSU already handles it and this hurts critical path.\n io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := io.req.bits.uop\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n }\n}\n\n/**\n * Functional unit that wraps RocketChips ALU\n *\n * @param isBranchUnit is this a branch unit?\n * @param numStages how many pipeline stages does the functional unit have\n * @param dataWidth width of the data being operated on in the functional unit\n */\nclass ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = numStages,\n isAluUnit = true,\n earliestBypassStage = 0,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit)\n with boom.v3.ifu.HasBoomFrontendParameters\n{\n val uop = io.req.bits.uop\n\n // immediate generation\n val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)\n\n // operand 1 select\n var op1_data: UInt = null\n if (isJmpUnit) {\n // Get the uop PC for jumps\n val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)\n val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)\n\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),\n 0.U))\n } else {\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n 0.U)\n }\n\n // operand 2 select\n val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),\n Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),\n Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,\n Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),\n 0.U))))\n\n val alu = Module(new freechips.rocketchip.rocket.ALU())\n\n alu.io.in1 := op1_data.asUInt\n alu.io.in2 := op2_data.asUInt\n alu.io.fn := uop.ctrl.op_fcn\n alu.io.dw := uop.ctrl.fcn_dw\n\n\n // Did I just get killed by the previous cycle's branch,\n // or by a flush pipeline?\n val killed = WireInit(false.B)\n when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {\n killed := true.B\n }\n\n val rs1 = io.req.bits.rs1_data\n val rs2 = io.req.bits.rs2_data\n val br_eq = (rs1 === rs2)\n val br_ltu = (rs1.asUInt < rs2.asUInt)\n val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |\n rs1(xLen-1) & ~rs2(xLen-1)).asBool\n\n val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(\n Seq( BR_N -> PC_PLUS4,\n BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),\n BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),\n BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),\n BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),\n BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),\n BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),\n BR_J -> PC_BRJMP,\n BR_JR -> PC_JALR\n ))\n\n val is_taken = io.req.valid &&\n !killed &&\n (uop.is_br || uop.is_jalr || uop.is_jal) &&\n (pc_sel =/= PC_PLUS4)\n\n // \"mispredict\" means that a branch has been resolved and it must be killed\n val mispredict = WireInit(false.B)\n\n val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb\n val is_jal = io.req.valid && !killed && uop.is_jal\n val is_jalr = io.req.valid && !killed && uop.is_jalr\n\n when (is_br || is_jalr) {\n if (!isJmpUnit) {\n assert (pc_sel =/= PC_JALR)\n }\n when (pc_sel === PC_PLUS4) {\n mispredict := uop.taken\n }\n when (pc_sel === PC_BRJMP) {\n mispredict := !uop.taken\n }\n }\n\n val brinfo = Wire(new BrResolutionInfo)\n\n // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit\n brinfo.valid := is_br || is_jalr\n brinfo.mispredict := mispredict\n brinfo.uop := uop\n brinfo.cfi_type := Mux(is_jalr, CFI_JALR,\n Mux(is_br , CFI_BR, CFI_X))\n brinfo.taken := is_taken\n brinfo.pc_sel := pc_sel\n\n brinfo.jalr_target := DontCare\n\n\n // Branch/Jump Target Calculation\n // For jumps we read the FTQ, and can calculate the target\n // For branches we emit the offset for the core to redirect if necessary\n val target_offset = imm_xprlen(20,0).asSInt\n brinfo.jalr_target := DontCare\n if (isJmpUnit) {\n def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {\n ea\n } else {\n // Efficient means to compress 64-bit VA into vaddrBits+1 bits.\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).\n val a = a0.asSInt >> vaddrBits\n val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))\n Cat(msb, ea(vaddrBits-1,0))\n }\n\n\n val jalr_target_base = io.req.bits.rs1_data.asSInt\n val jalr_target_xlen = Wire(UInt(xLen.W))\n jalr_target_xlen := (jalr_target_base + target_offset).asUInt\n val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt\n\n brinfo.jalr_target := jalr_target\n val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)\n\n when (pc_sel === PC_JALR) {\n mispredict := !io.get_ftq_pc.next_val ||\n (io.get_ftq_pc.next_pc =/= jalr_target) ||\n !io.get_ftq_pc.entry.cfi_idx.valid ||\n (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)\n }\n }\n\n brinfo.target_offset := target_offset\n\n\n io.brinfo := brinfo\n\n\n\n// Response\n// TODO add clock gate on resp bits from functional units\n// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)\n// val reg_data = Reg(outType = Bits(width = xLen))\n// reg_data := alu.io.out\n// io.resp.bits.data := reg_data\n\n val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_data = Reg(Vec(numStages, UInt(xLen.W)))\n val r_pred = Reg(Vec(numStages, Bool()))\n val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,\n Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),\n Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))\n r_val (0) := io.req.valid\n r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data\n for (i <- 1 until numStages) {\n r_val(i) := r_val(i-1)\n r_data(i) := r_data(i-1)\n r_pred(i) := r_pred(i-1)\n }\n io.resp.bits.data := r_data(numStages-1)\n io.resp.bits.predicated := r_pred(numStages-1)\n // Bypass\n // for the ALU, we can bypass same cycle as compute\n require (numStages >= 1)\n require (numBypassStages >= 1)\n io.bypass(0).valid := io.req.valid\n io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n for (i <- 1 until numStages) {\n io.bypass(i).valid := r_val(i-1)\n io.bypass(i).bits.data := r_data(i-1)\n }\n\n // Exceptions\n io.resp.bits.fflags.valid := false.B\n}\n\n/**\n * Functional unit that passes in base+imm to calculate addresses, and passes store data\n * to the LSU.\n * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form\n */\nclass MemAddrCalcUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = 0,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65, // TODO enable this only if FP is enabled?\n isMemAddrCalcUnit = true)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n with freechips.rocketchip.rocket.constants.ScalarOpConstants\n{\n // perform address calculation\n val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt\n val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,\n sum(63,vaddrBits) =/= 0.U)\n val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt\n\n val store_data = io.req.bits.rs2_data\n\n io.resp.bits.addr := effective_address\n io.resp.bits.data := store_data\n\n if (dataWidth > 63) {\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&\n io.resp.bits.data(64).asBool === true.B), \"65th bit set in MemAddrCalcUnit.\")\n\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),\n \"FP store-data should now be going through a different unit.\")\n }\n\n assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=\n uopLD && io.req.bits.uop.uopc =/= uopSTA),\n \"[maddrcalc] assert we never get store data in here.\")\n\n // Handle misaligned exceptions\n val size = io.req.bits.uop.mem_size\n val misaligned =\n (size === 1.U && (effective_address(0) =/= 0.U)) ||\n (size === 2.U && (effective_address(1,0) =/= 0.U)) ||\n (size === 3.U && (effective_address(2,0) =/= 0.U))\n\n val bkptu = Module(new BreakpointUnit(nBreakpoints))\n bkptu.io.status := io.status\n bkptu.io.bp := io.bp\n bkptu.io.pc := DontCare\n bkptu.io.ea := effective_address\n bkptu.io.mcontext := io.mcontext\n bkptu.io.scontext := io.scontext\n\n val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned\n val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned\n val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))\n val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n val (xcpt_val, xcpt_cause) = checkExceptions(List(\n (ma_ld, (Causes.misaligned_load).U),\n (ma_st, (Causes.misaligned_store).U),\n (dbg_bp, (CSR.debugTriggerCause).U),\n (bp, (Causes.breakpoint).U)))\n\n io.resp.bits.mxcpt.valid := xcpt_val\n io.resp.bits.mxcpt.bits := xcpt_cause\n assert (!(ma_ld && ma_st), \"Mutually-exclusive exceptions are firing.\")\n\n io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE\n io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)\n io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)\n io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data\n io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data\n}\n\n\n/**\n * Functional unit to wrap lower level FPU\n *\n * Currently, bypassing is unsupported!\n * All FP instructions are padded out to the max latency unit for easy\n * write-port scheduling.\n */\nclass FPUUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n{\n val fpu = Module(new FPU())\n fpu.io.req.valid := io.req.valid\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.fcsr_rm := io.fcsr_rm\n\n io.resp.bits.data := fpu.io.resp.bits.data\n io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now\n}\n\n/**\n * Int to FP conversion functional unit\n *\n * @param latency the amount of stages to delay by\n */\nclass IntToFPUnit(latency: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = latency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n with tile.HasFPUParameters\n{\n val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder\n val io_req = io.req.bits\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, None)\n req.in2 := unbox(io_req.rs2_data, tag, None)\n req.in3 := DontCare\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := DontCare // FIXME: this may not be the right thing to do here\n req.fmaCmd := DontCare\n\n assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n \"[func] IntToFP integer input has 65th high-order bit set!\")\n\n assert (!(io.req.valid && !fp_ctrl.fromint),\n \"[func] Only support fromInt micro-ops.\")\n\n val ifpu = Module(new tile.IntToFP(intToFpLatency))\n ifpu.io.in.valid := io.req.valid\n ifpu.io.in.bits := req\n ifpu.io.in.bits.in1 := io_req.rs1_data\n val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits\n\n//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)\n io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)\n io.resp.bits.fflags.valid := ifpu.io.out.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc\n}\n\n/**\n * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time\n * assumes at least one register between request and response\n *\n * TODO allow up to N micro-ops simultaneously.\n *\n * @param dataWidth width of the data to be passed into the functional unit\n */\nabstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)\n extends FunctionalUnit(\n isPipelined = false,\n numStages = 1,\n numBypassStages = 0,\n dataWidth = dataWidth)\n{\n val r_uop = Reg(new MicroOp())\n\n val do_kill = Wire(Bool())\n do_kill := io.req.bits.kill // irrelevant default\n\n when (io.req.fire) {\n // update incoming uop\n do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill\n r_uop := io.req.bits.uop\n r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n } .otherwise {\n do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill\n r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)\n }\n\n // assumes at least one pipeline register between request and response\n io.resp.bits.uop := r_uop\n}\n\n/**\n * Divide functional unit.\n *\n * @param dataWidth data to be passed into the functional unit\n */\nclass DivUnit(dataWidth: Int)(implicit p: Parameters)\n extends IterativeFunctionalUnit(dataWidth)\n{\n\n // We don't use the iterative multiply functionality here.\n // Instead we use the PipelinedMultiplier\n val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))\n\n // request\n div.io.req.valid := io.req.valid && !this.do_kill\n div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n div.io.req.bits.in1 := io.req.bits.rs1_data\n div.io.req.bits.in2 := io.req.bits.rs2_data\n div.io.req.bits.tag := DontCare\n io.req.ready := div.io.req.ready\n\n // handle pipeline kills and branch misspeculations\n div.io.kill := this.do_kill\n\n // response\n io.resp.valid := div.io.resp.valid && !this.do_kill\n div.io.resp.ready := io.resp.ready\n io.resp.bits.data := div.io.resp.bits.data\n}\n\n/**\n * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier\n *\n * @param numStages number of pipeline stages\n * @param dataWidth size of the data being passed into the functional unit\n */\nclass PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = dataWidth)\n{\n val imul = Module(new PipelinedMultiplier(xLen, numStages))\n // request\n imul.io.req.valid := io.req.valid\n imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n imul.io.req.bits.in1 := io.req.bits.rs1_data\n imul.io.req.bits.in2 := io.req.bits.rs2_data\n imul.io.req.bits.tag := DontCare\n // response\n io.resp.bits.data := imul.io.resp.bits.data\n}", + "response": "module DivUnit(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [7:0] io_req_bits_uop_br_mask,\n input [4:0] io_req_bits_uop_rob_idx,\n input [5:0] io_req_bits_uop_pdst,\n input io_req_bits_uop_bypassable,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_stq,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [63:0] io_req_bits_rs1_data,\n input [63:0] io_req_bits_rs2_data,\n input io_req_bits_kill,\n input io_resp_ready,\n output io_resp_valid,\n output [4:0] io_resp_bits_uop_rob_idx,\n output [5:0] io_resp_bits_uop_pdst,\n output io_resp_bits_uop_bypassable,\n output io_resp_bits_uop_is_amo,\n output io_resp_bits_uop_uses_stq,\n output [1:0] io_resp_bits_uop_dst_rtype,\n output [63:0] io_resp_bits_data,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask\n);\n\n wire _div_io_req_ready;\n wire _div_io_resp_valid;\n reg [7:0] r_uop_br_mask;\n reg [4:0] r_uop_rob_idx;\n reg [5:0] r_uop_pdst;\n reg r_uop_bypassable;\n reg r_uop_is_amo;\n reg r_uop_uses_stq;\n reg [1:0] r_uop_dst_rtype;\n wire _GEN = _div_io_req_ready & io_req_valid;\n wire do_kill = _GEN ? (|(io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask)) | io_req_bits_kill : (|(io_brupdate_b1_mispredict_mask & r_uop_br_mask)) | io_req_bits_kill;\n always @(posedge clock) begin\n r_uop_br_mask <= _GEN ? io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : r_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n if (_GEN) begin\n r_uop_rob_idx <= io_req_bits_uop_rob_idx;\n r_uop_pdst <= io_req_bits_uop_pdst;\n r_uop_bypassable <= io_req_bits_uop_bypassable;\n r_uop_is_amo <= io_req_bits_uop_is_amo;\n r_uop_uses_stq <= io_req_bits_uop_uses_stq;\n r_uop_dst_rtype <= io_req_bits_uop_dst_rtype;\n end\n end\n MulDiv div (\n .clock (clock),\n .reset (reset),\n .io_req_ready (_div_io_req_ready),\n .io_req_valid (io_req_valid & ~do_kill),\n .io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_in1 (io_req_bits_rs1_data),\n .io_req_bits_in2 (io_req_bits_rs2_data),\n .io_kill (do_kill),\n .io_resp_ready (io_resp_ready),\n .io_resp_valid (_div_io_resp_valid),\n .io_resp_bits_data (io_resp_bits_data)\n );\n assign io_req_ready = _div_io_req_ready;\n assign io_resp_valid = _div_io_resp_valid & ~do_kill;\n assign io_resp_bits_uop_rob_idx = r_uop_rob_idx;\n assign io_resp_bits_uop_pdst = r_uop_pdst;\n assign io_resp_bits_uop_bypassable = r_uop_bypassable;\n assign io_resp_bits_uop_is_amo = r_uop_is_amo;\n assign io_resp_bits_uop_uses_stq = r_uop_uses_stq;\n assign io_resp_bits_uop_dst_rtype = r_uop_dst_rtype;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module dataArrayWay_1(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [63:0] RW0_wdata,\n output [63:0] RW0_rdata\n);\n\n dataArrayWay_0_ext dataArrayWay_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// BOOM Instruction Dispatcher\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\n\nclass DispatchIO(implicit p: Parameters) extends BoomBundle\n{\n // incoming microops from rename2\n val ren_uops = Vec(coreWidth, Flipped(DecoupledIO(new MicroOp)))\n\n // outgoing microops to issue queues\n // N issues each accept up to dispatchWidth uops\n // dispatchWidth may vary between issue queues\n val dis_uops = MixedVec(issueParams.map(ip=>Vec(ip.dispatchWidth, DecoupledIO(new MicroOp))))\n}\n\nabstract class Dispatcher(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new DispatchIO)\n}\n\n/**\n * This Dispatcher assumes worst case, all dispatched uops go to 1 issue queue\n * This is equivalent to BOOMv2 behavior\n */\nclass BasicDispatcher(implicit p: Parameters) extends Dispatcher\n{\n issueParams.map(ip=>require(ip.dispatchWidth == coreWidth))\n\n val ren_readys = io.dis_uops.map(d=>VecInit(d.map(_.ready)).asUInt).reduce(_&_)\n\n for (w <- 0 until coreWidth) {\n io.ren_uops(w).ready := ren_readys(w)\n }\n\n for {i <- 0 until issueParams.size\n w <- 0 until coreWidth} {\n val issueParam = issueParams(i)\n val dis = io.dis_uops(i)\n\n dis(w).valid := io.ren_uops(w).valid && ((io.ren_uops(w).bits.iq_type & issueParam.iqType.U) =/= 0.U)\n dis(w).bits := io.ren_uops(w).bits\n }\n}\n\n/**\n * Tries to dispatch as many uops as it can to issue queues,\n * which may accept fewer than coreWidth per cycle.\n * When dispatchWidth == coreWidth, its behavior differs\n * from the BasicDispatcher in that it will only stall dispatch when\n * an issue queue required by a uop is full.\n */\nclass CompactingDispatcher(implicit p: Parameters) extends Dispatcher\n{\n issueParams.map(ip => require(ip.dispatchWidth >= ip.issueWidth))\n\n val ren_readys = Wire(Vec(issueParams.size, Vec(coreWidth, Bool())))\n\n for (((ip, dis), rdy) <- issueParams zip io.dis_uops zip ren_readys) {\n val ren = Wire(Vec(coreWidth, Decoupled(new MicroOp)))\n ren <> io.ren_uops\n\n val uses_iq = ren map (u => (u.bits.iq_type & ip.iqType.U).orR)\n\n // Only request an issue slot if the uop needs to enter that queue.\n (ren zip io.ren_uops zip uses_iq) foreach {case ((u,v),q) =>\n u.valid := v.valid && q}\n\n val compactor = Module(new Compactor(coreWidth, ip.dispatchWidth, new MicroOp))\n compactor.io.in <> ren\n dis <> compactor.io.out\n\n // The queue is considered ready if the uop doesn't use it.\n rdy := ren zip uses_iq map {case (u,q) => u.ready || !q}\n }\n\n (ren_readys.reduce((r,i) =>\n VecInit(r zip i map {case (r,i) =>\n r && i})) zip io.ren_uops) foreach {case (r,u) =>\n u.ready := r}\n}", + "response": "module BasicDispatcher(\n output io_ren_uops_0_ready,\n input io_ren_uops_0_valid,\n input [6:0] io_ren_uops_0_bits_uopc,\n input [31:0] io_ren_uops_0_bits_inst,\n input [31:0] io_ren_uops_0_bits_debug_inst,\n input io_ren_uops_0_bits_is_rvc,\n input [39:0] io_ren_uops_0_bits_debug_pc,\n input [2:0] io_ren_uops_0_bits_iq_type,\n input [9:0] io_ren_uops_0_bits_fu_code,\n input io_ren_uops_0_bits_is_br,\n input io_ren_uops_0_bits_is_jalr,\n input io_ren_uops_0_bits_is_jal,\n input io_ren_uops_0_bits_is_sfb,\n input [7:0] io_ren_uops_0_bits_br_mask,\n input [2:0] io_ren_uops_0_bits_br_tag,\n input [3:0] io_ren_uops_0_bits_ftq_idx,\n input io_ren_uops_0_bits_edge_inst,\n input [5:0] io_ren_uops_0_bits_pc_lob,\n input io_ren_uops_0_bits_taken,\n input [19:0] io_ren_uops_0_bits_imm_packed,\n input [11:0] io_ren_uops_0_bits_csr_addr,\n input [4:0] io_ren_uops_0_bits_rob_idx,\n input [2:0] io_ren_uops_0_bits_ldq_idx,\n input [2:0] io_ren_uops_0_bits_stq_idx,\n input [1:0] io_ren_uops_0_bits_rxq_idx,\n input [5:0] io_ren_uops_0_bits_pdst,\n input [5:0] io_ren_uops_0_bits_prs1,\n input [5:0] io_ren_uops_0_bits_prs2,\n input [5:0] io_ren_uops_0_bits_prs3,\n input io_ren_uops_0_bits_prs1_busy,\n input io_ren_uops_0_bits_prs2_busy,\n input io_ren_uops_0_bits_prs3_busy,\n input [5:0] io_ren_uops_0_bits_stale_pdst,\n input io_ren_uops_0_bits_exception,\n input [63:0] io_ren_uops_0_bits_exc_cause,\n input io_ren_uops_0_bits_bypassable,\n input [4:0] io_ren_uops_0_bits_mem_cmd,\n input [1:0] io_ren_uops_0_bits_mem_size,\n input io_ren_uops_0_bits_mem_signed,\n input io_ren_uops_0_bits_is_fence,\n input io_ren_uops_0_bits_is_fencei,\n input io_ren_uops_0_bits_is_amo,\n input io_ren_uops_0_bits_uses_ldq,\n input io_ren_uops_0_bits_uses_stq,\n input io_ren_uops_0_bits_is_sys_pc2epc,\n input io_ren_uops_0_bits_is_unique,\n input io_ren_uops_0_bits_flush_on_commit,\n input io_ren_uops_0_bits_ldst_is_rs1,\n input [5:0] io_ren_uops_0_bits_ldst,\n input [5:0] io_ren_uops_0_bits_lrs1,\n input [5:0] io_ren_uops_0_bits_lrs2,\n input [5:0] io_ren_uops_0_bits_lrs3,\n input io_ren_uops_0_bits_ldst_val,\n input [1:0] io_ren_uops_0_bits_dst_rtype,\n input [1:0] io_ren_uops_0_bits_lrs1_rtype,\n input [1:0] io_ren_uops_0_bits_lrs2_rtype,\n input io_ren_uops_0_bits_frs3_en,\n input io_ren_uops_0_bits_fp_val,\n input io_ren_uops_0_bits_fp_single,\n input io_ren_uops_0_bits_xcpt_pf_if,\n input io_ren_uops_0_bits_xcpt_ae_if,\n input io_ren_uops_0_bits_xcpt_ma_if,\n input io_ren_uops_0_bits_bp_debug_if,\n input io_ren_uops_0_bits_bp_xcpt_if,\n input [1:0] io_ren_uops_0_bits_debug_fsrc,\n input [1:0] io_ren_uops_0_bits_debug_tsrc,\n input io_dis_uops_2_0_ready,\n output io_dis_uops_2_0_valid,\n output [6:0] io_dis_uops_2_0_bits_uopc,\n output [31:0] io_dis_uops_2_0_bits_inst,\n output [31:0] io_dis_uops_2_0_bits_debug_inst,\n output io_dis_uops_2_0_bits_is_rvc,\n output [39:0] io_dis_uops_2_0_bits_debug_pc,\n output [2:0] io_dis_uops_2_0_bits_iq_type,\n output [9:0] io_dis_uops_2_0_bits_fu_code,\n output io_dis_uops_2_0_bits_is_br,\n output io_dis_uops_2_0_bits_is_jalr,\n output io_dis_uops_2_0_bits_is_jal,\n output io_dis_uops_2_0_bits_is_sfb,\n output [7:0] io_dis_uops_2_0_bits_br_mask,\n output [2:0] io_dis_uops_2_0_bits_br_tag,\n output [3:0] io_dis_uops_2_0_bits_ftq_idx,\n output io_dis_uops_2_0_bits_edge_inst,\n output [5:0] io_dis_uops_2_0_bits_pc_lob,\n output io_dis_uops_2_0_bits_taken,\n output [19:0] io_dis_uops_2_0_bits_imm_packed,\n output [11:0] io_dis_uops_2_0_bits_csr_addr,\n output [4:0] io_dis_uops_2_0_bits_rob_idx,\n output [2:0] io_dis_uops_2_0_bits_ldq_idx,\n output [2:0] io_dis_uops_2_0_bits_stq_idx,\n output [1:0] io_dis_uops_2_0_bits_rxq_idx,\n output [5:0] io_dis_uops_2_0_bits_pdst,\n output [5:0] io_dis_uops_2_0_bits_prs1,\n output [5:0] io_dis_uops_2_0_bits_prs2,\n output [5:0] io_dis_uops_2_0_bits_prs3,\n output io_dis_uops_2_0_bits_prs1_busy,\n output io_dis_uops_2_0_bits_prs2_busy,\n output io_dis_uops_2_0_bits_prs3_busy,\n output [5:0] io_dis_uops_2_0_bits_stale_pdst,\n output io_dis_uops_2_0_bits_exception,\n output [63:0] io_dis_uops_2_0_bits_exc_cause,\n output io_dis_uops_2_0_bits_bypassable,\n output [4:0] io_dis_uops_2_0_bits_mem_cmd,\n output [1:0] io_dis_uops_2_0_bits_mem_size,\n output io_dis_uops_2_0_bits_mem_signed,\n output io_dis_uops_2_0_bits_is_fence,\n output io_dis_uops_2_0_bits_is_fencei,\n output io_dis_uops_2_0_bits_is_amo,\n output io_dis_uops_2_0_bits_uses_ldq,\n output io_dis_uops_2_0_bits_uses_stq,\n output io_dis_uops_2_0_bits_is_sys_pc2epc,\n output io_dis_uops_2_0_bits_is_unique,\n output io_dis_uops_2_0_bits_flush_on_commit,\n output io_dis_uops_2_0_bits_ldst_is_rs1,\n output [5:0] io_dis_uops_2_0_bits_ldst,\n output [5:0] io_dis_uops_2_0_bits_lrs1,\n output [5:0] io_dis_uops_2_0_bits_lrs2,\n output [5:0] io_dis_uops_2_0_bits_lrs3,\n output io_dis_uops_2_0_bits_ldst_val,\n output [1:0] io_dis_uops_2_0_bits_dst_rtype,\n output [1:0] io_dis_uops_2_0_bits_lrs1_rtype,\n output [1:0] io_dis_uops_2_0_bits_lrs2_rtype,\n output io_dis_uops_2_0_bits_frs3_en,\n output io_dis_uops_2_0_bits_fp_val,\n output io_dis_uops_2_0_bits_fp_single,\n output io_dis_uops_2_0_bits_xcpt_pf_if,\n output io_dis_uops_2_0_bits_xcpt_ae_if,\n output io_dis_uops_2_0_bits_xcpt_ma_if,\n output io_dis_uops_2_0_bits_bp_debug_if,\n output io_dis_uops_2_0_bits_bp_xcpt_if,\n output [1:0] io_dis_uops_2_0_bits_debug_fsrc,\n output [1:0] io_dis_uops_2_0_bits_debug_tsrc,\n input io_dis_uops_1_0_ready,\n output io_dis_uops_1_0_valid,\n output [6:0] io_dis_uops_1_0_bits_uopc,\n output [31:0] io_dis_uops_1_0_bits_inst,\n output [31:0] io_dis_uops_1_0_bits_debug_inst,\n output io_dis_uops_1_0_bits_is_rvc,\n output [39:0] io_dis_uops_1_0_bits_debug_pc,\n output [2:0] io_dis_uops_1_0_bits_iq_type,\n output [9:0] io_dis_uops_1_0_bits_fu_code,\n output io_dis_uops_1_0_bits_is_br,\n output io_dis_uops_1_0_bits_is_jalr,\n output io_dis_uops_1_0_bits_is_jal,\n output io_dis_uops_1_0_bits_is_sfb,\n output [7:0] io_dis_uops_1_0_bits_br_mask,\n output [2:0] io_dis_uops_1_0_bits_br_tag,\n output [3:0] io_dis_uops_1_0_bits_ftq_idx,\n output io_dis_uops_1_0_bits_edge_inst,\n output [5:0] io_dis_uops_1_0_bits_pc_lob,\n output io_dis_uops_1_0_bits_taken,\n output [19:0] io_dis_uops_1_0_bits_imm_packed,\n output [11:0] io_dis_uops_1_0_bits_csr_addr,\n output [4:0] io_dis_uops_1_0_bits_rob_idx,\n output [2:0] io_dis_uops_1_0_bits_ldq_idx,\n output [2:0] io_dis_uops_1_0_bits_stq_idx,\n output [1:0] io_dis_uops_1_0_bits_rxq_idx,\n output [5:0] io_dis_uops_1_0_bits_pdst,\n output [5:0] io_dis_uops_1_0_bits_prs1,\n output [5:0] io_dis_uops_1_0_bits_prs2,\n output [5:0] io_dis_uops_1_0_bits_prs3,\n output io_dis_uops_1_0_bits_prs1_busy,\n output io_dis_uops_1_0_bits_prs2_busy,\n output [5:0] io_dis_uops_1_0_bits_stale_pdst,\n output io_dis_uops_1_0_bits_exception,\n output [63:0] io_dis_uops_1_0_bits_exc_cause,\n output io_dis_uops_1_0_bits_bypassable,\n output [4:0] io_dis_uops_1_0_bits_mem_cmd,\n output [1:0] io_dis_uops_1_0_bits_mem_size,\n output io_dis_uops_1_0_bits_mem_signed,\n output io_dis_uops_1_0_bits_is_fence,\n output io_dis_uops_1_0_bits_is_fencei,\n output io_dis_uops_1_0_bits_is_amo,\n output io_dis_uops_1_0_bits_uses_ldq,\n output io_dis_uops_1_0_bits_uses_stq,\n output io_dis_uops_1_0_bits_is_sys_pc2epc,\n output io_dis_uops_1_0_bits_is_unique,\n output io_dis_uops_1_0_bits_flush_on_commit,\n output io_dis_uops_1_0_bits_ldst_is_rs1,\n output [5:0] io_dis_uops_1_0_bits_ldst,\n output [5:0] io_dis_uops_1_0_bits_lrs1,\n output [5:0] io_dis_uops_1_0_bits_lrs2,\n output [5:0] io_dis_uops_1_0_bits_lrs3,\n output io_dis_uops_1_0_bits_ldst_val,\n output [1:0] io_dis_uops_1_0_bits_dst_rtype,\n output [1:0] io_dis_uops_1_0_bits_lrs1_rtype,\n output [1:0] io_dis_uops_1_0_bits_lrs2_rtype,\n output io_dis_uops_1_0_bits_frs3_en,\n output io_dis_uops_1_0_bits_fp_val,\n output io_dis_uops_1_0_bits_fp_single,\n output io_dis_uops_1_0_bits_xcpt_pf_if,\n output io_dis_uops_1_0_bits_xcpt_ae_if,\n output io_dis_uops_1_0_bits_xcpt_ma_if,\n output io_dis_uops_1_0_bits_bp_debug_if,\n output io_dis_uops_1_0_bits_bp_xcpt_if,\n output [1:0] io_dis_uops_1_0_bits_debug_fsrc,\n output [1:0] io_dis_uops_1_0_bits_debug_tsrc,\n input io_dis_uops_0_0_ready,\n output io_dis_uops_0_0_valid,\n output [6:0] io_dis_uops_0_0_bits_uopc,\n output [31:0] io_dis_uops_0_0_bits_inst,\n output [31:0] io_dis_uops_0_0_bits_debug_inst,\n output io_dis_uops_0_0_bits_is_rvc,\n output [39:0] io_dis_uops_0_0_bits_debug_pc,\n output [2:0] io_dis_uops_0_0_bits_iq_type,\n output [9:0] io_dis_uops_0_0_bits_fu_code,\n output io_dis_uops_0_0_bits_is_br,\n output io_dis_uops_0_0_bits_is_jalr,\n output io_dis_uops_0_0_bits_is_jal,\n output io_dis_uops_0_0_bits_is_sfb,\n output [7:0] io_dis_uops_0_0_bits_br_mask,\n output [2:0] io_dis_uops_0_0_bits_br_tag,\n output [3:0] io_dis_uops_0_0_bits_ftq_idx,\n output io_dis_uops_0_0_bits_edge_inst,\n output [5:0] io_dis_uops_0_0_bits_pc_lob,\n output io_dis_uops_0_0_bits_taken,\n output [19:0] io_dis_uops_0_0_bits_imm_packed,\n output [11:0] io_dis_uops_0_0_bits_csr_addr,\n output [4:0] io_dis_uops_0_0_bits_rob_idx,\n output [2:0] io_dis_uops_0_0_bits_ldq_idx,\n output [2:0] io_dis_uops_0_0_bits_stq_idx,\n output [1:0] io_dis_uops_0_0_bits_rxq_idx,\n output [5:0] io_dis_uops_0_0_bits_pdst,\n output [5:0] io_dis_uops_0_0_bits_prs1,\n output [5:0] io_dis_uops_0_0_bits_prs2,\n output [5:0] io_dis_uops_0_0_bits_prs3,\n output io_dis_uops_0_0_bits_prs1_busy,\n output io_dis_uops_0_0_bits_prs2_busy,\n output [5:0] io_dis_uops_0_0_bits_stale_pdst,\n output io_dis_uops_0_0_bits_exception,\n output [63:0] io_dis_uops_0_0_bits_exc_cause,\n output io_dis_uops_0_0_bits_bypassable,\n output [4:0] io_dis_uops_0_0_bits_mem_cmd,\n output [1:0] io_dis_uops_0_0_bits_mem_size,\n output io_dis_uops_0_0_bits_mem_signed,\n output io_dis_uops_0_0_bits_is_fence,\n output io_dis_uops_0_0_bits_is_fencei,\n output io_dis_uops_0_0_bits_is_amo,\n output io_dis_uops_0_0_bits_uses_ldq,\n output io_dis_uops_0_0_bits_uses_stq,\n output io_dis_uops_0_0_bits_is_sys_pc2epc,\n output io_dis_uops_0_0_bits_is_unique,\n output io_dis_uops_0_0_bits_flush_on_commit,\n output io_dis_uops_0_0_bits_ldst_is_rs1,\n output [5:0] io_dis_uops_0_0_bits_ldst,\n output [5:0] io_dis_uops_0_0_bits_lrs1,\n output [5:0] io_dis_uops_0_0_bits_lrs2,\n output [5:0] io_dis_uops_0_0_bits_lrs3,\n output io_dis_uops_0_0_bits_ldst_val,\n output [1:0] io_dis_uops_0_0_bits_dst_rtype,\n output [1:0] io_dis_uops_0_0_bits_lrs1_rtype,\n output [1:0] io_dis_uops_0_0_bits_lrs2_rtype,\n output io_dis_uops_0_0_bits_frs3_en,\n output io_dis_uops_0_0_bits_fp_val,\n output io_dis_uops_0_0_bits_fp_single,\n output io_dis_uops_0_0_bits_xcpt_pf_if,\n output io_dis_uops_0_0_bits_xcpt_ae_if,\n output io_dis_uops_0_0_bits_xcpt_ma_if,\n output io_dis_uops_0_0_bits_bp_debug_if,\n output io_dis_uops_0_0_bits_bp_xcpt_if,\n output [1:0] io_dis_uops_0_0_bits_debug_fsrc,\n output [1:0] io_dis_uops_0_0_bits_debug_tsrc\n);\n\n assign io_ren_uops_0_ready = io_dis_uops_0_0_ready & io_dis_uops_1_0_ready & io_dis_uops_2_0_ready;\n assign io_dis_uops_2_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[2];\n assign io_dis_uops_2_0_bits_uopc = io_ren_uops_0_bits_uopc;\n assign io_dis_uops_2_0_bits_inst = io_ren_uops_0_bits_inst;\n assign io_dis_uops_2_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;\n assign io_dis_uops_2_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;\n assign io_dis_uops_2_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;\n assign io_dis_uops_2_0_bits_iq_type = io_ren_uops_0_bits_iq_type;\n assign io_dis_uops_2_0_bits_fu_code = io_ren_uops_0_bits_fu_code;\n assign io_dis_uops_2_0_bits_is_br = io_ren_uops_0_bits_is_br;\n assign io_dis_uops_2_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;\n assign io_dis_uops_2_0_bits_is_jal = io_ren_uops_0_bits_is_jal;\n assign io_dis_uops_2_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;\n assign io_dis_uops_2_0_bits_br_mask = io_ren_uops_0_bits_br_mask;\n assign io_dis_uops_2_0_bits_br_tag = io_ren_uops_0_bits_br_tag;\n assign io_dis_uops_2_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;\n assign io_dis_uops_2_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;\n assign io_dis_uops_2_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;\n assign io_dis_uops_2_0_bits_taken = io_ren_uops_0_bits_taken;\n assign io_dis_uops_2_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;\n assign io_dis_uops_2_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;\n assign io_dis_uops_2_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;\n assign io_dis_uops_2_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;\n assign io_dis_uops_2_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;\n assign io_dis_uops_2_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;\n assign io_dis_uops_2_0_bits_pdst = io_ren_uops_0_bits_pdst;\n assign io_dis_uops_2_0_bits_prs1 = io_ren_uops_0_bits_prs1;\n assign io_dis_uops_2_0_bits_prs2 = io_ren_uops_0_bits_prs2;\n assign io_dis_uops_2_0_bits_prs3 = io_ren_uops_0_bits_prs3;\n assign io_dis_uops_2_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;\n assign io_dis_uops_2_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;\n assign io_dis_uops_2_0_bits_prs3_busy = io_ren_uops_0_bits_prs3_busy;\n assign io_dis_uops_2_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;\n assign io_dis_uops_2_0_bits_exception = io_ren_uops_0_bits_exception;\n assign io_dis_uops_2_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;\n assign io_dis_uops_2_0_bits_bypassable = io_ren_uops_0_bits_bypassable;\n assign io_dis_uops_2_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;\n assign io_dis_uops_2_0_bits_mem_size = io_ren_uops_0_bits_mem_size;\n assign io_dis_uops_2_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;\n assign io_dis_uops_2_0_bits_is_fence = io_ren_uops_0_bits_is_fence;\n assign io_dis_uops_2_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;\n assign io_dis_uops_2_0_bits_is_amo = io_ren_uops_0_bits_is_amo;\n assign io_dis_uops_2_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;\n assign io_dis_uops_2_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;\n assign io_dis_uops_2_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;\n assign io_dis_uops_2_0_bits_is_unique = io_ren_uops_0_bits_is_unique;\n assign io_dis_uops_2_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;\n assign io_dis_uops_2_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;\n assign io_dis_uops_2_0_bits_ldst = io_ren_uops_0_bits_ldst;\n assign io_dis_uops_2_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;\n assign io_dis_uops_2_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;\n assign io_dis_uops_2_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;\n assign io_dis_uops_2_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;\n assign io_dis_uops_2_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;\n assign io_dis_uops_2_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;\n assign io_dis_uops_2_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;\n assign io_dis_uops_2_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;\n assign io_dis_uops_2_0_bits_fp_val = io_ren_uops_0_bits_fp_val;\n assign io_dis_uops_2_0_bits_fp_single = io_ren_uops_0_bits_fp_single;\n assign io_dis_uops_2_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;\n assign io_dis_uops_2_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;\n assign io_dis_uops_2_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;\n assign io_dis_uops_2_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;\n assign io_dis_uops_2_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;\n assign io_dis_uops_2_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;\n assign io_dis_uops_2_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;\n assign io_dis_uops_1_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[0];\n assign io_dis_uops_1_0_bits_uopc = io_ren_uops_0_bits_uopc;\n assign io_dis_uops_1_0_bits_inst = io_ren_uops_0_bits_inst;\n assign io_dis_uops_1_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;\n assign io_dis_uops_1_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;\n assign io_dis_uops_1_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;\n assign io_dis_uops_1_0_bits_iq_type = io_ren_uops_0_bits_iq_type;\n assign io_dis_uops_1_0_bits_fu_code = io_ren_uops_0_bits_fu_code;\n assign io_dis_uops_1_0_bits_is_br = io_ren_uops_0_bits_is_br;\n assign io_dis_uops_1_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;\n assign io_dis_uops_1_0_bits_is_jal = io_ren_uops_0_bits_is_jal;\n assign io_dis_uops_1_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;\n assign io_dis_uops_1_0_bits_br_mask = io_ren_uops_0_bits_br_mask;\n assign io_dis_uops_1_0_bits_br_tag = io_ren_uops_0_bits_br_tag;\n assign io_dis_uops_1_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;\n assign io_dis_uops_1_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;\n assign io_dis_uops_1_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;\n assign io_dis_uops_1_0_bits_taken = io_ren_uops_0_bits_taken;\n assign io_dis_uops_1_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;\n assign io_dis_uops_1_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;\n assign io_dis_uops_1_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;\n assign io_dis_uops_1_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;\n assign io_dis_uops_1_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;\n assign io_dis_uops_1_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;\n assign io_dis_uops_1_0_bits_pdst = io_ren_uops_0_bits_pdst;\n assign io_dis_uops_1_0_bits_prs1 = io_ren_uops_0_bits_prs1;\n assign io_dis_uops_1_0_bits_prs2 = io_ren_uops_0_bits_prs2;\n assign io_dis_uops_1_0_bits_prs3 = io_ren_uops_0_bits_prs3;\n assign io_dis_uops_1_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;\n assign io_dis_uops_1_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;\n assign io_dis_uops_1_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;\n assign io_dis_uops_1_0_bits_exception = io_ren_uops_0_bits_exception;\n assign io_dis_uops_1_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;\n assign io_dis_uops_1_0_bits_bypassable = io_ren_uops_0_bits_bypassable;\n assign io_dis_uops_1_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;\n assign io_dis_uops_1_0_bits_mem_size = io_ren_uops_0_bits_mem_size;\n assign io_dis_uops_1_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;\n assign io_dis_uops_1_0_bits_is_fence = io_ren_uops_0_bits_is_fence;\n assign io_dis_uops_1_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;\n assign io_dis_uops_1_0_bits_is_amo = io_ren_uops_0_bits_is_amo;\n assign io_dis_uops_1_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;\n assign io_dis_uops_1_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;\n assign io_dis_uops_1_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;\n assign io_dis_uops_1_0_bits_is_unique = io_ren_uops_0_bits_is_unique;\n assign io_dis_uops_1_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;\n assign io_dis_uops_1_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;\n assign io_dis_uops_1_0_bits_ldst = io_ren_uops_0_bits_ldst;\n assign io_dis_uops_1_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;\n assign io_dis_uops_1_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;\n assign io_dis_uops_1_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;\n assign io_dis_uops_1_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;\n assign io_dis_uops_1_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;\n assign io_dis_uops_1_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;\n assign io_dis_uops_1_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;\n assign io_dis_uops_1_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;\n assign io_dis_uops_1_0_bits_fp_val = io_ren_uops_0_bits_fp_val;\n assign io_dis_uops_1_0_bits_fp_single = io_ren_uops_0_bits_fp_single;\n assign io_dis_uops_1_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;\n assign io_dis_uops_1_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;\n assign io_dis_uops_1_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;\n assign io_dis_uops_1_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;\n assign io_dis_uops_1_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;\n assign io_dis_uops_1_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;\n assign io_dis_uops_1_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;\n assign io_dis_uops_0_0_valid = io_ren_uops_0_valid & io_ren_uops_0_bits_iq_type[1];\n assign io_dis_uops_0_0_bits_uopc = io_ren_uops_0_bits_uopc;\n assign io_dis_uops_0_0_bits_inst = io_ren_uops_0_bits_inst;\n assign io_dis_uops_0_0_bits_debug_inst = io_ren_uops_0_bits_debug_inst;\n assign io_dis_uops_0_0_bits_is_rvc = io_ren_uops_0_bits_is_rvc;\n assign io_dis_uops_0_0_bits_debug_pc = io_ren_uops_0_bits_debug_pc;\n assign io_dis_uops_0_0_bits_iq_type = io_ren_uops_0_bits_iq_type;\n assign io_dis_uops_0_0_bits_fu_code = io_ren_uops_0_bits_fu_code;\n assign io_dis_uops_0_0_bits_is_br = io_ren_uops_0_bits_is_br;\n assign io_dis_uops_0_0_bits_is_jalr = io_ren_uops_0_bits_is_jalr;\n assign io_dis_uops_0_0_bits_is_jal = io_ren_uops_0_bits_is_jal;\n assign io_dis_uops_0_0_bits_is_sfb = io_ren_uops_0_bits_is_sfb;\n assign io_dis_uops_0_0_bits_br_mask = io_ren_uops_0_bits_br_mask;\n assign io_dis_uops_0_0_bits_br_tag = io_ren_uops_0_bits_br_tag;\n assign io_dis_uops_0_0_bits_ftq_idx = io_ren_uops_0_bits_ftq_idx;\n assign io_dis_uops_0_0_bits_edge_inst = io_ren_uops_0_bits_edge_inst;\n assign io_dis_uops_0_0_bits_pc_lob = io_ren_uops_0_bits_pc_lob;\n assign io_dis_uops_0_0_bits_taken = io_ren_uops_0_bits_taken;\n assign io_dis_uops_0_0_bits_imm_packed = io_ren_uops_0_bits_imm_packed;\n assign io_dis_uops_0_0_bits_csr_addr = io_ren_uops_0_bits_csr_addr;\n assign io_dis_uops_0_0_bits_rob_idx = io_ren_uops_0_bits_rob_idx;\n assign io_dis_uops_0_0_bits_ldq_idx = io_ren_uops_0_bits_ldq_idx;\n assign io_dis_uops_0_0_bits_stq_idx = io_ren_uops_0_bits_stq_idx;\n assign io_dis_uops_0_0_bits_rxq_idx = io_ren_uops_0_bits_rxq_idx;\n assign io_dis_uops_0_0_bits_pdst = io_ren_uops_0_bits_pdst;\n assign io_dis_uops_0_0_bits_prs1 = io_ren_uops_0_bits_prs1;\n assign io_dis_uops_0_0_bits_prs2 = io_ren_uops_0_bits_prs2;\n assign io_dis_uops_0_0_bits_prs3 = io_ren_uops_0_bits_prs3;\n assign io_dis_uops_0_0_bits_prs1_busy = io_ren_uops_0_bits_prs1_busy;\n assign io_dis_uops_0_0_bits_prs2_busy = io_ren_uops_0_bits_prs2_busy;\n assign io_dis_uops_0_0_bits_stale_pdst = io_ren_uops_0_bits_stale_pdst;\n assign io_dis_uops_0_0_bits_exception = io_ren_uops_0_bits_exception;\n assign io_dis_uops_0_0_bits_exc_cause = io_ren_uops_0_bits_exc_cause;\n assign io_dis_uops_0_0_bits_bypassable = io_ren_uops_0_bits_bypassable;\n assign io_dis_uops_0_0_bits_mem_cmd = io_ren_uops_0_bits_mem_cmd;\n assign io_dis_uops_0_0_bits_mem_size = io_ren_uops_0_bits_mem_size;\n assign io_dis_uops_0_0_bits_mem_signed = io_ren_uops_0_bits_mem_signed;\n assign io_dis_uops_0_0_bits_is_fence = io_ren_uops_0_bits_is_fence;\n assign io_dis_uops_0_0_bits_is_fencei = io_ren_uops_0_bits_is_fencei;\n assign io_dis_uops_0_0_bits_is_amo = io_ren_uops_0_bits_is_amo;\n assign io_dis_uops_0_0_bits_uses_ldq = io_ren_uops_0_bits_uses_ldq;\n assign io_dis_uops_0_0_bits_uses_stq = io_ren_uops_0_bits_uses_stq;\n assign io_dis_uops_0_0_bits_is_sys_pc2epc = io_ren_uops_0_bits_is_sys_pc2epc;\n assign io_dis_uops_0_0_bits_is_unique = io_ren_uops_0_bits_is_unique;\n assign io_dis_uops_0_0_bits_flush_on_commit = io_ren_uops_0_bits_flush_on_commit;\n assign io_dis_uops_0_0_bits_ldst_is_rs1 = io_ren_uops_0_bits_ldst_is_rs1;\n assign io_dis_uops_0_0_bits_ldst = io_ren_uops_0_bits_ldst;\n assign io_dis_uops_0_0_bits_lrs1 = io_ren_uops_0_bits_lrs1;\n assign io_dis_uops_0_0_bits_lrs2 = io_ren_uops_0_bits_lrs2;\n assign io_dis_uops_0_0_bits_lrs3 = io_ren_uops_0_bits_lrs3;\n assign io_dis_uops_0_0_bits_ldst_val = io_ren_uops_0_bits_ldst_val;\n assign io_dis_uops_0_0_bits_dst_rtype = io_ren_uops_0_bits_dst_rtype;\n assign io_dis_uops_0_0_bits_lrs1_rtype = io_ren_uops_0_bits_lrs1_rtype;\n assign io_dis_uops_0_0_bits_lrs2_rtype = io_ren_uops_0_bits_lrs2_rtype;\n assign io_dis_uops_0_0_bits_frs3_en = io_ren_uops_0_bits_frs3_en;\n assign io_dis_uops_0_0_bits_fp_val = io_ren_uops_0_bits_fp_val;\n assign io_dis_uops_0_0_bits_fp_single = io_ren_uops_0_bits_fp_single;\n assign io_dis_uops_0_0_bits_xcpt_pf_if = io_ren_uops_0_bits_xcpt_pf_if;\n assign io_dis_uops_0_0_bits_xcpt_ae_if = io_ren_uops_0_bits_xcpt_ae_if;\n assign io_dis_uops_0_0_bits_xcpt_ma_if = io_ren_uops_0_bits_xcpt_ma_if;\n assign io_dis_uops_0_0_bits_bp_debug_if = io_ren_uops_0_bits_bp_debug_if;\n assign io_dis_uops_0_0_bits_bp_xcpt_if = io_ren_uops_0_bits_bp_xcpt_if;\n assign io_dis_uops_0_0_bits_debug_fsrc = io_ren_uops_0_bits_debug_fsrc;\n assign io_dis_uops_0_0_bits_debug_tsrc = io_ren_uops_0_bits_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw87_f32(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us_4(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n\n\n\n// A branch prediction for a single instruction\nclass BranchPrediction(implicit p: Parameters) extends BoomBundle()(p)\n{\n // If this is a branch, do we take it?\n val taken = Bool()\n\n // Is this a branch?\n val is_br = Bool()\n // Is this a JAL?\n val is_jal = Bool()\n // What is the target of his branch/jump? Do we know the target?\n val predicted_pc = Valid(UInt(vaddrBitsExtended.W))\n\n\n}\n\n// A branch prediction for a entire fetch-width worth of instructions\n// This is typically merged from individual predictions from the banked\n// predictor\nclass BranchPredictionBundle(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n val pc = UInt(vaddrBitsExtended.W)\n val preds = Vec(fetchWidth, new BranchPrediction)\n val meta = Output(Vec(nBanks, UInt(bpdMaxMetaLength.W)))\n val lhist = Output(Vec(nBanks, UInt(localHistoryLength.W)))\n}\n\n\n// A branch update for a fetch-width worth of instructions\nclass BranchPredictionUpdate(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n // Indicates that this update is due to a speculated misprediction\n // Local predictors typically update themselves with speculative info\n // Global predictors only care about non-speculative updates\n val is_mispredict_update = Bool()\n val is_repair_update = Bool()\n val btb_mispredicts = UInt(fetchWidth.W)\n def is_btb_mispredict_update = btb_mispredicts =/= 0.U\n def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)\n\n val pc = UInt(vaddrBitsExtended.W)\n // Mask of instructions which are branches.\n // If these are not cfi_idx, then they were predicted not taken\n val br_mask = UInt(fetchWidth.W)\n // Which CFI was taken/mispredicted (if any)\n val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))\n // Was the cfi taken?\n val cfi_taken = Bool()\n // Was the cfi mispredicted from the original prediction?\n val cfi_mispredicted = Bool()\n // Was the cfi a br?\n val cfi_is_br = Bool()\n // Was the cfi a jal/jalr?\n val cfi_is_jal = Bool()\n // Was the cfi a jalr\n val cfi_is_jalr = Bool()\n //val cfi_is_ret = Bool()\n\n val ghist = new GlobalHistory\n val lhist = Vec(nBanks, UInt(localHistoryLength.W))\n\n\n // What did this CFI jump to?\n val target = UInt(vaddrBitsExtended.W)\n\n val meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))\n}\n\n// A branch update to a single bank\nclass BranchPredictionBankUpdate(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n val is_mispredict_update = Bool()\n val is_repair_update = Bool()\n\n val btb_mispredicts = UInt(bankWidth.W)\n def is_btb_mispredict_update = btb_mispredicts =/= 0.U\n\n def is_commit_update = !(is_mispredict_update || is_repair_update || is_btb_mispredict_update)\n\n val pc = UInt(vaddrBitsExtended.W)\n\n val br_mask = UInt(bankWidth.W)\n val cfi_idx = Valid(UInt(log2Ceil(bankWidth).W))\n val cfi_taken = Bool()\n val cfi_mispredicted = Bool()\n\n val cfi_is_br = Bool()\n val cfi_is_jal = Bool()\n val cfi_is_jalr = Bool()\n\n val ghist = UInt(globalHistoryLength.W)\n val lhist = UInt(localHistoryLength.W)\n\n val target = UInt(vaddrBitsExtended.W)\n\n val meta = UInt(bpdMaxMetaLength.W)\n}\n\nclass BranchPredictionRequest(implicit p: Parameters) extends BoomBundle()(p)\n{\n val pc = UInt(vaddrBitsExtended.W)\n val ghist = new GlobalHistory\n}\n\n\nclass BranchPredictionBankResponse(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n val f1 = Vec(bankWidth, new BranchPrediction)\n val f2 = Vec(bankWidth, new BranchPrediction)\n val f3 = Vec(bankWidth, new BranchPrediction)\n}\n\nabstract class BranchPredictorBank(implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n val metaSz = 0\n def nInputs = 1\n\n val mems: Seq[Tuple3[String, Int, Int]]\n\n val io = IO(new Bundle {\n val f0_valid = Input(Bool())\n val f0_pc = Input(UInt(vaddrBitsExtended.W))\n val f0_mask = Input(UInt(bankWidth.W))\n // Local history not available until end of f1\n val f1_ghist = Input(UInt(globalHistoryLength.W))\n val f1_lhist = Input(UInt(localHistoryLength.W))\n\n val resp_in = Input(Vec(nInputs, new BranchPredictionBankResponse))\n val resp = Output(new BranchPredictionBankResponse)\n\n // Store the meta as a UInt, use width inference to figure out the shape\n val f3_meta = Output(UInt(bpdMaxMetaLength.W))\n\n val f3_fire = Input(Bool())\n\n val update = Input(Valid(new BranchPredictionBankUpdate))\n })\n io.resp := io.resp_in(0)\n\n io.f3_meta := 0.U\n\n val s0_idx = fetchIdx(io.f0_pc)\n val s1_idx = RegNext(s0_idx)\n val s2_idx = RegNext(s1_idx)\n val s3_idx = RegNext(s2_idx)\n\n val s0_valid = io.f0_valid\n val s1_valid = RegNext(s0_valid)\n val s2_valid = RegNext(s1_valid)\n val s3_valid = RegNext(s2_valid)\n\n val s0_mask = io.f0_mask\n val s1_mask = RegNext(s0_mask)\n val s2_mask = RegNext(s1_mask)\n val s3_mask = RegNext(s2_mask)\n\n val s0_pc = io.f0_pc\n val s1_pc = RegNext(s0_pc)\n\n val s0_update = io.update\n val s0_update_idx = fetchIdx(io.update.bits.pc)\n val s0_update_valid = io.update.valid\n\n val s1_update = RegNext(s0_update)\n val s1_update_idx = RegNext(s0_update_idx)\n val s1_update_valid = RegNext(s0_update_valid)\n\n\n\n}\n\n\n\nclass BranchPredictor(implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n val io = IO(new Bundle {\n\n // Requests and responses\n val f0_req = Input(Valid(new BranchPredictionRequest))\n\n val resp = Output(new Bundle {\n val f1 = new BranchPredictionBundle\n val f2 = new BranchPredictionBundle\n val f3 = new BranchPredictionBundle\n })\n\n val f3_fire = Input(Bool())\n\n // Update\n val update = Input(Valid(new BranchPredictionUpdate))\n })\n\n var total_memsize = 0\n val bpdStr = new StringBuilder\n bpdStr.append(BoomCoreStringPrefix(\"==Branch Predictor Memory Sizes==\\n\"))\n val banked_predictors = (0 until nBanks) map ( b => {\n val m = Module(if (useBPD) new ComposedBranchPredictorBank else new NullBranchPredictorBank)\n for ((n, d, w) <- m.mems) {\n bpdStr.append(BoomCoreStringPrefix(f\"bank$b $n: $d x $w = ${d * w / 8}\"))\n total_memsize = total_memsize + d * w / 8\n }\n m\n })\n bpdStr.append(BoomCoreStringPrefix(f\"Total bpd size: ${total_memsize / 1024} KB\\n\"))\n override def toString: String = bpdStr.toString\n\n val banked_lhist_providers = Seq.fill(nBanks) { Module(if (localHistoryNSets > 0) new LocalBranchPredictorBank else new NullLocalBranchPredictorBank) }\n\n\n if (nBanks == 1) {\n banked_lhist_providers(0).io.f0_valid := io.f0_req.valid\n banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n\n banked_predictors(0).io.f0_valid := io.f0_req.valid\n banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)\n\n banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))\n banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist\n\n banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)\n } else {\n require(nBanks == 2)\n\n banked_predictors(0).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)\n banked_predictors(1).io.resp_in(0) := (0.U).asTypeOf(new BranchPredictionBankResponse)\n\n banked_predictors(0).io.f1_lhist := banked_lhist_providers(0).io.f1_lhist\n banked_predictors(1).io.f1_lhist := banked_lhist_providers(1).io.f1_lhist\n\n when (bank(io.f0_req.bits.pc) === 0.U) {\n banked_lhist_providers(0).io.f0_valid := io.f0_req.valid\n banked_lhist_providers(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n\n banked_lhist_providers(1).io.f0_valid := io.f0_req.valid\n banked_lhist_providers(1).io.f0_pc := nextBank(io.f0_req.bits.pc)\n\n banked_predictors(0).io.f0_valid := io.f0_req.valid\n banked_predictors(0).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n banked_predictors(0).io.f0_mask := fetchMask(io.f0_req.bits.pc)\n\n banked_predictors(1).io.f0_valid := io.f0_req.valid\n banked_predictors(1).io.f0_pc := nextBank(io.f0_req.bits.pc)\n banked_predictors(1).io.f0_mask := ~(0.U(bankWidth.W))\n } .otherwise {\n banked_lhist_providers(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)\n banked_lhist_providers(0).io.f0_pc := nextBank(io.f0_req.bits.pc)\n\n banked_lhist_providers(1).io.f0_valid := io.f0_req.valid\n banked_lhist_providers(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n\n banked_predictors(0).io.f0_valid := io.f0_req.valid && !mayNotBeDualBanked(io.f0_req.bits.pc)\n banked_predictors(0).io.f0_pc := nextBank(io.f0_req.bits.pc)\n banked_predictors(0).io.f0_mask := ~(0.U(bankWidth.W))\n\n banked_predictors(1).io.f0_valid := io.f0_req.valid\n banked_predictors(1).io.f0_pc := bankAlign(io.f0_req.bits.pc)\n banked_predictors(1).io.f0_mask := fetchMask(io.f0_req.bits.pc)\n }\n when (RegNext(bank(io.f0_req.bits.pc) === 0.U)) {\n banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))\n banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))\n } .otherwise {\n banked_predictors(0).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(1))\n banked_predictors(1).io.f1_ghist := RegNext(io.f0_req.bits.ghist.histories(0))\n }\n }\n\n\n for (i <- 0 until nBanks) {\n banked_lhist_providers(i).io.f3_taken_br := banked_predictors(i).io.resp.f3.map ( p =>\n p.is_br && p.predicted_pc.valid && p.taken\n ).reduce(_||_)\n }\n\n if (nBanks == 1) {\n io.resp.f1.preds := banked_predictors(0).io.resp.f1\n io.resp.f2.preds := banked_predictors(0).io.resp.f2\n io.resp.f3.preds := banked_predictors(0).io.resp.f3\n io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta\n io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist\n\n banked_predictors(0).io.f3_fire := io.f3_fire\n banked_lhist_providers(0).io.f3_fire := io.f3_fire\n } else {\n require(nBanks == 2)\n val b0_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(0).io.f0_valid)))\n val b1_fire = io.f3_fire && RegNext(RegNext(RegNext(banked_predictors(1).io.f0_valid)))\n banked_predictors(0).io.f3_fire := b0_fire\n banked_predictors(1).io.f3_fire := b1_fire\n\n banked_lhist_providers(0).io.f3_fire := b0_fire\n banked_lhist_providers(1).io.f3_fire := b1_fire\n\n\n\n // The branch prediction metadata is stored un-shuffled\n io.resp.f3.meta(0) := banked_predictors(0).io.f3_meta\n io.resp.f3.meta(1) := banked_predictors(1).io.f3_meta\n\n io.resp.f3.lhist(0) := banked_lhist_providers(0).io.f3_lhist\n io.resp.f3.lhist(1) := banked_lhist_providers(1).io.f3_lhist\n\n when (bank(io.resp.f1.pc) === 0.U) {\n for (i <- 0 until bankWidth) {\n io.resp.f1.preds(i) := banked_predictors(0).io.resp.f1(i)\n io.resp.f1.preds(i+bankWidth) := banked_predictors(1).io.resp.f1(i)\n }\n } .otherwise {\n for (i <- 0 until bankWidth) {\n io.resp.f1.preds(i) := banked_predictors(1).io.resp.f1(i)\n io.resp.f1.preds(i+bankWidth) := banked_predictors(0).io.resp.f1(i)\n }\n }\n\n when (bank(io.resp.f2.pc) === 0.U) {\n for (i <- 0 until bankWidth) {\n io.resp.f2.preds(i) := banked_predictors(0).io.resp.f2(i)\n io.resp.f2.preds(i+bankWidth) := banked_predictors(1).io.resp.f2(i)\n }\n } .otherwise {\n for (i <- 0 until bankWidth) {\n io.resp.f2.preds(i) := banked_predictors(1).io.resp.f2(i)\n io.resp.f2.preds(i+bankWidth) := banked_predictors(0).io.resp.f2(i)\n }\n }\n\n when (bank(io.resp.f3.pc) === 0.U) {\n for (i <- 0 until bankWidth) {\n io.resp.f3.preds(i) := banked_predictors(0).io.resp.f3(i)\n io.resp.f3.preds(i+bankWidth) := banked_predictors(1).io.resp.f3(i)\n }\n } .otherwise {\n for (i <- 0 until bankWidth) {\n io.resp.f3.preds(i) := banked_predictors(1).io.resp.f3(i)\n io.resp.f3.preds(i+bankWidth) := banked_predictors(0).io.resp.f3(i)\n }\n }\n }\n\n io.resp.f1.pc := RegNext(io.f0_req.bits.pc)\n io.resp.f2.pc := RegNext(io.resp.f1.pc)\n io.resp.f3.pc := RegNext(io.resp.f2.pc)\n\n // We don't care about meta from the f1 and f2 resps\n // Use the meta from the latest resp\n io.resp.f1.meta := DontCare\n io.resp.f2.meta := DontCare\n io.resp.f1.lhist := DontCare\n io.resp.f2.lhist := DontCare\n\n\n for (i <- 0 until nBanks) {\n banked_predictors(i).io.update.bits.is_mispredict_update := io.update.bits.is_mispredict_update\n banked_predictors(i).io.update.bits.is_repair_update := io.update.bits.is_repair_update\n\n banked_predictors(i).io.update.bits.meta := io.update.bits.meta(i)\n banked_predictors(i).io.update.bits.lhist := io.update.bits.lhist(i)\n banked_predictors(i).io.update.bits.cfi_idx.bits := io.update.bits.cfi_idx.bits\n banked_predictors(i).io.update.bits.cfi_taken := io.update.bits.cfi_taken\n banked_predictors(i).io.update.bits.cfi_mispredicted := io.update.bits.cfi_mispredicted\n banked_predictors(i).io.update.bits.cfi_is_br := io.update.bits.cfi_is_br\n banked_predictors(i).io.update.bits.cfi_is_jal := io.update.bits.cfi_is_jal\n banked_predictors(i).io.update.bits.cfi_is_jalr := io.update.bits.cfi_is_jalr\n banked_predictors(i).io.update.bits.target := io.update.bits.target\n\n banked_lhist_providers(i).io.update.mispredict := io.update.bits.is_mispredict_update\n banked_lhist_providers(i).io.update.repair := io.update.bits.is_repair_update\n banked_lhist_providers(i).io.update.lhist := io.update.bits.lhist(i)\n }\n\n if (nBanks == 1) {\n banked_predictors(0).io.update.valid := io.update.valid\n banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)\n banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask\n banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts\n banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid\n banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)\n\n banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask =/= 0.U\n banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)\n } else {\n require(nBanks == 2)\n // Split the single update bundle for the fetchpacket into two updates\n // 1 for each bank.\n\n when (bank(io.update.bits.pc) === 0.U) {\n val b1_update_valid = io.update.valid &&\n (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)\n\n banked_lhist_providers(0).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U\n banked_lhist_providers(1).io.update.valid := b1_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U\n\n banked_lhist_providers(0).io.update.pc := bankAlign(io.update.bits.pc)\n banked_lhist_providers(1).io.update.pc := nextBank(io.update.bits.pc)\n\n banked_predictors(0).io.update.valid := io.update.valid\n banked_predictors(1).io.update.valid := b1_update_valid\n\n banked_predictors(0).io.update.bits.pc := bankAlign(io.update.bits.pc)\n banked_predictors(1).io.update.bits.pc := nextBank(io.update.bits.pc)\n\n banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask\n banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth\n\n banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts\n banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth\n\n banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U\n banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U\n\n banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(0)\n banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(1)\n } .otherwise {\n val b0_update_valid = io.update.valid && !mayNotBeDualBanked(io.update.bits.pc) &&\n (!io.update.bits.cfi_idx.valid || io.update.bits.cfi_idx.bits >= bankWidth.U)\n\n banked_lhist_providers(1).io.update.valid := io.update.valid && io.update.bits.br_mask(bankWidth-1,0) =/= 0.U\n banked_lhist_providers(0).io.update.valid := b0_update_valid && io.update.bits.br_mask(fetchWidth-1,bankWidth) =/= 0.U\n\n banked_lhist_providers(1).io.update.pc := bankAlign(io.update.bits.pc)\n banked_lhist_providers(0).io.update.pc := nextBank(io.update.bits.pc)\n\n banked_predictors(1).io.update.valid := io.update.valid\n banked_predictors(0).io.update.valid := b0_update_valid\n\n banked_predictors(1).io.update.bits.pc := bankAlign(io.update.bits.pc)\n banked_predictors(0).io.update.bits.pc := nextBank(io.update.bits.pc)\n\n banked_predictors(1).io.update.bits.br_mask := io.update.bits.br_mask\n banked_predictors(0).io.update.bits.br_mask := io.update.bits.br_mask >> bankWidth\n\n banked_predictors(1).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts\n banked_predictors(0).io.update.bits.btb_mispredicts := io.update.bits.btb_mispredicts >> bankWidth\n\n banked_predictors(1).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits < bankWidth.U\n banked_predictors(0).io.update.bits.cfi_idx.valid := io.update.bits.cfi_idx.valid && io.update.bits.cfi_idx.bits >= bankWidth.U\n\n banked_predictors(1).io.update.bits.ghist := io.update.bits.ghist.histories(0)\n banked_predictors(0).io.update.bits.ghist := io.update.bits.ghist.histories(1)\n }\n\n }\n\n when (io.update.valid) {\n when (io.update.bits.cfi_is_br && io.update.bits.cfi_idx.valid) {\n assert(io.update.bits.br_mask(io.update.bits.cfi_idx.bits))\n }\n }\n}\n\nclass NullBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) {\n val mems = Nil\n}", + "response": "module BranchPredictor(\n input clock,\n input reset,\n input io_f0_req_valid,\n input [39:0] io_f0_req_bits_pc,\n input [63:0] io_f0_req_bits_ghist_old_history,\n output io_resp_f1_preds_0_taken,\n output io_resp_f1_preds_0_is_br,\n output io_resp_f1_preds_0_is_jal,\n output io_resp_f1_preds_0_predicted_pc_valid,\n output [39:0] io_resp_f1_preds_0_predicted_pc_bits,\n output io_resp_f1_preds_1_taken,\n output io_resp_f1_preds_1_is_br,\n output io_resp_f1_preds_1_is_jal,\n output io_resp_f1_preds_1_predicted_pc_valid,\n output [39:0] io_resp_f1_preds_1_predicted_pc_bits,\n output io_resp_f1_preds_2_taken,\n output io_resp_f1_preds_2_is_br,\n output io_resp_f1_preds_2_is_jal,\n output io_resp_f1_preds_2_predicted_pc_valid,\n output [39:0] io_resp_f1_preds_2_predicted_pc_bits,\n output io_resp_f1_preds_3_taken,\n output io_resp_f1_preds_3_is_br,\n output io_resp_f1_preds_3_is_jal,\n output io_resp_f1_preds_3_predicted_pc_valid,\n output [39:0] io_resp_f1_preds_3_predicted_pc_bits,\n output io_resp_f2_preds_0_taken,\n output io_resp_f2_preds_0_is_br,\n output io_resp_f2_preds_0_is_jal,\n output io_resp_f2_preds_0_predicted_pc_valid,\n output [39:0] io_resp_f2_preds_0_predicted_pc_bits,\n output io_resp_f2_preds_1_taken,\n output io_resp_f2_preds_1_is_br,\n output io_resp_f2_preds_1_is_jal,\n output io_resp_f2_preds_1_predicted_pc_valid,\n output [39:0] io_resp_f2_preds_1_predicted_pc_bits,\n output io_resp_f2_preds_2_taken,\n output io_resp_f2_preds_2_is_br,\n output io_resp_f2_preds_2_is_jal,\n output io_resp_f2_preds_2_predicted_pc_valid,\n output [39:0] io_resp_f2_preds_2_predicted_pc_bits,\n output io_resp_f2_preds_3_taken,\n output io_resp_f2_preds_3_is_br,\n output io_resp_f2_preds_3_is_jal,\n output io_resp_f2_preds_3_predicted_pc_valid,\n output [39:0] io_resp_f2_preds_3_predicted_pc_bits,\n output [39:0] io_resp_f3_pc,\n output io_resp_f3_preds_0_taken,\n output io_resp_f3_preds_0_is_br,\n output io_resp_f3_preds_0_is_jal,\n output io_resp_f3_preds_0_predicted_pc_valid,\n output [39:0] io_resp_f3_preds_0_predicted_pc_bits,\n output io_resp_f3_preds_1_taken,\n output io_resp_f3_preds_1_is_br,\n output io_resp_f3_preds_1_is_jal,\n output io_resp_f3_preds_1_predicted_pc_valid,\n output [39:0] io_resp_f3_preds_1_predicted_pc_bits,\n output io_resp_f3_preds_2_taken,\n output io_resp_f3_preds_2_is_br,\n output io_resp_f3_preds_2_is_jal,\n output io_resp_f3_preds_2_predicted_pc_valid,\n output [39:0] io_resp_f3_preds_2_predicted_pc_bits,\n output io_resp_f3_preds_3_taken,\n output io_resp_f3_preds_3_is_br,\n output io_resp_f3_preds_3_is_jal,\n output io_resp_f3_preds_3_predicted_pc_valid,\n output [39:0] io_resp_f3_preds_3_predicted_pc_bits,\n output [119:0] io_resp_f3_meta_0,\n input io_f3_fire,\n input io_update_valid,\n input io_update_bits_is_mispredict_update,\n input io_update_bits_is_repair_update,\n input [3:0] io_update_bits_btb_mispredicts,\n input [39:0] io_update_bits_pc,\n input [3:0] io_update_bits_br_mask,\n input io_update_bits_cfi_idx_valid,\n input [1:0] io_update_bits_cfi_idx_bits,\n input io_update_bits_cfi_taken,\n input io_update_bits_cfi_mispredicted,\n input io_update_bits_cfi_is_br,\n input io_update_bits_cfi_is_jal,\n input [63:0] io_update_bits_ghist_old_history,\n input [39:0] io_update_bits_target,\n input [119:0] io_update_bits_meta_0\n);\n\n wire [6:0] _banked_predictors_0_io_f0_mask_T = 7'hF << io_f0_req_bits_pc[2:1];\n reg [63:0] banked_predictors_0_io_f1_ghist_REG;\n reg [39:0] io_resp_f1_pc_REG;\n reg [39:0] io_resp_f2_pc_REG;\n reg [39:0] io_resp_f3_pc_REG;\n always @(posedge clock) begin\n banked_predictors_0_io_f1_ghist_REG <= io_f0_req_bits_ghist_old_history;\n io_resp_f1_pc_REG <= io_f0_req_bits_pc;\n io_resp_f2_pc_REG <= io_resp_f1_pc_REG;\n io_resp_f3_pc_REG <= io_resp_f2_pc_REG;\n end\n ComposedBranchPredictorBank banked_predictors_0 (\n .clock (clock),\n .reset (reset),\n .io_f0_valid (io_f0_req_valid),\n .io_f0_pc ({io_f0_req_bits_pc[39:3], 3'h0}),\n .io_f0_mask (_banked_predictors_0_io_f0_mask_T[3:0]),\n .io_f1_ghist (banked_predictors_0_io_f1_ghist_REG),\n .io_resp_f1_0_taken (io_resp_f1_preds_0_taken),\n .io_resp_f1_0_is_br (io_resp_f1_preds_0_is_br),\n .io_resp_f1_0_is_jal (io_resp_f1_preds_0_is_jal),\n .io_resp_f1_0_predicted_pc_valid (io_resp_f1_preds_0_predicted_pc_valid),\n .io_resp_f1_0_predicted_pc_bits (io_resp_f1_preds_0_predicted_pc_bits),\n .io_resp_f1_1_taken (io_resp_f1_preds_1_taken),\n .io_resp_f1_1_is_br (io_resp_f1_preds_1_is_br),\n .io_resp_f1_1_is_jal (io_resp_f1_preds_1_is_jal),\n .io_resp_f1_1_predicted_pc_valid (io_resp_f1_preds_1_predicted_pc_valid),\n .io_resp_f1_1_predicted_pc_bits (io_resp_f1_preds_1_predicted_pc_bits),\n .io_resp_f1_2_taken (io_resp_f1_preds_2_taken),\n .io_resp_f1_2_is_br (io_resp_f1_preds_2_is_br),\n .io_resp_f1_2_is_jal (io_resp_f1_preds_2_is_jal),\n .io_resp_f1_2_predicted_pc_valid (io_resp_f1_preds_2_predicted_pc_valid),\n .io_resp_f1_2_predicted_pc_bits (io_resp_f1_preds_2_predicted_pc_bits),\n .io_resp_f1_3_taken (io_resp_f1_preds_3_taken),\n .io_resp_f1_3_is_br (io_resp_f1_preds_3_is_br),\n .io_resp_f1_3_is_jal (io_resp_f1_preds_3_is_jal),\n .io_resp_f1_3_predicted_pc_valid (io_resp_f1_preds_3_predicted_pc_valid),\n .io_resp_f1_3_predicted_pc_bits (io_resp_f1_preds_3_predicted_pc_bits),\n .io_resp_f2_0_taken (io_resp_f2_preds_0_taken),\n .io_resp_f2_0_is_br (io_resp_f2_preds_0_is_br),\n .io_resp_f2_0_is_jal (io_resp_f2_preds_0_is_jal),\n .io_resp_f2_0_predicted_pc_valid (io_resp_f2_preds_0_predicted_pc_valid),\n .io_resp_f2_0_predicted_pc_bits (io_resp_f2_preds_0_predicted_pc_bits),\n .io_resp_f2_1_taken (io_resp_f2_preds_1_taken),\n .io_resp_f2_1_is_br (io_resp_f2_preds_1_is_br),\n .io_resp_f2_1_is_jal (io_resp_f2_preds_1_is_jal),\n .io_resp_f2_1_predicted_pc_valid (io_resp_f2_preds_1_predicted_pc_valid),\n .io_resp_f2_1_predicted_pc_bits (io_resp_f2_preds_1_predicted_pc_bits),\n .io_resp_f2_2_taken (io_resp_f2_preds_2_taken),\n .io_resp_f2_2_is_br (io_resp_f2_preds_2_is_br),\n .io_resp_f2_2_is_jal (io_resp_f2_preds_2_is_jal),\n .io_resp_f2_2_predicted_pc_valid (io_resp_f2_preds_2_predicted_pc_valid),\n .io_resp_f2_2_predicted_pc_bits (io_resp_f2_preds_2_predicted_pc_bits),\n .io_resp_f2_3_taken (io_resp_f2_preds_3_taken),\n .io_resp_f2_3_is_br (io_resp_f2_preds_3_is_br),\n .io_resp_f2_3_is_jal (io_resp_f2_preds_3_is_jal),\n .io_resp_f2_3_predicted_pc_valid (io_resp_f2_preds_3_predicted_pc_valid),\n .io_resp_f2_3_predicted_pc_bits (io_resp_f2_preds_3_predicted_pc_bits),\n .io_resp_f3_0_taken (io_resp_f3_preds_0_taken),\n .io_resp_f3_0_is_br (io_resp_f3_preds_0_is_br),\n .io_resp_f3_0_is_jal (io_resp_f3_preds_0_is_jal),\n .io_resp_f3_0_predicted_pc_valid (io_resp_f3_preds_0_predicted_pc_valid),\n .io_resp_f3_0_predicted_pc_bits (io_resp_f3_preds_0_predicted_pc_bits),\n .io_resp_f3_1_taken (io_resp_f3_preds_1_taken),\n .io_resp_f3_1_is_br (io_resp_f3_preds_1_is_br),\n .io_resp_f3_1_is_jal (io_resp_f3_preds_1_is_jal),\n .io_resp_f3_1_predicted_pc_valid (io_resp_f3_preds_1_predicted_pc_valid),\n .io_resp_f3_1_predicted_pc_bits (io_resp_f3_preds_1_predicted_pc_bits),\n .io_resp_f3_2_taken (io_resp_f3_preds_2_taken),\n .io_resp_f3_2_is_br (io_resp_f3_preds_2_is_br),\n .io_resp_f3_2_is_jal (io_resp_f3_preds_2_is_jal),\n .io_resp_f3_2_predicted_pc_valid (io_resp_f3_preds_2_predicted_pc_valid),\n .io_resp_f3_2_predicted_pc_bits (io_resp_f3_preds_2_predicted_pc_bits),\n .io_resp_f3_3_taken (io_resp_f3_preds_3_taken),\n .io_resp_f3_3_is_br (io_resp_f3_preds_3_is_br),\n .io_resp_f3_3_is_jal (io_resp_f3_preds_3_is_jal),\n .io_resp_f3_3_predicted_pc_valid (io_resp_f3_preds_3_predicted_pc_valid),\n .io_resp_f3_3_predicted_pc_bits (io_resp_f3_preds_3_predicted_pc_bits),\n .io_f3_meta (io_resp_f3_meta_0),\n .io_f3_fire (io_f3_fire),\n .io_update_valid (io_update_valid),\n .io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update),\n .io_update_bits_is_repair_update (io_update_bits_is_repair_update),\n .io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts),\n .io_update_bits_pc ({io_update_bits_pc[39:3], 3'h0}),\n .io_update_bits_br_mask (io_update_bits_br_mask),\n .io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid),\n .io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits),\n .io_update_bits_cfi_taken (io_update_bits_cfi_taken),\n .io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted),\n .io_update_bits_cfi_is_br (io_update_bits_cfi_is_br),\n .io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal),\n .io_update_bits_ghist (io_update_bits_ghist_old_history),\n .io_update_bits_target (io_update_bits_target),\n .io_update_bits_meta (io_update_bits_meta_0)\n );\n assign io_resp_f3_pc = io_resp_f3_pc_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", + "response": "module ClockCrossingReg_w55(\n input clock,\n input [54:0] io_d,\n output [54:0] io_q,\n input io_en\n);\n\n reg [54:0] cdc_reg;\n always @(posedge clock) begin\n if (io_en)\n cdc_reg <= io_d;\n end\n assign io_q = cdc_reg;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us_2(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_0_ext hi_us_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tilelink\n\nimport chisel3._\nimport chisel3.util._\n\nclass Atomics(params: TLBundleParameters) extends Module\n{\n val io = IO(new Bundle {\n val write = Flipped(Bool()) // ignore opcode\n val a = Flipped(new TLBundleA(params))\n val data_in = Flipped(UInt(params.dataBits.W))\n val data_out = UInt(params.dataBits.W)\n })\n\n // Arithmetic, what to do\n val adder = io.a.param(2)\n val unsigned = io.a.param(1)\n val take_max = io.a.param(0)\n\n val signBit = io.a.mask & Cat(1.U, ~io.a.mask >> 1)\n val inv_d = Mux(adder, io.data_in, ~io.data_in)\n val sum = (FillInterleaved(8, io.a.mask) & io.a.data) + inv_d\n def sign(x: UInt): Bool = (Cat(x.asBools.grouped(8).map(_.last).toList.reverse) & signBit).orR\n val sign_a = sign(io.a.data)\n val sign_d = sign(io.data_in)\n val sign_s = sign(sum)\n val a_bigger_uneq = unsigned === sign_a // result if high bits are unequal\n val a_bigger = Mux(sign_a === sign_d, !sign_s, a_bigger_uneq)\n val pick_a = take_max === a_bigger\n\n // Logical, what to do\n val lut = VecInit(Seq(\n (0x6).U, // XOR\n (0xe).U, // OR\n (0x8).U, // AND\n (0xc).U))( // SWAP\n io.a.param(1,0))\n val logical = Cat((io.a.data.asBools zip io.data_in.asBools).map { case (a, d) =>\n lut(Cat(a, d))\n }.reverse)\n\n // Operation, what to do? (0=d, 1=a, 2=sum, 3=logical)\n val select = Mux(io.write, 1.U, VecInit(Seq(\n 1.U, // PutFullData\n 1.U, // PutPartialData\n Mux(adder, 2.U, Mux(pick_a, 1.U, 0.U)), // ArithmeticData\n 3.U, // LogicalData\n 0.U, // Get\n 0.U, // Hint\n 0.U, // AcquireBlock\n 0.U))( // AcquirePerm\n io.a.opcode))\n\n // Only the masked bytes can be modified\n val selects = io.a.mask.asBools.map(b => Mux(b, select, 0.U))\n io.data_out := Cat(selects.zipWithIndex.map { case (s, i) =>\n VecInit(Seq(io.data_in, io.a.data, sum, logical).map(_((i + 1) * 8 - 1, i * 8)))(s)\n }.reverse)\n}", + "response": "module Atomics(\n input io_write,\n input [2:0] io_a_opcode,\n input [2:0] io_a_param,\n input [3:0] io_a_mask,\n input [31:0] io_a_data,\n input [31:0] io_data_in,\n output [31:0] io_data_out\n);\n\n wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};\n wire [3:0] signBit = io_a_mask & {1'h1, ~(io_a_mask[3:1])};\n wire [31:0] _sum_T_10 = ({{8{io_a_mask[3]}}, {8{io_a_mask[2]}}, {8{io_a_mask[1]}}, {8{io_a_mask[0]}}} & io_a_data) + ({32{~(io_a_param[2])}} ^ io_data_in);\n wire [3:0] _sign_a_T_33 = {io_a_data[31], io_a_data[23], io_a_data[15], io_a_data[7]} & signBit;\n wire [3:0] _GEN_0 = _GEN[io_a_param[1:0]];\n wire [3:0] _logical_T_65 = _GEN_0 >> {2'h0, io_a_data[0], io_data_in[0]};\n wire [3:0] _logical_T_68 = _GEN_0 >> {2'h0, io_a_data[1], io_data_in[1]};\n wire [3:0] _logical_T_71 = _GEN_0 >> {2'h0, io_a_data[2], io_data_in[2]};\n wire [3:0] _logical_T_74 = _GEN_0 >> {2'h0, io_a_data[3], io_data_in[3]};\n wire [3:0] _logical_T_77 = _GEN_0 >> {2'h0, io_a_data[4], io_data_in[4]};\n wire [3:0] _logical_T_80 = _GEN_0 >> {2'h0, io_a_data[5], io_data_in[5]};\n wire [3:0] _logical_T_83 = _GEN_0 >> {2'h0, io_a_data[6], io_data_in[6]};\n wire [3:0] _logical_T_86 = _GEN_0 >> {2'h0, io_a_data[7], io_data_in[7]};\n wire [3:0] _logical_T_89 = _GEN_0 >> {2'h0, io_a_data[8], io_data_in[8]};\n wire [3:0] _logical_T_92 = _GEN_0 >> {2'h0, io_a_data[9], io_data_in[9]};\n wire [3:0] _logical_T_95 = _GEN_0 >> {2'h0, io_a_data[10], io_data_in[10]};\n wire [3:0] _logical_T_98 = _GEN_0 >> {2'h0, io_a_data[11], io_data_in[11]};\n wire [3:0] _logical_T_101 = _GEN_0 >> {2'h0, io_a_data[12], io_data_in[12]};\n wire [3:0] _logical_T_104 = _GEN_0 >> {2'h0, io_a_data[13], io_data_in[13]};\n wire [3:0] _logical_T_107 = _GEN_0 >> {2'h0, io_a_data[14], io_data_in[14]};\n wire [3:0] _logical_T_110 = _GEN_0 >> {2'h0, io_a_data[15], io_data_in[15]};\n wire [3:0] _logical_T_113 = _GEN_0 >> {2'h0, io_a_data[16], io_data_in[16]};\n wire [3:0] _logical_T_116 = _GEN_0 >> {2'h0, io_a_data[17], io_data_in[17]};\n wire [3:0] _logical_T_119 = _GEN_0 >> {2'h0, io_a_data[18], io_data_in[18]};\n wire [3:0] _logical_T_122 = _GEN_0 >> {2'h0, io_a_data[19], io_data_in[19]};\n wire [3:0] _logical_T_125 = _GEN_0 >> {2'h0, io_a_data[20], io_data_in[20]};\n wire [3:0] _logical_T_128 = _GEN_0 >> {2'h0, io_a_data[21], io_data_in[21]};\n wire [3:0] _logical_T_131 = _GEN_0 >> {2'h0, io_a_data[22], io_data_in[22]};\n wire [3:0] _logical_T_134 = _GEN_0 >> {2'h0, io_a_data[23], io_data_in[23]};\n wire [3:0] _logical_T_137 = _GEN_0 >> {2'h0, io_a_data[24], io_data_in[24]};\n wire [3:0] _logical_T_140 = _GEN_0 >> {2'h0, io_a_data[25], io_data_in[25]};\n wire [3:0] _logical_T_143 = _GEN_0 >> {2'h0, io_a_data[26], io_data_in[26]};\n wire [3:0] _logical_T_146 = _GEN_0 >> {2'h0, io_a_data[27], io_data_in[27]};\n wire [3:0] _logical_T_149 = _GEN_0 >> {2'h0, io_a_data[28], io_data_in[28]};\n wire [3:0] _logical_T_152 = _GEN_0 >> {2'h0, io_a_data[29], io_data_in[29]};\n wire [3:0] _logical_T_155 = _GEN_0 >> {2'h0, io_a_data[30], io_data_in[30]};\n wire [3:0] _logical_T_158 = _GEN_0 >> {2'h0, io_a_data[31], io_data_in[31]};\n wire [7:0][1:0] _GEN_1 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {io_a_param[2] ? 2'h2 : {1'h0, io_a_param[0] == ((|_sign_a_T_33) == (|({io_data_in[31], io_data_in[23], io_data_in[15], io_data_in[7]} & signBit)) ? ({_sum_T_10[31], _sum_T_10[23], _sum_T_10[15], _sum_T_10[7]} & signBit) == 4'h0 : io_a_param[1] == (|_sign_a_T_33))}}, {2'h1}, {2'h1}};\n wire [1:0] select = io_write ? 2'h1 : _GEN_1[io_a_opcode];\n wire [3:0][7:0] _GEN_2 = {{{_logical_T_110[0], _logical_T_107[0], _logical_T_104[0], _logical_T_101[0], _logical_T_98[0], _logical_T_95[0], _logical_T_92[0], _logical_T_89[0]}}, {_sum_T_10[15:8]}, {io_a_data[15:8]}, {io_data_in[15:8]}};\n wire [3:0][7:0] _GEN_3 = {{{_logical_T_86[0], _logical_T_83[0], _logical_T_80[0], _logical_T_77[0], _logical_T_74[0], _logical_T_71[0], _logical_T_68[0], _logical_T_65[0]}}, {_sum_T_10[7:0]}, {io_a_data[7:0]}, {io_data_in[7:0]}};\n wire [3:0][7:0] _GEN_4 = {{{_logical_T_158[0], _logical_T_155[0], _logical_T_152[0], _logical_T_149[0], _logical_T_146[0], _logical_T_143[0], _logical_T_140[0], _logical_T_137[0]}}, {_sum_T_10[31:24]}, {io_a_data[31:24]}, {io_data_in[31:24]}};\n wire [3:0][7:0] _GEN_5 = {{{_logical_T_134[0], _logical_T_131[0], _logical_T_128[0], _logical_T_125[0], _logical_T_122[0], _logical_T_119[0], _logical_T_116[0], _logical_T_113[0]}}, {_sum_T_10[23:16]}, {io_a_data[23:16]}, {io_data_in[23:16]}};\n assign io_data_out = {_GEN_4[io_a_mask[3] ? select : 2'h0], _GEN_5[io_a_mask[2] ? select : 2'h0], _GEN_2[io_a_mask[1] ? select : 2'h0], _GEN_3[io_a_mask[0] ? select : 2'h0]};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLEFromBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\n\nclass DivSqrtRecF64 extends Module\n{\n val io = IO(new Bundle {\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(Bits(3.W))\n val detectTininess = Input(UInt(1.W))\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(Bits(65.W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val ds = Module(new DivSqrtRecF64_mulAddZ31(0))\n\n io.inReady_div := ds.io.inReady_div\n io.inReady_sqrt := ds.io.inReady_sqrt\n ds.io.inValid := io.inValid\n ds.io.sqrtOp := io.sqrtOp\n ds.io.a := io.a\n ds.io.b := io.b\n ds.io.roundingMode := io.roundingMode\n ds.io.detectTininess := io.detectTininess\n io.outValid_div := ds.io.outValid_div\n io.outValid_sqrt := ds.io.outValid_sqrt\n io.out := ds.io.out\n io.exceptionFlags := ds.io.exceptionFlags\n\n val mul = Module(new Mul54)\n\n mul.io.val_s0 := ds.io.usingMulAdd(0)\n mul.io.latch_a_s0 := ds.io.latchMulAddA_0\n mul.io.a_s0 := ds.io.mulAddA_0\n mul.io.latch_b_s0 := ds.io.latchMulAddB_0\n mul.io.b_s0 := ds.io.mulAddB_0\n mul.io.c_s2 := ds.io.mulAddC_2\n ds.io.mulAddResult_3 := mul.io.result_s3\n}\n\nclass Mul54 extends Module\n{\n val io = IO(new Bundle {\n val val_s0 = Input(Bool())\n val latch_a_s0 = Input(Bool())\n val a_s0 = Input(UInt(54.W))\n val latch_b_s0 = Input(Bool())\n val b_s0 = Input(UInt(54.W))\n val c_s2 = Input(UInt(105.W))\n val result_s3 = Output(UInt(105.W))\n })\n\n val val_s1 = Reg(Bool())\n val val_s2 = Reg(Bool())\n val reg_a_s1 = Reg(UInt(54.W))\n val reg_b_s1 = Reg(UInt(54.W))\n val reg_a_s2 = Reg(UInt(54.W))\n val reg_b_s2 = Reg(UInt(54.W))\n val reg_result_s3 = Reg(UInt(105.W))\n\n val_s1 := io.val_s0\n val_s2 := val_s1\n\n when (io.val_s0) {\n when (io.latch_a_s0) {\n reg_a_s1 := io.a_s0\n }\n when (io.latch_b_s0) {\n reg_b_s1 := io.b_s0\n }\n }\n\n when (val_s1) {\n reg_a_s2 := reg_a_s1\n reg_b_s2 := reg_b_s1\n }\n\n when (val_s2) {\n reg_result_s3 := (reg_a_s2 * reg_b_s2)(104,0) + io.c_s2\n }\n\n io.result_s3 := reg_result_s3\n}", + "response": "module DivSqrtRecF64(\n input clock,\n input reset,\n output io_inReady_div,\n output io_inReady_sqrt,\n input io_inValid,\n input io_sqrtOp,\n input [64:0] io_a,\n input [64:0] io_b,\n input [2:0] io_roundingMode,\n output io_outValid_div,\n output io_outValid_sqrt,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire [104:0] _mul_io_result_s3;\n wire [3:0] _ds_io_usingMulAdd;\n wire _ds_io_latchMulAddA_0;\n wire [53:0] _ds_io_mulAddA_0;\n wire _ds_io_latchMulAddB_0;\n wire [53:0] _ds_io_mulAddB_0;\n wire [104:0] _ds_io_mulAddC_2;\n DivSqrtRecF64_mulAddZ31 ds (\n .clock (clock),\n .reset (reset),\n .io_inReady_div (io_inReady_div),\n .io_inReady_sqrt (io_inReady_sqrt),\n .io_inValid (io_inValid),\n .io_sqrtOp (io_sqrtOp),\n .io_a (io_a),\n .io_b (io_b),\n .io_roundingMode (io_roundingMode),\n .io_usingMulAdd (_ds_io_usingMulAdd),\n .io_latchMulAddA_0 (_ds_io_latchMulAddA_0),\n .io_mulAddA_0 (_ds_io_mulAddA_0),\n .io_latchMulAddB_0 (_ds_io_latchMulAddB_0),\n .io_mulAddB_0 (_ds_io_mulAddB_0),\n .io_mulAddC_2 (_ds_io_mulAddC_2),\n .io_mulAddResult_3 (_mul_io_result_s3),\n .io_outValid_div (io_outValid_div),\n .io_outValid_sqrt (io_outValid_sqrt),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\n Mul54 mul (\n .clock (clock),\n .io_val_s0 (_ds_io_usingMulAdd[0]),\n .io_latch_a_s0 (_ds_io_latchMulAddA_0),\n .io_a_s0 (_ds_io_mulAddA_0),\n .io_latch_b_s0 (_ds_io_latchMulAddB_0),\n .io_b_s0 (_ds_io_mulAddB_0),\n .io_c_s2 (_ds_io_mulAddC_2),\n .io_result_s3 (_mul_io_result_s3)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module data_35x43(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [42:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [42:0] W0_data\n);\n\n reg [42:0] Memory[0:34];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 43'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module data_33x44(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [43:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [43:0] W0_data\n);\n\n reg [43:0] Memory[0:32];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 44'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomBTBParams(\n nSets: Int = 128,\n nWays: Int = 2,\n offsetSz: Int = 13,\n extendedNSets: Int = 128\n)\n\n\nclass BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n override val nWays = params.nWays\n val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1\n val offsetSz = params.offsetSz\n val extendedNSets = params.extendedNSets\n\n require(isPow2(nSets))\n require(isPow2(extendedNSets) || extendedNSets == 0)\n require(extendedNSets <= nSets)\n require(extendedNSets >= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }\n val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n\n val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })\n val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })\n val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n\n for (w <- 0 until bankWidth) {\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := Mux(\n entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n for (w <- 0 until nWays) {\n when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {\n btb(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wbtb_mask).asBools\n )\n meta(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wmeta_mask).asBools\n )\n\n\n }\n }\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n\n}", + "response": "module btb_1(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [55:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [55:0] W0_data,\n input [3:0] W0_mask\n);\n\n btb_0_ext btb_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.tilelink._\n\nclass SinkEResponse(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val sink = UInt(params.inner.bundle.sinkBits.W)\n}\n\nclass SinkE(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val resp = Valid(new SinkEResponse(params))\n val e = Flipped(Decoupled(new TLBundleE(params.inner.bundle)))\n })\n\n if (params.firstLevel) {\n // Tie off unused ports\n io.resp.valid := false.B\n io.resp.bits := DontCare\n io.e.ready := true.B\n } else {\n // No restrictions on buffer\n val e = params.micro.innerBuf.e(io.e)\n\n e.ready := true.B\n io.resp.valid := e.valid\n io.resp.bits.sink := e.bits.sink\n }\n}", + "response": "module SinkE(\n output io_resp_valid,\n output [2:0] io_resp_bits_sink,\n input io_e_valid,\n input [2:0] io_e_bits_sink\n);\n\n assign io_resp_valid = io_e_valid;\n assign io_resp_bits_sink = io_e_bits_sink;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n/** This black-boxes an Async Reset\n * (or Set)\n * Register.\n * \n * Because Chisel doesn't support\n * parameterized black boxes, \n * we unfortunately have to \n * instantiate a number of these.\n * \n * We also have to hard-code the set/\n * reset behavior.\n * \n * Do not confuse an asynchronous\n * reset signal with an asynchronously\n * reset reg. You should still \n * properly synchronize your reset \n * deassertion.\n * \n * @param d Data input\n * @param q Data Output\n * @param clk Clock Input\n * @param rst Reset Input\n * @param en Write Enable Input\n * \n */\n\nclass AsyncResetReg(resetValue: Int = 0) extends RawModule {\n val io = IO(new Bundle {\n val d = Input(Bool())\n val q = Output(Bool())\n val en = Input(Bool())\n\n val clk = Input(Clock())\n val rst = Input(Reset())\n })\n\n val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nclass SimpleRegIO(val w: Int) extends Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n}\n\nclass AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {\n override def desiredName = s\"AsyncResetRegVec_w${w}_i${init}\"\n\n val io = IO(new SimpleRegIO(w))\n\n val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nobject AsyncResetReg {\n // Create Single Registers\n def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {\n val reg = Module(new AsyncResetReg(if (init) 1 else 0))\n reg.io.d := d\n reg.io.clk := clk\n reg.io.rst := rst\n reg.io.en := true.B\n name.foreach(reg.suggestName(_))\n reg.io.q\n }\n\n def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)\n def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))\n\n // Create Vectors of Registers\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {\n val w = updateData.getWidth max resetData.bitLength\n val reg = Module(new AsyncResetRegVec(w, resetData))\n name.foreach(reg.suggestName(_))\n reg.io.d := updateData\n reg.io.en := enable\n reg.io.q\n }\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,\n resetData, enable, Some(name))\n\n\n def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))\n\n def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)\n def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))\n\n def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)\n def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))\n}", + "response": "module AsyncResetRegVec_w1_i0(\n input clock,\n input reset,\n input io_d,\n output io_q\n);\n\n reg reg_0;\n always @(posedge clock or posedge reset) begin\n if (reset)\n reg_0 <= 1'h0;\n else\n reg_0 <= io_d;\n end\n assign io_q = reg_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie8_is24_oe11_os53(\n input io_invalidExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [9:0] io_in_sExp,\n input [24:0] io_in_sig,\n output [64:0] io_out\n);\n\n wire isNaNOut = io_invalidExc | io_in_isNaN;\n assign io_out = {~isNaNOut & io_in_sign, {{2{io_in_sExp[9]}}, io_in_sExp} + 12'h700 & ~(io_in_isZero ? 12'hE00 : 12'h0) & {2'h3, ~io_in_isInf, 9'h1FF} | (io_in_isInf ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), isNaNOut | io_in_isZero ? {isNaNOut, 51'h0} : {io_in_sig[22:0], 29'h0}};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// ICache\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.util.random._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property._\nimport freechips.rocketchip.rocket.{HasL1ICacheParameters, ICacheParams, ICacheErrors, ICacheReq}\n\n\n\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * ICache module\n *\n * @param icacheParams parameters for the icache\n * @param hartId the id of the hardware thread in the cache\n * @param enableBlackBox use a blackbox icache\n */\nclass ICache(\n val icacheParams: ICacheParams,\n val staticIdForMetadataUseOnly: Int)(implicit p: Parameters)\n extends LazyModule\n{\n lazy val module = new ICacheModule(this)\n val masterNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(\n sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint\n name = s\"Core ${staticIdForMetadataUseOnly} ICache\")))))\n\n val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes\n private val wordBytes = icacheParams.fetchBytes\n}\n\n/**\n * IO Signals leaving the ICache\n *\n * @param outer top level ICache class\n */\nclass ICacheResp(val outer: ICache) extends Bundle\n{\n val data = UInt((outer.icacheParams.fetchBytes*8).W)\n val replay = Bool()\n val ae = Bool()\n}\n\n/**\n * IO Signals for interacting with the ICache\n *\n * @param outer top level ICache class\n */\nclass ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p)\n with HasBoomFrontendParameters\n{\n val req = Flipped(Decoupled(new ICacheReq))\n val s1_paddr = Input(UInt(paddrBits.W)) // delayed one cycle w.r.t. req\n\n val s1_kill = Input(Bool()) // delayed one cycle w.r.t. req\n val s2_kill = Input(Bool()) // delayed two cycles; prevents I$ miss emission\n\n val resp = Valid(new ICacheResp(outer))\n val invalidate = Input(Bool())\n\n val perf = Output(new Bundle {\n val acquire = Bool()\n })\n}\n\n/**\n * Get a tile-specific property without breaking deduplication\n */\nobject GetPropertyByHartId\n{\n def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {\n PriorityMux(tiles.collect { case t if f(t).isDefined => (t.tileId.U === hartId) -> f(t).get })\n }\n}\n\n\n/**\n * Main ICache module\n *\n * @param outer top level ICache class\n */\nclass ICacheModule(outer: ICache) extends LazyModuleImp(outer)\n with HasBoomFrontendParameters\n{\n val enableICacheDelay = tileParams.core.asInstanceOf[BoomCoreParams].enableICacheDelay\n val io = IO(new ICacheBundle(outer))\n val (tl_out, edge_out) = outer.masterNode.out(0)\n\n require(isPow2(nSets) && isPow2(nWays))\n require(usingVM)\n require(pgIdxBits >= untagBits)\n\n // How many bits do we intend to fetch at most every cycle?\n val wordBits = outer.icacheParams.fetchBytes*8\n // Each of these cases require some special-case handling.\n require (tl_out.d.bits.data.getWidth == wordBits || (2*tl_out.d.bits.data.getWidth == wordBits && nBanks == 2))\n // If TL refill is half the wordBits size and we have two banks, then the\n // refill writes to only one bank per cycle (instead of across two banks every\n // cycle).\n val refillsToOneBank = (2*tl_out.d.bits.data.getWidth == wordBits)\n\n\n\n val s0_valid = io.req.fire\n val s0_vaddr = io.req.bits.addr\n\n val s1_valid = RegNext(s0_valid)\n val s1_tag_hit = Wire(Vec(nWays, Bool()))\n val s1_hit = s1_tag_hit.reduce(_||_)\n val s2_valid = RegNext(s1_valid && !io.s1_kill)\n val s2_hit = RegNext(s1_hit)\n\n\n val invalidated = Reg(Bool())\n val refill_valid = RegInit(false.B)\n val refill_fire = tl_out.a.fire\n val s2_miss = s2_valid && !s2_hit && !RegNext(refill_valid)\n val refill_paddr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss))\n val refill_tag = refill_paddr(tagBits+untagBits-1,untagBits)\n val refill_idx = refill_paddr(untagBits-1,blockOffBits)\n val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits)\n\n io.req.ready := !refill_one_beat\n\n val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)\n val refill_done = refill_one_beat && d_done\n tl_out.d.ready := true.B\n require (edge_out.manager.minLatency > 0)\n\n val repl_way = if (isDM) 0.U else LFSR(16, refill_fire)(log2Ceil(nWays)-1,0)\n\n val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(tagBits.W)))\n val tag_rdata = tag_array.read(s0_vaddr(untagBits-1, blockOffBits), !refill_done && s0_valid)\n when (refill_done) {\n tag_array.write(refill_idx, VecInit(Seq.fill(nWays)(refill_tag)), Seq.tabulate(nWays)(repl_way === _.U))\n }\n\n val vb_array = RegInit(0.U((nSets*nWays).W))\n when (refill_one_beat) {\n vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)\n }\n\n when (io.invalidate) {\n vb_array := 0.U\n invalidated := true.B\n }\n\n val s2_dout = Wire(Vec(nWays, UInt(wordBits.W)))\n val s1_bankid = Wire(Bool())\n\n for (i <- 0 until nWays) {\n val s1_idx = io.s1_paddr(untagBits-1,blockOffBits)\n val s1_tag = io.s1_paddr(tagBits+untagBits-1,untagBits)\n val s1_vb = vb_array(Cat(i.U, s1_idx))\n val tag = tag_rdata(i)\n s1_tag_hit(i) := s1_vb && tag === s1_tag\n }\n assert(PopCount(s1_tag_hit) <= 1.U || !s1_valid)\n\n val ramDepth = if (refillsToOneBank && nBanks == 2) {\n nSets * refillCycles / 2\n } else {\n nSets * refillCycles\n }\n\n val dataArrays = if (nBanks == 1) {\n // Use unbanked icache for narrow accesses.\n (0 until nWays).map { x =>\n DescribedSRAM(\n name = s\"dataArrayWay_${x}\",\n desc = \"ICache Data Array\",\n size = ramDepth,\n data = UInt((wordBits).W)\n )\n }\n } else {\n // Use two banks, interleaved.\n (0 until nWays).map { x =>\n DescribedSRAM(\n name = s\"dataArrayB0Way_${x}\",\n desc = \"ICache Data Array\",\n size = ramDepth,\n data = UInt((wordBits/nBanks).W)\n )} ++\n (0 until nWays).map { x =>\n DescribedSRAM(\n name = s\"dataArrayB1Way_${x}\",\n desc = \"ICache Data Array\",\n size = ramDepth,\n data = UInt((wordBits/nBanks).W)\n )}\n }\n if (nBanks == 1) {\n // Use unbanked icache for narrow accesses.\n s1_bankid := 0.U\n for ((dataArray, i) <- dataArrays.zipWithIndex) {\n def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))\n val s0_ren = s0_valid\n\n val wen = (refill_one_beat && !invalidated) && repl_way === i.U\n\n val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,\n row(s0_vaddr))\n when (wen) {\n dataArray.write(mem_idx, tl_out.d.bits.data)\n }\n if (enableICacheDelay)\n s2_dout(i) := dataArray.read(RegNext(mem_idx), RegNext(!wen && s0_ren))\n else\n s2_dout(i) := RegNext(dataArray.read(mem_idx, !wen && s0_ren))\n }\n } else {\n // Use two banks, interleaved.\n val dataArraysB0 = dataArrays.take(nWays)\n val dataArraysB1 = dataArrays.drop(nWays)\n require (nBanks == 2)\n\n // Bank0 row's id wraps around if Bank1 is the starting bank.\n def b0Row(addr: UInt) =\n if (refillsToOneBank) {\n addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1) + bank(addr)\n } else {\n addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) + bank(addr)\n }\n // Bank1 row's id stays the same regardless of which Bank has the fetch address.\n def b1Row(addr: UInt) =\n if (refillsToOneBank) {\n addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)+1)\n } else {\n addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))\n }\n\n s1_bankid := RegNext(bank(s0_vaddr))\n\n for (i <- 0 until nWays) {\n val s0_ren = s0_valid\n val wen = (refill_one_beat && !invalidated)&& repl_way === i.U\n\n var mem_idx0: UInt = null\n var mem_idx1: UInt = null\n\n if (refillsToOneBank) {\n // write a refill beat across only one beat.\n mem_idx0 =\n Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U),\n b0Row(s0_vaddr))\n mem_idx1 =\n Mux(refill_one_beat, (refill_idx << (log2Ceil(refillCycles)-1)) | (refill_cnt >> 1.U),\n b1Row(s0_vaddr))\n\n when (wen && refill_cnt(0) === 0.U) {\n dataArraysB0(i).write(mem_idx0, tl_out.d.bits.data)\n }\n when (wen && refill_cnt(0) === 1.U) {\n dataArraysB1(i).write(mem_idx1, tl_out.d.bits.data)\n }\n } else {\n // write a refill beat across both banks.\n mem_idx0 =\n Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,\n b0Row(s0_vaddr))\n mem_idx1 =\n Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,\n b1Row(s0_vaddr))\n\n when (wen) {\n val data = tl_out.d.bits.data\n dataArraysB0(i).write(mem_idx0, data(wordBits/2-1, 0))\n dataArraysB1(i).write(mem_idx1, data(wordBits-1, wordBits/2))\n }\n }\n if (enableICacheDelay) {\n s2_dout(i) := Cat(dataArraysB1(i).read(RegNext(mem_idx1), RegNext(!wen && s0_ren)),\n dataArraysB0(i).read(RegNext(mem_idx0), RegNext(!wen && s0_ren)))\n } else {\n s2_dout(i) := RegNext(Cat(dataArraysB1(i).read(mem_idx1, !wen && s0_ren),\n dataArraysB0(i).read(mem_idx0, !wen && s0_ren)))\n }\n }\n }\n val s2_tag_hit = RegNext(s1_tag_hit)\n val s2_hit_way = OHToUInt(s2_tag_hit)\n val s2_bankid = RegNext(s1_bankid)\n val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)\n\n val s2_unbanked_data = s2_way_mux\n val sz = s2_way_mux.getWidth\n val s2_bank0_data = s2_way_mux(sz/2-1,0)\n val s2_bank1_data = s2_way_mux(sz-1,sz/2)\n\n val s2_data =\n if (nBanks == 2) {\n Mux(s2_bankid,\n Cat(s2_bank0_data, s2_bank1_data),\n Cat(s2_bank1_data, s2_bank0_data))\n } else {\n s2_unbanked_data\n }\n\n io.resp.bits.ae := DontCare\n io.resp.bits.replay := DontCare\n io.resp.bits.data := s2_data\n io.resp.valid := s2_valid && s2_hit\n\n tl_out.a.valid := s2_miss && !refill_valid && !io.s2_kill\n tl_out.a.bits := edge_out.Get(\n fromSource = 0.U,\n toAddress = (refill_paddr >> blockOffBits) << blockOffBits,\n lgSize = lgCacheBlockBytes.U)._2\n tl_out.b.ready := true.B\n tl_out.c.valid := false.B\n tl_out.e.valid := false.B\n\n io.perf.acquire := tl_out.a.fire\n\n when (!refill_valid) { invalidated := false.B }\n when (refill_fire) { refill_valid := true.B }\n when (refill_done) { refill_valid := false.B }\n\n override def toString: String = BoomCoreStringPrefix(\n \"==L1-ICache==\",\n \"Fetch bytes : \" + cacheParams.fetchBytes,\n \"Block bytes : \" + (1 << blockOffBits),\n \"Row bytes : \" + rowBytes,\n \"Word bits : \" + wordBits,\n \"Sets : \" + nSets,\n \"Ways : \" + nWays,\n \"Refill cycles : \" + refillCycles,\n \"RAMs : (\" + wordBits/nBanks + \" x \" + nSets*refillCycles + \") using \" + nBanks + \" banks\",\n \"\" + (if (nBanks == 2) \"Dual-banked\" else \"Single-banked\"),\n \"I-TLB ways : \" + cacheParams.nTLBWays + \"\\n\")\n}", + "response": "module tag_array_0(\n input [5:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [79:0] RW0_wdata,\n output [79:0] RW0_rdata,\n input [3:0] RW0_wmask\n);\n\n tag_array_0_ext tag_array_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLAFromBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Execution Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// The issue window schedules micro-ops onto a specific execution pipeline\n// A given execution pipeline may contain multiple functional units; one or more\n// read ports, and one or more writeports.\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.rocket.{BP}\nimport freechips.rocketchip.tile\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.ifu.{GetPCFromFtqIO}\nimport boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}\n\n/**\n * Response from Execution Unit. Bundles a MicroOp with data\n *\n * @param dataWidth width of the data coming from the execution unit\n */\nclass ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val data = Bits(dataWidth.W)\n val predicated = Bool() // Was this predicated off?\n val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better\n}\n\n/**\n * Floating Point flag response\n */\nclass FFlagsResp(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val flags = Bits(tile.FPConstants.FLAGS_SZ.W)\n}\n\n\n/**\n * Abstract Top level Execution Unit that wraps lower level functional units to make a\n * multi function execution unit.\n *\n * @param readsIrf does this exe unit need a integer regfile port\n * @param writesIrf does this exe unit need a integer regfile port\n * @param readsFrf does this exe unit need a integer regfile port\n * @param writesFrf does this exe unit need a integer regfile port\n * @param writesLlIrf does this exe unit need a integer regfile port\n * @param writesLlFrf does this exe unit need a integer regfile port\n * @param numBypassStages number of bypass ports for the exe unit\n * @param dataWidth width of the data coming out of the exe unit\n * @param bypassable is the exe unit able to be bypassed\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasAlu does the exe unit have a alu\n * @param hasFpu does the exe unit have a fpu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nabstract class ExecutionUnit(\n val readsIrf : Boolean = false,\n val writesIrf : Boolean = false,\n val readsFrf : Boolean = false,\n val writesFrf : Boolean = false,\n val writesLlIrf : Boolean = false,\n val writesLlFrf : Boolean = false,\n val numBypassStages : Int,\n val dataWidth : Int,\n val bypassable : Boolean = false, // TODO make override def for code clarity\n val alwaysBypassable : Boolean = false,\n val hasMem : Boolean = false,\n val hasCSR : Boolean = false,\n val hasJmpUnit : Boolean = false,\n val hasAlu : Boolean = false,\n val hasFpu : Boolean = false,\n val hasMul : Boolean = false,\n val hasDiv : Boolean = false,\n val hasFdiv : Boolean = false,\n val hasIfpu : Boolean = false,\n val hasFpiu : Boolean = false,\n val hasRocc : Boolean = false\n )(implicit p: Parameters) extends BoomModule\n{\n\n val io = IO(new Bundle {\n val fu_types = Output(Bits(FUC_SZ.W))\n\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n\n val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n val brupdate = Input(new BrUpdateInfo())\n\n\n // only used by the rocc unit\n val rocc = if (hasRocc) new RoCCShimCoreIO else null\n\n // only used by the branch unit\n val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n\n // only used by the fpu unit\n val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by the mem unit\n val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null\n val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null\n\n // TODO move this out of ExecutionUnit\n val com_exception = if (hasMem || hasRocc) Input(Bool()) else null\n })\n\n io.req.ready := false.B\n\n if (writesIrf) {\n io.iresp.valid := false.B\n io.iresp.bits := DontCare\n io.iresp.bits.fflags.valid := false.B\n io.iresp.bits.predicated := false.B\n assert(io.iresp.ready)\n }\n if (writesLlIrf) {\n io.ll_iresp.valid := false.B\n io.ll_iresp.bits := DontCare\n io.ll_iresp.bits.fflags.valid := false.B\n io.ll_iresp.bits.predicated := false.B\n }\n if (writesFrf) {\n io.fresp.valid := false.B\n io.fresp.bits := DontCare\n io.fresp.bits.fflags.valid := false.B\n io.fresp.bits.predicated := false.B\n assert(io.fresp.ready)\n }\n if (writesLlFrf) {\n io.ll_fresp.valid := false.B\n io.ll_fresp.bits := DontCare\n io.ll_fresp.bits.fflags.valid := false.B\n io.ll_fresp.bits.predicated := false.B\n }\n\n // TODO add \"number of fflag ports\", so we can properly account for FPU+Mem combinations\n def hasFFlags : Boolean = hasFpu || hasFdiv\n\n require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),\n \"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.\")\n def hasFcsr = hasIfpu || hasFpu || hasFdiv\n\n require (bypassable || !alwaysBypassable,\n \"[execute] an execution unit must be bypassable if it is always bypassable\")\n\n def supportedFuncUnits = {\n new SupportedFuncUnits(\n alu = hasAlu,\n jmp = hasJmpUnit,\n mem = hasMem,\n muld = hasMul || hasDiv,\n fpu = hasFpu,\n csr = hasCSR,\n fdiv = hasFdiv,\n ifpu = hasIfpu)\n }\n}\n\n/**\n * ALU execution unit that can have a branch, alu, mul, div, int to FP,\n * and memory unit.\n *\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasAlu does the exe unit have a alu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n */\nclass ALUExeUnit(\n hasJmpUnit : Boolean = false,\n hasCSR : Boolean = false,\n hasAlu : Boolean = true,\n hasMul : Boolean = false,\n hasDiv : Boolean = false,\n hasIfpu : Boolean = false,\n hasMem : Boolean = false,\n hasRocc : Boolean = false)\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsIrf = true,\n writesIrf = hasAlu || hasMul || hasDiv,\n writesLlIrf = hasMem || hasRocc,\n writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,\n numBypassStages =\n if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency\n else if (hasAlu) 1 else 0,\n dataWidth = 64 + 1,\n bypassable = hasAlu,\n alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),\n hasCSR = hasCSR,\n hasJmpUnit = hasJmpUnit,\n hasAlu = hasAlu,\n hasMul = hasMul,\n hasDiv = hasDiv,\n hasIfpu = hasIfpu,\n hasMem = hasMem,\n hasRocc = hasRocc)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n require(!(hasRocc && !hasCSR),\n \"RoCC needs to be shared with CSR unit\")\n require(!(hasMem && hasRocc),\n \"We do not support execution unit with both Mem and Rocc writebacks\")\n require(!(hasMem && hasIfpu),\n \"TODO. Currently do not support AluMemExeUnit with FP\")\n\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\") +\n (if (hasAlu) BoomCoreStringPrefix(\" - ALU\") else \"\") +\n (if (hasMul) BoomCoreStringPrefix(\" - Mul\") else \"\") +\n (if (hasDiv) BoomCoreStringPrefix(\" - Div\") else \"\") +\n (if (hasIfpu) BoomCoreStringPrefix(\" - IFPU\") else \"\") +\n (if (hasMem) BoomCoreStringPrefix(\" - Mem\") else \"\") +\n (if (hasRocc) BoomCoreStringPrefix(\" - RoCC\") else \"\")\n\n override def toString: String = out_str.toString\n\n val div_busy = WireInit(false.B)\n val ifpu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n // Specifically the functional units with fast writeback to IRF\n val iresp_fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |\n Mux(hasMul.B, FU_MUL, 0.U) |\n Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |\n Mux(hasCSR.B, FU_CSR, 0.U) |\n Mux(hasJmpUnit.B, FU_JMP, 0.U) |\n Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |\n Mux(hasMem.B, FU_MEM, 0.U)\n\n // ALU Unit -------------------------------\n var alu: ALUUnit = null\n if (hasAlu) {\n alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,\n numStages = numBypassStages,\n dataWidth = xLen))\n alu.io.req.valid := (\n io.req.valid &&\n (io.req.bits.uop.fu_code === FU_ALU ||\n io.req.bits.uop.fu_code === FU_JMP ||\n (io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))\n //ROCC Rocc Commands are taken by the RoCC unit\n\n alu.io.req.bits.uop := io.req.bits.uop\n alu.io.req.bits.kill := io.req.bits.kill\n alu.io.req.bits.rs1_data := io.req.bits.rs1_data\n alu.io.req.bits.rs2_data := io.req.bits.rs2_data\n alu.io.req.bits.rs3_data := DontCare\n alu.io.req.bits.pred_data := io.req.bits.pred_data\n alu.io.resp.ready := DontCare\n alu.io.brupdate := io.brupdate\n\n iresp_fu_units += alu\n\n // Bypassing only applies to ALU\n io.bypass := alu.io.bypass\n\n // branch unit is embedded inside the ALU\n io.brinfo := alu.io.brinfo\n if (hasJmpUnit) {\n alu.io.get_ftq_pc <> io.get_ftq_pc\n }\n }\n\n var rocc: RoCCShim = null\n if (hasRocc) {\n rocc = Module(new RoCCShim)\n rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC\n rocc.io.req.bits := DontCare\n rocc.io.req.bits.uop := io.req.bits.uop\n rocc.io.req.bits.kill := io.req.bits.kill\n rocc.io.req.bits.rs1_data := io.req.bits.rs1_data\n rocc.io.req.bits.rs2_data := io.req.bits.rs2_data\n rocc.io.brupdate := io.brupdate // We should assert on this somewhere\n rocc.io.status := io.status\n rocc.io.exception := io.com_exception\n io.rocc <> rocc.io.core\n\n rocc.io.resp.ready := io.ll_iresp.ready\n io.ll_iresp.valid := rocc.io.resp.valid\n io.ll_iresp.bits.uop := rocc.io.resp.bits.uop\n io.ll_iresp.bits.data := rocc.io.resp.bits.data\n }\n\n\n // Pipelined, IMul Unit ------------------\n var imul: PipelinedMulUnit = null\n if (hasMul) {\n imul = Module(new PipelinedMulUnit(imulLatency, xLen))\n imul.io <> DontCare\n imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)\n imul.io.req.bits.uop := io.req.bits.uop\n imul.io.req.bits.rs1_data := io.req.bits.rs1_data\n imul.io.req.bits.rs2_data := io.req.bits.rs2_data\n imul.io.req.bits.kill := io.req.bits.kill\n imul.io.brupdate := io.brupdate\n iresp_fu_units += imul\n }\n\n var ifpu: IntToFPUnit = null\n if (hasIfpu) {\n ifpu = Module(new IntToFPUnit(latency=intToFpLatency))\n ifpu.io.req <> io.req\n ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)\n ifpu.io.fcsr_rm := io.fcsr_rm\n ifpu.io.brupdate <> io.brupdate\n ifpu.io.resp.ready := DontCare\n\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = intToFpLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := ifpu.io.resp.valid\n queue.io.enq.bits.uop := ifpu.io.resp.bits.uop\n queue.io.enq.bits.data := ifpu.io.resp.bits.data\n queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n io.ll_fresp <> queue.io.deq\n ifpu_busy := !(queue.io.empty)\n assert (queue.io.enq.ready)\n }\n\n // Div/Rem Unit -----------------------\n var div: DivUnit = null\n val div_resp_val = WireInit(false.B)\n if (hasDiv) {\n div = Module(new DivUnit(xLen))\n div.io <> DontCare\n div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B\n div.io.req.bits.uop := io.req.bits.uop\n div.io.req.bits.rs1_data := io.req.bits.rs1_data\n div.io.req.bits.rs2_data := io.req.bits.rs2_data\n div.io.brupdate := io.brupdate\n div.io.req.bits.kill := io.req.bits.kill\n\n // share write port with the pipelined units\n div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))\n\n div_resp_val := div.io.resp.valid\n div_busy := !div.io.req.ready ||\n (io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))\n\n iresp_fu_units += div\n }\n\n // Mem Unit --------------------------\n if (hasMem) {\n require(!hasAlu)\n val maddrcalc = Module(new MemAddrCalcUnit)\n maddrcalc.io.req <> io.req\n maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)\n maddrcalc.io.brupdate <> io.brupdate\n maddrcalc.io.status := io.status\n maddrcalc.io.bp := io.bp\n maddrcalc.io.mcontext := io.mcontext\n maddrcalc.io.scontext := io.scontext\n maddrcalc.io.resp.ready := DontCare\n require(numBypassStages == 0)\n\n io.lsu_io.req := maddrcalc.io.resp\n\n io.ll_iresp <> io.lsu_io.iresp\n if (usingFPU) {\n io.ll_fresp <> io.lsu_io.fresp\n }\n }\n\n // Outputs (Write Port #0) ---------------\n if (writesIrf) {\n io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)\n io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.uop)).toSeq)\n io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)\n\n // pulled out for critical path reasons\n // TODO: Does this make sense as part of the iresp bundle?\n if (hasAlu) {\n io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt\n io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd\n }\n }\n\n assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n (PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),\n \"Multiple functional units are fighting over the write port.\")\n}\n\n/**\n * FPU-only unit, with optional second write-port for ToInt micro-ops.\n *\n * @param hasFpu does the exe unit have a fpu\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nclass FPUExeUnit(\n hasFpu : Boolean = true,\n hasFdiv : Boolean = false,\n hasFpiu : Boolean = false\n )\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsFrf = true,\n writesFrf = true,\n writesLlIrf = hasFpiu,\n writesIrf = false,\n numBypassStages = 0,\n dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,\n bypassable = false,\n hasFpu = hasFpu,\n hasFdiv = hasFdiv,\n hasFpiu = hasFpiu) with tile.HasFPUParameters\n{\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\")\n (if (hasFpu) BoomCoreStringPrefix(\"- FPU (Latency: \" + dfmaLatency + \")\") else \"\") +\n (if (hasFdiv) BoomCoreStringPrefix(\"- FDiv/FSqrt\") else \"\") +\n (if (hasFpiu) BoomCoreStringPrefix(\"- FPIU (writes to Integer RF)\") else \"\")\n\n val fdiv_busy = WireInit(false.B)\n val fpiu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n val fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |\n Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |\n Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)\n\n // FPU Unit -----------------------\n var fpu: FPUUnit = null\n val fpu_resp_val = WireInit(false.B)\n val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fpu_resp_fflags.valid := false.B\n if (hasFpu) {\n fpu = Module(new FPUUnit())\n fpu.io.req.valid := io.req.valid &&\n (io.req.bits.uop.fu_code_is(FU_FPU) ||\n io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.pred_data := false.B\n fpu.io.req.bits.kill := io.req.bits.kill\n fpu.io.fcsr_rm := io.fcsr_rm\n fpu.io.brupdate := io.brupdate\n fpu.io.resp.ready := DontCare\n fpu_resp_val := fpu.io.resp.valid\n fpu_resp_fflags := fpu.io.resp.bits.fflags\n\n fu_units += fpu\n }\n\n // FDiv/FSqrt Unit -----------------------\n var fdivsqrt: FDivSqrtUnit = null\n val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fdiv_resp_fflags := DontCare\n fdiv_resp_fflags.valid := false.B\n if (hasFdiv) {\n fdivsqrt = Module(new FDivSqrtUnit())\n fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)\n fdivsqrt.io.req.bits.uop := io.req.bits.uop\n fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data\n fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data\n fdivsqrt.io.req.bits.rs3_data := DontCare\n fdivsqrt.io.req.bits.pred_data := false.B\n fdivsqrt.io.req.bits.kill := io.req.bits.kill\n fdivsqrt.io.fcsr_rm := io.fcsr_rm\n fdivsqrt.io.brupdate := io.brupdate\n\n // share write port with the pipelined units\n fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.\n\n fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))\n\n fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags\n\n fu_units += fdivsqrt\n }\n\n // Outputs (Write Port #0) ---------------\n\n io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&\n !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))\n io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,\n f.io.resp.bits.uop)).toSeq)\n io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)\n\n // Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------\n\n if (hasFpiu) {\n // TODO instantiate our own fpiu; and remove it from fpu.scala.\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = dfmaLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := (fpu.io.resp.valid &&\n fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&\n fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point\n queue.io.enq.bits.uop := fpu.io.resp.bits.uop\n queue.io.enq.bits.data := fpu.io.resp.bits.data\n queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.\n\n val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = 3)) // Lets us backpressure floating point store data\n fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n fp_sdq.io.enq.bits.uop := io.req.bits.uop\n fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)\n fp_sdq.io.enq.bits.predicated := false.B\n fp_sdq.io.enq.bits.fflags := DontCare\n fp_sdq.io.brupdate := io.brupdate\n fp_sdq.io.flush := io.req.bits.kill\n\n assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))\n\n val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))\n resp_arb.io.in(0) <> queue.io.deq\n resp_arb.io.in(1) <> fp_sdq.io.deq\n io.ll_iresp <> resp_arb.io.out\n\n fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)\n }\n\n override def toString: String = out_str.toString\n}", + "response": "module FPUExeUnit(\n input clock,\n input reset,\n output [9:0] io_fu_types,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_iw_p1_poisoned,\n input io_req_bits_uop_iw_p2_poisoned,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [64:0] io_req_bits_rs1_data,\n input [64:0] io_req_bits_rs2_data,\n input [64:0] io_req_bits_rs3_data,\n input io_req_bits_kill,\n output io_fresp_valid,\n output [4:0] io_fresp_bits_uop_rob_idx,\n output [5:0] io_fresp_bits_uop_pdst,\n output io_fresp_bits_uop_is_amo,\n output io_fresp_bits_uop_uses_ldq,\n output io_fresp_bits_uop_uses_stq,\n output [1:0] io_fresp_bits_uop_dst_rtype,\n output io_fresp_bits_uop_fp_val,\n output [64:0] io_fresp_bits_data,\n output io_fresp_bits_fflags_valid,\n output [4:0] io_fresp_bits_fflags_bits_uop_rob_idx,\n output [4:0] io_fresp_bits_fflags_bits_flags,\n input io_ll_iresp_ready,\n output io_ll_iresp_valid,\n output [6:0] io_ll_iresp_bits_uop_uopc,\n output [7:0] io_ll_iresp_bits_uop_br_mask,\n output [4:0] io_ll_iresp_bits_uop_rob_idx,\n output [2:0] io_ll_iresp_bits_uop_stq_idx,\n output [5:0] io_ll_iresp_bits_uop_pdst,\n output io_ll_iresp_bits_uop_is_amo,\n output io_ll_iresp_bits_uop_uses_stq,\n output [1:0] io_ll_iresp_bits_uop_dst_rtype,\n output [64:0] io_ll_iresp_bits_data,\n output io_ll_iresp_bits_predicated,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input [2:0] io_fcsr_rm\n);\n\n wire _fpiu_busy_T;\n wire fdiv_busy;\n wire _resp_arb_io_in_0_ready;\n wire _resp_arb_io_in_1_ready;\n wire _fp_sdq_io_enq_ready;\n wire _fp_sdq_io_deq_valid;\n wire [6:0] _fp_sdq_io_deq_bits_uop_uopc;\n wire [7:0] _fp_sdq_io_deq_bits_uop_br_mask;\n wire [4:0] _fp_sdq_io_deq_bits_uop_rob_idx;\n wire [2:0] _fp_sdq_io_deq_bits_uop_stq_idx;\n wire [5:0] _fp_sdq_io_deq_bits_uop_pdst;\n wire _fp_sdq_io_deq_bits_uop_is_amo;\n wire _fp_sdq_io_deq_bits_uop_uses_stq;\n wire [1:0] _fp_sdq_io_deq_bits_uop_dst_rtype;\n wire _fp_sdq_io_deq_bits_uop_fp_val;\n wire [64:0] _fp_sdq_io_deq_bits_data;\n wire _fp_sdq_io_deq_bits_predicated;\n wire _fp_sdq_io_deq_bits_fflags_valid;\n wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx;\n wire [4:0] _fp_sdq_io_deq_bits_fflags_bits_flags;\n wire _fp_sdq_io_empty;\n wire _queue_io_enq_ready;\n wire _queue_io_deq_valid;\n wire [6:0] _queue_io_deq_bits_uop_uopc;\n wire [7:0] _queue_io_deq_bits_uop_br_mask;\n wire [4:0] _queue_io_deq_bits_uop_rob_idx;\n wire [2:0] _queue_io_deq_bits_uop_stq_idx;\n wire [5:0] _queue_io_deq_bits_uop_pdst;\n wire _queue_io_deq_bits_uop_is_amo;\n wire _queue_io_deq_bits_uop_uses_stq;\n wire [1:0] _queue_io_deq_bits_uop_dst_rtype;\n wire _queue_io_deq_bits_uop_fp_val;\n wire [64:0] _queue_io_deq_bits_data;\n wire _queue_io_deq_bits_predicated;\n wire _queue_io_deq_bits_fflags_valid;\n wire [4:0] _queue_io_deq_bits_fflags_bits_uop_rob_idx;\n wire [4:0] _queue_io_deq_bits_fflags_bits_flags;\n wire _queue_io_empty;\n wire _FDivSqrtUnit_io_req_ready;\n wire _FDivSqrtUnit_io_resp_valid;\n wire [4:0] _FDivSqrtUnit_io_resp_bits_uop_rob_idx;\n wire [5:0] _FDivSqrtUnit_io_resp_bits_uop_pdst;\n wire _FDivSqrtUnit_io_resp_bits_uop_is_amo;\n wire _FDivSqrtUnit_io_resp_bits_uop_uses_ldq;\n wire _FDivSqrtUnit_io_resp_bits_uop_uses_stq;\n wire [1:0] _FDivSqrtUnit_io_resp_bits_uop_dst_rtype;\n wire _FDivSqrtUnit_io_resp_bits_uop_fp_val;\n wire [64:0] _FDivSqrtUnit_io_resp_bits_data;\n wire _FDivSqrtUnit_io_resp_bits_fflags_valid;\n wire [4:0] _FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx;\n wire [4:0] _FDivSqrtUnit_io_resp_bits_fflags_bits_flags;\n wire _FPUUnit_io_resp_valid;\n wire [6:0] _FPUUnit_io_resp_bits_uop_uopc;\n wire [31:0] _FPUUnit_io_resp_bits_uop_inst;\n wire [31:0] _FPUUnit_io_resp_bits_uop_debug_inst;\n wire _FPUUnit_io_resp_bits_uop_is_rvc;\n wire [39:0] _FPUUnit_io_resp_bits_uop_debug_pc;\n wire [2:0] _FPUUnit_io_resp_bits_uop_iq_type;\n wire [9:0] _FPUUnit_io_resp_bits_uop_fu_code;\n wire [3:0] _FPUUnit_io_resp_bits_uop_ctrl_br_type;\n wire [1:0] _FPUUnit_io_resp_bits_uop_ctrl_op1_sel;\n wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_op2_sel;\n wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_imm_sel;\n wire [4:0] _FPUUnit_io_resp_bits_uop_ctrl_op_fcn;\n wire _FPUUnit_io_resp_bits_uop_ctrl_fcn_dw;\n wire [2:0] _FPUUnit_io_resp_bits_uop_ctrl_csr_cmd;\n wire _FPUUnit_io_resp_bits_uop_ctrl_is_load;\n wire _FPUUnit_io_resp_bits_uop_ctrl_is_sta;\n wire _FPUUnit_io_resp_bits_uop_ctrl_is_std;\n wire [1:0] _FPUUnit_io_resp_bits_uop_iw_state;\n wire _FPUUnit_io_resp_bits_uop_iw_p1_poisoned;\n wire _FPUUnit_io_resp_bits_uop_iw_p2_poisoned;\n wire _FPUUnit_io_resp_bits_uop_is_br;\n wire _FPUUnit_io_resp_bits_uop_is_jalr;\n wire _FPUUnit_io_resp_bits_uop_is_jal;\n wire _FPUUnit_io_resp_bits_uop_is_sfb;\n wire [7:0] _FPUUnit_io_resp_bits_uop_br_mask;\n wire [2:0] _FPUUnit_io_resp_bits_uop_br_tag;\n wire [3:0] _FPUUnit_io_resp_bits_uop_ftq_idx;\n wire _FPUUnit_io_resp_bits_uop_edge_inst;\n wire [5:0] _FPUUnit_io_resp_bits_uop_pc_lob;\n wire _FPUUnit_io_resp_bits_uop_taken;\n wire [19:0] _FPUUnit_io_resp_bits_uop_imm_packed;\n wire [11:0] _FPUUnit_io_resp_bits_uop_csr_addr;\n wire [4:0] _FPUUnit_io_resp_bits_uop_rob_idx;\n wire [2:0] _FPUUnit_io_resp_bits_uop_ldq_idx;\n wire [2:0] _FPUUnit_io_resp_bits_uop_stq_idx;\n wire [1:0] _FPUUnit_io_resp_bits_uop_rxq_idx;\n wire [5:0] _FPUUnit_io_resp_bits_uop_pdst;\n wire [5:0] _FPUUnit_io_resp_bits_uop_prs1;\n wire [5:0] _FPUUnit_io_resp_bits_uop_prs2;\n wire [5:0] _FPUUnit_io_resp_bits_uop_prs3;\n wire [3:0] _FPUUnit_io_resp_bits_uop_ppred;\n wire _FPUUnit_io_resp_bits_uop_prs1_busy;\n wire _FPUUnit_io_resp_bits_uop_prs2_busy;\n wire _FPUUnit_io_resp_bits_uop_prs3_busy;\n wire _FPUUnit_io_resp_bits_uop_ppred_busy;\n wire [5:0] _FPUUnit_io_resp_bits_uop_stale_pdst;\n wire _FPUUnit_io_resp_bits_uop_exception;\n wire [63:0] _FPUUnit_io_resp_bits_uop_exc_cause;\n wire _FPUUnit_io_resp_bits_uop_bypassable;\n wire [4:0] _FPUUnit_io_resp_bits_uop_mem_cmd;\n wire [1:0] _FPUUnit_io_resp_bits_uop_mem_size;\n wire _FPUUnit_io_resp_bits_uop_mem_signed;\n wire _FPUUnit_io_resp_bits_uop_is_fence;\n wire _FPUUnit_io_resp_bits_uop_is_fencei;\n wire _FPUUnit_io_resp_bits_uop_is_amo;\n wire _FPUUnit_io_resp_bits_uop_uses_ldq;\n wire _FPUUnit_io_resp_bits_uop_uses_stq;\n wire _FPUUnit_io_resp_bits_uop_is_sys_pc2epc;\n wire _FPUUnit_io_resp_bits_uop_is_unique;\n wire _FPUUnit_io_resp_bits_uop_flush_on_commit;\n wire _FPUUnit_io_resp_bits_uop_ldst_is_rs1;\n wire [5:0] _FPUUnit_io_resp_bits_uop_ldst;\n wire [5:0] _FPUUnit_io_resp_bits_uop_lrs1;\n wire [5:0] _FPUUnit_io_resp_bits_uop_lrs2;\n wire [5:0] _FPUUnit_io_resp_bits_uop_lrs3;\n wire _FPUUnit_io_resp_bits_uop_ldst_val;\n wire [1:0] _FPUUnit_io_resp_bits_uop_dst_rtype;\n wire [1:0] _FPUUnit_io_resp_bits_uop_lrs1_rtype;\n wire [1:0] _FPUUnit_io_resp_bits_uop_lrs2_rtype;\n wire _FPUUnit_io_resp_bits_uop_frs3_en;\n wire _FPUUnit_io_resp_bits_uop_fp_val;\n wire _FPUUnit_io_resp_bits_uop_fp_single;\n wire _FPUUnit_io_resp_bits_uop_xcpt_pf_if;\n wire _FPUUnit_io_resp_bits_uop_xcpt_ae_if;\n wire _FPUUnit_io_resp_bits_uop_xcpt_ma_if;\n wire _FPUUnit_io_resp_bits_uop_bp_debug_if;\n wire _FPUUnit_io_resp_bits_uop_bp_xcpt_if;\n wire [1:0] _FPUUnit_io_resp_bits_uop_debug_fsrc;\n wire [1:0] _FPUUnit_io_resp_bits_uop_debug_tsrc;\n wire [64:0] _FPUUnit_io_resp_bits_data;\n wire _FPUUnit_io_resp_bits_fflags_valid;\n wire [6:0] _FPUUnit_io_resp_bits_fflags_bits_uop_uopc;\n wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_inst;\n wire [31:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc;\n wire [39:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iq_type;\n wire [9:0] _FPUUnit_io_resp_bits_fflags_bits_uop_fu_code;\n wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel;\n wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_iw_state;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_br;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_jal;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb;\n wire [7:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_mask;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_br_tag;\n wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_taken;\n wire [19:0] _FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed;\n wire [11:0] _FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr;\n wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx;\n wire [2:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_pdst;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs1;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs2;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_prs3;\n wire [3:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ppred;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_exception;\n wire [63:0] _FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_bypassable;\n wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_mem_size;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fence;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_amo;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_is_unique;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_ldst;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2;\n wire [5:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs3;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_val;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_fp_single;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if;\n wire _FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc;\n wire [1:0] _FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc;\n wire [4:0] _FPUUnit_io_resp_bits_fflags_bits_flags;\n assign fdiv_busy = ~_FDivSqrtUnit_io_req_ready | io_req_valid & io_req_bits_uop_fu_code[7];\n wire fp_sdq_io_enq_valid = io_req_valid & io_req_bits_uop_uopc == 7'h2 & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0;\n wire fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf = (&(io_req_bits_rs2_data[63:62])) & ~(io_req_bits_rs2_data[61]);\n wire fp_sdq_io_enq_bits_data_unrecoded_isSubnormal = $signed({1'h0, io_req_bits_rs2_data[63:52]}) < 13'sh402;\n wire [52:0] _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1 = {1'h0, |(io_req_bits_rs2_data[63:61]), io_req_bits_rs2_data[51:1]} >> 6'h1 - io_req_bits_rs2_data[57:52];\n wire [51:0] fp_sdq_io_enq_bits_data_unrecoded_fractOut = fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? _fp_sdq_io_enq_bits_data_unrecoded_denormFract_T_1[51:0] : fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf ? 52'h0 : io_req_bits_rs2_data[51:0];\n wire [1:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T = {io_req_bits_rs2_data[52], io_req_bits_rs2_data[30]};\n wire fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf = (&_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T) & ~(io_req_bits_rs2_data[29]);\n wire fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal = $signed({1'h0, io_req_bits_rs2_data[52], io_req_bits_rs2_data[30:23]}) < 10'sh82;\n wire [23:0] _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1 = {1'h0, |{io_req_bits_rs2_data[52], io_req_bits_rs2_data[30:29]}, io_req_bits_rs2_data[22:1]} >> 5'h1 - io_req_bits_rs2_data[27:23];\n assign _fpiu_busy_T = _queue_io_empty & _fp_sdq_io_empty;\n FPUUnit FPUUnit (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid & (|{io_req_bits_uop_fu_code[6], io_req_bits_uop_fu_code[9]})),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_inst (io_req_bits_uop_inst),\n .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst),\n .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),\n .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc),\n .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type),\n .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code),\n .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),\n .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),\n .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),\n .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),\n .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),\n .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),\n .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),\n .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state),\n .io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned),\n .io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned),\n .io_req_bits_uop_is_br (io_req_bits_uop_is_br),\n .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),\n .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),\n .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),\n .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),\n .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),\n .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),\n .io_req_bits_uop_taken (io_req_bits_uop_taken),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),\n .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),\n .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_prs1 (io_req_bits_uop_prs1),\n .io_req_bits_uop_prs2 (io_req_bits_uop_prs2),\n .io_req_bits_uop_prs3 (io_req_bits_uop_prs3),\n .io_req_bits_uop_ppred (io_req_bits_uop_ppred),\n .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),\n .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),\n .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),\n .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),\n .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),\n .io_req_bits_uop_exception (io_req_bits_uop_exception),\n .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),\n .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size),\n .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed),\n .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence),\n .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),\n .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique),\n .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),\n .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),\n .io_req_bits_uop_ldst (io_req_bits_uop_ldst),\n .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1),\n .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2),\n .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3),\n .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),\n .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),\n .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en),\n .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),\n .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single),\n .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),\n .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),\n .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),\n .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),\n .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),\n .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),\n .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),\n .io_req_bits_rs1_data (io_req_bits_rs1_data),\n .io_req_bits_rs2_data (io_req_bits_rs2_data),\n .io_req_bits_rs3_data (io_req_bits_rs3_data),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_valid (_FPUUnit_io_resp_valid),\n .io_resp_bits_uop_uopc (_FPUUnit_io_resp_bits_uop_uopc),\n .io_resp_bits_uop_inst (_FPUUnit_io_resp_bits_uop_inst),\n .io_resp_bits_uop_debug_inst (_FPUUnit_io_resp_bits_uop_debug_inst),\n .io_resp_bits_uop_is_rvc (_FPUUnit_io_resp_bits_uop_is_rvc),\n .io_resp_bits_uop_debug_pc (_FPUUnit_io_resp_bits_uop_debug_pc),\n .io_resp_bits_uop_iq_type (_FPUUnit_io_resp_bits_uop_iq_type),\n .io_resp_bits_uop_fu_code (_FPUUnit_io_resp_bits_uop_fu_code),\n .io_resp_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_uop_ctrl_br_type),\n .io_resp_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_uop_ctrl_op1_sel),\n .io_resp_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_uop_ctrl_op2_sel),\n .io_resp_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_uop_ctrl_imm_sel),\n .io_resp_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_uop_ctrl_op_fcn),\n .io_resp_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_uop_ctrl_fcn_dw),\n .io_resp_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_uop_ctrl_is_load),\n .io_resp_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_uop_ctrl_is_sta),\n .io_resp_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_uop_ctrl_is_std),\n .io_resp_bits_uop_iw_state (_FPUUnit_io_resp_bits_uop_iw_state),\n .io_resp_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_uop_iw_p1_poisoned),\n .io_resp_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_uop_iw_p2_poisoned),\n .io_resp_bits_uop_is_br (_FPUUnit_io_resp_bits_uop_is_br),\n .io_resp_bits_uop_is_jalr (_FPUUnit_io_resp_bits_uop_is_jalr),\n .io_resp_bits_uop_is_jal (_FPUUnit_io_resp_bits_uop_is_jal),\n .io_resp_bits_uop_is_sfb (_FPUUnit_io_resp_bits_uop_is_sfb),\n .io_resp_bits_uop_br_mask (_FPUUnit_io_resp_bits_uop_br_mask),\n .io_resp_bits_uop_br_tag (_FPUUnit_io_resp_bits_uop_br_tag),\n .io_resp_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_uop_ftq_idx),\n .io_resp_bits_uop_edge_inst (_FPUUnit_io_resp_bits_uop_edge_inst),\n .io_resp_bits_uop_pc_lob (_FPUUnit_io_resp_bits_uop_pc_lob),\n .io_resp_bits_uop_taken (_FPUUnit_io_resp_bits_uop_taken),\n .io_resp_bits_uop_imm_packed (_FPUUnit_io_resp_bits_uop_imm_packed),\n .io_resp_bits_uop_csr_addr (_FPUUnit_io_resp_bits_uop_csr_addr),\n .io_resp_bits_uop_rob_idx (_FPUUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_uop_ldq_idx),\n .io_resp_bits_uop_stq_idx (_FPUUnit_io_resp_bits_uop_stq_idx),\n .io_resp_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_uop_rxq_idx),\n .io_resp_bits_uop_pdst (_FPUUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_prs1 (_FPUUnit_io_resp_bits_uop_prs1),\n .io_resp_bits_uop_prs2 (_FPUUnit_io_resp_bits_uop_prs2),\n .io_resp_bits_uop_prs3 (_FPUUnit_io_resp_bits_uop_prs3),\n .io_resp_bits_uop_ppred (_FPUUnit_io_resp_bits_uop_ppred),\n .io_resp_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_uop_prs1_busy),\n .io_resp_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_uop_prs2_busy),\n .io_resp_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_uop_prs3_busy),\n .io_resp_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_uop_ppred_busy),\n .io_resp_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_uop_stale_pdst),\n .io_resp_bits_uop_exception (_FPUUnit_io_resp_bits_uop_exception),\n .io_resp_bits_uop_exc_cause (_FPUUnit_io_resp_bits_uop_exc_cause),\n .io_resp_bits_uop_bypassable (_FPUUnit_io_resp_bits_uop_bypassable),\n .io_resp_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_uop_mem_cmd),\n .io_resp_bits_uop_mem_size (_FPUUnit_io_resp_bits_uop_mem_size),\n .io_resp_bits_uop_mem_signed (_FPUUnit_io_resp_bits_uop_mem_signed),\n .io_resp_bits_uop_is_fence (_FPUUnit_io_resp_bits_uop_is_fence),\n .io_resp_bits_uop_is_fencei (_FPUUnit_io_resp_bits_uop_is_fencei),\n .io_resp_bits_uop_is_amo (_FPUUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_uop_uses_ldq),\n .io_resp_bits_uop_uses_stq (_FPUUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_uop_is_sys_pc2epc),\n .io_resp_bits_uop_is_unique (_FPUUnit_io_resp_bits_uop_is_unique),\n .io_resp_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_uop_flush_on_commit),\n .io_resp_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_uop_ldst_is_rs1),\n .io_resp_bits_uop_ldst (_FPUUnit_io_resp_bits_uop_ldst),\n .io_resp_bits_uop_lrs1 (_FPUUnit_io_resp_bits_uop_lrs1),\n .io_resp_bits_uop_lrs2 (_FPUUnit_io_resp_bits_uop_lrs2),\n .io_resp_bits_uop_lrs3 (_FPUUnit_io_resp_bits_uop_lrs3),\n .io_resp_bits_uop_ldst_val (_FPUUnit_io_resp_bits_uop_ldst_val),\n .io_resp_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_uop_lrs1_rtype),\n .io_resp_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_uop_lrs2_rtype),\n .io_resp_bits_uop_frs3_en (_FPUUnit_io_resp_bits_uop_frs3_en),\n .io_resp_bits_uop_fp_val (_FPUUnit_io_resp_bits_uop_fp_val),\n .io_resp_bits_uop_fp_single (_FPUUnit_io_resp_bits_uop_fp_single),\n .io_resp_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_uop_xcpt_pf_if),\n .io_resp_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_uop_xcpt_ae_if),\n .io_resp_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_uop_xcpt_ma_if),\n .io_resp_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_uop_bp_debug_if),\n .io_resp_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_uop_bp_xcpt_if),\n .io_resp_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_uop_debug_fsrc),\n .io_resp_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_uop_debug_tsrc),\n .io_resp_bits_data (_FPUUnit_io_resp_bits_data),\n .io_resp_bits_fflags_valid (_FPUUnit_io_resp_bits_fflags_valid),\n .io_resp_bits_fflags_bits_uop_uopc (_FPUUnit_io_resp_bits_fflags_bits_uop_uopc),\n .io_resp_bits_fflags_bits_uop_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_inst),\n .io_resp_bits_fflags_bits_uop_debug_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst),\n .io_resp_bits_fflags_bits_uop_is_rvc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc),\n .io_resp_bits_fflags_bits_uop_debug_pc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc),\n .io_resp_bits_fflags_bits_uop_iq_type (_FPUUnit_io_resp_bits_fflags_bits_uop_iq_type),\n .io_resp_bits_fflags_bits_uop_fu_code (_FPUUnit_io_resp_bits_fflags_bits_uop_fu_code),\n .io_resp_bits_fflags_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),\n .io_resp_bits_fflags_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),\n .io_resp_bits_fflags_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),\n .io_resp_bits_fflags_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_fflags_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),\n .io_resp_bits_fflags_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),\n .io_resp_bits_fflags_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),\n .io_resp_bits_fflags_bits_uop_iw_state (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_state),\n .io_resp_bits_fflags_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),\n .io_resp_bits_fflags_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),\n .io_resp_bits_fflags_bits_uop_is_br (_FPUUnit_io_resp_bits_fflags_bits_uop_is_br),\n .io_resp_bits_fflags_bits_uop_is_jalr (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr),\n .io_resp_bits_fflags_bits_uop_is_jal (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jal),\n .io_resp_bits_fflags_bits_uop_is_sfb (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb),\n .io_resp_bits_fflags_bits_uop_br_mask (_FPUUnit_io_resp_bits_fflags_bits_uop_br_mask),\n .io_resp_bits_fflags_bits_uop_br_tag (_FPUUnit_io_resp_bits_fflags_bits_uop_br_tag),\n .io_resp_bits_fflags_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx),\n .io_resp_bits_fflags_bits_uop_edge_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst),\n .io_resp_bits_fflags_bits_uop_pc_lob (_FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob),\n .io_resp_bits_fflags_bits_uop_taken (_FPUUnit_io_resp_bits_fflags_bits_uop_taken),\n .io_resp_bits_fflags_bits_uop_imm_packed (_FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed),\n .io_resp_bits_fflags_bits_uop_csr_addr (_FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr),\n .io_resp_bits_fflags_bits_uop_rob_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx),\n .io_resp_bits_fflags_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx),\n .io_resp_bits_fflags_bits_uop_stq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx),\n .io_resp_bits_fflags_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx),\n .io_resp_bits_fflags_bits_uop_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_pdst),\n .io_resp_bits_fflags_bits_uop_prs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1),\n .io_resp_bits_fflags_bits_uop_prs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2),\n .io_resp_bits_fflags_bits_uop_prs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3),\n .io_resp_bits_fflags_bits_uop_ppred (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred),\n .io_resp_bits_fflags_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy),\n .io_resp_bits_fflags_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy),\n .io_resp_bits_fflags_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy),\n .io_resp_bits_fflags_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy),\n .io_resp_bits_fflags_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst),\n .io_resp_bits_fflags_bits_uop_exception (_FPUUnit_io_resp_bits_fflags_bits_uop_exception),\n .io_resp_bits_fflags_bits_uop_exc_cause (_FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause),\n .io_resp_bits_fflags_bits_uop_bypassable (_FPUUnit_io_resp_bits_fflags_bits_uop_bypassable),\n .io_resp_bits_fflags_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd),\n .io_resp_bits_fflags_bits_uop_mem_size (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_size),\n .io_resp_bits_fflags_bits_uop_mem_signed (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed),\n .io_resp_bits_fflags_bits_uop_is_fence (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fence),\n .io_resp_bits_fflags_bits_uop_is_fencei (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei),\n .io_resp_bits_fflags_bits_uop_is_amo (_FPUUnit_io_resp_bits_fflags_bits_uop_is_amo),\n .io_resp_bits_fflags_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq),\n .io_resp_bits_fflags_bits_uop_uses_stq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq),\n .io_resp_bits_fflags_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),\n .io_resp_bits_fflags_bits_uop_is_unique (_FPUUnit_io_resp_bits_fflags_bits_uop_is_unique),\n .io_resp_bits_fflags_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),\n .io_resp_bits_fflags_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),\n .io_resp_bits_fflags_bits_uop_ldst (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst),\n .io_resp_bits_fflags_bits_uop_lrs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1),\n .io_resp_bits_fflags_bits_uop_lrs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2),\n .io_resp_bits_fflags_bits_uop_lrs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs3),\n .io_resp_bits_fflags_bits_uop_ldst_val (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val),\n .io_resp_bits_fflags_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype),\n .io_resp_bits_fflags_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),\n .io_resp_bits_fflags_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),\n .io_resp_bits_fflags_bits_uop_frs3_en (_FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en),\n .io_resp_bits_fflags_bits_uop_fp_val (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_val),\n .io_resp_bits_fflags_bits_uop_fp_single (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_single),\n .io_resp_bits_fflags_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),\n .io_resp_bits_fflags_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),\n .io_resp_bits_fflags_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),\n .io_resp_bits_fflags_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),\n .io_resp_bits_fflags_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),\n .io_resp_bits_fflags_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),\n .io_resp_bits_fflags_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),\n .io_resp_bits_fflags_bits_flags (_FPUUnit_io_resp_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_fcsr_rm (io_fcsr_rm)\n );\n FDivSqrtUnit FDivSqrtUnit (\n .clock (clock),\n .reset (reset),\n .io_req_ready (_FDivSqrtUnit_io_req_ready),\n .io_req_valid (io_req_valid & io_req_bits_uop_fu_code[7]),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),\n .io_req_bits_rs1_data (io_req_bits_rs1_data),\n .io_req_bits_rs2_data (io_req_bits_rs2_data),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_ready (~_FPUUnit_io_resp_valid),\n .io_resp_valid (_FDivSqrtUnit_io_resp_valid),\n .io_resp_bits_uop_rob_idx (_FDivSqrtUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_pdst (_FDivSqrtUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_is_amo (_FDivSqrtUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_ldq (_FDivSqrtUnit_io_resp_bits_uop_uses_ldq),\n .io_resp_bits_uop_uses_stq (_FDivSqrtUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_dst_rtype (_FDivSqrtUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_uop_fp_val (_FDivSqrtUnit_io_resp_bits_uop_fp_val),\n .io_resp_bits_data (_FDivSqrtUnit_io_resp_bits_data),\n .io_resp_bits_fflags_valid (_FDivSqrtUnit_io_resp_bits_fflags_valid),\n .io_resp_bits_fflags_bits_uop_rob_idx (_FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx),\n .io_resp_bits_fflags_bits_flags (_FDivSqrtUnit_io_resp_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_fcsr_rm (io_fcsr_rm)\n );\n BranchKillableQueue_4 queue (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_queue_io_enq_ready),\n .io_enq_valid (_FPUUnit_io_resp_valid & _FPUUnit_io_resp_bits_uop_fu_code[9] & _FPUUnit_io_resp_bits_uop_uopc != 7'h2),\n .io_enq_bits_uop_uopc (_FPUUnit_io_resp_bits_uop_uopc),\n .io_enq_bits_uop_inst (_FPUUnit_io_resp_bits_uop_inst),\n .io_enq_bits_uop_debug_inst (_FPUUnit_io_resp_bits_uop_debug_inst),\n .io_enq_bits_uop_is_rvc (_FPUUnit_io_resp_bits_uop_is_rvc),\n .io_enq_bits_uop_debug_pc (_FPUUnit_io_resp_bits_uop_debug_pc),\n .io_enq_bits_uop_iq_type (_FPUUnit_io_resp_bits_uop_iq_type),\n .io_enq_bits_uop_fu_code (_FPUUnit_io_resp_bits_uop_fu_code),\n .io_enq_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_uop_ctrl_br_type),\n .io_enq_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_uop_ctrl_op1_sel),\n .io_enq_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_uop_ctrl_op2_sel),\n .io_enq_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_uop_ctrl_imm_sel),\n .io_enq_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_uop_ctrl_op_fcn),\n .io_enq_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_uop_ctrl_fcn_dw),\n .io_enq_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_uop_ctrl_csr_cmd),\n .io_enq_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_uop_ctrl_is_load),\n .io_enq_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_uop_ctrl_is_sta),\n .io_enq_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_uop_ctrl_is_std),\n .io_enq_bits_uop_iw_state (_FPUUnit_io_resp_bits_uop_iw_state),\n .io_enq_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_uop_iw_p1_poisoned),\n .io_enq_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_uop_iw_p2_poisoned),\n .io_enq_bits_uop_is_br (_FPUUnit_io_resp_bits_uop_is_br),\n .io_enq_bits_uop_is_jalr (_FPUUnit_io_resp_bits_uop_is_jalr),\n .io_enq_bits_uop_is_jal (_FPUUnit_io_resp_bits_uop_is_jal),\n .io_enq_bits_uop_is_sfb (_FPUUnit_io_resp_bits_uop_is_sfb),\n .io_enq_bits_uop_br_mask (_FPUUnit_io_resp_bits_uop_br_mask),\n .io_enq_bits_uop_br_tag (_FPUUnit_io_resp_bits_uop_br_tag),\n .io_enq_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_uop_ftq_idx),\n .io_enq_bits_uop_edge_inst (_FPUUnit_io_resp_bits_uop_edge_inst),\n .io_enq_bits_uop_pc_lob (_FPUUnit_io_resp_bits_uop_pc_lob),\n .io_enq_bits_uop_taken (_FPUUnit_io_resp_bits_uop_taken),\n .io_enq_bits_uop_imm_packed (_FPUUnit_io_resp_bits_uop_imm_packed),\n .io_enq_bits_uop_csr_addr (_FPUUnit_io_resp_bits_uop_csr_addr),\n .io_enq_bits_uop_rob_idx (_FPUUnit_io_resp_bits_uop_rob_idx),\n .io_enq_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_uop_ldq_idx),\n .io_enq_bits_uop_stq_idx (_FPUUnit_io_resp_bits_uop_stq_idx),\n .io_enq_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_uop_rxq_idx),\n .io_enq_bits_uop_pdst (_FPUUnit_io_resp_bits_uop_pdst),\n .io_enq_bits_uop_prs1 (_FPUUnit_io_resp_bits_uop_prs1),\n .io_enq_bits_uop_prs2 (_FPUUnit_io_resp_bits_uop_prs2),\n .io_enq_bits_uop_prs3 (_FPUUnit_io_resp_bits_uop_prs3),\n .io_enq_bits_uop_ppred (_FPUUnit_io_resp_bits_uop_ppred),\n .io_enq_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_uop_prs1_busy),\n .io_enq_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_uop_prs2_busy),\n .io_enq_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_uop_prs3_busy),\n .io_enq_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_uop_ppred_busy),\n .io_enq_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_uop_stale_pdst),\n .io_enq_bits_uop_exception (_FPUUnit_io_resp_bits_uop_exception),\n .io_enq_bits_uop_exc_cause (_FPUUnit_io_resp_bits_uop_exc_cause),\n .io_enq_bits_uop_bypassable (_FPUUnit_io_resp_bits_uop_bypassable),\n .io_enq_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_uop_mem_cmd),\n .io_enq_bits_uop_mem_size (_FPUUnit_io_resp_bits_uop_mem_size),\n .io_enq_bits_uop_mem_signed (_FPUUnit_io_resp_bits_uop_mem_signed),\n .io_enq_bits_uop_is_fence (_FPUUnit_io_resp_bits_uop_is_fence),\n .io_enq_bits_uop_is_fencei (_FPUUnit_io_resp_bits_uop_is_fencei),\n .io_enq_bits_uop_is_amo (_FPUUnit_io_resp_bits_uop_is_amo),\n .io_enq_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_uop_uses_ldq),\n .io_enq_bits_uop_uses_stq (_FPUUnit_io_resp_bits_uop_uses_stq),\n .io_enq_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_uop_is_sys_pc2epc),\n .io_enq_bits_uop_is_unique (_FPUUnit_io_resp_bits_uop_is_unique),\n .io_enq_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_uop_flush_on_commit),\n .io_enq_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_uop_ldst_is_rs1),\n .io_enq_bits_uop_ldst (_FPUUnit_io_resp_bits_uop_ldst),\n .io_enq_bits_uop_lrs1 (_FPUUnit_io_resp_bits_uop_lrs1),\n .io_enq_bits_uop_lrs2 (_FPUUnit_io_resp_bits_uop_lrs2),\n .io_enq_bits_uop_lrs3 (_FPUUnit_io_resp_bits_uop_lrs3),\n .io_enq_bits_uop_ldst_val (_FPUUnit_io_resp_bits_uop_ldst_val),\n .io_enq_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_uop_dst_rtype),\n .io_enq_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_uop_lrs1_rtype),\n .io_enq_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_uop_lrs2_rtype),\n .io_enq_bits_uop_frs3_en (_FPUUnit_io_resp_bits_uop_frs3_en),\n .io_enq_bits_uop_fp_val (_FPUUnit_io_resp_bits_uop_fp_val),\n .io_enq_bits_uop_fp_single (_FPUUnit_io_resp_bits_uop_fp_single),\n .io_enq_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_uop_xcpt_pf_if),\n .io_enq_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_uop_xcpt_ae_if),\n .io_enq_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_uop_xcpt_ma_if),\n .io_enq_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_uop_bp_debug_if),\n .io_enq_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_uop_bp_xcpt_if),\n .io_enq_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_uop_debug_fsrc),\n .io_enq_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_uop_debug_tsrc),\n .io_enq_bits_data (_FPUUnit_io_resp_bits_data),\n .io_enq_bits_fflags_valid (_FPUUnit_io_resp_bits_fflags_valid),\n .io_enq_bits_fflags_bits_uop_uopc (_FPUUnit_io_resp_bits_fflags_bits_uop_uopc),\n .io_enq_bits_fflags_bits_uop_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_inst),\n .io_enq_bits_fflags_bits_uop_debug_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_inst),\n .io_enq_bits_fflags_bits_uop_is_rvc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_rvc),\n .io_enq_bits_fflags_bits_uop_debug_pc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_pc),\n .io_enq_bits_fflags_bits_uop_iq_type (_FPUUnit_io_resp_bits_fflags_bits_uop_iq_type),\n .io_enq_bits_fflags_bits_uop_fu_code (_FPUUnit_io_resp_bits_fflags_bits_uop_fu_code),\n .io_enq_bits_fflags_bits_uop_ctrl_br_type (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),\n .io_enq_bits_fflags_bits_uop_ctrl_op1_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_op2_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_imm_sel (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_op_fcn (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),\n .io_enq_bits_fflags_bits_uop_ctrl_fcn_dw (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),\n .io_enq_bits_fflags_bits_uop_ctrl_csr_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),\n .io_enq_bits_fflags_bits_uop_ctrl_is_load (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),\n .io_enq_bits_fflags_bits_uop_ctrl_is_sta (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),\n .io_enq_bits_fflags_bits_uop_ctrl_is_std (_FPUUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),\n .io_enq_bits_fflags_bits_uop_iw_state (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_state),\n .io_enq_bits_fflags_bits_uop_iw_p1_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),\n .io_enq_bits_fflags_bits_uop_iw_p2_poisoned (_FPUUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),\n .io_enq_bits_fflags_bits_uop_is_br (_FPUUnit_io_resp_bits_fflags_bits_uop_is_br),\n .io_enq_bits_fflags_bits_uop_is_jalr (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jalr),\n .io_enq_bits_fflags_bits_uop_is_jal (_FPUUnit_io_resp_bits_fflags_bits_uop_is_jal),\n .io_enq_bits_fflags_bits_uop_is_sfb (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sfb),\n .io_enq_bits_fflags_bits_uop_br_mask (_FPUUnit_io_resp_bits_fflags_bits_uop_br_mask),\n .io_enq_bits_fflags_bits_uop_br_tag (_FPUUnit_io_resp_bits_fflags_bits_uop_br_tag),\n .io_enq_bits_fflags_bits_uop_ftq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ftq_idx),\n .io_enq_bits_fflags_bits_uop_edge_inst (_FPUUnit_io_resp_bits_fflags_bits_uop_edge_inst),\n .io_enq_bits_fflags_bits_uop_pc_lob (_FPUUnit_io_resp_bits_fflags_bits_uop_pc_lob),\n .io_enq_bits_fflags_bits_uop_taken (_FPUUnit_io_resp_bits_fflags_bits_uop_taken),\n .io_enq_bits_fflags_bits_uop_imm_packed (_FPUUnit_io_resp_bits_fflags_bits_uop_imm_packed),\n .io_enq_bits_fflags_bits_uop_csr_addr (_FPUUnit_io_resp_bits_fflags_bits_uop_csr_addr),\n .io_enq_bits_fflags_bits_uop_rob_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx),\n .io_enq_bits_fflags_bits_uop_ldq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_ldq_idx),\n .io_enq_bits_fflags_bits_uop_stq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_stq_idx),\n .io_enq_bits_fflags_bits_uop_rxq_idx (_FPUUnit_io_resp_bits_fflags_bits_uop_rxq_idx),\n .io_enq_bits_fflags_bits_uop_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_pdst),\n .io_enq_bits_fflags_bits_uop_prs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1),\n .io_enq_bits_fflags_bits_uop_prs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2),\n .io_enq_bits_fflags_bits_uop_prs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3),\n .io_enq_bits_fflags_bits_uop_ppred (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred),\n .io_enq_bits_fflags_bits_uop_prs1_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs1_busy),\n .io_enq_bits_fflags_bits_uop_prs2_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs2_busy),\n .io_enq_bits_fflags_bits_uop_prs3_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_prs3_busy),\n .io_enq_bits_fflags_bits_uop_ppred_busy (_FPUUnit_io_resp_bits_fflags_bits_uop_ppred_busy),\n .io_enq_bits_fflags_bits_uop_stale_pdst (_FPUUnit_io_resp_bits_fflags_bits_uop_stale_pdst),\n .io_enq_bits_fflags_bits_uop_exception (_FPUUnit_io_resp_bits_fflags_bits_uop_exception),\n .io_enq_bits_fflags_bits_uop_exc_cause (_FPUUnit_io_resp_bits_fflags_bits_uop_exc_cause),\n .io_enq_bits_fflags_bits_uop_bypassable (_FPUUnit_io_resp_bits_fflags_bits_uop_bypassable),\n .io_enq_bits_fflags_bits_uop_mem_cmd (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_cmd),\n .io_enq_bits_fflags_bits_uop_mem_size (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_size),\n .io_enq_bits_fflags_bits_uop_mem_signed (_FPUUnit_io_resp_bits_fflags_bits_uop_mem_signed),\n .io_enq_bits_fflags_bits_uop_is_fence (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fence),\n .io_enq_bits_fflags_bits_uop_is_fencei (_FPUUnit_io_resp_bits_fflags_bits_uop_is_fencei),\n .io_enq_bits_fflags_bits_uop_is_amo (_FPUUnit_io_resp_bits_fflags_bits_uop_is_amo),\n .io_enq_bits_fflags_bits_uop_uses_ldq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_ldq),\n .io_enq_bits_fflags_bits_uop_uses_stq (_FPUUnit_io_resp_bits_fflags_bits_uop_uses_stq),\n .io_enq_bits_fflags_bits_uop_is_sys_pc2epc (_FPUUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),\n .io_enq_bits_fflags_bits_uop_is_unique (_FPUUnit_io_resp_bits_fflags_bits_uop_is_unique),\n .io_enq_bits_fflags_bits_uop_flush_on_commit (_FPUUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),\n .io_enq_bits_fflags_bits_uop_ldst_is_rs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),\n .io_enq_bits_fflags_bits_uop_ldst (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst),\n .io_enq_bits_fflags_bits_uop_lrs1 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1),\n .io_enq_bits_fflags_bits_uop_lrs2 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2),\n .io_enq_bits_fflags_bits_uop_lrs3 (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs3),\n .io_enq_bits_fflags_bits_uop_ldst_val (_FPUUnit_io_resp_bits_fflags_bits_uop_ldst_val),\n .io_enq_bits_fflags_bits_uop_dst_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_dst_rtype),\n .io_enq_bits_fflags_bits_uop_lrs1_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),\n .io_enq_bits_fflags_bits_uop_lrs2_rtype (_FPUUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),\n .io_enq_bits_fflags_bits_uop_frs3_en (_FPUUnit_io_resp_bits_fflags_bits_uop_frs3_en),\n .io_enq_bits_fflags_bits_uop_fp_val (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_val),\n .io_enq_bits_fflags_bits_uop_fp_single (_FPUUnit_io_resp_bits_fflags_bits_uop_fp_single),\n .io_enq_bits_fflags_bits_uop_xcpt_pf_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),\n .io_enq_bits_fflags_bits_uop_xcpt_ae_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),\n .io_enq_bits_fflags_bits_uop_xcpt_ma_if (_FPUUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),\n .io_enq_bits_fflags_bits_uop_bp_debug_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),\n .io_enq_bits_fflags_bits_uop_bp_xcpt_if (_FPUUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),\n .io_enq_bits_fflags_bits_uop_debug_fsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),\n .io_enq_bits_fflags_bits_uop_debug_tsrc (_FPUUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),\n .io_enq_bits_fflags_bits_flags (_FPUUnit_io_resp_bits_fflags_bits_flags),\n .io_deq_ready (_resp_arb_io_in_0_ready),\n .io_deq_valid (_queue_io_deq_valid),\n .io_deq_bits_uop_uopc (_queue_io_deq_bits_uop_uopc),\n .io_deq_bits_uop_br_mask (_queue_io_deq_bits_uop_br_mask),\n .io_deq_bits_uop_rob_idx (_queue_io_deq_bits_uop_rob_idx),\n .io_deq_bits_uop_stq_idx (_queue_io_deq_bits_uop_stq_idx),\n .io_deq_bits_uop_pdst (_queue_io_deq_bits_uop_pdst),\n .io_deq_bits_uop_is_amo (_queue_io_deq_bits_uop_is_amo),\n .io_deq_bits_uop_uses_stq (_queue_io_deq_bits_uop_uses_stq),\n .io_deq_bits_uop_dst_rtype (_queue_io_deq_bits_uop_dst_rtype),\n .io_deq_bits_uop_fp_val (_queue_io_deq_bits_uop_fp_val),\n .io_deq_bits_data (_queue_io_deq_bits_data),\n .io_deq_bits_predicated (_queue_io_deq_bits_predicated),\n .io_deq_bits_fflags_valid (_queue_io_deq_bits_fflags_valid),\n .io_deq_bits_fflags_bits_uop_rob_idx (_queue_io_deq_bits_fflags_bits_uop_rob_idx),\n .io_deq_bits_fflags_bits_flags (_queue_io_deq_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_flush (io_req_bits_kill),\n .io_empty (_queue_io_empty)\n );\n BranchKillableQueue_5 fp_sdq (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_fp_sdq_io_enq_ready),\n .io_enq_valid (fp_sdq_io_enq_valid),\n .io_enq_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_enq_bits_uop_inst (io_req_bits_uop_inst),\n .io_enq_bits_uop_debug_inst (io_req_bits_uop_debug_inst),\n .io_enq_bits_uop_is_rvc (io_req_bits_uop_is_rvc),\n .io_enq_bits_uop_debug_pc (io_req_bits_uop_debug_pc),\n .io_enq_bits_uop_iq_type (io_req_bits_uop_iq_type),\n .io_enq_bits_uop_fu_code (io_req_bits_uop_fu_code),\n .io_enq_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),\n .io_enq_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),\n .io_enq_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),\n .io_enq_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),\n .io_enq_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_enq_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_enq_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),\n .io_enq_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),\n .io_enq_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),\n .io_enq_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),\n .io_enq_bits_uop_iw_state (io_req_bits_uop_iw_state),\n .io_enq_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned),\n .io_enq_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned),\n .io_enq_bits_uop_is_br (io_req_bits_uop_is_br),\n .io_enq_bits_uop_is_jalr (io_req_bits_uop_is_jalr),\n .io_enq_bits_uop_is_jal (io_req_bits_uop_is_jal),\n .io_enq_bits_uop_is_sfb (io_req_bits_uop_is_sfb),\n .io_enq_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_enq_bits_uop_br_tag (io_req_bits_uop_br_tag),\n .io_enq_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),\n .io_enq_bits_uop_edge_inst (io_req_bits_uop_edge_inst),\n .io_enq_bits_uop_pc_lob (io_req_bits_uop_pc_lob),\n .io_enq_bits_uop_taken (io_req_bits_uop_taken),\n .io_enq_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_enq_bits_uop_csr_addr (io_req_bits_uop_csr_addr),\n .io_enq_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_enq_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),\n .io_enq_bits_uop_stq_idx (io_req_bits_uop_stq_idx),\n .io_enq_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),\n .io_enq_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_enq_bits_uop_prs1 (io_req_bits_uop_prs1),\n .io_enq_bits_uop_prs2 (io_req_bits_uop_prs2),\n .io_enq_bits_uop_prs3 (io_req_bits_uop_prs3),\n .io_enq_bits_uop_ppred (io_req_bits_uop_ppred),\n .io_enq_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),\n .io_enq_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),\n .io_enq_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),\n .io_enq_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),\n .io_enq_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),\n .io_enq_bits_uop_exception (io_req_bits_uop_exception),\n .io_enq_bits_uop_exc_cause (io_req_bits_uop_exc_cause),\n .io_enq_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_enq_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),\n .io_enq_bits_uop_mem_size (io_req_bits_uop_mem_size),\n .io_enq_bits_uop_mem_signed (io_req_bits_uop_mem_signed),\n .io_enq_bits_uop_is_fence (io_req_bits_uop_is_fence),\n .io_enq_bits_uop_is_fencei (io_req_bits_uop_is_fencei),\n .io_enq_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_enq_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),\n .io_enq_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_enq_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),\n .io_enq_bits_uop_is_unique (io_req_bits_uop_is_unique),\n .io_enq_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),\n .io_enq_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),\n .io_enq_bits_uop_ldst (io_req_bits_uop_ldst),\n .io_enq_bits_uop_lrs1 (io_req_bits_uop_lrs1),\n .io_enq_bits_uop_lrs2 (io_req_bits_uop_lrs2),\n .io_enq_bits_uop_lrs3 (io_req_bits_uop_lrs3),\n .io_enq_bits_uop_ldst_val (io_req_bits_uop_ldst_val),\n .io_enq_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_enq_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),\n .io_enq_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),\n .io_enq_bits_uop_frs3_en (io_req_bits_uop_frs3_en),\n .io_enq_bits_uop_fp_val (io_req_bits_uop_fp_val),\n .io_enq_bits_uop_fp_single (io_req_bits_uop_fp_single),\n .io_enq_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),\n .io_enq_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),\n .io_enq_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),\n .io_enq_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),\n .io_enq_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),\n .io_enq_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),\n .io_enq_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),\n .io_enq_bits_data ({1'h0, io_req_bits_rs2_data[64], (fp_sdq_io_enq_bits_data_unrecoded_isSubnormal ? 11'h0 : io_req_bits_rs2_data[62:52] + 11'h3FF) | {11{(&(io_req_bits_rs2_data[63:62])) & io_req_bits_rs2_data[61] | fp_sdq_io_enq_bits_data_unrecoded_rawIn_isInf}}, fp_sdq_io_enq_bits_data_unrecoded_fractOut[51:32], (&(io_req_bits_rs2_data[63:61])) ? {io_req_bits_rs2_data[31], (fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : io_req_bits_rs2_data[30:23] + 8'h7F) | {8{(&_fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isSpecial_T) & io_req_bits_rs2_data[29] | fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf}}, fp_sdq_io_enq_bits_data_prevUnrecoded_isSubnormal ? _fp_sdq_io_enq_bits_data_prevUnrecoded_denormFract_T_1[22:0] : fp_sdq_io_enq_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : io_req_bits_rs2_data[22:0]} : fp_sdq_io_enq_bits_data_unrecoded_fractOut[31:0]}),\n .io_deq_ready (_resp_arb_io_in_1_ready),\n .io_deq_valid (_fp_sdq_io_deq_valid),\n .io_deq_bits_uop_uopc (_fp_sdq_io_deq_bits_uop_uopc),\n .io_deq_bits_uop_br_mask (_fp_sdq_io_deq_bits_uop_br_mask),\n .io_deq_bits_uop_rob_idx (_fp_sdq_io_deq_bits_uop_rob_idx),\n .io_deq_bits_uop_stq_idx (_fp_sdq_io_deq_bits_uop_stq_idx),\n .io_deq_bits_uop_pdst (_fp_sdq_io_deq_bits_uop_pdst),\n .io_deq_bits_uop_is_amo (_fp_sdq_io_deq_bits_uop_is_amo),\n .io_deq_bits_uop_uses_stq (_fp_sdq_io_deq_bits_uop_uses_stq),\n .io_deq_bits_uop_dst_rtype (_fp_sdq_io_deq_bits_uop_dst_rtype),\n .io_deq_bits_uop_fp_val (_fp_sdq_io_deq_bits_uop_fp_val),\n .io_deq_bits_data (_fp_sdq_io_deq_bits_data),\n .io_deq_bits_predicated (_fp_sdq_io_deq_bits_predicated),\n .io_deq_bits_fflags_valid (_fp_sdq_io_deq_bits_fflags_valid),\n .io_deq_bits_fflags_bits_uop_rob_idx (_fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx),\n .io_deq_bits_fflags_bits_flags (_fp_sdq_io_deq_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_flush (io_req_bits_kill),\n .io_empty (_fp_sdq_io_empty)\n );\n Arbiter2_ExeUnitResp resp_arb (\n .io_in_0_ready (_resp_arb_io_in_0_ready),\n .io_in_0_valid (_queue_io_deq_valid),\n .io_in_0_bits_uop_uopc (_queue_io_deq_bits_uop_uopc),\n .io_in_0_bits_uop_br_mask (_queue_io_deq_bits_uop_br_mask),\n .io_in_0_bits_uop_rob_idx (_queue_io_deq_bits_uop_rob_idx),\n .io_in_0_bits_uop_stq_idx (_queue_io_deq_bits_uop_stq_idx),\n .io_in_0_bits_uop_pdst (_queue_io_deq_bits_uop_pdst),\n .io_in_0_bits_uop_is_amo (_queue_io_deq_bits_uop_is_amo),\n .io_in_0_bits_uop_uses_stq (_queue_io_deq_bits_uop_uses_stq),\n .io_in_0_bits_uop_dst_rtype (_queue_io_deq_bits_uop_dst_rtype),\n .io_in_0_bits_uop_fp_val (_queue_io_deq_bits_uop_fp_val),\n .io_in_0_bits_data (_queue_io_deq_bits_data),\n .io_in_0_bits_predicated (_queue_io_deq_bits_predicated),\n .io_in_0_bits_fflags_valid (_queue_io_deq_bits_fflags_valid),\n .io_in_0_bits_fflags_bits_uop_rob_idx (_queue_io_deq_bits_fflags_bits_uop_rob_idx),\n .io_in_0_bits_fflags_bits_flags (_queue_io_deq_bits_fflags_bits_flags),\n .io_in_1_ready (_resp_arb_io_in_1_ready),\n .io_in_1_valid (_fp_sdq_io_deq_valid),\n .io_in_1_bits_uop_uopc (_fp_sdq_io_deq_bits_uop_uopc),\n .io_in_1_bits_uop_br_mask (_fp_sdq_io_deq_bits_uop_br_mask),\n .io_in_1_bits_uop_rob_idx (_fp_sdq_io_deq_bits_uop_rob_idx),\n .io_in_1_bits_uop_stq_idx (_fp_sdq_io_deq_bits_uop_stq_idx),\n .io_in_1_bits_uop_pdst (_fp_sdq_io_deq_bits_uop_pdst),\n .io_in_1_bits_uop_is_amo (_fp_sdq_io_deq_bits_uop_is_amo),\n .io_in_1_bits_uop_uses_stq (_fp_sdq_io_deq_bits_uop_uses_stq),\n .io_in_1_bits_uop_dst_rtype (_fp_sdq_io_deq_bits_uop_dst_rtype),\n .io_in_1_bits_uop_fp_val (_fp_sdq_io_deq_bits_uop_fp_val),\n .io_in_1_bits_data (_fp_sdq_io_deq_bits_data),\n .io_in_1_bits_predicated (_fp_sdq_io_deq_bits_predicated),\n .io_in_1_bits_fflags_valid (_fp_sdq_io_deq_bits_fflags_valid),\n .io_in_1_bits_fflags_bits_uop_rob_idx (_fp_sdq_io_deq_bits_fflags_bits_uop_rob_idx),\n .io_in_1_bits_fflags_bits_flags (_fp_sdq_io_deq_bits_fflags_bits_flags),\n .io_out_ready (io_ll_iresp_ready),\n .io_out_valid (io_ll_iresp_valid),\n .io_out_bits_uop_uopc (io_ll_iresp_bits_uop_uopc),\n .io_out_bits_uop_br_mask (io_ll_iresp_bits_uop_br_mask),\n .io_out_bits_uop_rob_idx (io_ll_iresp_bits_uop_rob_idx),\n .io_out_bits_uop_stq_idx (io_ll_iresp_bits_uop_stq_idx),\n .io_out_bits_uop_pdst (io_ll_iresp_bits_uop_pdst),\n .io_out_bits_uop_is_amo (io_ll_iresp_bits_uop_is_amo),\n .io_out_bits_uop_uses_stq (io_ll_iresp_bits_uop_uses_stq),\n .io_out_bits_uop_dst_rtype (io_ll_iresp_bits_uop_dst_rtype),\n .io_out_bits_uop_fp_val (/* unused */),\n .io_out_bits_data (io_ll_iresp_bits_data),\n .io_out_bits_predicated (io_ll_iresp_bits_predicated),\n .io_out_bits_fflags_valid (/* unused */),\n .io_out_bits_fflags_bits_uop_rob_idx (/* unused */),\n .io_out_bits_fflags_bits_flags (/* unused */)\n );\n assign io_fu_types = {_fpiu_busy_T, 1'h0, ~fdiv_busy, 7'h40};\n assign io_fresp_valid = (_FPUUnit_io_resp_valid | _FDivSqrtUnit_io_resp_valid) & ~(_FPUUnit_io_resp_valid & _FPUUnit_io_resp_bits_uop_fu_code[9]);\n assign io_fresp_bits_uop_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_uop_rob_idx;\n assign io_fresp_bits_uop_pdst = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_pdst : _FDivSqrtUnit_io_resp_bits_uop_pdst;\n assign io_fresp_bits_uop_is_amo = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_is_amo : _FDivSqrtUnit_io_resp_bits_uop_is_amo;\n assign io_fresp_bits_uop_uses_ldq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_ldq : _FDivSqrtUnit_io_resp_bits_uop_uses_ldq;\n assign io_fresp_bits_uop_uses_stq = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_uses_stq : _FDivSqrtUnit_io_resp_bits_uop_uses_stq;\n assign io_fresp_bits_uop_dst_rtype = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_dst_rtype : _FDivSqrtUnit_io_resp_bits_uop_dst_rtype;\n assign io_fresp_bits_uop_fp_val = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_uop_fp_val : _FDivSqrtUnit_io_resp_bits_uop_fp_val;\n assign io_fresp_bits_data = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_data : _FDivSqrtUnit_io_resp_bits_data;\n assign io_fresp_bits_fflags_valid = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_valid : _FDivSqrtUnit_io_resp_bits_fflags_valid;\n assign io_fresp_bits_fflags_bits_uop_rob_idx = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_bits_uop_rob_idx : _FDivSqrtUnit_io_resp_bits_fflags_bits_uop_rob_idx;\n assign io_fresp_bits_fflags_bits_flags = _FPUUnit_io_resp_valid ? _FPUUnit_io_resp_bits_fflags_bits_flags : _FDivSqrtUnit_io_resp_bits_fflags_bits_flags;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericSerializer_TLBeatw87_f32(\n input clock,\n input reset,\n input io_in_bits_head,\n input io_in_bits_tail,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_flit\n);\n\n wire [0:0][31:0] _GEN = '{32'h0};\n reg [31:0] data_1;\n reg [31:0] data_2;\n reg [1:0] beat;\n wire _io_out_bits_flit_T = beat == 2'h0;\n wire [3:0][31:0] _GEN_0 = {_GEN, {{data_2}, {data_1}, {32'h0}}};\n wire _GEN_1 = io_out_ready & (|beat);\n always @(posedge clock) begin\n if (_GEN_1 & _io_out_bits_flit_T) begin\n data_1 <= 32'h0;\n data_2 <= 32'h0;\n end\n if (reset)\n beat <= 2'h0;\n else if (_GEN_1)\n beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;\n end\n assign io_out_valid = |beat;\n assign io_out_bits_flit = _io_out_bits_flit_T ? {30'h0, io_in_bits_head, io_in_bits_tail} : _GEN_0[beat];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericSerializer_TLBeatw10_f32(\n input io_in_bits_head,\n output [31:0] io_out_bits_flit\n);\n\n assign io_out_bits_flit = {30'h0, io_in_bits_head, 1'h1};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericSerializer_TLBeatw67_f32(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [64:0] io_in_bits_payload,\n input io_in_bits_head,\n input io_in_bits_tail,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_flit\n);\n\n wire [0:0][31:0] _GEN = '{32'h0};\n reg [31:0] data_1;\n reg [31:0] data_2;\n reg [1:0] beat;\n wire _io_out_bits_flit_T = beat == 2'h0;\n wire [2:0] _GEN_0 = {io_in_valid, beat};\n wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}};\n wire _GEN_2 = io_out_ready & (|_GEN_0);\n always @(posedge clock) begin\n if (_GEN_2 & _io_out_bits_flit_T) begin\n data_1 <= io_in_bits_payload[61:30];\n data_2 <= {29'h0, io_in_bits_payload[64:62]};\n end\n if (reset)\n beat <= 2'h0;\n else if (_GEN_2)\n beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_out_ready & _io_out_bits_flit_T;\n assign io_out_valid = |_GEN_0;\n assign io_out_bits_flit = _io_out_bits_flit_T ? {io_in_bits_payload[29:0], io_in_bits_head, io_in_bits_tail} : _GEN_1[beat];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\n\nclass Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {\n val xcpt0 = new FrontendExceptions // exceptions on first half of instruction\n val xcpt1 = new FrontendExceptions // exceptions on second half of instruction\n val replay = Bool()\n val rvc = Bool()\n val inst = new ExpandedInstruction\n val raw = UInt(32.W)\n require(coreInstBits == (if (usingCompressed) 16 else 32))\n}\n\nclass IBuf(implicit p: Parameters) extends CoreModule {\n val io = IO(new Bundle {\n val imem = Flipped(Decoupled(new FrontendResp))\n val kill = Input(Bool())\n val pc = Output(UInt(vaddrBitsExtended.W))\n val btb_resp = Output(new BTBResp())\n val inst = Vec(retireWidth, Decoupled(new Instruction))\n })\n\n // This module is meant to be more general, but it's not there yet\n require(decodeWidth == 1)\n\n val n = fetchWidth - 1\n val nBufValid = if (n == 0) 0.U else RegInit(init=0.U(log2Ceil(fetchWidth).W))\n val buf = Reg(chiselTypeOf(io.imem.bits))\n val ibufBTBResp = Reg(new BTBResp)\n val pcWordMask = (coreInstBytes*fetchWidth-1).U(vaddrBitsExtended.W)\n\n val pcWordBits = io.imem.bits.pc.extract(log2Ceil(fetchWidth*coreInstBytes)-1, log2Ceil(coreInstBytes))\n val nReady = WireDefault(0.U(log2Ceil(fetchWidth+1).W))\n val nIC = Mux(io.imem.bits.btb.taken, io.imem.bits.btb.bridx +& 1.U, fetchWidth.U) - pcWordBits\n val nICReady = nReady - nBufValid\n val nValid = Mux(io.imem.valid, nIC, 0.U) + nBufValid\n io.imem.ready := io.inst(0).ready && nReady >= nBufValid && (nICReady >= nIC || n.U >= nIC - nICReady)\n\n if (n > 0) {\n when (io.inst(0).ready) {\n nBufValid := Mux(nReady >== nBufValid, 0.U, nBufValid - nReady)\n if (n > 1) when (nReady > 0.U && nReady < nBufValid) {\n val shiftedBuf = shiftInsnRight(buf.data(n*coreInstBits-1, coreInstBits), (nReady-1.U)(log2Ceil(n-1)-1,0))\n buf.data := Cat(buf.data(n*coreInstBits-1, (n-1)*coreInstBits), shiftedBuf((n-1)*coreInstBits-1, 0))\n buf.pc := buf.pc & ~pcWordMask | (buf.pc + (nReady << log2Ceil(coreInstBytes))) & pcWordMask\n }\n when (io.imem.valid && nReady >= nBufValid && nICReady < nIC && n.U >= nIC - nICReady) {\n val shamt = pcWordBits + nICReady\n nBufValid := nIC - nICReady\n buf := io.imem.bits\n buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)\n buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask\n ibufBTBResp := io.imem.bits.btb\n }\n }\n when (io.kill) {\n nBufValid := 0.U\n }\n }\n\n val icShiftAmt = (fetchWidth.U + nBufValid - pcWordBits)(log2Ceil(fetchWidth), 0)\n val icData = shiftInsnLeft(Cat(io.imem.bits.data, Fill(fetchWidth, io.imem.bits.data(coreInstBits-1, 0))), icShiftAmt)\n .extract(3*fetchWidth*coreInstBits-1, 2*fetchWidth*coreInstBits)\n val icMask = (~0.U((fetchWidth*coreInstBits).W) << (nBufValid << log2Ceil(coreInstBits)))(fetchWidth*coreInstBits-1,0)\n val inst = icData & icMask | buf.data & ~icMask\n\n val valid = (UIntToOH(nValid) - 1.U)(fetchWidth-1, 0)\n val bufMask = UIntToOH(nBufValid) - 1.U\n val xcpt = (0 until bufMask.getWidth).map(i => Mux(bufMask(i), buf.xcpt, io.imem.bits.xcpt))\n val buf_replay = Mux(buf.replay, bufMask, 0.U)\n val ic_replay = buf_replay | Mux(io.imem.bits.replay, valid & ~bufMask, 0.U)\n assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n\n io.btb_resp := io.imem.bits.btb\n io.pc := Mux(nBufValid > 0.U, buf.pc, io.imem.bits.pc)\n expand(0, 0.U, inst)\n\n def expand(i: Int, j: UInt, curInst: UInt): Unit = if (i < retireWidth) {\n val exp = Module(new RVCExpander)\n exp.io.in := curInst\n io.inst(i).bits.inst := exp.io.out\n io.inst(i).bits.raw := curInst\n\n if (usingCompressed) {\n val replay = ic_replay(j) || (!exp.io.rvc && ic_replay(j+1.U))\n val full_insn = exp.io.rvc || valid(j+1.U) || buf_replay(j)\n io.inst(i).valid := valid(j) && full_insn\n io.inst(i).bits.xcpt0 := xcpt(j)\n io.inst(i).bits.xcpt1 := Mux(exp.io.rvc, 0.U, xcpt(j+1.U).asUInt).asTypeOf(new FrontendExceptions)\n io.inst(i).bits.replay := replay\n io.inst(i).bits.rvc := exp.io.rvc\n\n when ((bufMask(j) && exp.io.rvc) || bufMask(j+1.U)) { io.btb_resp := ibufBTBResp }\n\n when (full_insn && ((i == 0).B || io.inst(i).ready)) { nReady := Mux(exp.io.rvc, j+1.U, j+2.U) }\n\n expand(i+1, Mux(exp.io.rvc, j+1.U, j+2.U), Mux(exp.io.rvc, curInst >> 16, curInst >> 32))\n } else {\n when ((i == 0).B || io.inst(i).ready) { nReady := (i+1).U }\n io.inst(i).valid := valid(i)\n io.inst(i).bits.xcpt0 := xcpt(i)\n io.inst(i).bits.xcpt1 := 0.U.asTypeOf(new FrontendExceptions)\n io.inst(i).bits.replay := ic_replay(i)\n io.inst(i).bits.rvc := false.B\n\n expand(i+1, null, curInst >> 32)\n }\n }\n\n def shiftInsnLeft(in: UInt, dist: UInt) = {\n val r = in.getWidth/coreInstBits\n require(in.getWidth % coreInstBits == 0)\n val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)\n data << (dist << log2Ceil(coreInstBits))\n }\n\n def shiftInsnRight(in: UInt, dist: UInt) = {\n val r = in.getWidth/coreInstBits\n require(in.getWidth % coreInstBits == 0)\n val data = Cat(Fill((1 << (log2Ceil(r) + 1)) - r, in >> (r-1)*coreInstBits), in)\n data >> (dist << log2Ceil(coreInstBits))\n }\n}", + "response": "module IBuf(\n input clock,\n input reset,\n output io_imem_ready,\n input io_imem_valid,\n input io_imem_bits_btb_taken,\n input io_imem_bits_btb_bridx,\n input [4:0] io_imem_bits_btb_entry,\n input [7:0] io_imem_bits_btb_bht_history,\n input [39:0] io_imem_bits_pc,\n input [31:0] io_imem_bits_data,\n input io_imem_bits_xcpt_pf_inst,\n input io_imem_bits_xcpt_gf_inst,\n input io_imem_bits_xcpt_ae_inst,\n input io_imem_bits_replay,\n input io_kill,\n output [39:0] io_pc,\n output [4:0] io_btb_resp_entry,\n output [7:0] io_btb_resp_bht_history,\n input io_inst_0_ready,\n output io_inst_0_valid,\n output io_inst_0_bits_xcpt0_pf_inst,\n output io_inst_0_bits_xcpt0_gf_inst,\n output io_inst_0_bits_xcpt0_ae_inst,\n output io_inst_0_bits_xcpt1_pf_inst,\n output io_inst_0_bits_xcpt1_gf_inst,\n output io_inst_0_bits_xcpt1_ae_inst,\n output io_inst_0_bits_replay,\n output io_inst_0_bits_rvc,\n output [31:0] io_inst_0_bits_inst_bits,\n output [4:0] io_inst_0_bits_inst_rd,\n output [4:0] io_inst_0_bits_inst_rs1,\n output [4:0] io_inst_0_bits_inst_rs2,\n output [4:0] io_inst_0_bits_inst_rs3,\n output [31:0] io_inst_0_bits_raw\n);\n\n wire [1:0] nReady;\n wire _exp_io_rvc;\n reg nBufValid;\n reg [39:0] buf_pc;\n reg [31:0] buf_data;\n reg buf_xcpt_pf_inst;\n reg buf_xcpt_gf_inst;\n reg buf_xcpt_ae_inst;\n reg buf_replay;\n reg [4:0] ibufBTBResp_entry;\n reg [7:0] ibufBTBResp_bht_history;\n wire [1:0] _GEN = {1'h0, io_imem_bits_pc[1]};\n wire [1:0] _nIC_T_2 = (io_imem_bits_btb_taken ? {1'h0, io_imem_bits_btb_bridx} + 2'h1 : 2'h2) - _GEN;\n wire [1:0] _GEN_0 = {1'h0, nBufValid};\n wire [1:0] _nICReady_T = nReady - _GEN_0;\n wire _nBufValid_T = nReady >= _GEN_0;\n wire [1:0] _nBufValid_T_6 = _nIC_T_2 - _nICReady_T;\n wire [190:0] _icData_T_4 = {63'h0, {2{{2{io_imem_bits_data[31:16]}}}}, io_imem_bits_data, {2{io_imem_bits_data[15:0]}}} << {185'h0, _GEN_0 - 2'h2 - _GEN, 4'h0};\n wire [62:0] _icMask_T_2 = 63'hFFFFFFFF << {58'h0, nBufValid, 4'h0};\n wire [31:0] inst = _icData_T_4[95:64] & _icMask_T_2[31:0] | buf_data & ~(_icMask_T_2[31:0]);\n wire [3:0] _valid_T = 4'h1 << (io_imem_valid ? _nIC_T_2 : 2'h0) + _GEN_0;\n wire [1:0] _valid_T_1 = _valid_T[1:0] - 2'h1;\n wire [1:0] _bufMask_T_1 = (2'h1 << _GEN_0) - 2'h1;\n wire [1:0] buf_replay_0 = buf_replay ? _bufMask_T_1 : 2'h0;\n wire [1:0] ic_replay = buf_replay_0 | (io_imem_bits_replay ? _valid_T_1 & ~_bufMask_T_1 : 2'h0);\n wire full_insn = _exp_io_rvc | _valid_T_1[1] | buf_replay_0[0];\n wire [2:0] _io_inst_0_bits_xcpt1_T_5 = _exp_io_rvc ? 3'h0 : {_bufMask_T_1[1] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst, _bufMask_T_1[1] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst, _bufMask_T_1[1] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst};\n wire _GEN_1 = _bufMask_T_1[0] & _exp_io_rvc | _bufMask_T_1[1];\n assign nReady = full_insn ? (_exp_io_rvc ? 2'h1 : 2'h2) : 2'h0;\n wire [63:0] _buf_data_T_1 = {{2{io_imem_bits_data[31:16]}}, io_imem_bits_data} >> {58'h0, _GEN + _nICReady_T, 4'h0};\n wire _GEN_2 = io_imem_valid & _nBufValid_T & _nICReady_T < _nIC_T_2 & ~(_nBufValid_T_6[1]);\n always @(posedge clock) begin\n if (reset)\n nBufValid <= 1'h0;\n else\n nBufValid <= ~io_kill & (io_inst_0_ready ? (_GEN_2 ? _nBufValid_T_6[0] : ~(_nBufValid_T | ~nBufValid) & nBufValid - nReady[0]) : nBufValid);\n if (io_inst_0_ready & _GEN_2) begin\n buf_pc <= io_imem_bits_pc & 40'hFFFFFFFFFC | io_imem_bits_pc + {37'h0, _nICReady_T, 1'h0} & 40'h3;\n buf_data <= {16'h0, _buf_data_T_1[15:0]};\n buf_xcpt_pf_inst <= io_imem_bits_xcpt_pf_inst;\n buf_xcpt_gf_inst <= io_imem_bits_xcpt_gf_inst;\n buf_xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst;\n buf_replay <= io_imem_bits_replay;\n ibufBTBResp_entry <= io_imem_bits_btb_entry;\n ibufBTBResp_bht_history <= io_imem_bits_btb_bht_history;\n end\n end\n RVCExpander exp (\n .io_in (inst),\n .io_out_bits (io_inst_0_bits_inst_bits),\n .io_out_rd (io_inst_0_bits_inst_rd),\n .io_out_rs1 (io_inst_0_bits_inst_rs1),\n .io_out_rs2 (io_inst_0_bits_inst_rs2),\n .io_out_rs3 (io_inst_0_bits_inst_rs3),\n .io_rvc (_exp_io_rvc)\n );\n assign io_imem_ready = io_inst_0_ready & _nBufValid_T & (_nICReady_T >= _nIC_T_2 | ~(_nBufValid_T_6[1]));\n assign io_pc = nBufValid ? buf_pc : io_imem_bits_pc;\n assign io_btb_resp_entry = _GEN_1 ? ibufBTBResp_entry : io_imem_bits_btb_entry;\n assign io_btb_resp_bht_history = _GEN_1 ? ibufBTBResp_bht_history : io_imem_bits_btb_bht_history;\n assign io_inst_0_valid = _valid_T_1[0] & full_insn;\n assign io_inst_0_bits_xcpt0_pf_inst = _bufMask_T_1[0] ? buf_xcpt_pf_inst : io_imem_bits_xcpt_pf_inst;\n assign io_inst_0_bits_xcpt0_gf_inst = _bufMask_T_1[0] ? buf_xcpt_gf_inst : io_imem_bits_xcpt_gf_inst;\n assign io_inst_0_bits_xcpt0_ae_inst = _bufMask_T_1[0] ? buf_xcpt_ae_inst : io_imem_bits_xcpt_ae_inst;\n assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_T_5[2];\n assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_T_5[1];\n assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_T_5[0];\n assign io_inst_0_bits_replay = ic_replay[0] | ~_exp_io_rvc & ic_replay[1];\n assign io_inst_0_bits_rvc = _exp_io_rvc;\n assign io_inst_0_bits_raw = inst;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRecFM_small_e5_s11(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input [16:0] io_a,\n input [16:0] io_b,\n input [2:0] io_roundingMode,\n output io_outValid_div,\n output io_outValid_sqrt,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;\n wire _divSqrtRecFNToRaw_io_invalidExc;\n wire _divSqrtRecFNToRaw_io_infiniteExc;\n wire _divSqrtRecFNToRaw_io_rawOut_isNaN;\n wire _divSqrtRecFNToRaw_io_rawOut_isInf;\n wire _divSqrtRecFNToRaw_io_rawOut_isZero;\n wire _divSqrtRecFNToRaw_io_rawOut_sign;\n wire [6:0] _divSqrtRecFNToRaw_io_rawOut_sExp;\n wire [13:0] _divSqrtRecFNToRaw_io_rawOut_sig;\n DivSqrtRecFMToRaw_small_e5_s11 divSqrtRecFNToRaw (\n .clock (clock),\n .reset (reset),\n .io_inReady (io_inReady),\n .io_inValid (io_inValid),\n .io_sqrtOp (io_sqrtOp),\n .io_a (io_a),\n .io_b (io_b),\n .io_roundingMode (io_roundingMode),\n .io_rawOutValid_div (io_outValid_div),\n .io_rawOutValid_sqrt (io_outValid_sqrt),\n .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN (\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),\n .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Re-order Buffer\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Bank the ROB, such that each \"dispatch\" group gets its own row of the ROB,\n// and each instruction in the dispatch group goes to a different bank.\n// We can compress out the PC by only saving the high-order bits!\n//\n// ASSUMPTIONS:\n// - dispatch groups are aligned to the PC.\n//\n// NOTES:\n// - Currently we do not compress out bubbles in the ROB.\n// - Exceptions are only taken when at the head of the commit bundle --\n// this helps deal with loads, stores, and refetch instructions.\n\npackage boom.v3.exu\n\nimport scala.math.ceil\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nimport boom.v3.common._\nimport boom.v3.util._\n\n/**\n * IO bundle to interact with the ROB\n *\n * @param numWakeupPorts number of wakeup ports to the rob\n * @param numFpuPorts number of fpu ports that will write back fflags\n */\nclass RobIo(\n val numWakeupPorts: Int,\n val numFpuPorts: Int\n )(implicit p: Parameters) extends BoomBundle\n{\n // Decode Stage\n // (Allocate, write instruction to ROB).\n val enq_valids = Input(Vec(coreWidth, Bool()))\n val enq_uops = Input(Vec(coreWidth, new MicroOp()))\n val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,\n // and stalling on the rest of it (don't\n // advance the tail ptr)\n\n val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))\n\n val rob_tail_idx = Output(UInt(robAddrSz.W))\n val rob_pnr_idx = Output(UInt(robAddrSz.W))\n val rob_head_idx = Output(UInt(robAddrSz.W))\n\n // Handle Branch Misspeculations\n val brupdate = Input(new BrUpdateInfo())\n\n // Write-back Stage\n // (Update of ROB)\n // Instruction is no longer busy and can be committed\n val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))\n\n // Unbusying ports for stores.\n // +1 for fpstdata\n val lsu_clr_bsy = Input(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))\n\n // Port for unmarking loads/stores as speculation hazards..\n val lsu_clr_unsafe = Input(Vec(memWidth, Valid(UInt(robAddrSz.W))))\n\n\n // Track side-effects for debug purposes.\n // Also need to know when loads write back, whereas we don't need loads to unbusy.\n val debug_wb_valids = Input(Vec(numWakeupPorts, Bool()))\n val debug_wb_wdata = Input(Vec(numWakeupPorts, Bits(xLen.W)))\n\n val fflags = Flipped(Vec(numFpuPorts, new ValidIO(new FFlagsResp())))\n val lxcpt = Input(Valid(new Exception())) // LSU\n val csr_replay = Input(Valid(new Exception()))\n\n // Commit stage (free resources; also used for rollback).\n val commit = Output(new CommitSignals())\n\n // tell the LSU that the head of the ROB is a load\n // (some loads can only execute once they are at the head of the ROB).\n val com_load_is_at_rob_head = Output(Bool())\n\n // Communicate exceptions to the CSRFile\n val com_xcpt = Valid(new CommitExceptionSignals())\n\n // Let the CSRFile stall us (e.g., wfi).\n val csr_stall = Input(Bool())\n\n // Flush signals (including exceptions, pipeline replays, and memory ordering failures)\n // to send to the frontend for redirection.\n val flush = Valid(new CommitExceptionSignals)\n\n // Stall Decode as appropriate\n val empty = Output(Bool())\n val ready = Output(Bool()) // ROB is busy unrolling rename state...\n\n // Stall the frontend if we know we will redirect the PC\n val flush_frontend = Output(Bool())\n\n\n val debug_tsc = Input(UInt(xLen.W))\n}\n\n/**\n * Bundle to send commit signals across processor\n */\nclass CommitSignals(implicit p: Parameters) extends BoomBundle\n{\n val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn\n val arch_valids = Vec(retireWidth, Bool())\n val uops = Vec(retireWidth, new MicroOp())\n val fflags = Valid(UInt(5.W))\n\n // These come a cycle later\n val debug_insts = Vec(retireWidth, UInt(32.W))\n\n // Perform rollback of rename state (in conjuction with commit.uops).\n val rbk_valids = Vec(retireWidth, Bool())\n val rollback = Bool()\n\n val debug_wdata = Vec(retireWidth, UInt(xLen.W))\n}\n\n/**\n * Bundle to communicate exceptions to CSRFile\n *\n * TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).\n */\nclass CommitExceptionSignals(implicit p: Parameters) extends BoomBundle\n{\n val ftq_idx = UInt(log2Ceil(ftqSz).W)\n val edge_inst = Bool()\n val is_rvc = Bool()\n val pc_lob = UInt(log2Ceil(icBlockBytes).W)\n val cause = UInt(xLen.W)\n val badvaddr = UInt(xLen.W)\n// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)\n// so the FTQ can drive the frontend with the correct redirected PC.\n val flush_typ = FlushTypes()\n}\n\n/**\n * Tell the frontend the type of flush so it can set up the next PC properly.\n */\nobject FlushTypes\n{\n def SZ = 3\n def apply() = UInt(SZ.W)\n def none = 0.U\n def xcpt = 1.U // An exception occurred.\n def eret = (2+1).U // Execute an environment return instruction.\n def refetch = 2.U // Flush and refetch the head instruction.\n def next = 4.U // Flush and fetch the next instruction.\n\n def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U\n def useSamePC(typ: UInt): Bool = typ === refetch\n def usePCplus4(typ: UInt): Bool = typ === next\n\n def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {\n val ret =\n Mux(!valid, none,\n Mux(i_eret, eret,\n Mux(i_xcpt, xcpt,\n Mux(i_refetch, refetch,\n next))))\n ret\n }\n}\n\n/**\n * Bundle of signals indicating that an exception occurred\n */\nclass Exception(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)\n val badvaddr = UInt(coreMaxAddrBits.W)\n}\n\n/**\n * Bundle for debug ROB signals\n * These should not be synthesized!\n */\nclass DebugRobSignals(implicit p: Parameters) extends BoomBundle\n{\n val state = UInt()\n val rob_head = UInt(robAddrSz.W)\n val rob_pnr = UInt(robAddrSz.W)\n val xcpt_val = Bool()\n val xcpt_uop = new MicroOp()\n val xcpt_badvaddr = UInt(xLen.W)\n}\n\n/**\n * Reorder Buffer to keep track of dependencies and inflight instructions\n *\n * @param numWakeupPorts number of wakeup ports to the ROB\n * @param numFpuPorts number of FPU units that will write back fflags\n */\nclass Rob(\n val numWakeupPorts: Int,\n val numFpuPorts: Int\n )(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new RobIo(numWakeupPorts, numFpuPorts))\n\n // ROB Finite State Machine\n val s_reset :: s_normal :: s_rollback :: s_wait_till_empty :: Nil = Enum(4)\n val rob_state = RegInit(s_reset)\n\n //commit entries at the head, and unwind exceptions from the tail\n val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)\n val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)\n\n val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))\n val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)\n\n val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))\n val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)\n\n val com_idx = Mux(rob_state === s_rollback, rob_tail, rob_head)\n\n\n val maybe_full = RegInit(false.B)\n val full = Wire(Bool())\n val empty = Wire(Bool())\n\n val will_commit = Wire(Vec(coreWidth, Bool()))\n val can_commit = Wire(Vec(coreWidth, Bool()))\n val can_throw_exception = Wire(Vec(coreWidth, Bool()))\n\n val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?\n val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?\n val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)\n val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))\n val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))\n val rob_head_fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))\n\n val exception_thrown = Wire(Bool())\n\n // exception info\n // TODO compress xcpt cause size. Most bits in the middle are zero.\n val r_xcpt_val = RegInit(false.B)\n val r_xcpt_uop = Reg(new MicroOp())\n val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))\n io.flush_frontend := r_xcpt_val\n\n //--------------------------------------------------\n // Utility\n\n def GetRowIdx(rob_idx: UInt): UInt = {\n if (coreWidth == 1) return rob_idx\n else return rob_idx >> log2Ceil(coreWidth).U\n }\n def GetBankIdx(rob_idx: UInt): UInt = {\n if(coreWidth == 1) { return 0.U }\n else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }\n }\n\n // **************************************************************************\n // Debug\n\n class DebugRobBundle extends BoomBundle\n {\n val valid = Bool()\n val busy = Bool()\n val unsafe = Bool()\n val uop = new MicroOp()\n val exception = Bool()\n }\n val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))\n debug_entry := DontCare // override in statements below\n\n // **************************************************************************\n // --------------------------------------------------------------------------\n // **************************************************************************\n\n // Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.\n val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))\n\n // Used for trace port, for debug purposes only\n val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))\n val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))\n val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))\n rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)\n val rob_debug_inst_rdata = rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))\n\n val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))\n\n for (w <- 0 until coreWidth) {\n def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)\n\n // one bank\n val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))\n val rob_bsy = Reg(Vec(numRobRows, Bool()))\n val rob_unsafe = Reg(Vec(numRobRows, Bool()))\n val rob_uop = Reg(Vec(numRobRows, new MicroOp()))\n val rob_exception = Reg(Vec(numRobRows, Bool()))\n val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?\n\n val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))\n\n //-----------------------------------------------\n // Dispatch: Add Entry to ROB\n\n rob_debug_inst_wmask(w) := io.enq_valids(w)\n rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst\n\n when (io.enq_valids(w)) {\n rob_val(rob_tail) := true.B\n rob_bsy(rob_tail) := !(io.enq_uops(w).is_fence ||\n io.enq_uops(w).is_fencei)\n rob_unsafe(rob_tail) := io.enq_uops(w).unsafe\n rob_uop(rob_tail) := io.enq_uops(w)\n rob_exception(rob_tail) := io.enq_uops(w).exception\n rob_predicated(rob_tail) := false.B\n rob_fflags(w)(rob_tail) := 0.U\n\n assert (rob_val(rob_tail) === false.B, \"[rob] overwriting a valid entry.\")\n assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)\n } .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {\n rob_uop(rob_tail).debug_inst := BUBBLE // just for debug purposes\n }\n\n //-----------------------------------------------\n // Writeback\n\n for (i <- 0 until numWakeupPorts) {\n val wb_resp = io.wb_resps(i)\n val wb_uop = wb_resp.bits.uop\n val row_idx = GetRowIdx(wb_uop.rob_idx)\n when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {\n rob_bsy(row_idx) := false.B\n rob_unsafe(row_idx) := false.B\n rob_predicated(row_idx) := wb_resp.bits.predicated\n }\n // TODO check that fflags aren't overwritten\n // TODO check that the wb is to a valid ROB entry, give it a time stamp\n// assert (!(wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx)) &&\n// wb_uop.fp_val && !(wb_uop.is_load || wb_uop.is_store) &&\n// rob_exc_cause(row_idx) =/= 0.U),\n// \"FP instruction writing back exc bits is overriding an existing exception.\")\n }\n\n // Stores have a separate method to clear busy bits\n for (clr_rob_idx <- io.lsu_clr_bsy) {\n when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {\n val cidx = GetRowIdx(clr_rob_idx.bits)\n rob_bsy(cidx) := false.B\n rob_unsafe(cidx) := false.B\n assert (rob_val(cidx) === true.B, \"[rob] store writing back to invalid entry.\")\n assert (rob_bsy(cidx) === true.B, \"[rob] store writing back to a not-busy entry.\")\n }\n }\n for (clr <- io.lsu_clr_unsafe) {\n when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {\n val cidx = GetRowIdx(clr.bits)\n rob_unsafe(cidx) := false.B\n }\n }\n\n\n //-----------------------------------------------\n // Accruing fflags\n for (i <- 0 until numFpuPorts) {\n val fflag_uop = io.fflags(i).bits.uop\n when (io.fflags(i).valid && MatchBank(GetBankIdx(fflag_uop.rob_idx))) {\n rob_fflags(w)(GetRowIdx(fflag_uop.rob_idx)) := io.fflags(i).bits.flags\n }\n }\n\n //-----------------------------------------------------\n // Exceptions\n // (the cause bits are compressed and stored elsewhere)\n\n when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {\n rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B\n when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {\n // In the case of a mem-ordering failure, the failing load will have been marked safe already.\n assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),\n \"An instruction marked as safe is causing an exception\")\n }\n }\n\n when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {\n rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B\n }\n can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)\n\n //-----------------------------------------------\n // Commit or Rollback\n\n // Can this instruction commit? (the check for exceptions/rob_state happens later).\n can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall\n\n\n // use the same \"com_uop\" for both rollback AND commit\n // Perform Commit\n io.commit.valids(w) := will_commit(w)\n io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(com_idx)\n io.commit.uops(w) := rob_uop(com_idx)\n io.commit.debug_insts(w) := rob_debug_inst_rdata(w)\n\n // We unbusy branches in b1, but its easier to mark the taken/provider src in b2,\n // when the branch might be committing\n when (io.brupdate.b2.mispredict &&\n MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&\n GetRowIdx(io.brupdate.b2.uop.rob_idx) === com_idx) {\n io.commit.uops(w).debug_fsrc := BSRC_C\n io.commit.uops(w).taken := io.brupdate.b2.taken\n }\n\n\n // Don't attempt to rollback the tail's row when the rob is full.\n val rbk_row = rob_state === s_rollback && !full\n\n io.commit.rbk_valids(w) := rbk_row && rob_val(com_idx) && !(enableCommitMapTable.B)\n io.commit.rollback := (rob_state === s_rollback)\n\n assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),\n \"com_valids and rbk_valids are mutually exclusive\")\n\n when (rbk_row) {\n rob_val(com_idx) := false.B\n rob_exception(com_idx) := false.B\n }\n\n if (enableCommitMapTable) {\n when (RegNext(exception_thrown)) {\n for (i <- 0 until numRobRows) {\n rob_val(i) := false.B\n rob_bsy(i) := false.B\n rob_uop(i).debug_inst := BUBBLE\n }\n }\n }\n\n // -----------------------------------------------\n // Kill speculated entries on branch mispredict\n for (i <- 0 until numRobRows) {\n val br_mask = rob_uop(i).br_mask\n\n //kill instruction if mispredict & br mask match\n when (IsKilledByBranch(io.brupdate, br_mask))\n {\n rob_val(i) := false.B\n rob_uop(i.U).debug_inst := BUBBLE\n } .elsewhen (rob_val(i)) {\n // clear speculation bit even on correct speculation\n rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)\n }\n }\n\n\n // Debug signal to figure out which prediction structure\n // or core resolved a branch correctly\n when (io.brupdate.b2.mispredict &&\n MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {\n rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C\n rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken\n }\n\n // -----------------------------------------------\n // Commit\n when (will_commit(w)) {\n rob_val(rob_head) := false.B\n }\n\n // -----------------------------------------------\n // Outputs\n rob_head_vals(w) := rob_val(rob_head)\n rob_tail_vals(w) := rob_val(rob_tail)\n rob_head_fflags(w) := rob_fflags(w)(rob_head)\n rob_head_uses_stq(w) := rob_uop(rob_head).uses_stq\n rob_head_uses_ldq(w) := rob_uop(rob_head).uses_ldq\n\n //------------------------------------------------\n // Invalid entries are safe; thrown exceptions are unsafe.\n for (i <- 0 until numRobRows) {\n rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))\n }\n // Read unsafe status of PNR row.\n rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))\n\n // -----------------------------------------------\n // debugging write ports that should not be synthesized\n when (will_commit(w)) {\n rob_uop(rob_head).debug_inst := BUBBLE\n } .elsewhen (rbk_row)\n {\n rob_uop(rob_tail).debug_inst := BUBBLE\n }\n\n //--------------------------------------------------\n // Debug: for debug purposes, track side-effects to all register destinations\n\n for (i <- 0 until numWakeupPorts) {\n val rob_idx = io.wb_resps(i).bits.uop.rob_idx\n when (io.debug_wb_valids(i) && MatchBank(GetBankIdx(rob_idx))) {\n rob_debug_wdata(GetRowIdx(rob_idx)) := io.debug_wb_wdata(i)\n }\n val temp_uop = rob_uop(GetRowIdx(rob_idx))\n\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n !rob_val(GetRowIdx(rob_idx))),\n \"[rob] writeback (\" + i + \") occurred to an invalid ROB entry.\")\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n !rob_bsy(GetRowIdx(rob_idx))),\n \"[rob] writeback (\" + i + \") occurred to a not-busy ROB entry.\")\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n temp_uop.ldst_val && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),\n \"[rob] writeback (\" + i + \") occurred to the wrong pdst.\")\n }\n io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)\n\n } //for (w <- 0 until coreWidth)\n\n // **************************************************************************\n // --------------------------------------------------------------------------\n // **************************************************************************\n\n // -----------------------------------------------\n // Commit Logic\n // need to take a \"can_commit\" array, and let the first can_commits commit\n // previous instructions may block the commit of younger instructions in the commit bundle\n // e.g., exception, or (valid && busy).\n // Finally, don't throw an exception if there are instructions in front of\n // it that want to commit (only throw exception when head of the bundle).\n\n var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))\n var will_throw_exception = false.B\n var block_xcpt = false.B\n\n for (w <- 0 until coreWidth) {\n will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception\n\n will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit\n block_commit = (rob_head_vals(w) &&\n (!can_commit(w) || can_throw_exception(w))) || block_commit\n block_xcpt = will_commit(w)\n }\n\n // Note: exception must be in the commit bundle.\n // Note: exception must be the first valid instruction in the commit bundle.\n exception_thrown := will_throw_exception\n val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)\n io.com_xcpt.valid := exception_thrown && !is_mini_exception\n io.com_xcpt.bits := DontCare\n io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause\n\n io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)\n val insn_sys_pc2epc =\n rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})\n\n val refetch_inst = exception_thrown || insn_sys_pc2epc\n val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)\n io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx\n io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst\n io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc\n io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob\n\n val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}\n val flush_commit = flush_commit_mask.reduce(_|_)\n val flush_val = exception_thrown || flush_commit\n\n assert(!(PopCount(flush_commit_mask) > 1.U),\n \"[rob] Can't commit multiple flush_on_commit instructions on one cycle\")\n\n val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))\n\n // delay a cycle for critical path considerations\n io.flush.valid := flush_val\n io.flush.bits := DontCare\n io.flush.bits.ftq_idx := flush_uop.ftq_idx\n io.flush.bits.pc_lob := flush_uop.pc_lob\n io.flush.bits.edge_inst := flush_uop.edge_inst\n io.flush.bits.is_rvc := flush_uop.is_rvc\n io.flush.bits.flush_typ := FlushTypes.getType(flush_val,\n exception_thrown && !is_mini_exception,\n flush_commit && flush_uop.uopc === uopERET,\n refetch_inst)\n\n\n // -----------------------------------------------\n // FP Exceptions\n // send fflags bits to the CSRFile to accrue\n\n val fflags_val = Wire(Vec(coreWidth, Bool()))\n val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))\n\n for (w <- 0 until coreWidth) {\n fflags_val(w) :=\n io.commit.valids(w) &&\n io.commit.uops(w).fp_val &&\n !io.commit.uops(w).uses_stq\n\n fflags(w) := Mux(fflags_val(w), rob_head_fflags(w), 0.U)\n\n assert (!(io.commit.valids(w) &&\n !io.commit.uops(w).fp_val &&\n rob_head_fflags(w) =/= 0.U),\n \"Committed non-FP instruction has non-zero fflag bits.\")\n assert (!(io.commit.valids(w) &&\n io.commit.uops(w).fp_val &&\n (io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&\n rob_head_fflags(w) =/= 0.U),\n \"Committed FP load or store has non-zero fflag bits.\")\n }\n io.commit.fflags.valid := fflags_val.reduce(_|_)\n io.commit.fflags.bits := fflags.reduce(_|_)\n\n // -----------------------------------------------\n // Exception Tracking Logic\n // only store the oldest exception, since only one can happen!\n\n val next_xcpt_uop = Wire(new MicroOp())\n next_xcpt_uop := r_xcpt_uop\n val enq_xcpts = Wire(Vec(coreWidth, Bool()))\n for (i <- 0 until coreWidth) {\n enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception\n }\n\n when (!(io.flush.valid || exception_thrown) && rob_state =/= s_rollback) {\n\n val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid\n val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)\n val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)\n\n when (new_xcpt_valid) {\n when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {\n r_xcpt_val := true.B\n next_xcpt_uop := new_xcpt.uop\n next_xcpt_uop.exc_cause := new_xcpt.cause\n r_xcpt_badvaddr := new_xcpt.badvaddr\n }\n } .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {\n val idx = enq_xcpts.indexWhere{i: Bool => i}\n\n // if no exception yet, dispatch exception wins\n r_xcpt_val := true.B\n next_xcpt_uop := io.enq_uops(idx)\n r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob\n\n }\n }\n\n r_xcpt_uop := next_xcpt_uop\n r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)\n when (io.flush.valid || IsKilledByBranch(io.brupdate, next_xcpt_uop)) {\n r_xcpt_val := false.B\n }\n\n assert (!(exception_thrown && !r_xcpt_val),\n \"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause\")\n\n assert (!(empty && r_xcpt_val),\n \"ROB is empty, but believes it has an outstanding exception.\")\n\n assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),\n \"ROB is throwing an exception, but the stored exception information's \" +\n \"rob_idx does not match the rob_head\")\n\n // -----------------------------------------------\n // ROB Head Logic\n\n // remember if we're still waiting on the rest of the dispatch packet, and prevent\n // the rob_head from advancing if it commits a partial parket before we\n // dispatch the rest of it.\n // update when committed ALL valid instructions in commit_bundle\n\n val rob_deq = WireInit(false.B)\n val r_partial_row = RegInit(false.B)\n\n when (io.enq_valids.reduce(_|_)) {\n r_partial_row := io.enq_partial_stall\n }\n\n val finished_committing_row =\n (io.commit.valids.asUInt =/= 0.U) &&\n ((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&\n !(r_partial_row && rob_head === rob_tail && !maybe_full)\n\n when (finished_committing_row) {\n rob_head := WrapInc(rob_head, numRobRows)\n rob_head_lsb := 0.U\n rob_deq := true.B\n } .otherwise {\n rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))\n }\n\n // -----------------------------------------------\n // ROB Point-of-No-Return (PNR) Logic\n // Acts as a second head, but only waits on busy instructions which might cause misspeculation.\n // TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?\n // Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.\n // Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.\n\n if (enableFastPNR) {\n val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)\n val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,\n AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),\n rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))\n rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)\n if (coreWidth > 1)\n rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)\n } else {\n // Distinguish between PNR being at head/tail when ROB is full.\n // Works the same as maybe_full tracking for the ROB tail.\n val pnr_maybe_at_tail = RegInit(false.B)\n\n val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty\n val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))\n when (empty && io.enq_valids.asUInt =/= 0.U) {\n // Unforunately for us, the ROB does not use its entries in monotonically\n // increasing order, even in the case of no exceptions. The edge case\n // arises when partial rows are enqueued and committed, leaving an empty\n // ROB.\n rob_pnr := rob_head\n rob_pnr_lsb := PriorityEncoder(io.enq_valids)\n } .elsewhen (safe_to_inc && do_inc_row) {\n rob_pnr := WrapInc(rob_pnr, numRobRows)\n rob_pnr_lsb := 0.U\n } .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))) {\n rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)\n } .elsewhen (safe_to_inc && !full && !empty) {\n rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))\n } .elsewhen (full && pnr_maybe_at_tail) {\n rob_pnr_lsb := 0.U\n }\n\n pnr_maybe_at_tail := !rob_deq && (do_inc_row || pnr_maybe_at_tail)\n }\n\n // Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.\n assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)\n\n // PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.\n assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)\n\n // -----------------------------------------------\n // ROB Tail Logic\n\n val rob_enq = WireInit(false.B)\n\n when (rob_state === s_rollback && (rob_tail =/= rob_head || maybe_full)) {\n // Rollback a row\n rob_tail := WrapDec(rob_tail, numRobRows)\n rob_tail_lsb := (coreWidth-1).U\n rob_deq := true.B\n } .elsewhen (rob_state === s_rollback && (rob_tail === rob_head) && !maybe_full) {\n // Rollback an entry\n rob_tail_lsb := rob_head_lsb\n } .elsewhen (io.brupdate.b2.mispredict) {\n rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)\n rob_tail_lsb := 0.U\n } .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {\n rob_tail := WrapInc(rob_tail, numRobRows)\n rob_tail_lsb := 0.U\n rob_enq := true.B\n } .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {\n rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))\n }\n\n\n if (enableCommitMapTable) {\n when (RegNext(exception_thrown)) {\n rob_tail := 0.U\n rob_tail_lsb := 0.U\n rob_head := 0.U\n rob_pnr := 0.U\n rob_pnr_lsb := 0.U\n }\n }\n\n // -----------------------------------------------\n // Full/Empty Logic\n // The ROB can be completely full, but only if it did not dispatch a row in the prior cycle.\n // I.E. at least one entry will be empty when in a steady state of dispatching and committing a row each cycle.\n // TODO should we add an extra 'parity bit' onto the ROB pointers to simplify this logic?\n\n maybe_full := !rob_deq && (rob_enq || maybe_full) || io.brupdate.b1.mispredict_mask =/= 0.U\n full := rob_tail === rob_head && maybe_full\n empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)\n\n io.rob_head_idx := rob_head_idx\n io.rob_tail_idx := rob_tail_idx\n io.rob_pnr_idx := rob_pnr_idx\n io.empty := empty\n io.ready := (rob_state === s_normal) && !full && !r_xcpt_val\n\n //-----------------------------------------------\n //-----------------------------------------------\n //-----------------------------------------------\n\n // ROB FSM\n if (!enableCommitMapTable) {\n switch (rob_state) {\n is (s_reset) {\n rob_state := s_normal\n }\n is (s_normal) {\n // Delay rollback 2 cycles so branch mispredictions can drain\n when (RegNext(RegNext(exception_thrown))) {\n rob_state := s_rollback\n } .otherwise {\n for (w <- 0 until coreWidth) {\n when (io.enq_valids(w) && io.enq_uops(w).is_unique) {\n rob_state := s_wait_till_empty\n }\n }\n }\n }\n is (s_rollback) {\n when (empty) {\n rob_state := s_normal\n }\n }\n is (s_wait_till_empty) {\n when (RegNext(exception_thrown)) {\n rob_state := s_rollback\n } .elsewhen (empty) {\n rob_state := s_normal\n }\n }\n }\n } else {\n switch (rob_state) {\n is (s_reset) {\n rob_state := s_normal\n }\n is (s_normal) {\n when (exception_thrown) {\n ; //rob_state := s_rollback\n } .otherwise {\n for (w <- 0 until coreWidth) {\n when (io.enq_valids(w) && io.enq_uops(w).is_unique) {\n rob_state := s_wait_till_empty\n }\n }\n }\n }\n is (s_rollback) {\n when (rob_tail_idx === rob_head_idx) {\n rob_state := s_normal\n }\n }\n is (s_wait_till_empty) {\n when (exception_thrown) {\n ; //rob_state := s_rollback\n } .elsewhen (rob_tail === rob_head) {\n rob_state := s_normal\n }\n }\n }\n }\n\n // -----------------------------------------------\n // Outputs\n\n io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&\n !will_commit.reduce(_||_))\n\n\n\n override def toString: String = BoomCoreStringPrefix(\n \"==ROB==\",\n \"Machine Width : \" + coreWidth,\n \"Rob Entries : \" + numRobEntries,\n \"Rob Rows : \" + numRobRows,\n \"Rob Row size : \" + log2Ceil(numRobRows),\n \"log2Ceil(coreWidth): \" + log2Ceil(coreWidth),\n \"FPU FFlag Ports : \" + numFpuPorts)\n}", + "response": "module Rob(\n input clock,\n input reset,\n input io_enq_valids_0,\n input [6:0] io_enq_uops_0_uopc,\n input [31:0] io_enq_uops_0_debug_inst,\n input io_enq_uops_0_is_rvc,\n input io_enq_uops_0_is_br,\n input io_enq_uops_0_is_jalr,\n input io_enq_uops_0_is_jal,\n input [7:0] io_enq_uops_0_br_mask,\n input [3:0] io_enq_uops_0_ftq_idx,\n input io_enq_uops_0_edge_inst,\n input [5:0] io_enq_uops_0_pc_lob,\n input [4:0] io_enq_uops_0_rob_idx,\n input [5:0] io_enq_uops_0_pdst,\n input [5:0] io_enq_uops_0_stale_pdst,\n input io_enq_uops_0_exception,\n input [63:0] io_enq_uops_0_exc_cause,\n input io_enq_uops_0_is_fence,\n input io_enq_uops_0_is_fencei,\n input io_enq_uops_0_uses_ldq,\n input io_enq_uops_0_uses_stq,\n input io_enq_uops_0_is_sys_pc2epc,\n input io_enq_uops_0_is_unique,\n input io_enq_uops_0_flush_on_commit,\n input [5:0] io_enq_uops_0_ldst,\n input io_enq_uops_0_ldst_val,\n input [1:0] io_enq_uops_0_dst_rtype,\n input io_enq_uops_0_fp_val,\n input [1:0] io_enq_uops_0_debug_fsrc,\n input io_enq_partial_stall,\n input [39:0] io_xcpt_fetch_pc,\n output [4:0] io_rob_tail_idx,\n output [4:0] io_rob_head_idx,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input [4:0] io_brupdate_b2_uop_rob_idx,\n input io_brupdate_b2_mispredict,\n input io_wb_resps_0_valid,\n input [4:0] io_wb_resps_0_bits_uop_rob_idx,\n input [5:0] io_wb_resps_0_bits_uop_pdst,\n input io_wb_resps_0_bits_predicated,\n input io_wb_resps_1_valid,\n input [4:0] io_wb_resps_1_bits_uop_rob_idx,\n input [5:0] io_wb_resps_1_bits_uop_pdst,\n input io_wb_resps_2_valid,\n input [4:0] io_wb_resps_2_bits_uop_rob_idx,\n input [5:0] io_wb_resps_2_bits_uop_pdst,\n input io_wb_resps_2_bits_predicated,\n input io_wb_resps_3_valid,\n input [4:0] io_wb_resps_3_bits_uop_rob_idx,\n input [5:0] io_wb_resps_3_bits_uop_pdst,\n input io_lsu_clr_bsy_0_valid,\n input [4:0] io_lsu_clr_bsy_0_bits,\n input io_lsu_clr_bsy_1_valid,\n input [4:0] io_lsu_clr_bsy_1_bits,\n input io_fflags_0_valid,\n input [4:0] io_fflags_0_bits_uop_rob_idx,\n input [4:0] io_fflags_0_bits_flags,\n input io_fflags_1_valid,\n input [4:0] io_fflags_1_bits_uop_rob_idx,\n input [4:0] io_fflags_1_bits_flags,\n input io_lxcpt_valid,\n input [7:0] io_lxcpt_bits_uop_br_mask,\n input [4:0] io_lxcpt_bits_uop_rob_idx,\n input [4:0] io_lxcpt_bits_cause,\n input [39:0] io_lxcpt_bits_badvaddr,\n output io_commit_valids_0,\n output io_commit_arch_valids_0,\n output io_commit_uops_0_is_br,\n output io_commit_uops_0_is_jalr,\n output io_commit_uops_0_is_jal,\n output [3:0] io_commit_uops_0_ftq_idx,\n output [5:0] io_commit_uops_0_pdst,\n output [5:0] io_commit_uops_0_stale_pdst,\n output io_commit_uops_0_is_fencei,\n output io_commit_uops_0_uses_ldq,\n output io_commit_uops_0_uses_stq,\n output [5:0] io_commit_uops_0_ldst,\n output io_commit_uops_0_ldst_val,\n output [1:0] io_commit_uops_0_dst_rtype,\n output [1:0] io_commit_uops_0_debug_fsrc,\n output io_commit_fflags_valid,\n output [4:0] io_commit_fflags_bits,\n output io_commit_rbk_valids_0,\n output io_commit_rollback,\n output io_com_load_is_at_rob_head,\n output io_com_xcpt_valid,\n output [3:0] io_com_xcpt_bits_ftq_idx,\n output io_com_xcpt_bits_edge_inst,\n output [5:0] io_com_xcpt_bits_pc_lob,\n output [63:0] io_com_xcpt_bits_cause,\n output [63:0] io_com_xcpt_bits_badvaddr,\n input io_csr_stall,\n output io_flush_valid,\n output [3:0] io_flush_bits_ftq_idx,\n output io_flush_bits_edge_inst,\n output io_flush_bits_is_rvc,\n output [5:0] io_flush_bits_pc_lob,\n output [2:0] io_flush_bits_flush_typ,\n output io_empty,\n output io_ready,\n output io_flush_frontend\n);\n\n wire empty;\n wire full;\n wire will_commit_0;\n reg [1:0] rob_state;\n reg [4:0] rob_head;\n reg [4:0] rob_tail;\n reg [4:0] rob_pnr;\n wire io_commit_rollback_0 = rob_state == 2'h2;\n wire [4:0] com_idx = io_commit_rollback_0 ? rob_tail : rob_head;\n reg maybe_full;\n reg r_xcpt_val;\n reg [7:0] r_xcpt_uop_br_mask;\n reg [4:0] r_xcpt_uop_rob_idx;\n reg [63:0] r_xcpt_uop_exc_cause;\n reg [39:0] r_xcpt_badvaddr;\n reg [4:0] rob_fflags_0_0;\n reg [4:0] rob_fflags_0_1;\n reg [4:0] rob_fflags_0_2;\n reg [4:0] rob_fflags_0_3;\n reg [4:0] rob_fflags_0_4;\n reg [4:0] rob_fflags_0_5;\n reg [4:0] rob_fflags_0_6;\n reg [4:0] rob_fflags_0_7;\n reg [4:0] rob_fflags_0_8;\n reg [4:0] rob_fflags_0_9;\n reg [4:0] rob_fflags_0_10;\n reg [4:0] rob_fflags_0_11;\n reg [4:0] rob_fflags_0_12;\n reg [4:0] rob_fflags_0_13;\n reg [4:0] rob_fflags_0_14;\n reg [4:0] rob_fflags_0_15;\n reg [4:0] rob_fflags_0_16;\n reg [4:0] rob_fflags_0_17;\n reg [4:0] rob_fflags_0_18;\n reg [4:0] rob_fflags_0_19;\n reg [4:0] rob_fflags_0_20;\n reg [4:0] rob_fflags_0_21;\n reg [4:0] rob_fflags_0_22;\n reg [4:0] rob_fflags_0_23;\n reg [4:0] rob_fflags_0_24;\n reg [4:0] rob_fflags_0_25;\n reg [4:0] rob_fflags_0_26;\n reg [4:0] rob_fflags_0_27;\n reg [4:0] rob_fflags_0_28;\n reg [4:0] rob_fflags_0_29;\n reg [4:0] rob_fflags_0_30;\n reg [4:0] rob_fflags_0_31;\n reg rob_val_0;\n reg rob_val_1;\n reg rob_val_2;\n reg rob_val_3;\n reg rob_val_4;\n reg rob_val_5;\n reg rob_val_6;\n reg rob_val_7;\n reg rob_val_8;\n reg rob_val_9;\n reg rob_val_10;\n reg rob_val_11;\n reg rob_val_12;\n reg rob_val_13;\n reg rob_val_14;\n reg rob_val_15;\n reg rob_val_16;\n reg rob_val_17;\n reg rob_val_18;\n reg rob_val_19;\n reg rob_val_20;\n reg rob_val_21;\n reg rob_val_22;\n reg rob_val_23;\n reg rob_val_24;\n reg rob_val_25;\n reg rob_val_26;\n reg rob_val_27;\n reg rob_val_28;\n reg rob_val_29;\n reg rob_val_30;\n reg rob_val_31;\n reg rob_bsy_0;\n reg rob_bsy_1;\n reg rob_bsy_2;\n reg rob_bsy_3;\n reg rob_bsy_4;\n reg rob_bsy_5;\n reg rob_bsy_6;\n reg rob_bsy_7;\n reg rob_bsy_8;\n reg rob_bsy_9;\n reg rob_bsy_10;\n reg rob_bsy_11;\n reg rob_bsy_12;\n reg rob_bsy_13;\n reg rob_bsy_14;\n reg rob_bsy_15;\n reg rob_bsy_16;\n reg rob_bsy_17;\n reg rob_bsy_18;\n reg rob_bsy_19;\n reg rob_bsy_20;\n reg rob_bsy_21;\n reg rob_bsy_22;\n reg rob_bsy_23;\n reg rob_bsy_24;\n reg rob_bsy_25;\n reg rob_bsy_26;\n reg rob_bsy_27;\n reg rob_bsy_28;\n reg rob_bsy_29;\n reg rob_bsy_30;\n reg rob_bsy_31;\n reg rob_unsafe_0;\n reg rob_unsafe_1;\n reg rob_unsafe_2;\n reg rob_unsafe_3;\n reg rob_unsafe_4;\n reg rob_unsafe_5;\n reg rob_unsafe_6;\n reg rob_unsafe_7;\n reg rob_unsafe_8;\n reg rob_unsafe_9;\n reg rob_unsafe_10;\n reg rob_unsafe_11;\n reg rob_unsafe_12;\n reg rob_unsafe_13;\n reg rob_unsafe_14;\n reg rob_unsafe_15;\n reg rob_unsafe_16;\n reg rob_unsafe_17;\n reg rob_unsafe_18;\n reg rob_unsafe_19;\n reg rob_unsafe_20;\n reg rob_unsafe_21;\n reg rob_unsafe_22;\n reg rob_unsafe_23;\n reg rob_unsafe_24;\n reg rob_unsafe_25;\n reg rob_unsafe_26;\n reg rob_unsafe_27;\n reg rob_unsafe_28;\n reg rob_unsafe_29;\n reg rob_unsafe_30;\n reg rob_unsafe_31;\n reg [6:0] rob_uop_0_uopc;\n reg rob_uop_0_is_rvc;\n reg rob_uop_0_is_br;\n reg rob_uop_0_is_jalr;\n reg rob_uop_0_is_jal;\n reg [7:0] rob_uop_0_br_mask;\n reg [3:0] rob_uop_0_ftq_idx;\n reg rob_uop_0_edge_inst;\n reg [5:0] rob_uop_0_pc_lob;\n reg [5:0] rob_uop_0_pdst;\n reg [5:0] rob_uop_0_stale_pdst;\n reg rob_uop_0_is_fencei;\n reg rob_uop_0_uses_ldq;\n reg rob_uop_0_uses_stq;\n reg rob_uop_0_is_sys_pc2epc;\n reg rob_uop_0_flush_on_commit;\n reg [5:0] rob_uop_0_ldst;\n reg rob_uop_0_ldst_val;\n reg [1:0] rob_uop_0_dst_rtype;\n reg rob_uop_0_fp_val;\n reg [1:0] rob_uop_0_debug_fsrc;\n reg [6:0] rob_uop_1_uopc;\n reg rob_uop_1_is_rvc;\n reg rob_uop_1_is_br;\n reg rob_uop_1_is_jalr;\n reg rob_uop_1_is_jal;\n reg [7:0] rob_uop_1_br_mask;\n reg [3:0] rob_uop_1_ftq_idx;\n reg rob_uop_1_edge_inst;\n reg [5:0] rob_uop_1_pc_lob;\n reg [5:0] rob_uop_1_pdst;\n reg [5:0] rob_uop_1_stale_pdst;\n reg rob_uop_1_is_fencei;\n reg rob_uop_1_uses_ldq;\n reg rob_uop_1_uses_stq;\n reg rob_uop_1_is_sys_pc2epc;\n reg rob_uop_1_flush_on_commit;\n reg [5:0] rob_uop_1_ldst;\n reg rob_uop_1_ldst_val;\n reg [1:0] rob_uop_1_dst_rtype;\n reg rob_uop_1_fp_val;\n reg [1:0] rob_uop_1_debug_fsrc;\n reg [6:0] rob_uop_2_uopc;\n reg rob_uop_2_is_rvc;\n reg rob_uop_2_is_br;\n reg rob_uop_2_is_jalr;\n reg rob_uop_2_is_jal;\n reg [7:0] rob_uop_2_br_mask;\n reg [3:0] rob_uop_2_ftq_idx;\n reg rob_uop_2_edge_inst;\n reg [5:0] rob_uop_2_pc_lob;\n reg [5:0] rob_uop_2_pdst;\n reg [5:0] rob_uop_2_stale_pdst;\n reg rob_uop_2_is_fencei;\n reg rob_uop_2_uses_ldq;\n reg rob_uop_2_uses_stq;\n reg rob_uop_2_is_sys_pc2epc;\n reg rob_uop_2_flush_on_commit;\n reg [5:0] rob_uop_2_ldst;\n reg rob_uop_2_ldst_val;\n reg [1:0] rob_uop_2_dst_rtype;\n reg rob_uop_2_fp_val;\n reg [1:0] rob_uop_2_debug_fsrc;\n reg [6:0] rob_uop_3_uopc;\n reg rob_uop_3_is_rvc;\n reg rob_uop_3_is_br;\n reg rob_uop_3_is_jalr;\n reg rob_uop_3_is_jal;\n reg [7:0] rob_uop_3_br_mask;\n reg [3:0] rob_uop_3_ftq_idx;\n reg rob_uop_3_edge_inst;\n reg [5:0] rob_uop_3_pc_lob;\n reg [5:0] rob_uop_3_pdst;\n reg [5:0] rob_uop_3_stale_pdst;\n reg rob_uop_3_is_fencei;\n reg rob_uop_3_uses_ldq;\n reg rob_uop_3_uses_stq;\n reg rob_uop_3_is_sys_pc2epc;\n reg rob_uop_3_flush_on_commit;\n reg [5:0] rob_uop_3_ldst;\n reg rob_uop_3_ldst_val;\n reg [1:0] rob_uop_3_dst_rtype;\n reg rob_uop_3_fp_val;\n reg [1:0] rob_uop_3_debug_fsrc;\n reg [6:0] rob_uop_4_uopc;\n reg rob_uop_4_is_rvc;\n reg rob_uop_4_is_br;\n reg rob_uop_4_is_jalr;\n reg rob_uop_4_is_jal;\n reg [7:0] rob_uop_4_br_mask;\n reg [3:0] rob_uop_4_ftq_idx;\n reg rob_uop_4_edge_inst;\n reg [5:0] rob_uop_4_pc_lob;\n reg [5:0] rob_uop_4_pdst;\n reg [5:0] rob_uop_4_stale_pdst;\n reg rob_uop_4_is_fencei;\n reg rob_uop_4_uses_ldq;\n reg rob_uop_4_uses_stq;\n reg rob_uop_4_is_sys_pc2epc;\n reg rob_uop_4_flush_on_commit;\n reg [5:0] rob_uop_4_ldst;\n reg rob_uop_4_ldst_val;\n reg [1:0] rob_uop_4_dst_rtype;\n reg rob_uop_4_fp_val;\n reg [1:0] rob_uop_4_debug_fsrc;\n reg [6:0] rob_uop_5_uopc;\n reg rob_uop_5_is_rvc;\n reg rob_uop_5_is_br;\n reg rob_uop_5_is_jalr;\n reg rob_uop_5_is_jal;\n reg [7:0] rob_uop_5_br_mask;\n reg [3:0] rob_uop_5_ftq_idx;\n reg rob_uop_5_edge_inst;\n reg [5:0] rob_uop_5_pc_lob;\n reg [5:0] rob_uop_5_pdst;\n reg [5:0] rob_uop_5_stale_pdst;\n reg rob_uop_5_is_fencei;\n reg rob_uop_5_uses_ldq;\n reg rob_uop_5_uses_stq;\n reg rob_uop_5_is_sys_pc2epc;\n reg rob_uop_5_flush_on_commit;\n reg [5:0] rob_uop_5_ldst;\n reg rob_uop_5_ldst_val;\n reg [1:0] rob_uop_5_dst_rtype;\n reg rob_uop_5_fp_val;\n reg [1:0] rob_uop_5_debug_fsrc;\n reg [6:0] rob_uop_6_uopc;\n reg rob_uop_6_is_rvc;\n reg rob_uop_6_is_br;\n reg rob_uop_6_is_jalr;\n reg rob_uop_6_is_jal;\n reg [7:0] rob_uop_6_br_mask;\n reg [3:0] rob_uop_6_ftq_idx;\n reg rob_uop_6_edge_inst;\n reg [5:0] rob_uop_6_pc_lob;\n reg [5:0] rob_uop_6_pdst;\n reg [5:0] rob_uop_6_stale_pdst;\n reg rob_uop_6_is_fencei;\n reg rob_uop_6_uses_ldq;\n reg rob_uop_6_uses_stq;\n reg rob_uop_6_is_sys_pc2epc;\n reg rob_uop_6_flush_on_commit;\n reg [5:0] rob_uop_6_ldst;\n reg rob_uop_6_ldst_val;\n reg [1:0] rob_uop_6_dst_rtype;\n reg rob_uop_6_fp_val;\n reg [1:0] rob_uop_6_debug_fsrc;\n reg [6:0] rob_uop_7_uopc;\n reg rob_uop_7_is_rvc;\n reg rob_uop_7_is_br;\n reg rob_uop_7_is_jalr;\n reg rob_uop_7_is_jal;\n reg [7:0] rob_uop_7_br_mask;\n reg [3:0] rob_uop_7_ftq_idx;\n reg rob_uop_7_edge_inst;\n reg [5:0] rob_uop_7_pc_lob;\n reg [5:0] rob_uop_7_pdst;\n reg [5:0] rob_uop_7_stale_pdst;\n reg rob_uop_7_is_fencei;\n reg rob_uop_7_uses_ldq;\n reg rob_uop_7_uses_stq;\n reg rob_uop_7_is_sys_pc2epc;\n reg rob_uop_7_flush_on_commit;\n reg [5:0] rob_uop_7_ldst;\n reg rob_uop_7_ldst_val;\n reg [1:0] rob_uop_7_dst_rtype;\n reg rob_uop_7_fp_val;\n reg [1:0] rob_uop_7_debug_fsrc;\n reg [6:0] rob_uop_8_uopc;\n reg rob_uop_8_is_rvc;\n reg rob_uop_8_is_br;\n reg rob_uop_8_is_jalr;\n reg rob_uop_8_is_jal;\n reg [7:0] rob_uop_8_br_mask;\n reg [3:0] rob_uop_8_ftq_idx;\n reg rob_uop_8_edge_inst;\n reg [5:0] rob_uop_8_pc_lob;\n reg [5:0] rob_uop_8_pdst;\n reg [5:0] rob_uop_8_stale_pdst;\n reg rob_uop_8_is_fencei;\n reg rob_uop_8_uses_ldq;\n reg rob_uop_8_uses_stq;\n reg rob_uop_8_is_sys_pc2epc;\n reg rob_uop_8_flush_on_commit;\n reg [5:0] rob_uop_8_ldst;\n reg rob_uop_8_ldst_val;\n reg [1:0] rob_uop_8_dst_rtype;\n reg rob_uop_8_fp_val;\n reg [1:0] rob_uop_8_debug_fsrc;\n reg [6:0] rob_uop_9_uopc;\n reg rob_uop_9_is_rvc;\n reg rob_uop_9_is_br;\n reg rob_uop_9_is_jalr;\n reg rob_uop_9_is_jal;\n reg [7:0] rob_uop_9_br_mask;\n reg [3:0] rob_uop_9_ftq_idx;\n reg rob_uop_9_edge_inst;\n reg [5:0] rob_uop_9_pc_lob;\n reg [5:0] rob_uop_9_pdst;\n reg [5:0] rob_uop_9_stale_pdst;\n reg rob_uop_9_is_fencei;\n reg rob_uop_9_uses_ldq;\n reg rob_uop_9_uses_stq;\n reg rob_uop_9_is_sys_pc2epc;\n reg rob_uop_9_flush_on_commit;\n reg [5:0] rob_uop_9_ldst;\n reg rob_uop_9_ldst_val;\n reg [1:0] rob_uop_9_dst_rtype;\n reg rob_uop_9_fp_val;\n reg [1:0] rob_uop_9_debug_fsrc;\n reg [6:0] rob_uop_10_uopc;\n reg rob_uop_10_is_rvc;\n reg rob_uop_10_is_br;\n reg rob_uop_10_is_jalr;\n reg rob_uop_10_is_jal;\n reg [7:0] rob_uop_10_br_mask;\n reg [3:0] rob_uop_10_ftq_idx;\n reg rob_uop_10_edge_inst;\n reg [5:0] rob_uop_10_pc_lob;\n reg [5:0] rob_uop_10_pdst;\n reg [5:0] rob_uop_10_stale_pdst;\n reg rob_uop_10_is_fencei;\n reg rob_uop_10_uses_ldq;\n reg rob_uop_10_uses_stq;\n reg rob_uop_10_is_sys_pc2epc;\n reg rob_uop_10_flush_on_commit;\n reg [5:0] rob_uop_10_ldst;\n reg rob_uop_10_ldst_val;\n reg [1:0] rob_uop_10_dst_rtype;\n reg rob_uop_10_fp_val;\n reg [1:0] rob_uop_10_debug_fsrc;\n reg [6:0] rob_uop_11_uopc;\n reg rob_uop_11_is_rvc;\n reg rob_uop_11_is_br;\n reg rob_uop_11_is_jalr;\n reg rob_uop_11_is_jal;\n reg [7:0] rob_uop_11_br_mask;\n reg [3:0] rob_uop_11_ftq_idx;\n reg rob_uop_11_edge_inst;\n reg [5:0] rob_uop_11_pc_lob;\n reg [5:0] rob_uop_11_pdst;\n reg [5:0] rob_uop_11_stale_pdst;\n reg rob_uop_11_is_fencei;\n reg rob_uop_11_uses_ldq;\n reg rob_uop_11_uses_stq;\n reg rob_uop_11_is_sys_pc2epc;\n reg rob_uop_11_flush_on_commit;\n reg [5:0] rob_uop_11_ldst;\n reg rob_uop_11_ldst_val;\n reg [1:0] rob_uop_11_dst_rtype;\n reg rob_uop_11_fp_val;\n reg [1:0] rob_uop_11_debug_fsrc;\n reg [6:0] rob_uop_12_uopc;\n reg rob_uop_12_is_rvc;\n reg rob_uop_12_is_br;\n reg rob_uop_12_is_jalr;\n reg rob_uop_12_is_jal;\n reg [7:0] rob_uop_12_br_mask;\n reg [3:0] rob_uop_12_ftq_idx;\n reg rob_uop_12_edge_inst;\n reg [5:0] rob_uop_12_pc_lob;\n reg [5:0] rob_uop_12_pdst;\n reg [5:0] rob_uop_12_stale_pdst;\n reg rob_uop_12_is_fencei;\n reg rob_uop_12_uses_ldq;\n reg rob_uop_12_uses_stq;\n reg rob_uop_12_is_sys_pc2epc;\n reg rob_uop_12_flush_on_commit;\n reg [5:0] rob_uop_12_ldst;\n reg rob_uop_12_ldst_val;\n reg [1:0] rob_uop_12_dst_rtype;\n reg rob_uop_12_fp_val;\n reg [1:0] rob_uop_12_debug_fsrc;\n reg [6:0] rob_uop_13_uopc;\n reg rob_uop_13_is_rvc;\n reg rob_uop_13_is_br;\n reg rob_uop_13_is_jalr;\n reg rob_uop_13_is_jal;\n reg [7:0] rob_uop_13_br_mask;\n reg [3:0] rob_uop_13_ftq_idx;\n reg rob_uop_13_edge_inst;\n reg [5:0] rob_uop_13_pc_lob;\n reg [5:0] rob_uop_13_pdst;\n reg [5:0] rob_uop_13_stale_pdst;\n reg rob_uop_13_is_fencei;\n reg rob_uop_13_uses_ldq;\n reg rob_uop_13_uses_stq;\n reg rob_uop_13_is_sys_pc2epc;\n reg rob_uop_13_flush_on_commit;\n reg [5:0] rob_uop_13_ldst;\n reg rob_uop_13_ldst_val;\n reg [1:0] rob_uop_13_dst_rtype;\n reg rob_uop_13_fp_val;\n reg [1:0] rob_uop_13_debug_fsrc;\n reg [6:0] rob_uop_14_uopc;\n reg rob_uop_14_is_rvc;\n reg rob_uop_14_is_br;\n reg rob_uop_14_is_jalr;\n reg rob_uop_14_is_jal;\n reg [7:0] rob_uop_14_br_mask;\n reg [3:0] rob_uop_14_ftq_idx;\n reg rob_uop_14_edge_inst;\n reg [5:0] rob_uop_14_pc_lob;\n reg [5:0] rob_uop_14_pdst;\n reg [5:0] rob_uop_14_stale_pdst;\n reg rob_uop_14_is_fencei;\n reg rob_uop_14_uses_ldq;\n reg rob_uop_14_uses_stq;\n reg rob_uop_14_is_sys_pc2epc;\n reg rob_uop_14_flush_on_commit;\n reg [5:0] rob_uop_14_ldst;\n reg rob_uop_14_ldst_val;\n reg [1:0] rob_uop_14_dst_rtype;\n reg rob_uop_14_fp_val;\n reg [1:0] rob_uop_14_debug_fsrc;\n reg [6:0] rob_uop_15_uopc;\n reg rob_uop_15_is_rvc;\n reg rob_uop_15_is_br;\n reg rob_uop_15_is_jalr;\n reg rob_uop_15_is_jal;\n reg [7:0] rob_uop_15_br_mask;\n reg [3:0] rob_uop_15_ftq_idx;\n reg rob_uop_15_edge_inst;\n reg [5:0] rob_uop_15_pc_lob;\n reg [5:0] rob_uop_15_pdst;\n reg [5:0] rob_uop_15_stale_pdst;\n reg rob_uop_15_is_fencei;\n reg rob_uop_15_uses_ldq;\n reg rob_uop_15_uses_stq;\n reg rob_uop_15_is_sys_pc2epc;\n reg rob_uop_15_flush_on_commit;\n reg [5:0] rob_uop_15_ldst;\n reg rob_uop_15_ldst_val;\n reg [1:0] rob_uop_15_dst_rtype;\n reg rob_uop_15_fp_val;\n reg [1:0] rob_uop_15_debug_fsrc;\n reg [6:0] rob_uop_16_uopc;\n reg rob_uop_16_is_rvc;\n reg rob_uop_16_is_br;\n reg rob_uop_16_is_jalr;\n reg rob_uop_16_is_jal;\n reg [7:0] rob_uop_16_br_mask;\n reg [3:0] rob_uop_16_ftq_idx;\n reg rob_uop_16_edge_inst;\n reg [5:0] rob_uop_16_pc_lob;\n reg [5:0] rob_uop_16_pdst;\n reg [5:0] rob_uop_16_stale_pdst;\n reg rob_uop_16_is_fencei;\n reg rob_uop_16_uses_ldq;\n reg rob_uop_16_uses_stq;\n reg rob_uop_16_is_sys_pc2epc;\n reg rob_uop_16_flush_on_commit;\n reg [5:0] rob_uop_16_ldst;\n reg rob_uop_16_ldst_val;\n reg [1:0] rob_uop_16_dst_rtype;\n reg rob_uop_16_fp_val;\n reg [1:0] rob_uop_16_debug_fsrc;\n reg [6:0] rob_uop_17_uopc;\n reg rob_uop_17_is_rvc;\n reg rob_uop_17_is_br;\n reg rob_uop_17_is_jalr;\n reg rob_uop_17_is_jal;\n reg [7:0] rob_uop_17_br_mask;\n reg [3:0] rob_uop_17_ftq_idx;\n reg rob_uop_17_edge_inst;\n reg [5:0] rob_uop_17_pc_lob;\n reg [5:0] rob_uop_17_pdst;\n reg [5:0] rob_uop_17_stale_pdst;\n reg rob_uop_17_is_fencei;\n reg rob_uop_17_uses_ldq;\n reg rob_uop_17_uses_stq;\n reg rob_uop_17_is_sys_pc2epc;\n reg rob_uop_17_flush_on_commit;\n reg [5:0] rob_uop_17_ldst;\n reg rob_uop_17_ldst_val;\n reg [1:0] rob_uop_17_dst_rtype;\n reg rob_uop_17_fp_val;\n reg [1:0] rob_uop_17_debug_fsrc;\n reg [6:0] rob_uop_18_uopc;\n reg rob_uop_18_is_rvc;\n reg rob_uop_18_is_br;\n reg rob_uop_18_is_jalr;\n reg rob_uop_18_is_jal;\n reg [7:0] rob_uop_18_br_mask;\n reg [3:0] rob_uop_18_ftq_idx;\n reg rob_uop_18_edge_inst;\n reg [5:0] rob_uop_18_pc_lob;\n reg [5:0] rob_uop_18_pdst;\n reg [5:0] rob_uop_18_stale_pdst;\n reg rob_uop_18_is_fencei;\n reg rob_uop_18_uses_ldq;\n reg rob_uop_18_uses_stq;\n reg rob_uop_18_is_sys_pc2epc;\n reg rob_uop_18_flush_on_commit;\n reg [5:0] rob_uop_18_ldst;\n reg rob_uop_18_ldst_val;\n reg [1:0] rob_uop_18_dst_rtype;\n reg rob_uop_18_fp_val;\n reg [1:0] rob_uop_18_debug_fsrc;\n reg [6:0] rob_uop_19_uopc;\n reg rob_uop_19_is_rvc;\n reg rob_uop_19_is_br;\n reg rob_uop_19_is_jalr;\n reg rob_uop_19_is_jal;\n reg [7:0] rob_uop_19_br_mask;\n reg [3:0] rob_uop_19_ftq_idx;\n reg rob_uop_19_edge_inst;\n reg [5:0] rob_uop_19_pc_lob;\n reg [5:0] rob_uop_19_pdst;\n reg [5:0] rob_uop_19_stale_pdst;\n reg rob_uop_19_is_fencei;\n reg rob_uop_19_uses_ldq;\n reg rob_uop_19_uses_stq;\n reg rob_uop_19_is_sys_pc2epc;\n reg rob_uop_19_flush_on_commit;\n reg [5:0] rob_uop_19_ldst;\n reg rob_uop_19_ldst_val;\n reg [1:0] rob_uop_19_dst_rtype;\n reg rob_uop_19_fp_val;\n reg [1:0] rob_uop_19_debug_fsrc;\n reg [6:0] rob_uop_20_uopc;\n reg rob_uop_20_is_rvc;\n reg rob_uop_20_is_br;\n reg rob_uop_20_is_jalr;\n reg rob_uop_20_is_jal;\n reg [7:0] rob_uop_20_br_mask;\n reg [3:0] rob_uop_20_ftq_idx;\n reg rob_uop_20_edge_inst;\n reg [5:0] rob_uop_20_pc_lob;\n reg [5:0] rob_uop_20_pdst;\n reg [5:0] rob_uop_20_stale_pdst;\n reg rob_uop_20_is_fencei;\n reg rob_uop_20_uses_ldq;\n reg rob_uop_20_uses_stq;\n reg rob_uop_20_is_sys_pc2epc;\n reg rob_uop_20_flush_on_commit;\n reg [5:0] rob_uop_20_ldst;\n reg rob_uop_20_ldst_val;\n reg [1:0] rob_uop_20_dst_rtype;\n reg rob_uop_20_fp_val;\n reg [1:0] rob_uop_20_debug_fsrc;\n reg [6:0] rob_uop_21_uopc;\n reg rob_uop_21_is_rvc;\n reg rob_uop_21_is_br;\n reg rob_uop_21_is_jalr;\n reg rob_uop_21_is_jal;\n reg [7:0] rob_uop_21_br_mask;\n reg [3:0] rob_uop_21_ftq_idx;\n reg rob_uop_21_edge_inst;\n reg [5:0] rob_uop_21_pc_lob;\n reg [5:0] rob_uop_21_pdst;\n reg [5:0] rob_uop_21_stale_pdst;\n reg rob_uop_21_is_fencei;\n reg rob_uop_21_uses_ldq;\n reg rob_uop_21_uses_stq;\n reg rob_uop_21_is_sys_pc2epc;\n reg rob_uop_21_flush_on_commit;\n reg [5:0] rob_uop_21_ldst;\n reg rob_uop_21_ldst_val;\n reg [1:0] rob_uop_21_dst_rtype;\n reg rob_uop_21_fp_val;\n reg [1:0] rob_uop_21_debug_fsrc;\n reg [6:0] rob_uop_22_uopc;\n reg rob_uop_22_is_rvc;\n reg rob_uop_22_is_br;\n reg rob_uop_22_is_jalr;\n reg rob_uop_22_is_jal;\n reg [7:0] rob_uop_22_br_mask;\n reg [3:0] rob_uop_22_ftq_idx;\n reg rob_uop_22_edge_inst;\n reg [5:0] rob_uop_22_pc_lob;\n reg [5:0] rob_uop_22_pdst;\n reg [5:0] rob_uop_22_stale_pdst;\n reg rob_uop_22_is_fencei;\n reg rob_uop_22_uses_ldq;\n reg rob_uop_22_uses_stq;\n reg rob_uop_22_is_sys_pc2epc;\n reg rob_uop_22_flush_on_commit;\n reg [5:0] rob_uop_22_ldst;\n reg rob_uop_22_ldst_val;\n reg [1:0] rob_uop_22_dst_rtype;\n reg rob_uop_22_fp_val;\n reg [1:0] rob_uop_22_debug_fsrc;\n reg [6:0] rob_uop_23_uopc;\n reg rob_uop_23_is_rvc;\n reg rob_uop_23_is_br;\n reg rob_uop_23_is_jalr;\n reg rob_uop_23_is_jal;\n reg [7:0] rob_uop_23_br_mask;\n reg [3:0] rob_uop_23_ftq_idx;\n reg rob_uop_23_edge_inst;\n reg [5:0] rob_uop_23_pc_lob;\n reg [5:0] rob_uop_23_pdst;\n reg [5:0] rob_uop_23_stale_pdst;\n reg rob_uop_23_is_fencei;\n reg rob_uop_23_uses_ldq;\n reg rob_uop_23_uses_stq;\n reg rob_uop_23_is_sys_pc2epc;\n reg rob_uop_23_flush_on_commit;\n reg [5:0] rob_uop_23_ldst;\n reg rob_uop_23_ldst_val;\n reg [1:0] rob_uop_23_dst_rtype;\n reg rob_uop_23_fp_val;\n reg [1:0] rob_uop_23_debug_fsrc;\n reg [6:0] rob_uop_24_uopc;\n reg rob_uop_24_is_rvc;\n reg rob_uop_24_is_br;\n reg rob_uop_24_is_jalr;\n reg rob_uop_24_is_jal;\n reg [7:0] rob_uop_24_br_mask;\n reg [3:0] rob_uop_24_ftq_idx;\n reg rob_uop_24_edge_inst;\n reg [5:0] rob_uop_24_pc_lob;\n reg [5:0] rob_uop_24_pdst;\n reg [5:0] rob_uop_24_stale_pdst;\n reg rob_uop_24_is_fencei;\n reg rob_uop_24_uses_ldq;\n reg rob_uop_24_uses_stq;\n reg rob_uop_24_is_sys_pc2epc;\n reg rob_uop_24_flush_on_commit;\n reg [5:0] rob_uop_24_ldst;\n reg rob_uop_24_ldst_val;\n reg [1:0] rob_uop_24_dst_rtype;\n reg rob_uop_24_fp_val;\n reg [1:0] rob_uop_24_debug_fsrc;\n reg [6:0] rob_uop_25_uopc;\n reg rob_uop_25_is_rvc;\n reg rob_uop_25_is_br;\n reg rob_uop_25_is_jalr;\n reg rob_uop_25_is_jal;\n reg [7:0] rob_uop_25_br_mask;\n reg [3:0] rob_uop_25_ftq_idx;\n reg rob_uop_25_edge_inst;\n reg [5:0] rob_uop_25_pc_lob;\n reg [5:0] rob_uop_25_pdst;\n reg [5:0] rob_uop_25_stale_pdst;\n reg rob_uop_25_is_fencei;\n reg rob_uop_25_uses_ldq;\n reg rob_uop_25_uses_stq;\n reg rob_uop_25_is_sys_pc2epc;\n reg rob_uop_25_flush_on_commit;\n reg [5:0] rob_uop_25_ldst;\n reg rob_uop_25_ldst_val;\n reg [1:0] rob_uop_25_dst_rtype;\n reg rob_uop_25_fp_val;\n reg [1:0] rob_uop_25_debug_fsrc;\n reg [6:0] rob_uop_26_uopc;\n reg rob_uop_26_is_rvc;\n reg rob_uop_26_is_br;\n reg rob_uop_26_is_jalr;\n reg rob_uop_26_is_jal;\n reg [7:0] rob_uop_26_br_mask;\n reg [3:0] rob_uop_26_ftq_idx;\n reg rob_uop_26_edge_inst;\n reg [5:0] rob_uop_26_pc_lob;\n reg [5:0] rob_uop_26_pdst;\n reg [5:0] rob_uop_26_stale_pdst;\n reg rob_uop_26_is_fencei;\n reg rob_uop_26_uses_ldq;\n reg rob_uop_26_uses_stq;\n reg rob_uop_26_is_sys_pc2epc;\n reg rob_uop_26_flush_on_commit;\n reg [5:0] rob_uop_26_ldst;\n reg rob_uop_26_ldst_val;\n reg [1:0] rob_uop_26_dst_rtype;\n reg rob_uop_26_fp_val;\n reg [1:0] rob_uop_26_debug_fsrc;\n reg [6:0] rob_uop_27_uopc;\n reg rob_uop_27_is_rvc;\n reg rob_uop_27_is_br;\n reg rob_uop_27_is_jalr;\n reg rob_uop_27_is_jal;\n reg [7:0] rob_uop_27_br_mask;\n reg [3:0] rob_uop_27_ftq_idx;\n reg rob_uop_27_edge_inst;\n reg [5:0] rob_uop_27_pc_lob;\n reg [5:0] rob_uop_27_pdst;\n reg [5:0] rob_uop_27_stale_pdst;\n reg rob_uop_27_is_fencei;\n reg rob_uop_27_uses_ldq;\n reg rob_uop_27_uses_stq;\n reg rob_uop_27_is_sys_pc2epc;\n reg rob_uop_27_flush_on_commit;\n reg [5:0] rob_uop_27_ldst;\n reg rob_uop_27_ldst_val;\n reg [1:0] rob_uop_27_dst_rtype;\n reg rob_uop_27_fp_val;\n reg [1:0] rob_uop_27_debug_fsrc;\n reg [6:0] rob_uop_28_uopc;\n reg rob_uop_28_is_rvc;\n reg rob_uop_28_is_br;\n reg rob_uop_28_is_jalr;\n reg rob_uop_28_is_jal;\n reg [7:0] rob_uop_28_br_mask;\n reg [3:0] rob_uop_28_ftq_idx;\n reg rob_uop_28_edge_inst;\n reg [5:0] rob_uop_28_pc_lob;\n reg [5:0] rob_uop_28_pdst;\n reg [5:0] rob_uop_28_stale_pdst;\n reg rob_uop_28_is_fencei;\n reg rob_uop_28_uses_ldq;\n reg rob_uop_28_uses_stq;\n reg rob_uop_28_is_sys_pc2epc;\n reg rob_uop_28_flush_on_commit;\n reg [5:0] rob_uop_28_ldst;\n reg rob_uop_28_ldst_val;\n reg [1:0] rob_uop_28_dst_rtype;\n reg rob_uop_28_fp_val;\n reg [1:0] rob_uop_28_debug_fsrc;\n reg [6:0] rob_uop_29_uopc;\n reg rob_uop_29_is_rvc;\n reg rob_uop_29_is_br;\n reg rob_uop_29_is_jalr;\n reg rob_uop_29_is_jal;\n reg [7:0] rob_uop_29_br_mask;\n reg [3:0] rob_uop_29_ftq_idx;\n reg rob_uop_29_edge_inst;\n reg [5:0] rob_uop_29_pc_lob;\n reg [5:0] rob_uop_29_pdst;\n reg [5:0] rob_uop_29_stale_pdst;\n reg rob_uop_29_is_fencei;\n reg rob_uop_29_uses_ldq;\n reg rob_uop_29_uses_stq;\n reg rob_uop_29_is_sys_pc2epc;\n reg rob_uop_29_flush_on_commit;\n reg [5:0] rob_uop_29_ldst;\n reg rob_uop_29_ldst_val;\n reg [1:0] rob_uop_29_dst_rtype;\n reg rob_uop_29_fp_val;\n reg [1:0] rob_uop_29_debug_fsrc;\n reg [6:0] rob_uop_30_uopc;\n reg rob_uop_30_is_rvc;\n reg rob_uop_30_is_br;\n reg rob_uop_30_is_jalr;\n reg rob_uop_30_is_jal;\n reg [7:0] rob_uop_30_br_mask;\n reg [3:0] rob_uop_30_ftq_idx;\n reg rob_uop_30_edge_inst;\n reg [5:0] rob_uop_30_pc_lob;\n reg [5:0] rob_uop_30_pdst;\n reg [5:0] rob_uop_30_stale_pdst;\n reg rob_uop_30_is_fencei;\n reg rob_uop_30_uses_ldq;\n reg rob_uop_30_uses_stq;\n reg rob_uop_30_is_sys_pc2epc;\n reg rob_uop_30_flush_on_commit;\n reg [5:0] rob_uop_30_ldst;\n reg rob_uop_30_ldst_val;\n reg [1:0] rob_uop_30_dst_rtype;\n reg rob_uop_30_fp_val;\n reg [1:0] rob_uop_30_debug_fsrc;\n reg [6:0] rob_uop_31_uopc;\n reg rob_uop_31_is_rvc;\n reg rob_uop_31_is_br;\n reg rob_uop_31_is_jalr;\n reg rob_uop_31_is_jal;\n reg [7:0] rob_uop_31_br_mask;\n reg [3:0] rob_uop_31_ftq_idx;\n reg rob_uop_31_edge_inst;\n reg [5:0] rob_uop_31_pc_lob;\n reg [5:0] rob_uop_31_pdst;\n reg [5:0] rob_uop_31_stale_pdst;\n reg rob_uop_31_is_fencei;\n reg rob_uop_31_uses_ldq;\n reg rob_uop_31_uses_stq;\n reg rob_uop_31_is_sys_pc2epc;\n reg rob_uop_31_flush_on_commit;\n reg [5:0] rob_uop_31_ldst;\n reg rob_uop_31_ldst_val;\n reg [1:0] rob_uop_31_dst_rtype;\n reg rob_uop_31_fp_val;\n reg [1:0] rob_uop_31_debug_fsrc;\n reg rob_exception_0;\n reg rob_exception_1;\n reg rob_exception_2;\n reg rob_exception_3;\n reg rob_exception_4;\n reg rob_exception_5;\n reg rob_exception_6;\n reg rob_exception_7;\n reg rob_exception_8;\n reg rob_exception_9;\n reg rob_exception_10;\n reg rob_exception_11;\n reg rob_exception_12;\n reg rob_exception_13;\n reg rob_exception_14;\n reg rob_exception_15;\n reg rob_exception_16;\n reg rob_exception_17;\n reg rob_exception_18;\n reg rob_exception_19;\n reg rob_exception_20;\n reg rob_exception_21;\n reg rob_exception_22;\n reg rob_exception_23;\n reg rob_exception_24;\n reg rob_exception_25;\n reg rob_exception_26;\n reg rob_exception_27;\n reg rob_exception_28;\n reg rob_exception_29;\n reg rob_exception_30;\n reg rob_exception_31;\n reg rob_predicated_0;\n reg rob_predicated_1;\n reg rob_predicated_2;\n reg rob_predicated_3;\n reg rob_predicated_4;\n reg rob_predicated_5;\n reg rob_predicated_6;\n reg rob_predicated_7;\n reg rob_predicated_8;\n reg rob_predicated_9;\n reg rob_predicated_10;\n reg rob_predicated_11;\n reg rob_predicated_12;\n reg rob_predicated_13;\n reg rob_predicated_14;\n reg rob_predicated_15;\n reg rob_predicated_16;\n reg rob_predicated_17;\n reg rob_predicated_18;\n reg rob_predicated_19;\n reg rob_predicated_20;\n reg rob_predicated_21;\n reg rob_predicated_22;\n reg rob_predicated_23;\n reg rob_predicated_24;\n reg rob_predicated_25;\n reg rob_predicated_26;\n reg rob_predicated_27;\n reg rob_predicated_28;\n reg rob_predicated_29;\n reg rob_predicated_30;\n reg rob_predicated_31;\n wire [31:0] _GEN = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}};\n wire [31:0] _GEN_0 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}};\n wire _GEN_1 = io_lxcpt_valid & io_lxcpt_bits_cause != 5'h10 & ~reset;\n wire [31:0] _GEN_2 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}};\n wire rob_head_vals_0 = _GEN[rob_head];\n wire [31:0] _GEN_3 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}};\n wire can_throw_exception_0 = rob_head_vals_0 & _GEN_3[rob_head];\n wire [31:0] _GEN_4 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}};\n wire [31:0][6:0] _GEN_5 = {{rob_uop_31_uopc}, {rob_uop_30_uopc}, {rob_uop_29_uopc}, {rob_uop_28_uopc}, {rob_uop_27_uopc}, {rob_uop_26_uopc}, {rob_uop_25_uopc}, {rob_uop_24_uopc}, {rob_uop_23_uopc}, {rob_uop_22_uopc}, {rob_uop_21_uopc}, {rob_uop_20_uopc}, {rob_uop_19_uopc}, {rob_uop_18_uopc}, {rob_uop_17_uopc}, {rob_uop_16_uopc}, {rob_uop_15_uopc}, {rob_uop_14_uopc}, {rob_uop_13_uopc}, {rob_uop_12_uopc}, {rob_uop_11_uopc}, {rob_uop_10_uopc}, {rob_uop_9_uopc}, {rob_uop_8_uopc}, {rob_uop_7_uopc}, {rob_uop_6_uopc}, {rob_uop_5_uopc}, {rob_uop_4_uopc}, {rob_uop_3_uopc}, {rob_uop_2_uopc}, {rob_uop_1_uopc}, {rob_uop_0_uopc}};\n wire [31:0] _GEN_6 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}};\n wire [31:0] _GEN_7 = {{rob_uop_31_is_br}, {rob_uop_30_is_br}, {rob_uop_29_is_br}, {rob_uop_28_is_br}, {rob_uop_27_is_br}, {rob_uop_26_is_br}, {rob_uop_25_is_br}, {rob_uop_24_is_br}, {rob_uop_23_is_br}, {rob_uop_22_is_br}, {rob_uop_21_is_br}, {rob_uop_20_is_br}, {rob_uop_19_is_br}, {rob_uop_18_is_br}, {rob_uop_17_is_br}, {rob_uop_16_is_br}, {rob_uop_15_is_br}, {rob_uop_14_is_br}, {rob_uop_13_is_br}, {rob_uop_12_is_br}, {rob_uop_11_is_br}, {rob_uop_10_is_br}, {rob_uop_9_is_br}, {rob_uop_8_is_br}, {rob_uop_7_is_br}, {rob_uop_6_is_br}, {rob_uop_5_is_br}, {rob_uop_4_is_br}, {rob_uop_3_is_br}, {rob_uop_2_is_br}, {rob_uop_1_is_br}, {rob_uop_0_is_br}};\n wire [31:0] _GEN_8 = {{rob_uop_31_is_jalr}, {rob_uop_30_is_jalr}, {rob_uop_29_is_jalr}, {rob_uop_28_is_jalr}, {rob_uop_27_is_jalr}, {rob_uop_26_is_jalr}, {rob_uop_25_is_jalr}, {rob_uop_24_is_jalr}, {rob_uop_23_is_jalr}, {rob_uop_22_is_jalr}, {rob_uop_21_is_jalr}, {rob_uop_20_is_jalr}, {rob_uop_19_is_jalr}, {rob_uop_18_is_jalr}, {rob_uop_17_is_jalr}, {rob_uop_16_is_jalr}, {rob_uop_15_is_jalr}, {rob_uop_14_is_jalr}, {rob_uop_13_is_jalr}, {rob_uop_12_is_jalr}, {rob_uop_11_is_jalr}, {rob_uop_10_is_jalr}, {rob_uop_9_is_jalr}, {rob_uop_8_is_jalr}, {rob_uop_7_is_jalr}, {rob_uop_6_is_jalr}, {rob_uop_5_is_jalr}, {rob_uop_4_is_jalr}, {rob_uop_3_is_jalr}, {rob_uop_2_is_jalr}, {rob_uop_1_is_jalr}, {rob_uop_0_is_jalr}};\n wire [31:0] _GEN_9 = {{rob_uop_31_is_jal}, {rob_uop_30_is_jal}, {rob_uop_29_is_jal}, {rob_uop_28_is_jal}, {rob_uop_27_is_jal}, {rob_uop_26_is_jal}, {rob_uop_25_is_jal}, {rob_uop_24_is_jal}, {rob_uop_23_is_jal}, {rob_uop_22_is_jal}, {rob_uop_21_is_jal}, {rob_uop_20_is_jal}, {rob_uop_19_is_jal}, {rob_uop_18_is_jal}, {rob_uop_17_is_jal}, {rob_uop_16_is_jal}, {rob_uop_15_is_jal}, {rob_uop_14_is_jal}, {rob_uop_13_is_jal}, {rob_uop_12_is_jal}, {rob_uop_11_is_jal}, {rob_uop_10_is_jal}, {rob_uop_9_is_jal}, {rob_uop_8_is_jal}, {rob_uop_7_is_jal}, {rob_uop_6_is_jal}, {rob_uop_5_is_jal}, {rob_uop_4_is_jal}, {rob_uop_3_is_jal}, {rob_uop_2_is_jal}, {rob_uop_1_is_jal}, {rob_uop_0_is_jal}};\n wire [31:0][3:0] _GEN_10 = {{rob_uop_31_ftq_idx}, {rob_uop_30_ftq_idx}, {rob_uop_29_ftq_idx}, {rob_uop_28_ftq_idx}, {rob_uop_27_ftq_idx}, {rob_uop_26_ftq_idx}, {rob_uop_25_ftq_idx}, {rob_uop_24_ftq_idx}, {rob_uop_23_ftq_idx}, {rob_uop_22_ftq_idx}, {rob_uop_21_ftq_idx}, {rob_uop_20_ftq_idx}, {rob_uop_19_ftq_idx}, {rob_uop_18_ftq_idx}, {rob_uop_17_ftq_idx}, {rob_uop_16_ftq_idx}, {rob_uop_15_ftq_idx}, {rob_uop_14_ftq_idx}, {rob_uop_13_ftq_idx}, {rob_uop_12_ftq_idx}, {rob_uop_11_ftq_idx}, {rob_uop_10_ftq_idx}, {rob_uop_9_ftq_idx}, {rob_uop_8_ftq_idx}, {rob_uop_7_ftq_idx}, {rob_uop_6_ftq_idx}, {rob_uop_5_ftq_idx}, {rob_uop_4_ftq_idx}, {rob_uop_3_ftq_idx}, {rob_uop_2_ftq_idx}, {rob_uop_1_ftq_idx}, {rob_uop_0_ftq_idx}};\n wire [31:0] _GEN_11 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}};\n wire [31:0][5:0] _GEN_12 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}};\n wire [31:0][5:0] _GEN_13 = {{rob_uop_31_pdst}, {rob_uop_30_pdst}, {rob_uop_29_pdst}, {rob_uop_28_pdst}, {rob_uop_27_pdst}, {rob_uop_26_pdst}, {rob_uop_25_pdst}, {rob_uop_24_pdst}, {rob_uop_23_pdst}, {rob_uop_22_pdst}, {rob_uop_21_pdst}, {rob_uop_20_pdst}, {rob_uop_19_pdst}, {rob_uop_18_pdst}, {rob_uop_17_pdst}, {rob_uop_16_pdst}, {rob_uop_15_pdst}, {rob_uop_14_pdst}, {rob_uop_13_pdst}, {rob_uop_12_pdst}, {rob_uop_11_pdst}, {rob_uop_10_pdst}, {rob_uop_9_pdst}, {rob_uop_8_pdst}, {rob_uop_7_pdst}, {rob_uop_6_pdst}, {rob_uop_5_pdst}, {rob_uop_4_pdst}, {rob_uop_3_pdst}, {rob_uop_2_pdst}, {rob_uop_1_pdst}, {rob_uop_0_pdst}};\n wire [31:0][5:0] _GEN_14 = {{rob_uop_31_stale_pdst}, {rob_uop_30_stale_pdst}, {rob_uop_29_stale_pdst}, {rob_uop_28_stale_pdst}, {rob_uop_27_stale_pdst}, {rob_uop_26_stale_pdst}, {rob_uop_25_stale_pdst}, {rob_uop_24_stale_pdst}, {rob_uop_23_stale_pdst}, {rob_uop_22_stale_pdst}, {rob_uop_21_stale_pdst}, {rob_uop_20_stale_pdst}, {rob_uop_19_stale_pdst}, {rob_uop_18_stale_pdst}, {rob_uop_17_stale_pdst}, {rob_uop_16_stale_pdst}, {rob_uop_15_stale_pdst}, {rob_uop_14_stale_pdst}, {rob_uop_13_stale_pdst}, {rob_uop_12_stale_pdst}, {rob_uop_11_stale_pdst}, {rob_uop_10_stale_pdst}, {rob_uop_9_stale_pdst}, {rob_uop_8_stale_pdst}, {rob_uop_7_stale_pdst}, {rob_uop_6_stale_pdst}, {rob_uop_5_stale_pdst}, {rob_uop_4_stale_pdst}, {rob_uop_3_stale_pdst}, {rob_uop_2_stale_pdst}, {rob_uop_1_stale_pdst}, {rob_uop_0_stale_pdst}};\n wire [31:0] _GEN_15 = {{rob_uop_31_is_fencei}, {rob_uop_30_is_fencei}, {rob_uop_29_is_fencei}, {rob_uop_28_is_fencei}, {rob_uop_27_is_fencei}, {rob_uop_26_is_fencei}, {rob_uop_25_is_fencei}, {rob_uop_24_is_fencei}, {rob_uop_23_is_fencei}, {rob_uop_22_is_fencei}, {rob_uop_21_is_fencei}, {rob_uop_20_is_fencei}, {rob_uop_19_is_fencei}, {rob_uop_18_is_fencei}, {rob_uop_17_is_fencei}, {rob_uop_16_is_fencei}, {rob_uop_15_is_fencei}, {rob_uop_14_is_fencei}, {rob_uop_13_is_fencei}, {rob_uop_12_is_fencei}, {rob_uop_11_is_fencei}, {rob_uop_10_is_fencei}, {rob_uop_9_is_fencei}, {rob_uop_8_is_fencei}, {rob_uop_7_is_fencei}, {rob_uop_6_is_fencei}, {rob_uop_5_is_fencei}, {rob_uop_4_is_fencei}, {rob_uop_3_is_fencei}, {rob_uop_2_is_fencei}, {rob_uop_1_is_fencei}, {rob_uop_0_is_fencei}};\n wire [31:0] _GEN_16 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}};\n wire [31:0] _GEN_17 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}};\n wire [31:0] _GEN_18 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}};\n wire [31:0] _GEN_19 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}};\n wire [31:0][5:0] _GEN_20 = {{rob_uop_31_ldst}, {rob_uop_30_ldst}, {rob_uop_29_ldst}, {rob_uop_28_ldst}, {rob_uop_27_ldst}, {rob_uop_26_ldst}, {rob_uop_25_ldst}, {rob_uop_24_ldst}, {rob_uop_23_ldst}, {rob_uop_22_ldst}, {rob_uop_21_ldst}, {rob_uop_20_ldst}, {rob_uop_19_ldst}, {rob_uop_18_ldst}, {rob_uop_17_ldst}, {rob_uop_16_ldst}, {rob_uop_15_ldst}, {rob_uop_14_ldst}, {rob_uop_13_ldst}, {rob_uop_12_ldst}, {rob_uop_11_ldst}, {rob_uop_10_ldst}, {rob_uop_9_ldst}, {rob_uop_8_ldst}, {rob_uop_7_ldst}, {rob_uop_6_ldst}, {rob_uop_5_ldst}, {rob_uop_4_ldst}, {rob_uop_3_ldst}, {rob_uop_2_ldst}, {rob_uop_1_ldst}, {rob_uop_0_ldst}};\n wire [31:0] _GEN_21 = {{rob_uop_31_ldst_val}, {rob_uop_30_ldst_val}, {rob_uop_29_ldst_val}, {rob_uop_28_ldst_val}, {rob_uop_27_ldst_val}, {rob_uop_26_ldst_val}, {rob_uop_25_ldst_val}, {rob_uop_24_ldst_val}, {rob_uop_23_ldst_val}, {rob_uop_22_ldst_val}, {rob_uop_21_ldst_val}, {rob_uop_20_ldst_val}, {rob_uop_19_ldst_val}, {rob_uop_18_ldst_val}, {rob_uop_17_ldst_val}, {rob_uop_16_ldst_val}, {rob_uop_15_ldst_val}, {rob_uop_14_ldst_val}, {rob_uop_13_ldst_val}, {rob_uop_12_ldst_val}, {rob_uop_11_ldst_val}, {rob_uop_10_ldst_val}, {rob_uop_9_ldst_val}, {rob_uop_8_ldst_val}, {rob_uop_7_ldst_val}, {rob_uop_6_ldst_val}, {rob_uop_5_ldst_val}, {rob_uop_4_ldst_val}, {rob_uop_3_ldst_val}, {rob_uop_2_ldst_val}, {rob_uop_1_ldst_val}, {rob_uop_0_ldst_val}};\n wire [31:0][1:0] _GEN_22 = {{rob_uop_31_dst_rtype}, {rob_uop_30_dst_rtype}, {rob_uop_29_dst_rtype}, {rob_uop_28_dst_rtype}, {rob_uop_27_dst_rtype}, {rob_uop_26_dst_rtype}, {rob_uop_25_dst_rtype}, {rob_uop_24_dst_rtype}, {rob_uop_23_dst_rtype}, {rob_uop_22_dst_rtype}, {rob_uop_21_dst_rtype}, {rob_uop_20_dst_rtype}, {rob_uop_19_dst_rtype}, {rob_uop_18_dst_rtype}, {rob_uop_17_dst_rtype}, {rob_uop_16_dst_rtype}, {rob_uop_15_dst_rtype}, {rob_uop_14_dst_rtype}, {rob_uop_13_dst_rtype}, {rob_uop_12_dst_rtype}, {rob_uop_11_dst_rtype}, {rob_uop_10_dst_rtype}, {rob_uop_9_dst_rtype}, {rob_uop_8_dst_rtype}, {rob_uop_7_dst_rtype}, {rob_uop_6_dst_rtype}, {rob_uop_5_dst_rtype}, {rob_uop_4_dst_rtype}, {rob_uop_3_dst_rtype}, {rob_uop_2_dst_rtype}, {rob_uop_1_dst_rtype}, {rob_uop_0_dst_rtype}};\n wire [31:0] _GEN_23 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}};\n wire [31:0][1:0] _GEN_24 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}};\n wire rbk_row = io_commit_rollback_0 & ~full;\n wire io_commit_rbk_valids_0_0 = rbk_row & _GEN[com_idx];\n wire [31:0][4:0] _GEN_25 = {{rob_fflags_0_31}, {rob_fflags_0_30}, {rob_fflags_0_29}, {rob_fflags_0_28}, {rob_fflags_0_27}, {rob_fflags_0_26}, {rob_fflags_0_25}, {rob_fflags_0_24}, {rob_fflags_0_23}, {rob_fflags_0_22}, {rob_fflags_0_21}, {rob_fflags_0_20}, {rob_fflags_0_19}, {rob_fflags_0_18}, {rob_fflags_0_17}, {rob_fflags_0_16}, {rob_fflags_0_15}, {rob_fflags_0_14}, {rob_fflags_0_13}, {rob_fflags_0_12}, {rob_fflags_0_11}, {rob_fflags_0_10}, {rob_fflags_0_9}, {rob_fflags_0_8}, {rob_fflags_0_7}, {rob_fflags_0_6}, {rob_fflags_0_5}, {rob_fflags_0_4}, {rob_fflags_0_3}, {rob_fflags_0_2}, {rob_fflags_0_1}, {rob_fflags_0_0}};\n wire [4:0] rob_head_fflags_0 = _GEN_25[rob_head];\n reg block_commit_REG;\n reg block_commit_REG_1;\n reg block_commit_REG_2;\n wire block_commit = rob_state != 2'h1 & rob_state != 2'h3 | block_commit_REG | block_commit_REG_2;\n wire exception_thrown = can_throw_exception_0 & ~block_commit;\n assign will_commit_0 = rob_head_vals_0 & ~_GEN_0[rob_head] & ~io_csr_stall & ~can_throw_exception_0 & ~block_commit;\n wire is_mini_exception = r_xcpt_uop_exc_cause == 64'h10 | r_xcpt_uop_exc_cause == 64'h11;\n wire flush_commit_mask_0 = will_commit_0 & _GEN_19[com_idx];\n wire flush_val = exception_thrown | flush_commit_mask_0;\n wire _fflags_val_0_T = will_commit_0 & _GEN_23[com_idx];\n wire fflags_val_0 = _fflags_val_0_T & ~_GEN_17[com_idx];\n reg r_partial_row;\n wire _empty_T = rob_head == rob_tail;\n wire finished_committing_row = will_commit_0 & (will_commit_0 ^ ~rob_head_vals_0) & ~(r_partial_row & _empty_T & ~maybe_full);\n reg pnr_maybe_at_tail;\n wire _io_ready_T = rob_state == 2'h1;\n wire _GEN_30 = io_commit_rollback_0 & (rob_tail != rob_head | maybe_full);\n wire rob_deq = _GEN_30 | finished_committing_row;\n assign full = _empty_T & maybe_full;\n assign empty = _empty_T & ~rob_head_vals_0;\n reg REG;\n reg REG_1;\n reg REG_2;\n reg io_com_load_is_at_rob_head_REG;\n wire do_inc_row = ~(_GEN[rob_pnr] & (_GEN_2[rob_pnr] | _GEN_3[rob_pnr])) & (rob_pnr != rob_tail | full & ~pnr_maybe_at_tail);\n wire _GEN_31 = io_commit_rollback_0 & _empty_T & ~maybe_full;\n wire _GEN_32 = io_enq_valids_0 & ~io_enq_partial_stall;\n wire [1:0] _GEN_33 = empty ? 2'h1 : rob_state;\n wire [3:0][1:0] _GEN_34 = {{REG_2 ? 2'h2 : _GEN_33}, {_GEN_33}, {REG_1 ? 2'h2 : io_enq_valids_0 & io_enq_uops_0_is_unique ? 2'h3 : rob_state}, {2'h1}};\n wire _GEN_35 = io_enq_valids_0 & rob_tail == 5'h0;\n wire _GEN_36 = io_enq_valids_0 & rob_tail == 5'h1;\n wire _GEN_37 = io_enq_valids_0 & rob_tail == 5'h2;\n wire _GEN_38 = io_enq_valids_0 & rob_tail == 5'h3;\n wire _GEN_39 = io_enq_valids_0 & rob_tail == 5'h4;\n wire _GEN_40 = io_enq_valids_0 & rob_tail == 5'h5;\n wire _GEN_41 = io_enq_valids_0 & rob_tail == 5'h6;\n wire _GEN_42 = io_enq_valids_0 & rob_tail == 5'h7;\n wire _GEN_43 = io_enq_valids_0 & rob_tail == 5'h8;\n wire _GEN_44 = io_enq_valids_0 & rob_tail == 5'h9;\n wire _GEN_45 = io_enq_valids_0 & rob_tail == 5'hA;\n wire _GEN_46 = io_enq_valids_0 & rob_tail == 5'hB;\n wire _GEN_47 = io_enq_valids_0 & rob_tail == 5'hC;\n wire _GEN_48 = io_enq_valids_0 & rob_tail == 5'hD;\n wire _GEN_49 = io_enq_valids_0 & rob_tail == 5'hE;\n wire _GEN_50 = io_enq_valids_0 & rob_tail == 5'hF;\n wire _GEN_51 = io_enq_valids_0 & rob_tail == 5'h10;\n wire _GEN_52 = io_enq_valids_0 & rob_tail == 5'h11;\n wire _GEN_53 = io_enq_valids_0 & rob_tail == 5'h12;\n wire _GEN_54 = io_enq_valids_0 & rob_tail == 5'h13;\n wire _GEN_55 = io_enq_valids_0 & rob_tail == 5'h14;\n wire _GEN_56 = io_enq_valids_0 & rob_tail == 5'h15;\n wire _GEN_57 = io_enq_valids_0 & rob_tail == 5'h16;\n wire _GEN_58 = io_enq_valids_0 & rob_tail == 5'h17;\n wire _GEN_59 = io_enq_valids_0 & rob_tail == 5'h18;\n wire _GEN_60 = io_enq_valids_0 & rob_tail == 5'h19;\n wire _GEN_61 = io_enq_valids_0 & rob_tail == 5'h1A;\n wire _GEN_62 = io_enq_valids_0 & rob_tail == 5'h1B;\n wire _GEN_63 = io_enq_valids_0 & rob_tail == 5'h1C;\n wire _GEN_64 = io_enq_valids_0 & rob_tail == 5'h1D;\n wire _GEN_65 = io_enq_valids_0 & rob_tail == 5'h1E;\n wire _GEN_66 = io_enq_valids_0 & (&rob_tail);\n wire _rob_bsy_T = io_enq_uops_0_is_fence | io_enq_uops_0_is_fencei;\n wire _GEN_67 = _GEN_35 ? ~_rob_bsy_T : rob_bsy_0;\n wire _GEN_68 = _GEN_36 ? ~_rob_bsy_T : rob_bsy_1;\n wire _GEN_69 = _GEN_37 ? ~_rob_bsy_T : rob_bsy_2;\n wire _GEN_70 = _GEN_38 ? ~_rob_bsy_T : rob_bsy_3;\n wire _GEN_71 = _GEN_39 ? ~_rob_bsy_T : rob_bsy_4;\n wire _GEN_72 = _GEN_40 ? ~_rob_bsy_T : rob_bsy_5;\n wire _GEN_73 = _GEN_41 ? ~_rob_bsy_T : rob_bsy_6;\n wire _GEN_74 = _GEN_42 ? ~_rob_bsy_T : rob_bsy_7;\n wire _GEN_75 = _GEN_43 ? ~_rob_bsy_T : rob_bsy_8;\n wire _GEN_76 = _GEN_44 ? ~_rob_bsy_T : rob_bsy_9;\n wire _GEN_77 = _GEN_45 ? ~_rob_bsy_T : rob_bsy_10;\n wire _GEN_78 = _GEN_46 ? ~_rob_bsy_T : rob_bsy_11;\n wire _GEN_79 = _GEN_47 ? ~_rob_bsy_T : rob_bsy_12;\n wire _GEN_80 = _GEN_48 ? ~_rob_bsy_T : rob_bsy_13;\n wire _GEN_81 = _GEN_49 ? ~_rob_bsy_T : rob_bsy_14;\n wire _GEN_82 = _GEN_50 ? ~_rob_bsy_T : rob_bsy_15;\n wire _GEN_83 = _GEN_51 ? ~_rob_bsy_T : rob_bsy_16;\n wire _GEN_84 = _GEN_52 ? ~_rob_bsy_T : rob_bsy_17;\n wire _GEN_85 = _GEN_53 ? ~_rob_bsy_T : rob_bsy_18;\n wire _GEN_86 = _GEN_54 ? ~_rob_bsy_T : rob_bsy_19;\n wire _GEN_87 = _GEN_55 ? ~_rob_bsy_T : rob_bsy_20;\n wire _GEN_88 = _GEN_56 ? ~_rob_bsy_T : rob_bsy_21;\n wire _GEN_89 = _GEN_57 ? ~_rob_bsy_T : rob_bsy_22;\n wire _GEN_90 = _GEN_58 ? ~_rob_bsy_T : rob_bsy_23;\n wire _GEN_91 = _GEN_59 ? ~_rob_bsy_T : rob_bsy_24;\n wire _GEN_92 = _GEN_60 ? ~_rob_bsy_T : rob_bsy_25;\n wire _GEN_93 = _GEN_61 ? ~_rob_bsy_T : rob_bsy_26;\n wire _GEN_94 = _GEN_62 ? ~_rob_bsy_T : rob_bsy_27;\n wire _GEN_95 = _GEN_63 ? ~_rob_bsy_T : rob_bsy_28;\n wire _GEN_96 = _GEN_64 ? ~_rob_bsy_T : rob_bsy_29;\n wire _GEN_97 = _GEN_65 ? ~_rob_bsy_T : rob_bsy_30;\n wire _GEN_98 = _GEN_66 ? ~_rob_bsy_T : rob_bsy_31;\n wire _rob_unsafe_T_4 = io_enq_uops_0_uses_ldq | io_enq_uops_0_uses_stq & ~io_enq_uops_0_is_fence | io_enq_uops_0_is_br | io_enq_uops_0_is_jalr;\n wire _GEN_99 = _GEN_35 ? _rob_unsafe_T_4 : rob_unsafe_0;\n wire _GEN_100 = _GEN_36 ? _rob_unsafe_T_4 : rob_unsafe_1;\n wire _GEN_101 = _GEN_37 ? _rob_unsafe_T_4 : rob_unsafe_2;\n wire _GEN_102 = _GEN_38 ? _rob_unsafe_T_4 : rob_unsafe_3;\n wire _GEN_103 = _GEN_39 ? _rob_unsafe_T_4 : rob_unsafe_4;\n wire _GEN_104 = _GEN_40 ? _rob_unsafe_T_4 : rob_unsafe_5;\n wire _GEN_105 = _GEN_41 ? _rob_unsafe_T_4 : rob_unsafe_6;\n wire _GEN_106 = _GEN_42 ? _rob_unsafe_T_4 : rob_unsafe_7;\n wire _GEN_107 = _GEN_43 ? _rob_unsafe_T_4 : rob_unsafe_8;\n wire _GEN_108 = _GEN_44 ? _rob_unsafe_T_4 : rob_unsafe_9;\n wire _GEN_109 = _GEN_45 ? _rob_unsafe_T_4 : rob_unsafe_10;\n wire _GEN_110 = _GEN_46 ? _rob_unsafe_T_4 : rob_unsafe_11;\n wire _GEN_111 = _GEN_47 ? _rob_unsafe_T_4 : rob_unsafe_12;\n wire _GEN_112 = _GEN_48 ? _rob_unsafe_T_4 : rob_unsafe_13;\n wire _GEN_113 = _GEN_49 ? _rob_unsafe_T_4 : rob_unsafe_14;\n wire _GEN_114 = _GEN_50 ? _rob_unsafe_T_4 : rob_unsafe_15;\n wire _GEN_115 = _GEN_51 ? _rob_unsafe_T_4 : rob_unsafe_16;\n wire _GEN_116 = _GEN_52 ? _rob_unsafe_T_4 : rob_unsafe_17;\n wire _GEN_117 = _GEN_53 ? _rob_unsafe_T_4 : rob_unsafe_18;\n wire _GEN_118 = _GEN_54 ? _rob_unsafe_T_4 : rob_unsafe_19;\n wire _GEN_119 = _GEN_55 ? _rob_unsafe_T_4 : rob_unsafe_20;\n wire _GEN_120 = _GEN_56 ? _rob_unsafe_T_4 : rob_unsafe_21;\n wire _GEN_121 = _GEN_57 ? _rob_unsafe_T_4 : rob_unsafe_22;\n wire _GEN_122 = _GEN_58 ? _rob_unsafe_T_4 : rob_unsafe_23;\n wire _GEN_123 = _GEN_59 ? _rob_unsafe_T_4 : rob_unsafe_24;\n wire _GEN_124 = _GEN_60 ? _rob_unsafe_T_4 : rob_unsafe_25;\n wire _GEN_125 = _GEN_61 ? _rob_unsafe_T_4 : rob_unsafe_26;\n wire _GEN_126 = _GEN_62 ? _rob_unsafe_T_4 : rob_unsafe_27;\n wire _GEN_127 = _GEN_63 ? _rob_unsafe_T_4 : rob_unsafe_28;\n wire _GEN_128 = _GEN_64 ? _rob_unsafe_T_4 : rob_unsafe_29;\n wire _GEN_129 = _GEN_65 ? _rob_unsafe_T_4 : rob_unsafe_30;\n wire _GEN_130 = _GEN_66 ? _rob_unsafe_T_4 : rob_unsafe_31;\n wire _GEN_131 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h0;\n wire _GEN_132 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1;\n wire _GEN_133 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h2;\n wire _GEN_134 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h3;\n wire _GEN_135 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h4;\n wire _GEN_136 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h5;\n wire _GEN_137 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h6;\n wire _GEN_138 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h7;\n wire _GEN_139 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h8;\n wire _GEN_140 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h9;\n wire _GEN_141 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hA;\n wire _GEN_142 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hB;\n wire _GEN_143 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hC;\n wire _GEN_144 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hD;\n wire _GEN_145 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hE;\n wire _GEN_146 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'hF;\n wire _GEN_147 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h10;\n wire _GEN_148 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h11;\n wire _GEN_149 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h12;\n wire _GEN_150 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h13;\n wire _GEN_151 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h14;\n wire _GEN_152 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h15;\n wire _GEN_153 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h16;\n wire _GEN_154 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h17;\n wire _GEN_155 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h18;\n wire _GEN_156 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h19;\n wire _GEN_157 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1A;\n wire _GEN_158 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1B;\n wire _GEN_159 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1C;\n wire _GEN_160 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1D;\n wire _GEN_161 = io_wb_resps_0_valid & io_wb_resps_0_bits_uop_rob_idx == 5'h1E;\n wire _GEN_162 = io_wb_resps_0_valid & (&io_wb_resps_0_bits_uop_rob_idx);\n wire _GEN_163 = io_wb_resps_1_bits_uop_rob_idx == 5'h0;\n wire _GEN_164 = _GEN_163 | _GEN_131;\n wire _GEN_165 = io_wb_resps_1_valid ? ~_GEN_164 & _GEN_67 : ~_GEN_131 & _GEN_67;\n wire _GEN_166 = io_wb_resps_1_bits_uop_rob_idx == 5'h1;\n wire _GEN_167 = _GEN_166 | _GEN_132;\n wire _GEN_168 = io_wb_resps_1_valid ? ~_GEN_167 & _GEN_68 : ~_GEN_132 & _GEN_68;\n wire _GEN_169 = io_wb_resps_1_bits_uop_rob_idx == 5'h2;\n wire _GEN_170 = _GEN_169 | _GEN_133;\n wire _GEN_171 = io_wb_resps_1_valid ? ~_GEN_170 & _GEN_69 : ~_GEN_133 & _GEN_69;\n wire _GEN_172 = io_wb_resps_1_bits_uop_rob_idx == 5'h3;\n wire _GEN_173 = _GEN_172 | _GEN_134;\n wire _GEN_174 = io_wb_resps_1_valid ? ~_GEN_173 & _GEN_70 : ~_GEN_134 & _GEN_70;\n wire _GEN_175 = io_wb_resps_1_bits_uop_rob_idx == 5'h4;\n wire _GEN_176 = _GEN_175 | _GEN_135;\n wire _GEN_177 = io_wb_resps_1_valid ? ~_GEN_176 & _GEN_71 : ~_GEN_135 & _GEN_71;\n wire _GEN_178 = io_wb_resps_1_bits_uop_rob_idx == 5'h5;\n wire _GEN_179 = _GEN_178 | _GEN_136;\n wire _GEN_180 = io_wb_resps_1_valid ? ~_GEN_179 & _GEN_72 : ~_GEN_136 & _GEN_72;\n wire _GEN_181 = io_wb_resps_1_bits_uop_rob_idx == 5'h6;\n wire _GEN_182 = _GEN_181 | _GEN_137;\n wire _GEN_183 = io_wb_resps_1_valid ? ~_GEN_182 & _GEN_73 : ~_GEN_137 & _GEN_73;\n wire _GEN_184 = io_wb_resps_1_bits_uop_rob_idx == 5'h7;\n wire _GEN_185 = _GEN_184 | _GEN_138;\n wire _GEN_186 = io_wb_resps_1_valid ? ~_GEN_185 & _GEN_74 : ~_GEN_138 & _GEN_74;\n wire _GEN_187 = io_wb_resps_1_bits_uop_rob_idx == 5'h8;\n wire _GEN_188 = _GEN_187 | _GEN_139;\n wire _GEN_189 = io_wb_resps_1_valid ? ~_GEN_188 & _GEN_75 : ~_GEN_139 & _GEN_75;\n wire _GEN_190 = io_wb_resps_1_bits_uop_rob_idx == 5'h9;\n wire _GEN_191 = _GEN_190 | _GEN_140;\n wire _GEN_192 = io_wb_resps_1_valid ? ~_GEN_191 & _GEN_76 : ~_GEN_140 & _GEN_76;\n wire _GEN_193 = io_wb_resps_1_bits_uop_rob_idx == 5'hA;\n wire _GEN_194 = _GEN_193 | _GEN_141;\n wire _GEN_195 = io_wb_resps_1_valid ? ~_GEN_194 & _GEN_77 : ~_GEN_141 & _GEN_77;\n wire _GEN_196 = io_wb_resps_1_bits_uop_rob_idx == 5'hB;\n wire _GEN_197 = _GEN_196 | _GEN_142;\n wire _GEN_198 = io_wb_resps_1_valid ? ~_GEN_197 & _GEN_78 : ~_GEN_142 & _GEN_78;\n wire _GEN_199 = io_wb_resps_1_bits_uop_rob_idx == 5'hC;\n wire _GEN_200 = _GEN_199 | _GEN_143;\n wire _GEN_201 = io_wb_resps_1_valid ? ~_GEN_200 & _GEN_79 : ~_GEN_143 & _GEN_79;\n wire _GEN_202 = io_wb_resps_1_bits_uop_rob_idx == 5'hD;\n wire _GEN_203 = _GEN_202 | _GEN_144;\n wire _GEN_204 = io_wb_resps_1_valid ? ~_GEN_203 & _GEN_80 : ~_GEN_144 & _GEN_80;\n wire _GEN_205 = io_wb_resps_1_bits_uop_rob_idx == 5'hE;\n wire _GEN_206 = _GEN_205 | _GEN_145;\n wire _GEN_207 = io_wb_resps_1_valid ? ~_GEN_206 & _GEN_81 : ~_GEN_145 & _GEN_81;\n wire _GEN_208 = io_wb_resps_1_bits_uop_rob_idx == 5'hF;\n wire _GEN_209 = _GEN_208 | _GEN_146;\n wire _GEN_210 = io_wb_resps_1_valid ? ~_GEN_209 & _GEN_82 : ~_GEN_146 & _GEN_82;\n wire _GEN_211 = io_wb_resps_1_bits_uop_rob_idx == 5'h10;\n wire _GEN_212 = _GEN_211 | _GEN_147;\n wire _GEN_213 = io_wb_resps_1_valid ? ~_GEN_212 & _GEN_83 : ~_GEN_147 & _GEN_83;\n wire _GEN_214 = io_wb_resps_1_bits_uop_rob_idx == 5'h11;\n wire _GEN_215 = _GEN_214 | _GEN_148;\n wire _GEN_216 = io_wb_resps_1_valid ? ~_GEN_215 & _GEN_84 : ~_GEN_148 & _GEN_84;\n wire _GEN_217 = io_wb_resps_1_bits_uop_rob_idx == 5'h12;\n wire _GEN_218 = _GEN_217 | _GEN_149;\n wire _GEN_219 = io_wb_resps_1_valid ? ~_GEN_218 & _GEN_85 : ~_GEN_149 & _GEN_85;\n wire _GEN_220 = io_wb_resps_1_bits_uop_rob_idx == 5'h13;\n wire _GEN_221 = _GEN_220 | _GEN_150;\n wire _GEN_222 = io_wb_resps_1_valid ? ~_GEN_221 & _GEN_86 : ~_GEN_150 & _GEN_86;\n wire _GEN_223 = io_wb_resps_1_bits_uop_rob_idx == 5'h14;\n wire _GEN_224 = _GEN_223 | _GEN_151;\n wire _GEN_225 = io_wb_resps_1_valid ? ~_GEN_224 & _GEN_87 : ~_GEN_151 & _GEN_87;\n wire _GEN_226 = io_wb_resps_1_bits_uop_rob_idx == 5'h15;\n wire _GEN_227 = _GEN_226 | _GEN_152;\n wire _GEN_228 = io_wb_resps_1_valid ? ~_GEN_227 & _GEN_88 : ~_GEN_152 & _GEN_88;\n wire _GEN_229 = io_wb_resps_1_bits_uop_rob_idx == 5'h16;\n wire _GEN_230 = _GEN_229 | _GEN_153;\n wire _GEN_231 = io_wb_resps_1_valid ? ~_GEN_230 & _GEN_89 : ~_GEN_153 & _GEN_89;\n wire _GEN_232 = io_wb_resps_1_bits_uop_rob_idx == 5'h17;\n wire _GEN_233 = _GEN_232 | _GEN_154;\n wire _GEN_234 = io_wb_resps_1_valid ? ~_GEN_233 & _GEN_90 : ~_GEN_154 & _GEN_90;\n wire _GEN_235 = io_wb_resps_1_bits_uop_rob_idx == 5'h18;\n wire _GEN_236 = _GEN_235 | _GEN_155;\n wire _GEN_237 = io_wb_resps_1_valid ? ~_GEN_236 & _GEN_91 : ~_GEN_155 & _GEN_91;\n wire _GEN_238 = io_wb_resps_1_bits_uop_rob_idx == 5'h19;\n wire _GEN_239 = _GEN_238 | _GEN_156;\n wire _GEN_240 = io_wb_resps_1_valid ? ~_GEN_239 & _GEN_92 : ~_GEN_156 & _GEN_92;\n wire _GEN_241 = io_wb_resps_1_bits_uop_rob_idx == 5'h1A;\n wire _GEN_242 = _GEN_241 | _GEN_157;\n wire _GEN_243 = io_wb_resps_1_valid ? ~_GEN_242 & _GEN_93 : ~_GEN_157 & _GEN_93;\n wire _GEN_244 = io_wb_resps_1_bits_uop_rob_idx == 5'h1B;\n wire _GEN_245 = _GEN_244 | _GEN_158;\n wire _GEN_246 = io_wb_resps_1_valid ? ~_GEN_245 & _GEN_94 : ~_GEN_158 & _GEN_94;\n wire _GEN_247 = io_wb_resps_1_bits_uop_rob_idx == 5'h1C;\n wire _GEN_248 = _GEN_247 | _GEN_159;\n wire _GEN_249 = io_wb_resps_1_valid ? ~_GEN_248 & _GEN_95 : ~_GEN_159 & _GEN_95;\n wire _GEN_250 = io_wb_resps_1_bits_uop_rob_idx == 5'h1D;\n wire _GEN_251 = _GEN_250 | _GEN_160;\n wire _GEN_252 = io_wb_resps_1_valid ? ~_GEN_251 & _GEN_96 : ~_GEN_160 & _GEN_96;\n wire _GEN_253 = io_wb_resps_1_bits_uop_rob_idx == 5'h1E;\n wire _GEN_254 = _GEN_253 | _GEN_161;\n wire _GEN_255 = io_wb_resps_1_valid ? ~_GEN_254 & _GEN_97 : ~_GEN_161 & _GEN_97;\n wire _GEN_256 = (&io_wb_resps_1_bits_uop_rob_idx) | _GEN_162;\n wire _GEN_257 = io_wb_resps_1_valid ? ~_GEN_256 & _GEN_98 : ~_GEN_162 & _GEN_98;\n wire _GEN_258 = io_wb_resps_1_valid ? ~_GEN_164 & _GEN_99 : ~_GEN_131 & _GEN_99;\n wire _GEN_259 = io_wb_resps_1_valid ? ~_GEN_167 & _GEN_100 : ~_GEN_132 & _GEN_100;\n wire _GEN_260 = io_wb_resps_1_valid ? ~_GEN_170 & _GEN_101 : ~_GEN_133 & _GEN_101;\n wire _GEN_261 = io_wb_resps_1_valid ? ~_GEN_173 & _GEN_102 : ~_GEN_134 & _GEN_102;\n wire _GEN_262 = io_wb_resps_1_valid ? ~_GEN_176 & _GEN_103 : ~_GEN_135 & _GEN_103;\n wire _GEN_263 = io_wb_resps_1_valid ? ~_GEN_179 & _GEN_104 : ~_GEN_136 & _GEN_104;\n wire _GEN_264 = io_wb_resps_1_valid ? ~_GEN_182 & _GEN_105 : ~_GEN_137 & _GEN_105;\n wire _GEN_265 = io_wb_resps_1_valid ? ~_GEN_185 & _GEN_106 : ~_GEN_138 & _GEN_106;\n wire _GEN_266 = io_wb_resps_1_valid ? ~_GEN_188 & _GEN_107 : ~_GEN_139 & _GEN_107;\n wire _GEN_267 = io_wb_resps_1_valid ? ~_GEN_191 & _GEN_108 : ~_GEN_140 & _GEN_108;\n wire _GEN_268 = io_wb_resps_1_valid ? ~_GEN_194 & _GEN_109 : ~_GEN_141 & _GEN_109;\n wire _GEN_269 = io_wb_resps_1_valid ? ~_GEN_197 & _GEN_110 : ~_GEN_142 & _GEN_110;\n wire _GEN_270 = io_wb_resps_1_valid ? ~_GEN_200 & _GEN_111 : ~_GEN_143 & _GEN_111;\n wire _GEN_271 = io_wb_resps_1_valid ? ~_GEN_203 & _GEN_112 : ~_GEN_144 & _GEN_112;\n wire _GEN_272 = io_wb_resps_1_valid ? ~_GEN_206 & _GEN_113 : ~_GEN_145 & _GEN_113;\n wire _GEN_273 = io_wb_resps_1_valid ? ~_GEN_209 & _GEN_114 : ~_GEN_146 & _GEN_114;\n wire _GEN_274 = io_wb_resps_1_valid ? ~_GEN_212 & _GEN_115 : ~_GEN_147 & _GEN_115;\n wire _GEN_275 = io_wb_resps_1_valid ? ~_GEN_215 & _GEN_116 : ~_GEN_148 & _GEN_116;\n wire _GEN_276 = io_wb_resps_1_valid ? ~_GEN_218 & _GEN_117 : ~_GEN_149 & _GEN_117;\n wire _GEN_277 = io_wb_resps_1_valid ? ~_GEN_221 & _GEN_118 : ~_GEN_150 & _GEN_118;\n wire _GEN_278 = io_wb_resps_1_valid ? ~_GEN_224 & _GEN_119 : ~_GEN_151 & _GEN_119;\n wire _GEN_279 = io_wb_resps_1_valid ? ~_GEN_227 & _GEN_120 : ~_GEN_152 & _GEN_120;\n wire _GEN_280 = io_wb_resps_1_valid ? ~_GEN_230 & _GEN_121 : ~_GEN_153 & _GEN_121;\n wire _GEN_281 = io_wb_resps_1_valid ? ~_GEN_233 & _GEN_122 : ~_GEN_154 & _GEN_122;\n wire _GEN_282 = io_wb_resps_1_valid ? ~_GEN_236 & _GEN_123 : ~_GEN_155 & _GEN_123;\n wire _GEN_283 = io_wb_resps_1_valid ? ~_GEN_239 & _GEN_124 : ~_GEN_156 & _GEN_124;\n wire _GEN_284 = io_wb_resps_1_valid ? ~_GEN_242 & _GEN_125 : ~_GEN_157 & _GEN_125;\n wire _GEN_285 = io_wb_resps_1_valid ? ~_GEN_245 & _GEN_126 : ~_GEN_158 & _GEN_126;\n wire _GEN_286 = io_wb_resps_1_valid ? ~_GEN_248 & _GEN_127 : ~_GEN_159 & _GEN_127;\n wire _GEN_287 = io_wb_resps_1_valid ? ~_GEN_251 & _GEN_128 : ~_GEN_160 & _GEN_128;\n wire _GEN_288 = io_wb_resps_1_valid ? ~_GEN_254 & _GEN_129 : ~_GEN_161 & _GEN_129;\n wire _GEN_289 = io_wb_resps_1_valid ? ~_GEN_256 & _GEN_130 : ~_GEN_162 & _GEN_130;\n wire _GEN_290 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h0;\n wire _GEN_291 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1;\n wire _GEN_292 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h2;\n wire _GEN_293 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h3;\n wire _GEN_294 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h4;\n wire _GEN_295 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h5;\n wire _GEN_296 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h6;\n wire _GEN_297 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h7;\n wire _GEN_298 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h8;\n wire _GEN_299 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h9;\n wire _GEN_300 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hA;\n wire _GEN_301 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hB;\n wire _GEN_302 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hC;\n wire _GEN_303 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hD;\n wire _GEN_304 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hE;\n wire _GEN_305 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'hF;\n wire _GEN_306 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h10;\n wire _GEN_307 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h11;\n wire _GEN_308 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h12;\n wire _GEN_309 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h13;\n wire _GEN_310 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h14;\n wire _GEN_311 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h15;\n wire _GEN_312 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h16;\n wire _GEN_313 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h17;\n wire _GEN_314 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h18;\n wire _GEN_315 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h19;\n wire _GEN_316 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1A;\n wire _GEN_317 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1B;\n wire _GEN_318 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1C;\n wire _GEN_319 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1D;\n wire _GEN_320 = io_wb_resps_2_valid & io_wb_resps_2_bits_uop_rob_idx == 5'h1E;\n wire _GEN_321 = io_wb_resps_2_valid & (&io_wb_resps_2_bits_uop_rob_idx);\n wire _GEN_322 = io_wb_resps_3_bits_uop_rob_idx == 5'h0;\n wire _GEN_323 = _GEN_322 | _GEN_290;\n wire _GEN_324 = io_wb_resps_3_valid ? ~_GEN_323 & _GEN_165 : ~_GEN_290 & _GEN_165;\n wire _GEN_325 = io_wb_resps_3_bits_uop_rob_idx == 5'h1;\n wire _GEN_326 = _GEN_325 | _GEN_291;\n wire _GEN_327 = io_wb_resps_3_valid ? ~_GEN_326 & _GEN_168 : ~_GEN_291 & _GEN_168;\n wire _GEN_328 = io_wb_resps_3_bits_uop_rob_idx == 5'h2;\n wire _GEN_329 = _GEN_328 | _GEN_292;\n wire _GEN_330 = io_wb_resps_3_valid ? ~_GEN_329 & _GEN_171 : ~_GEN_292 & _GEN_171;\n wire _GEN_331 = io_wb_resps_3_bits_uop_rob_idx == 5'h3;\n wire _GEN_332 = _GEN_331 | _GEN_293;\n wire _GEN_333 = io_wb_resps_3_valid ? ~_GEN_332 & _GEN_174 : ~_GEN_293 & _GEN_174;\n wire _GEN_334 = io_wb_resps_3_bits_uop_rob_idx == 5'h4;\n wire _GEN_335 = _GEN_334 | _GEN_294;\n wire _GEN_336 = io_wb_resps_3_valid ? ~_GEN_335 & _GEN_177 : ~_GEN_294 & _GEN_177;\n wire _GEN_337 = io_wb_resps_3_bits_uop_rob_idx == 5'h5;\n wire _GEN_338 = _GEN_337 | _GEN_295;\n wire _GEN_339 = io_wb_resps_3_valid ? ~_GEN_338 & _GEN_180 : ~_GEN_295 & _GEN_180;\n wire _GEN_340 = io_wb_resps_3_bits_uop_rob_idx == 5'h6;\n wire _GEN_341 = _GEN_340 | _GEN_296;\n wire _GEN_342 = io_wb_resps_3_valid ? ~_GEN_341 & _GEN_183 : ~_GEN_296 & _GEN_183;\n wire _GEN_343 = io_wb_resps_3_bits_uop_rob_idx == 5'h7;\n wire _GEN_344 = _GEN_343 | _GEN_297;\n wire _GEN_345 = io_wb_resps_3_valid ? ~_GEN_344 & _GEN_186 : ~_GEN_297 & _GEN_186;\n wire _GEN_346 = io_wb_resps_3_bits_uop_rob_idx == 5'h8;\n wire _GEN_347 = _GEN_346 | _GEN_298;\n wire _GEN_348 = io_wb_resps_3_valid ? ~_GEN_347 & _GEN_189 : ~_GEN_298 & _GEN_189;\n wire _GEN_349 = io_wb_resps_3_bits_uop_rob_idx == 5'h9;\n wire _GEN_350 = _GEN_349 | _GEN_299;\n wire _GEN_351 = io_wb_resps_3_valid ? ~_GEN_350 & _GEN_192 : ~_GEN_299 & _GEN_192;\n wire _GEN_352 = io_wb_resps_3_bits_uop_rob_idx == 5'hA;\n wire _GEN_353 = _GEN_352 | _GEN_300;\n wire _GEN_354 = io_wb_resps_3_valid ? ~_GEN_353 & _GEN_195 : ~_GEN_300 & _GEN_195;\n wire _GEN_355 = io_wb_resps_3_bits_uop_rob_idx == 5'hB;\n wire _GEN_356 = _GEN_355 | _GEN_301;\n wire _GEN_357 = io_wb_resps_3_valid ? ~_GEN_356 & _GEN_198 : ~_GEN_301 & _GEN_198;\n wire _GEN_358 = io_wb_resps_3_bits_uop_rob_idx == 5'hC;\n wire _GEN_359 = _GEN_358 | _GEN_302;\n wire _GEN_360 = io_wb_resps_3_valid ? ~_GEN_359 & _GEN_201 : ~_GEN_302 & _GEN_201;\n wire _GEN_361 = io_wb_resps_3_bits_uop_rob_idx == 5'hD;\n wire _GEN_362 = _GEN_361 | _GEN_303;\n wire _GEN_363 = io_wb_resps_3_valid ? ~_GEN_362 & _GEN_204 : ~_GEN_303 & _GEN_204;\n wire _GEN_364 = io_wb_resps_3_bits_uop_rob_idx == 5'hE;\n wire _GEN_365 = _GEN_364 | _GEN_304;\n wire _GEN_366 = io_wb_resps_3_valid ? ~_GEN_365 & _GEN_207 : ~_GEN_304 & _GEN_207;\n wire _GEN_367 = io_wb_resps_3_bits_uop_rob_idx == 5'hF;\n wire _GEN_368 = _GEN_367 | _GEN_305;\n wire _GEN_369 = io_wb_resps_3_valid ? ~_GEN_368 & _GEN_210 : ~_GEN_305 & _GEN_210;\n wire _GEN_370 = io_wb_resps_3_bits_uop_rob_idx == 5'h10;\n wire _GEN_371 = _GEN_370 | _GEN_306;\n wire _GEN_372 = io_wb_resps_3_valid ? ~_GEN_371 & _GEN_213 : ~_GEN_306 & _GEN_213;\n wire _GEN_373 = io_wb_resps_3_bits_uop_rob_idx == 5'h11;\n wire _GEN_374 = _GEN_373 | _GEN_307;\n wire _GEN_375 = io_wb_resps_3_valid ? ~_GEN_374 & _GEN_216 : ~_GEN_307 & _GEN_216;\n wire _GEN_376 = io_wb_resps_3_bits_uop_rob_idx == 5'h12;\n wire _GEN_377 = _GEN_376 | _GEN_308;\n wire _GEN_378 = io_wb_resps_3_valid ? ~_GEN_377 & _GEN_219 : ~_GEN_308 & _GEN_219;\n wire _GEN_379 = io_wb_resps_3_bits_uop_rob_idx == 5'h13;\n wire _GEN_380 = _GEN_379 | _GEN_309;\n wire _GEN_381 = io_wb_resps_3_valid ? ~_GEN_380 & _GEN_222 : ~_GEN_309 & _GEN_222;\n wire _GEN_382 = io_wb_resps_3_bits_uop_rob_idx == 5'h14;\n wire _GEN_383 = _GEN_382 | _GEN_310;\n wire _GEN_384 = io_wb_resps_3_valid ? ~_GEN_383 & _GEN_225 : ~_GEN_310 & _GEN_225;\n wire _GEN_385 = io_wb_resps_3_bits_uop_rob_idx == 5'h15;\n wire _GEN_386 = _GEN_385 | _GEN_311;\n wire _GEN_387 = io_wb_resps_3_valid ? ~_GEN_386 & _GEN_228 : ~_GEN_311 & _GEN_228;\n wire _GEN_388 = io_wb_resps_3_bits_uop_rob_idx == 5'h16;\n wire _GEN_389 = _GEN_388 | _GEN_312;\n wire _GEN_390 = io_wb_resps_3_valid ? ~_GEN_389 & _GEN_231 : ~_GEN_312 & _GEN_231;\n wire _GEN_391 = io_wb_resps_3_bits_uop_rob_idx == 5'h17;\n wire _GEN_392 = _GEN_391 | _GEN_313;\n wire _GEN_393 = io_wb_resps_3_valid ? ~_GEN_392 & _GEN_234 : ~_GEN_313 & _GEN_234;\n wire _GEN_394 = io_wb_resps_3_bits_uop_rob_idx == 5'h18;\n wire _GEN_395 = _GEN_394 | _GEN_314;\n wire _GEN_396 = io_wb_resps_3_valid ? ~_GEN_395 & _GEN_237 : ~_GEN_314 & _GEN_237;\n wire _GEN_397 = io_wb_resps_3_bits_uop_rob_idx == 5'h19;\n wire _GEN_398 = _GEN_397 | _GEN_315;\n wire _GEN_399 = io_wb_resps_3_valid ? ~_GEN_398 & _GEN_240 : ~_GEN_315 & _GEN_240;\n wire _GEN_400 = io_wb_resps_3_bits_uop_rob_idx == 5'h1A;\n wire _GEN_401 = _GEN_400 | _GEN_316;\n wire _GEN_402 = io_wb_resps_3_valid ? ~_GEN_401 & _GEN_243 : ~_GEN_316 & _GEN_243;\n wire _GEN_403 = io_wb_resps_3_bits_uop_rob_idx == 5'h1B;\n wire _GEN_404 = _GEN_403 | _GEN_317;\n wire _GEN_405 = io_wb_resps_3_valid ? ~_GEN_404 & _GEN_246 : ~_GEN_317 & _GEN_246;\n wire _GEN_406 = io_wb_resps_3_bits_uop_rob_idx == 5'h1C;\n wire _GEN_407 = _GEN_406 | _GEN_318;\n wire _GEN_408 = io_wb_resps_3_valid ? ~_GEN_407 & _GEN_249 : ~_GEN_318 & _GEN_249;\n wire _GEN_409 = io_wb_resps_3_bits_uop_rob_idx == 5'h1D;\n wire _GEN_410 = _GEN_409 | _GEN_319;\n wire _GEN_411 = io_wb_resps_3_valid ? ~_GEN_410 & _GEN_252 : ~_GEN_319 & _GEN_252;\n wire _GEN_412 = io_wb_resps_3_bits_uop_rob_idx == 5'h1E;\n wire _GEN_413 = _GEN_412 | _GEN_320;\n wire _GEN_414 = io_wb_resps_3_valid ? ~_GEN_413 & _GEN_255 : ~_GEN_320 & _GEN_255;\n wire _GEN_415 = (&io_wb_resps_3_bits_uop_rob_idx) | _GEN_321;\n wire _GEN_416 = io_wb_resps_3_valid ? ~_GEN_415 & _GEN_257 : ~_GEN_321 & _GEN_257;\n wire _GEN_417 = io_wb_resps_3_valid ? ~_GEN_323 & _GEN_258 : ~_GEN_290 & _GEN_258;\n wire _GEN_418 = io_wb_resps_3_valid ? ~_GEN_326 & _GEN_259 : ~_GEN_291 & _GEN_259;\n wire _GEN_419 = io_wb_resps_3_valid ? ~_GEN_329 & _GEN_260 : ~_GEN_292 & _GEN_260;\n wire _GEN_420 = io_wb_resps_3_valid ? ~_GEN_332 & _GEN_261 : ~_GEN_293 & _GEN_261;\n wire _GEN_421 = io_wb_resps_3_valid ? ~_GEN_335 & _GEN_262 : ~_GEN_294 & _GEN_262;\n wire _GEN_422 = io_wb_resps_3_valid ? ~_GEN_338 & _GEN_263 : ~_GEN_295 & _GEN_263;\n wire _GEN_423 = io_wb_resps_3_valid ? ~_GEN_341 & _GEN_264 : ~_GEN_296 & _GEN_264;\n wire _GEN_424 = io_wb_resps_3_valid ? ~_GEN_344 & _GEN_265 : ~_GEN_297 & _GEN_265;\n wire _GEN_425 = io_wb_resps_3_valid ? ~_GEN_347 & _GEN_266 : ~_GEN_298 & _GEN_266;\n wire _GEN_426 = io_wb_resps_3_valid ? ~_GEN_350 & _GEN_267 : ~_GEN_299 & _GEN_267;\n wire _GEN_427 = io_wb_resps_3_valid ? ~_GEN_353 & _GEN_268 : ~_GEN_300 & _GEN_268;\n wire _GEN_428 = io_wb_resps_3_valid ? ~_GEN_356 & _GEN_269 : ~_GEN_301 & _GEN_269;\n wire _GEN_429 = io_wb_resps_3_valid ? ~_GEN_359 & _GEN_270 : ~_GEN_302 & _GEN_270;\n wire _GEN_430 = io_wb_resps_3_valid ? ~_GEN_362 & _GEN_271 : ~_GEN_303 & _GEN_271;\n wire _GEN_431 = io_wb_resps_3_valid ? ~_GEN_365 & _GEN_272 : ~_GEN_304 & _GEN_272;\n wire _GEN_432 = io_wb_resps_3_valid ? ~_GEN_368 & _GEN_273 : ~_GEN_305 & _GEN_273;\n wire _GEN_433 = io_wb_resps_3_valid ? ~_GEN_371 & _GEN_274 : ~_GEN_306 & _GEN_274;\n wire _GEN_434 = io_wb_resps_3_valid ? ~_GEN_374 & _GEN_275 : ~_GEN_307 & _GEN_275;\n wire _GEN_435 = io_wb_resps_3_valid ? ~_GEN_377 & _GEN_276 : ~_GEN_308 & _GEN_276;\n wire _GEN_436 = io_wb_resps_3_valid ? ~_GEN_380 & _GEN_277 : ~_GEN_309 & _GEN_277;\n wire _GEN_437 = io_wb_resps_3_valid ? ~_GEN_383 & _GEN_278 : ~_GEN_310 & _GEN_278;\n wire _GEN_438 = io_wb_resps_3_valid ? ~_GEN_386 & _GEN_279 : ~_GEN_311 & _GEN_279;\n wire _GEN_439 = io_wb_resps_3_valid ? ~_GEN_389 & _GEN_280 : ~_GEN_312 & _GEN_280;\n wire _GEN_440 = io_wb_resps_3_valid ? ~_GEN_392 & _GEN_281 : ~_GEN_313 & _GEN_281;\n wire _GEN_441 = io_wb_resps_3_valid ? ~_GEN_395 & _GEN_282 : ~_GEN_314 & _GEN_282;\n wire _GEN_442 = io_wb_resps_3_valid ? ~_GEN_398 & _GEN_283 : ~_GEN_315 & _GEN_283;\n wire _GEN_443 = io_wb_resps_3_valid ? ~_GEN_401 & _GEN_284 : ~_GEN_316 & _GEN_284;\n wire _GEN_444 = io_wb_resps_3_valid ? ~_GEN_404 & _GEN_285 : ~_GEN_317 & _GEN_285;\n wire _GEN_445 = io_wb_resps_3_valid ? ~_GEN_407 & _GEN_286 : ~_GEN_318 & _GEN_286;\n wire _GEN_446 = io_wb_resps_3_valid ? ~_GEN_410 & _GEN_287 : ~_GEN_319 & _GEN_287;\n wire _GEN_447 = io_wb_resps_3_valid ? ~_GEN_413 & _GEN_288 : ~_GEN_320 & _GEN_288;\n wire _GEN_448 = io_wb_resps_3_valid ? ~_GEN_415 & _GEN_289 : ~_GEN_321 & _GEN_289;\n wire _GEN_449 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h0;\n wire _GEN_450 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1;\n wire _GEN_451 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h2;\n wire _GEN_452 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h3;\n wire _GEN_453 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h4;\n wire _GEN_454 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h5;\n wire _GEN_455 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h6;\n wire _GEN_456 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h7;\n wire _GEN_457 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h8;\n wire _GEN_458 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h9;\n wire _GEN_459 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hA;\n wire _GEN_460 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hB;\n wire _GEN_461 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hC;\n wire _GEN_462 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hD;\n wire _GEN_463 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hE;\n wire _GEN_464 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'hF;\n wire _GEN_465 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h10;\n wire _GEN_466 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h11;\n wire _GEN_467 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h12;\n wire _GEN_468 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h13;\n wire _GEN_469 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h14;\n wire _GEN_470 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h15;\n wire _GEN_471 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h16;\n wire _GEN_472 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h17;\n wire _GEN_473 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h18;\n wire _GEN_474 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h19;\n wire _GEN_475 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1A;\n wire _GEN_476 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1B;\n wire _GEN_477 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1C;\n wire _GEN_478 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1D;\n wire _GEN_479 = io_lsu_clr_bsy_0_valid & io_lsu_clr_bsy_0_bits == 5'h1E;\n wire _GEN_480 = io_lsu_clr_bsy_0_valid & (&io_lsu_clr_bsy_0_bits);\n wire _GEN_481 = io_lsu_clr_bsy_1_bits == 5'h0 | _GEN_449;\n wire _GEN_482 = io_lsu_clr_bsy_1_bits == 5'h1 | _GEN_450;\n wire _GEN_483 = io_lsu_clr_bsy_1_bits == 5'h2 | _GEN_451;\n wire _GEN_484 = io_lsu_clr_bsy_1_bits == 5'h3 | _GEN_452;\n wire _GEN_485 = io_lsu_clr_bsy_1_bits == 5'h4 | _GEN_453;\n wire _GEN_486 = io_lsu_clr_bsy_1_bits == 5'h5 | _GEN_454;\n wire _GEN_487 = io_lsu_clr_bsy_1_bits == 5'h6 | _GEN_455;\n wire _GEN_488 = io_lsu_clr_bsy_1_bits == 5'h7 | _GEN_456;\n wire _GEN_489 = io_lsu_clr_bsy_1_bits == 5'h8 | _GEN_457;\n wire _GEN_490 = io_lsu_clr_bsy_1_bits == 5'h9 | _GEN_458;\n wire _GEN_491 = io_lsu_clr_bsy_1_bits == 5'hA | _GEN_459;\n wire _GEN_492 = io_lsu_clr_bsy_1_bits == 5'hB | _GEN_460;\n wire _GEN_493 = io_lsu_clr_bsy_1_bits == 5'hC | _GEN_461;\n wire _GEN_494 = io_lsu_clr_bsy_1_bits == 5'hD | _GEN_462;\n wire _GEN_495 = io_lsu_clr_bsy_1_bits == 5'hE | _GEN_463;\n wire _GEN_496 = io_lsu_clr_bsy_1_bits == 5'hF | _GEN_464;\n wire _GEN_497 = io_lsu_clr_bsy_1_bits == 5'h10 | _GEN_465;\n wire _GEN_498 = io_lsu_clr_bsy_1_bits == 5'h11 | _GEN_466;\n wire _GEN_499 = io_lsu_clr_bsy_1_bits == 5'h12 | _GEN_467;\n wire _GEN_500 = io_lsu_clr_bsy_1_bits == 5'h13 | _GEN_468;\n wire _GEN_501 = io_lsu_clr_bsy_1_bits == 5'h14 | _GEN_469;\n wire _GEN_502 = io_lsu_clr_bsy_1_bits == 5'h15 | _GEN_470;\n wire _GEN_503 = io_lsu_clr_bsy_1_bits == 5'h16 | _GEN_471;\n wire _GEN_504 = io_lsu_clr_bsy_1_bits == 5'h17 | _GEN_472;\n wire _GEN_505 = io_lsu_clr_bsy_1_bits == 5'h18 | _GEN_473;\n wire _GEN_506 = io_lsu_clr_bsy_1_bits == 5'h19 | _GEN_474;\n wire _GEN_507 = io_lsu_clr_bsy_1_bits == 5'h1A | _GEN_475;\n wire _GEN_508 = io_lsu_clr_bsy_1_bits == 5'h1B | _GEN_476;\n wire _GEN_509 = io_lsu_clr_bsy_1_bits == 5'h1C | _GEN_477;\n wire _GEN_510 = io_lsu_clr_bsy_1_bits == 5'h1D | _GEN_478;\n wire _GEN_511 = io_lsu_clr_bsy_1_bits == 5'h1E | _GEN_479;\n wire _GEN_512 = (&io_lsu_clr_bsy_1_bits) | _GEN_480;\n wire _GEN_513 = rbk_row & com_idx == 5'h0;\n wire _GEN_514 = rbk_row & com_idx == 5'h1;\n wire _GEN_515 = rbk_row & com_idx == 5'h2;\n wire _GEN_516 = rbk_row & com_idx == 5'h3;\n wire _GEN_517 = rbk_row & com_idx == 5'h4;\n wire _GEN_518 = rbk_row & com_idx == 5'h5;\n wire _GEN_519 = rbk_row & com_idx == 5'h6;\n wire _GEN_520 = rbk_row & com_idx == 5'h7;\n wire _GEN_521 = rbk_row & com_idx == 5'h8;\n wire _GEN_522 = rbk_row & com_idx == 5'h9;\n wire _GEN_523 = rbk_row & com_idx == 5'hA;\n wire _GEN_524 = rbk_row & com_idx == 5'hB;\n wire _GEN_525 = rbk_row & com_idx == 5'hC;\n wire _GEN_526 = rbk_row & com_idx == 5'hD;\n wire _GEN_527 = rbk_row & com_idx == 5'hE;\n wire _GEN_528 = rbk_row & com_idx == 5'hF;\n wire _GEN_529 = rbk_row & com_idx == 5'h10;\n wire _GEN_530 = rbk_row & com_idx == 5'h11;\n wire _GEN_531 = rbk_row & com_idx == 5'h12;\n wire _GEN_532 = rbk_row & com_idx == 5'h13;\n wire _GEN_533 = rbk_row & com_idx == 5'h14;\n wire _GEN_534 = rbk_row & com_idx == 5'h15;\n wire _GEN_535 = rbk_row & com_idx == 5'h16;\n wire _GEN_536 = rbk_row & com_idx == 5'h17;\n wire _GEN_537 = rbk_row & com_idx == 5'h18;\n wire _GEN_538 = rbk_row & com_idx == 5'h19;\n wire _GEN_539 = rbk_row & com_idx == 5'h1A;\n wire _GEN_540 = rbk_row & com_idx == 5'h1B;\n wire _GEN_541 = rbk_row & com_idx == 5'h1C;\n wire _GEN_542 = rbk_row & com_idx == 5'h1D;\n wire _GEN_543 = rbk_row & com_idx == 5'h1E;\n wire _GEN_544 = rbk_row & (&com_idx);\n wire [7:0] _GEN_545 = io_brupdate_b1_mispredict_mask & rob_uop_0_br_mask;\n wire [7:0] _GEN_546 = io_brupdate_b1_mispredict_mask & rob_uop_1_br_mask;\n wire [7:0] _GEN_547 = io_brupdate_b1_mispredict_mask & rob_uop_2_br_mask;\n wire [7:0] _GEN_548 = io_brupdate_b1_mispredict_mask & rob_uop_3_br_mask;\n wire [7:0] _GEN_549 = io_brupdate_b1_mispredict_mask & rob_uop_4_br_mask;\n wire [7:0] _GEN_550 = io_brupdate_b1_mispredict_mask & rob_uop_5_br_mask;\n wire [7:0] _GEN_551 = io_brupdate_b1_mispredict_mask & rob_uop_6_br_mask;\n wire [7:0] _GEN_552 = io_brupdate_b1_mispredict_mask & rob_uop_7_br_mask;\n wire [7:0] _GEN_553 = io_brupdate_b1_mispredict_mask & rob_uop_8_br_mask;\n wire [7:0] _GEN_554 = io_brupdate_b1_mispredict_mask & rob_uop_9_br_mask;\n wire [7:0] _GEN_555 = io_brupdate_b1_mispredict_mask & rob_uop_10_br_mask;\n wire [7:0] _GEN_556 = io_brupdate_b1_mispredict_mask & rob_uop_11_br_mask;\n wire [7:0] _GEN_557 = io_brupdate_b1_mispredict_mask & rob_uop_12_br_mask;\n wire [7:0] _GEN_558 = io_brupdate_b1_mispredict_mask & rob_uop_13_br_mask;\n wire [7:0] _GEN_559 = io_brupdate_b1_mispredict_mask & rob_uop_14_br_mask;\n wire [7:0] _GEN_560 = io_brupdate_b1_mispredict_mask & rob_uop_15_br_mask;\n wire [7:0] _GEN_561 = io_brupdate_b1_mispredict_mask & rob_uop_16_br_mask;\n wire [7:0] _GEN_562 = io_brupdate_b1_mispredict_mask & rob_uop_17_br_mask;\n wire [7:0] _GEN_563 = io_brupdate_b1_mispredict_mask & rob_uop_18_br_mask;\n wire [7:0] _GEN_564 = io_brupdate_b1_mispredict_mask & rob_uop_19_br_mask;\n wire [7:0] _GEN_565 = io_brupdate_b1_mispredict_mask & rob_uop_20_br_mask;\n wire [7:0] _GEN_566 = io_brupdate_b1_mispredict_mask & rob_uop_21_br_mask;\n wire [7:0] _GEN_567 = io_brupdate_b1_mispredict_mask & rob_uop_22_br_mask;\n wire [7:0] _GEN_568 = io_brupdate_b1_mispredict_mask & rob_uop_23_br_mask;\n wire [7:0] _GEN_569 = io_brupdate_b1_mispredict_mask & rob_uop_24_br_mask;\n wire [7:0] _GEN_570 = io_brupdate_b1_mispredict_mask & rob_uop_25_br_mask;\n wire [7:0] _GEN_571 = io_brupdate_b1_mispredict_mask & rob_uop_26_br_mask;\n wire [7:0] _GEN_572 = io_brupdate_b1_mispredict_mask & rob_uop_27_br_mask;\n wire [7:0] _GEN_573 = io_brupdate_b1_mispredict_mask & rob_uop_28_br_mask;\n wire [7:0] _GEN_574 = io_brupdate_b1_mispredict_mask & rob_uop_29_br_mask;\n wire [7:0] _GEN_575 = io_brupdate_b1_mispredict_mask & rob_uop_30_br_mask;\n wire [7:0] _GEN_576 = io_brupdate_b1_mispredict_mask & rob_uop_31_br_mask;\n wire _GEN_577 = ~flush_val & rob_state != 2'h2;\n wire _GEN_578 = ~r_xcpt_val | io_lxcpt_bits_uop_rob_idx < r_xcpt_uop_rob_idx ^ io_lxcpt_bits_uop_rob_idx < rob_head ^ r_xcpt_uop_rob_idx < rob_head;\n wire _GEN_579 = ~r_xcpt_val & io_enq_valids_0 & io_enq_uops_0_exception;\n wire [7:0] next_xcpt_uop_br_mask = _GEN_577 ? (io_lxcpt_valid ? (_GEN_578 ? io_lxcpt_bits_uop_br_mask : r_xcpt_uop_br_mask) : _GEN_579 ? io_enq_uops_0_br_mask : r_xcpt_uop_br_mask) : r_xcpt_uop_br_mask;\n wire _GEN_580 = _GEN_35 | rob_val_0;\n wire _GEN_581 = _GEN_36 | rob_val_1;\n wire _GEN_582 = _GEN_37 | rob_val_2;\n wire _GEN_583 = _GEN_38 | rob_val_3;\n wire _GEN_584 = _GEN_39 | rob_val_4;\n wire _GEN_585 = _GEN_40 | rob_val_5;\n wire _GEN_586 = _GEN_41 | rob_val_6;\n wire _GEN_587 = _GEN_42 | rob_val_7;\n wire _GEN_588 = _GEN_43 | rob_val_8;\n wire _GEN_589 = _GEN_44 | rob_val_9;\n wire _GEN_590 = _GEN_45 | rob_val_10;\n wire _GEN_591 = _GEN_46 | rob_val_11;\n wire _GEN_592 = _GEN_47 | rob_val_12;\n wire _GEN_593 = _GEN_48 | rob_val_13;\n wire _GEN_594 = _GEN_49 | rob_val_14;\n wire _GEN_595 = _GEN_50 | rob_val_15;\n wire _GEN_596 = _GEN_51 | rob_val_16;\n wire _GEN_597 = _GEN_52 | rob_val_17;\n wire _GEN_598 = _GEN_53 | rob_val_18;\n wire _GEN_599 = _GEN_54 | rob_val_19;\n wire _GEN_600 = _GEN_55 | rob_val_20;\n wire _GEN_601 = _GEN_56 | rob_val_21;\n wire _GEN_602 = _GEN_57 | rob_val_22;\n wire _GEN_603 = _GEN_58 | rob_val_23;\n wire _GEN_604 = _GEN_59 | rob_val_24;\n wire _GEN_605 = _GEN_60 | rob_val_25;\n wire _GEN_606 = _GEN_61 | rob_val_26;\n wire _GEN_607 = _GEN_62 | rob_val_27;\n wire _GEN_608 = _GEN_63 | rob_val_28;\n wire _GEN_609 = _GEN_64 | rob_val_29;\n wire _GEN_610 = _GEN_65 | rob_val_30;\n wire _GEN_611 = _GEN_66 | rob_val_31;\n always @(posedge clock) begin\n if (_GEN_1)\n assert__assert_6: assert(_GEN_2[io_lxcpt_bits_uop_rob_idx]);\n if (reset) begin\n rob_state <= 2'h0;\n rob_head <= 5'h0;\n rob_tail <= 5'h0;\n rob_pnr <= 5'h0;\n maybe_full <= 1'h0;\n r_xcpt_val <= 1'h0;\n rob_val_0 <= 1'h0;\n rob_val_1 <= 1'h0;\n rob_val_2 <= 1'h0;\n rob_val_3 <= 1'h0;\n rob_val_4 <= 1'h0;\n rob_val_5 <= 1'h0;\n rob_val_6 <= 1'h0;\n rob_val_7 <= 1'h0;\n rob_val_8 <= 1'h0;\n rob_val_9 <= 1'h0;\n rob_val_10 <= 1'h0;\n rob_val_11 <= 1'h0;\n rob_val_12 <= 1'h0;\n rob_val_13 <= 1'h0;\n rob_val_14 <= 1'h0;\n rob_val_15 <= 1'h0;\n rob_val_16 <= 1'h0;\n rob_val_17 <= 1'h0;\n rob_val_18 <= 1'h0;\n rob_val_19 <= 1'h0;\n rob_val_20 <= 1'h0;\n rob_val_21 <= 1'h0;\n rob_val_22 <= 1'h0;\n rob_val_23 <= 1'h0;\n rob_val_24 <= 1'h0;\n rob_val_25 <= 1'h0;\n rob_val_26 <= 1'h0;\n rob_val_27 <= 1'h0;\n rob_val_28 <= 1'h0;\n rob_val_29 <= 1'h0;\n rob_val_30 <= 1'h0;\n rob_val_31 <= 1'h0;\n r_partial_row <= 1'h0;\n pnr_maybe_at_tail <= 1'h0;\n end\n else begin\n rob_state <= _GEN_34[rob_state];\n if (finished_committing_row)\n rob_head <= rob_head + 5'h1;\n if (_GEN_30)\n rob_tail <= rob_tail - 5'h1;\n else if (~_GEN_31) begin\n if (io_brupdate_b2_mispredict)\n rob_tail <= io_brupdate_b2_uop_rob_idx + 5'h1;\n else if (_GEN_32)\n rob_tail <= rob_tail + 5'h1;\n end\n if (empty & io_enq_valids_0)\n rob_pnr <= rob_head;\n else if ((_io_ready_T | (&rob_state)) & do_inc_row)\n rob_pnr <= rob_pnr + 5'h1;\n maybe_full <= |{~rob_deq & (~(_GEN_30 | _GEN_31 | io_brupdate_b2_mispredict) & _GEN_32 | maybe_full), io_brupdate_b1_mispredict_mask};\n r_xcpt_val <= {flush_val, io_brupdate_b1_mispredict_mask & next_xcpt_uop_br_mask} == 9'h0 & (_GEN_577 ? (io_lxcpt_valid ? _GEN_578 | r_xcpt_val : _GEN_579 | r_xcpt_val) : r_xcpt_val);\n rob_val_0 <= will_commit_0 ? ~((|{rob_head == 5'h0, _GEN_545}) | _GEN_513) & _GEN_580 : ~((|_GEN_545) | _GEN_513) & _GEN_580;\n rob_val_1 <= will_commit_0 ? ~((|{rob_head == 5'h1, _GEN_546}) | _GEN_514) & _GEN_581 : ~((|_GEN_546) | _GEN_514) & _GEN_581;\n rob_val_2 <= will_commit_0 ? ~((|{rob_head == 5'h2, _GEN_547}) | _GEN_515) & _GEN_582 : ~((|_GEN_547) | _GEN_515) & _GEN_582;\n rob_val_3 <= will_commit_0 ? ~((|{rob_head == 5'h3, _GEN_548}) | _GEN_516) & _GEN_583 : ~((|_GEN_548) | _GEN_516) & _GEN_583;\n rob_val_4 <= will_commit_0 ? ~((|{rob_head == 5'h4, _GEN_549}) | _GEN_517) & _GEN_584 : ~((|_GEN_549) | _GEN_517) & _GEN_584;\n rob_val_5 <= will_commit_0 ? ~((|{rob_head == 5'h5, _GEN_550}) | _GEN_518) & _GEN_585 : ~((|_GEN_550) | _GEN_518) & _GEN_585;\n rob_val_6 <= will_commit_0 ? ~((|{rob_head == 5'h6, _GEN_551}) | _GEN_519) & _GEN_586 : ~((|_GEN_551) | _GEN_519) & _GEN_586;\n rob_val_7 <= will_commit_0 ? ~((|{rob_head == 5'h7, _GEN_552}) | _GEN_520) & _GEN_587 : ~((|_GEN_552) | _GEN_520) & _GEN_587;\n rob_val_8 <= will_commit_0 ? ~((|{rob_head == 5'h8, _GEN_553}) | _GEN_521) & _GEN_588 : ~((|_GEN_553) | _GEN_521) & _GEN_588;\n rob_val_9 <= will_commit_0 ? ~((|{rob_head == 5'h9, _GEN_554}) | _GEN_522) & _GEN_589 : ~((|_GEN_554) | _GEN_522) & _GEN_589;\n rob_val_10 <= will_commit_0 ? ~((|{rob_head == 5'hA, _GEN_555}) | _GEN_523) & _GEN_590 : ~((|_GEN_555) | _GEN_523) & _GEN_590;\n rob_val_11 <= will_commit_0 ? ~((|{rob_head == 5'hB, _GEN_556}) | _GEN_524) & _GEN_591 : ~((|_GEN_556) | _GEN_524) & _GEN_591;\n rob_val_12 <= will_commit_0 ? ~((|{rob_head == 5'hC, _GEN_557}) | _GEN_525) & _GEN_592 : ~((|_GEN_557) | _GEN_525) & _GEN_592;\n rob_val_13 <= will_commit_0 ? ~((|{rob_head == 5'hD, _GEN_558}) | _GEN_526) & _GEN_593 : ~((|_GEN_558) | _GEN_526) & _GEN_593;\n rob_val_14 <= will_commit_0 ? ~((|{rob_head == 5'hE, _GEN_559}) | _GEN_527) & _GEN_594 : ~((|_GEN_559) | _GEN_527) & _GEN_594;\n rob_val_15 <= will_commit_0 ? ~((|{rob_head == 5'hF, _GEN_560}) | _GEN_528) & _GEN_595 : ~((|_GEN_560) | _GEN_528) & _GEN_595;\n rob_val_16 <= will_commit_0 ? ~((|{rob_head == 5'h10, _GEN_561}) | _GEN_529) & _GEN_596 : ~((|_GEN_561) | _GEN_529) & _GEN_596;\n rob_val_17 <= will_commit_0 ? ~((|{rob_head == 5'h11, _GEN_562}) | _GEN_530) & _GEN_597 : ~((|_GEN_562) | _GEN_530) & _GEN_597;\n rob_val_18 <= will_commit_0 ? ~((|{rob_head == 5'h12, _GEN_563}) | _GEN_531) & _GEN_598 : ~((|_GEN_563) | _GEN_531) & _GEN_598;\n rob_val_19 <= will_commit_0 ? ~((|{rob_head == 5'h13, _GEN_564}) | _GEN_532) & _GEN_599 : ~((|_GEN_564) | _GEN_532) & _GEN_599;\n rob_val_20 <= will_commit_0 ? ~((|{rob_head == 5'h14, _GEN_565}) | _GEN_533) & _GEN_600 : ~((|_GEN_565) | _GEN_533) & _GEN_600;\n rob_val_21 <= will_commit_0 ? ~((|{rob_head == 5'h15, _GEN_566}) | _GEN_534) & _GEN_601 : ~((|_GEN_566) | _GEN_534) & _GEN_601;\n rob_val_22 <= will_commit_0 ? ~((|{rob_head == 5'h16, _GEN_567}) | _GEN_535) & _GEN_602 : ~((|_GEN_567) | _GEN_535) & _GEN_602;\n rob_val_23 <= will_commit_0 ? ~((|{rob_head == 5'h17, _GEN_568}) | _GEN_536) & _GEN_603 : ~((|_GEN_568) | _GEN_536) & _GEN_603;\n rob_val_24 <= will_commit_0 ? ~((|{rob_head == 5'h18, _GEN_569}) | _GEN_537) & _GEN_604 : ~((|_GEN_569) | _GEN_537) & _GEN_604;\n rob_val_25 <= will_commit_0 ? ~((|{rob_head == 5'h19, _GEN_570}) | _GEN_538) & _GEN_605 : ~((|_GEN_570) | _GEN_538) & _GEN_605;\n rob_val_26 <= will_commit_0 ? ~((|{rob_head == 5'h1A, _GEN_571}) | _GEN_539) & _GEN_606 : ~((|_GEN_571) | _GEN_539) & _GEN_606;\n rob_val_27 <= will_commit_0 ? ~((|{rob_head == 5'h1B, _GEN_572}) | _GEN_540) & _GEN_607 : ~((|_GEN_572) | _GEN_540) & _GEN_607;\n rob_val_28 <= will_commit_0 ? ~((|{rob_head == 5'h1C, _GEN_573}) | _GEN_541) & _GEN_608 : ~((|_GEN_573) | _GEN_541) & _GEN_608;\n rob_val_29 <= will_commit_0 ? ~((|{rob_head == 5'h1D, _GEN_574}) | _GEN_542) & _GEN_609 : ~((|_GEN_574) | _GEN_542) & _GEN_609;\n rob_val_30 <= will_commit_0 ? ~((|{rob_head == 5'h1E, _GEN_575}) | _GEN_543) & _GEN_610 : ~((|_GEN_575) | _GEN_543) & _GEN_610;\n rob_val_31 <= will_commit_0 ? ~((|{&rob_head, _GEN_576}) | _GEN_544) & _GEN_611 : ~((|_GEN_576) | _GEN_544) & _GEN_611;\n if (io_enq_valids_0)\n r_partial_row <= io_enq_partial_stall;\n pnr_maybe_at_tail <= ~rob_deq & (do_inc_row | pnr_maybe_at_tail);\n end\n r_xcpt_uop_br_mask <= next_xcpt_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n if (_GEN_577) begin\n if (io_lxcpt_valid) begin\n if (_GEN_578) begin\n r_xcpt_uop_rob_idx <= io_lxcpt_bits_uop_rob_idx;\n r_xcpt_uop_exc_cause <= {59'h0, io_lxcpt_bits_cause};\n r_xcpt_badvaddr <= io_lxcpt_bits_badvaddr;\n end\n end\n else if (_GEN_579) begin\n r_xcpt_uop_rob_idx <= io_enq_uops_0_rob_idx;\n r_xcpt_uop_exc_cause <= io_enq_uops_0_exc_cause;\n r_xcpt_badvaddr <= {io_xcpt_fetch_pc[39:6], io_enq_uops_0_pc_lob};\n end\n end\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h0)\n rob_fflags_0_0 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h0)\n rob_fflags_0_0 <= io_fflags_0_bits_flags;\n else if (_GEN_35)\n rob_fflags_0_0 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1)\n rob_fflags_0_1 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1)\n rob_fflags_0_1 <= io_fflags_0_bits_flags;\n else if (_GEN_36)\n rob_fflags_0_1 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h2)\n rob_fflags_0_2 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h2)\n rob_fflags_0_2 <= io_fflags_0_bits_flags;\n else if (_GEN_37)\n rob_fflags_0_2 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h3)\n rob_fflags_0_3 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h3)\n rob_fflags_0_3 <= io_fflags_0_bits_flags;\n else if (_GEN_38)\n rob_fflags_0_3 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h4)\n rob_fflags_0_4 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h4)\n rob_fflags_0_4 <= io_fflags_0_bits_flags;\n else if (_GEN_39)\n rob_fflags_0_4 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h5)\n rob_fflags_0_5 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h5)\n rob_fflags_0_5 <= io_fflags_0_bits_flags;\n else if (_GEN_40)\n rob_fflags_0_5 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h6)\n rob_fflags_0_6 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h6)\n rob_fflags_0_6 <= io_fflags_0_bits_flags;\n else if (_GEN_41)\n rob_fflags_0_6 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h7)\n rob_fflags_0_7 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h7)\n rob_fflags_0_7 <= io_fflags_0_bits_flags;\n else if (_GEN_42)\n rob_fflags_0_7 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h8)\n rob_fflags_0_8 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h8)\n rob_fflags_0_8 <= io_fflags_0_bits_flags;\n else if (_GEN_43)\n rob_fflags_0_8 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h9)\n rob_fflags_0_9 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h9)\n rob_fflags_0_9 <= io_fflags_0_bits_flags;\n else if (_GEN_44)\n rob_fflags_0_9 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hA)\n rob_fflags_0_10 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hA)\n rob_fflags_0_10 <= io_fflags_0_bits_flags;\n else if (_GEN_45)\n rob_fflags_0_10 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hB)\n rob_fflags_0_11 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hB)\n rob_fflags_0_11 <= io_fflags_0_bits_flags;\n else if (_GEN_46)\n rob_fflags_0_11 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hC)\n rob_fflags_0_12 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hC)\n rob_fflags_0_12 <= io_fflags_0_bits_flags;\n else if (_GEN_47)\n rob_fflags_0_12 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hD)\n rob_fflags_0_13 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hD)\n rob_fflags_0_13 <= io_fflags_0_bits_flags;\n else if (_GEN_48)\n rob_fflags_0_13 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hE)\n rob_fflags_0_14 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hE)\n rob_fflags_0_14 <= io_fflags_0_bits_flags;\n else if (_GEN_49)\n rob_fflags_0_14 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'hF)\n rob_fflags_0_15 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'hF)\n rob_fflags_0_15 <= io_fflags_0_bits_flags;\n else if (_GEN_50)\n rob_fflags_0_15 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h10)\n rob_fflags_0_16 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h10)\n rob_fflags_0_16 <= io_fflags_0_bits_flags;\n else if (_GEN_51)\n rob_fflags_0_16 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h11)\n rob_fflags_0_17 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h11)\n rob_fflags_0_17 <= io_fflags_0_bits_flags;\n else if (_GEN_52)\n rob_fflags_0_17 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h12)\n rob_fflags_0_18 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h12)\n rob_fflags_0_18 <= io_fflags_0_bits_flags;\n else if (_GEN_53)\n rob_fflags_0_18 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h13)\n rob_fflags_0_19 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h13)\n rob_fflags_0_19 <= io_fflags_0_bits_flags;\n else if (_GEN_54)\n rob_fflags_0_19 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h14)\n rob_fflags_0_20 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h14)\n rob_fflags_0_20 <= io_fflags_0_bits_flags;\n else if (_GEN_55)\n rob_fflags_0_20 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h15)\n rob_fflags_0_21 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h15)\n rob_fflags_0_21 <= io_fflags_0_bits_flags;\n else if (_GEN_56)\n rob_fflags_0_21 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h16)\n rob_fflags_0_22 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h16)\n rob_fflags_0_22 <= io_fflags_0_bits_flags;\n else if (_GEN_57)\n rob_fflags_0_22 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h17)\n rob_fflags_0_23 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h17)\n rob_fflags_0_23 <= io_fflags_0_bits_flags;\n else if (_GEN_58)\n rob_fflags_0_23 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h18)\n rob_fflags_0_24 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h18)\n rob_fflags_0_24 <= io_fflags_0_bits_flags;\n else if (_GEN_59)\n rob_fflags_0_24 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h19)\n rob_fflags_0_25 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h19)\n rob_fflags_0_25 <= io_fflags_0_bits_flags;\n else if (_GEN_60)\n rob_fflags_0_25 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1A)\n rob_fflags_0_26 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1A)\n rob_fflags_0_26 <= io_fflags_0_bits_flags;\n else if (_GEN_61)\n rob_fflags_0_26 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1B)\n rob_fflags_0_27 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1B)\n rob_fflags_0_27 <= io_fflags_0_bits_flags;\n else if (_GEN_62)\n rob_fflags_0_27 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1C)\n rob_fflags_0_28 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1C)\n rob_fflags_0_28 <= io_fflags_0_bits_flags;\n else if (_GEN_63)\n rob_fflags_0_28 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1D)\n rob_fflags_0_29 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1D)\n rob_fflags_0_29 <= io_fflags_0_bits_flags;\n else if (_GEN_64)\n rob_fflags_0_29 <= 5'h0;\n if (io_fflags_1_valid & io_fflags_1_bits_uop_rob_idx == 5'h1E)\n rob_fflags_0_30 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & io_fflags_0_bits_uop_rob_idx == 5'h1E)\n rob_fflags_0_30 <= io_fflags_0_bits_flags;\n else if (_GEN_65)\n rob_fflags_0_30 <= 5'h0;\n if (io_fflags_1_valid & (&io_fflags_1_bits_uop_rob_idx))\n rob_fflags_0_31 <= io_fflags_1_bits_flags;\n else if (io_fflags_0_valid & (&io_fflags_0_bits_uop_rob_idx))\n rob_fflags_0_31 <= io_fflags_0_bits_flags;\n else if (_GEN_66)\n rob_fflags_0_31 <= 5'h0;\n rob_bsy_0 <= io_lsu_clr_bsy_1_valid ? ~_GEN_481 & _GEN_324 : ~_GEN_449 & _GEN_324;\n rob_bsy_1 <= io_lsu_clr_bsy_1_valid ? ~_GEN_482 & _GEN_327 : ~_GEN_450 & _GEN_327;\n rob_bsy_2 <= io_lsu_clr_bsy_1_valid ? ~_GEN_483 & _GEN_330 : ~_GEN_451 & _GEN_330;\n rob_bsy_3 <= io_lsu_clr_bsy_1_valid ? ~_GEN_484 & _GEN_333 : ~_GEN_452 & _GEN_333;\n rob_bsy_4 <= io_lsu_clr_bsy_1_valid ? ~_GEN_485 & _GEN_336 : ~_GEN_453 & _GEN_336;\n rob_bsy_5 <= io_lsu_clr_bsy_1_valid ? ~_GEN_486 & _GEN_339 : ~_GEN_454 & _GEN_339;\n rob_bsy_6 <= io_lsu_clr_bsy_1_valid ? ~_GEN_487 & _GEN_342 : ~_GEN_455 & _GEN_342;\n rob_bsy_7 <= io_lsu_clr_bsy_1_valid ? ~_GEN_488 & _GEN_345 : ~_GEN_456 & _GEN_345;\n rob_bsy_8 <= io_lsu_clr_bsy_1_valid ? ~_GEN_489 & _GEN_348 : ~_GEN_457 & _GEN_348;\n rob_bsy_9 <= io_lsu_clr_bsy_1_valid ? ~_GEN_490 & _GEN_351 : ~_GEN_458 & _GEN_351;\n rob_bsy_10 <= io_lsu_clr_bsy_1_valid ? ~_GEN_491 & _GEN_354 : ~_GEN_459 & _GEN_354;\n rob_bsy_11 <= io_lsu_clr_bsy_1_valid ? ~_GEN_492 & _GEN_357 : ~_GEN_460 & _GEN_357;\n rob_bsy_12 <= io_lsu_clr_bsy_1_valid ? ~_GEN_493 & _GEN_360 : ~_GEN_461 & _GEN_360;\n rob_bsy_13 <= io_lsu_clr_bsy_1_valid ? ~_GEN_494 & _GEN_363 : ~_GEN_462 & _GEN_363;\n rob_bsy_14 <= io_lsu_clr_bsy_1_valid ? ~_GEN_495 & _GEN_366 : ~_GEN_463 & _GEN_366;\n rob_bsy_15 <= io_lsu_clr_bsy_1_valid ? ~_GEN_496 & _GEN_369 : ~_GEN_464 & _GEN_369;\n rob_bsy_16 <= io_lsu_clr_bsy_1_valid ? ~_GEN_497 & _GEN_372 : ~_GEN_465 & _GEN_372;\n rob_bsy_17 <= io_lsu_clr_bsy_1_valid ? ~_GEN_498 & _GEN_375 : ~_GEN_466 & _GEN_375;\n rob_bsy_18 <= io_lsu_clr_bsy_1_valid ? ~_GEN_499 & _GEN_378 : ~_GEN_467 & _GEN_378;\n rob_bsy_19 <= io_lsu_clr_bsy_1_valid ? ~_GEN_500 & _GEN_381 : ~_GEN_468 & _GEN_381;\n rob_bsy_20 <= io_lsu_clr_bsy_1_valid ? ~_GEN_501 & _GEN_384 : ~_GEN_469 & _GEN_384;\n rob_bsy_21 <= io_lsu_clr_bsy_1_valid ? ~_GEN_502 & _GEN_387 : ~_GEN_470 & _GEN_387;\n rob_bsy_22 <= io_lsu_clr_bsy_1_valid ? ~_GEN_503 & _GEN_390 : ~_GEN_471 & _GEN_390;\n rob_bsy_23 <= io_lsu_clr_bsy_1_valid ? ~_GEN_504 & _GEN_393 : ~_GEN_472 & _GEN_393;\n rob_bsy_24 <= io_lsu_clr_bsy_1_valid ? ~_GEN_505 & _GEN_396 : ~_GEN_473 & _GEN_396;\n rob_bsy_25 <= io_lsu_clr_bsy_1_valid ? ~_GEN_506 & _GEN_399 : ~_GEN_474 & _GEN_399;\n rob_bsy_26 <= io_lsu_clr_bsy_1_valid ? ~_GEN_507 & _GEN_402 : ~_GEN_475 & _GEN_402;\n rob_bsy_27 <= io_lsu_clr_bsy_1_valid ? ~_GEN_508 & _GEN_405 : ~_GEN_476 & _GEN_405;\n rob_bsy_28 <= io_lsu_clr_bsy_1_valid ? ~_GEN_509 & _GEN_408 : ~_GEN_477 & _GEN_408;\n rob_bsy_29 <= io_lsu_clr_bsy_1_valid ? ~_GEN_510 & _GEN_411 : ~_GEN_478 & _GEN_411;\n rob_bsy_30 <= io_lsu_clr_bsy_1_valid ? ~_GEN_511 & _GEN_414 : ~_GEN_479 & _GEN_414;\n rob_bsy_31 <= io_lsu_clr_bsy_1_valid ? ~_GEN_512 & _GEN_416 : ~_GEN_480 & _GEN_416;\n rob_unsafe_0 <= io_lsu_clr_bsy_1_valid ? ~_GEN_481 & _GEN_417 : ~_GEN_449 & _GEN_417;\n rob_unsafe_1 <= io_lsu_clr_bsy_1_valid ? ~_GEN_482 & _GEN_418 : ~_GEN_450 & _GEN_418;\n rob_unsafe_2 <= io_lsu_clr_bsy_1_valid ? ~_GEN_483 & _GEN_419 : ~_GEN_451 & _GEN_419;\n rob_unsafe_3 <= io_lsu_clr_bsy_1_valid ? ~_GEN_484 & _GEN_420 : ~_GEN_452 & _GEN_420;\n rob_unsafe_4 <= io_lsu_clr_bsy_1_valid ? ~_GEN_485 & _GEN_421 : ~_GEN_453 & _GEN_421;\n rob_unsafe_5 <= io_lsu_clr_bsy_1_valid ? ~_GEN_486 & _GEN_422 : ~_GEN_454 & _GEN_422;\n rob_unsafe_6 <= io_lsu_clr_bsy_1_valid ? ~_GEN_487 & _GEN_423 : ~_GEN_455 & _GEN_423;\n rob_unsafe_7 <= io_lsu_clr_bsy_1_valid ? ~_GEN_488 & _GEN_424 : ~_GEN_456 & _GEN_424;\n rob_unsafe_8 <= io_lsu_clr_bsy_1_valid ? ~_GEN_489 & _GEN_425 : ~_GEN_457 & _GEN_425;\n rob_unsafe_9 <= io_lsu_clr_bsy_1_valid ? ~_GEN_490 & _GEN_426 : ~_GEN_458 & _GEN_426;\n rob_unsafe_10 <= io_lsu_clr_bsy_1_valid ? ~_GEN_491 & _GEN_427 : ~_GEN_459 & _GEN_427;\n rob_unsafe_11 <= io_lsu_clr_bsy_1_valid ? ~_GEN_492 & _GEN_428 : ~_GEN_460 & _GEN_428;\n rob_unsafe_12 <= io_lsu_clr_bsy_1_valid ? ~_GEN_493 & _GEN_429 : ~_GEN_461 & _GEN_429;\n rob_unsafe_13 <= io_lsu_clr_bsy_1_valid ? ~_GEN_494 & _GEN_430 : ~_GEN_462 & _GEN_430;\n rob_unsafe_14 <= io_lsu_clr_bsy_1_valid ? ~_GEN_495 & _GEN_431 : ~_GEN_463 & _GEN_431;\n rob_unsafe_15 <= io_lsu_clr_bsy_1_valid ? ~_GEN_496 & _GEN_432 : ~_GEN_464 & _GEN_432;\n rob_unsafe_16 <= io_lsu_clr_bsy_1_valid ? ~_GEN_497 & _GEN_433 : ~_GEN_465 & _GEN_433;\n rob_unsafe_17 <= io_lsu_clr_bsy_1_valid ? ~_GEN_498 & _GEN_434 : ~_GEN_466 & _GEN_434;\n rob_unsafe_18 <= io_lsu_clr_bsy_1_valid ? ~_GEN_499 & _GEN_435 : ~_GEN_467 & _GEN_435;\n rob_unsafe_19 <= io_lsu_clr_bsy_1_valid ? ~_GEN_500 & _GEN_436 : ~_GEN_468 & _GEN_436;\n rob_unsafe_20 <= io_lsu_clr_bsy_1_valid ? ~_GEN_501 & _GEN_437 : ~_GEN_469 & _GEN_437;\n rob_unsafe_21 <= io_lsu_clr_bsy_1_valid ? ~_GEN_502 & _GEN_438 : ~_GEN_470 & _GEN_438;\n rob_unsafe_22 <= io_lsu_clr_bsy_1_valid ? ~_GEN_503 & _GEN_439 : ~_GEN_471 & _GEN_439;\n rob_unsafe_23 <= io_lsu_clr_bsy_1_valid ? ~_GEN_504 & _GEN_440 : ~_GEN_472 & _GEN_440;\n rob_unsafe_24 <= io_lsu_clr_bsy_1_valid ? ~_GEN_505 & _GEN_441 : ~_GEN_473 & _GEN_441;\n rob_unsafe_25 <= io_lsu_clr_bsy_1_valid ? ~_GEN_506 & _GEN_442 : ~_GEN_474 & _GEN_442;\n rob_unsafe_26 <= io_lsu_clr_bsy_1_valid ? ~_GEN_507 & _GEN_443 : ~_GEN_475 & _GEN_443;\n rob_unsafe_27 <= io_lsu_clr_bsy_1_valid ? ~_GEN_508 & _GEN_444 : ~_GEN_476 & _GEN_444;\n rob_unsafe_28 <= io_lsu_clr_bsy_1_valid ? ~_GEN_509 & _GEN_445 : ~_GEN_477 & _GEN_445;\n rob_unsafe_29 <= io_lsu_clr_bsy_1_valid ? ~_GEN_510 & _GEN_446 : ~_GEN_478 & _GEN_446;\n rob_unsafe_30 <= io_lsu_clr_bsy_1_valid ? ~_GEN_511 & _GEN_447 : ~_GEN_479 & _GEN_447;\n rob_unsafe_31 <= io_lsu_clr_bsy_1_valid ? ~_GEN_512 & _GEN_448 : ~_GEN_480 & _GEN_448;\n if (_GEN_35) begin\n rob_uop_0_uopc <= io_enq_uops_0_uopc;\n rob_uop_0_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_0_is_br <= io_enq_uops_0_is_br;\n rob_uop_0_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_0_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_0_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_0_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_0_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_0_pdst <= io_enq_uops_0_pdst;\n rob_uop_0_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_0_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_0_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_0_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_0_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_0_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_0_ldst <= io_enq_uops_0_ldst;\n rob_uop_0_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_0_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_0_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_545) | ~rob_val_0) begin\n if (_GEN_35)\n rob_uop_0_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_0_br_mask <= rob_uop_0_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h0)\n rob_uop_0_debug_fsrc <= 2'h3;\n else if (_GEN_35)\n rob_uop_0_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_36) begin\n rob_uop_1_uopc <= io_enq_uops_0_uopc;\n rob_uop_1_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_1_is_br <= io_enq_uops_0_is_br;\n rob_uop_1_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_1_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_1_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_1_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_1_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_1_pdst <= io_enq_uops_0_pdst;\n rob_uop_1_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_1_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_1_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_1_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_1_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_1_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_1_ldst <= io_enq_uops_0_ldst;\n rob_uop_1_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_1_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_1_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_546) | ~rob_val_1) begin\n if (_GEN_36)\n rob_uop_1_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_1_br_mask <= rob_uop_1_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1)\n rob_uop_1_debug_fsrc <= 2'h3;\n else if (_GEN_36)\n rob_uop_1_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_37) begin\n rob_uop_2_uopc <= io_enq_uops_0_uopc;\n rob_uop_2_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_2_is_br <= io_enq_uops_0_is_br;\n rob_uop_2_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_2_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_2_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_2_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_2_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_2_pdst <= io_enq_uops_0_pdst;\n rob_uop_2_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_2_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_2_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_2_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_2_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_2_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_2_ldst <= io_enq_uops_0_ldst;\n rob_uop_2_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_2_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_2_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_547) | ~rob_val_2) begin\n if (_GEN_37)\n rob_uop_2_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_2_br_mask <= rob_uop_2_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h2)\n rob_uop_2_debug_fsrc <= 2'h3;\n else if (_GEN_37)\n rob_uop_2_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_38) begin\n rob_uop_3_uopc <= io_enq_uops_0_uopc;\n rob_uop_3_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_3_is_br <= io_enq_uops_0_is_br;\n rob_uop_3_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_3_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_3_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_3_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_3_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_3_pdst <= io_enq_uops_0_pdst;\n rob_uop_3_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_3_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_3_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_3_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_3_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_3_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_3_ldst <= io_enq_uops_0_ldst;\n rob_uop_3_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_3_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_3_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_548) | ~rob_val_3) begin\n if (_GEN_38)\n rob_uop_3_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_3_br_mask <= rob_uop_3_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h3)\n rob_uop_3_debug_fsrc <= 2'h3;\n else if (_GEN_38)\n rob_uop_3_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_39) begin\n rob_uop_4_uopc <= io_enq_uops_0_uopc;\n rob_uop_4_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_4_is_br <= io_enq_uops_0_is_br;\n rob_uop_4_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_4_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_4_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_4_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_4_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_4_pdst <= io_enq_uops_0_pdst;\n rob_uop_4_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_4_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_4_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_4_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_4_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_4_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_4_ldst <= io_enq_uops_0_ldst;\n rob_uop_4_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_4_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_4_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_549) | ~rob_val_4) begin\n if (_GEN_39)\n rob_uop_4_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_4_br_mask <= rob_uop_4_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h4)\n rob_uop_4_debug_fsrc <= 2'h3;\n else if (_GEN_39)\n rob_uop_4_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_40) begin\n rob_uop_5_uopc <= io_enq_uops_0_uopc;\n rob_uop_5_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_5_is_br <= io_enq_uops_0_is_br;\n rob_uop_5_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_5_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_5_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_5_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_5_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_5_pdst <= io_enq_uops_0_pdst;\n rob_uop_5_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_5_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_5_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_5_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_5_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_5_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_5_ldst <= io_enq_uops_0_ldst;\n rob_uop_5_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_5_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_5_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_550) | ~rob_val_5) begin\n if (_GEN_40)\n rob_uop_5_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_5_br_mask <= rob_uop_5_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h5)\n rob_uop_5_debug_fsrc <= 2'h3;\n else if (_GEN_40)\n rob_uop_5_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_41) begin\n rob_uop_6_uopc <= io_enq_uops_0_uopc;\n rob_uop_6_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_6_is_br <= io_enq_uops_0_is_br;\n rob_uop_6_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_6_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_6_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_6_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_6_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_6_pdst <= io_enq_uops_0_pdst;\n rob_uop_6_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_6_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_6_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_6_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_6_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_6_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_6_ldst <= io_enq_uops_0_ldst;\n rob_uop_6_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_6_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_6_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_551) | ~rob_val_6) begin\n if (_GEN_41)\n rob_uop_6_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_6_br_mask <= rob_uop_6_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h6)\n rob_uop_6_debug_fsrc <= 2'h3;\n else if (_GEN_41)\n rob_uop_6_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_42) begin\n rob_uop_7_uopc <= io_enq_uops_0_uopc;\n rob_uop_7_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_7_is_br <= io_enq_uops_0_is_br;\n rob_uop_7_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_7_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_7_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_7_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_7_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_7_pdst <= io_enq_uops_0_pdst;\n rob_uop_7_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_7_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_7_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_7_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_7_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_7_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_7_ldst <= io_enq_uops_0_ldst;\n rob_uop_7_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_7_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_7_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_552) | ~rob_val_7) begin\n if (_GEN_42)\n rob_uop_7_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_7_br_mask <= rob_uop_7_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h7)\n rob_uop_7_debug_fsrc <= 2'h3;\n else if (_GEN_42)\n rob_uop_7_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_43) begin\n rob_uop_8_uopc <= io_enq_uops_0_uopc;\n rob_uop_8_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_8_is_br <= io_enq_uops_0_is_br;\n rob_uop_8_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_8_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_8_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_8_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_8_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_8_pdst <= io_enq_uops_0_pdst;\n rob_uop_8_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_8_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_8_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_8_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_8_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_8_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_8_ldst <= io_enq_uops_0_ldst;\n rob_uop_8_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_8_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_8_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_553) | ~rob_val_8) begin\n if (_GEN_43)\n rob_uop_8_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_8_br_mask <= rob_uop_8_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h8)\n rob_uop_8_debug_fsrc <= 2'h3;\n else if (_GEN_43)\n rob_uop_8_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_44) begin\n rob_uop_9_uopc <= io_enq_uops_0_uopc;\n rob_uop_9_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_9_is_br <= io_enq_uops_0_is_br;\n rob_uop_9_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_9_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_9_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_9_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_9_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_9_pdst <= io_enq_uops_0_pdst;\n rob_uop_9_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_9_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_9_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_9_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_9_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_9_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_9_ldst <= io_enq_uops_0_ldst;\n rob_uop_9_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_9_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_9_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_554) | ~rob_val_9) begin\n if (_GEN_44)\n rob_uop_9_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_9_br_mask <= rob_uop_9_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h9)\n rob_uop_9_debug_fsrc <= 2'h3;\n else if (_GEN_44)\n rob_uop_9_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_45) begin\n rob_uop_10_uopc <= io_enq_uops_0_uopc;\n rob_uop_10_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_10_is_br <= io_enq_uops_0_is_br;\n rob_uop_10_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_10_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_10_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_10_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_10_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_10_pdst <= io_enq_uops_0_pdst;\n rob_uop_10_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_10_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_10_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_10_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_10_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_10_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_10_ldst <= io_enq_uops_0_ldst;\n rob_uop_10_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_10_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_10_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_555) | ~rob_val_10) begin\n if (_GEN_45)\n rob_uop_10_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_10_br_mask <= rob_uop_10_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hA)\n rob_uop_10_debug_fsrc <= 2'h3;\n else if (_GEN_45)\n rob_uop_10_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_46) begin\n rob_uop_11_uopc <= io_enq_uops_0_uopc;\n rob_uop_11_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_11_is_br <= io_enq_uops_0_is_br;\n rob_uop_11_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_11_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_11_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_11_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_11_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_11_pdst <= io_enq_uops_0_pdst;\n rob_uop_11_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_11_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_11_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_11_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_11_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_11_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_11_ldst <= io_enq_uops_0_ldst;\n rob_uop_11_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_11_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_11_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_556) | ~rob_val_11) begin\n if (_GEN_46)\n rob_uop_11_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_11_br_mask <= rob_uop_11_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hB)\n rob_uop_11_debug_fsrc <= 2'h3;\n else if (_GEN_46)\n rob_uop_11_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_47) begin\n rob_uop_12_uopc <= io_enq_uops_0_uopc;\n rob_uop_12_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_12_is_br <= io_enq_uops_0_is_br;\n rob_uop_12_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_12_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_12_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_12_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_12_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_12_pdst <= io_enq_uops_0_pdst;\n rob_uop_12_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_12_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_12_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_12_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_12_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_12_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_12_ldst <= io_enq_uops_0_ldst;\n rob_uop_12_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_12_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_12_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_557) | ~rob_val_12) begin\n if (_GEN_47)\n rob_uop_12_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_12_br_mask <= rob_uop_12_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hC)\n rob_uop_12_debug_fsrc <= 2'h3;\n else if (_GEN_47)\n rob_uop_12_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_48) begin\n rob_uop_13_uopc <= io_enq_uops_0_uopc;\n rob_uop_13_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_13_is_br <= io_enq_uops_0_is_br;\n rob_uop_13_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_13_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_13_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_13_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_13_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_13_pdst <= io_enq_uops_0_pdst;\n rob_uop_13_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_13_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_13_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_13_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_13_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_13_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_13_ldst <= io_enq_uops_0_ldst;\n rob_uop_13_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_13_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_13_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_558) | ~rob_val_13) begin\n if (_GEN_48)\n rob_uop_13_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_13_br_mask <= rob_uop_13_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hD)\n rob_uop_13_debug_fsrc <= 2'h3;\n else if (_GEN_48)\n rob_uop_13_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_49) begin\n rob_uop_14_uopc <= io_enq_uops_0_uopc;\n rob_uop_14_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_14_is_br <= io_enq_uops_0_is_br;\n rob_uop_14_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_14_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_14_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_14_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_14_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_14_pdst <= io_enq_uops_0_pdst;\n rob_uop_14_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_14_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_14_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_14_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_14_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_14_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_14_ldst <= io_enq_uops_0_ldst;\n rob_uop_14_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_14_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_14_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_559) | ~rob_val_14) begin\n if (_GEN_49)\n rob_uop_14_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_14_br_mask <= rob_uop_14_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hE)\n rob_uop_14_debug_fsrc <= 2'h3;\n else if (_GEN_49)\n rob_uop_14_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_50) begin\n rob_uop_15_uopc <= io_enq_uops_0_uopc;\n rob_uop_15_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_15_is_br <= io_enq_uops_0_is_br;\n rob_uop_15_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_15_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_15_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_15_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_15_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_15_pdst <= io_enq_uops_0_pdst;\n rob_uop_15_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_15_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_15_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_15_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_15_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_15_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_15_ldst <= io_enq_uops_0_ldst;\n rob_uop_15_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_15_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_15_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_560) | ~rob_val_15) begin\n if (_GEN_50)\n rob_uop_15_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_15_br_mask <= rob_uop_15_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'hF)\n rob_uop_15_debug_fsrc <= 2'h3;\n else if (_GEN_50)\n rob_uop_15_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_51) begin\n rob_uop_16_uopc <= io_enq_uops_0_uopc;\n rob_uop_16_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_16_is_br <= io_enq_uops_0_is_br;\n rob_uop_16_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_16_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_16_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_16_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_16_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_16_pdst <= io_enq_uops_0_pdst;\n rob_uop_16_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_16_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_16_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_16_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_16_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_16_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_16_ldst <= io_enq_uops_0_ldst;\n rob_uop_16_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_16_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_16_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_561) | ~rob_val_16) begin\n if (_GEN_51)\n rob_uop_16_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_16_br_mask <= rob_uop_16_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h10)\n rob_uop_16_debug_fsrc <= 2'h3;\n else if (_GEN_51)\n rob_uop_16_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_52) begin\n rob_uop_17_uopc <= io_enq_uops_0_uopc;\n rob_uop_17_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_17_is_br <= io_enq_uops_0_is_br;\n rob_uop_17_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_17_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_17_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_17_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_17_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_17_pdst <= io_enq_uops_0_pdst;\n rob_uop_17_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_17_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_17_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_17_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_17_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_17_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_17_ldst <= io_enq_uops_0_ldst;\n rob_uop_17_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_17_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_17_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_562) | ~rob_val_17) begin\n if (_GEN_52)\n rob_uop_17_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_17_br_mask <= rob_uop_17_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h11)\n rob_uop_17_debug_fsrc <= 2'h3;\n else if (_GEN_52)\n rob_uop_17_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_53) begin\n rob_uop_18_uopc <= io_enq_uops_0_uopc;\n rob_uop_18_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_18_is_br <= io_enq_uops_0_is_br;\n rob_uop_18_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_18_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_18_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_18_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_18_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_18_pdst <= io_enq_uops_0_pdst;\n rob_uop_18_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_18_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_18_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_18_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_18_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_18_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_18_ldst <= io_enq_uops_0_ldst;\n rob_uop_18_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_18_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_18_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_563) | ~rob_val_18) begin\n if (_GEN_53)\n rob_uop_18_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_18_br_mask <= rob_uop_18_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h12)\n rob_uop_18_debug_fsrc <= 2'h3;\n else if (_GEN_53)\n rob_uop_18_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_54) begin\n rob_uop_19_uopc <= io_enq_uops_0_uopc;\n rob_uop_19_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_19_is_br <= io_enq_uops_0_is_br;\n rob_uop_19_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_19_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_19_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_19_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_19_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_19_pdst <= io_enq_uops_0_pdst;\n rob_uop_19_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_19_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_19_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_19_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_19_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_19_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_19_ldst <= io_enq_uops_0_ldst;\n rob_uop_19_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_19_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_19_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_564) | ~rob_val_19) begin\n if (_GEN_54)\n rob_uop_19_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_19_br_mask <= rob_uop_19_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h13)\n rob_uop_19_debug_fsrc <= 2'h3;\n else if (_GEN_54)\n rob_uop_19_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_55) begin\n rob_uop_20_uopc <= io_enq_uops_0_uopc;\n rob_uop_20_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_20_is_br <= io_enq_uops_0_is_br;\n rob_uop_20_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_20_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_20_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_20_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_20_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_20_pdst <= io_enq_uops_0_pdst;\n rob_uop_20_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_20_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_20_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_20_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_20_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_20_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_20_ldst <= io_enq_uops_0_ldst;\n rob_uop_20_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_20_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_20_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_565) | ~rob_val_20) begin\n if (_GEN_55)\n rob_uop_20_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_20_br_mask <= rob_uop_20_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h14)\n rob_uop_20_debug_fsrc <= 2'h3;\n else if (_GEN_55)\n rob_uop_20_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_56) begin\n rob_uop_21_uopc <= io_enq_uops_0_uopc;\n rob_uop_21_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_21_is_br <= io_enq_uops_0_is_br;\n rob_uop_21_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_21_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_21_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_21_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_21_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_21_pdst <= io_enq_uops_0_pdst;\n rob_uop_21_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_21_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_21_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_21_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_21_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_21_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_21_ldst <= io_enq_uops_0_ldst;\n rob_uop_21_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_21_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_21_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_566) | ~rob_val_21) begin\n if (_GEN_56)\n rob_uop_21_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_21_br_mask <= rob_uop_21_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h15)\n rob_uop_21_debug_fsrc <= 2'h3;\n else if (_GEN_56)\n rob_uop_21_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_57) begin\n rob_uop_22_uopc <= io_enq_uops_0_uopc;\n rob_uop_22_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_22_is_br <= io_enq_uops_0_is_br;\n rob_uop_22_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_22_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_22_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_22_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_22_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_22_pdst <= io_enq_uops_0_pdst;\n rob_uop_22_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_22_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_22_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_22_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_22_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_22_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_22_ldst <= io_enq_uops_0_ldst;\n rob_uop_22_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_22_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_22_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_567) | ~rob_val_22) begin\n if (_GEN_57)\n rob_uop_22_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_22_br_mask <= rob_uop_22_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h16)\n rob_uop_22_debug_fsrc <= 2'h3;\n else if (_GEN_57)\n rob_uop_22_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_58) begin\n rob_uop_23_uopc <= io_enq_uops_0_uopc;\n rob_uop_23_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_23_is_br <= io_enq_uops_0_is_br;\n rob_uop_23_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_23_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_23_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_23_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_23_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_23_pdst <= io_enq_uops_0_pdst;\n rob_uop_23_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_23_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_23_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_23_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_23_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_23_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_23_ldst <= io_enq_uops_0_ldst;\n rob_uop_23_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_23_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_23_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_568) | ~rob_val_23) begin\n if (_GEN_58)\n rob_uop_23_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_23_br_mask <= rob_uop_23_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h17)\n rob_uop_23_debug_fsrc <= 2'h3;\n else if (_GEN_58)\n rob_uop_23_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_59) begin\n rob_uop_24_uopc <= io_enq_uops_0_uopc;\n rob_uop_24_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_24_is_br <= io_enq_uops_0_is_br;\n rob_uop_24_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_24_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_24_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_24_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_24_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_24_pdst <= io_enq_uops_0_pdst;\n rob_uop_24_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_24_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_24_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_24_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_24_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_24_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_24_ldst <= io_enq_uops_0_ldst;\n rob_uop_24_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_24_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_24_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_569) | ~rob_val_24) begin\n if (_GEN_59)\n rob_uop_24_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_24_br_mask <= rob_uop_24_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h18)\n rob_uop_24_debug_fsrc <= 2'h3;\n else if (_GEN_59)\n rob_uop_24_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_60) begin\n rob_uop_25_uopc <= io_enq_uops_0_uopc;\n rob_uop_25_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_25_is_br <= io_enq_uops_0_is_br;\n rob_uop_25_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_25_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_25_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_25_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_25_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_25_pdst <= io_enq_uops_0_pdst;\n rob_uop_25_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_25_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_25_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_25_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_25_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_25_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_25_ldst <= io_enq_uops_0_ldst;\n rob_uop_25_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_25_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_25_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_570) | ~rob_val_25) begin\n if (_GEN_60)\n rob_uop_25_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_25_br_mask <= rob_uop_25_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h19)\n rob_uop_25_debug_fsrc <= 2'h3;\n else if (_GEN_60)\n rob_uop_25_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_61) begin\n rob_uop_26_uopc <= io_enq_uops_0_uopc;\n rob_uop_26_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_26_is_br <= io_enq_uops_0_is_br;\n rob_uop_26_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_26_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_26_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_26_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_26_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_26_pdst <= io_enq_uops_0_pdst;\n rob_uop_26_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_26_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_26_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_26_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_26_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_26_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_26_ldst <= io_enq_uops_0_ldst;\n rob_uop_26_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_26_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_26_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_571) | ~rob_val_26) begin\n if (_GEN_61)\n rob_uop_26_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_26_br_mask <= rob_uop_26_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1A)\n rob_uop_26_debug_fsrc <= 2'h3;\n else if (_GEN_61)\n rob_uop_26_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_62) begin\n rob_uop_27_uopc <= io_enq_uops_0_uopc;\n rob_uop_27_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_27_is_br <= io_enq_uops_0_is_br;\n rob_uop_27_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_27_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_27_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_27_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_27_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_27_pdst <= io_enq_uops_0_pdst;\n rob_uop_27_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_27_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_27_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_27_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_27_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_27_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_27_ldst <= io_enq_uops_0_ldst;\n rob_uop_27_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_27_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_27_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_572) | ~rob_val_27) begin\n if (_GEN_62)\n rob_uop_27_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_27_br_mask <= rob_uop_27_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1B)\n rob_uop_27_debug_fsrc <= 2'h3;\n else if (_GEN_62)\n rob_uop_27_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_63) begin\n rob_uop_28_uopc <= io_enq_uops_0_uopc;\n rob_uop_28_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_28_is_br <= io_enq_uops_0_is_br;\n rob_uop_28_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_28_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_28_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_28_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_28_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_28_pdst <= io_enq_uops_0_pdst;\n rob_uop_28_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_28_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_28_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_28_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_28_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_28_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_28_ldst <= io_enq_uops_0_ldst;\n rob_uop_28_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_28_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_28_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_573) | ~rob_val_28) begin\n if (_GEN_63)\n rob_uop_28_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_28_br_mask <= rob_uop_28_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1C)\n rob_uop_28_debug_fsrc <= 2'h3;\n else if (_GEN_63)\n rob_uop_28_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_64) begin\n rob_uop_29_uopc <= io_enq_uops_0_uopc;\n rob_uop_29_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_29_is_br <= io_enq_uops_0_is_br;\n rob_uop_29_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_29_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_29_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_29_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_29_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_29_pdst <= io_enq_uops_0_pdst;\n rob_uop_29_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_29_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_29_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_29_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_29_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_29_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_29_ldst <= io_enq_uops_0_ldst;\n rob_uop_29_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_29_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_29_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_574) | ~rob_val_29) begin\n if (_GEN_64)\n rob_uop_29_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_29_br_mask <= rob_uop_29_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1D)\n rob_uop_29_debug_fsrc <= 2'h3;\n else if (_GEN_64)\n rob_uop_29_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_65) begin\n rob_uop_30_uopc <= io_enq_uops_0_uopc;\n rob_uop_30_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_30_is_br <= io_enq_uops_0_is_br;\n rob_uop_30_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_30_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_30_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_30_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_30_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_30_pdst <= io_enq_uops_0_pdst;\n rob_uop_30_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_30_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_30_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_30_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_30_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_30_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_30_ldst <= io_enq_uops_0_ldst;\n rob_uop_30_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_30_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_30_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_575) | ~rob_val_30) begin\n if (_GEN_65)\n rob_uop_30_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_30_br_mask <= rob_uop_30_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == 5'h1E)\n rob_uop_30_debug_fsrc <= 2'h3;\n else if (_GEN_65)\n rob_uop_30_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n if (_GEN_66) begin\n rob_uop_31_uopc <= io_enq_uops_0_uopc;\n rob_uop_31_is_rvc <= io_enq_uops_0_is_rvc;\n rob_uop_31_is_br <= io_enq_uops_0_is_br;\n rob_uop_31_is_jalr <= io_enq_uops_0_is_jalr;\n rob_uop_31_is_jal <= io_enq_uops_0_is_jal;\n rob_uop_31_ftq_idx <= io_enq_uops_0_ftq_idx;\n rob_uop_31_edge_inst <= io_enq_uops_0_edge_inst;\n rob_uop_31_pc_lob <= io_enq_uops_0_pc_lob;\n rob_uop_31_pdst <= io_enq_uops_0_pdst;\n rob_uop_31_stale_pdst <= io_enq_uops_0_stale_pdst;\n rob_uop_31_is_fencei <= io_enq_uops_0_is_fencei;\n rob_uop_31_uses_ldq <= io_enq_uops_0_uses_ldq;\n rob_uop_31_uses_stq <= io_enq_uops_0_uses_stq;\n rob_uop_31_is_sys_pc2epc <= io_enq_uops_0_is_sys_pc2epc;\n rob_uop_31_flush_on_commit <= io_enq_uops_0_flush_on_commit;\n rob_uop_31_ldst <= io_enq_uops_0_ldst;\n rob_uop_31_ldst_val <= io_enq_uops_0_ldst_val;\n rob_uop_31_dst_rtype <= io_enq_uops_0_dst_rtype;\n rob_uop_31_fp_val <= io_enq_uops_0_fp_val;\n end\n if ((|_GEN_576) | ~rob_val_31) begin\n if (_GEN_66)\n rob_uop_31_br_mask <= io_enq_uops_0_br_mask;\n end\n else\n rob_uop_31_br_mask <= rob_uop_31_br_mask & ~io_brupdate_b1_resolve_mask;\n if (io_brupdate_b2_mispredict & (&io_brupdate_b2_uop_rob_idx))\n rob_uop_31_debug_fsrc <= 2'h3;\n else if (_GEN_66)\n rob_uop_31_debug_fsrc <= io_enq_uops_0_debug_fsrc;\n rob_exception_0 <= ~_GEN_513 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h0 | (_GEN_35 ? io_enq_uops_0_exception : rob_exception_0));\n rob_exception_1 <= ~_GEN_514 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1 | (_GEN_36 ? io_enq_uops_0_exception : rob_exception_1));\n rob_exception_2 <= ~_GEN_515 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h2 | (_GEN_37 ? io_enq_uops_0_exception : rob_exception_2));\n rob_exception_3 <= ~_GEN_516 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h3 | (_GEN_38 ? io_enq_uops_0_exception : rob_exception_3));\n rob_exception_4 <= ~_GEN_517 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h4 | (_GEN_39 ? io_enq_uops_0_exception : rob_exception_4));\n rob_exception_5 <= ~_GEN_518 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h5 | (_GEN_40 ? io_enq_uops_0_exception : rob_exception_5));\n rob_exception_6 <= ~_GEN_519 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h6 | (_GEN_41 ? io_enq_uops_0_exception : rob_exception_6));\n rob_exception_7 <= ~_GEN_520 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h7 | (_GEN_42 ? io_enq_uops_0_exception : rob_exception_7));\n rob_exception_8 <= ~_GEN_521 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h8 | (_GEN_43 ? io_enq_uops_0_exception : rob_exception_8));\n rob_exception_9 <= ~_GEN_522 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h9 | (_GEN_44 ? io_enq_uops_0_exception : rob_exception_9));\n rob_exception_10 <= ~_GEN_523 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hA | (_GEN_45 ? io_enq_uops_0_exception : rob_exception_10));\n rob_exception_11 <= ~_GEN_524 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hB | (_GEN_46 ? io_enq_uops_0_exception : rob_exception_11));\n rob_exception_12 <= ~_GEN_525 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hC | (_GEN_47 ? io_enq_uops_0_exception : rob_exception_12));\n rob_exception_13 <= ~_GEN_526 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hD | (_GEN_48 ? io_enq_uops_0_exception : rob_exception_13));\n rob_exception_14 <= ~_GEN_527 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hE | (_GEN_49 ? io_enq_uops_0_exception : rob_exception_14));\n rob_exception_15 <= ~_GEN_528 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'hF | (_GEN_50 ? io_enq_uops_0_exception : rob_exception_15));\n rob_exception_16 <= ~_GEN_529 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h10 | (_GEN_51 ? io_enq_uops_0_exception : rob_exception_16));\n rob_exception_17 <= ~_GEN_530 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h11 | (_GEN_52 ? io_enq_uops_0_exception : rob_exception_17));\n rob_exception_18 <= ~_GEN_531 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h12 | (_GEN_53 ? io_enq_uops_0_exception : rob_exception_18));\n rob_exception_19 <= ~_GEN_532 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h13 | (_GEN_54 ? io_enq_uops_0_exception : rob_exception_19));\n rob_exception_20 <= ~_GEN_533 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h14 | (_GEN_55 ? io_enq_uops_0_exception : rob_exception_20));\n rob_exception_21 <= ~_GEN_534 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h15 | (_GEN_56 ? io_enq_uops_0_exception : rob_exception_21));\n rob_exception_22 <= ~_GEN_535 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h16 | (_GEN_57 ? io_enq_uops_0_exception : rob_exception_22));\n rob_exception_23 <= ~_GEN_536 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h17 | (_GEN_58 ? io_enq_uops_0_exception : rob_exception_23));\n rob_exception_24 <= ~_GEN_537 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h18 | (_GEN_59 ? io_enq_uops_0_exception : rob_exception_24));\n rob_exception_25 <= ~_GEN_538 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h19 | (_GEN_60 ? io_enq_uops_0_exception : rob_exception_25));\n rob_exception_26 <= ~_GEN_539 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1A | (_GEN_61 ? io_enq_uops_0_exception : rob_exception_26));\n rob_exception_27 <= ~_GEN_540 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1B | (_GEN_62 ? io_enq_uops_0_exception : rob_exception_27));\n rob_exception_28 <= ~_GEN_541 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1C | (_GEN_63 ? io_enq_uops_0_exception : rob_exception_28));\n rob_exception_29 <= ~_GEN_542 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1D | (_GEN_64 ? io_enq_uops_0_exception : rob_exception_29));\n rob_exception_30 <= ~_GEN_543 & (io_lxcpt_valid & io_lxcpt_bits_uop_rob_idx == 5'h1E | (_GEN_65 ? io_enq_uops_0_exception : rob_exception_30));\n rob_exception_31 <= ~_GEN_544 & (io_lxcpt_valid & (&io_lxcpt_bits_uop_rob_idx) | (_GEN_66 ? io_enq_uops_0_exception : rob_exception_31));\n rob_predicated_0 <= ~(io_wb_resps_3_valid & _GEN_322) & (_GEN_290 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_163) & (_GEN_131 ? io_wb_resps_0_bits_predicated : ~_GEN_35 & rob_predicated_0));\n rob_predicated_1 <= ~(io_wb_resps_3_valid & _GEN_325) & (_GEN_291 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_166) & (_GEN_132 ? io_wb_resps_0_bits_predicated : ~_GEN_36 & rob_predicated_1));\n rob_predicated_2 <= ~(io_wb_resps_3_valid & _GEN_328) & (_GEN_292 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_169) & (_GEN_133 ? io_wb_resps_0_bits_predicated : ~_GEN_37 & rob_predicated_2));\n rob_predicated_3 <= ~(io_wb_resps_3_valid & _GEN_331) & (_GEN_293 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_172) & (_GEN_134 ? io_wb_resps_0_bits_predicated : ~_GEN_38 & rob_predicated_3));\n rob_predicated_4 <= ~(io_wb_resps_3_valid & _GEN_334) & (_GEN_294 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_175) & (_GEN_135 ? io_wb_resps_0_bits_predicated : ~_GEN_39 & rob_predicated_4));\n rob_predicated_5 <= ~(io_wb_resps_3_valid & _GEN_337) & (_GEN_295 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_178) & (_GEN_136 ? io_wb_resps_0_bits_predicated : ~_GEN_40 & rob_predicated_5));\n rob_predicated_6 <= ~(io_wb_resps_3_valid & _GEN_340) & (_GEN_296 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_181) & (_GEN_137 ? io_wb_resps_0_bits_predicated : ~_GEN_41 & rob_predicated_6));\n rob_predicated_7 <= ~(io_wb_resps_3_valid & _GEN_343) & (_GEN_297 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_184) & (_GEN_138 ? io_wb_resps_0_bits_predicated : ~_GEN_42 & rob_predicated_7));\n rob_predicated_8 <= ~(io_wb_resps_3_valid & _GEN_346) & (_GEN_298 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_187) & (_GEN_139 ? io_wb_resps_0_bits_predicated : ~_GEN_43 & rob_predicated_8));\n rob_predicated_9 <= ~(io_wb_resps_3_valid & _GEN_349) & (_GEN_299 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_190) & (_GEN_140 ? io_wb_resps_0_bits_predicated : ~_GEN_44 & rob_predicated_9));\n rob_predicated_10 <= ~(io_wb_resps_3_valid & _GEN_352) & (_GEN_300 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_193) & (_GEN_141 ? io_wb_resps_0_bits_predicated : ~_GEN_45 & rob_predicated_10));\n rob_predicated_11 <= ~(io_wb_resps_3_valid & _GEN_355) & (_GEN_301 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_196) & (_GEN_142 ? io_wb_resps_0_bits_predicated : ~_GEN_46 & rob_predicated_11));\n rob_predicated_12 <= ~(io_wb_resps_3_valid & _GEN_358) & (_GEN_302 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_199) & (_GEN_143 ? io_wb_resps_0_bits_predicated : ~_GEN_47 & rob_predicated_12));\n rob_predicated_13 <= ~(io_wb_resps_3_valid & _GEN_361) & (_GEN_303 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_202) & (_GEN_144 ? io_wb_resps_0_bits_predicated : ~_GEN_48 & rob_predicated_13));\n rob_predicated_14 <= ~(io_wb_resps_3_valid & _GEN_364) & (_GEN_304 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_205) & (_GEN_145 ? io_wb_resps_0_bits_predicated : ~_GEN_49 & rob_predicated_14));\n rob_predicated_15 <= ~(io_wb_resps_3_valid & _GEN_367) & (_GEN_305 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_208) & (_GEN_146 ? io_wb_resps_0_bits_predicated : ~_GEN_50 & rob_predicated_15));\n rob_predicated_16 <= ~(io_wb_resps_3_valid & _GEN_370) & (_GEN_306 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_211) & (_GEN_147 ? io_wb_resps_0_bits_predicated : ~_GEN_51 & rob_predicated_16));\n rob_predicated_17 <= ~(io_wb_resps_3_valid & _GEN_373) & (_GEN_307 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_214) & (_GEN_148 ? io_wb_resps_0_bits_predicated : ~_GEN_52 & rob_predicated_17));\n rob_predicated_18 <= ~(io_wb_resps_3_valid & _GEN_376) & (_GEN_308 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_217) & (_GEN_149 ? io_wb_resps_0_bits_predicated : ~_GEN_53 & rob_predicated_18));\n rob_predicated_19 <= ~(io_wb_resps_3_valid & _GEN_379) & (_GEN_309 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_220) & (_GEN_150 ? io_wb_resps_0_bits_predicated : ~_GEN_54 & rob_predicated_19));\n rob_predicated_20 <= ~(io_wb_resps_3_valid & _GEN_382) & (_GEN_310 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_223) & (_GEN_151 ? io_wb_resps_0_bits_predicated : ~_GEN_55 & rob_predicated_20));\n rob_predicated_21 <= ~(io_wb_resps_3_valid & _GEN_385) & (_GEN_311 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_226) & (_GEN_152 ? io_wb_resps_0_bits_predicated : ~_GEN_56 & rob_predicated_21));\n rob_predicated_22 <= ~(io_wb_resps_3_valid & _GEN_388) & (_GEN_312 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_229) & (_GEN_153 ? io_wb_resps_0_bits_predicated : ~_GEN_57 & rob_predicated_22));\n rob_predicated_23 <= ~(io_wb_resps_3_valid & _GEN_391) & (_GEN_313 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_232) & (_GEN_154 ? io_wb_resps_0_bits_predicated : ~_GEN_58 & rob_predicated_23));\n rob_predicated_24 <= ~(io_wb_resps_3_valid & _GEN_394) & (_GEN_314 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_235) & (_GEN_155 ? io_wb_resps_0_bits_predicated : ~_GEN_59 & rob_predicated_24));\n rob_predicated_25 <= ~(io_wb_resps_3_valid & _GEN_397) & (_GEN_315 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_238) & (_GEN_156 ? io_wb_resps_0_bits_predicated : ~_GEN_60 & rob_predicated_25));\n rob_predicated_26 <= ~(io_wb_resps_3_valid & _GEN_400) & (_GEN_316 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_241) & (_GEN_157 ? io_wb_resps_0_bits_predicated : ~_GEN_61 & rob_predicated_26));\n rob_predicated_27 <= ~(io_wb_resps_3_valid & _GEN_403) & (_GEN_317 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_244) & (_GEN_158 ? io_wb_resps_0_bits_predicated : ~_GEN_62 & rob_predicated_27));\n rob_predicated_28 <= ~(io_wb_resps_3_valid & _GEN_406) & (_GEN_318 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_247) & (_GEN_159 ? io_wb_resps_0_bits_predicated : ~_GEN_63 & rob_predicated_28));\n rob_predicated_29 <= ~(io_wb_resps_3_valid & _GEN_409) & (_GEN_319 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_250) & (_GEN_160 ? io_wb_resps_0_bits_predicated : ~_GEN_64 & rob_predicated_29));\n rob_predicated_30 <= ~(io_wb_resps_3_valid & _GEN_412) & (_GEN_320 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & _GEN_253) & (_GEN_161 ? io_wb_resps_0_bits_predicated : ~_GEN_65 & rob_predicated_30));\n rob_predicated_31 <= ~(io_wb_resps_3_valid & (&io_wb_resps_3_bits_uop_rob_idx)) & (_GEN_321 ? io_wb_resps_2_bits_predicated : ~(io_wb_resps_1_valid & (&io_wb_resps_1_bits_uop_rob_idx)) & (_GEN_162 ? io_wb_resps_0_bits_predicated : ~_GEN_66 & rob_predicated_31));\n block_commit_REG <= exception_thrown;\n block_commit_REG_1 <= exception_thrown;\n block_commit_REG_2 <= block_commit_REG_1;\n REG <= exception_thrown;\n REG_1 <= REG;\n REG_2 <= exception_thrown;\n io_com_load_is_at_rob_head_REG <= _GEN_16[rob_head] & ~will_commit_0;\n end\n rob_debug_inst_mem_0 rob_debug_inst_mem_0 (\n .R0_addr (rob_head),\n .R0_en (will_commit_0),\n .R0_clk (clock),\n .W0_addr (rob_tail),\n .W0_en (io_enq_valids_0),\n .W0_clk (clock),\n .W0_data (io_enq_uops_0_debug_inst)\n );\n assign io_rob_tail_idx = rob_tail;\n assign io_rob_head_idx = rob_head;\n assign io_commit_valids_0 = will_commit_0;\n assign io_commit_arch_valids_0 = will_commit_0 & ~_GEN_4[com_idx];\n assign io_commit_uops_0_is_br = _GEN_7[com_idx];\n assign io_commit_uops_0_is_jalr = _GEN_8[com_idx];\n assign io_commit_uops_0_is_jal = _GEN_9[com_idx];\n assign io_commit_uops_0_ftq_idx = _GEN_10[com_idx];\n assign io_commit_uops_0_pdst = _GEN_13[com_idx];\n assign io_commit_uops_0_stale_pdst = _GEN_14[com_idx];\n assign io_commit_uops_0_is_fencei = _GEN_15[com_idx];\n assign io_commit_uops_0_uses_ldq = _GEN_16[com_idx];\n assign io_commit_uops_0_uses_stq = _GEN_17[com_idx];\n assign io_commit_uops_0_ldst = _GEN_20[com_idx];\n assign io_commit_uops_0_ldst_val = _GEN_21[com_idx];\n assign io_commit_uops_0_dst_rtype = _GEN_22[com_idx];\n assign io_commit_uops_0_debug_fsrc = io_brupdate_b2_mispredict & io_brupdate_b2_uop_rob_idx == com_idx ? 2'h3 : _GEN_24[com_idx];\n assign io_commit_fflags_valid = fflags_val_0;\n assign io_commit_fflags_bits = fflags_val_0 ? rob_head_fflags_0 : 5'h0;\n assign io_commit_rbk_valids_0 = io_commit_rbk_valids_0_0;\n assign io_commit_rollback = io_commit_rollback_0;\n assign io_com_load_is_at_rob_head = io_com_load_is_at_rob_head_REG;\n assign io_com_xcpt_valid = exception_thrown & ~is_mini_exception;\n assign io_com_xcpt_bits_ftq_idx = _GEN_10[com_idx];\n assign io_com_xcpt_bits_edge_inst = _GEN_11[com_idx];\n assign io_com_xcpt_bits_pc_lob = _GEN_12[com_idx];\n assign io_com_xcpt_bits_cause = r_xcpt_uop_exc_cause;\n assign io_com_xcpt_bits_badvaddr = {{24{r_xcpt_badvaddr[39]}}, r_xcpt_badvaddr};\n assign io_flush_valid = flush_val;\n assign io_flush_bits_ftq_idx = _GEN_10[com_idx];\n assign io_flush_bits_edge_inst = _GEN_11[com_idx];\n assign io_flush_bits_is_rvc = _GEN_6[com_idx];\n assign io_flush_bits_pc_lob = _GEN_12[com_idx];\n assign io_flush_bits_flush_typ = flush_val ? (flush_commit_mask_0 & _GEN_5[com_idx] == 7'h6A ? 3'h3 : exception_thrown & ~is_mini_exception ? 3'h1 : exception_thrown | rob_head_vals_0 & _GEN_18[com_idx] ? 3'h2 : 3'h4) : 3'h0;\n assign io_empty = empty;\n assign io_ready = _io_ready_T & ~full & ~r_xcpt_val;\n assign io_flush_frontend = r_xcpt_val;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitToFlit_p32_f32_TestHarness_UNIQUIFIED(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_phit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_flit\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_flit = io_in_bits_phit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_postMul_e11_s53(\n input io_fromPreMul_isSigNaNAny,\n input io_fromPreMul_isNaNAOrB,\n input io_fromPreMul_isInfA,\n input io_fromPreMul_isZeroA,\n input io_fromPreMul_isInfB,\n input io_fromPreMul_isZeroB,\n input io_fromPreMul_signProd,\n input io_fromPreMul_isNaNC,\n input io_fromPreMul_isInfC,\n input io_fromPreMul_isZeroC,\n input [12:0] io_fromPreMul_sExpSum,\n input io_fromPreMul_doSubMags,\n input io_fromPreMul_CIsDominant,\n input [5:0] io_fromPreMul_CDom_CAlignDist,\n input [54:0] io_fromPreMul_highAlignedSigC,\n input io_fromPreMul_bit0AlignedSigC,\n input [106:0] io_mulAddResult,\n input [2:0] io_roundingMode,\n output io_invalidExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [12:0] io_rawOut_sExp,\n output [55:0] io_rawOut_sig\n);\n\n wire roundingMode_min = io_roundingMode == 3'h2;\n wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;\n wire [54:0] _sigSum_T_3 = io_mulAddResult[106] ? io_fromPreMul_highAlignedSigC + 55'h1 : io_fromPreMul_highAlignedSigC;\n wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[105:53]} : {1'h0, io_fromPreMul_highAlignedSigC[54:53], _sigSum_T_3[52:0], io_mulAddResult[105:54]};\n wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;\n wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2]));\n wire [108:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + {108'h0, io_fromPreMul_doSubMags};\n wire [5:0] notCDom_normDistReduced2 =\n notCDom_absSigSum[108]\n ? 6'h0\n : (|(notCDom_absSigSum[107:106]))\n ? 6'h1\n : (|(notCDom_absSigSum[105:104]))\n ? 6'h2\n : (|(notCDom_absSigSum[103:102])) ? 6'h3 : (|(notCDom_absSigSum[101:100])) ? 6'h4 : (|(notCDom_absSigSum[99:98])) ? 6'h5 : (|(notCDom_absSigSum[97:96])) ? 6'h6 : (|(notCDom_absSigSum[95:94])) ? 6'h7 : (|(notCDom_absSigSum[93:92])) ? 6'h8 : (|(notCDom_absSigSum[91:90])) ? 6'h9 : (|(notCDom_absSigSum[89:88])) ? 6'hA : (|(notCDom_absSigSum[87:86])) ? 6'hB : (|(notCDom_absSigSum[85:84])) ? 6'hC : (|(notCDom_absSigSum[83:82])) ? 6'hD : (|(notCDom_absSigSum[81:80])) ? 6'hE : (|(notCDom_absSigSum[79:78])) ? 6'hF : (|(notCDom_absSigSum[77:76])) ? 6'h10 : (|(notCDom_absSigSum[75:74])) ? 6'h11 : (|(notCDom_absSigSum[73:72])) ? 6'h12 : (|(notCDom_absSigSum[71:70])) ? 6'h13 : (|(notCDom_absSigSum[69:68])) ? 6'h14 : (|(notCDom_absSigSum[67:66])) ? 6'h15 : (|(notCDom_absSigSum[65:64])) ? 6'h16 : (|(notCDom_absSigSum[63:62])) ? 6'h17 : (|(notCDom_absSigSum[61:60])) ? 6'h18 : (|(notCDom_absSigSum[59:58])) ? 6'h19 : (|(notCDom_absSigSum[57:56])) ? 6'h1A : (|(notCDom_absSigSum[55:54])) ? 6'h1B : (|(notCDom_absSigSum[53:52])) ? 6'h1C : (|(notCDom_absSigSum[51:50])) ? 6'h1D : (|(notCDom_absSigSum[49:48])) ? 6'h1E : (|(notCDom_absSigSum[47:46])) ? 6'h1F : (|(notCDom_absSigSum[45:44])) ? 6'h20 : (|(notCDom_absSigSum[43:42])) ? 6'h21 : (|(notCDom_absSigSum[41:40])) ? 6'h22 : (|(notCDom_absSigSum[39:38])) ? 6'h23 : (|(notCDom_absSigSum[37:36])) ? 6'h24 : (|(notCDom_absSigSum[35:34])) ? 6'h25 : (|(notCDom_absSigSum[33:32])) ? 6'h26 : (|(notCDom_absSigSum[31:30])) ? 6'h27 : (|(notCDom_absSigSum[29:28])) ? 6'h28 : (|(notCDom_absSigSum[27:26])) ? 6'h29 : (|(notCDom_absSigSum[25:24])) ? 6'h2A : (|(notCDom_absSigSum[23:22])) ? 6'h2B : (|(notCDom_absSigSum[21:20])) ? 6'h2C : (|(notCDom_absSigSum[19:18])) ? 6'h2D : (|(notCDom_absSigSum[17:16])) ? 6'h2E : (|(notCDom_absSigSum[15:14])) ? 6'h2F : (|(notCDom_absSigSum[13:12])) ? 6'h30 : (|(notCDom_absSigSum[11:10])) ? 6'h31 : (|(notCDom_absSigSum[9:8])) ? 6'h32 : (|(notCDom_absSigSum[7:6])) ? 6'h33 : (|(notCDom_absSigSum[5:4])) ? 6'h34 : (|(notCDom_absSigSum[3:2])) ? 6'h35 : 6'h36;\n wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0};\n wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1]));\n wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0;\n wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;\n wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;\n wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;\n assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;\n assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;\n assign io_rawOut_isInf = notNaN_isInfOut;\n assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;\n assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);\n assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0};\n assign io_rawOut_sig =\n io_fromPreMul_CIsDominant\n ? {_CDom_mainSig_T[107:53], (|{_CDom_mainSig_T[52:50], {|(CDom_absSigSum[49:46]), |(CDom_absSigSum[45:42]), |(CDom_absSigSum[41:38]), |(CDom_absSigSum[37:34]), |(CDom_absSigSum[33:30]), |(CDom_absSigSum[29:26]), |(CDom_absSigSum[25:22]), |(CDom_absSigSum[21:18]), |(CDom_absSigSum[17:14]), |(CDom_absSigSum[13:10]), |(CDom_absSigSum[9:6]), |(CDom_absSigSum[5:2]), |(CDom_absSigSum[1:0])} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6], CDom_reduced4SigExtra_shift[7], CDom_reduced4SigExtra_shift[8], CDom_reduced4SigExtra_shift[9], CDom_reduced4SigExtra_shift[10], CDom_reduced4SigExtra_shift[11], CDom_reduced4SigExtra_shift[12], CDom_reduced4SigExtra_shift[13]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF : (|(io_mulAddResult[53:0])))}\n : {_notCDom_mainSig_T[109:55], |{_notCDom_mainSig_T[54:52], {|{|(notCDom_absSigSum[51:50]), |(notCDom_absSigSum[49:48])}, |{|(notCDom_absSigSum[47:46]), |(notCDom_absSigSum[45:44])}, |{|(notCDom_absSigSum[43:42]), |(notCDom_absSigSum[41:40])}, |{|(notCDom_absSigSum[39:38]), |(notCDom_absSigSum[37:36])}, |{|(notCDom_absSigSum[35:34]), |(notCDom_absSigSum[33:32])}, |{|(notCDom_absSigSum[31:30]), |(notCDom_absSigSum[29:28])}, |{|(notCDom_absSigSum[27:26]), |(notCDom_absSigSum[25:24])}, |{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6], notCDom_reduced4SigExtra_shift[7], notCDom_reduced4SigExtra_shift[8], notCDom_reduced4SigExtra_shift[9], notCDom_reduced4SigExtra_shift[10], notCDom_reduced4SigExtra_shift[11], notCDom_reduced4SigExtra_shift[12], notCDom_reduced4SigExtra_shift[13]}}};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module MulAddRecFNPipe_l2_e11_s53(\n input clock,\n input reset,\n input io_validin,\n input [1:0] io_op,\n input [64:0] io_a,\n input [64:0] io_b,\n input [64:0] io_c,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags,\n output io_validout\n);\n\n wire _mulAddRecFNToRaw_postMul_io_invalidExc;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA;\n wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB;\n wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;\n reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;\n reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;\n reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;\n reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;\n reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;\n reg [2:0] roundingMode_stage0_pipe_b;\n reg valid_stage0_pipe_v;\n reg roundRawFNToRecFN_io_invalidExc_pipe_b;\n reg roundRawFNToRecFN_io_in_pipe_b_isNaN;\n reg roundRawFNToRecFN_io_in_pipe_b_isInf;\n reg roundRawFNToRecFN_io_in_pipe_b_isZero;\n reg roundRawFNToRecFN_io_in_pipe_b_sign;\n reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp;\n reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig;\n reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;\n reg io_validout_pipe_v;\n always @(posedge clock) begin\n if (io_validin) begin\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= {1'h0, {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;\n roundingMode_stage0_pipe_b <= io_roundingMode;\n end\n if (valid_stage0_pipe_v) begin\n roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;\n roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;\n end\n if (reset) begin\n valid_stage0_pipe_v <= 1'h0;\n io_validout_pipe_v <= 1'h0;\n end\n else begin\n valid_stage0_pipe_v <= io_validin;\n io_validout_pipe_v <= valid_stage0_pipe_v;\n end\n end\n MulAddRecFNToRaw_preMul_e11_s53 mulAddRecFNToRaw_preMul (\n .io_op (io_op),\n .io_a (io_a),\n .io_b (io_b),\n .io_c (io_c),\n .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),\n .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),\n .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),\n .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),\n .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),\n .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),\n .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),\n .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),\n .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),\n .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),\n .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),\n .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),\n .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),\n .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),\n .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),\n .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),\n .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),\n .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),\n .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)\n );\n MulAddRecFNToRaw_postMul_e11_s53 mulAddRecFNToRaw_postMul (\n .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),\n .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),\n .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),\n .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),\n .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),\n .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),\n .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),\n .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),\n .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),\n .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),\n .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),\n .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),\n .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),\n .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),\n .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),\n .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),\n .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),\n .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),\n .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),\n .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),\n .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),\n .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),\n .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),\n .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),\n .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN (\n .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),\n .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),\n .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),\n .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),\n .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),\n .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),\n .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),\n .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\n assign io_validout = io_validout_pipe_v;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us_3(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module next_33x6(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:32];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLCToBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_bits_head\n);\n\n assign io_beat_bits_head = 1'h1;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericSerializer_TLBeatw88_f32(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [85:0] io_in_bits_payload,\n input io_in_bits_head,\n input io_in_bits_tail,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_flit\n);\n\n wire [0:0][31:0] _GEN = '{32'h0};\n reg [31:0] data_1;\n reg [31:0] data_2;\n reg [1:0] beat;\n wire _io_out_bits_flit_T = beat == 2'h0;\n wire [2:0] _GEN_0 = {io_in_valid, beat};\n wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}};\n wire _GEN_2 = io_out_ready & (|_GEN_0);\n always @(posedge clock) begin\n if (_GEN_2 & _io_out_bits_flit_T) begin\n data_1 <= io_in_bits_payload[61:30];\n data_2 <= {8'h0, io_in_bits_payload[85:62]};\n end\n if (reset)\n beat <= 2'h0;\n else if (_GEN_2)\n beat <= beat == 2'h2 ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_out_ready & _io_out_bits_flit_T;\n assign io_out_valid = |_GEN_0;\n assign io_out_bits_flit = _io_out_bits_flit_T ? {io_in_bits_payload[29:0], io_in_bits_head, io_in_bits_tail} : _GEN_1[beat];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Register File (Abstract class and Synthesizable RegFile)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.ArrayBuffer\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * IO bundle for a register read port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = Input(UInt(addrWidth.W))\n val data = Output(UInt(dataWidth.W))\n}\n\n/**\n * IO bundle for the register write port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n}\n\n/**\n * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.\n */\nobject WritePort\n{\n def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)\n (implicit p: Parameters): Valid[RegisterFileWritePort] = {\n val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))\n\n wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype\n wport.bits.addr := enq.bits.uop.pdst\n wport.bits.data := enq.bits.data\n enq.ready := true.B\n wport\n }\n}\n\n/**\n * Register file abstract class\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nabstract class RegisterFile(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new BoomBundle {\n val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))\n val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))\n })\n\n private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)\n private val type_str = if (registerWidth == fLen+1) \"Floating Point\" else \"Integer\"\n override def toString: String = BoomCoreStringPrefix(\n \"==\" + type_str + \" Regfile==\",\n \"Num RF Read Ports : \" + numReadPorts,\n \"Num RF Write Ports : \" + numWritePorts,\n \"RF Cost (R+W)*(R+2W) : \" + rf_cost,\n \"Bypassable Units : \" + bypassableArray)\n}\n\n/**\n * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nclass RegisterFileSynthesizable(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean])\n (implicit p: Parameters)\n extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)\n{\n // --------------------------------------------------------------\n\n val regfile = Mem(numRegisters, UInt(registerWidth.W))\n\n // --------------------------------------------------------------\n // Read ports.\n\n val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))\n\n // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).\n val read_addrs = io.read_ports.map(p => RegNext(p.addr))\n\n for (i <- 0 until numReadPorts) {\n read_data(i) := regfile(read_addrs(i))\n }\n\n // --------------------------------------------------------------\n // Bypass out of the ALU's write ports.\n // We are assuming we cannot bypass a writer to a reader within the regfile memory\n // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.\n // But since these bypasses are expensive, and not all write ports need to bypass their data,\n // only perform the w->r bypass on a select number of write ports.\n\n require (bypassableArray.length == io.write_ports.length)\n\n if (bypassableArray.reduce(_||_)) {\n val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()\n io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }\n\n for (i <- 0 until numReadPorts) {\n val bypass_ens = bypassable_wports.map(x => x.valid &&\n x.bits.addr === read_addrs(i))\n\n val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))\n\n io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))\n }\n } else {\n for (i <- 0 until numReadPorts) {\n io.read_ports(i).data := read_data(i)\n }\n }\n\n // --------------------------------------------------------------\n // Write ports.\n\n for (wport <- io.write_ports) {\n when (wport.valid) {\n regfile(wport.bits.addr) := wport.bits.data\n }\n }\n\n // ensure there is only 1 writer per register (unless to preg0)\n if (numWritePorts > 1) {\n for (i <- 0 until (numWritePorts - 1)) {\n for (j <- (i + 1) until numWritePorts) {\n assert(!io.write_ports(i).valid ||\n !io.write_ports(j).valid ||\n (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||\n (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here\n \"[regfile] too many writers a register\")\n }\n }\n }\n}", + "response": "module regfile_52x64(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [5:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [63:0] R1_data,\n input [5:0] R2_addr,\n input R2_en,\n input R2_clk,\n output [63:0] R2_data,\n input [5:0] R3_addr,\n input R3_en,\n input R3_clk,\n output [63:0] R3_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data,\n input [5:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [63:0] W1_data\n);\n\n reg [63:0] Memory[0:51];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 64'bx;\n assign R2_data = R2_en ? Memory[R2_addr] : 64'bx;\n assign R3_data = R3_en ? Memory[R3_addr] : 64'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a28d64s3k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [2:0] io_enq_bits_source,\n input [27:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [2:0] io_deq_bits_source,\n output [27:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [2:0] saved_source;\n reg [27:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module ListBuffer_PutBufferAEntry_q40_e40(\n input clock,\n input reset,\n output io_push_ready,\n input io_push_valid,\n input [5:0] io_push_bits_index,\n input [31:0] io_push_bits_data_data,\n input [3:0] io_push_bits_data_mask,\n input io_push_bits_data_corrupt,\n output [39:0] io_valid,\n input io_pop_valid,\n input [5:0] io_pop_bits,\n output [31:0] io_data_data,\n output [3:0] io_data_mask,\n output io_data_corrupt\n);\n\n wire [36:0] _data_ext_R0_data;\n wire [5:0] _next_ext_R0_data;\n wire [5:0] _tail_ext_R0_data;\n wire [5:0] _tail_ext_R1_data;\n wire [5:0] _head_ext_R0_data;\n reg [39:0] valid;\n reg [39:0] used;\n wire [39:0] _freeOH_T_22 = ~used;\n wire [38:0] _freeOH_T_3 = _freeOH_T_22[38:0] | {_freeOH_T_22[37:0], 1'h0};\n wire [38:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[36:0], 2'h0};\n wire [38:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[34:0], 4'h0};\n wire [38:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[30:0], 8'h0};\n wire [38:0] _freeOH_T_15 = _freeOH_T_12 | {_freeOH_T_12[22:0], 16'h0};\n wire [39:0] _GEN = {~(_freeOH_T_15 | {_freeOH_T_15[6:0], 32'h0}), 1'h1} & _freeOH_T_22;\n wire [30:0] _freeIdx_T_1 = {24'h0, _GEN[39:33]} | _GEN[31:1];\n wire [14:0] _freeIdx_T_3 = _freeIdx_T_1[30:16] | _freeIdx_T_1[14:0];\n wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0];\n wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0];\n wire [5:0] freeIdx = {|(_GEN[39:32]), |(_freeIdx_T_1[30:15]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]};\n wire [39:0] _push_valid_T = valid >> io_push_bits_index;\n wire io_push_ready_0 = used != 40'hFFFFFFFFFF;\n wire data_MPORT_en = io_push_ready_0 & io_push_valid;\n wire [63:0] _valid_clr_T = 64'h1 << io_pop_bits;\n wire [63:0] _valid_set_T = 64'h1 << io_push_bits_index;\n wire [63:0] _used_clr_T = 64'h1 << _head_ext_R0_data;\n always @(posedge clock) begin\n if (reset) begin\n valid <= 40'h0;\n used <= 40'h0;\n end\n else begin\n valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? _valid_clr_T[39:0] : 40'h0) | (data_MPORT_en ? _valid_set_T[39:0] : 40'h0);\n used <= used & ~(io_pop_valid ? _used_clr_T[39:0] : 40'h0) | (data_MPORT_en ? _GEN : 40'h0);\n end\n end\n head_40x6 head_ext (\n .R0_addr (io_pop_bits),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_head_ext_R0_data),\n .W0_addr (io_pop_bits),\n .W0_en (io_pop_valid),\n .W0_clk (clock),\n .W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? freeIdx : _next_ext_R0_data),\n .W1_addr (io_push_bits_index),\n .W1_en (data_MPORT_en & ~(_push_valid_T[0])),\n .W1_clk (clock),\n .W1_data (freeIdx)\n );\n tail_40x6 tail_ext (\n .R0_addr (io_push_bits_index),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_tail_ext_R0_data),\n .R1_addr (io_pop_bits),\n .R1_en (io_pop_valid),\n .R1_clk (clock),\n .R1_data (_tail_ext_R1_data),\n .W0_addr (io_push_bits_index),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n next_40x6 next_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (io_pop_valid),\n .R0_clk (clock),\n .R0_data (_next_ext_R0_data),\n .W0_addr (_tail_ext_R0_data),\n .W0_en (data_MPORT_en & _push_valid_T[0]),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n data_40x37 data_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_data_ext_R0_data),\n .W0_addr (freeIdx),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data ({io_push_bits_data_corrupt, io_push_bits_data_mask, io_push_bits_data_data})\n );\n assign io_push_ready = io_push_ready_0;\n assign io_valid = valid;\n assign io_data_data = _data_ext_R0_data[31:0];\n assign io_data_mask = _data_ext_R0_data[35:32];\n assign io_data_corrupt = _data_ext_R0_data[36];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [43:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [43:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_ext table_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw88_f32(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [85:0] io_out_bits_payload,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_payload = {io_in_bits_flit[23:0], data_1, data_0[31:2]};\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module head_15x6(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data,\n input [3:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [5:0] W1_data\n);\n\n reg [5:0] Memory[0:14];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module ListBuffer_QueuedRequest_q21_e33(\n input clock,\n input reset,\n output io_push_ready,\n input io_push_valid,\n input [4:0] io_push_bits_index,\n input io_push_bits_data_prio_0,\n input io_push_bits_data_prio_2,\n input io_push_bits_data_control,\n input [2:0] io_push_bits_data_opcode,\n input [2:0] io_push_bits_data_param,\n input [2:0] io_push_bits_data_size,\n input [5:0] io_push_bits_data_source,\n input [12:0] io_push_bits_data_tag,\n input [5:0] io_push_bits_data_offset,\n input [5:0] io_push_bits_data_put,\n output [20:0] io_valid,\n input io_pop_valid,\n input [4:0] io_pop_bits,\n output io_data_prio_0,\n output io_data_prio_1,\n output io_data_prio_2,\n output io_data_control,\n output [2:0] io_data_opcode,\n output [2:0] io_data_param,\n output [2:0] io_data_size,\n output [5:0] io_data_source,\n output [12:0] io_data_tag,\n output [5:0] io_data_offset,\n output [5:0] io_data_put\n);\n\n wire [43:0] _data_ext_R0_data;\n wire [5:0] _next_ext_R0_data;\n wire [5:0] _tail_ext_R0_data;\n wire [5:0] _tail_ext_R1_data;\n wire [5:0] _head_ext_R0_data;\n reg [20:0] valid;\n reg [32:0] used;\n wire [32:0] _freeOH_T_22 = ~used;\n wire [31:0] _freeOH_T_3 = _freeOH_T_22[31:0] | {_freeOH_T_22[30:0], 1'h0};\n wire [31:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[29:0], 2'h0};\n wire [31:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[27:0], 4'h0};\n wire [31:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[23:0], 8'h0};\n wire [32:0] _GEN = {~(_freeOH_T_12 | {_freeOH_T_12[15:0], 16'h0}), 1'h1} & _freeOH_T_22;\n wire [14:0] _freeIdx_T_3 = _GEN[31:17] | _GEN[15:1];\n wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0];\n wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0];\n wire [5:0] freeIdx = {_GEN[32], |(_GEN[31:16]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]};\n wire [20:0] _push_valid_T = valid >> io_push_bits_index;\n wire io_push_ready_0 = used != 33'h1FFFFFFFF;\n wire data_MPORT_en = io_push_ready_0 & io_push_valid;\n wire [31:0] _valid_clr_T = 32'h1 << io_pop_bits;\n wire [31:0] _valid_set_T = 32'h1 << io_push_bits_index;\n wire [63:0] _used_clr_T = 64'h1 << _head_ext_R0_data;\n always @(posedge clock) begin\n if (reset) begin\n valid <= 21'h0;\n used <= 33'h0;\n end\n else begin\n valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? _valid_clr_T[20:0] : 21'h0) | (data_MPORT_en ? _valid_set_T[20:0] : 21'h0);\n used <= used & ~(io_pop_valid ? _used_clr_T[32:0] : 33'h0) | (data_MPORT_en ? _GEN : 33'h0);\n end\n end\n head_21x6 head_ext (\n .R0_addr (io_pop_bits),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_head_ext_R0_data),\n .W0_addr (io_pop_bits),\n .W0_en (io_pop_valid),\n .W0_clk (clock),\n .W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? freeIdx : _next_ext_R0_data),\n .W1_addr (io_push_bits_index),\n .W1_en (data_MPORT_en & ~(_push_valid_T[0])),\n .W1_clk (clock),\n .W1_data (freeIdx)\n );\n tail_21x6 tail_ext (\n .R0_addr (io_push_bits_index),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_tail_ext_R0_data),\n .R1_addr (io_pop_bits),\n .R1_en (io_pop_valid),\n .R1_clk (clock),\n .R1_data (_tail_ext_R1_data),\n .W0_addr (io_push_bits_index),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n next_33x6 next_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (io_pop_valid),\n .R0_clk (clock),\n .R0_data (_next_ext_R0_data),\n .W0_addr (_tail_ext_R0_data),\n .W0_en (data_MPORT_en & _push_valid_T[0]),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n data_33x44 data_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_data_ext_R0_data),\n .W0_addr (freeIdx),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data ({io_push_bits_data_put, io_push_bits_data_offset, io_push_bits_data_tag, io_push_bits_data_source, io_push_bits_data_size, io_push_bits_data_param, io_push_bits_data_opcode, io_push_bits_data_control, io_push_bits_data_prio_2, 1'h0, io_push_bits_data_prio_0})\n );\n assign io_push_ready = io_push_ready_0;\n assign io_valid = valid;\n assign io_data_prio_0 = _data_ext_R0_data[0];\n assign io_data_prio_1 = _data_ext_R0_data[1];\n assign io_data_prio_2 = _data_ext_R0_data[2];\n assign io_data_control = _data_ext_R0_data[3];\n assign io_data_opcode = _data_ext_R0_data[6:4];\n assign io_data_param = _data_ext_R0_data[9:7];\n assign io_data_size = _data_ext_R0_data[12:10];\n assign io_data_source = _data_ext_R0_data[18:13];\n assign io_data_tag = _data_ext_R0_data[31:19];\n assign io_data_offset = _data_ext_R0_data[37:32];\n assign io_data_put = _data_ext_R0_data[43:38];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Ported from Rocket-Chip\n// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.rocket._\n\nimport boom.v3.common._\nimport boom.v3.exu.BrUpdateInfo\nimport boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose}\n\n\nclass BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))\n val meta_read = Decoupled(new L1MetaReadReq)\n val resp = Output(Bool())\n val idx = Output(Valid(UInt()))\n val data_req = Decoupled(new L1DataReadReq)\n val data_resp = Input(UInt(encRowBits.W))\n val mem_grant = Input(Bool())\n val release = Decoupled(new TLBundleC(edge.bundle))\n val lsu_release = Decoupled(new TLBundleC(edge.bundle))\n })\n\n val req = Reg(new WritebackReq(edge.bundle))\n val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5)\n val state = RegInit(s_invalid)\n val r1_data_req_fired = RegInit(false.B)\n val r2_data_req_fired = RegInit(false.B)\n val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))\n val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))\n val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))\n val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)\n val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W)))\n val acked = RegInit(false.B)\n\n io.idx.valid := state =/= s_invalid\n io.idx.bits := req.idx\n io.release.valid := false.B\n io.release.bits := DontCare\n io.req.ready := false.B\n io.meta_read.valid := false.B\n io.meta_read.bits := DontCare\n io.data_req.valid := false.B\n io.data_req.bits := DontCare\n io.resp := false.B\n io.lsu_release.valid := false.B\n io.lsu_release.bits := DontCare\n\n\n val r_address = Cat(req.tag, req.idx) << blockOffBits\n val id = cfg.nMSHRs\n val probeResponse = edge.ProbeAck(\n fromSource = id.U,\n toAddress = r_address,\n lgSize = lgCacheBlockBytes.U,\n reportPermissions = req.param,\n data = wb_buffer(data_req_cnt))\n\n val voluntaryRelease = edge.Release(\n fromSource = id.U,\n toAddress = r_address,\n lgSize = lgCacheBlockBytes.U,\n shrinkPermissions = req.param,\n data = wb_buffer(data_req_cnt))._2\n\n\n when (state === s_invalid) {\n io.req.ready := true.B\n when (io.req.fire) {\n state := s_fill_buffer\n data_req_cnt := 0.U\n req := io.req.bits\n acked := false.B\n }\n } .elsewhen (state === s_fill_buffer) {\n io.meta_read.valid := data_req_cnt < refillCycles.U\n io.meta_read.bits.idx := req.idx\n io.meta_read.bits.tag := req.tag\n\n io.data_req.valid := data_req_cnt < refillCycles.U\n io.data_req.bits.way_en := req.way_en\n io.data_req.bits.addr := (if(refillCycles > 1)\n Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))\n else req.idx) << rowOffBits\n\n r1_data_req_fired := false.B\n r1_data_req_cnt := 0.U\n r2_data_req_fired := r1_data_req_fired\n r2_data_req_cnt := r1_data_req_cnt\n when (io.data_req.fire && io.meta_read.fire) {\n r1_data_req_fired := true.B\n r1_data_req_cnt := data_req_cnt\n data_req_cnt := data_req_cnt + 1.U\n }\n when (r2_data_req_fired) {\n wb_buffer(r2_data_req_cnt) := io.data_resp\n when (r2_data_req_cnt === (refillCycles-1).U) {\n io.resp := true.B\n state := s_lsu_release\n data_req_cnt := 0.U\n }\n }\n } .elsewhen (state === s_lsu_release) {\n io.lsu_release.valid := true.B\n io.lsu_release.bits := probeResponse\n when (io.lsu_release.fire) {\n state := s_active\n }\n } .elsewhen (state === s_active) {\n io.release.valid := data_req_cnt < refillCycles.U\n io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)\n\n when (io.mem_grant) {\n acked := true.B\n }\n when (io.release.fire) {\n data_req_cnt := data_req_cnt + 1.U\n }\n when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) {\n state := Mux(req.voluntary, s_grant, s_invalid)\n }\n } .elsewhen (state === s_grant) {\n when (io.mem_grant) {\n acked := true.B\n }\n when (acked) {\n state := s_invalid\n }\n }\n}\n\nclass BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))\n val rep = Decoupled(new TLBundleC(edge.bundle))\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_write = Decoupled(new L1MetaWriteReq)\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n val way_en = Input(UInt(nWays.W))\n val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done\n val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed?\n val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?\n val block_state = Input(new ClientMetadata())\n val lsu_release = Decoupled(new TLBundleC(edge.bundle))\n\n val state = Output(Valid(UInt(coreMaxAddrBits.W)))\n })\n\n val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::\n s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp ::\n s_meta_write :: s_meta_write_resp :: Nil) = Enum(11)\n val state = RegInit(s_invalid)\n\n val req = Reg(new TLBundleB(edge.bundle))\n val req_idx = req.address(idxMSB, idxLSB)\n val req_tag = req.address >> untagBits\n\n val way_en = Reg(UInt())\n val tag_matches = way_en.orR\n val old_coh = Reg(new ClientMetadata)\n val miss_coh = ClientMetadata.onReset\n val reply_coh = Mux(tag_matches, old_coh, miss_coh)\n val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)\n\n io.state.valid := state =/= s_invalid\n io.state.bits := req.address\n\n io.req.ready := state === s_invalid\n io.rep.valid := state === s_release\n io.rep.bits := edge.ProbeAck(req, report_param)\n\n assert(!io.rep.valid || !edge.hasData(io.rep.bits),\n \"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\")\n\n io.meta_read.valid := state === s_meta_read\n io.meta_read.bits.idx := req_idx\n io.meta_read.bits.tag := req_tag\n io.meta_read.bits.way_en := ~(0.U(nWays.W))\n\n io.meta_write.valid := state === s_meta_write\n io.meta_write.bits.way_en := way_en\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.tag := req_tag\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.data.coh := new_coh\n\n io.wb_req.valid := state === s_writeback_req\n io.wb_req.bits.source := req.source\n io.wb_req.bits.idx := req_idx\n io.wb_req.bits.tag := req_tag\n io.wb_req.bits.param := report_param\n io.wb_req.bits.way_en := way_en\n io.wb_req.bits.voluntary := false.B\n\n\n io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp)\n\n io.lsu_release.valid := state === s_lsu_release\n io.lsu_release.bits := edge.ProbeAck(req, report_param)\n\n // state === s_invalid\n when (state === s_invalid) {\n when (io.req.fire) {\n state := s_meta_read\n req := io.req.bits\n }\n } .elsewhen (state === s_meta_read) {\n when (io.meta_read.fire) {\n state := s_meta_resp\n }\n } .elsewhen (state === s_meta_resp) {\n // we need to wait one cycle for the metadata to be read from the array\n state := s_mshr_req\n } .elsewhen (state === s_mshr_req) {\n old_coh := io.block_state\n way_en := io.way_en\n // if the read didn't go through, we need to retry\n state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read)\n } .elsewhen (state === s_mshr_resp) {\n state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release)\n } .elsewhen (state === s_lsu_release) {\n when (io.lsu_release.fire) {\n state := s_release\n }\n } .elsewhen (state === s_release) {\n when (io.rep.ready) {\n state := Mux(tag_matches, s_meta_write, s_invalid)\n }\n } .elsewhen (state === s_writeback_req) {\n when (io.wb_req.fire) {\n state := s_writeback_resp\n }\n } .elsewhen (state === s_writeback_resp) {\n // wait for the writeback request to finish before updating the metadata\n when (io.wb_req.ready) {\n state := s_meta_write\n }\n } .elsewhen (state === s_meta_write) {\n when (io.meta_write.fire) {\n state := s_meta_write_resp\n }\n } .elsewhen (state === s_meta_write_resp) {\n state := s_invalid\n }\n}\n\nclass BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) {\n val req = Vec(memWidth, new L1MetaReadReq)\n}\n\nclass BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) {\n val req = Vec(memWidth, new L1DataReadReq)\n val valid = Vec(memWidth, Bool())\n}\n\nabstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters {\n val io = IO(new BoomBundle {\n val read = Input(Vec(memWidth, Valid(new L1DataReadReq)))\n val write = Input(Valid(new L1DataWriteReq))\n val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W))))\n val nacks = Output(Vec(memWidth, Bool()))\n })\n\n def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n}\n\nclass BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray\n{\n\n val waddr = io.write.bits.addr >> rowOffBits\n for (j <- 0 until memWidth) {\n\n val raddr = io.read(j).bits.addr >> rowOffBits\n for (w <- 0 until nWays) {\n val array = DescribedSRAM(\n name = s\"array_${w}_${j}\",\n desc = \"Non-blocking DCache Data Array\",\n size = nSets * refillCycles,\n data = Vec(rowWords, Bits(encDataBits.W))\n )\n when (io.write.bits.way_en(w) && io.write.valid) {\n val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))\n array.write(waddr, data, io.write.bits.wmask.asBools)\n }\n io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt)\n }\n io.nacks(j) := false.B\n }\n}\n\nclass BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray {\n\n val nBanks = boomParams.numDCacheBanks\n val bankSize = nSets * refillCycles / nBanks\n require (nBanks >= memWidth)\n require (bankSize > 0)\n\n val bankBits = log2Ceil(nBanks)\n val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes)\n val bidxBits = log2Ceil(bankSize)\n val bidxOffBits = bankOffBits + bankBits\n\n //----------------------------------------------------------------------------------------------------\n\n val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U)\n val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U\n val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0)))\n val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0)\n\n val s0_read_valids = VecInit(io.read.map(_.valid))\n val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)))\n val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c}\n val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)}))\n val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools\n\n //----------------------------------------------------------------------------------------------------\n\n val s1_rbanks = RegNext(s0_rbanks)\n val s1_ridxs = RegNext(s0_ridxs)\n val s1_read_valids = RegNext(s0_read_valids)\n val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j =>\n if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i)\n else if (j == i) true.B else false.B))))\n val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i)\n else if (j == i) true.B else false.B))\n val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR)\n val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks))\n\n //----------------------------------------------------------------------------------------------------\n\n val s2_bank_selection = RegNext(s1_bank_selection)\n val s2_nacks = RegNext(s1_nacks)\n\n for (w <- 0 until nWays) {\n val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W)))\n\n for (b <- 0 until nBanks) {\n val array = DescribedSRAM(\n name = s\"array_${w}_${b}\",\n desc = \"Non-blocking DCache Data Array\",\n size = bankSize,\n data = Vec(rowWords, Bits(encDataBits.W))\n )\n val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs)\n val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en))\n s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt\n\n when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) {\n val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))\n array.write(s0_widx, data, io.write.bits.wmask.asBools)\n }\n }\n\n for (i <- 0 until memWidth) {\n io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))\n }\n }\n\n io.nacks := s2_nacks\n}\n\n/**\n * Top level class wrapping a non-blocking dcache.\n *\n * @param hartid hardware thread for the cache\n */\nclass BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule\n{\n private val tileParams = p(TileKey)\n protected val cfg = tileParams.dcache.get\n\n protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(\n name = s\"Core ${staticIdForMetadataUseOnly} DCache\",\n sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)),\n supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))\n\n protected def mmioClientParameters = Seq(TLMasterParameters.v1(\n name = s\"Core ${staticIdForMetadataUseOnly} DCache MMIO\",\n sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),\n requestFifo = true))\n\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(\n cacheClientParameters ++ mmioClientParameters,\n minLatency = 1)))\n\n\n lazy val module = new BoomNonBlockingDCacheModule(this)\n\n def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)\n\n require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, \"CFLUSH_D_L1 instruction requires a D$\")\n}\n\n\nclass BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) {\n val lsu = Flipped(new LSUDMemIO)\n}\n\nclass BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer)\n with HasL1HellaCacheParameters\n with HasBoomCoreParameters\n{\n implicit val edge = outer.node.edges.out(0)\n val (tl_out, _) = outer.node.out(0)\n val io = IO(new BoomDCacheBundle)\n\n private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)\n fifoManagers.foreach { m =>\n require (m.fifoId == fifoManagers.head.fifoId,\n s\"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}\")\n }\n\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6)\n\n val wb = Module(new BoomWritebackUnit)\n val prober = Module(new BoomProbeUnit)\n val mshrs = Module(new BoomMSHRFile)\n mshrs.io.clear_all := io.lsu.force_order\n mshrs.io.brupdate := io.lsu.brupdate\n mshrs.io.exception := io.lsu.exception\n mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx\n mshrs.io.rob_head_idx := io.lsu.rob_head_idx\n\n // tags\n def onReset = L1Metadata(0.U, ClientMetadata.onReset)\n val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) }\n val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))\n // 0 goes to MSHR refills, 1 goes to prober\n val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6))\n // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read,\n // 4 goes to pipeline, 5 goes to prefetcher\n\n metaReadArb.io.in := DontCare\n for (w <- 0 until memWidth) {\n meta(w).io.write.valid := metaWriteArb.io.out.fire\n meta(w).io.write.bits := metaWriteArb.io.out.bits\n meta(w).io.read.valid := metaReadArb.io.out.valid\n meta(w).io.read.bits := metaReadArb.io.out.bits.req(w)\n }\n metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_)\n metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_)\n\n // data\n val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray)\n val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2))\n // 0 goes to pipeline, 1 goes to MSHR refills\n val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3))\n // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline\n dataReadArb.io.in := DontCare\n\n for (w <- 0 until memWidth) {\n data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid\n data.io.read(w).bits := dataReadArb.io.out.bits.req(w)\n }\n dataReadArb.io.out.ready := true.B\n\n data.io.write.valid := dataWriteArb.io.out.fire\n data.io.write.bits := dataWriteArb.io.out.bits\n dataWriteArb.io.out.ready := true.B\n\n // ------------\n // New requests\n\n io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready\n metaReadArb.io.in(4).valid := io.lsu.req.valid\n dataReadArb.io.in(2).valid := io.lsu.req.valid\n for (w <- 0 until memWidth) {\n // Tag read for new requests\n metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits\n metaReadArb.io.in(4).bits.req(w).way_en := DontCare\n metaReadArb.io.in(4).bits.req(w).tag := DontCare\n // Data read for new requests\n dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid\n dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr\n dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W)\n }\n\n // ------------\n // MSHR Replays\n val replay_req = Wire(Vec(memWidth, new BoomDCacheReq))\n replay_req := DontCare\n replay_req(0).uop := mshrs.io.replay.bits.uop\n replay_req(0).addr := mshrs.io.replay.bits.addr\n replay_req(0).data := mshrs.io.replay.bits.data\n replay_req(0).is_hella := mshrs.io.replay.bits.is_hella\n mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready\n // Tag read for MSHR replays\n // We don't actually need to read the metadata, for replays we already know our way\n metaReadArb.io.in(0).valid := mshrs.io.replay.valid\n metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits\n metaReadArb.io.in(0).bits.req(0).way_en := DontCare\n metaReadArb.io.in(0).bits.req(0).tag := DontCare\n // Data read for MSHR replays\n dataReadArb.io.in(0).valid := mshrs.io.replay.valid\n dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr\n dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en\n dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B)\n\n // -----------\n // MSHR Meta read\n val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq))\n mshr_read_req := DontCare\n mshr_read_req(0).uop := NullMicroOp\n mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits\n mshr_read_req(0).data := DontCare\n mshr_read_req(0).is_hella := false.B\n metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid\n metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits\n mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready\n\n\n\n // -----------\n // Write-backs\n val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire\n val wb_req = Wire(Vec(memWidth, new BoomDCacheReq))\n wb_req := DontCare\n wb_req(0).uop := NullMicroOp\n wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)\n wb_req(0).data := DontCare\n wb_req(0).is_hella := false.B\n // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read\n // Tag read for write-back\n metaReadArb.io.in(2).valid := wb.io.meta_read.valid\n metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits\n wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready\n // Data read for write-back\n dataReadArb.io.in(1).valid := wb.io.data_req.valid\n dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits\n dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B)\n wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready\n assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\n\n // -------\n // Prober\n val prober_fire = prober.io.meta_read.fire\n val prober_req = Wire(Vec(memWidth, new BoomDCacheReq))\n prober_req := DontCare\n prober_req(0).uop := NullMicroOp\n prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits\n prober_req(0).data := DontCare\n prober_req(0).is_hella := false.B\n // Tag read for prober\n metaReadArb.io.in(1).valid := prober.io.meta_read.valid\n metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits\n prober.io.meta_read.ready := metaReadArb.io.in(1).ready\n // Prober does not need to read data array\n\n // -------\n // Prefetcher\n val prefetch_fire = mshrs.io.prefetch.fire\n val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq))\n prefetch_req := DontCare\n prefetch_req(0) := mshrs.io.prefetch.bits\n // Tag read for prefetch\n metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid\n metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits\n metaReadArb.io.in(5).bits.req(0).way_en := DontCare\n metaReadArb.io.in(5).bits.req(0).tag := DontCare\n mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready\n // Prefetch does not need to read data array\n\n val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)),\n Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire,\n VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools)))\n val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)),\n Mux(wb_fire , wb_req,\n Mux(prober_fire , prober_req,\n Mux(prefetch_fire , prefetch_req,\n Mux(mshrs.io.meta_read.fire, mshr_read_req\n , replay_req)))))\n val s0_type = Mux(io.lsu.req.fire , t_lsu,\n Mux(wb_fire , t_wb,\n Mux(prober_fire , t_probe,\n Mux(prefetch_fire , t_prefetch,\n Mux(mshrs.io.meta_read.fire, t_mshr_meta_read\n , t_replay)))))\n\n // Does this request need to send a response or nack\n val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid,\n VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools))\n\n\n val s1_req = RegNext(s0_req)\n for (w <- 0 until memWidth)\n s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop)\n val s2_store_failed = Wire(Bool())\n val s1_valid = widthMap(w =>\n RegNext(s0_valid(w) &&\n !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) &&\n !(io.lsu.exception && s0_req(w).uop.uses_ldq) &&\n !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq),\n init=false.B))\n for (w <- 0 until memWidth)\n assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\n val s1_addr = s1_req.map(_.addr)\n val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready)\n val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack)\n val s1_type = RegNext(s0_type)\n\n val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en)\n val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet\n val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en)\n\n // tag check\n def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))\n val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt)\n val s1_tag_match_way = widthMap(i =>\n Mux(s1_type === t_replay, s1_replay_way_en,\n Mux(s1_type === t_wb, s1_wb_way_en,\n Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en,\n wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt))))\n\n val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid)\n\n val s2_req = RegNext(s1_req)\n val s2_type = RegNext(s1_type)\n val s2_valid = widthMap(w =>\n RegNext(s1_valid(w) &&\n !io.lsu.s1_kill(w) &&\n !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) &&\n !(io.lsu.exception && s1_req(w).uop.uses_ldq) &&\n !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq)))\n for (w <- 0 until memWidth)\n s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop)\n\n val s2_tag_match_way = RegNext(s1_tag_match_way)\n val s2_tag_match = s2_tag_match_way.map(_.orR)\n val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh))))\n val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1)\n val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3)\n\n val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb))\n val s2_nack = Wire(Vec(memWidth, Bool()))\n assert(!(s2_type === t_replay && !s2_hit(0)), \"Replays should always hit\")\n assert(!(s2_type === t_wb && !s2_hit(0)), \"Writeback should always see data hit\")\n\n val s2_wb_idx_matches = RegNext(s1_wb_idx_matches)\n\n // lr/sc\n val debug_sc_fail_addr = RegInit(0.U)\n val debug_sc_fail_cnt = RegInit(0.U(8.W))\n\n val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W))\n val lrsc_valid = lrsc_count > lrscBackoff.U\n val lrsc_addr = Reg(UInt())\n val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay)\n val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay)\n val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits))\n val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0)\n when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }\n when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) ||\n (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) {\n when (s2_lr) {\n lrsc_count := (lrscCycles - 1).U\n lrsc_addr := s2_req(0).addr >> blockOffBits\n }\n when (lrsc_count > 0.U) {\n lrsc_count := 0.U\n }\n }\n for (w <- 0 until memWidth) {\n when (s2_valid(w) &&\n s2_type === t_lsu &&\n !s2_hit(w) &&\n !(s2_has_permission(w) && s2_tag_match(w)) &&\n s2_lrsc_addr_match(w) &&\n !s2_nack(w)) {\n lrsc_count := 0.U\n }\n }\n\n when (s2_valid(0)) {\n when (s2_req(0).addr === debug_sc_fail_addr) {\n when (s2_sc_fail) {\n debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U\n } .elsewhen (s2_sc) {\n debug_sc_fail_cnt := 0.U\n }\n } .otherwise {\n when (s2_sc_fail) {\n debug_sc_fail_addr := s2_req(0).addr\n debug_sc_fail_cnt := 1.U\n }\n }\n }\n assert(debug_sc_fail_cnt < 100.U, \"L1DCache failed too many SCs in a row\")\n\n val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W))))\n for (i <- 0 until memWidth) {\n for (w <- 0 until nWays) {\n s2_data(i)(w) := data.io.resp(i)(w)\n }\n }\n\n val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w)))\n val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes)))\n\n // replacement policy\n val replacer = cacheParams.replacement\n val s1_replaced_way_en = UIntToOH(replacer.way)\n val s2_replaced_way_en = UIntToOH(RegNext(replacer.way))\n val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq))\n\n // nack because of incoming probe\n val s2_nack_hit = RegNext(VecInit(s1_nack))\n // Nack when we hit something currently being evicted\n val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w))\n // MSHRs not ready for request\n val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready)\n // Bank conflict on data arrays\n val s2_nack_data = widthMap(w => data.io.nacks(w))\n // Can't allocate MSHR for same set currently being written back\n val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w))\n\n s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay)\n val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) &&\n (s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd)))))\n val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w)))\n for (w <- 0 until memWidth)\n assert(!(s2_send_resp(w) && s2_send_nack(w)))\n\n // hits always send a response\n // If MSHR is not available, LSU has to replay this request later\n // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later\n s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq\n\n // Miss handling\n for (w <- 0 until memWidth) {\n mshrs.io.req(w).valid := s2_valid(w) &&\n !s2_hit(w) &&\n !s2_nack_hit(w) &&\n !s2_nack_victim(w) &&\n !s2_nack_data(w) &&\n !s2_nack_wb(w) &&\n s2_type.isOneOf(t_lsu, t_prefetch) &&\n !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) &&\n !(io.lsu.exception && s2_req(w).uop.uses_ldq) &&\n (isPrefetch(s2_req(w).uop.mem_cmd) ||\n isRead(s2_req(w).uop.mem_cmd) ||\n isWrite(s2_req(w).uop.mem_cmd))\n assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \"Replays should not need to go back into MSHRs\")\n mshrs.io.req(w).bits := DontCare\n mshrs.io.req(w).bits.uop := s2_req(w).uop\n mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop)\n mshrs.io.req(w).bits.addr := s2_req(w).addr\n mshrs.io.req(w).bits.tag_match := s2_tag_match(w)\n mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w))\n mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en)\n\n mshrs.io.req(w).bits.data := s2_req(w).data\n mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella\n mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w)\n }\n\n mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy\n mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp))\n when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss }\n tl_out.a <> mshrs.io.mem_acquire\n\n // probes and releases\n prober.io.req.valid := tl_out.b.valid && !lrsc_valid\n tl_out.b.ready := prober.io.req.ready && !lrsc_valid\n prober.io.req.bits := tl_out.b.bits\n prober.io.way_en := s2_tag_match_way(0)\n prober.io.block_state := s2_hit_state(0)\n metaWriteArb.io.in(1) <> prober.io.meta_write\n prober.io.mshr_rdy := mshrs.io.probe_rdy\n prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid\n mshrs.io.prober_state := prober.io.state\n\n // refills\n when (tl_out.d.bits.source === cfg.nMSHRs.U) {\n // This should be ReleaseAck\n tl_out.d.ready := true.B\n mshrs.io.mem_grant.valid := false.B\n mshrs.io.mem_grant.bits := DontCare\n } .otherwise {\n // This should be GrantData\n mshrs.io.mem_grant <> tl_out.d\n }\n\n dataWriteArb.io.in(1) <> mshrs.io.refill\n metaWriteArb.io.in(0) <> mshrs.io.meta_write\n\n tl_out.e <> mshrs.io.mem_finish\n\n // writebacks\n val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))\n // 0 goes to prober, 1 goes to MSHR evictions\n wbArb.io.in(0) <> prober.io.wb_req\n wbArb.io.in(1) <> mshrs.io.wb_req\n wb.io.req <> wbArb.io.out\n wb.io.data_resp := s2_data_muxed(0)\n mshrs.io.wb_resp := wb.io.resp\n wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U\n\n val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2))\n io.lsu.release <> lsu_release_arb.io.out\n lsu_release_arb.io.in(0) <> wb.io.lsu_release\n lsu_release_arb.io.in(1) <> prober.io.lsu_release\n\n TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)\n\n io.lsu.perf.release := edge.done(tl_out.c)\n io.lsu.perf.acquire := edge.done(tl_out.a)\n\n // load data gen\n val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))\n val s2_data_word = Wire(Vec(memWidth, UInt()))\n\n val loadgen = (0 until memWidth).map { w =>\n new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr,\n s2_data_word(w), s2_sc && (w == 0).B, wordBytes)\n }\n // Mux between cache responses and uncache responses\n val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp)))\n for (w <- 0 until memWidth) {\n cache_resp(w).valid := s2_valid(w) && s2_send_resp(w)\n cache_resp(w).bits.uop := s2_req(w).uop\n cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail\n cache_resp(w).bits.is_hella := s2_req(w).is_hella\n }\n\n val uncache_resp = Wire(Valid(new BoomDCacheResp))\n uncache_resp.bits := mshrs.io.resp.bits\n uncache_resp.valid := mshrs.io.resp.valid\n mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits\n\n val resp = WireInit(cache_resp)\n var uncache_responding = false.B\n for (w <- 0 until memWidth) {\n val uncache_respond = !cache_resp(w).valid && !uncache_responding\n when (uncache_respond) {\n resp(w) := uncache_resp\n }\n uncache_responding = uncache_responding || uncache_respond\n }\n\n for (w <- 0 until memWidth) {\n io.lsu.resp(w).valid := resp(w).valid &&\n !(io.lsu.exception && resp(w).bits.uop.uses_ldq) &&\n !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop)\n io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits)\n\n io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) &&\n !(io.lsu.exception && s2_req(w).uop.uses_ldq) &&\n !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop)\n io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w))\n assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\n }\n\n // Store/amo hits\n val s3_req = RegNext(s2_req(0))\n val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) &&\n !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0)))\n for (w <- 1 until memWidth) {\n assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) &&\n !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))),\n \"Store must go through 0th pipe in L1D\")\n }\n\n // For bypassing\n val s4_req = RegNext(s3_req)\n val s4_valid = RegNext(s3_valid)\n val s5_req = RegNext(s4_req)\n val s5_valid = RegNext(s4_valid)\n\n val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits)))\n val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits)))\n val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits)))\n\n // Store -> Load bypassing\n for (w <- 0 until memWidth) {\n s2_data_word(w) := Mux(s3_bypass(w), s3_req.data,\n Mux(s4_bypass(w), s4_req.data,\n Mux(s5_bypass(w), s5_req.data,\n s2_data_word_prebypass(w))))\n }\n val amoalu = Module(new AMOALU(xLen))\n amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask\n amoalu.io.cmd := s2_req(0).uop.mem_cmd\n amoalu.io.lhs := s2_data_word(0)\n amoalu.io.rhs := s2_req(0).data\n\n\n s3_req.data := amoalu.io.out\n val s3_way = RegNext(s2_tag_match_way(0))\n\n dataWriteArb.io.in(0).valid := s3_valid\n dataWriteArb.io.in(0).bits.addr := s3_req.addr\n dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))\n dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)\n dataWriteArb.io.in(0).bits.way_en := s3_way\n\n\n io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_)\n}", + "response": "module BoomProbeUnit(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [1:0] io_req_bits_param,\n input [3:0] io_req_bits_size,\n input [1:0] io_req_bits_source,\n input [31:0] io_req_bits_address,\n input io_rep_ready,\n output io_rep_valid,\n output [2:0] io_rep_bits_param,\n output [3:0] io_rep_bits_size,\n output [1:0] io_rep_bits_source,\n output [31:0] io_rep_bits_address,\n input io_meta_read_ready,\n output io_meta_read_valid,\n output [5:0] io_meta_read_bits_idx,\n output [19:0] io_meta_read_bits_tag,\n input io_meta_write_ready,\n output io_meta_write_valid,\n output [5:0] io_meta_write_bits_idx,\n output [3:0] io_meta_write_bits_way_en,\n output [1:0] io_meta_write_bits_data_coh_state,\n output [19:0] io_meta_write_bits_data_tag,\n input io_wb_req_ready,\n output io_wb_req_valid,\n output [19:0] io_wb_req_bits_tag,\n output [5:0] io_wb_req_bits_idx,\n output [2:0] io_wb_req_bits_param,\n output [3:0] io_wb_req_bits_way_en,\n input [3:0] io_way_en,\n input io_wb_rdy,\n input io_mshr_rdy,\n output io_mshr_wb_rdy,\n input [1:0] io_block_state_state,\n input io_lsu_release_ready,\n output io_lsu_release_valid,\n output [31:0] io_lsu_release_bits_address,\n output io_state_valid,\n output [39:0] io_state_bits\n);\n\n reg [3:0] state;\n reg [1:0] req_param;\n reg [3:0] req_size;\n reg [1:0] req_source;\n reg [31:0] req_address;\n reg [3:0] way_en;\n reg [1:0] old_coh_state;\n wire [3:0] _r_T = {req_param, (|way_en) ? old_coh_state : 2'h0};\n wire _r_T_26 = _r_T == 4'hB;\n wire _r_T_29 = _r_T == 4'h4;\n wire _r_T_33 = _r_T == 4'h5;\n wire _r_T_37 = _r_T == 4'h6;\n wire _r_T_41 = _r_T == 4'h7;\n wire _r_T_45 = _r_T == 4'h0;\n wire _r_T_49 = _r_T == 4'h1;\n wire _r_T_53 = _r_T == 4'h2;\n wire _r_T_57 = _r_T == 4'h3;\n wire _GEN = _r_T_57 | _r_T_53;\n wire [2:0] report_param = _GEN ? 3'h3 : _r_T_49 ? 3'h4 : _r_T_45 ? 3'h5 : _r_T_41 | _r_T_37 ? 3'h0 : _r_T_33 ? 3'h4 : _r_T_29 ? 3'h5 : _r_T_26 | _r_T == 4'hA ? 3'h1 : _r_T == 4'h9 ? 3'h2 : _r_T == 4'h8 ? 3'h5 : 3'h0;\n wire io_req_ready_0 = state == 4'h0;\n wire io_rep_valid_0 = state == 4'h6;\n wire io_meta_read_valid_0 = state == 4'h1;\n wire io_meta_write_valid_0 = state == 4'h9;\n wire io_wb_req_valid_0 = state == 4'h7;\n wire io_lsu_release_valid_0 = state == 4'h5;\n wire _GEN_0 = io_req_ready_0 & io_req_valid;\n wire [15:0][3:0] _GEN_1 = {{state}, {state}, {state}, {state}, {state}, {4'h0}, {io_meta_write_ready & io_meta_write_valid_0 ? 4'hA : state}, {io_wb_req_ready ? 4'h9 : state}, {io_wb_req_ready & io_wb_req_valid_0 ? 4'h8 : state}, {io_rep_ready ? ((|way_en) ? 4'h9 : 4'h0) : state}, {io_lsu_release_ready & io_lsu_release_valid_0 ? 4'h6 : state}, {{2'h1, (|way_en) & (_r_T_57 | ~(_r_T_53 | _r_T_49 | _r_T_45) & (_r_T_41 | ~(_r_T_37 | _r_T_33 | _r_T_29) & _r_T_26)), 1'h1}}, {io_mshr_rdy & io_wb_rdy ? 4'h4 : 4'h1}, {4'h3}, {io_meta_read_ready & io_meta_read_valid_0 ? 4'h2 : state}, {_GEN_0 ? 4'h1 : state}};\n always @(posedge clock) begin\n if (reset)\n state <= 4'h0;\n else\n state <= _GEN_1[state];\n if (_GEN_0) begin\n req_param <= io_req_bits_param;\n req_size <= io_req_bits_size;\n req_source <= io_req_bits_source;\n req_address <= io_req_bits_address;\n end\n if (io_req_ready_0 | io_meta_read_valid_0 | state == 4'h2 | state != 4'h3) begin\n end\n else begin\n way_en <= io_way_en;\n old_coh_state <= io_block_state_state;\n end\n end\n assign io_req_ready = io_req_ready_0;\n assign io_rep_valid = io_rep_valid_0;\n assign io_rep_bits_param = report_param;\n assign io_rep_bits_size = req_size;\n assign io_rep_bits_source = req_source;\n assign io_rep_bits_address = req_address;\n assign io_meta_read_valid = io_meta_read_valid_0;\n assign io_meta_read_bits_idx = req_address[11:6];\n assign io_meta_read_bits_tag = req_address[31:12];\n assign io_meta_write_valid = io_meta_write_valid_0;\n assign io_meta_write_bits_idx = req_address[11:6];\n assign io_meta_write_bits_way_en = way_en;\n assign io_meta_write_bits_data_coh_state = _GEN ? 2'h2 : _r_T_49 ? 2'h1 : _r_T_45 ? 2'h0 : {1'h0, _r_T_41 | _r_T_37 | _r_T_33};\n assign io_meta_write_bits_data_tag = req_address[31:12];\n assign io_wb_req_valid = io_wb_req_valid_0;\n assign io_wb_req_bits_tag = req_address[31:12];\n assign io_wb_req_bits_idx = req_address[11:6];\n assign io_wb_req_bits_param = report_param;\n assign io_wb_req_bits_way_en = way_en;\n assign io_mshr_wb_rdy = ~(io_rep_valid_0 | io_wb_req_valid_0 | state == 4'h8 | io_meta_write_valid_0 | state == 4'hA);\n assign io_lsu_release_valid = io_lsu_release_valid_0;\n assign io_lsu_release_bits_address = req_address;\n assign io_state_valid = |state;\n assign io_state_bits = {8'h0, req_address};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw10_f32(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_head = io_in_bits_flit[1];\n assign io_out_bits_tail = io_in_bits_flit[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Fetch Target Queue (FTQ)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.\n//\n// TODO:\n// * reduce port counts.\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.util.{Str}\n\nimport boom.v3.common._\nimport boom.v3.exu._\nimport boom.v3.util._\n\n/**\n * FTQ Parameters used in configurations\n *\n * @param nEntries # of entries in the FTQ\n */\ncase class FtqParameters(\n nEntries: Int = 16\n)\n\n/**\n * Bundle to add to the FTQ RAM and to be used as the pass in IO\n */\nclass FTQBundle(implicit p: Parameters) extends BoomBundle\n with HasBoomFrontendParameters\n{\n // // TODO compress out high-order bits\n // val fetch_pc = UInt(vaddrBitsExtended.W)\n // IDX of instruction that was predicted taken, if any\n val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))\n // Was the CFI in this bundle found to be taken? or not\n val cfi_taken = Bool()\n // Was this CFI mispredicted by the branch prediction pipeline?\n val cfi_mispredicted = Bool()\n // What type of CFI was taken out of this bundle\n val cfi_type = UInt(CFI_SZ.W)\n // mask of branches which were visible in this fetch bundle\n val br_mask = UInt(fetchWidth.W)\n // This CFI is likely a CALL\n val cfi_is_call = Bool()\n // This CFI is likely a RET\n val cfi_is_ret = Bool()\n // Is the NPC after the CFI +4 or +2\n val cfi_npc_plus4 = Bool()\n // What was the top of the RAS that this bundle saw?\n val ras_top = UInt(vaddrBitsExtended.W)\n val ras_idx = UInt(log2Ceil(nRasEntries).W)\n\n // Which bank did this start from?\n val start_bank = UInt(1.W)\n\n // // Metadata for the branch predictor\n // val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))\n}\n\n/**\n * IO to provide a port for a FunctionalUnit to get the PC of an instruction.\n * And for JALRs, the PC of the next instruction.\n */\nclass GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle\n{\n val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))\n\n val entry = Output(new FTQBundle)\n val ghist = Output(new GlobalHistory)\n\n val pc = Output(UInt(vaddrBitsExtended.W))\n val com_pc = Output(UInt(vaddrBitsExtended.W))\n\n // the next_pc may not be valid (stalled or still being fetched)\n val next_val = Output(Bool())\n val next_pc = Output(UInt(vaddrBitsExtended.W))\n}\n\n/**\n * Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the\n * processor.\n *\n * @param num_entries # of entries in the FTQ\n */\nclass FetchTargetQueue(implicit p: Parameters) extends BoomModule\n with HasBoomCoreParameters\n with HasBoomFrontendParameters\n{\n val num_entries = ftqSz\n private val idx_sz = log2Ceil(num_entries)\n\n val io = IO(new BoomBundle {\n // Enqueue one entry for every fetch cycle.\n val enq = Flipped(Decoupled(new FetchBundle()))\n // Pass to FetchBuffer (newly fetched instructions).\n val enq_idx = Output(UInt(idx_sz.W))\n // ROB tells us the youngest committed ftq_idx to remove from FTQ.\n val deq = Flipped(Valid(UInt(idx_sz.W)))\n\n // Give PC info to BranchUnit.\n val get_ftq_pc = Vec(2, new GetPCFromFtqIO())\n\n\n // Used to regenerate PC for trace port stuff in FireSim\n // Don't tape this out, this blows up the FTQ\n val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))\n val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))\n\n val redirect = Input(Valid(UInt(idx_sz.W)))\n\n val brupdate = Input(new BrUpdateInfo)\n\n val bpdupdate = Output(Valid(new BranchPredictionUpdate))\n\n val ras_update = Output(Bool())\n val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))\n val ras_update_pc = Output(UInt(vaddrBitsExtended.W))\n\n })\n val bpd_ptr = RegInit(0.U(idx_sz.W))\n val deq_ptr = RegInit(0.U(idx_sz.W))\n val enq_ptr = RegInit(1.U(idx_sz.W))\n\n val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||\n (WrapInc(enq_ptr, num_entries) === bpd_ptr))\n\n\n val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))\n val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))\n val ram = Reg(Vec(num_entries, new FTQBundle))\n val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }\n val lhist = if (useLHist) {\n Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))\n } else {\n None\n }\n\n val do_enq = io.enq.fire\n\n\n // This register lets us initialize the ghist to 0\n val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))\n val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))\n val prev_pc = RegInit(0.U(vaddrBitsExtended.W))\n when (do_enq) {\n\n pcs(enq_ptr) := io.enq.bits.pc\n\n val new_entry = Wire(new FTQBundle)\n\n new_entry.cfi_idx := io.enq.bits.cfi_idx\n // Initially, if we see a CFI, it is assumed to be taken.\n // Branch resolutions may change this\n new_entry.cfi_taken := io.enq.bits.cfi_idx.valid\n new_entry.cfi_mispredicted := false.B\n new_entry.cfi_type := io.enq.bits.cfi_type\n new_entry.cfi_is_call := io.enq.bits.cfi_is_call\n new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret\n new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4\n new_entry.ras_top := io.enq.bits.ras_top\n new_entry.ras_idx := io.enq.bits.ghist.ras_idx\n new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask\n new_entry.start_bank := bank(io.enq.bits.pc)\n\n val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,\n io.enq.bits.ghist,\n prev_ghist.update(\n prev_entry.br_mask,\n prev_entry.cfi_taken,\n prev_entry.br_mask(prev_entry.cfi_idx.bits),\n prev_entry.cfi_idx.bits,\n prev_entry.cfi_idx.valid,\n prev_pc,\n prev_entry.cfi_is_call,\n prev_entry.cfi_is_ret\n )\n )\n\n lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))\n ghist.map( g => g.write(enq_ptr, new_ghist))\n meta.write(enq_ptr, io.enq.bits.bpd_meta)\n ram(enq_ptr) := new_entry\n\n prev_pc := io.enq.bits.pc\n prev_entry := new_entry\n prev_ghist := new_ghist\n\n enq_ptr := WrapInc(enq_ptr, num_entries)\n }\n\n io.enq_idx := enq_ptr\n\n io.bpdupdate.valid := false.B\n io.bpdupdate.bits := DontCare\n\n when (io.deq.valid) {\n deq_ptr := io.deq.bits\n }\n\n // This register avoids a spurious bpd update on the first fetch packet\n val first_empty = RegInit(true.B)\n\n // We can update the branch predictors when we know the target of the\n // CFI in this fetch bundle\n\n val ras_update = WireInit(false.B)\n val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))\n val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))\n io.ras_update := RegNext(ras_update)\n io.ras_update_pc := RegNext(ras_update_pc)\n io.ras_update_idx := RegNext(ras_update_idx)\n\n val bpd_update_mispredict = RegInit(false.B)\n val bpd_update_repair = RegInit(false.B)\n val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))\n\n val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,\n Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))\n val bpd_entry = RegNext(ram(bpd_idx))\n val bpd_ghist = ghist(0).read(bpd_idx, true.B)\n val bpd_lhist = if (useLHist) {\n lhist.get.read(bpd_idx, true.B)\n } else {\n VecInit(Seq.fill(nBanks) { 0.U })\n }\n val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs\n val bpd_pc = RegNext(pcs(bpd_idx))\n val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))\n\n when (io.redirect.valid) {\n bpd_update_mispredict := false.B\n bpd_update_repair := false.B\n } .elsewhen (RegNext(io.brupdate.b2.mispredict)) {\n bpd_update_mispredict := true.B\n bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)\n bpd_end_idx := RegNext(enq_ptr)\n } .elsewhen (bpd_update_mispredict) {\n bpd_update_mispredict := false.B\n bpd_update_repair := true.B\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {\n bpd_repair_pc := bpd_pc\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair) {\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||\n bpd_pc === bpd_repair_pc) {\n bpd_update_repair := false.B\n }\n\n }\n\n\n val do_commit_update = (!bpd_update_mispredict &&\n !bpd_update_repair &&\n bpd_ptr =/= deq_ptr &&\n enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&\n !io.brupdate.b2.mispredict &&\n !io.redirect.valid && !RegNext(io.redirect.valid))\n val do_mispredict_update = bpd_update_mispredict\n val do_repair_update = bpd_update_repair\n\n when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {\n val cfi_idx = bpd_entry.cfi_idx.bits\n val valid_repair = bpd_pc =/= bpd_repair_pc\n\n io.bpdupdate.valid := (!first_empty &&\n (bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&\n !(RegNext(do_repair_update) && !valid_repair))\n io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)\n io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)\n io.bpdupdate.bits.pc := bpd_pc\n io.bpdupdate.bits.btb_mispredicts := 0.U\n io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,\n MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)\n io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx\n io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted\n io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken\n io.bpdupdate.bits.target := bpd_target\n io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)\n io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR\n io.bpdupdate.bits.ghist := bpd_ghist\n io.bpdupdate.bits.lhist := bpd_lhist\n io.bpdupdate.bits.meta := bpd_meta\n\n first_empty := false.B\n }\n\n when (do_commit_update) {\n bpd_ptr := WrapInc(bpd_ptr, num_entries)\n }\n\n io.enq.ready := RegNext(!full || do_commit_update)\n\n val redirect_idx = io.redirect.bits\n val redirect_entry = ram(redirect_idx)\n val redirect_new_entry = WireInit(redirect_entry)\n\n when (io.redirect.valid) {\n enq_ptr := WrapInc(io.redirect.bits, num_entries)\n\n when (io.brupdate.b2.mispredict) {\n val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^\n Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)\n redirect_new_entry.cfi_idx.valid := true.B\n redirect_new_entry.cfi_idx.bits := new_cfi_idx\n redirect_new_entry.cfi_mispredicted := true.B\n redirect_new_entry.cfi_taken := io.brupdate.b2.taken\n redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx\n redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx\n }\n\n ras_update := true.B\n ras_update_pc := redirect_entry.ras_top\n ras_update_idx := redirect_entry.ras_idx\n\n } .elsewhen (RegNext(io.redirect.valid)) {\n prev_entry := RegNext(redirect_new_entry)\n prev_ghist := bpd_ghist\n prev_pc := bpd_pc\n\n ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)\n }\n\n //-------------------------------------------------------------\n // **** Core Read PCs ****\n //-------------------------------------------------------------\n\n for (i <- 0 until 2) {\n val idx = io.get_ftq_pc(i).ftq_idx\n val next_idx = WrapInc(idx, num_entries)\n val next_is_enq = (next_idx === enq_ptr) && io.enq.fire\n val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))\n val get_entry = ram(idx)\n val next_entry = ram(next_idx)\n io.get_ftq_pc(i).entry := RegNext(get_entry)\n if (i == 1)\n io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)\n else\n io.get_ftq_pc(i).ghist := DontCare\n io.get_ftq_pc(i).pc := RegNext(pcs(idx))\n io.get_ftq_pc(i).next_pc := RegNext(next_pc)\n io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)\n io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))\n }\n\n for (w <- 0 until coreWidth) {\n io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))\n }\n}", + "response": "module meta_0_0(\n input [3:0] R0_addr,\n input R0_clk,\n output [119:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [119:0] W0_data\n);\n\n meta_0_0_ext meta_0_0_ext (\n .R0_addr (R0_addr),\n .R0_en (1'h1),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Ported from Rocket-Chip\n// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.rocket._\n\nimport boom.v3.common._\nimport boom.v3.exu.BrUpdateInfo\nimport boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}\n\nclass BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)\n with HasL1HellaCacheParameters\n{\n // miss info\n val tag_match = Bool()\n val old_meta = new L1Metadata\n val way_en = UInt(nWays.W)\n\n // Used in the MSHRs\n val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)\n}\n\n\nclass BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val id = Input(UInt())\n\n val req_pri_val = Input(Bool())\n val req_pri_rdy = Output(Bool())\n val req_sec_val = Input(Bool())\n val req_sec_rdy = Output(Bool())\n\n val clear_prefetch = Input(Bool())\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val req = Input(new BoomDCacheReqInternal)\n val req_is_probe = Input(Bool())\n\n val idx = Output(Valid(UInt()))\n val way = Output(Valid(UInt()))\n val tag = Output(Valid(UInt()))\n\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val refill = Decoupled(new L1DataWriteReq)\n\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n // To inform the prefetcher when we are commiting the fetch of this line\n val commit_val = Output(Bool())\n val commit_addr = Output(UInt(coreMaxAddrBits.W))\n val commit_coh = Output(new ClientMetadata)\n\n // Reading from the line buffer\n val lb_read = Decoupled(new LineBufferReadReq)\n val lb_resp = Input(UInt(encRowBits.W))\n val lb_write = Decoupled(new LineBufferWriteReq)\n\n // Replays go through the cache pipeline again\n val replay = Decoupled(new BoomDCacheReqInternal)\n // Resp go straight out to the core\n val resp = Decoupled(new BoomDCacheResp)\n\n // Writeback unit tells us when it is done processing our wb\n val wb_resp = Input(Bool())\n\n val probe_rdy = Output(Bool())\n })\n\n // TODO: Optimize this. We don't want to mess with cache during speculation\n // s_refill_req : Make a request for a new cache line\n // s_refill_resp : Store the refill response into our buffer\n // s_drain_rpq_loads : Drain out loads from the rpq\n // : If miss was misspeculated, go to s_invalid\n // s_wb_req : Write back the evicted cache line\n // s_wb_resp : Finish writing back the evicted cache line\n // s_meta_write_req : Write the metadata for new cache lne\n // s_meta_write_resp :\n\n val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)\n val state = RegInit(s_invalid)\n\n val req = Reg(new BoomDCacheReqInternal)\n val req_idx = req.addr(untagBits-1, blockOffBits)\n val req_tag = req.addr >> untagBits\n val req_block_addr = (req.addr >> blockOffBits) << blockOffBits\n val req_needs_wb = RegInit(false.B)\n\n val new_coh = RegInit(ClientMetadata.onReset)\n val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)\n val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2\n val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)\n\n // We only accept secondary misses if the original request had sufficient permissions\n val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =\n new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)\n\n val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)\n val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&\n !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses\n\n val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))\n rpq.io.brupdate := io.brupdate\n rpq.io.flush := io.exception\n assert(!(state === s_invalid && !rpq.io.empty))\n\n rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)\n rpq.io.enq.bits := io.req\n rpq.io.deq.ready := false.B\n\n\n val grantack = Reg(Valid(new TLBundleE(edge.bundle)))\n val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))\n val commit_line = Reg(Bool())\n val grant_had_data = Reg(Bool())\n val finish_to_prefetch = Reg(Bool())\n\n // Block probes if a tag write we started is still in the pipeline\n val meta_hazard = RegInit(0.U(2.W))\n when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }\n when (io.meta_write.fire) { meta_hazard := 1.U }\n io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))\n io.idx.valid := state =/= s_invalid\n io.tag.valid := state =/= s_invalid\n io.way.valid := !state.isOneOf(s_invalid, s_prefetch)\n io.idx.bits := req_idx\n io.tag.bits := req_tag\n io.way.bits := req.way_en\n\n io.meta_write.valid := false.B\n io.meta_write.bits := DontCare\n io.req_pri_rdy := false.B\n io.req_sec_rdy := sec_rdy && rpq.io.enq.ready\n io.mem_acquire.valid := false.B\n io.mem_acquire.bits := DontCare\n io.refill.valid := false.B\n io.refill.bits := DontCare\n io.replay.valid := false.B\n io.replay.bits := DontCare\n io.wb_req.valid := false.B\n io.wb_req.bits := DontCare\n io.resp.valid := false.B\n io.resp.bits := DontCare\n io.commit_val := false.B\n io.commit_addr := req.addr\n io.commit_coh := coh_on_grant\n io.meta_read.valid := false.B\n io.meta_read.bits := DontCare\n io.mem_finish.valid := false.B\n io.mem_finish.bits := DontCare\n io.lb_write.valid := false.B\n io.lb_write.bits := DontCare\n io.lb_read.valid := false.B\n io.lb_read.bits := DontCare\n io.mem_grant.ready := false.B\n\n when (io.req_sec_val && io.req_sec_rdy) {\n req.uop.mem_cmd := dirtier_cmd\n when (is_hit_again) {\n new_coh := dirtier_coh\n }\n }\n\n def handle_pri_req(old_state: UInt): UInt = {\n val new_state = WireInit(old_state)\n grantack.valid := false.B\n refill_ctr := 0.U\n assert(rpq.io.enq.ready)\n req := io.req\n val old_coh = io.req.old_meta.coh\n req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back\n when (io.req.tag_match) {\n val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // set dirty bit\n assert(isWrite(io.req.uop.mem_cmd))\n new_coh := coh_on_hit\n new_state := s_drain_rpq\n } .otherwise { // upgrade permissions\n new_coh := old_coh\n new_state := s_refill_req\n }\n } .otherwise { // refill and writeback if necessary\n new_coh := ClientMetadata.onReset\n new_state := s_refill_req\n }\n new_state\n }\n\n when (state === s_invalid) {\n io.req_pri_rdy := true.B\n grant_had_data := false.B\n\n when (io.req_pri_val && io.req_pri_rdy) {\n state := handle_pri_req(state)\n }\n } .elsewhen (state === s_refill_req) {\n io.mem_acquire.valid := true.B\n // TODO: Use AcquirePerm if just doing permissions acquire\n io.mem_acquire.bits := edge.AcquireBlock(\n fromSource = io.id,\n toAddress = Cat(req_tag, req_idx) << blockOffBits,\n lgSize = lgCacheBlockBytes.U,\n growPermissions = grow_param)._2\n when (io.mem_acquire.fire) {\n state := s_refill_resp\n }\n } .elsewhen (state === s_refill_resp) {\n when (edge.hasData(io.mem_grant.bits)) {\n io.mem_grant.ready := io.lb_write.ready\n io.lb_write.valid := io.mem_grant.valid\n io.lb_write.bits.id := io.id\n io.lb_write.bits.offset := refill_address_inc >> rowOffBits\n io.lb_write.bits.data := io.mem_grant.bits.data\n } .otherwise {\n io.mem_grant.ready := true.B\n }\n\n when (io.mem_grant.fire) {\n grant_had_data := edge.hasData(io.mem_grant.bits)\n }\n when (refill_done) {\n grantack.valid := edge.isRequest(io.mem_grant.bits)\n grantack.bits := edge.GrantAck(io.mem_grant.bits)\n state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)\n assert(!(!grant_had_data && req_needs_wb))\n commit_line := false.B\n new_coh := coh_on_grant\n\n }\n } .elsewhen (state === s_drain_rpq_loads) {\n val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&\n !isWrite(rpq.io.deq.bits.uop.mem_cmd) &&\n (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay\n // drain all loads for now\n val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))\n val data = io.lb_resp\n val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))\n val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,\n Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),\n data_word, false.B, wordBytes)\n\n\n rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load\n io.lb_read.valid := rpq.io.deq.valid && drain_load\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits\n\n io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load\n io.resp.bits.uop := rpq.io.deq.bits.uop\n io.resp.bits.data := loadgen.data\n io.resp.bits.is_hella := rpq.io.deq.bits.is_hella\n when (rpq.io.deq.fire) {\n commit_line := true.B\n }\n .elsewhen (rpq.io.empty && !commit_line)\n {\n when (!rpq.io.enq.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := enablePrefetching.B\n }\n } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {\n // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired\n // The prefetcher should consider fetching the next line\n io.commit_val := true.B\n state := s_meta_read\n }\n } .elsewhen (state === s_meta_read) {\n io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)\n io.meta_read.bits.idx := req_idx\n io.meta_read.bits.tag := req_tag\n io.meta_read.bits.way_en := req.way_en\n when (io.meta_read.fire) {\n state := s_meta_resp_1\n }\n } .elsewhen (state === s_meta_resp_1) {\n state := s_meta_resp_2\n } .elsewhen (state === s_meta_resp_2) {\n val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1\n state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read\n Mux(needs_wb, s_meta_clear, s_commit_line))\n } .elsewhen (state === s_meta_clear) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := coh_on_clear\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n\n when (io.meta_write.fire) {\n state := s_wb_req\n }\n } .elsewhen (state === s_wb_req) {\n io.wb_req.valid := true.B\n\n io.wb_req.bits.tag := req.old_meta.tag\n io.wb_req.bits.idx := req_idx\n io.wb_req.bits.param := shrink_param\n io.wb_req.bits.way_en := req.way_en\n io.wb_req.bits.source := io.id\n io.wb_req.bits.voluntary := true.B\n when (io.wb_req.fire) {\n state := s_wb_resp\n }\n } .elsewhen (state === s_wb_resp) {\n when (io.wb_resp) {\n state := s_commit_line\n }\n } .elsewhen (state === s_commit_line) {\n io.lb_read.valid := true.B\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := refill_ctr\n\n io.refill.valid := io.lb_read.fire\n io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)\n io.refill.bits.way_en := req.way_en\n io.refill.bits.wmask := ~(0.U(rowWords.W))\n io.refill.bits.data := io.lb_resp\n when (io.refill.fire) {\n refill_ctr := refill_ctr + 1.U\n when (refill_ctr === (cacheDataBeats - 1).U) {\n state := s_drain_rpq\n }\n }\n } .elsewhen (state === s_drain_rpq) {\n io.replay <> rpq.io.deq\n io.replay.bits.way_en := req.way_en\n io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {\n // Set dirty bit\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)\n assert(is_hit, \"We still don't have permissions for this store\")\n new_coh := coh_on_hit\n }\n when (rpq.io.empty && !rpq.io.enq.valid) {\n state := s_meta_write_req\n }\n } .elsewhen (state === s_meta_write_req) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := new_coh\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n when (io.meta_write.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := false.B\n }\n } .elsewhen (state === s_mem_finish_1) {\n io.mem_finish.valid := grantack.valid\n io.mem_finish.bits := grantack.bits\n when (io.mem_finish.fire || !grantack.valid) {\n grantack.valid := false.B\n state := s_mem_finish_2\n }\n } .elsewhen (state === s_mem_finish_2) {\n state := Mux(finish_to_prefetch, s_prefetch, s_invalid)\n } .elsewhen (state === s_prefetch) {\n io.req_pri_rdy := true.B\n when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {\n state := s_invalid\n } .elsewhen (io.req_sec_val && io.req_sec_rdy) {\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // Proceed with refill\n new_coh := coh_on_hit\n state := s_meta_read\n } .otherwise { // Reacquire this line\n new_coh := ClientMetadata.onReset\n state := s_refill_req\n }\n } .elsewhen (io.req_pri_val && io.req_pri_rdy) {\n grant_had_data := false.B\n state := handle_pri_req(state)\n }\n }\n}\n\nclass BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new BoomDCacheReq))\n val resp = Decoupled(new BoomDCacheResp)\n val mem_access = Decoupled(new TLBundleA(edge.bundle))\n val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))\n\n // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative\n })\n\n def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)\n\n def wordFromBeat(addr: UInt, dat: UInt) = {\n val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))\n (dat >> shift)(wordBits-1, 0)\n }\n\n val req = Reg(new BoomDCacheReq)\n val grant_word = Reg(UInt(wordBits.W))\n\n val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)\n\n val state = RegInit(s_idle)\n io.req.ready := state === s_idle\n\n val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)\n\n val a_source = id.U\n val a_address = req.addr\n val a_size = req.uop.mem_size\n val a_data = Fill(beatWords, req.data)\n\n val get = edge.Get(a_source, a_address, a_size)._2\n val put = edge.Put(a_source, a_address, a_size, a_data)._2\n val atomics = if (edge.manager.anySupportLogical) {\n MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(\n M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,\n M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,\n M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,\n M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,\n M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,\n M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,\n M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,\n M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,\n M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))\n } else {\n // If no managers support atomics, assert fail if processor asks for them\n assert(state === s_idle || !isAMO(req.uop.mem_cmd))\n (0.U).asTypeOf(new TLBundleA(edge.bundle))\n }\n assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n\n io.mem_access.valid := state === s_mem_access\n io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))\n\n val send_resp = isRead(req.uop.mem_cmd)\n\n io.resp.valid := (state === s_resp) && send_resp\n io.resp.bits.is_hella := req.is_hella\n io.resp.bits.uop := req.uop\n io.resp.bits.data := loadgen.data\n\n when (io.req.fire) {\n req := io.req.bits\n state := s_mem_access\n }\n when (io.mem_access.fire) {\n state := s_mem_ack\n }\n when (state === s_mem_ack && io.mem_ack.valid) {\n state := s_resp\n when (isRead(req.uop.mem_cmd)) {\n grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)\n }\n }\n when (state === s_resp) {\n when (!send_resp || io.resp.fire) {\n state := s_idle\n }\n }\n}\n\nclass LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val offset = UInt(log2Ceil(cacheDataBeats).W)\n def lb_addr = Cat(id, offset)\n}\n\nclass LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)\n{\n val data = UInt(encRowBits.W)\n}\n\nclass LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe\n val req_is_probe = Input(Vec(memWidth, Bool()))\n val resp = Decoupled(new BoomDCacheResp)\n val secondary_miss = Output(Vec(memWidth, Bool()))\n val block_hit = Output(Vec(memWidth, Bool()))\n\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val refill = Decoupled(new L1DataWriteReq)\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val replay = Decoupled(new BoomDCacheReqInternal)\n val prefetch = Decoupled(new BoomDCacheReq)\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence\n\n val wb_resp = Input(Bool())\n\n val fence_rdy = Output(Bool())\n val probe_rdy = Output(Bool())\n })\n\n val req_idx = OHToUInt(io.req.map(_.valid))\n val req = io.req(req_idx)\n val req_is_probe = io.req_is_probe(0)\n\n for (w <- 0 until memWidth)\n io.req(w).ready := false.B\n\n val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)\n else Module(new NullPrefetcher)\n\n io.prefetch <> prefetcher.io.prefetch\n\n\n val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)\n\n // --------------------\n // The MSHR SDQ\n val sdq_val = RegInit(0.U(cfg.nSDQ.W))\n val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))\n val sdq_rdy = !sdq_val.andR\n val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)\n val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))\n\n when (sdq_enq) {\n sdq(sdq_alloc_id) := req.bits.data\n }\n\n // --------------------\n // The LineBuffer Data\n // Holds refilling lines, prefetched lines\n val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))\n val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))\n val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))\n\n lb_read_arb.io.out.ready := false.B\n lb_write_arb.io.out.ready := true.B\n\n val lb_read_data = WireInit(0.U(encRowBits.W))\n when (lb_write_arb.io.out.fire) {\n lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)\n } .otherwise {\n lb_read_arb.io.out.ready := true.B\n when (lb_read_arb.io.out.fire) {\n lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)\n }\n }\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n\n\n\n val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n\n val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))\n val idx_match = widthMap(w => idx_matches(w).reduce(_||_))\n val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))\n\n val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))\n\n val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))\n val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))\n val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))\n val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))\n val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))\n val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))\n\n val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))\n val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))\n val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))\n\n var sec_rdy = false.B\n\n io.fence_rdy := true.B\n io.probe_rdy := true.B\n io.mem_grant.ready := false.B\n\n val mshr_alloc_idx = Wire(UInt())\n val pri_rdy = WireInit(false.B)\n val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)\n val mshrs = (0 until cfg.nMSHRs) map { i =>\n val mshr = Module(new BoomMSHR)\n mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)\n\n for (w <- 0 until memWidth) {\n idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)\n tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits\n way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en\n }\n wb_tag_list(i) := mshr.io.wb_req.bits.tag\n\n\n\n mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val\n when (i.U === mshr_alloc_idx) {\n pri_rdy := mshr.io.req_pri_rdy\n }\n\n mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable\n mshr.io.req := req.bits\n mshr.io.req_is_probe := req_is_probe\n mshr.io.req.sdq_id := sdq_alloc_id\n\n // Clear because of a FENCE, a request to the same idx as a prefetched line,\n // a probe to that prefetched line, all mshrs are in use\n mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||\n (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||\n (req_is_probe && idx_matches(req_idx)(i)))\n mshr.io.brupdate := io.brupdate\n mshr.io.exception := io.exception\n mshr.io.rob_pnr_idx := io.rob_pnr_idx\n mshr.io.rob_head_idx := io.rob_head_idx\n\n mshr.io.prober_state := io.prober_state\n\n mshr.io.wb_resp := io.wb_resp\n\n meta_write_arb.io.in(i) <> mshr.io.meta_write\n meta_read_arb.io.in(i) <> mshr.io.meta_read\n mshr.io.meta_resp := io.meta_resp\n wb_req_arb.io.in(i) <> mshr.io.wb_req\n replay_arb.io.in(i) <> mshr.io.replay\n refill_arb.io.in(i) <> mshr.io.refill\n\n lb_read_arb.io.in(i) <> mshr.io.lb_read\n mshr.io.lb_resp := lb_read_data\n lb_write_arb.io.in(i) <> mshr.io.lb_write\n\n commit_vals(i) := mshr.io.commit_val\n commit_addrs(i) := mshr.io.commit_addr\n commit_cohs(i) := mshr.io.commit_coh\n\n mshr.io.mem_grant.valid := false.B\n mshr.io.mem_grant.bits := DontCare\n when (io.mem_grant.bits.source === i.U) {\n mshr.io.mem_grant <> io.mem_grant\n }\n\n sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)\n resp_arb.io.in(i) <> mshr.io.resp\n\n when (!mshr.io.req_pri_rdy) {\n io.fence_rdy := false.B\n }\n for (w <- 0 until memWidth) {\n when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {\n io.probe_rdy := false.B\n }\n }\n\n mshr\n }\n\n // Try to round-robin the MSHRs\n val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))\n mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))\n when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }\n\n\n\n io.meta_write <> meta_write_arb.io.out\n io.meta_read <> meta_read_arb.io.out\n io.wb_req <> wb_req_arb.io.out\n\n val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))\n\n\n var mmio_rdy = false.B\n\n val mmios = (0 until nIOMSHRs) map { i =>\n val id = cfg.nMSHRs + 1 + i // +1 for wb unit\n val mshr = Module(new BoomIOMSHR(id))\n\n mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready\n mmio_alloc_arb.io.in(i).bits := DontCare\n mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready\n mshr.io.req.bits := req.bits\n\n mmio_rdy = mmio_rdy || mshr.io.req.ready\n\n mshr.io.mem_ack.bits := io.mem_grant.bits\n mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U\n when (io.mem_grant.bits.source === id.U) {\n io.mem_grant.ready := true.B\n }\n\n resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp\n when (!mshr.io.req.ready) {\n io.fence_rdy := false.B\n }\n mshr\n }\n\n mmio_alloc_arb.io.out.ready := req.valid && !cacheable\n\n TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))\n TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))\n\n val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))\n respq.io.brupdate := io.brupdate\n respq.io.flush := io.exception\n respq.io.enq <> resp_arb.io.out\n io.resp <> respq.io.deq\n\n for (w <- 0 until memWidth) {\n io.req(w).ready := (w.U === req_idx) &&\n Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))\n io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)\n io.block_hit(w) := idx_match(w) && tag_match(w)\n }\n io.refill <> refill_arb.io.out\n\n val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)\n\n io.replay <> replay_arb.io.out\n io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)\n\n when (io.replay.valid || sdq_enq) {\n sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |\n PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)\n }\n\n prefetcher.io.mshr_avail := RegNext(pri_rdy)\n prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))\n prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))\n prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))\n}", + "response": "module BoomIOMSHR(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_iw_p1_poisoned,\n input io_req_bits_uop_iw_p2_poisoned,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [39:0] io_req_bits_addr,\n input [63:0] io_req_bits_data,\n input io_req_bits_is_hella,\n input io_resp_ready,\n output io_resp_valid,\n output [6:0] io_resp_bits_uop_uopc,\n output [31:0] io_resp_bits_uop_inst,\n output [31:0] io_resp_bits_uop_debug_inst,\n output io_resp_bits_uop_is_rvc,\n output [39:0] io_resp_bits_uop_debug_pc,\n output [2:0] io_resp_bits_uop_iq_type,\n output [9:0] io_resp_bits_uop_fu_code,\n output [3:0] io_resp_bits_uop_ctrl_br_type,\n output [1:0] io_resp_bits_uop_ctrl_op1_sel,\n output [2:0] io_resp_bits_uop_ctrl_op2_sel,\n output [2:0] io_resp_bits_uop_ctrl_imm_sel,\n output [4:0] io_resp_bits_uop_ctrl_op_fcn,\n output io_resp_bits_uop_ctrl_fcn_dw,\n output [2:0] io_resp_bits_uop_ctrl_csr_cmd,\n output io_resp_bits_uop_ctrl_is_load,\n output io_resp_bits_uop_ctrl_is_sta,\n output io_resp_bits_uop_ctrl_is_std,\n output [1:0] io_resp_bits_uop_iw_state,\n output io_resp_bits_uop_iw_p1_poisoned,\n output io_resp_bits_uop_iw_p2_poisoned,\n output io_resp_bits_uop_is_br,\n output io_resp_bits_uop_is_jalr,\n output io_resp_bits_uop_is_jal,\n output io_resp_bits_uop_is_sfb,\n output [7:0] io_resp_bits_uop_br_mask,\n output [2:0] io_resp_bits_uop_br_tag,\n output [3:0] io_resp_bits_uop_ftq_idx,\n output io_resp_bits_uop_edge_inst,\n output [5:0] io_resp_bits_uop_pc_lob,\n output io_resp_bits_uop_taken,\n output [19:0] io_resp_bits_uop_imm_packed,\n output [11:0] io_resp_bits_uop_csr_addr,\n output [4:0] io_resp_bits_uop_rob_idx,\n output [2:0] io_resp_bits_uop_ldq_idx,\n output [2:0] io_resp_bits_uop_stq_idx,\n output [1:0] io_resp_bits_uop_rxq_idx,\n output [5:0] io_resp_bits_uop_pdst,\n output [5:0] io_resp_bits_uop_prs1,\n output [5:0] io_resp_bits_uop_prs2,\n output [5:0] io_resp_bits_uop_prs3,\n output [3:0] io_resp_bits_uop_ppred,\n output io_resp_bits_uop_prs1_busy,\n output io_resp_bits_uop_prs2_busy,\n output io_resp_bits_uop_prs3_busy,\n output io_resp_bits_uop_ppred_busy,\n output [5:0] io_resp_bits_uop_stale_pdst,\n output io_resp_bits_uop_exception,\n output [63:0] io_resp_bits_uop_exc_cause,\n output io_resp_bits_uop_bypassable,\n output [4:0] io_resp_bits_uop_mem_cmd,\n output [1:0] io_resp_bits_uop_mem_size,\n output io_resp_bits_uop_mem_signed,\n output io_resp_bits_uop_is_fence,\n output io_resp_bits_uop_is_fencei,\n output io_resp_bits_uop_is_amo,\n output io_resp_bits_uop_uses_ldq,\n output io_resp_bits_uop_uses_stq,\n output io_resp_bits_uop_is_sys_pc2epc,\n output io_resp_bits_uop_is_unique,\n output io_resp_bits_uop_flush_on_commit,\n output io_resp_bits_uop_ldst_is_rs1,\n output [5:0] io_resp_bits_uop_ldst,\n output [5:0] io_resp_bits_uop_lrs1,\n output [5:0] io_resp_bits_uop_lrs2,\n output [5:0] io_resp_bits_uop_lrs3,\n output io_resp_bits_uop_ldst_val,\n output [1:0] io_resp_bits_uop_dst_rtype,\n output [1:0] io_resp_bits_uop_lrs1_rtype,\n output [1:0] io_resp_bits_uop_lrs2_rtype,\n output io_resp_bits_uop_frs3_en,\n output io_resp_bits_uop_fp_val,\n output io_resp_bits_uop_fp_single,\n output io_resp_bits_uop_xcpt_pf_if,\n output io_resp_bits_uop_xcpt_ae_if,\n output io_resp_bits_uop_xcpt_ma_if,\n output io_resp_bits_uop_bp_debug_if,\n output io_resp_bits_uop_bp_xcpt_if,\n output [1:0] io_resp_bits_uop_debug_fsrc,\n output [1:0] io_resp_bits_uop_debug_tsrc,\n output [63:0] io_resp_bits_data,\n output io_resp_bits_is_hella,\n input io_mem_access_ready,\n output io_mem_access_valid,\n output [2:0] io_mem_access_bits_opcode,\n output [2:0] io_mem_access_bits_param,\n output [3:0] io_mem_access_bits_size,\n output [1:0] io_mem_access_bits_source,\n output [31:0] io_mem_access_bits_address,\n output [7:0] io_mem_access_bits_mask,\n output [63:0] io_mem_access_bits_data,\n input io_mem_ack_valid,\n input [63:0] io_mem_ack_bits_data\n);\n\n reg [6:0] req_uop_uopc;\n reg [31:0] req_uop_inst;\n reg [31:0] req_uop_debug_inst;\n reg req_uop_is_rvc;\n reg [39:0] req_uop_debug_pc;\n reg [2:0] req_uop_iq_type;\n reg [9:0] req_uop_fu_code;\n reg [3:0] req_uop_ctrl_br_type;\n reg [1:0] req_uop_ctrl_op1_sel;\n reg [2:0] req_uop_ctrl_op2_sel;\n reg [2:0] req_uop_ctrl_imm_sel;\n reg [4:0] req_uop_ctrl_op_fcn;\n reg req_uop_ctrl_fcn_dw;\n reg [2:0] req_uop_ctrl_csr_cmd;\n reg req_uop_ctrl_is_load;\n reg req_uop_ctrl_is_sta;\n reg req_uop_ctrl_is_std;\n reg [1:0] req_uop_iw_state;\n reg req_uop_iw_p1_poisoned;\n reg req_uop_iw_p2_poisoned;\n reg req_uop_is_br;\n reg req_uop_is_jalr;\n reg req_uop_is_jal;\n reg req_uop_is_sfb;\n reg [7:0] req_uop_br_mask;\n reg [2:0] req_uop_br_tag;\n reg [3:0] req_uop_ftq_idx;\n reg req_uop_edge_inst;\n reg [5:0] req_uop_pc_lob;\n reg req_uop_taken;\n reg [19:0] req_uop_imm_packed;\n reg [11:0] req_uop_csr_addr;\n reg [4:0] req_uop_rob_idx;\n reg [2:0] req_uop_ldq_idx;\n reg [2:0] req_uop_stq_idx;\n reg [1:0] req_uop_rxq_idx;\n reg [5:0] req_uop_pdst;\n reg [5:0] req_uop_prs1;\n reg [5:0] req_uop_prs2;\n reg [5:0] req_uop_prs3;\n reg [3:0] req_uop_ppred;\n reg req_uop_prs1_busy;\n reg req_uop_prs2_busy;\n reg req_uop_prs3_busy;\n reg req_uop_ppred_busy;\n reg [5:0] req_uop_stale_pdst;\n reg req_uop_exception;\n reg [63:0] req_uop_exc_cause;\n reg req_uop_bypassable;\n reg [4:0] req_uop_mem_cmd;\n reg [1:0] req_uop_mem_size;\n reg req_uop_mem_signed;\n reg req_uop_is_fence;\n reg req_uop_is_fencei;\n reg req_uop_is_amo;\n reg req_uop_uses_ldq;\n reg req_uop_uses_stq;\n reg req_uop_is_sys_pc2epc;\n reg req_uop_is_unique;\n reg req_uop_flush_on_commit;\n reg req_uop_ldst_is_rs1;\n reg [5:0] req_uop_ldst;\n reg [5:0] req_uop_lrs1;\n reg [5:0] req_uop_lrs2;\n reg [5:0] req_uop_lrs3;\n reg req_uop_ldst_val;\n reg [1:0] req_uop_dst_rtype;\n reg [1:0] req_uop_lrs1_rtype;\n reg [1:0] req_uop_lrs2_rtype;\n reg req_uop_frs3_en;\n reg req_uop_fp_val;\n reg req_uop_fp_single;\n reg req_uop_xcpt_pf_if;\n reg req_uop_xcpt_ae_if;\n reg req_uop_xcpt_ma_if;\n reg req_uop_bp_debug_if;\n reg req_uop_bp_xcpt_if;\n reg [1:0] req_uop_debug_fsrc;\n reg [1:0] req_uop_debug_tsrc;\n reg [39:0] req_addr;\n reg [63:0] req_data;\n reg req_is_hella;\n reg [63:0] grant_word;\n reg [1:0] state;\n wire io_req_ready_0 = state == 2'h0;\n wire get_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;\n wire get_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | get_a_mask_sub_sub_size & ~(req_addr[2]);\n wire get_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | get_a_mask_sub_sub_size & req_addr[2];\n wire get_a_mask_sub_size = req_uop_mem_size == 2'h1;\n wire get_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);\n wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | get_a_mask_sub_size & get_a_mask_sub_0_2;\n wire get_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];\n wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | get_a_mask_sub_size & get_a_mask_sub_1_2;\n wire get_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);\n wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | get_a_mask_sub_size & get_a_mask_sub_2_2;\n wire get_a_mask_sub_3_2 = req_addr[2] & req_addr[1];\n wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | get_a_mask_sub_size & get_a_mask_sub_3_2;\n wire put_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;\n wire put_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | put_a_mask_sub_sub_size & ~(req_addr[2]);\n wire put_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | put_a_mask_sub_sub_size & req_addr[2];\n wire put_a_mask_sub_size = req_uop_mem_size == 2'h1;\n wire put_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);\n wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | put_a_mask_sub_size & put_a_mask_sub_0_2;\n wire put_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];\n wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | put_a_mask_sub_size & put_a_mask_sub_1_2;\n wire put_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);\n wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | put_a_mask_sub_size & put_a_mask_sub_2_2;\n wire put_a_mask_sub_3_2 = req_addr[2] & req_addr[1];\n wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | put_a_mask_sub_size & put_a_mask_sub_3_2;\n wire atomics_a_mask_sub_sub_size = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size & req_addr[2];\n wire atomics_a_mask_sub_size = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_0_2;\n wire atomics_a_mask_sub_1_2 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_1_2;\n wire atomics_a_mask_sub_2_2 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_2_2;\n wire atomics_a_mask_sub_3_2 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | atomics_a_mask_sub_size & atomics_a_mask_sub_3_2;\n wire atomics_a_mask_sub_sub_size_1 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_1 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_1 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_1 & req_addr[2];\n wire atomics_a_mask_sub_size_1 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_1 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1;\n wire atomics_a_mask_sub_1_2_1 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1;\n wire atomics_a_mask_sub_2_2_1 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1;\n wire atomics_a_mask_sub_3_2_1 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1;\n wire atomics_a_mask_sub_sub_size_2 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_2 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_2 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_2 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_2 & req_addr[2];\n wire atomics_a_mask_sub_size_2 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_2 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2;\n wire atomics_a_mask_sub_1_2_2 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2;\n wire atomics_a_mask_sub_2_2_2 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2;\n wire atomics_a_mask_sub_3_2_2 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2;\n wire atomics_a_mask_sub_sub_size_3 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_3 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_3 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_3 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_3 & req_addr[2];\n wire atomics_a_mask_sub_size_3 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_3 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3;\n wire atomics_a_mask_sub_1_2_3 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3;\n wire atomics_a_mask_sub_2_2_3 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3;\n wire atomics_a_mask_sub_3_2_3 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3;\n wire atomics_a_mask_sub_sub_size_4 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_4 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_4 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_4 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_4 & req_addr[2];\n wire atomics_a_mask_sub_size_4 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_4 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4;\n wire atomics_a_mask_sub_1_2_4 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4;\n wire atomics_a_mask_sub_2_2_4 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4;\n wire atomics_a_mask_sub_3_2_4 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4;\n wire atomics_a_mask_sub_sub_size_5 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_5 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_5 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_5 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_5 & req_addr[2];\n wire atomics_a_mask_sub_size_5 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_5 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5;\n wire atomics_a_mask_sub_1_2_5 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5;\n wire atomics_a_mask_sub_2_2_5 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5;\n wire atomics_a_mask_sub_3_2_5 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5;\n wire atomics_a_mask_sub_sub_size_6 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_6 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_6 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_6 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_6 & req_addr[2];\n wire atomics_a_mask_sub_size_6 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_6 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6;\n wire atomics_a_mask_sub_1_2_6 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6;\n wire atomics_a_mask_sub_2_2_6 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6;\n wire atomics_a_mask_sub_3_2_6 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6;\n wire atomics_a_mask_sub_sub_size_7 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_7 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_7 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_7 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_7 & req_addr[2];\n wire atomics_a_mask_sub_size_7 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_7 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7;\n wire atomics_a_mask_sub_1_2_7 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7;\n wire atomics_a_mask_sub_2_2_7 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7;\n wire atomics_a_mask_sub_3_2_7 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7;\n wire atomics_a_mask_sub_sub_size_8 = req_uop_mem_size == 2'h2;\n wire atomics_a_mask_sub_sub_0_1_8 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_8 & ~(req_addr[2]);\n wire atomics_a_mask_sub_sub_1_1_8 = (&req_uop_mem_size) | atomics_a_mask_sub_sub_size_8 & req_addr[2];\n wire atomics_a_mask_sub_size_8 = req_uop_mem_size == 2'h1;\n wire atomics_a_mask_sub_0_2_8 = ~(req_addr[2]) & ~(req_addr[1]);\n wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8;\n wire atomics_a_mask_sub_1_2_8 = ~(req_addr[2]) & req_addr[1];\n wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8;\n wire atomics_a_mask_sub_2_2_8 = req_addr[2] & ~(req_addr[1]);\n wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8;\n wire atomics_a_mask_sub_3_2_8 = req_addr[2] & req_addr[1];\n wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8;\n wire _send_resp_T_7 = req_uop_mem_cmd == 5'h4;\n wire _send_resp_T_8 = req_uop_mem_cmd == 5'h9;\n wire _send_resp_T_9 = req_uop_mem_cmd == 5'hA;\n wire _send_resp_T_10 = req_uop_mem_cmd == 5'hB;\n wire _GEN = _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7;\n wire _send_resp_T_14 = req_uop_mem_cmd == 5'h8;\n wire _send_resp_T_15 = req_uop_mem_cmd == 5'hC;\n wire _send_resp_T_16 = req_uop_mem_cmd == 5'hD;\n wire _send_resp_T_17 = req_uop_mem_cmd == 5'hE;\n wire _send_resp_T_18 = req_uop_mem_cmd == 5'hF;\n wire _GEN_0 = _send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14;\n wire [7:0] atomics_mask =\n _send_resp_T_18\n ? {atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & req_addr[0], atomics_a_mask_sub_3_1_8 | atomics_a_mask_sub_3_2_8 & ~(req_addr[0]), atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & req_addr[0], atomics_a_mask_sub_2_1_8 | atomics_a_mask_sub_2_2_8 & ~(req_addr[0]), atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & req_addr[0], atomics_a_mask_sub_1_1_8 | atomics_a_mask_sub_1_2_8 & ~(req_addr[0]), atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & req_addr[0], atomics_a_mask_sub_0_1_8 | atomics_a_mask_sub_0_2_8 & ~(req_addr[0])}\n : _send_resp_T_17\n ? {atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & req_addr[0], atomics_a_mask_sub_3_1_7 | atomics_a_mask_sub_3_2_7 & ~(req_addr[0]), atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & req_addr[0], atomics_a_mask_sub_2_1_7 | atomics_a_mask_sub_2_2_7 & ~(req_addr[0]), atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & req_addr[0], atomics_a_mask_sub_1_1_7 | atomics_a_mask_sub_1_2_7 & ~(req_addr[0]), atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & req_addr[0], atomics_a_mask_sub_0_1_7 | atomics_a_mask_sub_0_2_7 & ~(req_addr[0])}\n : _send_resp_T_16\n ? {atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & req_addr[0], atomics_a_mask_sub_3_1_6 | atomics_a_mask_sub_3_2_6 & ~(req_addr[0]), atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & req_addr[0], atomics_a_mask_sub_2_1_6 | atomics_a_mask_sub_2_2_6 & ~(req_addr[0]), atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & req_addr[0], atomics_a_mask_sub_1_1_6 | atomics_a_mask_sub_1_2_6 & ~(req_addr[0]), atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & req_addr[0], atomics_a_mask_sub_0_1_6 | atomics_a_mask_sub_0_2_6 & ~(req_addr[0])}\n : _send_resp_T_15\n ? {atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5 & req_addr[0], atomics_a_mask_sub_3_1_5 | atomics_a_mask_sub_3_2_5 & ~(req_addr[0]), atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5 & req_addr[0], atomics_a_mask_sub_2_1_5 | atomics_a_mask_sub_2_2_5 & ~(req_addr[0]), atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5 & req_addr[0], atomics_a_mask_sub_1_1_5 | atomics_a_mask_sub_1_2_5 & ~(req_addr[0]), atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5 & req_addr[0], atomics_a_mask_sub_0_1_5 | atomics_a_mask_sub_0_2_5 & ~(req_addr[0])}\n : _send_resp_T_14\n ? {atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4 & req_addr[0], atomics_a_mask_sub_3_1_4 | atomics_a_mask_sub_3_2_4 & ~(req_addr[0]), atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4 & req_addr[0], atomics_a_mask_sub_2_1_4 | atomics_a_mask_sub_2_2_4 & ~(req_addr[0]), atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4 & req_addr[0], atomics_a_mask_sub_1_1_4 | atomics_a_mask_sub_1_2_4 & ~(req_addr[0]), atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4 & req_addr[0], atomics_a_mask_sub_0_1_4 | atomics_a_mask_sub_0_2_4 & ~(req_addr[0])}\n : _send_resp_T_10\n ? {atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3 & req_addr[0], atomics_a_mask_sub_3_1_3 | atomics_a_mask_sub_3_2_3 & ~(req_addr[0]), atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3 & req_addr[0], atomics_a_mask_sub_2_1_3 | atomics_a_mask_sub_2_2_3 & ~(req_addr[0]), atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3 & req_addr[0], atomics_a_mask_sub_1_1_3 | atomics_a_mask_sub_1_2_3 & ~(req_addr[0]), atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3 & req_addr[0], atomics_a_mask_sub_0_1_3 | atomics_a_mask_sub_0_2_3 & ~(req_addr[0])}\n : _send_resp_T_9 ? {atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2 & req_addr[0], atomics_a_mask_sub_3_1_2 | atomics_a_mask_sub_3_2_2 & ~(req_addr[0]), atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2 & req_addr[0], atomics_a_mask_sub_2_1_2 | atomics_a_mask_sub_2_2_2 & ~(req_addr[0]), atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2 & req_addr[0], atomics_a_mask_sub_1_1_2 | atomics_a_mask_sub_1_2_2 & ~(req_addr[0]), atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2 & req_addr[0], atomics_a_mask_sub_0_1_2 | atomics_a_mask_sub_0_2_2 & ~(req_addr[0])} : _send_resp_T_8 ? {atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1 & req_addr[0], atomics_a_mask_sub_3_1_1 | atomics_a_mask_sub_3_2_1 & ~(req_addr[0]), atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1 & req_addr[0], atomics_a_mask_sub_2_1_1 | atomics_a_mask_sub_2_2_1 & ~(req_addr[0]), atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1 & req_addr[0], atomics_a_mask_sub_1_1_1 | atomics_a_mask_sub_1_2_1 & ~(req_addr[0]), atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1 & req_addr[0], atomics_a_mask_sub_0_1_1 | atomics_a_mask_sub_0_2_1 & ~(req_addr[0])} : _send_resp_T_7 ? {atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2 & req_addr[0], atomics_a_mask_sub_3_1 | atomics_a_mask_sub_3_2 & ~(req_addr[0]), atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2 & req_addr[0], atomics_a_mask_sub_2_1 | atomics_a_mask_sub_2_2 & ~(req_addr[0]), atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2 & req_addr[0], atomics_a_mask_sub_1_1 | atomics_a_mask_sub_1_2 & ~(req_addr[0]), atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2 & req_addr[0], atomics_a_mask_sub_0_1 | atomics_a_mask_sub_0_2 & ~(req_addr[0])} : 8'h0;\n wire io_mem_access_valid_0 = state == 2'h1;\n wire _io_mem_access_bits_T_16 = _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;\n wire _send_resp_T = req_uop_mem_cmd == 5'h0;\n wire _send_resp_T_1 = req_uop_mem_cmd == 5'h10;\n wire _send_resp_T_2 = req_uop_mem_cmd == 5'h6;\n wire _send_resp_T_3 = req_uop_mem_cmd == 5'h7;\n wire _io_mem_access_bits_T_41 = _send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;\n wire _GEN_1 = ~_io_mem_access_bits_T_16 | _send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7;\n wire send_resp = _send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _send_resp_T_7 | _send_resp_T_8 | _send_resp_T_9 | _send_resp_T_10 | _send_resp_T_14 | _send_resp_T_15 | _send_resp_T_16 | _send_resp_T_17 | _send_resp_T_18;\n wire io_resp_valid_0 = (&state) & send_resp;\n wire [31:0] io_resp_bits_data_zeroed = req_addr[2] ? grant_word[63:32] : grant_word[31:0];\n wire [15:0] io_resp_bits_data_zeroed_1 = req_addr[1] ? io_resp_bits_data_zeroed[31:16] : io_resp_bits_data_zeroed[15:0];\n wire [7:0] io_resp_bits_data_zeroed_2 = req_addr[0] ? io_resp_bits_data_zeroed_1[15:8] : io_resp_bits_data_zeroed_1[7:0];\n wire _GEN_2 = io_req_ready_0 & io_req_valid;\n wire _GEN_3 = state == 2'h2 & io_mem_ack_valid;\n always @(posedge clock) begin\n if (_GEN_2) begin\n req_uop_uopc <= io_req_bits_uop_uopc;\n req_uop_inst <= io_req_bits_uop_inst;\n req_uop_debug_inst <= io_req_bits_uop_debug_inst;\n req_uop_is_rvc <= io_req_bits_uop_is_rvc;\n req_uop_debug_pc <= io_req_bits_uop_debug_pc;\n req_uop_iq_type <= io_req_bits_uop_iq_type;\n req_uop_fu_code <= io_req_bits_uop_fu_code;\n req_uop_ctrl_br_type <= io_req_bits_uop_ctrl_br_type;\n req_uop_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel;\n req_uop_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel;\n req_uop_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel;\n req_uop_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn;\n req_uop_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw;\n req_uop_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd;\n req_uop_ctrl_is_load <= io_req_bits_uop_ctrl_is_load;\n req_uop_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta;\n req_uop_ctrl_is_std <= io_req_bits_uop_ctrl_is_std;\n req_uop_iw_state <= io_req_bits_uop_iw_state;\n req_uop_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned;\n req_uop_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned;\n req_uop_is_br <= io_req_bits_uop_is_br;\n req_uop_is_jalr <= io_req_bits_uop_is_jalr;\n req_uop_is_jal <= io_req_bits_uop_is_jal;\n req_uop_is_sfb <= io_req_bits_uop_is_sfb;\n req_uop_br_mask <= io_req_bits_uop_br_mask;\n req_uop_br_tag <= io_req_bits_uop_br_tag;\n req_uop_ftq_idx <= io_req_bits_uop_ftq_idx;\n req_uop_edge_inst <= io_req_bits_uop_edge_inst;\n req_uop_pc_lob <= io_req_bits_uop_pc_lob;\n req_uop_taken <= io_req_bits_uop_taken;\n req_uop_imm_packed <= io_req_bits_uop_imm_packed;\n req_uop_csr_addr <= io_req_bits_uop_csr_addr;\n req_uop_rob_idx <= io_req_bits_uop_rob_idx;\n req_uop_ldq_idx <= io_req_bits_uop_ldq_idx;\n req_uop_stq_idx <= io_req_bits_uop_stq_idx;\n req_uop_rxq_idx <= io_req_bits_uop_rxq_idx;\n req_uop_pdst <= io_req_bits_uop_pdst;\n req_uop_prs1 <= io_req_bits_uop_prs1;\n req_uop_prs2 <= io_req_bits_uop_prs2;\n req_uop_prs3 <= io_req_bits_uop_prs3;\n req_uop_ppred <= io_req_bits_uop_ppred;\n req_uop_prs1_busy <= io_req_bits_uop_prs1_busy;\n req_uop_prs2_busy <= io_req_bits_uop_prs2_busy;\n req_uop_prs3_busy <= io_req_bits_uop_prs3_busy;\n req_uop_ppred_busy <= io_req_bits_uop_ppred_busy;\n req_uop_stale_pdst <= io_req_bits_uop_stale_pdst;\n req_uop_exception <= io_req_bits_uop_exception;\n req_uop_exc_cause <= io_req_bits_uop_exc_cause;\n req_uop_bypassable <= io_req_bits_uop_bypassable;\n req_uop_mem_cmd <= io_req_bits_uop_mem_cmd;\n req_uop_mem_size <= io_req_bits_uop_mem_size;\n req_uop_mem_signed <= io_req_bits_uop_mem_signed;\n req_uop_is_fence <= io_req_bits_uop_is_fence;\n req_uop_is_fencei <= io_req_bits_uop_is_fencei;\n req_uop_is_amo <= io_req_bits_uop_is_amo;\n req_uop_uses_ldq <= io_req_bits_uop_uses_ldq;\n req_uop_uses_stq <= io_req_bits_uop_uses_stq;\n req_uop_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc;\n req_uop_is_unique <= io_req_bits_uop_is_unique;\n req_uop_flush_on_commit <= io_req_bits_uop_flush_on_commit;\n req_uop_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1;\n req_uop_ldst <= io_req_bits_uop_ldst;\n req_uop_lrs1 <= io_req_bits_uop_lrs1;\n req_uop_lrs2 <= io_req_bits_uop_lrs2;\n req_uop_lrs3 <= io_req_bits_uop_lrs3;\n req_uop_ldst_val <= io_req_bits_uop_ldst_val;\n req_uop_dst_rtype <= io_req_bits_uop_dst_rtype;\n req_uop_lrs1_rtype <= io_req_bits_uop_lrs1_rtype;\n req_uop_lrs2_rtype <= io_req_bits_uop_lrs2_rtype;\n req_uop_frs3_en <= io_req_bits_uop_frs3_en;\n req_uop_fp_val <= io_req_bits_uop_fp_val;\n req_uop_fp_single <= io_req_bits_uop_fp_single;\n req_uop_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if;\n req_uop_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if;\n req_uop_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if;\n req_uop_bp_debug_if <= io_req_bits_uop_bp_debug_if;\n req_uop_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if;\n req_uop_debug_fsrc <= io_req_bits_uop_debug_fsrc;\n req_uop_debug_tsrc <= io_req_bits_uop_debug_tsrc;\n req_addr <= io_req_bits_addr;\n req_data <= io_req_bits_data;\n req_is_hella <= io_req_bits_is_hella;\n end\n if (_GEN_3 & (_send_resp_T | _send_resp_T_1 | _send_resp_T_2 | _send_resp_T_3 | _GEN | _GEN_0))\n grant_word <= io_mem_ack_bits_data;\n if (reset)\n state <= 2'h0;\n else if ((&state) & (~send_resp | io_resp_ready & io_resp_valid_0))\n state <= 2'h0;\n else if (_GEN_3)\n state <= 2'h3;\n else if (io_mem_access_ready & io_mem_access_valid_0)\n state <= 2'h2;\n else if (_GEN_2)\n state <= 2'h1;\n end\n assign io_req_ready = io_req_ready_0;\n assign io_resp_valid = io_resp_valid_0;\n assign io_resp_bits_uop_uopc = req_uop_uopc;\n assign io_resp_bits_uop_inst = req_uop_inst;\n assign io_resp_bits_uop_debug_inst = req_uop_debug_inst;\n assign io_resp_bits_uop_is_rvc = req_uop_is_rvc;\n assign io_resp_bits_uop_debug_pc = req_uop_debug_pc;\n assign io_resp_bits_uop_iq_type = req_uop_iq_type;\n assign io_resp_bits_uop_fu_code = req_uop_fu_code;\n assign io_resp_bits_uop_ctrl_br_type = req_uop_ctrl_br_type;\n assign io_resp_bits_uop_ctrl_op1_sel = req_uop_ctrl_op1_sel;\n assign io_resp_bits_uop_ctrl_op2_sel = req_uop_ctrl_op2_sel;\n assign io_resp_bits_uop_ctrl_imm_sel = req_uop_ctrl_imm_sel;\n assign io_resp_bits_uop_ctrl_op_fcn = req_uop_ctrl_op_fcn;\n assign io_resp_bits_uop_ctrl_fcn_dw = req_uop_ctrl_fcn_dw;\n assign io_resp_bits_uop_ctrl_csr_cmd = req_uop_ctrl_csr_cmd;\n assign io_resp_bits_uop_ctrl_is_load = req_uop_ctrl_is_load;\n assign io_resp_bits_uop_ctrl_is_sta = req_uop_ctrl_is_sta;\n assign io_resp_bits_uop_ctrl_is_std = req_uop_ctrl_is_std;\n assign io_resp_bits_uop_iw_state = req_uop_iw_state;\n assign io_resp_bits_uop_iw_p1_poisoned = req_uop_iw_p1_poisoned;\n assign io_resp_bits_uop_iw_p2_poisoned = req_uop_iw_p2_poisoned;\n assign io_resp_bits_uop_is_br = req_uop_is_br;\n assign io_resp_bits_uop_is_jalr = req_uop_is_jalr;\n assign io_resp_bits_uop_is_jal = req_uop_is_jal;\n assign io_resp_bits_uop_is_sfb = req_uop_is_sfb;\n assign io_resp_bits_uop_br_mask = req_uop_br_mask;\n assign io_resp_bits_uop_br_tag = req_uop_br_tag;\n assign io_resp_bits_uop_ftq_idx = req_uop_ftq_idx;\n assign io_resp_bits_uop_edge_inst = req_uop_edge_inst;\n assign io_resp_bits_uop_pc_lob = req_uop_pc_lob;\n assign io_resp_bits_uop_taken = req_uop_taken;\n assign io_resp_bits_uop_imm_packed = req_uop_imm_packed;\n assign io_resp_bits_uop_csr_addr = req_uop_csr_addr;\n assign io_resp_bits_uop_rob_idx = req_uop_rob_idx;\n assign io_resp_bits_uop_ldq_idx = req_uop_ldq_idx;\n assign io_resp_bits_uop_stq_idx = req_uop_stq_idx;\n assign io_resp_bits_uop_rxq_idx = req_uop_rxq_idx;\n assign io_resp_bits_uop_pdst = req_uop_pdst;\n assign io_resp_bits_uop_prs1 = req_uop_prs1;\n assign io_resp_bits_uop_prs2 = req_uop_prs2;\n assign io_resp_bits_uop_prs3 = req_uop_prs3;\n assign io_resp_bits_uop_ppred = req_uop_ppred;\n assign io_resp_bits_uop_prs1_busy = req_uop_prs1_busy;\n assign io_resp_bits_uop_prs2_busy = req_uop_prs2_busy;\n assign io_resp_bits_uop_prs3_busy = req_uop_prs3_busy;\n assign io_resp_bits_uop_ppred_busy = req_uop_ppred_busy;\n assign io_resp_bits_uop_stale_pdst = req_uop_stale_pdst;\n assign io_resp_bits_uop_exception = req_uop_exception;\n assign io_resp_bits_uop_exc_cause = req_uop_exc_cause;\n assign io_resp_bits_uop_bypassable = req_uop_bypassable;\n assign io_resp_bits_uop_mem_cmd = req_uop_mem_cmd;\n assign io_resp_bits_uop_mem_size = req_uop_mem_size;\n assign io_resp_bits_uop_mem_signed = req_uop_mem_signed;\n assign io_resp_bits_uop_is_fence = req_uop_is_fence;\n assign io_resp_bits_uop_is_fencei = req_uop_is_fencei;\n assign io_resp_bits_uop_is_amo = req_uop_is_amo;\n assign io_resp_bits_uop_uses_ldq = req_uop_uses_ldq;\n assign io_resp_bits_uop_uses_stq = req_uop_uses_stq;\n assign io_resp_bits_uop_is_sys_pc2epc = req_uop_is_sys_pc2epc;\n assign io_resp_bits_uop_is_unique = req_uop_is_unique;\n assign io_resp_bits_uop_flush_on_commit = req_uop_flush_on_commit;\n assign io_resp_bits_uop_ldst_is_rs1 = req_uop_ldst_is_rs1;\n assign io_resp_bits_uop_ldst = req_uop_ldst;\n assign io_resp_bits_uop_lrs1 = req_uop_lrs1;\n assign io_resp_bits_uop_lrs2 = req_uop_lrs2;\n assign io_resp_bits_uop_lrs3 = req_uop_lrs3;\n assign io_resp_bits_uop_ldst_val = req_uop_ldst_val;\n assign io_resp_bits_uop_dst_rtype = req_uop_dst_rtype;\n assign io_resp_bits_uop_lrs1_rtype = req_uop_lrs1_rtype;\n assign io_resp_bits_uop_lrs2_rtype = req_uop_lrs2_rtype;\n assign io_resp_bits_uop_frs3_en = req_uop_frs3_en;\n assign io_resp_bits_uop_fp_val = req_uop_fp_val;\n assign io_resp_bits_uop_fp_single = req_uop_fp_single;\n assign io_resp_bits_uop_xcpt_pf_if = req_uop_xcpt_pf_if;\n assign io_resp_bits_uop_xcpt_ae_if = req_uop_xcpt_ae_if;\n assign io_resp_bits_uop_xcpt_ma_if = req_uop_xcpt_ma_if;\n assign io_resp_bits_uop_bp_debug_if = req_uop_bp_debug_if;\n assign io_resp_bits_uop_bp_xcpt_if = req_uop_bp_xcpt_if;\n assign io_resp_bits_uop_debug_fsrc = req_uop_debug_fsrc;\n assign io_resp_bits_uop_debug_tsrc = req_uop_debug_tsrc;\n assign io_resp_bits_data = {req_uop_mem_size == 2'h0 ? {56{req_uop_mem_signed & io_resp_bits_data_zeroed_2[7]}} : {req_uop_mem_size == 2'h1 ? {48{req_uop_mem_signed & io_resp_bits_data_zeroed_1[15]}} : {req_uop_mem_size == 2'h2 ? {32{req_uop_mem_signed & io_resp_bits_data_zeroed[31]}} : grant_word[63:32], io_resp_bits_data_zeroed[31:16]}, io_resp_bits_data_zeroed_1[15:8]}, io_resp_bits_data_zeroed_2};\n assign io_resp_bits_is_hella = req_is_hella;\n assign io_mem_access_valid = io_mem_access_valid_0;\n assign io_mem_access_bits_opcode = _io_mem_access_bits_T_16 ? (_GEN_0 ? 3'h2 : _GEN ? 3'h3 : 3'h0) : {_io_mem_access_bits_T_41, 2'h0};\n assign io_mem_access_bits_param = _io_mem_access_bits_T_16 ? (_send_resp_T_18 ? 3'h3 : _send_resp_T_17 ? 3'h2 : _send_resp_T_16 ? 3'h1 : _send_resp_T_15 ? 3'h0 : _send_resp_T_14 ? 3'h4 : _send_resp_T_10 ? 3'h2 : _send_resp_T_9 ? 3'h1 : _send_resp_T_8 | ~_send_resp_T_7 ? 3'h0 : 3'h3) : 3'h0;\n assign io_mem_access_bits_size = _GEN_1 ? {2'h0, req_uop_mem_size} : 4'h0;\n assign io_mem_access_bits_source = _io_mem_access_bits_T_16 ? {2{_send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _GEN}} : 2'h3;\n assign io_mem_access_bits_address = _GEN_1 ? req_addr[31:0] : 32'h0;\n assign io_mem_access_bits_mask = _io_mem_access_bits_T_16 ? atomics_mask : _io_mem_access_bits_T_41 ? {get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & req_addr[0], get_a_mask_sub_3_1 | get_a_mask_sub_3_2 & ~(req_addr[0]), get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & req_addr[0], get_a_mask_sub_2_1 | get_a_mask_sub_2_2 & ~(req_addr[0]), get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & req_addr[0], get_a_mask_sub_1_1 | get_a_mask_sub_1_2 & ~(req_addr[0]), get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & req_addr[0], get_a_mask_sub_0_1 | get_a_mask_sub_0_2 & ~(req_addr[0])} : {put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & req_addr[0], put_a_mask_sub_3_1 | put_a_mask_sub_3_2 & ~(req_addr[0]), put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & req_addr[0], put_a_mask_sub_2_1 | put_a_mask_sub_2_2 & ~(req_addr[0]), put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & req_addr[0], put_a_mask_sub_1_1 | put_a_mask_sub_1_2 & ~(req_addr[0]), put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & req_addr[0], put_a_mask_sub_0_1 | put_a_mask_sub_0_2 & ~(req_addr[0])};\n assign io_mem_access_bits_data = _io_mem_access_bits_T_16 ? (_send_resp_T_18 | _send_resp_T_17 | _send_resp_T_16 | _send_resp_T_15 | _send_resp_T_14 | _send_resp_T_10 | _send_resp_T_9 | _send_resp_T_8 | _send_resp_T_7 ? req_data : 64'h0) : _io_mem_access_bits_T_41 ? 64'h0 : req_data;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module rockettile_icache_data_arrays_1(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [255:0] RW0_wdata,\n output [255:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util._\n\nclass SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val param = UInt(3.W)\n val tag = UInt(params.tagBits.W)\n val set = UInt(params.setBits.W)\n val clients = UInt(params.clientBits.W)\n}\n\nclass SourceB(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new SourceBRequest(params)))\n val b = Decoupled(new TLBundleB(params.inner.bundle))\n })\n\n if (params.firstLevel) {\n // Tie off unused ports\n io.req.ready := true.B\n io.b.valid := false.B\n io.b.bits := DontCare\n } else {\n val remain = RegInit(0.U(params.clientBits.W))\n val remain_set = WireInit(init = 0.U(params.clientBits.W))\n val remain_clr = WireInit(init = 0.U(params.clientBits.W))\n remain := (remain | remain_set) & ~remain_clr\n\n val busy = remain.orR\n val todo = Mux(busy, remain, io.req.bits.clients)\n val next = ~(leftOR(todo) << 1) & todo\n\n if (params.clientBits > 1) {\n params.ccover(PopCount(remain) > 1.U, \"SOURCEB_MULTI_PROBE\", \"Had to probe more than one client\")\n }\n\n assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n\n io.req.ready := !busy\n when (io.req.fire) { remain_set := io.req.bits.clients }\n\n // No restrictions on the type of buffer used here\n val b = Wire(chiselTypeOf(io.b))\n io.b <> params.micro.innerBuf.b(b)\n\n b.valid := busy || io.req.valid\n when (b.fire) { remain_clr := next }\n params.ccover(b.valid && !b.ready, \"SOURCEB_STALL\", \"Backpressured when issuing a probe\")\n\n val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire))\n val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire))\n val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire))\n\n b.bits.opcode := TLMessages.Probe\n b.bits.param := param\n b.bits.size := params.offsetBits .U\n b.bits.source := params.clientSource(next)\n b.bits.address := params.expandAddress(tag, set, 0.U)\n b.bits.mask := ~0.U(params.inner.manager.beatBytes.W)\n b.bits.data := 0.U\n b.bits.corrupt := false.B\n }\n}", + "response": "module SourceB(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [2:0] io_req_bits_param,\n input [12:0] io_req_bits_tag,\n input [9:0] io_req_bits_set,\n input io_req_bits_clients,\n input io_b_ready,\n output io_b_valid,\n output [1:0] io_b_bits_param,\n output [31:0] io_b_bits_address\n);\n\n reg busy;\n wire _param_T_1 = ~busy & io_req_valid;\n wire b_valid = busy | io_req_valid;\n reg [12:0] tag_r;\n wire [12:0] tag = busy ? tag_r : io_req_bits_tag;\n reg [9:0] set_r;\n reg [2:0] param_r;\n always @(posedge clock) begin\n if (reset)\n busy <= 1'h0;\n else\n busy <= (busy | _param_T_1 & io_req_bits_clients) & ~(io_b_ready & b_valid & (busy ? busy : io_req_bits_clients));\n if (_param_T_1) begin\n tag_r <= io_req_bits_tag;\n set_r <= io_req_bits_set;\n param_r <= io_req_bits_param;\n end\n end\n assign io_req_ready = ~busy;\n assign io_b_valid = b_valid;\n assign io_b_bits_param = busy ? param_r[1:0] : io_req_bits_param[1:0];\n assign io_b_bits_address = {tag[12], 3'h0, tag[11:0], busy ? set_r : io_req_bits_set, 6'h0};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\n\nclass CompareRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n val io = IO(new Bundle {\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val signaling = Input(Bool())\n val lt = Output(Bool())\n val eq = Output(Bool())\n val gt = Output(Bool())\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n\n val ordered = ! rawA.isNaN && ! rawB.isNaN\n val bothInfs = rawA.isInf && rawB.isInf\n val bothZeros = rawA.isZero && rawB.isZero\n val eqExps = (rawA.sExp === rawB.sExp)\n val common_ltMags =\n (rawA.sExp < rawB.sExp) || (eqExps && (rawA.sig < rawB.sig))\n val common_eqMags = eqExps && (rawA.sig === rawB.sig)\n\n val ordered_lt =\n ! bothZeros &&\n ((rawA.sign && ! rawB.sign) ||\n (! bothInfs &&\n ((rawA.sign && ! common_ltMags && ! common_eqMags) ||\n (! rawB.sign && common_ltMags))))\n val ordered_eq =\n bothZeros || ((rawA.sign === rawB.sign) && (bothInfs || common_eqMags))\n\n val invalid =\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n (io.signaling && ! ordered)\n\n io.lt := ordered && ordered_lt\n io.eq := ordered && ordered_eq\n io.gt := ordered && ! ordered_lt && ! ordered_eq\n io.exceptionFlags := invalid ## 0.U(4.W)\n}", + "response": "module CompareRecFN(\n input [64:0] io_a,\n input [64:0] io_b,\n input io_signaling,\n output io_lt,\n output io_eq,\n output [4:0] io_exceptionFlags\n);\n\n wire rawA_isNaN = (&(io_a[63:62])) & io_a[61];\n wire rawB_isNaN = (&(io_b[63:62])) & io_b[61];\n wire ordered = ~rawA_isNaN & ~rawB_isNaN;\n wire bothInfs = (&(io_a[63:62])) & ~(io_a[61]) & (&(io_b[63:62])) & ~(io_b[61]);\n wire bothZeros = ~(|(io_a[63:61])) & ~(|(io_b[63:61]));\n wire eqExps = io_a[63:52] == io_b[63:52];\n wire [52:0] _GEN = {|(io_a[63:61]), io_a[51:0]};\n wire [52:0] _GEN_0 = {|(io_b[63:61]), io_b[51:0]};\n wire common_ltMags = $signed({1'h0, io_a[63:52]}) < $signed({1'h0, io_b[63:52]}) | eqExps & _GEN < _GEN_0;\n wire common_eqMags = eqExps & _GEN == _GEN_0;\n assign io_lt = ordered & ~bothZeros & (io_a[64] & ~(io_b[64]) | ~bothInfs & (io_a[64] & ~common_ltMags & ~common_eqMags | ~(io_b[64]) & common_ltMags));\n assign io_eq = ordered & (bothZeros | io_a[64] == io_b[64] & (bothInfs | common_eqMags));\n assign io_exceptionFlags = {rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | io_signaling & ~ordered, 4'h0};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\n\nclass ExpandedInstruction extends Bundle {\n val bits = UInt(32.W)\n val rd = UInt(5.W)\n val rs1 = UInt(5.W)\n val rs2 = UInt(5.W)\n val rs3 = UInt(5.W)\n}\n\nclass RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {\n def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {\n val res = Wire(new ExpandedInstruction)\n res.bits := bits\n res.rd := rd\n res.rs1 := rs1\n res.rs2 := rs2\n res.rs3 := rs3\n res\n }\n\n def rs1p = Cat(1.U(2.W), x(9,7))\n def rs2p = Cat(1.U(2.W), x(4,2))\n def rs2 = x(6,2)\n def rd = x(11,7)\n def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))\n def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))\n def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))\n def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))\n def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))\n def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))\n def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))\n def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))\n def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))\n def addiImm = Cat(Fill(7, x(12)), x(6,2))\n def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))\n def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))\n def shamt = Cat(x(12), x(6,2))\n def x0 = 0.U(5.W)\n def ra = 1.U(5.W)\n def sp = 2.U(5.W)\n\n def q0 = {\n def addi4spn = {\n val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))\n inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)\n }\n def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)\n def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)\n def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)\n def flw = {\n if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)\n else ld\n }\n def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)\n def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)\n def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)\n def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)\n def fsw = {\n if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)\n else sd\n }\n Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)\n }\n\n def q1 = {\n def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)\n def addiw = {\n val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))\n inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)\n }\n def jal = {\n if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)\n else addiw\n }\n def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)\n def addi16sp = {\n val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))\n inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)\n }\n def lui = {\n val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))\n val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)\n Mux(rd === x0 || rd === sp, addi16sp, me)\n }\n def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)\n def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)\n def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)\n def arith = {\n def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))\n def srai = srli | (1 << 30).U\n def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))\n def rtype = {\n val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))\n val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)\n val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))\n Cat(rs2p, rs1p, funct, rs1p, opc) | sub\n }\n inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)\n }\n Seq(addi, jal, li, lui, arith, j, beqz, bnez)\n }\n \n def q2 = {\n val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))\n def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)\n def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)\n def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)\n def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)\n def flwsp = {\n if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)\n else ldsp\n }\n def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)\n def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)\n def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)\n def fswsp = {\n if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)\n else sdsp\n }\n def jalr = {\n val mv = {\n if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0)\n else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)\n }\n val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)\n val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))\n val reserved = Cat(jr >> 7, 0x1F.U(7.W))\n val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)\n val jr_mv = Mux(rs2.orR, mv, jr_reserved)\n val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))\n val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U\n val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)\n val jalr_add = Mux(rs2.orR, add, jalr_ebreak)\n Mux(x(12), jalr_add, jr_mv)\n }\n Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)\n }\n\n def q3 = Seq.fill(8)(passthrough)\n\n def passthrough = inst(x)\n\n def decode = {\n val s = q0 ++ q1 ++ q2 ++ q3\n s(Cat(x(1,0), x(15,13)))\n }\n\n def q0_ill = {\n def allz = !(x(12, 2).orR)\n def fld = if (fLen >= 64) false.B else true.B\n def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B\n def fsd = if (fLen >= 64) false.B else true.B\n def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B\n Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)\n }\n\n def q1_ill = {\n def rd0 = if (xLen == 32) false.B else rd === 0.U\n def immz = !(x(12) | x(6, 2).orR)\n def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U)\n Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B)\n }\n\n def q2_ill = {\n def fldsp = if (fLen >= 64) false.B else true.B\n def rd0 = rd === 0.U\n def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B\n def jr_res = !(x(12 ,2).orR)\n def fsdsp = if (fLen >= 64) false.B else true.B\n def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B\n Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32)\n }\n def q3_ill = Seq.fill(8)(false.B)\n\n def ill = {\n val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill\n s(Cat(x(1,0), x(15,13)))\n }\n}\n\nclass RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters {\n val io = IO(new Bundle {\n val in = Input(UInt(32.W))\n val out = Output(new ExpandedInstruction)\n val rvc = Output(Bool())\n val ill = Output(Bool())\n })\n\n if (usingCompressed) {\n io.rvc := io.in(1,0) =/= 3.U\n val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)\n io.out := decoder.decode\n io.ill := decoder.ill\n } else {\n io.rvc := false.B\n io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough\n io.ill := false.B // only used for RVC\n }\n}", + "response": "module RVCExpander(\n input [31:0] io_in,\n output [31:0] io_out_bits,\n output io_rvc\n);\n\n wire [2:0] _io_out_s_funct_T_2 = {io_in[12], io_in[6:5]};\n wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_2 == 3'h1, 2'h0};\n wire [7:0][2:0] _GEN = {{3'h3}, {3'h2}, {3'h0}, {3'h0}, {3'h7}, {3'h6}, {_io_out_s_funct_T_4}, {_io_out_s_funct_T_4}};\n wire [3:0] _GEN_0 = {4{io_in[12]}};\n wire [6:0] io_out_s_load_opc = (|(io_in[11:7])) ? 7'h3 : 7'h1F;\n wire [4:0] _io_out_T_2 = {io_in[1:0], io_in[15:13]};\n wire [31:0] _io_out_T_42_bits =\n _io_out_T_2 == 5'h14\n ? {7'h0, io_in[12] ? ((|(io_in[6:2])) ? {io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h33} : (|(io_in[11:7])) ? {io_in[6:2], io_in[11:7], 15'hE7} : {io_in[6:3], 1'h1, io_in[11:7], 15'h73}) : {io_in[6:2], (|(io_in[6:2])) ? {8'h0, io_in[11:7], 7'h33} : {io_in[11:7], (|(io_in[11:7])) ? 15'h67 : 15'h1F}}}\n : _io_out_T_2 == 5'h13\n ? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], io_out_s_load_opc}\n : _io_out_T_2 == 5'h12\n ? {4'h0, io_in[3:2], io_in[12], io_in[6:4], 10'h12, io_in[11:7], io_out_s_load_opc}\n : _io_out_T_2 == 5'h11\n ? {3'h0, io_in[4:2], io_in[12], io_in[6:5], 11'h13, io_in[11:7], 7'h7}\n : _io_out_T_2 == 5'h10\n ? {6'h0, io_in[12], io_in[6:2], io_in[11:7], 3'h1, io_in[11:7], 7'h13}\n : _io_out_T_2 == 5'hF\n ? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h1, io_in[11:10], io_in[4:3], io_in[12], 7'h63}\n : _io_out_T_2 == 5'hE\n ? {_GEN_0, io_in[6:5], io_in[2], 7'h1, io_in[9:7], 3'h0, io_in[11:10], io_in[4:3], io_in[12], 7'h63}\n : _io_out_T_2 == 5'hD ? {io_in[12], io_in[8], io_in[10:9], io_in[6], io_in[7], io_in[2], io_in[11], io_in[5:3], {9{io_in[12]}}, 12'h6F} : _io_out_T_2 == 5'hC ? ((&(io_in[11:10])) ? {1'h0, io_in[6:5] == 2'h0, 7'h1, io_in[4:2], 2'h1, io_in[9:7], _GEN[_io_out_s_funct_T_2], 2'h1, io_in[9:7], 3'h3, io_in[12], 3'h3} : {io_in[11:10] == 2'h2 ? {{7{io_in[12]}}, io_in[6:2], 2'h1, io_in[9:7], 5'h1D} : {1'h0, io_in[11:10] == 2'h1, 4'h0, io_in[12], io_in[6:2], 2'h1, io_in[9:7], 5'h15}, io_in[9:7], 7'h13}) : _io_out_T_2 == 5'hB ? {{3{io_in[12]}}, io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? {io_in[4:3], io_in[5], io_in[2], io_in[6], 4'h0, io_in[11:7], 3'h0, io_in[11:7], (|{{7{io_in[12]}}, io_in[6:2]}) ? 7'h13 : 7'h1F} : {{12{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h3, {{7{io_in[12]}}, io_in[6:2]} == 12'h0, 3'h7}} : _io_out_T_2 == 5'hA ? {{7{io_in[12]}}, io_in[6:2], 8'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h9 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 4'h3, io_in[11:7] == 5'h0, 2'h3} : _io_out_T_2 == 5'h8 ? {{7{io_in[12]}}, io_in[6:2], io_in[11:7], 3'h0, io_in[11:7], 7'h13} : _io_out_T_2 == 5'h7 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h23} : _io_out_T_2 == 5'h6 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h23} : _io_out_T_2 == 5'h5 ? {4'h0, io_in[6:5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h3, io_in[11:10], 10'h27} : _io_out_T_2 == 5'h4 ? {5'h0, io_in[5], io_in[12], 2'h1, io_in[4:2], 2'h1, io_in[9:7], 3'h2, io_in[11:10], io_in[6], 9'h3F} : _io_out_T_2 == 5'h3 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h2 ? {5'h0, io_in[5], io_in[12:10], io_in[6], 4'h1, io_in[9:7], 5'h9, io_in[4:2], 7'h3} : _io_out_T_2 == 5'h1 ? {4'h0, io_in[6:5], io_in[12:10], 5'h1, io_in[9:7], 5'hD, io_in[4:2], 7'h7} : {2'h0, io_in[10:7], io_in[12:11], io_in[5], io_in[6], 12'h41, io_in[4:2], (|(io_in[12:5])) ? 7'h13 : 7'h1F};\n assign io_out_bits = (&_io_out_T_2) | _io_out_T_2 == 5'h1E | _io_out_T_2 == 5'h1D | _io_out_T_2 == 5'h1C | _io_out_T_2 == 5'h1B | _io_out_T_2 == 5'h1A | _io_out_T_2 == 5'h19 | _io_out_T_2 == 5'h18 ? io_in : _io_out_T_2 == 5'h17 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h23} : _io_out_T_2 == 5'h16 ? {4'h0, io_in[8:7], io_in[12], io_in[6:2], 8'h12, io_in[11:9], 9'h23} : _io_out_T_2 == 5'h15 ? {3'h0, io_in[9:7], io_in[12], io_in[6:2], 8'h13, io_in[11:10], 10'h27} : _io_out_T_42_bits;\n assign io_rvc = io_in[1:0] != 2'h3;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.uart\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.{IntParam}\n\nimport org.chipsalliance.cde.config.{Parameters, Field}\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.diplomacy._\n\nimport sifive.blocks.devices.uart._\nimport testchipip.serdes.{SerialIO}\n\nobject UARTAdapterConsts {\n val DATA_WIDTH = 8\n}\nimport UARTAdapterConsts._\n\n/**\n * Module to connect with a DUT UART and converts the UART signal to/from DATA_WIDTH\n * packets.\n *\n * @param uartno the uart number\n * @param div the divisor (equal to the clock frequency divided by the baud rate)\n */\nclass UARTAdapter(uartno: Int, div: Int, forcePty: Boolean) extends Module\n{\n val io = IO(new Bundle {\n val uart = Flipped(new UARTPortIO(UARTParams(address = 0))) // We do not support the four wire variant\n })\n\n val sim = Module(new SimUART(uartno, forcePty))\n\n val uartParams = UARTParams(0)\n val txm = Module(new UARTRx(uartParams))\n val txq = Module(new Queue(UInt(uartParams.dataBits.W), uartParams.nTxEntries))\n val rxm = Module(new UARTTx(uartParams))\n val rxq = Module(new Queue(UInt(uartParams.dataBits.W), uartParams.nRxEntries))\n\n sim.io.clock := clock\n sim.io.reset := reset.asBool\n\n txm.io.en := true.B\n txm.io.in := io.uart.txd\n txm.io.div := div.U\n txq.io.enq.valid := txm.io.out.valid\n txq.io.enq.bits := txm.io.out.bits\n when (txq.io.enq.valid) { assert(txq.io.enq.ready) }\n\n rxm.io.en := true.B\n rxm.io.in <> rxq.io.deq\n rxm.io.div := div.U\n rxm.io.nstop := 0.U\n io.uart.rxd := rxm.io.out\n\n sim.io.serial.out.bits := txq.io.deq.bits\n sim.io.serial.out.valid := txq.io.deq.valid\n txq.io.deq.ready := sim.io.serial.out.ready\n\n rxq.io.enq.bits := sim.io.serial.in.bits\n rxq.io.enq.valid := sim.io.serial.in.valid\n sim.io.serial.in.ready := rxq.io.enq.ready && rxq.io.count < (uartParams.nRxEntries - 1).U\n}\n\nobject UARTAdapter {\n var uartno = 0\n def connect(uart: Seq[UARTPortIO], baudrate: BigInt = 115200, forcePty: Boolean = false)(implicit p: Parameters) {\n UARTAdapter.connect(uart, baudrate, p(PeripheryBusKey).dtsFrequency.get, forcePty)\n }\n def connect(uart: Seq[UARTPortIO], baudrate: BigInt, clockFrequency: BigInt, forcePty: Boolean) {\n val div = (clockFrequency / baudrate).toInt\n UARTAdapter.connect(uart, div, forcePty)\n }\n def connect(uart: Seq[UARTPortIO], div: Int, forcePty: Boolean) {\n uart.zipWithIndex.foreach { case (dut_io, i) =>\n val uart_sim = Module(new UARTAdapter(uartno, div, forcePty))\n uart_sim.suggestName(s\"uart_sim_${i}_uartno${uartno}\")\n uart_sim.io.uart.txd := dut_io.txd\n dut_io.rxd := uart_sim.io.uart.rxd\n uartno += 1\n }\n }\n}\n\n\n/**\n * Module to connect to a *.v blackbox that uses DPI calls to interact with the DUT UART.\n *\n * @param uartno the uart number\n */\nclass SimUART(uartno: Int, forcePty: Boolean) extends BlackBox(Map(\n \"UARTNO\" -> IntParam(uartno),\n \"FORCEPTY\" -> IntParam(if (forcePty) 1 else 0)\n)) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val clock = Input(Clock())\n val reset = Input(Bool())\n\n val serial = Flipped(new SerialIO(DATA_WIDTH))\n })\n\n addResource(\"/testchipip/vsrc/SimUART.v\")\n addResource(\"/testchipip/csrc/SimUART.cc\")\n addResource(\"/testchipip/csrc/uart.cc\")\n addResource(\"/testchipip/csrc/uart.h\")\n}", + "response": "module UARTAdapter(\n input clock,\n input reset,\n input io_uart_txd,\n output io_uart_rxd\n);\n\n wire _rxq_io_enq_ready;\n wire _rxq_io_deq_valid;\n wire [7:0] _rxq_io_deq_bits;\n wire [3:0] _rxq_io_count;\n wire _rxm_io_in_ready;\n wire _txq_io_enq_ready;\n wire _txq_io_deq_valid;\n wire [7:0] _txq_io_deq_bits;\n wire _txm_io_out_valid;\n wire [7:0] _txm_io_out_bits;\n wire _sim_serial_in_valid;\n wire [7:0] _sim_serial_in_bits;\n wire _sim_serial_out_ready;\n SimUART #(\n .FORCEPTY(0),\n .UARTNO(0)\n ) sim (\n .clock (clock),\n .reset (reset),\n .serial_in_ready (_rxq_io_enq_ready & _rxq_io_count < 4'h7),\n .serial_in_valid (_sim_serial_in_valid),\n .serial_in_bits (_sim_serial_in_bits),\n .serial_out_ready (_sim_serial_out_ready),\n .serial_out_valid (_txq_io_deq_valid),\n .serial_out_bits (_txq_io_deq_bits)\n );\n UARTRx txm (\n .clock (clock),\n .reset (reset),\n .io_en (1'h1),\n .io_in (io_uart_txd),\n .io_out_valid (_txm_io_out_valid),\n .io_out_bits (_txm_io_out_bits),\n .io_div (16'h364)\n );\n Queue8_UInt8 txq (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_txq_io_enq_ready),\n .io_enq_valid (_txm_io_out_valid),\n .io_enq_bits (_txm_io_out_bits),\n .io_deq_ready (_sim_serial_out_ready),\n .io_deq_valid (_txq_io_deq_valid),\n .io_deq_bits (_txq_io_deq_bits),\n .io_count (/* unused */)\n );\n UARTTx rxm (\n .clock (clock),\n .reset (reset),\n .io_en (1'h1),\n .io_in_ready (_rxm_io_in_ready),\n .io_in_valid (_rxq_io_deq_valid),\n .io_in_bits (_rxq_io_deq_bits),\n .io_out (io_uart_rxd),\n .io_div (16'h364),\n .io_nstop (1'h0)\n );\n Queue8_UInt8 rxq (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_rxq_io_enq_ready),\n .io_enq_valid (_sim_serial_in_valid),\n .io_enq_bits (_sim_serial_in_bits),\n .io_deq_ready (_rxm_io_in_ready),\n .io_deq_valid (_rxq_io_deq_valid),\n .io_deq_bits (_rxq_io_deq_bits),\n .io_count (_rxq_io_count)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Ported from Rocket-Chip\n// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.rocket._\n\nimport boom.v3.common._\nimport boom.v3.exu.BrUpdateInfo\nimport boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc, Transpose}\n\n\nclass BoomWritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new WritebackReq(edge.bundle)))\n val meta_read = Decoupled(new L1MetaReadReq)\n val resp = Output(Bool())\n val idx = Output(Valid(UInt()))\n val data_req = Decoupled(new L1DataReadReq)\n val data_resp = Input(UInt(encRowBits.W))\n val mem_grant = Input(Bool())\n val release = Decoupled(new TLBundleC(edge.bundle))\n val lsu_release = Decoupled(new TLBundleC(edge.bundle))\n })\n\n val req = Reg(new WritebackReq(edge.bundle))\n val s_invalid :: s_fill_buffer :: s_lsu_release :: s_active :: s_grant :: Nil = Enum(5)\n val state = RegInit(s_invalid)\n val r1_data_req_fired = RegInit(false.B)\n val r2_data_req_fired = RegInit(false.B)\n val r1_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))\n val r2_data_req_cnt = Reg(UInt(log2Up(refillCycles+1).W))\n val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W))\n val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)\n val wb_buffer = Reg(Vec(refillCycles, UInt(encRowBits.W)))\n val acked = RegInit(false.B)\n\n io.idx.valid := state =/= s_invalid\n io.idx.bits := req.idx\n io.release.valid := false.B\n io.release.bits := DontCare\n io.req.ready := false.B\n io.meta_read.valid := false.B\n io.meta_read.bits := DontCare\n io.data_req.valid := false.B\n io.data_req.bits := DontCare\n io.resp := false.B\n io.lsu_release.valid := false.B\n io.lsu_release.bits := DontCare\n\n\n val r_address = Cat(req.tag, req.idx) << blockOffBits\n val id = cfg.nMSHRs\n val probeResponse = edge.ProbeAck(\n fromSource = id.U,\n toAddress = r_address,\n lgSize = lgCacheBlockBytes.U,\n reportPermissions = req.param,\n data = wb_buffer(data_req_cnt))\n\n val voluntaryRelease = edge.Release(\n fromSource = id.U,\n toAddress = r_address,\n lgSize = lgCacheBlockBytes.U,\n shrinkPermissions = req.param,\n data = wb_buffer(data_req_cnt))._2\n\n\n when (state === s_invalid) {\n io.req.ready := true.B\n when (io.req.fire) {\n state := s_fill_buffer\n data_req_cnt := 0.U\n req := io.req.bits\n acked := false.B\n }\n } .elsewhen (state === s_fill_buffer) {\n io.meta_read.valid := data_req_cnt < refillCycles.U\n io.meta_read.bits.idx := req.idx\n io.meta_read.bits.tag := req.tag\n\n io.data_req.valid := data_req_cnt < refillCycles.U\n io.data_req.bits.way_en := req.way_en\n io.data_req.bits.addr := (if(refillCycles > 1)\n Cat(req.idx, data_req_cnt(log2Up(refillCycles)-1,0))\n else req.idx) << rowOffBits\n\n r1_data_req_fired := false.B\n r1_data_req_cnt := 0.U\n r2_data_req_fired := r1_data_req_fired\n r2_data_req_cnt := r1_data_req_cnt\n when (io.data_req.fire && io.meta_read.fire) {\n r1_data_req_fired := true.B\n r1_data_req_cnt := data_req_cnt\n data_req_cnt := data_req_cnt + 1.U\n }\n when (r2_data_req_fired) {\n wb_buffer(r2_data_req_cnt) := io.data_resp\n when (r2_data_req_cnt === (refillCycles-1).U) {\n io.resp := true.B\n state := s_lsu_release\n data_req_cnt := 0.U\n }\n }\n } .elsewhen (state === s_lsu_release) {\n io.lsu_release.valid := true.B\n io.lsu_release.bits := probeResponse\n when (io.lsu_release.fire) {\n state := s_active\n }\n } .elsewhen (state === s_active) {\n io.release.valid := data_req_cnt < refillCycles.U\n io.release.bits := Mux(req.voluntary, voluntaryRelease, probeResponse)\n\n when (io.mem_grant) {\n acked := true.B\n }\n when (io.release.fire) {\n data_req_cnt := data_req_cnt + 1.U\n }\n when ((data_req_cnt === (refillCycles-1).U) && io.release.fire) {\n state := Mux(req.voluntary, s_grant, s_invalid)\n }\n } .elsewhen (state === s_grant) {\n when (io.mem_grant) {\n acked := true.B\n }\n when (acked) {\n state := s_invalid\n }\n }\n}\n\nclass BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) {\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new TLBundleB(edge.bundle)))\n val rep = Decoupled(new TLBundleC(edge.bundle))\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_write = Decoupled(new L1MetaWriteReq)\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n val way_en = Input(UInt(nWays.W))\n val wb_rdy = Input(Bool()) // Is writeback unit currently busy? If so need to retry meta read when its done\n val mshr_rdy = Input(Bool()) // Is MSHR ready for this request to proceed?\n val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?\n val block_state = Input(new ClientMetadata())\n val lsu_release = Decoupled(new TLBundleC(edge.bundle))\n\n val state = Output(Valid(UInt(coreMaxAddrBits.W)))\n })\n\n val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::\n s_mshr_resp :: s_lsu_release :: s_release :: s_writeback_req :: s_writeback_resp ::\n s_meta_write :: s_meta_write_resp :: Nil) = Enum(11)\n val state = RegInit(s_invalid)\n\n val req = Reg(new TLBundleB(edge.bundle))\n val req_idx = req.address(idxMSB, idxLSB)\n val req_tag = req.address >> untagBits\n\n val way_en = Reg(UInt())\n val tag_matches = way_en.orR\n val old_coh = Reg(new ClientMetadata)\n val miss_coh = ClientMetadata.onReset\n val reply_coh = Mux(tag_matches, old_coh, miss_coh)\n val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)\n\n io.state.valid := state =/= s_invalid\n io.state.bits := req.address\n\n io.req.ready := state === s_invalid\n io.rep.valid := state === s_release\n io.rep.bits := edge.ProbeAck(req, report_param)\n\n assert(!io.rep.valid || !edge.hasData(io.rep.bits),\n \"ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\")\n\n io.meta_read.valid := state === s_meta_read\n io.meta_read.bits.idx := req_idx\n io.meta_read.bits.tag := req_tag\n io.meta_read.bits.way_en := ~(0.U(nWays.W))\n\n io.meta_write.valid := state === s_meta_write\n io.meta_write.bits.way_en := way_en\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.tag := req_tag\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.data.coh := new_coh\n\n io.wb_req.valid := state === s_writeback_req\n io.wb_req.bits.source := req.source\n io.wb_req.bits.idx := req_idx\n io.wb_req.bits.tag := req_tag\n io.wb_req.bits.param := report_param\n io.wb_req.bits.way_en := way_en\n io.wb_req.bits.voluntary := false.B\n\n\n io.mshr_wb_rdy := !state.isOneOf(s_release, s_writeback_req, s_writeback_resp, s_meta_write, s_meta_write_resp)\n\n io.lsu_release.valid := state === s_lsu_release\n io.lsu_release.bits := edge.ProbeAck(req, report_param)\n\n // state === s_invalid\n when (state === s_invalid) {\n when (io.req.fire) {\n state := s_meta_read\n req := io.req.bits\n }\n } .elsewhen (state === s_meta_read) {\n when (io.meta_read.fire) {\n state := s_meta_resp\n }\n } .elsewhen (state === s_meta_resp) {\n // we need to wait one cycle for the metadata to be read from the array\n state := s_mshr_req\n } .elsewhen (state === s_mshr_req) {\n old_coh := io.block_state\n way_en := io.way_en\n // if the read didn't go through, we need to retry\n state := Mux(io.mshr_rdy && io.wb_rdy, s_mshr_resp, s_meta_read)\n } .elsewhen (state === s_mshr_resp) {\n state := Mux(tag_matches && is_dirty, s_writeback_req, s_lsu_release)\n } .elsewhen (state === s_lsu_release) {\n when (io.lsu_release.fire) {\n state := s_release\n }\n } .elsewhen (state === s_release) {\n when (io.rep.ready) {\n state := Mux(tag_matches, s_meta_write, s_invalid)\n }\n } .elsewhen (state === s_writeback_req) {\n when (io.wb_req.fire) {\n state := s_writeback_resp\n }\n } .elsewhen (state === s_writeback_resp) {\n // wait for the writeback request to finish before updating the metadata\n when (io.wb_req.ready) {\n state := s_meta_write\n }\n } .elsewhen (state === s_meta_write) {\n when (io.meta_write.fire) {\n state := s_meta_write_resp\n }\n } .elsewhen (state === s_meta_write_resp) {\n state := s_invalid\n }\n}\n\nclass BoomL1MetaReadReq(implicit p: Parameters) extends BoomBundle()(p) {\n val req = Vec(memWidth, new L1MetaReadReq)\n}\n\nclass BoomL1DataReadReq(implicit p: Parameters) extends BoomBundle()(p) {\n val req = Vec(memWidth, new L1DataReadReq)\n val valid = Vec(memWidth, Bool())\n}\n\nabstract class AbstractBoomDataArray(implicit p: Parameters) extends BoomModule with HasL1HellaCacheParameters {\n val io = IO(new BoomBundle {\n val read = Input(Vec(memWidth, Valid(new L1DataReadReq)))\n val write = Input(Valid(new L1DataWriteReq))\n val resp = Output(Vec(memWidth, Vec(nWays, Bits(encRowBits.W))))\n val nacks = Output(Vec(memWidth, Bool()))\n })\n\n def pipeMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n}\n\nclass BoomDuplicatedDataArray(implicit p: Parameters) extends AbstractBoomDataArray\n{\n\n val waddr = io.write.bits.addr >> rowOffBits\n for (j <- 0 until memWidth) {\n\n val raddr = io.read(j).bits.addr >> rowOffBits\n for (w <- 0 until nWays) {\n val array = DescribedSRAM(\n name = s\"array_${w}_${j}\",\n desc = \"Non-blocking DCache Data Array\",\n size = nSets * refillCycles,\n data = Vec(rowWords, Bits(encDataBits.W))\n )\n when (io.write.bits.way_en(w) && io.write.valid) {\n val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))\n array.write(waddr, data, io.write.bits.wmask.asBools)\n }\n io.resp(j)(w) := RegNext(array.read(raddr, io.read(j).bits.way_en(w) && io.read(j).valid).asUInt)\n }\n io.nacks(j) := false.B\n }\n}\n\nclass BoomBankedDataArray(implicit p: Parameters) extends AbstractBoomDataArray {\n\n val nBanks = boomParams.numDCacheBanks\n val bankSize = nSets * refillCycles / nBanks\n require (nBanks >= memWidth)\n require (bankSize > 0)\n\n val bankBits = log2Ceil(nBanks)\n val bankOffBits = log2Ceil(rowWords) + log2Ceil(wordBytes)\n val bidxBits = log2Ceil(bankSize)\n val bidxOffBits = bankOffBits + bankBits\n\n //----------------------------------------------------------------------------------------------------\n\n val s0_rbanks = if (nBanks > 1) VecInit(io.read.map(r => (r.bits.addr >> bankOffBits)(bankBits-1,0))) else VecInit(0.U)\n val s0_wbank = if (nBanks > 1) (io.write.bits.addr >> bankOffBits)(bankBits-1,0) else 0.U\n val s0_ridxs = VecInit(io.read.map(r => (r.bits.addr >> bidxOffBits)(bidxBits-1,0)))\n val s0_widx = (io.write.bits.addr >> bidxOffBits)(bidxBits-1,0)\n\n val s0_read_valids = VecInit(io.read.map(_.valid))\n val s0_bank_conflicts = pipeMap(w => (0 until w).foldLeft(false.B)((c,i) => c || io.read(i).valid && s0_rbanks(i) === s0_rbanks(w)))\n val s0_do_bank_read = s0_read_valids zip s0_bank_conflicts map {case (v,c) => v && !c}\n val s0_bank_read_gnts = Transpose(VecInit(s0_rbanks zip s0_do_bank_read map {case (b,d) => VecInit((UIntToOH(b) & Fill(nBanks,d)).asBools)}))\n val s0_bank_write_gnt = (UIntToOH(s0_wbank) & Fill(nBanks, io.write.valid)).asBools\n\n //----------------------------------------------------------------------------------------------------\n\n val s1_rbanks = RegNext(s0_rbanks)\n val s1_ridxs = RegNext(s0_ridxs)\n val s1_read_valids = RegNext(s0_read_valids)\n val s1_pipe_selection = pipeMap(i => VecInit(PriorityEncoderOH(pipeMap(j =>\n if (j < i) s1_read_valids(j) && s1_rbanks(j) === s1_rbanks(i)\n else if (j == i) true.B else false.B))))\n val s1_ridx_match = pipeMap(i => pipeMap(j => if (j < i) s1_ridxs(j) === s1_ridxs(i)\n else if (j == i) true.B else false.B))\n val s1_nacks = pipeMap(w => s1_read_valids(w) && (s1_pipe_selection(w).asUInt & ~s1_ridx_match(w).asUInt).orR)\n val s1_bank_selection = pipeMap(w => Mux1H(s1_pipe_selection(w), s1_rbanks))\n\n //----------------------------------------------------------------------------------------------------\n\n val s2_bank_selection = RegNext(s1_bank_selection)\n val s2_nacks = RegNext(s1_nacks)\n\n for (w <- 0 until nWays) {\n val s2_bank_reads = Reg(Vec(nBanks, Bits(encRowBits.W)))\n\n for (b <- 0 until nBanks) {\n val array = DescribedSRAM(\n name = s\"array_${w}_${b}\",\n desc = \"Non-blocking DCache Data Array\",\n size = bankSize,\n data = Vec(rowWords, Bits(encDataBits.W))\n )\n val ridx = Mux1H(s0_bank_read_gnts(b), s0_ridxs)\n val way_en = Mux1H(s0_bank_read_gnts(b), io.read.map(_.bits.way_en))\n s2_bank_reads(b) := array.read(ridx, way_en(w) && s0_bank_read_gnts(b).reduce(_||_)).asUInt\n\n when (io.write.bits.way_en(w) && s0_bank_write_gnt(b)) {\n val data = VecInit((0 until rowWords) map (i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)))\n array.write(s0_widx, data, io.write.bits.wmask.asBools)\n }\n }\n\n for (i <- 0 until memWidth) {\n io.resp(i)(w) := s2_bank_reads(s2_bank_selection(i))\n }\n }\n\n io.nacks := s2_nacks\n}\n\n/**\n * Top level class wrapping a non-blocking dcache.\n *\n * @param hartid hardware thread for the cache\n */\nclass BoomNonBlockingDCache(staticIdForMetadataUseOnly: Int)(implicit p: Parameters) extends LazyModule\n{\n private val tileParams = p(TileKey)\n protected val cfg = tileParams.dcache.get\n\n protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(\n name = s\"Core ${staticIdForMetadataUseOnly} DCache\",\n sourceId = IdRange(0, 1 max (cfg.nMSHRs + 1)),\n supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))\n\n protected def mmioClientParameters = Seq(TLMasterParameters.v1(\n name = s\"Core ${staticIdForMetadataUseOnly} DCache MMIO\",\n sourceId = IdRange(cfg.nMSHRs + 1, cfg.nMSHRs + 1 + cfg.nMMIOs),\n requestFifo = true))\n\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(\n cacheClientParameters ++ mmioClientParameters,\n minLatency = 1)))\n\n\n lazy val module = new BoomNonBlockingDCacheModule(this)\n\n def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireT || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)\n\n require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, \"CFLUSH_D_L1 instruction requires a D$\")\n}\n\n\nclass BoomDCacheBundle(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p) {\n val lsu = Flipped(new LSUDMemIO)\n}\n\nclass BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModuleImp(outer)\n with HasL1HellaCacheParameters\n with HasBoomCoreParameters\n{\n implicit val edge = outer.node.edges.out(0)\n val (tl_out, _) = outer.node.out(0)\n val io = IO(new BoomDCacheBundle)\n\n private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)\n fifoManagers.foreach { m =>\n require (m.fifoId == fifoManagers.head.fifoId,\n s\"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees ${m.nodePath.map(_.name)}\")\n }\n\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n val t_replay :: t_probe :: t_wb :: t_mshr_meta_read :: t_lsu :: t_prefetch :: Nil = Enum(6)\n\n val wb = Module(new BoomWritebackUnit)\n val prober = Module(new BoomProbeUnit)\n val mshrs = Module(new BoomMSHRFile)\n mshrs.io.clear_all := io.lsu.force_order\n mshrs.io.brupdate := io.lsu.brupdate\n mshrs.io.exception := io.lsu.exception\n mshrs.io.rob_pnr_idx := io.lsu.rob_pnr_idx\n mshrs.io.rob_head_idx := io.lsu.rob_head_idx\n\n // tags\n def onReset = L1Metadata(0.U, ClientMetadata.onReset)\n val meta = Seq.fill(memWidth) { Module(new L1MetadataArray(onReset _)) }\n val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))\n // 0 goes to MSHR refills, 1 goes to prober\n val metaReadArb = Module(new Arbiter(new BoomL1MetaReadReq, 6))\n // 0 goes to MSHR replays, 1 goes to prober, 2 goes to wb, 3 goes to MSHR meta read,\n // 4 goes to pipeline, 5 goes to prefetcher\n\n metaReadArb.io.in := DontCare\n for (w <- 0 until memWidth) {\n meta(w).io.write.valid := metaWriteArb.io.out.fire\n meta(w).io.write.bits := metaWriteArb.io.out.bits\n meta(w).io.read.valid := metaReadArb.io.out.valid\n meta(w).io.read.bits := metaReadArb.io.out.bits.req(w)\n }\n metaReadArb.io.out.ready := meta.map(_.io.read.ready).reduce(_||_)\n metaWriteArb.io.out.ready := meta.map(_.io.write.ready).reduce(_||_)\n\n // data\n val data = Module(if (boomParams.numDCacheBanks == 1) new BoomDuplicatedDataArray else new BoomBankedDataArray)\n val dataWriteArb = Module(new Arbiter(new L1DataWriteReq, 2))\n // 0 goes to pipeline, 1 goes to MSHR refills\n val dataReadArb = Module(new Arbiter(new BoomL1DataReadReq, 3))\n // 0 goes to MSHR replays, 1 goes to wb, 2 goes to pipeline\n dataReadArb.io.in := DontCare\n\n for (w <- 0 until memWidth) {\n data.io.read(w).valid := dataReadArb.io.out.bits.valid(w) && dataReadArb.io.out.valid\n data.io.read(w).bits := dataReadArb.io.out.bits.req(w)\n }\n dataReadArb.io.out.ready := true.B\n\n data.io.write.valid := dataWriteArb.io.out.fire\n data.io.write.bits := dataWriteArb.io.out.bits\n dataWriteArb.io.out.ready := true.B\n\n // ------------\n // New requests\n\n io.lsu.req.ready := metaReadArb.io.in(4).ready && dataReadArb.io.in(2).ready\n metaReadArb.io.in(4).valid := io.lsu.req.valid\n dataReadArb.io.in(2).valid := io.lsu.req.valid\n for (w <- 0 until memWidth) {\n // Tag read for new requests\n metaReadArb.io.in(4).bits.req(w).idx := io.lsu.req.bits(w).bits.addr >> blockOffBits\n metaReadArb.io.in(4).bits.req(w).way_en := DontCare\n metaReadArb.io.in(4).bits.req(w).tag := DontCare\n // Data read for new requests\n dataReadArb.io.in(2).bits.valid(w) := io.lsu.req.bits(w).valid\n dataReadArb.io.in(2).bits.req(w).addr := io.lsu.req.bits(w).bits.addr\n dataReadArb.io.in(2).bits.req(w).way_en := ~0.U(nWays.W)\n }\n\n // ------------\n // MSHR Replays\n val replay_req = Wire(Vec(memWidth, new BoomDCacheReq))\n replay_req := DontCare\n replay_req(0).uop := mshrs.io.replay.bits.uop\n replay_req(0).addr := mshrs.io.replay.bits.addr\n replay_req(0).data := mshrs.io.replay.bits.data\n replay_req(0).is_hella := mshrs.io.replay.bits.is_hella\n mshrs.io.replay.ready := metaReadArb.io.in(0).ready && dataReadArb.io.in(0).ready\n // Tag read for MSHR replays\n // We don't actually need to read the metadata, for replays we already know our way\n metaReadArb.io.in(0).valid := mshrs.io.replay.valid\n metaReadArb.io.in(0).bits.req(0).idx := mshrs.io.replay.bits.addr >> blockOffBits\n metaReadArb.io.in(0).bits.req(0).way_en := DontCare\n metaReadArb.io.in(0).bits.req(0).tag := DontCare\n // Data read for MSHR replays\n dataReadArb.io.in(0).valid := mshrs.io.replay.valid\n dataReadArb.io.in(0).bits.req(0).addr := mshrs.io.replay.bits.addr\n dataReadArb.io.in(0).bits.req(0).way_en := mshrs.io.replay.bits.way_en\n dataReadArb.io.in(0).bits.valid := widthMap(w => (w == 0).B)\n\n // -----------\n // MSHR Meta read\n val mshr_read_req = Wire(Vec(memWidth, new BoomDCacheReq))\n mshr_read_req := DontCare\n mshr_read_req(0).uop := NullMicroOp\n mshr_read_req(0).addr := Cat(mshrs.io.meta_read.bits.tag, mshrs.io.meta_read.bits.idx) << blockOffBits\n mshr_read_req(0).data := DontCare\n mshr_read_req(0).is_hella := false.B\n metaReadArb.io.in(3).valid := mshrs.io.meta_read.valid\n metaReadArb.io.in(3).bits.req(0) := mshrs.io.meta_read.bits\n mshrs.io.meta_read.ready := metaReadArb.io.in(3).ready\n\n\n\n // -----------\n // Write-backs\n val wb_fire = wb.io.meta_read.fire && wb.io.data_req.fire\n val wb_req = Wire(Vec(memWidth, new BoomDCacheReq))\n wb_req := DontCare\n wb_req(0).uop := NullMicroOp\n wb_req(0).addr := Cat(wb.io.meta_read.bits.tag, wb.io.data_req.bits.addr)\n wb_req(0).data := DontCare\n wb_req(0).is_hella := false.B\n // Couple the two decoupled interfaces of the WBUnit's meta_read and data_read\n // Tag read for write-back\n metaReadArb.io.in(2).valid := wb.io.meta_read.valid\n metaReadArb.io.in(2).bits.req(0) := wb.io.meta_read.bits\n wb.io.meta_read.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready\n // Data read for write-back\n dataReadArb.io.in(1).valid := wb.io.data_req.valid\n dataReadArb.io.in(1).bits.req(0) := wb.io.data_req.bits\n dataReadArb.io.in(1).bits.valid := widthMap(w => (w == 0).B)\n wb.io.data_req.ready := metaReadArb.io.in(2).ready && dataReadArb.io.in(1).ready\n assert(!(wb.io.meta_read.fire ^ wb.io.data_req.fire))\n\n // -------\n // Prober\n val prober_fire = prober.io.meta_read.fire\n val prober_req = Wire(Vec(memWidth, new BoomDCacheReq))\n prober_req := DontCare\n prober_req(0).uop := NullMicroOp\n prober_req(0).addr := Cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) << blockOffBits\n prober_req(0).data := DontCare\n prober_req(0).is_hella := false.B\n // Tag read for prober\n metaReadArb.io.in(1).valid := prober.io.meta_read.valid\n metaReadArb.io.in(1).bits.req(0) := prober.io.meta_read.bits\n prober.io.meta_read.ready := metaReadArb.io.in(1).ready\n // Prober does not need to read data array\n\n // -------\n // Prefetcher\n val prefetch_fire = mshrs.io.prefetch.fire\n val prefetch_req = Wire(Vec(memWidth, new BoomDCacheReq))\n prefetch_req := DontCare\n prefetch_req(0) := mshrs.io.prefetch.bits\n // Tag read for prefetch\n metaReadArb.io.in(5).valid := mshrs.io.prefetch.valid\n metaReadArb.io.in(5).bits.req(0).idx := mshrs.io.prefetch.bits.addr >> blockOffBits\n metaReadArb.io.in(5).bits.req(0).way_en := DontCare\n metaReadArb.io.in(5).bits.req(0).tag := DontCare\n mshrs.io.prefetch.ready := metaReadArb.io.in(5).ready\n // Prefetch does not need to read data array\n\n val s0_valid = Mux(io.lsu.req.fire, VecInit(io.lsu.req.bits.map(_.valid)),\n Mux(mshrs.io.replay.fire || wb_fire || prober_fire || prefetch_fire || mshrs.io.meta_read.fire,\n VecInit(1.U(memWidth.W).asBools), VecInit(0.U(memWidth.W).asBools)))\n val s0_req = Mux(io.lsu.req.fire , VecInit(io.lsu.req.bits.map(_.bits)),\n Mux(wb_fire , wb_req,\n Mux(prober_fire , prober_req,\n Mux(prefetch_fire , prefetch_req,\n Mux(mshrs.io.meta_read.fire, mshr_read_req\n , replay_req)))))\n val s0_type = Mux(io.lsu.req.fire , t_lsu,\n Mux(wb_fire , t_wb,\n Mux(prober_fire , t_probe,\n Mux(prefetch_fire , t_prefetch,\n Mux(mshrs.io.meta_read.fire, t_mshr_meta_read\n , t_replay)))))\n\n // Does this request need to send a response or nack\n val s0_send_resp_or_nack = Mux(io.lsu.req.fire, s0_valid,\n VecInit(Mux(mshrs.io.replay.fire && isRead(mshrs.io.replay.bits.uop.mem_cmd), 1.U(memWidth.W), 0.U(memWidth.W)).asBools))\n\n\n val s1_req = RegNext(s0_req)\n for (w <- 0 until memWidth)\n s1_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s0_req(w).uop)\n val s2_store_failed = Wire(Bool())\n val s1_valid = widthMap(w =>\n RegNext(s0_valid(w) &&\n !IsKilledByBranch(io.lsu.brupdate, s0_req(w).uop) &&\n !(io.lsu.exception && s0_req(w).uop.uses_ldq) &&\n !(s2_store_failed && io.lsu.req.fire && s0_req(w).uop.uses_stq),\n init=false.B))\n for (w <- 0 until memWidth)\n assert(!(io.lsu.s1_kill(w) && !RegNext(io.lsu.req.fire) && !RegNext(io.lsu.req.bits(w).valid)))\n val s1_addr = s1_req.map(_.addr)\n val s1_nack = s1_addr.map(a => a(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready)\n val s1_send_resp_or_nack = RegNext(s0_send_resp_or_nack)\n val s1_type = RegNext(s0_type)\n\n val s1_mshr_meta_read_way_en = RegNext(mshrs.io.meta_read.bits.way_en)\n val s1_replay_way_en = RegNext(mshrs.io.replay.bits.way_en) // For replays, the metadata isn't written yet\n val s1_wb_way_en = RegNext(wb.io.data_req.bits.way_en)\n\n // tag check\n def wayMap[T <: Data](f: Int => T) = VecInit((0 until nWays).map(f))\n val s1_tag_eq_way = widthMap(i => wayMap((w: Int) => meta(i).io.resp(w).tag === (s1_addr(i) >> untagBits)).asUInt)\n val s1_tag_match_way = widthMap(i =>\n Mux(s1_type === t_replay, s1_replay_way_en,\n Mux(s1_type === t_wb, s1_wb_way_en,\n Mux(s1_type === t_mshr_meta_read, s1_mshr_meta_read_way_en,\n wayMap((w: Int) => s1_tag_eq_way(i)(w) && meta(i).io.resp(w).coh.isValid()).asUInt))))\n\n val s1_wb_idx_matches = widthMap(i => (s1_addr(i)(untagBits-1,blockOffBits) === wb.io.idx.bits) && wb.io.idx.valid)\n\n val s2_req = RegNext(s1_req)\n val s2_type = RegNext(s1_type)\n val s2_valid = widthMap(w =>\n RegNext(s1_valid(w) &&\n !io.lsu.s1_kill(w) &&\n !IsKilledByBranch(io.lsu.brupdate, s1_req(w).uop) &&\n !(io.lsu.exception && s1_req(w).uop.uses_ldq) &&\n !(s2_store_failed && (s1_type === t_lsu) && s1_req(w).uop.uses_stq)))\n for (w <- 0 until memWidth)\n s2_req(w).uop.br_mask := GetNewBrMask(io.lsu.brupdate, s1_req(w).uop)\n\n val s2_tag_match_way = RegNext(s1_tag_match_way)\n val s2_tag_match = s2_tag_match_way.map(_.orR)\n val s2_hit_state = widthMap(i => Mux1H(s2_tag_match_way(i), wayMap((w: Int) => RegNext(meta(i).io.resp(w).coh))))\n val s2_has_permission = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._1)\n val s2_new_hit_state = widthMap(w => s2_hit_state(w).onAccess(s2_req(w).uop.mem_cmd)._3)\n\n val s2_hit = widthMap(w => (s2_tag_match(w) && s2_has_permission(w) && s2_hit_state(w) === s2_new_hit_state(w) && !mshrs.io.block_hit(w)) || s2_type.isOneOf(t_replay, t_wb))\n val s2_nack = Wire(Vec(memWidth, Bool()))\n assert(!(s2_type === t_replay && !s2_hit(0)), \"Replays should always hit\")\n assert(!(s2_type === t_wb && !s2_hit(0)), \"Writeback should always see data hit\")\n\n val s2_wb_idx_matches = RegNext(s1_wb_idx_matches)\n\n // lr/sc\n val debug_sc_fail_addr = RegInit(0.U)\n val debug_sc_fail_cnt = RegInit(0.U(8.W))\n\n val lrsc_count = RegInit(0.U(log2Ceil(lrscCycles).W))\n val lrsc_valid = lrsc_count > lrscBackoff.U\n val lrsc_addr = Reg(UInt())\n val s2_lr = s2_req(0).uop.mem_cmd === M_XLR && (!RegNext(s1_nack(0)) || s2_type === t_replay)\n val s2_sc = s2_req(0).uop.mem_cmd === M_XSC && (!RegNext(s1_nack(0)) || s2_type === t_replay)\n val s2_lrsc_addr_match = widthMap(w => lrsc_valid && lrsc_addr === (s2_req(w).addr >> blockOffBits))\n val s2_sc_fail = s2_sc && !s2_lrsc_addr_match(0)\n when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }\n when (s2_valid(0) && ((s2_type === t_lsu && s2_hit(0) && !s2_nack(0)) ||\n (s2_type === t_replay && s2_req(0).uop.mem_cmd =/= M_FLUSH_ALL))) {\n when (s2_lr) {\n lrsc_count := (lrscCycles - 1).U\n lrsc_addr := s2_req(0).addr >> blockOffBits\n }\n when (lrsc_count > 0.U) {\n lrsc_count := 0.U\n }\n }\n for (w <- 0 until memWidth) {\n when (s2_valid(w) &&\n s2_type === t_lsu &&\n !s2_hit(w) &&\n !(s2_has_permission(w) && s2_tag_match(w)) &&\n s2_lrsc_addr_match(w) &&\n !s2_nack(w)) {\n lrsc_count := 0.U\n }\n }\n\n when (s2_valid(0)) {\n when (s2_req(0).addr === debug_sc_fail_addr) {\n when (s2_sc_fail) {\n debug_sc_fail_cnt := debug_sc_fail_cnt + 1.U\n } .elsewhen (s2_sc) {\n debug_sc_fail_cnt := 0.U\n }\n } .otherwise {\n when (s2_sc_fail) {\n debug_sc_fail_addr := s2_req(0).addr\n debug_sc_fail_cnt := 1.U\n }\n }\n }\n assert(debug_sc_fail_cnt < 100.U, \"L1DCache failed too many SCs in a row\")\n\n val s2_data = Wire(Vec(memWidth, Vec(nWays, UInt(encRowBits.W))))\n for (i <- 0 until memWidth) {\n for (w <- 0 until nWays) {\n s2_data(i)(w) := data.io.resp(i)(w)\n }\n }\n\n val s2_data_muxed = widthMap(w => Mux1H(s2_tag_match_way(w), s2_data(w)))\n val s2_word_idx = widthMap(w => if (rowWords == 1) 0.U else s2_req(w).addr(log2Up(rowWords*wordBytes)-1, log2Up(wordBytes)))\n\n // replacement policy\n val replacer = cacheParams.replacement\n val s1_replaced_way_en = UIntToOH(replacer.way)\n val s2_replaced_way_en = UIntToOH(RegNext(replacer.way))\n val s2_repl_meta = widthMap(i => Mux1H(s2_replaced_way_en, wayMap((w: Int) => RegNext(meta(i).io.resp(w))).toSeq))\n\n // nack because of incoming probe\n val s2_nack_hit = RegNext(VecInit(s1_nack))\n // Nack when we hit something currently being evicted\n val s2_nack_victim = widthMap(w => s2_valid(w) && s2_hit(w) && mshrs.io.secondary_miss(w))\n // MSHRs not ready for request\n val s2_nack_miss = widthMap(w => s2_valid(w) && !s2_hit(w) && !mshrs.io.req(w).ready)\n // Bank conflict on data arrays\n val s2_nack_data = widthMap(w => data.io.nacks(w))\n // Can't allocate MSHR for same set currently being written back\n val s2_nack_wb = widthMap(w => s2_valid(w) && !s2_hit(w) && s2_wb_idx_matches(w))\n\n s2_nack := widthMap(w => (s2_nack_miss(w) || s2_nack_hit(w) || s2_nack_victim(w) || s2_nack_data(w) || s2_nack_wb(w)) && s2_type =/= t_replay)\n val s2_send_resp = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && !s2_nack(w) &&\n (s2_hit(w) || (mshrs.io.req(w).fire && isWrite(s2_req(w).uop.mem_cmd) && !isRead(s2_req(w).uop.mem_cmd)))))\n val s2_send_nack = widthMap(w => (RegNext(s1_send_resp_or_nack(w)) && s2_nack(w)))\n for (w <- 0 until memWidth)\n assert(!(s2_send_resp(w) && s2_send_nack(w)))\n\n // hits always send a response\n // If MSHR is not available, LSU has to replay this request later\n // If MSHR is available and this is only a store(not a amo), we don't need to wait for resp later\n s2_store_failed := s2_valid(0) && s2_nack(0) && s2_send_nack(0) && s2_req(0).uop.uses_stq\n\n // Miss handling\n for (w <- 0 until memWidth) {\n mshrs.io.req(w).valid := s2_valid(w) &&\n !s2_hit(w) &&\n !s2_nack_hit(w) &&\n !s2_nack_victim(w) &&\n !s2_nack_data(w) &&\n !s2_nack_wb(w) &&\n s2_type.isOneOf(t_lsu, t_prefetch) &&\n !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop) &&\n !(io.lsu.exception && s2_req(w).uop.uses_ldq) &&\n (isPrefetch(s2_req(w).uop.mem_cmd) ||\n isRead(s2_req(w).uop.mem_cmd) ||\n isWrite(s2_req(w).uop.mem_cmd))\n assert(!(mshrs.io.req(w).valid && s2_type === t_replay), \"Replays should not need to go back into MSHRs\")\n mshrs.io.req(w).bits := DontCare\n mshrs.io.req(w).bits.uop := s2_req(w).uop\n mshrs.io.req(w).bits.uop.br_mask := GetNewBrMask(io.lsu.brupdate, s2_req(w).uop)\n mshrs.io.req(w).bits.addr := s2_req(w).addr\n mshrs.io.req(w).bits.tag_match := s2_tag_match(w)\n mshrs.io.req(w).bits.old_meta := Mux(s2_tag_match(w), L1Metadata(s2_repl_meta(w).tag, s2_hit_state(w)), s2_repl_meta(w))\n mshrs.io.req(w).bits.way_en := Mux(s2_tag_match(w), s2_tag_match_way(w), s2_replaced_way_en)\n\n mshrs.io.req(w).bits.data := s2_req(w).data\n mshrs.io.req(w).bits.is_hella := s2_req(w).is_hella\n mshrs.io.req_is_probe(w) := s2_type === t_probe && s2_valid(w)\n }\n\n mshrs.io.meta_resp.valid := !s2_nack_hit(0) || prober.io.mshr_wb_rdy\n mshrs.io.meta_resp.bits := Mux1H(s2_tag_match_way(0), RegNext(meta(0).io.resp))\n when (mshrs.io.req.map(_.fire).reduce(_||_)) { replacer.miss }\n tl_out.a <> mshrs.io.mem_acquire\n\n // probes and releases\n prober.io.req.valid := tl_out.b.valid && !lrsc_valid\n tl_out.b.ready := prober.io.req.ready && !lrsc_valid\n prober.io.req.bits := tl_out.b.bits\n prober.io.way_en := s2_tag_match_way(0)\n prober.io.block_state := s2_hit_state(0)\n metaWriteArb.io.in(1) <> prober.io.meta_write\n prober.io.mshr_rdy := mshrs.io.probe_rdy\n prober.io.wb_rdy := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid\n mshrs.io.prober_state := prober.io.state\n\n // refills\n when (tl_out.d.bits.source === cfg.nMSHRs.U) {\n // This should be ReleaseAck\n tl_out.d.ready := true.B\n mshrs.io.mem_grant.valid := false.B\n mshrs.io.mem_grant.bits := DontCare\n } .otherwise {\n // This should be GrantData\n mshrs.io.mem_grant <> tl_out.d\n }\n\n dataWriteArb.io.in(1) <> mshrs.io.refill\n metaWriteArb.io.in(0) <> mshrs.io.meta_write\n\n tl_out.e <> mshrs.io.mem_finish\n\n // writebacks\n val wbArb = Module(new Arbiter(new WritebackReq(edge.bundle), 2))\n // 0 goes to prober, 1 goes to MSHR evictions\n wbArb.io.in(0) <> prober.io.wb_req\n wbArb.io.in(1) <> mshrs.io.wb_req\n wb.io.req <> wbArb.io.out\n wb.io.data_resp := s2_data_muxed(0)\n mshrs.io.wb_resp := wb.io.resp\n wb.io.mem_grant := tl_out.d.fire && tl_out.d.bits.source === cfg.nMSHRs.U\n\n val lsu_release_arb = Module(new Arbiter(new TLBundleC(edge.bundle), 2))\n io.lsu.release <> lsu_release_arb.io.out\n lsu_release_arb.io.in(0) <> wb.io.lsu_release\n lsu_release_arb.io.in(1) <> prober.io.lsu_release\n\n TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)\n\n io.lsu.perf.release := edge.done(tl_out.c)\n io.lsu.perf.acquire := edge.done(tl_out.a)\n\n // load data gen\n val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))\n val s2_data_word = Wire(Vec(memWidth, UInt()))\n\n val loadgen = (0 until memWidth).map { w =>\n new LoadGen(s2_req(w).uop.mem_size, s2_req(w).uop.mem_signed, s2_req(w).addr,\n s2_data_word(w), s2_sc && (w == 0).B, wordBytes)\n }\n // Mux between cache responses and uncache responses\n val cache_resp = Wire(Vec(memWidth, Valid(new BoomDCacheResp)))\n for (w <- 0 until memWidth) {\n cache_resp(w).valid := s2_valid(w) && s2_send_resp(w)\n cache_resp(w).bits.uop := s2_req(w).uop\n cache_resp(w).bits.data := loadgen(w).data | s2_sc_fail\n cache_resp(w).bits.is_hella := s2_req(w).is_hella\n }\n\n val uncache_resp = Wire(Valid(new BoomDCacheResp))\n uncache_resp.bits := mshrs.io.resp.bits\n uncache_resp.valid := mshrs.io.resp.valid\n mshrs.io.resp.ready := !(cache_resp.map(_.valid).reduce(_&&_)) // We can backpressure the MSHRs, but not cache hits\n\n val resp = WireInit(cache_resp)\n var uncache_responding = false.B\n for (w <- 0 until memWidth) {\n val uncache_respond = !cache_resp(w).valid && !uncache_responding\n when (uncache_respond) {\n resp(w) := uncache_resp\n }\n uncache_responding = uncache_responding || uncache_respond\n }\n\n for (w <- 0 until memWidth) {\n io.lsu.resp(w).valid := resp(w).valid &&\n !(io.lsu.exception && resp(w).bits.uop.uses_ldq) &&\n !IsKilledByBranch(io.lsu.brupdate, resp(w).bits.uop)\n io.lsu.resp(w).bits := UpdateBrMask(io.lsu.brupdate, resp(w).bits)\n\n io.lsu.nack(w).valid := s2_valid(w) && s2_send_nack(w) &&\n !(io.lsu.exception && s2_req(w).uop.uses_ldq) &&\n !IsKilledByBranch(io.lsu.brupdate, s2_req(w).uop)\n io.lsu.nack(w).bits := UpdateBrMask(io.lsu.brupdate, s2_req(w))\n assert(!(io.lsu.nack(w).valid && s2_type =/= t_lsu))\n }\n\n // Store/amo hits\n val s3_req = RegNext(s2_req(0))\n val s3_valid = RegNext(s2_valid(0) && s2_hit(0) && isWrite(s2_req(0).uop.mem_cmd) &&\n !s2_sc_fail && !(s2_send_nack(0) && s2_nack(0)))\n for (w <- 1 until memWidth) {\n assert(!(s2_valid(w) && s2_hit(w) && isWrite(s2_req(w).uop.mem_cmd) &&\n !s2_sc_fail && !(s2_send_nack(w) && s2_nack(w))),\n \"Store must go through 0th pipe in L1D\")\n }\n\n // For bypassing\n val s4_req = RegNext(s3_req)\n val s4_valid = RegNext(s3_valid)\n val s5_req = RegNext(s4_req)\n val s5_valid = RegNext(s4_valid)\n\n val s3_bypass = widthMap(w => s3_valid && ((s2_req(w).addr >> wordOffBits) === (s3_req.addr >> wordOffBits)))\n val s4_bypass = widthMap(w => s4_valid && ((s2_req(w).addr >> wordOffBits) === (s4_req.addr >> wordOffBits)))\n val s5_bypass = widthMap(w => s5_valid && ((s2_req(w).addr >> wordOffBits) === (s5_req.addr >> wordOffBits)))\n\n // Store -> Load bypassing\n for (w <- 0 until memWidth) {\n s2_data_word(w) := Mux(s3_bypass(w), s3_req.data,\n Mux(s4_bypass(w), s4_req.data,\n Mux(s5_bypass(w), s5_req.data,\n s2_data_word_prebypass(w))))\n }\n val amoalu = Module(new AMOALU(xLen))\n amoalu.io.mask := new StoreGen(s2_req(0).uop.mem_size, s2_req(0).addr, 0.U, xLen/8).mask\n amoalu.io.cmd := s2_req(0).uop.mem_cmd\n amoalu.io.lhs := s2_data_word(0)\n amoalu.io.rhs := s2_req(0).data\n\n\n s3_req.data := amoalu.io.out\n val s3_way = RegNext(s2_tag_match_way(0))\n\n dataWriteArb.io.in(0).valid := s3_valid\n dataWriteArb.io.in(0).bits.addr := s3_req.addr\n dataWriteArb.io.in(0).bits.wmask := UIntToOH(s3_req.addr.extract(rowOffBits-1,offsetlsb))\n dataWriteArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)\n dataWriteArb.io.in(0).bits.way_en := s3_way\n\n\n io.lsu.ordered := mshrs.io.fence_rdy && !s1_valid.reduce(_||_) && !s2_valid.reduce(_||_)\n}", + "response": "module BoomWritebackUnit(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [19:0] io_req_bits_tag,\n input [5:0] io_req_bits_idx,\n input [2:0] io_req_bits_param,\n input [3:0] io_req_bits_way_en,\n input io_req_bits_voluntary,\n input io_meta_read_ready,\n output io_meta_read_valid,\n output [5:0] io_meta_read_bits_idx,\n output [19:0] io_meta_read_bits_tag,\n output io_resp,\n output io_idx_valid,\n output [5:0] io_idx_bits,\n input io_data_req_ready,\n output io_data_req_valid,\n output [3:0] io_data_req_bits_way_en,\n output [11:0] io_data_req_bits_addr,\n input [63:0] io_data_resp,\n input io_mem_grant,\n input io_release_ready,\n output io_release_valid,\n output [2:0] io_release_bits_opcode,\n output [2:0] io_release_bits_param,\n output [31:0] io_release_bits_address,\n output [63:0] io_release_bits_data,\n input io_lsu_release_ready,\n output io_lsu_release_valid,\n output [31:0] io_lsu_release_bits_address\n);\n\n reg [19:0] req_tag;\n reg [5:0] req_idx;\n reg [2:0] req_param;\n reg [3:0] req_way_en;\n reg req_voluntary;\n reg [2:0] state;\n reg r1_data_req_fired;\n reg r2_data_req_fired;\n reg [3:0] r1_data_req_cnt;\n reg [3:0] r2_data_req_cnt;\n reg [3:0] data_req_cnt;\n reg [63:0] wb_buffer_0;\n reg [63:0] wb_buffer_1;\n reg [63:0] wb_buffer_2;\n reg [63:0] wb_buffer_3;\n reg [63:0] wb_buffer_4;\n reg [63:0] wb_buffer_5;\n reg [63:0] wb_buffer_6;\n reg [63:0] wb_buffer_7;\n reg acked;\n wire [31:0] r_address = {req_tag, req_idx, 6'h0};\n wire [7:0][63:0] _GEN = {{wb_buffer_7}, {wb_buffer_6}, {wb_buffer_5}, {wb_buffer_4}, {wb_buffer_3}, {wb_buffer_2}, {wb_buffer_1}, {wb_buffer_0}};\n wire io_req_ready_0 = state == 3'h0;\n wire _GEN_0 = state == 3'h1;\n wire io_data_req_valid_0 = ~io_req_ready_0 & _GEN_0 & ~(data_req_cnt[3]);\n wire _GEN_1 = r2_data_req_cnt == 4'h7;\n wire _GEN_2 = state == 3'h2;\n wire io_lsu_release_valid_0 = ~(io_req_ready_0 | _GEN_0) & _GEN_2;\n wire _GEN_3 = state == 3'h3;\n wire _GEN_4 = _GEN_0 | _GEN_2;\n wire io_release_valid_0 = ~(io_req_ready_0 | _GEN_4) & _GEN_3 & ~(data_req_cnt[3]);\n wire _GEN_5 = io_release_ready & io_release_valid_0;\n wire _GEN_6 = state == 3'h4;\n wire _GEN_7 = io_req_ready_0 & io_req_valid;\n wire _GEN_8 = io_req_ready_0 | ~_GEN_0;\n wire _GEN_9 = io_data_req_ready & io_data_req_valid_0 & io_meta_read_ready;\n always @(posedge clock) begin\n if (_GEN_7) begin\n req_tag <= io_req_bits_tag;\n req_idx <= io_req_bits_idx;\n req_param <= io_req_bits_param;\n req_way_en <= io_req_bits_way_en;\n req_voluntary <= io_req_bits_voluntary;\n end\n if (_GEN_8) begin\n end\n else begin\n r1_data_req_cnt <= _GEN_9 ? data_req_cnt : 4'h0;\n r2_data_req_cnt <= r1_data_req_cnt;\n end\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h0)) begin\n end\n else\n wb_buffer_0 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h1)) begin\n end\n else\n wb_buffer_1 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h2)) begin\n end\n else\n wb_buffer_2 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h3)) begin\n end\n else\n wb_buffer_3 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h4)) begin\n end\n else\n wb_buffer_4 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h5)) begin\n end\n else\n wb_buffer_5 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & r2_data_req_cnt[2:0] == 3'h6)) begin\n end\n else\n wb_buffer_6 <= io_data_resp;\n if (io_req_ready_0 | ~(_GEN_0 & r2_data_req_fired & (&(r2_data_req_cnt[2:0])))) begin\n end\n else\n wb_buffer_7 <= io_data_resp;\n if (reset) begin\n state <= 3'h0;\n r1_data_req_fired <= 1'h0;\n r2_data_req_fired <= 1'h0;\n data_req_cnt <= 4'h0;\n acked <= 1'h0;\n end\n else begin\n if (io_req_ready_0) begin\n if (_GEN_7) begin\n state <= 3'h1;\n data_req_cnt <= 4'h0;\n end\n acked <= ~_GEN_7 & acked;\n end\n else begin\n if (_GEN_0) begin\n if (r2_data_req_fired & _GEN_1) begin\n state <= 3'h2;\n data_req_cnt <= 4'h0;\n end\n else if (_GEN_9)\n data_req_cnt <= data_req_cnt + 4'h1;\n end\n else begin\n if (_GEN_2) begin\n if (io_lsu_release_ready & io_lsu_release_valid_0)\n state <= 3'h3;\n end\n else if (_GEN_3) begin\n if (data_req_cnt == 4'h7 & _GEN_5)\n state <= {req_voluntary, 2'h0};\n end\n else if (_GEN_6 & acked)\n state <= 3'h0;\n if (_GEN_2 | ~_GEN_5) begin\n end\n else\n data_req_cnt <= data_req_cnt + 4'h1;\n end\n if (~_GEN_4)\n acked <= _GEN_3 ? io_mem_grant | acked : _GEN_6 & io_mem_grant | acked;\n end\n if (_GEN_8) begin\n end\n else begin\n r1_data_req_fired <= _GEN_9;\n r2_data_req_fired <= r1_data_req_fired;\n end\n end\n end\n assign io_req_ready = io_req_ready_0;\n assign io_meta_read_valid = io_data_req_valid_0;\n assign io_meta_read_bits_idx = req_idx;\n assign io_meta_read_bits_tag = req_tag;\n assign io_resp = ~io_req_ready_0 & _GEN_0 & r2_data_req_fired & _GEN_1;\n assign io_idx_valid = |state;\n assign io_idx_bits = req_idx;\n assign io_data_req_valid = io_data_req_valid_0;\n assign io_data_req_bits_way_en = req_way_en;\n assign io_data_req_bits_addr = {req_idx, data_req_cnt[2:0], 3'h0};\n assign io_release_valid = io_release_valid_0;\n assign io_release_bits_opcode = {1'h1, req_voluntary, 1'h1};\n assign io_release_bits_param = req_param;\n assign io_release_bits_address = r_address;\n assign io_release_bits_data = _GEN[data_req_cnt[2:0]];\n assign io_lsu_release_valid = io_lsu_release_valid_0;\n assign io_lsu_release_bits_address = r_address;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket.Instructions32\nimport freechips.rocketchip.rocket.CustomInstructions._\nimport freechips.rocketchip.rocket.RVCExpander\nimport freechips.rocketchip.rocket.{CSR,Causes}\nimport freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.util._\n\n// scalastyle:off\n/**\n * Abstract trait giving defaults and other relevant values to different Decode constants/\n */\nabstract trait DecodeConstants\n extends freechips.rocketchip.rocket.constants.ScalarOpConstants\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val xpr64 = Y // TODO inform this from xLen\n val DC2 = BitPat.dontCare(2) // Makes the listing below more readable\n def decode_default: List[BitPat] =\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)\n\n val table: Array[(BitPat, List[BitPat])]\n}\n// scalastyle:on\n\n/**\n * Decoded control signals\n */\nclass CtrlSigs extends Bundle\n{\n val legal = Bool()\n val fp_val = Bool()\n val fp_single = Bool()\n val uopc = UInt(UOPC_SZ.W)\n val iq_type = UInt(IQT_SZ.W)\n val fu_code = UInt(FUC_SZ.W)\n val dst_type = UInt(2.W)\n val rs1_type = UInt(2.W)\n val rs2_type = UInt(2.W)\n val frs3_en = Bool()\n val imm_sel = UInt(IS_X.getWidth.W)\n val uses_ldq = Bool()\n val uses_stq = Bool()\n val is_amo = Bool()\n val is_fence = Bool()\n val is_fencei = Bool()\n val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)\n val wakeup_delay = UInt(2.W)\n val bypassable = Bool()\n val is_br = Bool()\n val is_sys_pc2epc = Bool()\n val inst_unique = Bool()\n val flush_on_commit = Bool()\n val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)\n val rocc = Bool()\n\n def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)\n val sigs =\n Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,\n rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,\n is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,\n is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n rocc := false.B\n this\n }\n}\n\n// scalastyle:off\n/**\n * Decode constants for RV32\n */\nobject X32Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n Instructions32.SLLI ->\n List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRLI ->\n List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRAI ->\n List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Decode constants for RV64\n */\nobject X64Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Overall Decode constants\n */\nobject XDecode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n\n SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read\n JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n\n // I-type, the immediate12 holds the CSR register.\n CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),\n ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),\n FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance\n // currently serializes pipeline\n\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // A-type | | | | | | | | | | | | | | | | | | | | | | | |\n AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance\n AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),\n AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),\n SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)\n )\n}\n\n/**\n * FP Decode constants\n */\nobject FDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops\n FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to FP\n FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // Int to FP\n FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to Int\n FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // \"fp_single\" is used for wb_data formatting (and debugging)\n FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * FP Divide SquareRoot Constants\n */\nobject FDivSqrtDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n//scalastyle:on\n\n/**\n * RoCC initial decode\n */\nobject RoCCDecode extends DecodeConstants\n{\n // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec rs1 regtype | | | uses_stq | | |\n // | | | | rs2 type| | | | is_amo | | |\n // | | | micro-code func unit | | | | | | | is_fence | | |\n // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |\n CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n\n\n\n\n/**\n * IO bundle for the Decode unit\n */\nclass DecodeUnitIo(implicit p: Parameters) extends BoomBundle\n{\n val enq = new Bundle { val uop = Input(new MicroOp()) }\n val deq = new Bundle { val uop = Output(new MicroOp()) }\n\n // from CSRFile\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)\n val interrupt = Input(Bool())\n val interrupt_cause = Input(UInt(xLen.W))\n}\n\n/**\n * Decode unit that takes in a single instruction and generates a MicroOp.\n */\nclass DecodeUnit(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new DecodeUnitIo)\n\n val uop = Wire(new MicroOp())\n uop := io.enq.uop\n\n var decode_table = XDecode.table\n if (usingFPU) decode_table ++= FDecode.table\n if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table\n if (usingRoCC) decode_table ++= RoCCDecode.table\n decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)\n\n val inst = uop.inst\n\n val cs = Wire(new CtrlSigs()).decode(inst, decode_table)\n\n // Exception Handling\n io.csr_decode.inst := inst\n val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)\n val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U\n val system_insn = cs.csr_cmd === CSR.I\n val sfence = cs.uopc === uopSFENCE\n\n val cs_legal = cs.legal\n// dontTouch(cs_legal)\n\n val id_illegal_insn = !cs_legal ||\n cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)\n cs.rocc && io.csr_decode.rocc_illegal ||\n cs.is_amo && !io.status.isa('a'-'a') ||\n (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||\n csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||\n ((sfence || system_insn) && io.csr_decode.system_illegal)\n\n// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n\n val (xcpt_valid, xcpt_cause) = checkExceptions(List(\n (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB\n (uop.bp_debug_if, (CSR.debugTriggerCause).U),\n (uop.bp_xcpt_if, (Causes.breakpoint).U),\n (uop.xcpt_pf_if, (Causes.fetch_page_fault).U),\n (uop.xcpt_ae_if, (Causes.fetch_access).U),\n (id_illegal_insn, (Causes.illegal_instruction).U)))\n\n uop.exception := xcpt_valid\n uop.exc_cause := xcpt_cause\n\n //-------------------------------------------------------------\n\n uop.uopc := cs.uopc\n uop.iq_type := cs.iq_type\n uop.fu_code := cs.fu_code\n\n // x-registers placed in 0-31, f-registers placed in 32-63.\n // This allows us to straight-up compare register specifiers and not need to\n // verify the rtypes (e.g., bypassing in rename).\n uop.ldst := inst(RD_MSB,RD_LSB)\n uop.lrs1 := inst(RS1_MSB,RS1_LSB)\n uop.lrs2 := inst(RS2_MSB,RS2_LSB)\n uop.lrs3 := inst(RS3_MSB,RS3_LSB)\n\n uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)\n uop.dst_rtype := cs.dst_type\n uop.lrs1_rtype := cs.rs1_type\n uop.lrs2_rtype := cs.rs2_type\n uop.frs3_en := cs.frs3_en\n\n uop.ldst_is_rs1 := uop.is_sfb_shadow\n // SFB optimization\n when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {\n uop.lrs2_rtype := RT_FIX\n uop.lrs2 := inst(RD_MSB,RD_LSB)\n uop.ldst_is_rs1 := false.B\n } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {\n uop.uopc := uopMOV\n uop.lrs1 := inst(RD_MSB, RD_LSB)\n uop.ldst_is_rs1 := true.B\n }\n when (uop.is_sfb_br) {\n uop.fu_code := FU_JMP\n }\n\n\n uop.fp_val := cs.fp_val\n uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?\n\n uop.mem_cmd := cs.mem_cmd\n uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))\n uop.mem_signed := !inst(14)\n uop.uses_ldq := cs.uses_ldq\n uop.uses_stq := cs.uses_stq\n uop.is_amo := cs.is_amo\n uop.is_fence := cs.is_fence\n uop.is_fencei := cs.is_fencei\n uop.is_sys_pc2epc := cs.is_sys_pc2epc\n uop.is_unique := cs.inst_unique\n uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)\n\n uop.bypassable := cs.bypassable\n\n //-------------------------------------------------------------\n // immediates\n\n // repackage the immediate, and then pass the fewest number of bits around\n val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))\n uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))\n\n //-------------------------------------------------------------\n\n uop.is_br := cs.is_br\n uop.is_jal := (uop.uopc === uopJAL)\n uop.is_jalr := (uop.uopc === uopJALR)\n // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)\n // uop.is_ret := (uop.uopc === uopJALR) &&\n // (uop.ldst === X0) &&\n // (uop.lrs1 === RA)\n // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&\n // (uop.ldst === RA)\n\n //-------------------------------------------------------------\n\n io.deq.uop := uop\n}\n\n/**\n * Smaller Decode unit for the Frontend to decode different\n * branches.\n * Accepts EXPANDED RVC instructions\n */\n\nclass BranchDecodeSignals(implicit p: Parameters) extends BoomBundle\n{\n val is_ret = Bool()\n val is_call = Bool()\n val target = UInt(vaddrBitsExtended.W)\n val cfi_type = UInt(CFI_SZ.W)\n\n\n // Is this branch a short forwards jump?\n val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))\n // Is this instruction allowed to be inside a sfb?\n val shadowable = Bool()\n}\n\nclass BranchDecode(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val inst = Input(UInt(32.W))\n val pc = Input(UInt(vaddrBitsExtended.W))\n\n val out = Output(new BranchDecodeSignals)\n })\n\n val bpd_csignals =\n freechips.rocketchip.rocket.DecodeLogic(io.inst,\n List[BitPat](N, N, N, N, X),\n//// is br?\n//// | is jal?\n//// | | is jalr?\n//// | | |\n//// | | | shadowable\n//// | | | | has_rs2\n//// | | | | |\n Array[(BitPat, List[BitPat])](\n JAL -> List(N, Y, N, N, X),\n JALR -> List(N, N, Y, N, X),\n BEQ -> List(Y, N, N, N, X),\n BNE -> List(Y, N, N, N, X),\n BGE -> List(Y, N, N, N, X),\n BGEU -> List(Y, N, N, N, X),\n BLT -> List(Y, N, N, N, X),\n BLTU -> List(Y, N, N, N, X),\n\n SLLI -> List(N, N, N, Y, N),\n SRLI -> List(N, N, N, Y, N),\n SRAI -> List(N, N, N, Y, N),\n\n ADDIW -> List(N, N, N, Y, N),\n SLLIW -> List(N, N, N, Y, N),\n SRAIW -> List(N, N, N, Y, N),\n SRLIW -> List(N, N, N, Y, N),\n\n ADDW -> List(N, N, N, Y, Y),\n SUBW -> List(N, N, N, Y, Y),\n SLLW -> List(N, N, N, Y, Y),\n SRAW -> List(N, N, N, Y, Y),\n SRLW -> List(N, N, N, Y, Y),\n\n LUI -> List(N, N, N, Y, N),\n\n ADDI -> List(N, N, N, Y, N),\n ANDI -> List(N, N, N, Y, N),\n ORI -> List(N, N, N, Y, N),\n XORI -> List(N, N, N, Y, N),\n SLTI -> List(N, N, N, Y, N),\n SLTIU -> List(N, N, N, Y, N),\n\n SLL -> List(N, N, N, Y, Y),\n ADD -> List(N, N, N, Y, Y),\n SUB -> List(N, N, N, Y, Y),\n SLT -> List(N, N, N, Y, Y),\n SLTU -> List(N, N, N, Y, Y),\n AND -> List(N, N, N, Y, Y),\n OR -> List(N, N, N, Y, Y),\n XOR -> List(N, N, N, Y, Y),\n SRA -> List(N, N, N, Y, Y),\n SRL -> List(N, N, N, Y, Y)\n ))\n\n val cs_is_br = bpd_csignals(0)(0)\n val cs_is_jal = bpd_csignals(1)(0)\n val cs_is_jalr = bpd_csignals(2)(0)\n val cs_is_shadowable = bpd_csignals(3)(0)\n val cs_has_rs2 = bpd_csignals(4)(0)\n\n io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA\n io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat(\"b00?01\") && GetRd(io.inst) === X0\n\n io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),\n ComputeJALTarget(io.pc, io.inst, xLen))\n io.out.cfi_type :=\n Mux(cs_is_jalr,\n CFI_JALR,\n Mux(cs_is_jal,\n CFI_JAL,\n Mux(cs_is_br,\n CFI_BR,\n CFI_X)))\n\n val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))\n // Is a sfb if it points forwards (offset is positive)\n io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U\n io.out.sfb_offset.bits := br_offset\n io.out.shadowable := cs_is_shadowable && (\n !cs_has_rs2 ||\n (GetRs1(io.inst) === GetRd(io.inst)) ||\n (io.inst === ADD && GetRs1(io.inst) === X0)\n )\n}\n\n/**\n * Track the current \"branch mask\", and give out the branch mask to each micro-op in Decode\n * (each micro-op in the machine has a branch mask which says which branches it\n * is being speculated under).\n *\n * @param pl_width pipeline width for the processor\n */\nclass BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n // guess if the uop is a branch (we'll catch this later)\n val is_branch = Input(Vec(pl_width, Bool()))\n // lock in that it's actually a branch and will fire, so we update\n // the branch_masks.\n val will_fire = Input(Vec(pl_width, Bool()))\n\n // give out tag immediately (needed in rename)\n // mask can come later in the cycle\n val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))\n val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))\n\n // tell decoders the branch mask has filled up, but on the granularity\n // of an individual micro-op (so some micro-ops can go through)\n val is_full = Output(Vec(pl_width, Bool()))\n\n val brupdate = Input(new BrUpdateInfo())\n val flush_pipeline = Input(Bool())\n\n val debug_branch_mask = Output(UInt(maxBrCount.W))\n })\n\n val branch_mask = RegInit(0.U(maxBrCount.W))\n\n //-------------------------------------------------------------\n // Give out the branch tag to each branch micro-op\n\n var allocate_mask = branch_mask\n val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))\n\n for (w <- 0 until pl_width) {\n // TODO this is a loss of performance as we're blocking branches based on potentially fake branches\n io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)\n\n // find br_tag and compute next br_mask\n val new_br_tag = Wire(UInt(brTagSz.W))\n new_br_tag := 0.U\n tag_masks(w) := 0.U\n\n for (i <- maxBrCount-1 to 0 by -1) {\n when (~allocate_mask(i)) {\n new_br_tag := i.U\n tag_masks(w) := (1.U << i.U)\n }\n }\n\n io.br_tag(w) := new_br_tag\n allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)\n }\n\n //-------------------------------------------------------------\n // Give out the branch mask to each micro-op\n // (kill off the bits that corresponded to branches that aren't going to fire)\n\n var curr_mask = branch_mask\n for (w <- 0 until pl_width) {\n io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)\n curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)\n }\n\n //-------------------------------------------------------------\n // Update the current branch_mask\n\n when (io.flush_pipeline) {\n branch_mask := 0.U\n } .otherwise {\n val mask = Mux(io.brupdate.b2.mispredict,\n io.brupdate.b2.uop.br_mask,\n ~(0.U(maxBrCount.W)))\n branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask\n }\n\n io.debug_branch_mask := branch_mask\n}", + "response": "module BranchMaskGenerationLogic(\n input clock,\n input reset,\n input io_is_branch_0,\n input io_will_fire_0,\n output [2:0] io_br_tag_0,\n output [7:0] io_br_mask_0,\n output io_is_full_0,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b2_uop_br_mask,\n input io_brupdate_b2_mispredict,\n input io_flush_pipeline\n);\n\n reg [7:0] branch_mask;\n always @(posedge clock) begin\n if (reset)\n branch_mask <= 8'h0;\n else\n branch_mask <= io_flush_pipeline ? 8'h0 : ({8{io_will_fire_0}} & (branch_mask[0] ? (branch_mask[1] ? (branch_mask[2] ? (branch_mask[3] ? (branch_mask[4] ? (branch_mask[5] ? (branch_mask[6] ? {~(branch_mask[7]), 7'h0} : 8'h40) : 8'h20) : 8'h10) : 8'h8) : 8'h4) : 8'h2) : 8'h1) | branch_mask) & ~io_brupdate_b1_resolve_mask & (io_brupdate_b2_mispredict ? io_brupdate_b2_uop_br_mask : 8'hFF);\n end\n assign io_br_tag_0 = branch_mask[0] ? (branch_mask[1] ? (branch_mask[2] ? (branch_mask[3] ? (branch_mask[4] ? (branch_mask[5] ? (branch_mask[6] ? {3{~(branch_mask[7])}} : 3'h6) : 3'h5) : 3'h4) : 3'h3) : 3'h2) : 3'h1) : 3'h0;\n assign io_br_mask_0 = branch_mask & ~io_brupdate_b1_resolve_mask;\n assign io_is_full_0 = (&branch_mask) & io_is_branch_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_preMul_e5_s11(\n input [1:0] io_op,\n input [16:0] io_a,\n input [16:0] io_b,\n input [16:0] io_c,\n output [10:0] io_mulAddA,\n output [10:0] io_mulAddB,\n output [21:0] io_mulAddC,\n output io_toPostMul_isSigNaNAny,\n output io_toPostMul_isNaNAOrB,\n output io_toPostMul_isInfA,\n output io_toPostMul_isZeroA,\n output io_toPostMul_isInfB,\n output io_toPostMul_isZeroB,\n output io_toPostMul_signProd,\n output io_toPostMul_isNaNC,\n output io_toPostMul_isInfC,\n output io_toPostMul_isZeroC,\n output [6:0] io_toPostMul_sExpSum,\n output io_toPostMul_doSubMags,\n output io_toPostMul_CIsDominant,\n output [3:0] io_toPostMul_CDom_CAlignDist,\n output [12:0] io_toPostMul_highAlignedSigC,\n output io_toPostMul_bit0AlignedSigC\n);\n\n wire rawA_isNaN = (&(io_a[15:14])) & io_a[13];\n wire rawB_isNaN = (&(io_b[15:14])) & io_b[13];\n wire rawC_isNaN = (&(io_c[15:14])) & io_c[13];\n wire signProd = io_a[16] ^ io_b[16] ^ io_op[1];\n wire [7:0] _sExpAlignedProd_T_1 = {2'h0, io_a[15:10]} + {2'h0, io_b[15:10]} - 8'h12;\n wire doSubMags = signProd ^ io_c[16] ^ io_op[0];\n wire [7:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[15:10]};\n wire isMinCAlign = ~(|(io_a[15:13])) | ~(|(io_b[15:13])) | $signed(_sNatCAlignDist_T) < 8'sh0;\n wire CIsDominant = (|(io_c[15:13])) & (isMinCAlign | _sNatCAlignDist_T[6:0] < 7'hC);\n wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _sNatCAlignDist_T[6:0] < 7'h23 ? _sNatCAlignDist_T[5:0] : 6'h23;\n wire [38:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[15:13])), ~(io_c[9:0])} : {1'h0, |(io_c[15:13]), io_c[9:0]}, {27{doSubMags}}}) >>> CAlignDist);\n wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> CAlignDist[5:2]);\n wire [1:0] _GEN = {|(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[8], reduced4CExtra_shift[9]};\n assign io_mulAddA = {|(io_a[15:13]), io_a[9:0]};\n assign io_mulAddB = {|(io_b[15:13]), io_b[9:0]};\n assign io_mulAddC = mainAlignedSigC[24:3];\n assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[9]) | rawB_isNaN & ~(io_b[9]) | rawC_isNaN & ~(io_c[9]);\n assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;\n assign io_toPostMul_isInfA = (&(io_a[15:14])) & ~(io_a[13]);\n assign io_toPostMul_isZeroA = ~(|(io_a[15:13]));\n assign io_toPostMul_isInfB = (&(io_b[15:14])) & ~(io_b[13]);\n assign io_toPostMul_isZeroB = ~(|(io_b[15:13]));\n assign io_toPostMul_signProd = signProd;\n assign io_toPostMul_isNaNC = rawC_isNaN;\n assign io_toPostMul_isInfC = (&(io_c[15:14])) & ~(io_c[13]);\n assign io_toPostMul_isZeroC = ~(|(io_c[15:13]));\n assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[15:10]} : _sExpAlignedProd_T_1[6:0] - 7'hB;\n assign io_toPostMul_doSubMags = doSubMags;\n assign io_toPostMul_CIsDominant = CIsDominant;\n assign io_toPostMul_CDom_CAlignDist = CAlignDist[3:0];\n assign io_toPostMul_highAlignedSigC = mainAlignedSigC[37:25];\n assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 2'h0 : (|{mainAlignedSigC[2:0], _GEN});\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Unit Decode\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Generate the functional unit control signals from the micro-op opcodes.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.uintToBitPat\nimport freechips.rocketchip.rocket.CSR\nimport freechips.rocketchip.rocket.ALU._\n\nimport boom.v3.common._\n\n/**\n * Control signal bundle for register renaming\n */\nclass RRdCtrlSigs(implicit p: Parameters) extends BoomBundle\n{\n val br_type = UInt(BR_N.getWidth.W)\n val use_alupipe = Bool()\n val use_muldivpipe = Bool()\n val use_mempipe = Bool()\n val op_fcn = Bits(SZ_ALU_FN.W)\n val fcn_dw = Bool()\n val op1_sel = UInt(OP1_X.getWidth.W)\n val op2_sel = UInt(OP2_X.getWidth.W)\n val imm_sel = UInt(IS_X.getWidth.W)\n val rf_wen = Bool()\n val csr_cmd = Bits(CSR.SZ.W)\n\n def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)\n val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,\n fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n this\n }\n}\n\n/**\n * Default register read constants\n */\nabstract trait RRdDecodeConstants\n{\n val default: List[BitPat] =\n List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)\n val table: Array[(BitPat, List[BitPat])]\n}\n\n/**\n * ALU register read constants\n */\nobject AluRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),\n\n BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))\n}\n\nobject JmpRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),\n BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),\n BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))\n}\n\n/**\n * Multiply divider register read constants\n */\nobject MulDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n\n BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Memory unit register read constants\n */\nobject MemRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),\n BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),\n BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n\n BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))\n}\n\n/**\n * CSR register read constants\n */\nobject CsrRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),\n\n BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),\n\n BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),\n BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))\n}\n\n/**\n * FPU register read constants\n */\nobject FpuRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// TODO comment out I2F instructions.\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Fused multiple add register read constants\n */\nobject IfmvRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Floating point divide and square root register read constants\n */\nobject FDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Register read decoder\n *\n * @param supportedUnits indicate what functional units are being used\n */\nclass RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new BoomBundle {\n val iss_valid = Input(Bool())\n val iss_uop = Input(new MicroOp())\n\n val rrd_valid = Output(Bool())\n val rrd_uop = Output(new MicroOp())\n })\n\n // Issued Instruction\n val rrd_valid = io.iss_valid\n io.rrd_uop := io.iss_uop\n\n var dec_table = AluRRdDecode.table\n if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table\n if (supportedUnits.mem) dec_table ++= MemRRdDecode.table\n if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table\n if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table\n if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table\n if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table\n if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table\n val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)\n\n // rrd_use_alupipe is unused\n io.rrd_uop.ctrl.br_type := rrd_cs.br_type\n io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel\n io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel\n io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel\n io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt\n io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool\n io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD\n io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG\n io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)\n\n when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {\n io.rrd_uop.imm_packed := 0.U\n }\n\n val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0\n val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U\n io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)\n\n //-------------------------------------------------------------\n // set outputs\n\n io.rrd_valid := rrd_valid\n}", + "response": "module RegisterReadDecode(\n input io_iss_valid,\n input [6:0] io_iss_uop_uopc,\n input [31:0] io_iss_uop_inst,\n input [31:0] io_iss_uop_debug_inst,\n input io_iss_uop_is_rvc,\n input [39:0] io_iss_uop_debug_pc,\n input [2:0] io_iss_uop_iq_type,\n input [9:0] io_iss_uop_fu_code,\n input [1:0] io_iss_uop_iw_state,\n input io_iss_uop_is_br,\n input io_iss_uop_is_jalr,\n input io_iss_uop_is_jal,\n input io_iss_uop_is_sfb,\n input [7:0] io_iss_uop_br_mask,\n input [2:0] io_iss_uop_br_tag,\n input [3:0] io_iss_uop_ftq_idx,\n input io_iss_uop_edge_inst,\n input [5:0] io_iss_uop_pc_lob,\n input io_iss_uop_taken,\n input [19:0] io_iss_uop_imm_packed,\n input [11:0] io_iss_uop_csr_addr,\n input [4:0] io_iss_uop_rob_idx,\n input [2:0] io_iss_uop_ldq_idx,\n input [2:0] io_iss_uop_stq_idx,\n input [1:0] io_iss_uop_rxq_idx,\n input [5:0] io_iss_uop_pdst,\n input [5:0] io_iss_uop_prs1,\n input [5:0] io_iss_uop_prs2,\n input [5:0] io_iss_uop_prs3,\n input [3:0] io_iss_uop_ppred,\n input io_iss_uop_prs1_busy,\n input io_iss_uop_prs2_busy,\n input io_iss_uop_prs3_busy,\n input io_iss_uop_ppred_busy,\n input [5:0] io_iss_uop_stale_pdst,\n input io_iss_uop_exception,\n input [63:0] io_iss_uop_exc_cause,\n input io_iss_uop_bypassable,\n input [4:0] io_iss_uop_mem_cmd,\n input [1:0] io_iss_uop_mem_size,\n input io_iss_uop_mem_signed,\n input io_iss_uop_is_fence,\n input io_iss_uop_is_fencei,\n input io_iss_uop_is_amo,\n input io_iss_uop_uses_ldq,\n input io_iss_uop_uses_stq,\n input io_iss_uop_is_sys_pc2epc,\n input io_iss_uop_is_unique,\n input io_iss_uop_flush_on_commit,\n input io_iss_uop_ldst_is_rs1,\n input [5:0] io_iss_uop_ldst,\n input [5:0] io_iss_uop_lrs1,\n input [5:0] io_iss_uop_lrs2,\n input [5:0] io_iss_uop_lrs3,\n input io_iss_uop_ldst_val,\n input [1:0] io_iss_uop_dst_rtype,\n input [1:0] io_iss_uop_lrs1_rtype,\n input [1:0] io_iss_uop_lrs2_rtype,\n input io_iss_uop_frs3_en,\n input io_iss_uop_fp_val,\n input io_iss_uop_fp_single,\n input io_iss_uop_xcpt_pf_if,\n input io_iss_uop_xcpt_ae_if,\n input io_iss_uop_xcpt_ma_if,\n input io_iss_uop_bp_debug_if,\n input io_iss_uop_bp_xcpt_if,\n input [1:0] io_iss_uop_debug_fsrc,\n input [1:0] io_iss_uop_debug_tsrc,\n output io_rrd_valid,\n output [6:0] io_rrd_uop_uopc,\n output [31:0] io_rrd_uop_inst,\n output [31:0] io_rrd_uop_debug_inst,\n output io_rrd_uop_is_rvc,\n output [39:0] io_rrd_uop_debug_pc,\n output [2:0] io_rrd_uop_iq_type,\n output [9:0] io_rrd_uop_fu_code,\n output [3:0] io_rrd_uop_ctrl_br_type,\n output [1:0] io_rrd_uop_ctrl_op1_sel,\n output [2:0] io_rrd_uop_ctrl_op2_sel,\n output [2:0] io_rrd_uop_ctrl_imm_sel,\n output [4:0] io_rrd_uop_ctrl_op_fcn,\n output io_rrd_uop_ctrl_fcn_dw,\n output [2:0] io_rrd_uop_ctrl_csr_cmd,\n output io_rrd_uop_ctrl_is_load,\n output io_rrd_uop_ctrl_is_sta,\n output io_rrd_uop_ctrl_is_std,\n output [1:0] io_rrd_uop_iw_state,\n output io_rrd_uop_is_br,\n output io_rrd_uop_is_jalr,\n output io_rrd_uop_is_jal,\n output io_rrd_uop_is_sfb,\n output [7:0] io_rrd_uop_br_mask,\n output [2:0] io_rrd_uop_br_tag,\n output [3:0] io_rrd_uop_ftq_idx,\n output io_rrd_uop_edge_inst,\n output [5:0] io_rrd_uop_pc_lob,\n output io_rrd_uop_taken,\n output [19:0] io_rrd_uop_imm_packed,\n output [11:0] io_rrd_uop_csr_addr,\n output [4:0] io_rrd_uop_rob_idx,\n output [2:0] io_rrd_uop_ldq_idx,\n output [2:0] io_rrd_uop_stq_idx,\n output [1:0] io_rrd_uop_rxq_idx,\n output [5:0] io_rrd_uop_pdst,\n output [5:0] io_rrd_uop_prs1,\n output [5:0] io_rrd_uop_prs2,\n output [5:0] io_rrd_uop_prs3,\n output [3:0] io_rrd_uop_ppred,\n output io_rrd_uop_prs1_busy,\n output io_rrd_uop_prs2_busy,\n output io_rrd_uop_prs3_busy,\n output io_rrd_uop_ppred_busy,\n output [5:0] io_rrd_uop_stale_pdst,\n output io_rrd_uop_exception,\n output [63:0] io_rrd_uop_exc_cause,\n output io_rrd_uop_bypassable,\n output [4:0] io_rrd_uop_mem_cmd,\n output [1:0] io_rrd_uop_mem_size,\n output io_rrd_uop_mem_signed,\n output io_rrd_uop_is_fence,\n output io_rrd_uop_is_fencei,\n output io_rrd_uop_is_amo,\n output io_rrd_uop_uses_ldq,\n output io_rrd_uop_uses_stq,\n output io_rrd_uop_is_sys_pc2epc,\n output io_rrd_uop_is_unique,\n output io_rrd_uop_flush_on_commit,\n output io_rrd_uop_ldst_is_rs1,\n output [5:0] io_rrd_uop_ldst,\n output [5:0] io_rrd_uop_lrs1,\n output [5:0] io_rrd_uop_lrs2,\n output [5:0] io_rrd_uop_lrs3,\n output io_rrd_uop_ldst_val,\n output [1:0] io_rrd_uop_dst_rtype,\n output [1:0] io_rrd_uop_lrs1_rtype,\n output [1:0] io_rrd_uop_lrs2_rtype,\n output io_rrd_uop_frs3_en,\n output io_rrd_uop_fp_val,\n output io_rrd_uop_fp_single,\n output io_rrd_uop_xcpt_pf_if,\n output io_rrd_uop_xcpt_ae_if,\n output io_rrd_uop_xcpt_ma_if,\n output io_rrd_uop_bp_debug_if,\n output io_rrd_uop_bp_xcpt_if,\n output [1:0] io_rrd_uop_debug_fsrc,\n output [1:0] io_rrd_uop_debug_tsrc\n);\n\n wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_6 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_49 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_55 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[6]};\n wire [2:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_61 = {io_iss_uop_uopc[0], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [3:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_62 = {rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]};\n wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;\n wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;\n wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;\n assign io_rrd_valid = io_iss_valid;\n assign io_rrd_uop_uopc = io_iss_uop_uopc;\n assign io_rrd_uop_inst = io_iss_uop_inst;\n assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;\n assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;\n assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;\n assign io_rrd_uop_iq_type = io_iss_uop_iq_type;\n assign io_rrd_uop_fu_code = io_iss_uop_fu_code;\n assign io_rrd_uop_ctrl_br_type = {1'h0, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}};\n assign io_rrd_uop_ctrl_op1_sel = {1'h0, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3};\n assign io_rrd_uop_ctrl_op2_sel = {2'h0, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};\n assign io_rrd_uop_ctrl_imm_sel = {1'h0, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &{io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_3};\n assign io_rrd_uop_ctrl_op_fcn =\n {|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},\n |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},\n |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_6, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},\n |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_6, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_49, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_61, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62},\n |{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_55, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_62}};\n assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52} == 3'h0;\n assign io_rrd_uop_ctrl_csr_cmd = 3'h0;\n assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;\n assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;\n assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;\n assign io_rrd_uop_iw_state = io_iss_uop_iw_state;\n assign io_rrd_uop_is_br = io_iss_uop_is_br;\n assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;\n assign io_rrd_uop_is_jal = io_iss_uop_is_jal;\n assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;\n assign io_rrd_uop_br_mask = io_iss_uop_br_mask;\n assign io_rrd_uop_br_tag = io_iss_uop_br_tag;\n assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;\n assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;\n assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;\n assign io_rrd_uop_taken = io_iss_uop_taken;\n assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;\n assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;\n assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;\n assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;\n assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;\n assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;\n assign io_rrd_uop_pdst = io_iss_uop_pdst;\n assign io_rrd_uop_prs1 = io_iss_uop_prs1;\n assign io_rrd_uop_prs2 = io_iss_uop_prs2;\n assign io_rrd_uop_prs3 = io_iss_uop_prs3;\n assign io_rrd_uop_ppred = io_iss_uop_ppred;\n assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;\n assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;\n assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;\n assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;\n assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;\n assign io_rrd_uop_exception = io_iss_uop_exception;\n assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;\n assign io_rrd_uop_bypassable = io_iss_uop_bypassable;\n assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;\n assign io_rrd_uop_mem_size = io_iss_uop_mem_size;\n assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;\n assign io_rrd_uop_is_fence = io_iss_uop_is_fence;\n assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;\n assign io_rrd_uop_is_amo = io_iss_uop_is_amo;\n assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;\n assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;\n assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;\n assign io_rrd_uop_is_unique = io_iss_uop_is_unique;\n assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;\n assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;\n assign io_rrd_uop_ldst = io_iss_uop_ldst;\n assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;\n assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;\n assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;\n assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;\n assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;\n assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;\n assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;\n assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;\n assign io_rrd_uop_fp_val = io_iss_uop_fp_val;\n assign io_rrd_uop_fp_single = io_iss_uop_fp_single;\n assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;\n assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;\n assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;\n assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;\n assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;\n assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;\n assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a12d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [11:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [11:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [11:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module next_40x6(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:39];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw67_f32_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [64:0] io_out_bits_payload,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_payload = {io_in_bits_flit[2:0], data_1, data_0[31:2]};\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_postMul_e5_s11(\n input io_fromPreMul_isSigNaNAny,\n input io_fromPreMul_isNaNAOrB,\n input io_fromPreMul_isInfA,\n input io_fromPreMul_isZeroA,\n input io_fromPreMul_isInfB,\n input io_fromPreMul_isZeroB,\n input io_fromPreMul_signProd,\n input io_fromPreMul_isNaNC,\n input io_fromPreMul_isInfC,\n input io_fromPreMul_isZeroC,\n input [6:0] io_fromPreMul_sExpSum,\n input io_fromPreMul_doSubMags,\n input io_fromPreMul_CIsDominant,\n input [3:0] io_fromPreMul_CDom_CAlignDist,\n input [12:0] io_fromPreMul_highAlignedSigC,\n input io_fromPreMul_bit0AlignedSigC,\n input [22:0] io_mulAddResult,\n input [2:0] io_roundingMode,\n output io_invalidExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [6:0] io_rawOut_sExp,\n output [13:0] io_rawOut_sig\n);\n\n wire roundingMode_min = io_roundingMode == 3'h2;\n wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;\n wire [12:0] _sigSum_T_3 = io_mulAddResult[22] ? io_fromPreMul_highAlignedSigC + 13'h1 : io_fromPreMul_highAlignedSigC;\n wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[21:11]} : {1'h0, io_fromPreMul_highAlignedSigC[12:11], _sigSum_T_3[10:0], io_mulAddResult[21:12]};\n wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;\n wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> ~(io_fromPreMul_CDom_CAlignDist[3:2]));\n wire [24:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[21:0], io_fromPreMul_bit0AlignedSigC} + {24'h0, io_fromPreMul_doSubMags};\n wire [3:0] notCDom_normDistReduced2 = notCDom_absSigSum[24] ? 4'h0 : (|(notCDom_absSigSum[23:22])) ? 4'h1 : (|(notCDom_absSigSum[21:20])) ? 4'h2 : (|(notCDom_absSigSum[19:18])) ? 4'h3 : (|(notCDom_absSigSum[17:16])) ? 4'h4 : (|(notCDom_absSigSum[15:14])) ? 4'h5 : (|(notCDom_absSigSum[13:12])) ? 4'h6 : (|(notCDom_absSigSum[11:10])) ? 4'h7 : (|(notCDom_absSigSum[9:8])) ? 4'h8 : (|(notCDom_absSigSum[7:6])) ? 4'h9 : (|(notCDom_absSigSum[5:4])) ? 4'hA : (|(notCDom_absSigSum[3:2])) ? 4'hB : 4'hC;\n wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << {51'h0, notCDom_normDistReduced2, 1'h0};\n wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(notCDom_normDistReduced2[3:1]));\n wire notCDom_completeCancellation = _notCDom_mainSig_T[25:24] == 2'h0;\n wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;\n wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;\n wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;\n assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;\n assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;\n assign io_rawOut_isInf = notNaN_isInfOut;\n assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;\n assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);\n assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {6'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {2'h0, notCDom_normDistReduced2, 1'h0};\n assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[23:11], (|{_CDom_mainSig_T[10:8], {|(CDom_absSigSum[7:4]), |(CDom_absSigSum[3:0])} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[10:0] != 11'h7FF : (|(io_mulAddResult[11:0])))} : {_notCDom_mainSig_T[25:13], |{_notCDom_mainSig_T[12:10], {|{|(notCDom_absSigSum[9:8]), |(notCDom_absSigSum[7:6])}, |{|(notCDom_absSigSum[5:4]), |(notCDom_absSigSum[3:2])}, |(notCDom_absSigSum[1:0])} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3]}}};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11(\n input io_invalidExc,\n input io_infiniteExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [6:0] io_in_sExp,\n input [13:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire roundingMode_odd = io_roundingMode == 3'h6;\n wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(io_in_sExp[5:0]));\n wire _common_underflow_T_4 = roundMask_shift[18] | io_in_sig[13];\n wire [12:0] _GEN = {1'h1, ~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~_common_underflow_T_4};\n wire [12:0] _GEN_0 = {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4, 1'h1};\n wire [12:0] _roundPosBit_T = io_in_sig[13:1] & _GEN & _GEN_0;\n wire [12:0] _anyRoundExtra_T = io_in_sig[12:0] & _GEN_0;\n wire [25:0] _GEN_1 = {_roundPosBit_T, _anyRoundExtra_T};\n wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;\n wire [12:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_1) ? {1'h0, io_in_sig[13:2] | {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4}} + 13'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 13'h0 ? {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _common_underflow_T_4, 1'h1} : 13'h0) : {1'h0, io_in_sig[13:2] & {~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~_common_underflow_T_4}} | (roundingMode_odd & (|_GEN_1) ? _GEN & _GEN_0 : 13'h0);\n wire [7:0] sRoundedExp = {io_in_sExp[6], io_in_sExp} + {6'h0, roundedSig[12:11]};\n wire common_totalUnderflow = $signed(sRoundedExp) < 8'sh8;\n wire isNaNOut = io_invalidExc | io_in_isNaN;\n wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;\n wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;\n wire overflow = commonCase & $signed(sRoundedExp[7:4]) > 4'sh2;\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\n wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);\n wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;\n wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;\n assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) | (isNaNOut ? 6'h38 : 6'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 9'h0} : io_in_sig[13] ? roundedSig[10:1] : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};\n assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, overflow, commonCase & (common_totalUnderflow | (|_GEN_1) & io_in_sExp[6:5] != 2'h1 & (io_in_sig[13] ? roundMask_shift[17] : _common_underflow_T_4) & ~(~(io_in_sig[13] ? roundMask_shift[16] : roundMask_shift[17]) & (io_in_sig[13] ? roundedSig[12] : roundedSig[11]) & (|_roundPosBit_T) & (_overflow_roundMagUp_T & (io_in_sig[13] ? io_in_sig[2] : io_in_sig[1]) | roundMagUp & (|{io_in_sig[13] & io_in_sig[2], io_in_sig[1:0]})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Execution Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// The issue window schedules micro-ops onto a specific execution pipeline\n// A given execution pipeline may contain multiple functional units; one or more\n// read ports, and one or more writeports.\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.rocket.{BP}\nimport freechips.rocketchip.tile\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.ifu.{GetPCFromFtqIO}\nimport boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}\n\n/**\n * Response from Execution Unit. Bundles a MicroOp with data\n *\n * @param dataWidth width of the data coming from the execution unit\n */\nclass ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val data = Bits(dataWidth.W)\n val predicated = Bool() // Was this predicated off?\n val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better\n}\n\n/**\n * Floating Point flag response\n */\nclass FFlagsResp(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val flags = Bits(tile.FPConstants.FLAGS_SZ.W)\n}\n\n\n/**\n * Abstract Top level Execution Unit that wraps lower level functional units to make a\n * multi function execution unit.\n *\n * @param readsIrf does this exe unit need a integer regfile port\n * @param writesIrf does this exe unit need a integer regfile port\n * @param readsFrf does this exe unit need a integer regfile port\n * @param writesFrf does this exe unit need a integer regfile port\n * @param writesLlIrf does this exe unit need a integer regfile port\n * @param writesLlFrf does this exe unit need a integer regfile port\n * @param numBypassStages number of bypass ports for the exe unit\n * @param dataWidth width of the data coming out of the exe unit\n * @param bypassable is the exe unit able to be bypassed\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasAlu does the exe unit have a alu\n * @param hasFpu does the exe unit have a fpu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nabstract class ExecutionUnit(\n val readsIrf : Boolean = false,\n val writesIrf : Boolean = false,\n val readsFrf : Boolean = false,\n val writesFrf : Boolean = false,\n val writesLlIrf : Boolean = false,\n val writesLlFrf : Boolean = false,\n val numBypassStages : Int,\n val dataWidth : Int,\n val bypassable : Boolean = false, // TODO make override def for code clarity\n val alwaysBypassable : Boolean = false,\n val hasMem : Boolean = false,\n val hasCSR : Boolean = false,\n val hasJmpUnit : Boolean = false,\n val hasAlu : Boolean = false,\n val hasFpu : Boolean = false,\n val hasMul : Boolean = false,\n val hasDiv : Boolean = false,\n val hasFdiv : Boolean = false,\n val hasIfpu : Boolean = false,\n val hasFpiu : Boolean = false,\n val hasRocc : Boolean = false\n )(implicit p: Parameters) extends BoomModule\n{\n\n val io = IO(new Bundle {\n val fu_types = Output(Bits(FUC_SZ.W))\n\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n\n val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n val brupdate = Input(new BrUpdateInfo())\n\n\n // only used by the rocc unit\n val rocc = if (hasRocc) new RoCCShimCoreIO else null\n\n // only used by the branch unit\n val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n\n // only used by the fpu unit\n val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by the mem unit\n val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null\n val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null\n\n // TODO move this out of ExecutionUnit\n val com_exception = if (hasMem || hasRocc) Input(Bool()) else null\n })\n\n io.req.ready := false.B\n\n if (writesIrf) {\n io.iresp.valid := false.B\n io.iresp.bits := DontCare\n io.iresp.bits.fflags.valid := false.B\n io.iresp.bits.predicated := false.B\n assert(io.iresp.ready)\n }\n if (writesLlIrf) {\n io.ll_iresp.valid := false.B\n io.ll_iresp.bits := DontCare\n io.ll_iresp.bits.fflags.valid := false.B\n io.ll_iresp.bits.predicated := false.B\n }\n if (writesFrf) {\n io.fresp.valid := false.B\n io.fresp.bits := DontCare\n io.fresp.bits.fflags.valid := false.B\n io.fresp.bits.predicated := false.B\n assert(io.fresp.ready)\n }\n if (writesLlFrf) {\n io.ll_fresp.valid := false.B\n io.ll_fresp.bits := DontCare\n io.ll_fresp.bits.fflags.valid := false.B\n io.ll_fresp.bits.predicated := false.B\n }\n\n // TODO add \"number of fflag ports\", so we can properly account for FPU+Mem combinations\n def hasFFlags : Boolean = hasFpu || hasFdiv\n\n require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),\n \"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.\")\n def hasFcsr = hasIfpu || hasFpu || hasFdiv\n\n require (bypassable || !alwaysBypassable,\n \"[execute] an execution unit must be bypassable if it is always bypassable\")\n\n def supportedFuncUnits = {\n new SupportedFuncUnits(\n alu = hasAlu,\n jmp = hasJmpUnit,\n mem = hasMem,\n muld = hasMul || hasDiv,\n fpu = hasFpu,\n csr = hasCSR,\n fdiv = hasFdiv,\n ifpu = hasIfpu)\n }\n}\n\n/**\n * ALU execution unit that can have a branch, alu, mul, div, int to FP,\n * and memory unit.\n *\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasAlu does the exe unit have a alu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n */\nclass ALUExeUnit(\n hasJmpUnit : Boolean = false,\n hasCSR : Boolean = false,\n hasAlu : Boolean = true,\n hasMul : Boolean = false,\n hasDiv : Boolean = false,\n hasIfpu : Boolean = false,\n hasMem : Boolean = false,\n hasRocc : Boolean = false)\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsIrf = true,\n writesIrf = hasAlu || hasMul || hasDiv,\n writesLlIrf = hasMem || hasRocc,\n writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,\n numBypassStages =\n if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency\n else if (hasAlu) 1 else 0,\n dataWidth = 64 + 1,\n bypassable = hasAlu,\n alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),\n hasCSR = hasCSR,\n hasJmpUnit = hasJmpUnit,\n hasAlu = hasAlu,\n hasMul = hasMul,\n hasDiv = hasDiv,\n hasIfpu = hasIfpu,\n hasMem = hasMem,\n hasRocc = hasRocc)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n require(!(hasRocc && !hasCSR),\n \"RoCC needs to be shared with CSR unit\")\n require(!(hasMem && hasRocc),\n \"We do not support execution unit with both Mem and Rocc writebacks\")\n require(!(hasMem && hasIfpu),\n \"TODO. Currently do not support AluMemExeUnit with FP\")\n\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\") +\n (if (hasAlu) BoomCoreStringPrefix(\" - ALU\") else \"\") +\n (if (hasMul) BoomCoreStringPrefix(\" - Mul\") else \"\") +\n (if (hasDiv) BoomCoreStringPrefix(\" - Div\") else \"\") +\n (if (hasIfpu) BoomCoreStringPrefix(\" - IFPU\") else \"\") +\n (if (hasMem) BoomCoreStringPrefix(\" - Mem\") else \"\") +\n (if (hasRocc) BoomCoreStringPrefix(\" - RoCC\") else \"\")\n\n override def toString: String = out_str.toString\n\n val div_busy = WireInit(false.B)\n val ifpu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n // Specifically the functional units with fast writeback to IRF\n val iresp_fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |\n Mux(hasMul.B, FU_MUL, 0.U) |\n Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |\n Mux(hasCSR.B, FU_CSR, 0.U) |\n Mux(hasJmpUnit.B, FU_JMP, 0.U) |\n Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |\n Mux(hasMem.B, FU_MEM, 0.U)\n\n // ALU Unit -------------------------------\n var alu: ALUUnit = null\n if (hasAlu) {\n alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,\n numStages = numBypassStages,\n dataWidth = xLen))\n alu.io.req.valid := (\n io.req.valid &&\n (io.req.bits.uop.fu_code === FU_ALU ||\n io.req.bits.uop.fu_code === FU_JMP ||\n (io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))\n //ROCC Rocc Commands are taken by the RoCC unit\n\n alu.io.req.bits.uop := io.req.bits.uop\n alu.io.req.bits.kill := io.req.bits.kill\n alu.io.req.bits.rs1_data := io.req.bits.rs1_data\n alu.io.req.bits.rs2_data := io.req.bits.rs2_data\n alu.io.req.bits.rs3_data := DontCare\n alu.io.req.bits.pred_data := io.req.bits.pred_data\n alu.io.resp.ready := DontCare\n alu.io.brupdate := io.brupdate\n\n iresp_fu_units += alu\n\n // Bypassing only applies to ALU\n io.bypass := alu.io.bypass\n\n // branch unit is embedded inside the ALU\n io.brinfo := alu.io.brinfo\n if (hasJmpUnit) {\n alu.io.get_ftq_pc <> io.get_ftq_pc\n }\n }\n\n var rocc: RoCCShim = null\n if (hasRocc) {\n rocc = Module(new RoCCShim)\n rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC\n rocc.io.req.bits := DontCare\n rocc.io.req.bits.uop := io.req.bits.uop\n rocc.io.req.bits.kill := io.req.bits.kill\n rocc.io.req.bits.rs1_data := io.req.bits.rs1_data\n rocc.io.req.bits.rs2_data := io.req.bits.rs2_data\n rocc.io.brupdate := io.brupdate // We should assert on this somewhere\n rocc.io.status := io.status\n rocc.io.exception := io.com_exception\n io.rocc <> rocc.io.core\n\n rocc.io.resp.ready := io.ll_iresp.ready\n io.ll_iresp.valid := rocc.io.resp.valid\n io.ll_iresp.bits.uop := rocc.io.resp.bits.uop\n io.ll_iresp.bits.data := rocc.io.resp.bits.data\n }\n\n\n // Pipelined, IMul Unit ------------------\n var imul: PipelinedMulUnit = null\n if (hasMul) {\n imul = Module(new PipelinedMulUnit(imulLatency, xLen))\n imul.io <> DontCare\n imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)\n imul.io.req.bits.uop := io.req.bits.uop\n imul.io.req.bits.rs1_data := io.req.bits.rs1_data\n imul.io.req.bits.rs2_data := io.req.bits.rs2_data\n imul.io.req.bits.kill := io.req.bits.kill\n imul.io.brupdate := io.brupdate\n iresp_fu_units += imul\n }\n\n var ifpu: IntToFPUnit = null\n if (hasIfpu) {\n ifpu = Module(new IntToFPUnit(latency=intToFpLatency))\n ifpu.io.req <> io.req\n ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)\n ifpu.io.fcsr_rm := io.fcsr_rm\n ifpu.io.brupdate <> io.brupdate\n ifpu.io.resp.ready := DontCare\n\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = intToFpLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := ifpu.io.resp.valid\n queue.io.enq.bits.uop := ifpu.io.resp.bits.uop\n queue.io.enq.bits.data := ifpu.io.resp.bits.data\n queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n io.ll_fresp <> queue.io.deq\n ifpu_busy := !(queue.io.empty)\n assert (queue.io.enq.ready)\n }\n\n // Div/Rem Unit -----------------------\n var div: DivUnit = null\n val div_resp_val = WireInit(false.B)\n if (hasDiv) {\n div = Module(new DivUnit(xLen))\n div.io <> DontCare\n div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B\n div.io.req.bits.uop := io.req.bits.uop\n div.io.req.bits.rs1_data := io.req.bits.rs1_data\n div.io.req.bits.rs2_data := io.req.bits.rs2_data\n div.io.brupdate := io.brupdate\n div.io.req.bits.kill := io.req.bits.kill\n\n // share write port with the pipelined units\n div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))\n\n div_resp_val := div.io.resp.valid\n div_busy := !div.io.req.ready ||\n (io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))\n\n iresp_fu_units += div\n }\n\n // Mem Unit --------------------------\n if (hasMem) {\n require(!hasAlu)\n val maddrcalc = Module(new MemAddrCalcUnit)\n maddrcalc.io.req <> io.req\n maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)\n maddrcalc.io.brupdate <> io.brupdate\n maddrcalc.io.status := io.status\n maddrcalc.io.bp := io.bp\n maddrcalc.io.mcontext := io.mcontext\n maddrcalc.io.scontext := io.scontext\n maddrcalc.io.resp.ready := DontCare\n require(numBypassStages == 0)\n\n io.lsu_io.req := maddrcalc.io.resp\n\n io.ll_iresp <> io.lsu_io.iresp\n if (usingFPU) {\n io.ll_fresp <> io.lsu_io.fresp\n }\n }\n\n // Outputs (Write Port #0) ---------------\n if (writesIrf) {\n io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)\n io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.uop)).toSeq)\n io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)\n\n // pulled out for critical path reasons\n // TODO: Does this make sense as part of the iresp bundle?\n if (hasAlu) {\n io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt\n io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd\n }\n }\n\n assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n (PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),\n \"Multiple functional units are fighting over the write port.\")\n}\n\n/**\n * FPU-only unit, with optional second write-port for ToInt micro-ops.\n *\n * @param hasFpu does the exe unit have a fpu\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nclass FPUExeUnit(\n hasFpu : Boolean = true,\n hasFdiv : Boolean = false,\n hasFpiu : Boolean = false\n )\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsFrf = true,\n writesFrf = true,\n writesLlIrf = hasFpiu,\n writesIrf = false,\n numBypassStages = 0,\n dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,\n bypassable = false,\n hasFpu = hasFpu,\n hasFdiv = hasFdiv,\n hasFpiu = hasFpiu) with tile.HasFPUParameters\n{\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\")\n (if (hasFpu) BoomCoreStringPrefix(\"- FPU (Latency: \" + dfmaLatency + \")\") else \"\") +\n (if (hasFdiv) BoomCoreStringPrefix(\"- FDiv/FSqrt\") else \"\") +\n (if (hasFpiu) BoomCoreStringPrefix(\"- FPIU (writes to Integer RF)\") else \"\")\n\n val fdiv_busy = WireInit(false.B)\n val fpiu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n val fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |\n Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |\n Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)\n\n // FPU Unit -----------------------\n var fpu: FPUUnit = null\n val fpu_resp_val = WireInit(false.B)\n val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fpu_resp_fflags.valid := false.B\n if (hasFpu) {\n fpu = Module(new FPUUnit())\n fpu.io.req.valid := io.req.valid &&\n (io.req.bits.uop.fu_code_is(FU_FPU) ||\n io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.pred_data := false.B\n fpu.io.req.bits.kill := io.req.bits.kill\n fpu.io.fcsr_rm := io.fcsr_rm\n fpu.io.brupdate := io.brupdate\n fpu.io.resp.ready := DontCare\n fpu_resp_val := fpu.io.resp.valid\n fpu_resp_fflags := fpu.io.resp.bits.fflags\n\n fu_units += fpu\n }\n\n // FDiv/FSqrt Unit -----------------------\n var fdivsqrt: FDivSqrtUnit = null\n val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fdiv_resp_fflags := DontCare\n fdiv_resp_fflags.valid := false.B\n if (hasFdiv) {\n fdivsqrt = Module(new FDivSqrtUnit())\n fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)\n fdivsqrt.io.req.bits.uop := io.req.bits.uop\n fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data\n fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data\n fdivsqrt.io.req.bits.rs3_data := DontCare\n fdivsqrt.io.req.bits.pred_data := false.B\n fdivsqrt.io.req.bits.kill := io.req.bits.kill\n fdivsqrt.io.fcsr_rm := io.fcsr_rm\n fdivsqrt.io.brupdate := io.brupdate\n\n // share write port with the pipelined units\n fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.\n\n fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))\n\n fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags\n\n fu_units += fdivsqrt\n }\n\n // Outputs (Write Port #0) ---------------\n\n io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&\n !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))\n io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,\n f.io.resp.bits.uop)).toSeq)\n io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)\n\n // Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------\n\n if (hasFpiu) {\n // TODO instantiate our own fpiu; and remove it from fpu.scala.\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = dfmaLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := (fpu.io.resp.valid &&\n fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&\n fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point\n queue.io.enq.bits.uop := fpu.io.resp.bits.uop\n queue.io.enq.bits.data := fpu.io.resp.bits.data\n queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.\n\n val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = 3)) // Lets us backpressure floating point store data\n fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n fp_sdq.io.enq.bits.uop := io.req.bits.uop\n fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)\n fp_sdq.io.enq.bits.predicated := false.B\n fp_sdq.io.enq.bits.fflags := DontCare\n fp_sdq.io.brupdate := io.brupdate\n fp_sdq.io.flush := io.req.bits.kill\n\n assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))\n\n val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))\n resp_arb.io.in(0) <> queue.io.deq\n resp_arb.io.in(1) <> fp_sdq.io.deq\n io.ll_iresp <> resp_arb.io.out\n\n fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)\n }\n\n override def toString: String = out_str.toString\n}", + "response": "module ALUExeUnit(\n input clock,\n input reset,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [64:0] io_req_bits_rs1_data,\n input [64:0] io_req_bits_rs2_data,\n output io_ll_iresp_valid,\n output [4:0] io_ll_iresp_bits_uop_rob_idx,\n output [5:0] io_ll_iresp_bits_uop_pdst,\n output io_ll_iresp_bits_uop_is_amo,\n output io_ll_iresp_bits_uop_uses_stq,\n output [1:0] io_ll_iresp_bits_uop_dst_rtype,\n output [64:0] io_ll_iresp_bits_data,\n output io_ll_fresp_valid,\n output [6:0] io_ll_fresp_bits_uop_uopc,\n output [7:0] io_ll_fresp_bits_uop_br_mask,\n output [4:0] io_ll_fresp_bits_uop_rob_idx,\n output [2:0] io_ll_fresp_bits_uop_stq_idx,\n output [5:0] io_ll_fresp_bits_uop_pdst,\n output [1:0] io_ll_fresp_bits_uop_mem_size,\n output io_ll_fresp_bits_uop_is_amo,\n output io_ll_fresp_bits_uop_uses_stq,\n output [1:0] io_ll_fresp_bits_uop_dst_rtype,\n output io_ll_fresp_bits_uop_fp_val,\n output [64:0] io_ll_fresp_bits_data,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n output io_lsu_io_req_valid,\n output [6:0] io_lsu_io_req_bits_uop_uopc,\n output [31:0] io_lsu_io_req_bits_uop_inst,\n output [31:0] io_lsu_io_req_bits_uop_debug_inst,\n output io_lsu_io_req_bits_uop_is_rvc,\n output [39:0] io_lsu_io_req_bits_uop_debug_pc,\n output [2:0] io_lsu_io_req_bits_uop_iq_type,\n output [9:0] io_lsu_io_req_bits_uop_fu_code,\n output [3:0] io_lsu_io_req_bits_uop_ctrl_br_type,\n output [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel,\n output [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel,\n output [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel,\n output [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn,\n output io_lsu_io_req_bits_uop_ctrl_fcn_dw,\n output [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd,\n output io_lsu_io_req_bits_uop_ctrl_is_load,\n output io_lsu_io_req_bits_uop_ctrl_is_sta,\n output io_lsu_io_req_bits_uop_ctrl_is_std,\n output [1:0] io_lsu_io_req_bits_uop_iw_state,\n output io_lsu_io_req_bits_uop_is_br,\n output io_lsu_io_req_bits_uop_is_jalr,\n output io_lsu_io_req_bits_uop_is_jal,\n output io_lsu_io_req_bits_uop_is_sfb,\n output [7:0] io_lsu_io_req_bits_uop_br_mask,\n output [2:0] io_lsu_io_req_bits_uop_br_tag,\n output [3:0] io_lsu_io_req_bits_uop_ftq_idx,\n output io_lsu_io_req_bits_uop_edge_inst,\n output [5:0] io_lsu_io_req_bits_uop_pc_lob,\n output io_lsu_io_req_bits_uop_taken,\n output [19:0] io_lsu_io_req_bits_uop_imm_packed,\n output [11:0] io_lsu_io_req_bits_uop_csr_addr,\n output [4:0] io_lsu_io_req_bits_uop_rob_idx,\n output [2:0] io_lsu_io_req_bits_uop_ldq_idx,\n output [2:0] io_lsu_io_req_bits_uop_stq_idx,\n output [1:0] io_lsu_io_req_bits_uop_rxq_idx,\n output [5:0] io_lsu_io_req_bits_uop_pdst,\n output [5:0] io_lsu_io_req_bits_uop_prs1,\n output [5:0] io_lsu_io_req_bits_uop_prs2,\n output [5:0] io_lsu_io_req_bits_uop_prs3,\n output [3:0] io_lsu_io_req_bits_uop_ppred,\n output io_lsu_io_req_bits_uop_prs1_busy,\n output io_lsu_io_req_bits_uop_prs2_busy,\n output io_lsu_io_req_bits_uop_prs3_busy,\n output io_lsu_io_req_bits_uop_ppred_busy,\n output [5:0] io_lsu_io_req_bits_uop_stale_pdst,\n output io_lsu_io_req_bits_uop_exception,\n output [63:0] io_lsu_io_req_bits_uop_exc_cause,\n output io_lsu_io_req_bits_uop_bypassable,\n output [4:0] io_lsu_io_req_bits_uop_mem_cmd,\n output [1:0] io_lsu_io_req_bits_uop_mem_size,\n output io_lsu_io_req_bits_uop_mem_signed,\n output io_lsu_io_req_bits_uop_is_fence,\n output io_lsu_io_req_bits_uop_is_fencei,\n output io_lsu_io_req_bits_uop_is_amo,\n output io_lsu_io_req_bits_uop_uses_ldq,\n output io_lsu_io_req_bits_uop_uses_stq,\n output io_lsu_io_req_bits_uop_is_sys_pc2epc,\n output io_lsu_io_req_bits_uop_is_unique,\n output io_lsu_io_req_bits_uop_flush_on_commit,\n output io_lsu_io_req_bits_uop_ldst_is_rs1,\n output [5:0] io_lsu_io_req_bits_uop_ldst,\n output [5:0] io_lsu_io_req_bits_uop_lrs1,\n output [5:0] io_lsu_io_req_bits_uop_lrs2,\n output [5:0] io_lsu_io_req_bits_uop_lrs3,\n output io_lsu_io_req_bits_uop_ldst_val,\n output [1:0] io_lsu_io_req_bits_uop_dst_rtype,\n output [1:0] io_lsu_io_req_bits_uop_lrs1_rtype,\n output [1:0] io_lsu_io_req_bits_uop_lrs2_rtype,\n output io_lsu_io_req_bits_uop_frs3_en,\n output io_lsu_io_req_bits_uop_fp_val,\n output io_lsu_io_req_bits_uop_fp_single,\n output io_lsu_io_req_bits_uop_xcpt_pf_if,\n output io_lsu_io_req_bits_uop_xcpt_ae_if,\n output io_lsu_io_req_bits_uop_xcpt_ma_if,\n output io_lsu_io_req_bits_uop_bp_debug_if,\n output io_lsu_io_req_bits_uop_bp_xcpt_if,\n output [1:0] io_lsu_io_req_bits_uop_debug_fsrc,\n output [1:0] io_lsu_io_req_bits_uop_debug_tsrc,\n output [63:0] io_lsu_io_req_bits_data,\n output [39:0] io_lsu_io_req_bits_addr,\n output io_lsu_io_req_bits_mxcpt_valid,\n output io_lsu_io_req_bits_sfence_valid,\n output io_lsu_io_req_bits_sfence_bits_rs1,\n output io_lsu_io_req_bits_sfence_bits_rs2,\n output [38:0] io_lsu_io_req_bits_sfence_bits_addr,\n input io_lsu_io_iresp_valid,\n input [4:0] io_lsu_io_iresp_bits_uop_rob_idx,\n input [5:0] io_lsu_io_iresp_bits_uop_pdst,\n input io_lsu_io_iresp_bits_uop_is_amo,\n input io_lsu_io_iresp_bits_uop_uses_stq,\n input [1:0] io_lsu_io_iresp_bits_uop_dst_rtype,\n input [63:0] io_lsu_io_iresp_bits_data,\n input io_lsu_io_fresp_valid,\n input [6:0] io_lsu_io_fresp_bits_uop_uopc,\n input [7:0] io_lsu_io_fresp_bits_uop_br_mask,\n input [4:0] io_lsu_io_fresp_bits_uop_rob_idx,\n input [2:0] io_lsu_io_fresp_bits_uop_stq_idx,\n input [5:0] io_lsu_io_fresp_bits_uop_pdst,\n input [1:0] io_lsu_io_fresp_bits_uop_mem_size,\n input io_lsu_io_fresp_bits_uop_is_amo,\n input io_lsu_io_fresp_bits_uop_uses_stq,\n input [1:0] io_lsu_io_fresp_bits_uop_dst_rtype,\n input io_lsu_io_fresp_bits_uop_fp_val,\n input [64:0] io_lsu_io_fresp_bits_data\n);\n\n wire [64:0] _maddrcalc_io_resp_bits_data;\n MemAddrCalcUnit maddrcalc (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid & io_req_bits_uop_fu_code[2]),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_inst (io_req_bits_uop_inst),\n .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst),\n .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),\n .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc),\n .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type),\n .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code),\n .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),\n .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),\n .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),\n .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),\n .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),\n .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),\n .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),\n .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state),\n .io_req_bits_uop_is_br (io_req_bits_uop_is_br),\n .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),\n .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),\n .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),\n .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),\n .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),\n .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),\n .io_req_bits_uop_taken (io_req_bits_uop_taken),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),\n .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),\n .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_prs1 (io_req_bits_uop_prs1),\n .io_req_bits_uop_prs2 (io_req_bits_uop_prs2),\n .io_req_bits_uop_prs3 (io_req_bits_uop_prs3),\n .io_req_bits_uop_ppred (io_req_bits_uop_ppred),\n .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),\n .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),\n .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),\n .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),\n .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),\n .io_req_bits_uop_exception (io_req_bits_uop_exception),\n .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),\n .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size),\n .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed),\n .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence),\n .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),\n .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique),\n .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),\n .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),\n .io_req_bits_uop_ldst (io_req_bits_uop_ldst),\n .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1),\n .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2),\n .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3),\n .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),\n .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),\n .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en),\n .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),\n .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single),\n .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),\n .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),\n .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),\n .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),\n .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),\n .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),\n .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),\n .io_req_bits_rs1_data (io_req_bits_rs1_data),\n .io_req_bits_rs2_data (io_req_bits_rs2_data),\n .io_resp_valid (io_lsu_io_req_valid),\n .io_resp_bits_uop_uopc (io_lsu_io_req_bits_uop_uopc),\n .io_resp_bits_uop_inst (io_lsu_io_req_bits_uop_inst),\n .io_resp_bits_uop_debug_inst (io_lsu_io_req_bits_uop_debug_inst),\n .io_resp_bits_uop_is_rvc (io_lsu_io_req_bits_uop_is_rvc),\n .io_resp_bits_uop_debug_pc (io_lsu_io_req_bits_uop_debug_pc),\n .io_resp_bits_uop_iq_type (io_lsu_io_req_bits_uop_iq_type),\n .io_resp_bits_uop_fu_code (io_lsu_io_req_bits_uop_fu_code),\n .io_resp_bits_uop_ctrl_br_type (io_lsu_io_req_bits_uop_ctrl_br_type),\n .io_resp_bits_uop_ctrl_op1_sel (io_lsu_io_req_bits_uop_ctrl_op1_sel),\n .io_resp_bits_uop_ctrl_op2_sel (io_lsu_io_req_bits_uop_ctrl_op2_sel),\n .io_resp_bits_uop_ctrl_imm_sel (io_lsu_io_req_bits_uop_ctrl_imm_sel),\n .io_resp_bits_uop_ctrl_op_fcn (io_lsu_io_req_bits_uop_ctrl_op_fcn),\n .io_resp_bits_uop_ctrl_fcn_dw (io_lsu_io_req_bits_uop_ctrl_fcn_dw),\n .io_resp_bits_uop_ctrl_csr_cmd (io_lsu_io_req_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_uop_ctrl_is_load (io_lsu_io_req_bits_uop_ctrl_is_load),\n .io_resp_bits_uop_ctrl_is_sta (io_lsu_io_req_bits_uop_ctrl_is_sta),\n .io_resp_bits_uop_ctrl_is_std (io_lsu_io_req_bits_uop_ctrl_is_std),\n .io_resp_bits_uop_iw_state (io_lsu_io_req_bits_uop_iw_state),\n .io_resp_bits_uop_is_br (io_lsu_io_req_bits_uop_is_br),\n .io_resp_bits_uop_is_jalr (io_lsu_io_req_bits_uop_is_jalr),\n .io_resp_bits_uop_is_jal (io_lsu_io_req_bits_uop_is_jal),\n .io_resp_bits_uop_is_sfb (io_lsu_io_req_bits_uop_is_sfb),\n .io_resp_bits_uop_br_mask (io_lsu_io_req_bits_uop_br_mask),\n .io_resp_bits_uop_br_tag (io_lsu_io_req_bits_uop_br_tag),\n .io_resp_bits_uop_ftq_idx (io_lsu_io_req_bits_uop_ftq_idx),\n .io_resp_bits_uop_edge_inst (io_lsu_io_req_bits_uop_edge_inst),\n .io_resp_bits_uop_pc_lob (io_lsu_io_req_bits_uop_pc_lob),\n .io_resp_bits_uop_taken (io_lsu_io_req_bits_uop_taken),\n .io_resp_bits_uop_imm_packed (io_lsu_io_req_bits_uop_imm_packed),\n .io_resp_bits_uop_csr_addr (io_lsu_io_req_bits_uop_csr_addr),\n .io_resp_bits_uop_rob_idx (io_lsu_io_req_bits_uop_rob_idx),\n .io_resp_bits_uop_ldq_idx (io_lsu_io_req_bits_uop_ldq_idx),\n .io_resp_bits_uop_stq_idx (io_lsu_io_req_bits_uop_stq_idx),\n .io_resp_bits_uop_rxq_idx (io_lsu_io_req_bits_uop_rxq_idx),\n .io_resp_bits_uop_pdst (io_lsu_io_req_bits_uop_pdst),\n .io_resp_bits_uop_prs1 (io_lsu_io_req_bits_uop_prs1),\n .io_resp_bits_uop_prs2 (io_lsu_io_req_bits_uop_prs2),\n .io_resp_bits_uop_prs3 (io_lsu_io_req_bits_uop_prs3),\n .io_resp_bits_uop_ppred (io_lsu_io_req_bits_uop_ppred),\n .io_resp_bits_uop_prs1_busy (io_lsu_io_req_bits_uop_prs1_busy),\n .io_resp_bits_uop_prs2_busy (io_lsu_io_req_bits_uop_prs2_busy),\n .io_resp_bits_uop_prs3_busy (io_lsu_io_req_bits_uop_prs3_busy),\n .io_resp_bits_uop_ppred_busy (io_lsu_io_req_bits_uop_ppred_busy),\n .io_resp_bits_uop_stale_pdst (io_lsu_io_req_bits_uop_stale_pdst),\n .io_resp_bits_uop_exception (io_lsu_io_req_bits_uop_exception),\n .io_resp_bits_uop_exc_cause (io_lsu_io_req_bits_uop_exc_cause),\n .io_resp_bits_uop_bypassable (io_lsu_io_req_bits_uop_bypassable),\n .io_resp_bits_uop_mem_cmd (io_lsu_io_req_bits_uop_mem_cmd),\n .io_resp_bits_uop_mem_size (io_lsu_io_req_bits_uop_mem_size),\n .io_resp_bits_uop_mem_signed (io_lsu_io_req_bits_uop_mem_signed),\n .io_resp_bits_uop_is_fence (io_lsu_io_req_bits_uop_is_fence),\n .io_resp_bits_uop_is_fencei (io_lsu_io_req_bits_uop_is_fencei),\n .io_resp_bits_uop_is_amo (io_lsu_io_req_bits_uop_is_amo),\n .io_resp_bits_uop_uses_ldq (io_lsu_io_req_bits_uop_uses_ldq),\n .io_resp_bits_uop_uses_stq (io_lsu_io_req_bits_uop_uses_stq),\n .io_resp_bits_uop_is_sys_pc2epc (io_lsu_io_req_bits_uop_is_sys_pc2epc),\n .io_resp_bits_uop_is_unique (io_lsu_io_req_bits_uop_is_unique),\n .io_resp_bits_uop_flush_on_commit (io_lsu_io_req_bits_uop_flush_on_commit),\n .io_resp_bits_uop_ldst_is_rs1 (io_lsu_io_req_bits_uop_ldst_is_rs1),\n .io_resp_bits_uop_ldst (io_lsu_io_req_bits_uop_ldst),\n .io_resp_bits_uop_lrs1 (io_lsu_io_req_bits_uop_lrs1),\n .io_resp_bits_uop_lrs2 (io_lsu_io_req_bits_uop_lrs2),\n .io_resp_bits_uop_lrs3 (io_lsu_io_req_bits_uop_lrs3),\n .io_resp_bits_uop_ldst_val (io_lsu_io_req_bits_uop_ldst_val),\n .io_resp_bits_uop_dst_rtype (io_lsu_io_req_bits_uop_dst_rtype),\n .io_resp_bits_uop_lrs1_rtype (io_lsu_io_req_bits_uop_lrs1_rtype),\n .io_resp_bits_uop_lrs2_rtype (io_lsu_io_req_bits_uop_lrs2_rtype),\n .io_resp_bits_uop_frs3_en (io_lsu_io_req_bits_uop_frs3_en),\n .io_resp_bits_uop_fp_val (io_lsu_io_req_bits_uop_fp_val),\n .io_resp_bits_uop_fp_single (io_lsu_io_req_bits_uop_fp_single),\n .io_resp_bits_uop_xcpt_pf_if (io_lsu_io_req_bits_uop_xcpt_pf_if),\n .io_resp_bits_uop_xcpt_ae_if (io_lsu_io_req_bits_uop_xcpt_ae_if),\n .io_resp_bits_uop_xcpt_ma_if (io_lsu_io_req_bits_uop_xcpt_ma_if),\n .io_resp_bits_uop_bp_debug_if (io_lsu_io_req_bits_uop_bp_debug_if),\n .io_resp_bits_uop_bp_xcpt_if (io_lsu_io_req_bits_uop_bp_xcpt_if),\n .io_resp_bits_uop_debug_fsrc (io_lsu_io_req_bits_uop_debug_fsrc),\n .io_resp_bits_uop_debug_tsrc (io_lsu_io_req_bits_uop_debug_tsrc),\n .io_resp_bits_data (_maddrcalc_io_resp_bits_data),\n .io_resp_bits_addr (io_lsu_io_req_bits_addr),\n .io_resp_bits_mxcpt_valid (io_lsu_io_req_bits_mxcpt_valid),\n .io_resp_bits_sfence_valid (io_lsu_io_req_bits_sfence_valid),\n .io_resp_bits_sfence_bits_rs1 (io_lsu_io_req_bits_sfence_bits_rs1),\n .io_resp_bits_sfence_bits_rs2 (io_lsu_io_req_bits_sfence_bits_rs2),\n .io_resp_bits_sfence_bits_addr (io_lsu_io_req_bits_sfence_bits_addr),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask)\n );\n assign io_ll_iresp_valid = io_lsu_io_iresp_valid;\n assign io_ll_iresp_bits_uop_rob_idx = io_lsu_io_iresp_bits_uop_rob_idx;\n assign io_ll_iresp_bits_uop_pdst = io_lsu_io_iresp_bits_uop_pdst;\n assign io_ll_iresp_bits_uop_is_amo = io_lsu_io_iresp_bits_uop_is_amo;\n assign io_ll_iresp_bits_uop_uses_stq = io_lsu_io_iresp_bits_uop_uses_stq;\n assign io_ll_iresp_bits_uop_dst_rtype = io_lsu_io_iresp_bits_uop_dst_rtype;\n assign io_ll_iresp_bits_data = {1'h0, io_lsu_io_iresp_bits_data};\n assign io_ll_fresp_valid = io_lsu_io_fresp_valid;\n assign io_ll_fresp_bits_uop_uopc = io_lsu_io_fresp_bits_uop_uopc;\n assign io_ll_fresp_bits_uop_br_mask = io_lsu_io_fresp_bits_uop_br_mask;\n assign io_ll_fresp_bits_uop_rob_idx = io_lsu_io_fresp_bits_uop_rob_idx;\n assign io_ll_fresp_bits_uop_stq_idx = io_lsu_io_fresp_bits_uop_stq_idx;\n assign io_ll_fresp_bits_uop_pdst = io_lsu_io_fresp_bits_uop_pdst;\n assign io_ll_fresp_bits_uop_mem_size = io_lsu_io_fresp_bits_uop_mem_size;\n assign io_ll_fresp_bits_uop_is_amo = io_lsu_io_fresp_bits_uop_is_amo;\n assign io_ll_fresp_bits_uop_uses_stq = io_lsu_io_fresp_bits_uop_uses_stq;\n assign io_ll_fresp_bits_uop_dst_rtype = io_lsu_io_fresp_bits_uop_dst_rtype;\n assign io_ll_fresp_bits_uop_fp_val = io_lsu_io_fresp_bits_uop_fp_val;\n assign io_ll_fresp_bits_data = io_lsu_io_fresp_bits_data;\n assign io_lsu_io_req_bits_data = _maddrcalc_io_resp_bits_data[63:0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLBFromBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module ram_3x77(\n input [1:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [76:0] R0_data,\n input [1:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [76:0] W0_data\n);\n\n reg [76:0] Memory[0:2];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundRawFNToRecFN_e11_s53_1(\n input io_invalidExc,\n input io_infiniteExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [12:0] io_in_sExp,\n input [55:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 roundAnyRawFNToRecFN (\n .io_invalidExc (io_invalidExc),\n .io_infiniteExc (io_infiniteExc),\n .io_in_isNaN (io_in_isNaN),\n .io_in_isInf (io_in_isInf),\n .io_in_isZero (io_in_isZero),\n .io_in_sign (io_in_sign),\n .io_in_sExp (io_in_sExp),\n .io_in_sig (io_in_sig),\n .io_roundingMode (io_roundingMode),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Ported from Rocket-Chip\n// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.rocket._\n\nimport boom.v3.common._\nimport boom.v3.exu.BrUpdateInfo\nimport boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}\n\nclass BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)\n with HasL1HellaCacheParameters\n{\n // miss info\n val tag_match = Bool()\n val old_meta = new L1Metadata\n val way_en = UInt(nWays.W)\n\n // Used in the MSHRs\n val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)\n}\n\n\nclass BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val id = Input(UInt())\n\n val req_pri_val = Input(Bool())\n val req_pri_rdy = Output(Bool())\n val req_sec_val = Input(Bool())\n val req_sec_rdy = Output(Bool())\n\n val clear_prefetch = Input(Bool())\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val req = Input(new BoomDCacheReqInternal)\n val req_is_probe = Input(Bool())\n\n val idx = Output(Valid(UInt()))\n val way = Output(Valid(UInt()))\n val tag = Output(Valid(UInt()))\n\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val refill = Decoupled(new L1DataWriteReq)\n\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n // To inform the prefetcher when we are commiting the fetch of this line\n val commit_val = Output(Bool())\n val commit_addr = Output(UInt(coreMaxAddrBits.W))\n val commit_coh = Output(new ClientMetadata)\n\n // Reading from the line buffer\n val lb_read = Decoupled(new LineBufferReadReq)\n val lb_resp = Input(UInt(encRowBits.W))\n val lb_write = Decoupled(new LineBufferWriteReq)\n\n // Replays go through the cache pipeline again\n val replay = Decoupled(new BoomDCacheReqInternal)\n // Resp go straight out to the core\n val resp = Decoupled(new BoomDCacheResp)\n\n // Writeback unit tells us when it is done processing our wb\n val wb_resp = Input(Bool())\n\n val probe_rdy = Output(Bool())\n })\n\n // TODO: Optimize this. We don't want to mess with cache during speculation\n // s_refill_req : Make a request for a new cache line\n // s_refill_resp : Store the refill response into our buffer\n // s_drain_rpq_loads : Drain out loads from the rpq\n // : If miss was misspeculated, go to s_invalid\n // s_wb_req : Write back the evicted cache line\n // s_wb_resp : Finish writing back the evicted cache line\n // s_meta_write_req : Write the metadata for new cache lne\n // s_meta_write_resp :\n\n val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)\n val state = RegInit(s_invalid)\n\n val req = Reg(new BoomDCacheReqInternal)\n val req_idx = req.addr(untagBits-1, blockOffBits)\n val req_tag = req.addr >> untagBits\n val req_block_addr = (req.addr >> blockOffBits) << blockOffBits\n val req_needs_wb = RegInit(false.B)\n\n val new_coh = RegInit(ClientMetadata.onReset)\n val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)\n val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2\n val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)\n\n // We only accept secondary misses if the original request had sufficient permissions\n val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =\n new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)\n\n val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)\n val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&\n !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses\n\n val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))\n rpq.io.brupdate := io.brupdate\n rpq.io.flush := io.exception\n assert(!(state === s_invalid && !rpq.io.empty))\n\n rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)\n rpq.io.enq.bits := io.req\n rpq.io.deq.ready := false.B\n\n\n val grantack = Reg(Valid(new TLBundleE(edge.bundle)))\n val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))\n val commit_line = Reg(Bool())\n val grant_had_data = Reg(Bool())\n val finish_to_prefetch = Reg(Bool())\n\n // Block probes if a tag write we started is still in the pipeline\n val meta_hazard = RegInit(0.U(2.W))\n when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }\n when (io.meta_write.fire) { meta_hazard := 1.U }\n io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))\n io.idx.valid := state =/= s_invalid\n io.tag.valid := state =/= s_invalid\n io.way.valid := !state.isOneOf(s_invalid, s_prefetch)\n io.idx.bits := req_idx\n io.tag.bits := req_tag\n io.way.bits := req.way_en\n\n io.meta_write.valid := false.B\n io.meta_write.bits := DontCare\n io.req_pri_rdy := false.B\n io.req_sec_rdy := sec_rdy && rpq.io.enq.ready\n io.mem_acquire.valid := false.B\n io.mem_acquire.bits := DontCare\n io.refill.valid := false.B\n io.refill.bits := DontCare\n io.replay.valid := false.B\n io.replay.bits := DontCare\n io.wb_req.valid := false.B\n io.wb_req.bits := DontCare\n io.resp.valid := false.B\n io.resp.bits := DontCare\n io.commit_val := false.B\n io.commit_addr := req.addr\n io.commit_coh := coh_on_grant\n io.meta_read.valid := false.B\n io.meta_read.bits := DontCare\n io.mem_finish.valid := false.B\n io.mem_finish.bits := DontCare\n io.lb_write.valid := false.B\n io.lb_write.bits := DontCare\n io.lb_read.valid := false.B\n io.lb_read.bits := DontCare\n io.mem_grant.ready := false.B\n\n when (io.req_sec_val && io.req_sec_rdy) {\n req.uop.mem_cmd := dirtier_cmd\n when (is_hit_again) {\n new_coh := dirtier_coh\n }\n }\n\n def handle_pri_req(old_state: UInt): UInt = {\n val new_state = WireInit(old_state)\n grantack.valid := false.B\n refill_ctr := 0.U\n assert(rpq.io.enq.ready)\n req := io.req\n val old_coh = io.req.old_meta.coh\n req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back\n when (io.req.tag_match) {\n val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // set dirty bit\n assert(isWrite(io.req.uop.mem_cmd))\n new_coh := coh_on_hit\n new_state := s_drain_rpq\n } .otherwise { // upgrade permissions\n new_coh := old_coh\n new_state := s_refill_req\n }\n } .otherwise { // refill and writeback if necessary\n new_coh := ClientMetadata.onReset\n new_state := s_refill_req\n }\n new_state\n }\n\n when (state === s_invalid) {\n io.req_pri_rdy := true.B\n grant_had_data := false.B\n\n when (io.req_pri_val && io.req_pri_rdy) {\n state := handle_pri_req(state)\n }\n } .elsewhen (state === s_refill_req) {\n io.mem_acquire.valid := true.B\n // TODO: Use AcquirePerm if just doing permissions acquire\n io.mem_acquire.bits := edge.AcquireBlock(\n fromSource = io.id,\n toAddress = Cat(req_tag, req_idx) << blockOffBits,\n lgSize = lgCacheBlockBytes.U,\n growPermissions = grow_param)._2\n when (io.mem_acquire.fire) {\n state := s_refill_resp\n }\n } .elsewhen (state === s_refill_resp) {\n when (edge.hasData(io.mem_grant.bits)) {\n io.mem_grant.ready := io.lb_write.ready\n io.lb_write.valid := io.mem_grant.valid\n io.lb_write.bits.id := io.id\n io.lb_write.bits.offset := refill_address_inc >> rowOffBits\n io.lb_write.bits.data := io.mem_grant.bits.data\n } .otherwise {\n io.mem_grant.ready := true.B\n }\n\n when (io.mem_grant.fire) {\n grant_had_data := edge.hasData(io.mem_grant.bits)\n }\n when (refill_done) {\n grantack.valid := edge.isRequest(io.mem_grant.bits)\n grantack.bits := edge.GrantAck(io.mem_grant.bits)\n state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)\n assert(!(!grant_had_data && req_needs_wb))\n commit_line := false.B\n new_coh := coh_on_grant\n\n }\n } .elsewhen (state === s_drain_rpq_loads) {\n val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&\n !isWrite(rpq.io.deq.bits.uop.mem_cmd) &&\n (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay\n // drain all loads for now\n val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))\n val data = io.lb_resp\n val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))\n val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,\n Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),\n data_word, false.B, wordBytes)\n\n\n rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load\n io.lb_read.valid := rpq.io.deq.valid && drain_load\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits\n\n io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load\n io.resp.bits.uop := rpq.io.deq.bits.uop\n io.resp.bits.data := loadgen.data\n io.resp.bits.is_hella := rpq.io.deq.bits.is_hella\n when (rpq.io.deq.fire) {\n commit_line := true.B\n }\n .elsewhen (rpq.io.empty && !commit_line)\n {\n when (!rpq.io.enq.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := enablePrefetching.B\n }\n } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {\n // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired\n // The prefetcher should consider fetching the next line\n io.commit_val := true.B\n state := s_meta_read\n }\n } .elsewhen (state === s_meta_read) {\n io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)\n io.meta_read.bits.idx := req_idx\n io.meta_read.bits.tag := req_tag\n io.meta_read.bits.way_en := req.way_en\n when (io.meta_read.fire) {\n state := s_meta_resp_1\n }\n } .elsewhen (state === s_meta_resp_1) {\n state := s_meta_resp_2\n } .elsewhen (state === s_meta_resp_2) {\n val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1\n state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read\n Mux(needs_wb, s_meta_clear, s_commit_line))\n } .elsewhen (state === s_meta_clear) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := coh_on_clear\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n\n when (io.meta_write.fire) {\n state := s_wb_req\n }\n } .elsewhen (state === s_wb_req) {\n io.wb_req.valid := true.B\n\n io.wb_req.bits.tag := req.old_meta.tag\n io.wb_req.bits.idx := req_idx\n io.wb_req.bits.param := shrink_param\n io.wb_req.bits.way_en := req.way_en\n io.wb_req.bits.source := io.id\n io.wb_req.bits.voluntary := true.B\n when (io.wb_req.fire) {\n state := s_wb_resp\n }\n } .elsewhen (state === s_wb_resp) {\n when (io.wb_resp) {\n state := s_commit_line\n }\n } .elsewhen (state === s_commit_line) {\n io.lb_read.valid := true.B\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := refill_ctr\n\n io.refill.valid := io.lb_read.fire\n io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)\n io.refill.bits.way_en := req.way_en\n io.refill.bits.wmask := ~(0.U(rowWords.W))\n io.refill.bits.data := io.lb_resp\n when (io.refill.fire) {\n refill_ctr := refill_ctr + 1.U\n when (refill_ctr === (cacheDataBeats - 1).U) {\n state := s_drain_rpq\n }\n }\n } .elsewhen (state === s_drain_rpq) {\n io.replay <> rpq.io.deq\n io.replay.bits.way_en := req.way_en\n io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {\n // Set dirty bit\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)\n assert(is_hit, \"We still don't have permissions for this store\")\n new_coh := coh_on_hit\n }\n when (rpq.io.empty && !rpq.io.enq.valid) {\n state := s_meta_write_req\n }\n } .elsewhen (state === s_meta_write_req) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := new_coh\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n when (io.meta_write.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := false.B\n }\n } .elsewhen (state === s_mem_finish_1) {\n io.mem_finish.valid := grantack.valid\n io.mem_finish.bits := grantack.bits\n when (io.mem_finish.fire || !grantack.valid) {\n grantack.valid := false.B\n state := s_mem_finish_2\n }\n } .elsewhen (state === s_mem_finish_2) {\n state := Mux(finish_to_prefetch, s_prefetch, s_invalid)\n } .elsewhen (state === s_prefetch) {\n io.req_pri_rdy := true.B\n when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {\n state := s_invalid\n } .elsewhen (io.req_sec_val && io.req_sec_rdy) {\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // Proceed with refill\n new_coh := coh_on_hit\n state := s_meta_read\n } .otherwise { // Reacquire this line\n new_coh := ClientMetadata.onReset\n state := s_refill_req\n }\n } .elsewhen (io.req_pri_val && io.req_pri_rdy) {\n grant_had_data := false.B\n state := handle_pri_req(state)\n }\n }\n}\n\nclass BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new BoomDCacheReq))\n val resp = Decoupled(new BoomDCacheResp)\n val mem_access = Decoupled(new TLBundleA(edge.bundle))\n val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))\n\n // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative\n })\n\n def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)\n\n def wordFromBeat(addr: UInt, dat: UInt) = {\n val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))\n (dat >> shift)(wordBits-1, 0)\n }\n\n val req = Reg(new BoomDCacheReq)\n val grant_word = Reg(UInt(wordBits.W))\n\n val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)\n\n val state = RegInit(s_idle)\n io.req.ready := state === s_idle\n\n val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)\n\n val a_source = id.U\n val a_address = req.addr\n val a_size = req.uop.mem_size\n val a_data = Fill(beatWords, req.data)\n\n val get = edge.Get(a_source, a_address, a_size)._2\n val put = edge.Put(a_source, a_address, a_size, a_data)._2\n val atomics = if (edge.manager.anySupportLogical) {\n MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(\n M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,\n M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,\n M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,\n M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,\n M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,\n M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,\n M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,\n M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,\n M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))\n } else {\n // If no managers support atomics, assert fail if processor asks for them\n assert(state === s_idle || !isAMO(req.uop.mem_cmd))\n (0.U).asTypeOf(new TLBundleA(edge.bundle))\n }\n assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n\n io.mem_access.valid := state === s_mem_access\n io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))\n\n val send_resp = isRead(req.uop.mem_cmd)\n\n io.resp.valid := (state === s_resp) && send_resp\n io.resp.bits.is_hella := req.is_hella\n io.resp.bits.uop := req.uop\n io.resp.bits.data := loadgen.data\n\n when (io.req.fire) {\n req := io.req.bits\n state := s_mem_access\n }\n when (io.mem_access.fire) {\n state := s_mem_ack\n }\n when (state === s_mem_ack && io.mem_ack.valid) {\n state := s_resp\n when (isRead(req.uop.mem_cmd)) {\n grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)\n }\n }\n when (state === s_resp) {\n when (!send_resp || io.resp.fire) {\n state := s_idle\n }\n }\n}\n\nclass LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val offset = UInt(log2Ceil(cacheDataBeats).W)\n def lb_addr = Cat(id, offset)\n}\n\nclass LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)\n{\n val data = UInt(encRowBits.W)\n}\n\nclass LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe\n val req_is_probe = Input(Vec(memWidth, Bool()))\n val resp = Decoupled(new BoomDCacheResp)\n val secondary_miss = Output(Vec(memWidth, Bool()))\n val block_hit = Output(Vec(memWidth, Bool()))\n\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val refill = Decoupled(new L1DataWriteReq)\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val replay = Decoupled(new BoomDCacheReqInternal)\n val prefetch = Decoupled(new BoomDCacheReq)\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence\n\n val wb_resp = Input(Bool())\n\n val fence_rdy = Output(Bool())\n val probe_rdy = Output(Bool())\n })\n\n val req_idx = OHToUInt(io.req.map(_.valid))\n val req = io.req(req_idx)\n val req_is_probe = io.req_is_probe(0)\n\n for (w <- 0 until memWidth)\n io.req(w).ready := false.B\n\n val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)\n else Module(new NullPrefetcher)\n\n io.prefetch <> prefetcher.io.prefetch\n\n\n val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)\n\n // --------------------\n // The MSHR SDQ\n val sdq_val = RegInit(0.U(cfg.nSDQ.W))\n val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))\n val sdq_rdy = !sdq_val.andR\n val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)\n val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))\n\n when (sdq_enq) {\n sdq(sdq_alloc_id) := req.bits.data\n }\n\n // --------------------\n // The LineBuffer Data\n // Holds refilling lines, prefetched lines\n val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))\n val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))\n val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))\n\n lb_read_arb.io.out.ready := false.B\n lb_write_arb.io.out.ready := true.B\n\n val lb_read_data = WireInit(0.U(encRowBits.W))\n when (lb_write_arb.io.out.fire) {\n lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)\n } .otherwise {\n lb_read_arb.io.out.ready := true.B\n when (lb_read_arb.io.out.fire) {\n lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)\n }\n }\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n\n\n\n val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n\n val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))\n val idx_match = widthMap(w => idx_matches(w).reduce(_||_))\n val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))\n\n val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))\n\n val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))\n val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))\n val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))\n val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))\n val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))\n val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))\n\n val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))\n val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))\n val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))\n\n var sec_rdy = false.B\n\n io.fence_rdy := true.B\n io.probe_rdy := true.B\n io.mem_grant.ready := false.B\n\n val mshr_alloc_idx = Wire(UInt())\n val pri_rdy = WireInit(false.B)\n val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)\n val mshrs = (0 until cfg.nMSHRs) map { i =>\n val mshr = Module(new BoomMSHR)\n mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)\n\n for (w <- 0 until memWidth) {\n idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)\n tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits\n way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en\n }\n wb_tag_list(i) := mshr.io.wb_req.bits.tag\n\n\n\n mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val\n when (i.U === mshr_alloc_idx) {\n pri_rdy := mshr.io.req_pri_rdy\n }\n\n mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable\n mshr.io.req := req.bits\n mshr.io.req_is_probe := req_is_probe\n mshr.io.req.sdq_id := sdq_alloc_id\n\n // Clear because of a FENCE, a request to the same idx as a prefetched line,\n // a probe to that prefetched line, all mshrs are in use\n mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||\n (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||\n (req_is_probe && idx_matches(req_idx)(i)))\n mshr.io.brupdate := io.brupdate\n mshr.io.exception := io.exception\n mshr.io.rob_pnr_idx := io.rob_pnr_idx\n mshr.io.rob_head_idx := io.rob_head_idx\n\n mshr.io.prober_state := io.prober_state\n\n mshr.io.wb_resp := io.wb_resp\n\n meta_write_arb.io.in(i) <> mshr.io.meta_write\n meta_read_arb.io.in(i) <> mshr.io.meta_read\n mshr.io.meta_resp := io.meta_resp\n wb_req_arb.io.in(i) <> mshr.io.wb_req\n replay_arb.io.in(i) <> mshr.io.replay\n refill_arb.io.in(i) <> mshr.io.refill\n\n lb_read_arb.io.in(i) <> mshr.io.lb_read\n mshr.io.lb_resp := lb_read_data\n lb_write_arb.io.in(i) <> mshr.io.lb_write\n\n commit_vals(i) := mshr.io.commit_val\n commit_addrs(i) := mshr.io.commit_addr\n commit_cohs(i) := mshr.io.commit_coh\n\n mshr.io.mem_grant.valid := false.B\n mshr.io.mem_grant.bits := DontCare\n when (io.mem_grant.bits.source === i.U) {\n mshr.io.mem_grant <> io.mem_grant\n }\n\n sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)\n resp_arb.io.in(i) <> mshr.io.resp\n\n when (!mshr.io.req_pri_rdy) {\n io.fence_rdy := false.B\n }\n for (w <- 0 until memWidth) {\n when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {\n io.probe_rdy := false.B\n }\n }\n\n mshr\n }\n\n // Try to round-robin the MSHRs\n val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))\n mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))\n when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }\n\n\n\n io.meta_write <> meta_write_arb.io.out\n io.meta_read <> meta_read_arb.io.out\n io.wb_req <> wb_req_arb.io.out\n\n val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))\n\n\n var mmio_rdy = false.B\n\n val mmios = (0 until nIOMSHRs) map { i =>\n val id = cfg.nMSHRs + 1 + i // +1 for wb unit\n val mshr = Module(new BoomIOMSHR(id))\n\n mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready\n mmio_alloc_arb.io.in(i).bits := DontCare\n mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready\n mshr.io.req.bits := req.bits\n\n mmio_rdy = mmio_rdy || mshr.io.req.ready\n\n mshr.io.mem_ack.bits := io.mem_grant.bits\n mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U\n when (io.mem_grant.bits.source === id.U) {\n io.mem_grant.ready := true.B\n }\n\n resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp\n when (!mshr.io.req.ready) {\n io.fence_rdy := false.B\n }\n mshr\n }\n\n mmio_alloc_arb.io.out.ready := req.valid && !cacheable\n\n TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))\n TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))\n\n val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))\n respq.io.brupdate := io.brupdate\n respq.io.flush := io.exception\n respq.io.enq <> resp_arb.io.out\n io.resp <> respq.io.deq\n\n for (w <- 0 until memWidth) {\n io.req(w).ready := (w.U === req_idx) &&\n Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))\n io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)\n io.block_hit(w) := idx_match(w) && tag_match(w)\n }\n io.refill <> refill_arb.io.out\n\n val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)\n\n io.replay <> replay_arb.io.out\n io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)\n\n when (io.replay.valid || sdq_enq) {\n sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |\n PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)\n }\n\n prefetcher.io.mshr_avail := RegNext(pri_rdy)\n prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))\n prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))\n prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))\n}", + "response": "module lb_16x64(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n reg [63:0] Memory[0:15];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module tail_21x6(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [4:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [5:0] R1_data,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:20];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, WrapInc}\nimport scala.math.min\n\n\n\nclass BIMMeta(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomFrontendParameters\n{\n val bims = Vec(bankWidth, UInt(2.W))\n}\n\ncase class BoomBIMParams(\n nSets: Int = 2048\n)\n\nclass BIMBranchPredictorBank(params: BoomBIMParams = BoomBIMParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n\n require(isPow2(nSets))\n\n val nWrBypassEntries = 2\n\n def bimWrite(v: UInt, taken: Bool): UInt = {\n val old_bim_sat_taken = v === 3.U\n val old_bim_sat_ntaken = v === 0.U\n Mux(old_bim_sat_taken && taken, 3.U,\n Mux(old_bim_sat_ntaken && !taken, 0.U,\n Mux(taken, v + 1.U, v - 1.U)))\n }\n val s2_meta = Wire(new BIMMeta)\n override val metaSz = s2_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n\n val data = SyncReadMem(nSets, Vec(bankWidth, UInt(2.W)))\n\n val mems = Seq((\"bim\", nSets, bankWidth * 2))\n\n val s2_req_rdata = RegNext(data.read(s0_idx , s0_valid))\n\n val s2_resp = Wire(Vec(bankWidth, Bool()))\n\n for (w <- 0 until bankWidth) {\n\n s2_resp(w) := s2_valid && s2_req_rdata(w)(1) && !doing_reset\n s2_meta.bims(w) := s2_req_rdata(w)\n }\n\n\n val s1_update_wdata = Wire(Vec(bankWidth, UInt(2.W)))\n val s1_update_wmask = Wire(Vec(bankWidth, Bool()))\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BIMMeta)\n val s1_update_index = s1_update_idx\n\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nSets).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(2.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_idxs(i) === s1_update_index(log2Ceil(nSets)-1,0)\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n\n\n for (w <- 0 until bankWidth) {\n s1_update_wmask(w) := false.B\n s1_update_wdata(w) := DontCare\n\n val update_pc = s1_update.bits.pc + (w << 1).U\n\n when (s1_update.bits.br_mask(w) ||\n (s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) {\n val was_taken = (\n s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n (\n (s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) ||\n s1_update.bits.cfi_is_jal\n )\n )\n val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w))\n\n s1_update_wmask(w) := true.B\n\n s1_update_wdata(w) := bimWrite(old_bim_value, was_taken)\n }\n\n\n }\n\n when (doing_reset || (s1_update.valid && s1_update.bits.is_commit_update)) {\n data.write(\n Mux(doing_reset, reset_idx, s1_update_index),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata),\n Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt).asBools\n )\n }\n when (s1_update_wmask.reduce(_||_) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (wrbypass_hit) {\n wrbypass(wrbypass_hit_idx) := s1_update_wdata\n } .otherwise {\n wrbypass(wrbypass_enq_idx) := s1_update_wdata\n wrbypass_idxs(wrbypass_enq_idx) := s1_update_index\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n for (w <- 0 until bankWidth) {\n io.resp.f2(w).taken := s2_resp(w)\n io.resp.f3(w).taken := RegNext(io.resp.f2(w).taken)\n }\n io.f3_meta := RegNext(s2_meta.asUInt)\n}", + "response": "module data(\n input [10:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [7:0] R0_data,\n input [10:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [7:0] W0_data,\n input [3:0] W0_mask\n);\n\n data_ext data_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_postMul_e8_s24(\n input io_fromPreMul_isSigNaNAny,\n input io_fromPreMul_isNaNAOrB,\n input io_fromPreMul_isInfA,\n input io_fromPreMul_isZeroA,\n input io_fromPreMul_isInfB,\n input io_fromPreMul_isZeroB,\n input io_fromPreMul_signProd,\n input io_fromPreMul_isNaNC,\n input io_fromPreMul_isInfC,\n input io_fromPreMul_isZeroC,\n input [9:0] io_fromPreMul_sExpSum,\n input io_fromPreMul_doSubMags,\n input io_fromPreMul_CIsDominant,\n input [4:0] io_fromPreMul_CDom_CAlignDist,\n input [25:0] io_fromPreMul_highAlignedSigC,\n input io_fromPreMul_bit0AlignedSigC,\n input [48:0] io_mulAddResult,\n input [2:0] io_roundingMode,\n output io_invalidExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [9:0] io_rawOut_sExp,\n output [26:0] io_rawOut_sig\n);\n\n wire roundingMode_min = io_roundingMode == 3'h2;\n wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags;\n wire [25:0] _sigSum_T_3 = io_mulAddResult[48] ? io_fromPreMul_highAlignedSigC + 26'h1 : io_fromPreMul_highAlignedSigC;\n wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[47:24]} : {1'h0, io_fromPreMul_highAlignedSigC[25:24], _sigSum_T_3[23:0], io_mulAddResult[47:25]};\n wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist;\n wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> ~(io_fromPreMul_CDom_CAlignDist[4:2]));\n wire [50:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[47:0], io_fromPreMul_bit0AlignedSigC} + {50'h0, io_fromPreMul_doSubMags};\n wire [4:0] notCDom_normDistReduced2 = notCDom_absSigSum[50] ? 5'h0 : (|(notCDom_absSigSum[49:48])) ? 5'h1 : (|(notCDom_absSigSum[47:46])) ? 5'h2 : (|(notCDom_absSigSum[45:44])) ? 5'h3 : (|(notCDom_absSigSum[43:42])) ? 5'h4 : (|(notCDom_absSigSum[41:40])) ? 5'h5 : (|(notCDom_absSigSum[39:38])) ? 5'h6 : (|(notCDom_absSigSum[37:36])) ? 5'h7 : (|(notCDom_absSigSum[35:34])) ? 5'h8 : (|(notCDom_absSigSum[33:32])) ? 5'h9 : (|(notCDom_absSigSum[31:30])) ? 5'hA : (|(notCDom_absSigSum[29:28])) ? 5'hB : (|(notCDom_absSigSum[27:26])) ? 5'hC : (|(notCDom_absSigSum[25:24])) ? 5'hD : (|(notCDom_absSigSum[23:22])) ? 5'hE : (|(notCDom_absSigSum[21:20])) ? 5'hF : (|(notCDom_absSigSum[19:18])) ? 5'h10 : (|(notCDom_absSigSum[17:16])) ? 5'h11 : (|(notCDom_absSigSum[15:14])) ? 5'h12 : (|(notCDom_absSigSum[13:12])) ? 5'h13 : (|(notCDom_absSigSum[11:10])) ? 5'h14 : (|(notCDom_absSigSum[9:8])) ? 5'h15 : (|(notCDom_absSigSum[7:6])) ? 5'h16 : (|(notCDom_absSigSum[5:4])) ? 5'h17 : {4'hC, ~(|(notCDom_absSigSum[3:2]))};\n wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << {108'h0, notCDom_normDistReduced2, 1'h0};\n wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(notCDom_normDistReduced2[4:1]));\n wire notCDom_completeCancellation = _notCDom_mainSig_T[51:50] == 2'h0;\n wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB;\n wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC;\n wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC;\n assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags;\n assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC;\n assign io_rawOut_isInf = notNaN_isInfOut;\n assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation;\n assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]);\n assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {9'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {4'h0, notCDom_normDistReduced2, 1'h0};\n assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[49:24], (|{_CDom_mainSig_T[23:21], {|(CDom_absSigSum[20:17]), |(CDom_absSigSum[16:13]), |(CDom_absSigSum[12:9]), |(CDom_absSigSum[8:5]), |(CDom_absSigSum[4:1]), CDom_absSigSum[0]} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[23:0] != 24'hFFFFFF : (|(io_mulAddResult[24:0])))} : {_notCDom_mainSig_T[51:26], |{_notCDom_mainSig_T[25:23], {|{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6]}}};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package sifive.blocks.devices.uart\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.util._\n\n/** UARTRx module recivies serial input from Rx port and transmits them to Rx fifo in parallel\n *\n * ==Datapass==\n * Port(Rx) -> sample -> shifter -> Rx fifo -> TL bus\n *\n * ==Structure==\n * - baud rate divisor counter:\n * generate pulse, the enable signal for sample and data shift\n * - sample counter:\n * sample happens in middle\n * - data counter\n * control signals for data shift process\n * - sample and data shift logic\n *\n * ==State Machine==\n * s_idle: detect start bit, init data_count and sample count, start pulse counter\n * s_data: data reciving\n *\n * @note Rx fifo transmits Rx data to TL bus\n */\nclass UARTRx(c: UARTParams) extends Module {\n val io = IO(new Bundle {\n /** enable signal from top */\n val en = Input(Bool())\n /** input data from rx port */\n val in = Input(UInt(1.W))\n /** output data to Rx fifo */\n val out = Valid(UInt(c.dataBits.W))\n /** divisor bits */\n val div = Input(UInt(c.divisorBits.W))\n /** parity enable */\n val enparity = c.includeParity.option(Input(Bool()))\n /** parity select\n *\n * 0 -> even parity\n * 1 -> odd parity\n */\n val parity = c.includeParity.option(Input(Bool()))\n /** parity error bit */\n val errorparity = c.includeParity.option(Output(Bool()))\n /** databit select\n *\n * ture -> 8\n * false -> 9\n */\n val data8or9 = (c.dataBits == 9).option(Input(Bool()))\n })\n\n if (c.includeParity)\n io.errorparity.get := false.B\n\n val debounce = RegInit(0.U(2.W))\n val debounce_max = (debounce === 3.U)\n val debounce_min = (debounce === 0.U)\n\n val prescaler = Reg(UInt((c.divisorBits - c.oversample + 1).W))\n val start = WireDefault(false.B)\n /** enable signal for sampling and data shifting */\n val pulse = (prescaler === 0.U)\n\n private val dataCountBits = log2Floor(c.dataBits+c.includeParity.toInt) + 1\n /** init = data bits(8 or 9) + parity bit(0 or 1) + start bit(1) */\n val data_count = Reg(UInt(dataCountBits.W))\n val data_last = (data_count === 0.U)\n val parity_bit = (data_count === 1.U) && io.enparity.getOrElse(false.B)\n val sample_count = Reg(UInt(c.oversample.W))\n val sample_mid = (sample_count === ((c.oversampleFactor - c.nSamples + 1) >> 1).U)\n // todo unused\n val sample_last = (sample_count === 0.U)\n /** counter for data and sample\n *\n * {{{\n * | data_count | sample_count |\n * }}}\n */\n val countdown = Cat(data_count, sample_count) - 1.U\n\n // Compensate for the divisor not being a multiple of the oversampling period.\n // Let remainder k = (io.div % c.oversampleFactor).\n // For the last k samples, extend the sampling delay by 1 cycle.\n val remainder = io.div(c.oversample-1, 0)\n val extend = (sample_count < remainder) // Pad head: (sample_count > ~remainder)\n /** prescaler reset signal\n *\n * conditions:\n * {{{\n * start : transmisson starts\n * pulse : returns ture every pluse counter period\n * }}}\n */\n val restore = start || pulse\n val prescaler_in = Mux(restore, io.div >> c.oversample, prescaler)\n val prescaler_next = prescaler_in - Mux(restore && extend, 0.U, 1.U)\n /** buffer for sample results */\n val sample = Reg(UInt(c.nSamples.W))\n // take the majority bit of sample buffer\n val voter = Majority(sample.asBools.toSet)\n // data buffer\n val shifter = Reg(UInt(c.dataBits.W))\n\n val valid = RegInit(false.B)\n valid := false.B\n io.out.valid := valid\n io.out.bits := (if (c.dataBits == 8) shifter else Mux(io.data8or9.get, Cat(0.U, shifter(8,1)), shifter))\n\n val (s_idle :: s_data :: Nil) = Enum(2)\n val state = RegInit(s_idle)\n\n switch (state) {\n is (s_idle) {\n // todo !(!io.in)?\n when (!(!io.in) && !debounce_min) {\n debounce := debounce - 1.U\n }\n when (!io.in) {\n debounce := debounce + 1.U\n when (debounce_max) {\n state := s_data\n start := true.B\n prescaler := prescaler_next\n // init data_count\n data_count := (c.dataBits+1).U + (if (c.includeParity) io.enparity.get else 0.U) - io.data8or9.getOrElse(false.B).asUInt\n // init sample_count = 15\n sample_count := (c.oversampleFactor - 1).U\n }\n }\n }\n\n is (s_data) {\n prescaler := prescaler_next\n when (pulse) {\n // sample scan in\n sample := Cat(sample, io.in)\n data_count := countdown >> c.oversample\n sample_count := countdown(c.oversample-1, 0)\n\n when (sample_mid) {\n if (c.includeParity) {\n // act according to frame bit stage at its respective sampling point\n // check parity bit for error\n when (parity_bit) {\n io.errorparity.get := (shifter.asBools.reduce(_ ^ _) ^ voter ^ io.parity.get)\n }\n when (data_last) {\n state := s_idle\n valid := true.B\n } .elsewhen (!parity_bit) {\n // do not add parity bit to final rx data\n shifter := Cat(voter, shifter >> 1)\n }\n } else {\n when (data_last) {\n state := s_idle\n valid := true.B\n } .otherwise {\n shifter := Cat(voter, shifter >> 1)\n }\n }\n }\n }\n }\n }\n\n when (!io.en) {\n debounce := 0.U\n }\n}\n\n/*\n Copyright 2016 SiFive, Inc.\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n*/", + "response": "module UARTRx_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n input io_en,\n input io_in,\n output io_out_valid,\n output [7:0] io_out_bits,\n input [15:0] io_div\n);\n\n reg [1:0] debounce;\n reg [12:0] prescaler;\n reg [3:0] data_count;\n reg [3:0] sample_count;\n reg [2:0] sample;\n reg [7:0] shifter;\n reg valid;\n reg state;\n wire [7:0] _countdown_T_1 = {data_count, sample_count} - 8'h1;\n wire pulse = prescaler == 13'h0;\n wire data_last = data_count == 4'h0;\n wire sample_mid = sample_count == 4'h7;\n wire _GEN = ~io_in & (&debounce);\n wire _GEN_0 = _GEN | state;\n wire _GEN_1 = state & pulse;\n wire _GEN_2 = state & pulse & sample_mid;\n wire restore = ~state & ~io_in & (&debounce) | pulse;\n always @(posedge clock) begin\n if (reset) begin\n debounce <= 2'h0;\n valid <= 1'h0;\n state <= 1'h0;\n end\n else begin\n if (io_en) begin\n if (state) begin\n end\n else if (io_in) begin\n if (io_in & (|debounce))\n debounce <= debounce - 2'h1;\n end\n else\n debounce <= debounce + 2'h1;\n end\n else\n debounce <= 2'h0;\n valid <= _GEN_2 & data_last;\n if (state)\n state <= ~(state & pulse & sample_mid & data_last) & state;\n else\n state <= _GEN_0;\n end\n if (_GEN_0)\n prescaler <= (restore ? {1'h0, io_div[15:4]} : prescaler) - {12'h0, ~(restore & sample_count < io_div[3:0])};\n if (state) begin\n if (_GEN_1) begin\n data_count <= _countdown_T_1[7:4];\n sample_count <= _countdown_T_1[3:0];\n end\n end\n else if (_GEN) begin\n data_count <= 4'h9;\n sample_count <= 4'hF;\n end\n if (_GEN_1)\n sample <= {sample[1:0], io_in};\n if (~state | ~_GEN_2 | data_last) begin\n end\n else\n shifter <= {sample[0] & sample[1] | sample[0] & sample[2] | sample[1] & sample[2], shifter[7:1]};\n end\n assign io_out_valid = valid;\n assign io_out_bits = shifter;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLAFromBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n input io_protocol_ready,\n output io_protocol_valid,\n output [2:0] io_protocol_bits_opcode,\n output [2:0] io_protocol_bits_param,\n output [7:0] io_protocol_bits_size,\n output [7:0] io_protocol_bits_source,\n output [63:0] io_protocol_bits_address,\n output [7:0] io_protocol_bits_mask,\n output [63:0] io_protocol_bits_data,\n output io_protocol_bits_corrupt,\n output io_beat_ready,\n input io_beat_valid,\n input [85:0] io_beat_bits_payload,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n reg [85:0] const_reg;\n wire [85:0] const_0 = io_beat_bits_head ? io_beat_bits_payload : const_reg;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail | io_protocol_ready;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n wire _GEN_0 = _GEN & io_beat_bits_head;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~_GEN_0 & is_const;\n if (_GEN_0)\n const_reg <= io_beat_bits_payload;\n end\n assign io_protocol_valid = (~is_const | io_beat_bits_tail) & io_beat_valid;\n assign io_protocol_bits_opcode = const_0[85:83];\n assign io_protocol_bits_param = const_0[82:80];\n assign io_protocol_bits_size = const_0[79:72];\n assign io_protocol_bits_source = const_0[71:64];\n assign io_protocol_bits_address = const_0[63:0];\n assign io_protocol_bits_mask = io_beat_bits_head ? 8'hFF : io_beat_bits_payload[72:65];\n assign io_protocol_bits_data = io_beat_bits_payload[64:1];\n assign io_protocol_bits_corrupt = io_beat_bits_payload[0];\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLDFromBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24(\n input io_in_isZero,\n input io_in_sign,\n input [8:0] io_in_sExp,\n input [64:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [32:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire [1:0] _GEN = {io_in_sig[39], |(io_in_sig[38:0])};\n wire [25:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[39] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & (|_GEN) ? {1'h0, io_in_sig[64:40]} + 26'h1 & {25'h1FFFFFF, ~(roundingMode_near_even & io_in_sig[39] & ~(|(io_in_sig[38:0])))} : {1'h0, io_in_sig[64:41], io_in_sig[40] | io_roundingMode == 3'h6 & (|_GEN)};\n assign io_out = {io_in_sign, io_in_sExp + {7'h0, roundedSig[25:24]} + 9'h80 & ~(io_in_isZero ? 9'h1C0 : 9'h0), io_in_isZero ? 23'h0 : roundedSig[22:0]};\n assign io_exceptionFlags = {4'h0, ~io_in_isZero & (|_GEN)};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPUDecoder(\n input [31:0] io_inst,\n output io_sigs_wen,\n output io_sigs_ren1,\n output io_sigs_ren2,\n output io_sigs_ren3,\n output io_sigs_swap12,\n output io_sigs_swap23,\n output [1:0] io_sigs_typeTagIn,\n output [1:0] io_sigs_typeTagOut,\n output io_sigs_fromint,\n output io_sigs_toint,\n output io_sigs_fastpipe,\n output io_sigs_fma,\n output io_sigs_div,\n output io_sigs_sqrt,\n output io_sigs_wflags,\n output io_sigs_vec\n);\n\n wire [29:0] decoder_decoded_invInputs = ~(io_inst[31:2]);\n wire [4:0] _decoder_decoded_andMatrixOutputs_T = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6]};\n wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24]};\n wire [10:0] _decoder_decoded_andMatrixOutputs_T_2 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [10:0] _decoder_decoded_andMatrixOutputs_T_3 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [11:0] _decoder_decoded_andMatrixOutputs_T_4 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [11:0] _decoder_decoded_andMatrixOutputs_T_7 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [11:0] _decoder_decoded_andMatrixOutputs_T_8 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [8:0] _decoder_decoded_andMatrixOutputs_T_11 = {io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[12], decoder_decoded_invInputs[12]};\n wire [8:0] _decoder_decoded_andMatrixOutputs_T_14 = {io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[13], decoder_decoded_invInputs[12]};\n wire [6:0] _decoder_decoded_andMatrixOutputs_T_17 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_inst[6], io_inst[25], decoder_decoded_invInputs[24]};\n wire [11:0] _decoder_decoded_andMatrixOutputs_T_18 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_21 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_22 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_23 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_24 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_25 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_26 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_27 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [13:0] _decoder_decoded_andMatrixOutputs_T_28 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_29 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_30 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_31 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_32 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_33 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_34 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]};\n wire [16:0] _decoder_decoded_andMatrixOutputs_T_37 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_38 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [16:0] _decoder_decoded_andMatrixOutputs_T_40 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_41 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [16:0] _decoder_decoded_andMatrixOutputs_T_43 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_44 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [16:0] _decoder_decoded_andMatrixOutputs_T_46 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_47 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_49 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [17:0] _decoder_decoded_andMatrixOutputs_T_50 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [18:0] _decoder_decoded_andMatrixOutputs_T_51 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [18:0] _decoder_decoded_andMatrixOutputs_T_52 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_53 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_54 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_55 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};\n wire [14:0] _decoder_decoded_andMatrixOutputs_T_56 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], io_inst[31]};\n wire [15:0] _decoder_decoded_andMatrixOutputs_T_60 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};\n wire [15:0] _decoder_decoded_andMatrixOutputs_T_61 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};\n wire [15:0] _decoder_decoded_andMatrixOutputs_T_63 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};\n wire [15:0] _decoder_decoded_andMatrixOutputs_T_64 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]};\n wire [19:0] _decoder_decoded_andMatrixOutputs_T_67 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};\n wire [19:0] _decoder_decoded_andMatrixOutputs_T_69 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};\n wire [20:0] _decoder_decoded_andMatrixOutputs_T_72 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[29], io_inst[30], io_inst[31]};\n wire [20:0] _decoder_decoded_andMatrixOutputs_T_73 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]};\n wire [20:0] _decoder_decoded_andMatrixOutputs_T_74 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]};\n wire [20:0] _decoder_decoded_andMatrixOutputs_T_75 = {io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]};\n assign io_sigs_wen = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_inst[12], decoder_decoded_invInputs[12]}, &{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_inst[13], decoder_decoded_invInputs[12]}, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_30, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_41, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_47, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_63, &_decoder_decoded_andMatrixOutputs_T_64, &_decoder_decoded_andMatrixOutputs_T_74, &_decoder_decoded_andMatrixOutputs_T_75};\n assign io_sigs_ren1 = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &_decoder_decoded_andMatrixOutputs_T_21, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_23, &_decoder_decoded_andMatrixOutputs_T_24, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_37, &_decoder_decoded_andMatrixOutputs_T_40, &_decoder_decoded_andMatrixOutputs_T_43, &_decoder_decoded_andMatrixOutputs_T_46, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_60, &_decoder_decoded_andMatrixOutputs_T_61, &_decoder_decoded_andMatrixOutputs_T_67, &_decoder_decoded_andMatrixOutputs_T_69};\n assign io_sigs_ren2 = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_21, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_23, &_decoder_decoded_andMatrixOutputs_T_24, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28};\n assign io_sigs_ren3 = &_decoder_decoded_andMatrixOutputs_T;\n assign io_sigs_swap12 = |{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14};\n assign io_sigs_swap23 = |{&_decoder_decoded_andMatrixOutputs_T_7, &_decoder_decoded_andMatrixOutputs_T_8};\n assign io_sigs_typeTagIn =\n {|{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_17, &_decoder_decoded_andMatrixOutputs_T_18, &_decoder_decoded_andMatrixOutputs_T_32, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_52, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]}, &_decoder_decoded_andMatrixOutputs_T_72, &_decoder_decoded_andMatrixOutputs_T_73},\n |{&_decoder_decoded_andMatrixOutputs_T_1,\n &_decoder_decoded_andMatrixOutputs_T_4,\n &_decoder_decoded_andMatrixOutputs_T_25,\n &_decoder_decoded_andMatrixOutputs_T_26,\n &_decoder_decoded_andMatrixOutputs_T_29,\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], io_inst[26], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},\n &_decoder_decoded_andMatrixOutputs_T_51,\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]},\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[12], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]},\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[10], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], io_inst[29], io_inst[30], io_inst[31]}}};\n assign io_sigs_typeTagOut =\n {|{&{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], io_inst[12], io_inst[13], decoder_decoded_invInputs[12]}, &_decoder_decoded_andMatrixOutputs_T_17, &_decoder_decoded_andMatrixOutputs_T_18, &_decoder_decoded_andMatrixOutputs_T_32, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_52, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], io_inst[25], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &_decoder_decoded_andMatrixOutputs_T_72, &_decoder_decoded_andMatrixOutputs_T_73, &_decoder_decoded_andMatrixOutputs_T_74},\n |{&_decoder_decoded_andMatrixOutputs_T_1,\n &_decoder_decoded_andMatrixOutputs_T_4,\n &{io_inst[0], io_inst[1], io_inst[2], decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_inst[5], decoder_decoded_invInputs[4], decoder_decoded_invInputs[10], io_inst[13], decoder_decoded_invInputs[12]},\n &_decoder_decoded_andMatrixOutputs_T_25,\n &_decoder_decoded_andMatrixOutputs_T_26,\n &_decoder_decoded_andMatrixOutputs_T_29,\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], io_inst[20], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[18], io_inst[21], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], decoder_decoded_invInputs[27], io_inst[30], decoder_decoded_invInputs[29]},\n &_decoder_decoded_andMatrixOutputs_T_51,\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], io_inst[28], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]},\n &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[18], decoder_decoded_invInputs[19], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[26], io_inst[29], io_inst[30], io_inst[31]}}};\n assign io_sigs_fromint = |{&_decoder_decoded_andMatrixOutputs_T_63, &_decoder_decoded_andMatrixOutputs_T_64, &_decoder_decoded_andMatrixOutputs_T_74, &_decoder_decoded_andMatrixOutputs_T_75};\n assign io_sigs_toint = |{&_decoder_decoded_andMatrixOutputs_T_11, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_53, &_decoder_decoded_andMatrixOutputs_T_54, &_decoder_decoded_andMatrixOutputs_T_55, &_decoder_decoded_andMatrixOutputs_T_56, &_decoder_decoded_andMatrixOutputs_T_60, &_decoder_decoded_andMatrixOutputs_T_61, &_decoder_decoded_andMatrixOutputs_T_67, &_decoder_decoded_andMatrixOutputs_T_69};\n assign io_sigs_fastpipe = |{&_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_30, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_38, &_decoder_decoded_andMatrixOutputs_T_41, &_decoder_decoded_andMatrixOutputs_T_44, &_decoder_decoded_andMatrixOutputs_T_47};\n assign io_sigs_fma = |{&_decoder_decoded_andMatrixOutputs_T, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &_decoder_decoded_andMatrixOutputs_T_7, &_decoder_decoded_andMatrixOutputs_T_8};\n assign io_sigs_div = |{&{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[23], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[24], io_inst[27], io_inst[28], decoder_decoded_invInputs[27], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}};\n assign io_sigs_sqrt = |{&_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50};\n assign io_sigs_wflags = |{&_decoder_decoded_andMatrixOutputs_T, &_decoder_decoded_andMatrixOutputs_T_2, &_decoder_decoded_andMatrixOutputs_T_3, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[23], io_inst[27], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[11], decoder_decoded_invInputs[12], decoder_decoded_invInputs[24], io_inst[27], decoder_decoded_invInputs[26], io_inst[29], decoder_decoded_invInputs[28], decoder_decoded_invInputs[29]}, &_decoder_decoded_andMatrixOutputs_T_37, &_decoder_decoded_andMatrixOutputs_T_40, &_decoder_decoded_andMatrixOutputs_T_43, &_decoder_decoded_andMatrixOutputs_T_46, &_decoder_decoded_andMatrixOutputs_T_49, &_decoder_decoded_andMatrixOutputs_T_50, &_decoder_decoded_andMatrixOutputs_T_53, &_decoder_decoded_andMatrixOutputs_T_54, &_decoder_decoded_andMatrixOutputs_T_55, &_decoder_decoded_andMatrixOutputs_T_56, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[23], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}, &{io_inst[0], io_inst[1], decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_inst[4], decoder_decoded_invInputs[3], io_inst[6], decoder_decoded_invInputs[20], decoder_decoded_invInputs[21], decoder_decoded_invInputs[22], decoder_decoded_invInputs[24], decoder_decoded_invInputs[25], decoder_decoded_invInputs[27], io_inst[30], io_inst[31]}};\n assign io_sigs_vec = 1'h0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPUFMAPipe_l3_f32(\n input clock,\n input reset,\n input io_in_valid,\n input io_in_bits_ren3,\n input io_in_bits_swap23,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_fmaCmd,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n input [64:0] io_in_bits_in3,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc\n);\n\n wire [32:0] _fma_io_out;\n reg valid;\n reg [2:0] in_rm;\n reg [1:0] in_fmaCmd;\n reg [64:0] in_in1;\n reg [64:0] in_in2;\n reg [64:0] in_in3;\n always @(posedge clock) begin\n valid <= io_in_valid;\n if (io_in_valid) begin\n in_rm <= io_in_bits_rm;\n in_fmaCmd <= io_in_bits_fmaCmd;\n in_in1 <= io_in_bits_in1;\n in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2;\n in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000};\n end\n end\n MulAddRecFNPipe_l2_e8_s24 fma (\n .clock (clock),\n .reset (reset),\n .io_validin (valid),\n .io_op (in_fmaCmd),\n .io_a (in_in1[32:0]),\n .io_b (in_in2[32:0]),\n .io_c (in_in3[32:0]),\n .io_roundingMode (in_rm),\n .io_out (_fma_io_out),\n .io_exceptionFlags (io_out_bits_exc)\n );\n assign io_out_bits_data = {32'h0, ({33{_fma_io_out[31:29] != 3'h7}} | 33'h1EF7FFFFF) & _fma_io_out};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11(\n input io_in_isZero,\n input io_in_sign,\n input [8:0] io_in_sExp,\n input [64:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;\n wire [9:0] sAdjustedExp = {io_in_sExp[8], io_in_sExp} - 10'h60;\n wire [1:0] _GEN = {io_in_sig[52], |(io_in_sig[51:0])};\n wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;\n wire [12:0] roundedSig = _overflow_roundMagUp_T & io_in_sig[52] | roundMagUp & (|_GEN) ? {1'h0, io_in_sig[64:53]} + 13'h1 & {12'hFFF, ~(roundingMode_near_even & io_in_sig[52] & ~(|(io_in_sig[51:0])))} : {1'h0, io_in_sig[64:54], io_in_sig[53] | io_roundingMode == 3'h6 & (|_GEN)};\n wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {9'h0, roundedSig[12:11]};\n wire overflow = ~io_in_isZero & $signed(sRoundedExp[10:4]) > 7'sh2;\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\n wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;\n wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp;\n assign io_out = {io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero ? 6'h38 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~_notNaN_isInfOut_T, 3'h7} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (_notNaN_isInfOut_T ? 6'h30 : 6'h0), (io_in_isZero ? 10'h0 : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};\n assign io_exceptionFlags = {2'h0, overflow, 1'h0, overflow | ~io_in_isZero & (|_GEN)};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module ram_7x77(\n input [2:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [76:0] R0_data,\n input [2:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [76:0] W0_data\n);\n\n reg [76:0] Memory[0:6];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Unit Decode\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Generate the functional unit control signals from the micro-op opcodes.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.uintToBitPat\nimport freechips.rocketchip.rocket.CSR\nimport freechips.rocketchip.rocket.ALU._\n\nimport boom.v3.common._\n\n/**\n * Control signal bundle for register renaming\n */\nclass RRdCtrlSigs(implicit p: Parameters) extends BoomBundle\n{\n val br_type = UInt(BR_N.getWidth.W)\n val use_alupipe = Bool()\n val use_muldivpipe = Bool()\n val use_mempipe = Bool()\n val op_fcn = Bits(SZ_ALU_FN.W)\n val fcn_dw = Bool()\n val op1_sel = UInt(OP1_X.getWidth.W)\n val op2_sel = UInt(OP2_X.getWidth.W)\n val imm_sel = UInt(IS_X.getWidth.W)\n val rf_wen = Bool()\n val csr_cmd = Bits(CSR.SZ.W)\n\n def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)\n val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,\n fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n this\n }\n}\n\n/**\n * Default register read constants\n */\nabstract trait RRdDecodeConstants\n{\n val default: List[BitPat] =\n List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)\n val table: Array[(BitPat, List[BitPat])]\n}\n\n/**\n * ALU register read constants\n */\nobject AluRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),\n\n BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))\n}\n\nobject JmpRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),\n BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),\n BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))\n}\n\n/**\n * Multiply divider register read constants\n */\nobject MulDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n\n BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Memory unit register read constants\n */\nobject MemRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),\n BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),\n BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n\n BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))\n}\n\n/**\n * CSR register read constants\n */\nobject CsrRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),\n\n BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),\n\n BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),\n BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))\n}\n\n/**\n * FPU register read constants\n */\nobject FpuRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// TODO comment out I2F instructions.\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Fused multiple add register read constants\n */\nobject IfmvRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Floating point divide and square root register read constants\n */\nobject FDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Register read decoder\n *\n * @param supportedUnits indicate what functional units are being used\n */\nclass RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new BoomBundle {\n val iss_valid = Input(Bool())\n val iss_uop = Input(new MicroOp())\n\n val rrd_valid = Output(Bool())\n val rrd_uop = Output(new MicroOp())\n })\n\n // Issued Instruction\n val rrd_valid = io.iss_valid\n io.rrd_uop := io.iss_uop\n\n var dec_table = AluRRdDecode.table\n if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table\n if (supportedUnits.mem) dec_table ++= MemRRdDecode.table\n if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table\n if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table\n if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table\n if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table\n if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table\n val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)\n\n // rrd_use_alupipe is unused\n io.rrd_uop.ctrl.br_type := rrd_cs.br_type\n io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel\n io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel\n io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel\n io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt\n io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool\n io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD\n io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG\n io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)\n\n when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {\n io.rrd_uop.imm_packed := 0.U\n }\n\n val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0\n val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U\n io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)\n\n //-------------------------------------------------------------\n // set outputs\n\n io.rrd_valid := rrd_valid\n}", + "response": "module RegisterReadDecode_2(\n input io_iss_valid,\n input [6:0] io_iss_uop_uopc,\n input [31:0] io_iss_uop_inst,\n input [31:0] io_iss_uop_debug_inst,\n input io_iss_uop_is_rvc,\n input [39:0] io_iss_uop_debug_pc,\n input [2:0] io_iss_uop_iq_type,\n input [9:0] io_iss_uop_fu_code,\n input [1:0] io_iss_uop_iw_state,\n input io_iss_uop_is_br,\n input io_iss_uop_is_jalr,\n input io_iss_uop_is_jal,\n input io_iss_uop_is_sfb,\n input [7:0] io_iss_uop_br_mask,\n input [2:0] io_iss_uop_br_tag,\n input [3:0] io_iss_uop_ftq_idx,\n input io_iss_uop_edge_inst,\n input [5:0] io_iss_uop_pc_lob,\n input io_iss_uop_taken,\n input [19:0] io_iss_uop_imm_packed,\n input [11:0] io_iss_uop_csr_addr,\n input [4:0] io_iss_uop_rob_idx,\n input [2:0] io_iss_uop_ldq_idx,\n input [2:0] io_iss_uop_stq_idx,\n input [1:0] io_iss_uop_rxq_idx,\n input [5:0] io_iss_uop_pdst,\n input [5:0] io_iss_uop_prs1,\n input [5:0] io_iss_uop_prs2,\n input [5:0] io_iss_uop_prs3,\n input [3:0] io_iss_uop_ppred,\n input io_iss_uop_prs1_busy,\n input io_iss_uop_prs2_busy,\n input io_iss_uop_prs3_busy,\n input io_iss_uop_ppred_busy,\n input [5:0] io_iss_uop_stale_pdst,\n input io_iss_uop_exception,\n input [63:0] io_iss_uop_exc_cause,\n input io_iss_uop_bypassable,\n input [4:0] io_iss_uop_mem_cmd,\n input [1:0] io_iss_uop_mem_size,\n input io_iss_uop_mem_signed,\n input io_iss_uop_is_fence,\n input io_iss_uop_is_fencei,\n input io_iss_uop_is_amo,\n input io_iss_uop_uses_ldq,\n input io_iss_uop_uses_stq,\n input io_iss_uop_is_sys_pc2epc,\n input io_iss_uop_is_unique,\n input io_iss_uop_flush_on_commit,\n input io_iss_uop_ldst_is_rs1,\n input [5:0] io_iss_uop_ldst,\n input [5:0] io_iss_uop_lrs1,\n input [5:0] io_iss_uop_lrs2,\n input [5:0] io_iss_uop_lrs3,\n input io_iss_uop_ldst_val,\n input [1:0] io_iss_uop_dst_rtype,\n input [1:0] io_iss_uop_lrs1_rtype,\n input [1:0] io_iss_uop_lrs2_rtype,\n input io_iss_uop_frs3_en,\n input io_iss_uop_fp_val,\n input io_iss_uop_fp_single,\n input io_iss_uop_xcpt_pf_if,\n input io_iss_uop_xcpt_ae_if,\n input io_iss_uop_xcpt_ma_if,\n input io_iss_uop_bp_debug_if,\n input io_iss_uop_bp_xcpt_if,\n input [1:0] io_iss_uop_debug_fsrc,\n input [1:0] io_iss_uop_debug_tsrc,\n output io_rrd_valid,\n output [6:0] io_rrd_uop_uopc,\n output [31:0] io_rrd_uop_inst,\n output [31:0] io_rrd_uop_debug_inst,\n output io_rrd_uop_is_rvc,\n output [39:0] io_rrd_uop_debug_pc,\n output [2:0] io_rrd_uop_iq_type,\n output [9:0] io_rrd_uop_fu_code,\n output [3:0] io_rrd_uop_ctrl_br_type,\n output [1:0] io_rrd_uop_ctrl_op1_sel,\n output [2:0] io_rrd_uop_ctrl_op2_sel,\n output [2:0] io_rrd_uop_ctrl_imm_sel,\n output [4:0] io_rrd_uop_ctrl_op_fcn,\n output io_rrd_uop_ctrl_fcn_dw,\n output [2:0] io_rrd_uop_ctrl_csr_cmd,\n output io_rrd_uop_ctrl_is_load,\n output io_rrd_uop_ctrl_is_sta,\n output io_rrd_uop_ctrl_is_std,\n output [1:0] io_rrd_uop_iw_state,\n output io_rrd_uop_is_br,\n output io_rrd_uop_is_jalr,\n output io_rrd_uop_is_jal,\n output io_rrd_uop_is_sfb,\n output [7:0] io_rrd_uop_br_mask,\n output [2:0] io_rrd_uop_br_tag,\n output [3:0] io_rrd_uop_ftq_idx,\n output io_rrd_uop_edge_inst,\n output [5:0] io_rrd_uop_pc_lob,\n output io_rrd_uop_taken,\n output [19:0] io_rrd_uop_imm_packed,\n output [11:0] io_rrd_uop_csr_addr,\n output [4:0] io_rrd_uop_rob_idx,\n output [2:0] io_rrd_uop_ldq_idx,\n output [2:0] io_rrd_uop_stq_idx,\n output [1:0] io_rrd_uop_rxq_idx,\n output [5:0] io_rrd_uop_pdst,\n output [5:0] io_rrd_uop_prs1,\n output [5:0] io_rrd_uop_prs2,\n output [5:0] io_rrd_uop_prs3,\n output [3:0] io_rrd_uop_ppred,\n output io_rrd_uop_prs1_busy,\n output io_rrd_uop_prs2_busy,\n output io_rrd_uop_prs3_busy,\n output io_rrd_uop_ppred_busy,\n output [5:0] io_rrd_uop_stale_pdst,\n output io_rrd_uop_exception,\n output [63:0] io_rrd_uop_exc_cause,\n output io_rrd_uop_bypassable,\n output [4:0] io_rrd_uop_mem_cmd,\n output [1:0] io_rrd_uop_mem_size,\n output io_rrd_uop_mem_signed,\n output io_rrd_uop_is_fence,\n output io_rrd_uop_is_fencei,\n output io_rrd_uop_is_amo,\n output io_rrd_uop_uses_ldq,\n output io_rrd_uop_uses_stq,\n output io_rrd_uop_is_sys_pc2epc,\n output io_rrd_uop_is_unique,\n output io_rrd_uop_flush_on_commit,\n output io_rrd_uop_ldst_is_rs1,\n output [5:0] io_rrd_uop_ldst,\n output [5:0] io_rrd_uop_lrs1,\n output [5:0] io_rrd_uop_lrs2,\n output [5:0] io_rrd_uop_lrs3,\n output io_rrd_uop_ldst_val,\n output [1:0] io_rrd_uop_dst_rtype,\n output [1:0] io_rrd_uop_lrs1_rtype,\n output [1:0] io_rrd_uop_lrs2_rtype,\n output io_rrd_uop_frs3_en,\n output io_rrd_uop_fp_val,\n output io_rrd_uop_fp_single,\n output io_rrd_uop_xcpt_pf_if,\n output io_rrd_uop_xcpt_ae_if,\n output io_rrd_uop_xcpt_ma_if,\n output io_rrd_uop_bp_debug_if,\n output io_rrd_uop_bp_xcpt_if,\n output [1:0] io_rrd_uop_debug_fsrc,\n output [1:0] io_rrd_uop_debug_tsrc\n);\n\n wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_3 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_34 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_35 = {rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_52 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_53 = {io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_56 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_57 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_59 = {rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_60 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_64 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_69 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_82 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_84 = {rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]};\n wire [1:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_85 = {io_iss_uop_uopc[5], io_iss_uop_uopc[6]};\n wire [2:0] rrd_cs_csr_cmd = {|{&{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]}}, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53}, |{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52}};\n wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;\n wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;\n wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;\n assign io_rrd_valid = io_iss_valid;\n assign io_rrd_uop_uopc = io_iss_uop_uopc;\n assign io_rrd_uop_inst = io_iss_uop_inst;\n assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;\n assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;\n assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;\n assign io_rrd_uop_iq_type = io_iss_uop_iq_type;\n assign io_rrd_uop_fu_code = io_iss_uop_fu_code;\n assign io_rrd_uop_ctrl_br_type = {&_rrd_cs_decoder_decoded_andMatrixOutputs_T_59, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_57}};\n assign io_rrd_uop_ctrl_op1_sel = {&{io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_85}};\n assign io_rrd_uop_ctrl_op2_sel = {|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_52, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_53, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_85}, |{&{io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_56, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_59}, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};\n assign io_rrd_uop_ctrl_imm_sel = {&_rrd_cs_decoder_decoded_andMatrixOutputs_T_56, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60}, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_3, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_60}};\n assign io_rrd_uop_ctrl_op_fcn =\n {&_rrd_cs_decoder_decoded_andMatrixOutputs_T_84,\n |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_34, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_35, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},\n |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},\n |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_64, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84},\n |{&{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_82, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_84}};\n assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_69, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}} == 7'h0;\n assign io_rrd_uop_ctrl_csr_cmd = (rrd_cs_csr_cmd == 3'h6 | (&rrd_cs_csr_cmd)) & io_iss_uop_prs1 == 6'h0 ? 3'h2 : rrd_cs_csr_cmd;\n assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;\n assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;\n assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;\n assign io_rrd_uop_iw_state = io_iss_uop_iw_state;\n assign io_rrd_uop_is_br = io_iss_uop_is_br;\n assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;\n assign io_rrd_uop_is_jal = io_iss_uop_is_jal;\n assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;\n assign io_rrd_uop_br_mask = io_iss_uop_br_mask;\n assign io_rrd_uop_br_tag = io_iss_uop_br_tag;\n assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;\n assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;\n assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;\n assign io_rrd_uop_taken = io_iss_uop_taken;\n assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;\n assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;\n assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;\n assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;\n assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;\n assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;\n assign io_rrd_uop_pdst = io_iss_uop_pdst;\n assign io_rrd_uop_prs1 = io_iss_uop_prs1;\n assign io_rrd_uop_prs2 = io_iss_uop_prs2;\n assign io_rrd_uop_prs3 = io_iss_uop_prs3;\n assign io_rrd_uop_ppred = io_iss_uop_ppred;\n assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;\n assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;\n assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;\n assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;\n assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;\n assign io_rrd_uop_exception = io_iss_uop_exception;\n assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;\n assign io_rrd_uop_bypassable = io_iss_uop_bypassable;\n assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;\n assign io_rrd_uop_mem_size = io_iss_uop_mem_size;\n assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;\n assign io_rrd_uop_is_fence = io_iss_uop_is_fence;\n assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;\n assign io_rrd_uop_is_amo = io_iss_uop_is_amo;\n assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;\n assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;\n assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;\n assign io_rrd_uop_is_unique = io_iss_uop_is_unique;\n assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;\n assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;\n assign io_rrd_uop_ldst = io_iss_uop_ldst;\n assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;\n assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;\n assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;\n assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;\n assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;\n assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;\n assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;\n assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;\n assign io_rrd_uop_fp_val = io_iss_uop_fp_val;\n assign io_rrd_uop_fp_single = io_iss_uop_fp_single;\n assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;\n assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;\n assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;\n assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;\n assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;\n assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;\n assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitToFlit_p32_f32(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_phit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_flit\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_flit = io_in_bits_phit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.{Cat, Fill}\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for standard 64-bit floating-point in\n| recoded form, using a separate integer multiplier-adder. Multiple clock\n| cycles are needed for each division or square-root operation. See\n| \"docs/DivSqrtRecF64_mulAddZ31.txt\" for more details.\n*----------------------------------------------------------------------------*/\n\nclass DivSqrtRecF64ToRaw_mulAddZ31 extends Module\n{\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(UInt(3.W))\n//*** OPTIONALLY PROPAGATE:\n// val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val usingMulAdd = Output(Bits(4.W))\n val latchMulAddA_0 = Output(Bool())\n val mulAddA_0 = Output(UInt(54.W))\n val latchMulAddB_0 = Output(Bool())\n val mulAddB_0 = Output(UInt(54.W))\n val mulAddC_2 = Output(UInt(105.W))\n val mulAddResult_3 = Input(UInt(105.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(11, 55))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum_A = RegInit(0.U(3.W))\n val cycleNum_B = RegInit(0.U(4.W))\n val cycleNum_C = RegInit(0.U(3.W))\n val cycleNum_E = RegInit(0.U(3.W))\n\n val valid_PA = RegInit(false.B)\n val sqrtOp_PA = Reg(Bool())\n val majorExc_PA = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PA = Reg(Bool())\n val isInf_PA = Reg(Bool())\n val isZero_PA = Reg(Bool())\n val sign_PA = Reg(Bool())\n val sExp_PA = Reg(SInt(13.W))\n val fractB_PA = Reg(UInt(52.W))\n val fractA_PA = Reg(UInt(52.W))\n val roundingMode_PA = Reg(UInt(3.W))\n\n val valid_PB = RegInit(false.B)\n val sqrtOp_PB = Reg(Bool())\n val majorExc_PB = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PB = Reg(Bool())\n val isInf_PB = Reg(Bool())\n val isZero_PB = Reg(Bool())\n val sign_PB = Reg(Bool())\n val sExp_PB = Reg(SInt(13.W))\n val bit0FractA_PB = Reg(UInt(1.W))\n val fractB_PB = Reg(UInt(52.W))\n val roundingMode_PB = Reg(UInt(3.W))\n\n val valid_PC = RegInit(false.B)\n val sqrtOp_PC = Reg(Bool())\n val majorExc_PC = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PC = Reg(Bool())\n val isInf_PC = Reg(Bool())\n val isZero_PC = Reg(Bool())\n val sign_PC = Reg(Bool())\n val sExp_PC = Reg(SInt(13.W))\n val bit0FractA_PC = Reg(UInt(1.W))\n val fractB_PC = Reg(UInt(52.W))\n val roundingMode_PC = Reg(UInt(3.W))\n\n val fractR0_A = Reg(UInt(9.W))\n//*** COMBINE 'hiSqrR0_A_sqrt' AND 'partNegSigma0_A'?\n val hiSqrR0_A_sqrt = Reg(UInt(10.W))\n val partNegSigma0_A = Reg(UInt(21.W))\n val nextMulAdd9A_A = Reg(UInt(9.W))\n val nextMulAdd9B_A = Reg(UInt(9.W))\n val ER1_B_sqrt = Reg(UInt(17.W))\n\n val ESqrR1_B_sqrt = Reg(UInt(32.W))\n val sigX1_B = Reg(UInt(58.W))\n val sqrSigma1_C = Reg(UInt(33.W))\n val sigXN_C = Reg(UInt(58.W))\n val u_C_sqrt = Reg(UInt(31.W))\n val E_E_div = Reg(Bool())\n val sigT_E = Reg(UInt(54.W))\n val isNegRemT_E = Reg(Bool())\n val isZeroRemT_E = Reg(Bool())\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val ready_PA = Wire(Bool())\n val ready_PB = Wire(Bool())\n val ready_PC = Wire(Bool())\n val leaving_PA = Wire(Bool())\n val leaving_PB = Wire(Bool())\n val leaving_PC = Wire(Bool())\n\n val zSigma1_B4 = Wire(UInt())\n val sigXNU_B3_CX = Wire(UInt())\n val zComplSigT_C1_sqrt = Wire(UInt())\n val zComplSigT_C1 = Wire(UInt())\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cyc_S_div = io.inReady_div && io.inValid && ! io.sqrtOp\n val cyc_S_sqrt = io.inReady_sqrt && io.inValid && io.sqrtOp\n val cyc_S = cyc_S_div || cyc_S_sqrt\n\n val rawA_S = rawFloatFromRecFN(11, 53, io.a)\n val rawB_S = rawFloatFromRecFN(11, 53, io.b)\n\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawB_S.isNaN && ! rawB_S.isZero && rawB_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawB_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawB_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawB_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = (! io.sqrtOp && rawA_S.sign) ^ rawB_S.sign\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseB_S && ! rawB_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +& (rawB_S.sExp(11) ## ~rawB_S.sExp(10, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n (Mux(((7<<9).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(12, 9)\n ) ##\n sExpQuot_S_div(8, 0)\n ).asSInt\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PA_normalCase_div = cyc_S_div && normalCase_S_div\n val entering_PA_normalCase_sqrt = cyc_S_sqrt && normalCase_S_sqrt\n val entering_PA_normalCase =\n entering_PA_normalCase_div || entering_PA_normalCase_sqrt\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering_PA_normalCase || (cycleNum_A =/= 0.U)) {\n cycleNum_A :=\n Mux(entering_PA_normalCase_div, 3.U, 0.U) |\n Mux(entering_PA_normalCase_sqrt, 6.U, 0.U) |\n Mux(! entering_PA_normalCase, cycleNum_A - 1.U, 0.U)\n }\n\n val cyc_A7_sqrt = entering_PA_normalCase_sqrt\n val cyc_A6_sqrt = (cycleNum_A === 6.U)\n val cyc_A5_sqrt = (cycleNum_A === 5.U)\n val cyc_A4_sqrt = (cycleNum_A === 4.U)\n\n val cyc_A4_div = entering_PA_normalCase_div\n\n val cyc_A4 = cyc_A4_sqrt || cyc_A4_div\n val cyc_A3 = (cycleNum_A === 3.U)\n val cyc_A2 = (cycleNum_A === 2.U)\n val cyc_A1 = (cycleNum_A === 1.U)\n\n val cyc_A3_div = cyc_A3 && ! sqrtOp_PA\n val cyc_A2_div = cyc_A2 && ! sqrtOp_PA\n val cyc_A1_div = cyc_A1 && ! sqrtOp_PA\n\n val cyc_A3_sqrt = cyc_A3 && sqrtOp_PA\n val cyc_A2_sqrt = cyc_A2 && sqrtOp_PA\n val cyc_A1_sqrt = cyc_A1 && sqrtOp_PA\n\n when (cyc_A1 || (cycleNum_B =/= 0.U)) {\n cycleNum_B :=\n Mux(cyc_A1,\n Mux(sqrtOp_PA, 10.U, 6.U),\n cycleNum_B - 1.U\n )\n }\n\n val cyc_B10_sqrt = (cycleNum_B === 10.U)\n val cyc_B9_sqrt = (cycleNum_B === 9.U)\n val cyc_B8_sqrt = (cycleNum_B === 8.U)\n val cyc_B7_sqrt = (cycleNum_B === 7.U)\n\n val cyc_B6 = (cycleNum_B === 6.U)\n val cyc_B5 = (cycleNum_B === 5.U)\n val cyc_B4 = (cycleNum_B === 4.U)\n val cyc_B3 = (cycleNum_B === 3.U)\n val cyc_B2 = (cycleNum_B === 2.U)\n val cyc_B1 = (cycleNum_B === 1.U)\n\n val cyc_B6_div = cyc_B6 && valid_PA && ! sqrtOp_PA\n val cyc_B5_div = cyc_B5 && valid_PA && ! sqrtOp_PA\n val cyc_B4_div = cyc_B4 && valid_PA && ! sqrtOp_PA\n val cyc_B3_div = cyc_B3 && ! sqrtOp_PB\n val cyc_B2_div = cyc_B2 && ! sqrtOp_PB\n val cyc_B1_div = cyc_B1 && ! sqrtOp_PB\n\n val cyc_B6_sqrt = cyc_B6 && valid_PB && sqrtOp_PB\n val cyc_B5_sqrt = cyc_B5 && valid_PB && sqrtOp_PB\n val cyc_B4_sqrt = cyc_B4 && valid_PB && sqrtOp_PB\n val cyc_B3_sqrt = cyc_B3 && sqrtOp_PB\n val cyc_B2_sqrt = cyc_B2 && sqrtOp_PB\n val cyc_B1_sqrt = cyc_B1 && sqrtOp_PB\n\n when (cyc_B1 || (cycleNum_C =/= 0.U)) {\n cycleNum_C :=\n Mux(cyc_B1, Mux(sqrtOp_PB, 6.U, 5.U), cycleNum_C - 1.U)\n }\n\n val cyc_C6_sqrt = (cycleNum_C === 6.U)\n\n val cyc_C5 = (cycleNum_C === 5.U)\n val cyc_C4 = (cycleNum_C === 4.U)\n val cyc_C3 = (cycleNum_C === 3.U)\n val cyc_C2 = (cycleNum_C === 2.U)\n val cyc_C1 = (cycleNum_C === 1.U)\n\n val cyc_C5_div = cyc_C5 && ! sqrtOp_PB\n val cyc_C4_div = cyc_C4 && ! sqrtOp_PB\n val cyc_C3_div = cyc_C3 && ! sqrtOp_PB\n val cyc_C2_div = cyc_C2 && ! sqrtOp_PC\n val cyc_C1_div = cyc_C1 && ! sqrtOp_PC\n\n val cyc_C5_sqrt = cyc_C5 && sqrtOp_PB\n val cyc_C4_sqrt = cyc_C4 && sqrtOp_PB\n val cyc_C3_sqrt = cyc_C3 && sqrtOp_PB\n val cyc_C2_sqrt = cyc_C2 && sqrtOp_PC\n val cyc_C1_sqrt = cyc_C1 && sqrtOp_PC\n\n when (cyc_C1 || (cycleNum_E =/= 0.U)) {\n cycleNum_E := Mux(cyc_C1, 4.U, cycleNum_E - 1.U)\n }\n\n val cyc_E4 = (cycleNum_E === 4.U)\n val cyc_E3 = (cycleNum_E === 3.U)\n val cyc_E2 = (cycleNum_E === 2.U)\n val cyc_E1 = (cycleNum_E === 1.U)\n\n val cyc_E4_div = cyc_E4 && ! sqrtOp_PC\n val cyc_E3_div = cyc_E3 && ! sqrtOp_PC\n val cyc_E2_div = cyc_E2 && ! sqrtOp_PC\n val cyc_E1_div = cyc_E1 && ! sqrtOp_PC\n\n val cyc_E4_sqrt = cyc_E4 && sqrtOp_PC\n val cyc_E3_sqrt = cyc_E3 && sqrtOp_PC\n val cyc_E2_sqrt = cyc_E2 && sqrtOp_PC\n val cyc_E1_sqrt = cyc_E1 && sqrtOp_PC\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PA =\n entering_PA_normalCase || (cyc_S && (valid_PA || ! ready_PB))\n\n when (entering_PA || leaving_PA) {\n valid_PA := entering_PA\n }\n when (entering_PA) {\n sqrtOp_PA := io.sqrtOp\n majorExc_PA := majorExc_S\n isNaN_PA := isNaN_S\n isInf_PA := isInf_S\n isZero_PA := isZero_S\n sign_PA := sign_S\n }\n when (entering_PA_normalCase) {\n sExp_PA := Mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div)\n fractB_PA := rawB_S.sig(51, 0)\n roundingMode_PA := io.roundingMode\n }\n when (entering_PA_normalCase_div) {\n fractA_PA := rawA_S.sig(51, 0)\n }\n\n val normalCase_PA = ! isNaN_PA && ! isInf_PA && ! isZero_PA\n val sigA_PA = 1.U(1.W) ## fractA_PA\n val sigB_PA = 1.U(1.W) ## fractB_PA\n\n val valid_normalCase_leaving_PA = cyc_B4_div || cyc_B7_sqrt\n val valid_leaving_PA =\n Mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)\n leaving_PA := valid_PA && valid_leaving_PA\n ready_PA := ! valid_PA || valid_leaving_PA\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PB_S =\n cyc_S && ! normalCase_S && ! valid_PA &&\n (leaving_PB || (! valid_PB && ! ready_PC))\n val entering_PB_normalCase =\n valid_PA && normalCase_PA && valid_normalCase_leaving_PA\n val entering_PB = entering_PB_S || leaving_PA\n\n when (entering_PB || leaving_PB) {\n valid_PB := entering_PB\n }\n when (entering_PB) {\n sqrtOp_PB := Mux(valid_PA, sqrtOp_PA, io.sqrtOp )\n majorExc_PB := Mux(valid_PA, majorExc_PA, majorExc_S)\n isNaN_PB := Mux(valid_PA, isNaN_PA, isNaN_S )\n isInf_PB := Mux(valid_PA, isInf_PA, isInf_S )\n isZero_PB := Mux(valid_PA, isZero_PA, isZero_S )\n sign_PB := Mux(valid_PA, sign_PA, sign_S )\n }\n when (entering_PB_normalCase) {\n sExp_PB := sExp_PA\n bit0FractA_PB := fractA_PA(0)\n fractB_PB := fractB_PA\n roundingMode_PB := Mux(valid_PA, roundingMode_PA, io.roundingMode)\n }\n\n val normalCase_PB = ! isNaN_PB && ! isInf_PB && ! isZero_PB\n\n val valid_normalCase_leaving_PB = cyc_C3\n val valid_leaving_PB =\n Mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)\n leaving_PB := valid_PB && valid_leaving_PB\n ready_PB := ! valid_PB || valid_leaving_PB\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PC_S =\n cyc_S && ! normalCase_S && ! valid_PA && ! valid_PB && ready_PC\n val entering_PC_normalCase =\n valid_PB && normalCase_PB && valid_normalCase_leaving_PB\n val entering_PC = entering_PC_S || leaving_PB\n\n when (entering_PC || leaving_PC) {\n valid_PC := entering_PC\n }\n when (entering_PC) {\n sqrtOp_PC := Mux(valid_PB, sqrtOp_PB, io.sqrtOp )\n majorExc_PC := Mux(valid_PB, majorExc_PB, majorExc_S)\n isNaN_PC := Mux(valid_PB, isNaN_PB, isNaN_S )\n isInf_PC := Mux(valid_PB, isInf_PB, isInf_S )\n isZero_PC := Mux(valid_PB, isZero_PB, isZero_S )\n sign_PC := Mux(valid_PB, sign_PB, sign_S )\n }\n when (entering_PC_normalCase) {\n sExp_PC := sExp_PB\n bit0FractA_PC := bit0FractA_PB\n fractB_PC := fractB_PB\n roundingMode_PC := Mux(valid_PB, roundingMode_PB, io.roundingMode)\n }\n\n val normalCase_PC = ! isNaN_PC && ! isInf_PC && ! isZero_PC\n val sigB_PC = 1.U(1.W) ## fractB_PC\n\n val valid_leaving_PC = ! normalCase_PC || cyc_E1\n leaving_PC := valid_PC && valid_leaving_PC\n ready_PC := ! valid_PC || valid_leaving_PC\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n//*** NEED TO COMPUTE AS MUCH AS POSSIBLE IN PREVIOUS CYCLE?:\n io.inReady_div :=\n//*** REPLACE ALL OF '! cyc_B*_sqrt' BY '! (valid_PB && sqrtOp_PB)'?:\n ready_PA && ! cyc_B7_sqrt && ! cyc_B6_sqrt && ! cyc_B5_sqrt &&\n ! cyc_B4_sqrt && ! cyc_B3 && ! cyc_B2 && ! cyc_B1_sqrt &&\n ! cyc_C5 && ! cyc_C4\n io.inReady_sqrt :=\n ready_PA && ! cyc_B6_sqrt && ! cyc_B5_sqrt && ! cyc_B4_sqrt &&\n ! cyc_B2_div && ! cyc_B1_sqrt\n\n /*------------------------------------------------------------------------\n | Macrostage A, built around a 9x9-bit multiplier-adder.\n *------------------------------------------------------------------------*/\n val zFractB_A4_div = Mux(cyc_A4_div, rawB_S.sig(51, 0), 0.U)\n\n val zLinPiece_0_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 0.U)\n val zLinPiece_1_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 1.U)\n val zLinPiece_2_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 2.U)\n val zLinPiece_3_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 3.U)\n val zLinPiece_4_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 4.U)\n val zLinPiece_5_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 5.U)\n val zLinPiece_6_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 6.U)\n val zLinPiece_7_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 7.U)\n val zK1_A4_div =\n Mux(zLinPiece_0_A4_div, \"h1C7\".U, 0.U) |\n Mux(zLinPiece_1_A4_div, \"h16C\".U, 0.U) |\n Mux(zLinPiece_2_A4_div, \"h12A\".U, 0.U) |\n Mux(zLinPiece_3_A4_div, \"h0F8\".U, 0.U) |\n Mux(zLinPiece_4_A4_div, \"h0D2\".U, 0.U) |\n Mux(zLinPiece_5_A4_div, \"h0B4\".U, 0.U) |\n Mux(zLinPiece_6_A4_div, \"h09C\".U, 0.U) |\n Mux(zLinPiece_7_A4_div, \"h089\".U, 0.U)\n val zComplFractK0_A4_div =\n Mux(zLinPiece_0_A4_div, ~\"hFE3\".U(12.W), 0.U) |\n Mux(zLinPiece_1_A4_div, ~\"hC5D\".U(12.W), 0.U) |\n Mux(zLinPiece_2_A4_div, ~\"h98A\".U(12.W), 0.U) |\n Mux(zLinPiece_3_A4_div, ~\"h739\".U(12.W), 0.U) |\n Mux(zLinPiece_4_A4_div, ~\"h54B\".U(12.W), 0.U) |\n Mux(zLinPiece_5_A4_div, ~\"h3A9\".U(12.W), 0.U) |\n Mux(zLinPiece_6_A4_div, ~\"h242\".U(12.W), 0.U) |\n Mux(zLinPiece_7_A4_div, ~\"h10B\".U(12.W), 0.U)\n\n val zFractB_A7_sqrt = Mux(cyc_A7_sqrt, rawB_S.sig(51, 0), 0.U)\n\n val zQuadPiece_0_A7_sqrt =\n cyc_A7_sqrt && ! rawB_S.sExp(0) && ! rawB_S.sig(51)\n val zQuadPiece_1_A7_sqrt =\n cyc_A7_sqrt && ! rawB_S.sExp(0) && rawB_S.sig(51)\n val zQuadPiece_2_A7_sqrt =\n cyc_A7_sqrt && rawB_S.sExp(0) && ! rawB_S.sig(51)\n val zQuadPiece_3_A7_sqrt = cyc_A7_sqrt && rawB_S.sExp(0) && rawB_S.sig(51)\n val zK2_A7_sqrt =\n Mux(zQuadPiece_0_A7_sqrt, \"h1C8\".U, 0.U) |\n Mux(zQuadPiece_1_A7_sqrt, \"h0C1\".U, 0.U) |\n Mux(zQuadPiece_2_A7_sqrt, \"h143\".U, 0.U) |\n Mux(zQuadPiece_3_A7_sqrt, \"h089\".U, 0.U)\n val zComplK1_A7_sqrt =\n Mux(zQuadPiece_0_A7_sqrt, ~\"h3D0\".U(10.W), 0.U) |\n Mux(zQuadPiece_1_A7_sqrt, ~\"h220\".U(10.W), 0.U) |\n Mux(zQuadPiece_2_A7_sqrt, ~\"h2B2\".U(10.W), 0.U) |\n Mux(zQuadPiece_3_A7_sqrt, ~\"h181\".U(10.W), 0.U)\n\n val zQuadPiece_0_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && ! sigB_PA(51)\n val zQuadPiece_1_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && sigB_PA(51)\n val zQuadPiece_2_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && ! sigB_PA(51)\n val zQuadPiece_3_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && sigB_PA(51)\n val zComplFractK0_A6_sqrt =\n Mux(zQuadPiece_0_A6_sqrt, ~\"h1FE5\".U(13.W), 0.U) |\n Mux(zQuadPiece_1_A6_sqrt, ~\"h1435\".U(13.W), 0.U) |\n Mux(zQuadPiece_2_A6_sqrt, ~\"h0D2C\".U(13.W), 0.U) |\n Mux(zQuadPiece_3_A6_sqrt, ~\"h04E8\".U(13.W), 0.U)\n\n val mulAdd9A_A =\n zFractB_A4_div(48, 40) | zK2_A7_sqrt |\n Mux(! cyc_S, nextMulAdd9A_A, 0.U)\n val mulAdd9B_A =\n zK1_A4_div | zFractB_A7_sqrt(50, 42) |\n Mux(! cyc_S, nextMulAdd9B_A, 0.U)\n val mulAdd9C_A =\n//*** ADJUST CONSTANTS SO 'Fill'S AREN'T NEEDED:\n zComplK1_A7_sqrt ## Fill(10, cyc_A7_sqrt) |\n Cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt, Fill(6, cyc_A6_sqrt)) |\n Cat(cyc_A4_div, zComplFractK0_A4_div, Fill(8, cyc_A4_div )) |\n Mux(cyc_A5_sqrt, (1<<18).U +& (fractR0_A<<10), 0.U) |\n Mux(cyc_A4_sqrt && ! hiSqrR0_A_sqrt(9), (1<<10).U, 0.U) |\n Mux((cyc_A4_sqrt && hiSqrR0_A_sqrt(9)) || cyc_A3_div,\n sigB_PA(46, 26) + (1<<10).U,\n 0.U\n ) |\n Mux(cyc_A3_sqrt || cyc_A2, partNegSigma0_A, 0.U) |\n Mux(cyc_A1_sqrt, fractR0_A<<16, 0.U) |\n Mux(cyc_A1_div, fractR0_A<<15, 0.U)\n val loMulAdd9Out_A = mulAdd9A_A * mulAdd9B_A +& mulAdd9C_A(17, 0)\n val mulAdd9Out_A =\n Cat(Mux(loMulAdd9Out_A(18),\n mulAdd9C_A(24, 18) + 1.U,\n mulAdd9C_A(24, 18)\n ),\n loMulAdd9Out_A(17, 0)\n )\n\n val zFractR0_A6_sqrt =\n Mux(cyc_A6_sqrt && mulAdd9Out_A(19), ~(mulAdd9Out_A>>10), 0.U)\n /*------------------------------------------------------------------------\n | ('sqrR0_A5_sqrt' is usually >= 1, but not always.)\n *------------------------------------------------------------------------*/\n val sqrR0_A5_sqrt = Mux(sExp_PA(0), mulAdd9Out_A<<1, mulAdd9Out_A)\n val zFractR0_A4_div =\n Mux(cyc_A4_div && mulAdd9Out_A(20), ~(mulAdd9Out_A>>11), 0.U)\n val zSigma0_A2 =\n Mux(cyc_A2 && mulAdd9Out_A(11), ~(mulAdd9Out_A>>2), 0.U)\n val r1_A1 = (1<<15).U | Mux(sqrtOp_PA, mulAdd9Out_A>>10, mulAdd9Out_A>>9)\n val ER1_A1_sqrt = Mux(sExp_PA(0), r1_A1<<1, r1_A1)\n\n when (cyc_A6_sqrt || cyc_A4_div) {\n fractR0_A := zFractR0_A6_sqrt | zFractR0_A4_div\n }\n when (cyc_A5_sqrt) {\n hiSqrR0_A_sqrt := sqrR0_A5_sqrt>>10\n }\n when (cyc_A4_sqrt || cyc_A3) {\n partNegSigma0_A := Mux(cyc_A4_sqrt, mulAdd9Out_A, mulAdd9Out_A>>9)\n }\n when (\n cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A3 || cyc_A2\n ) {\n nextMulAdd9A_A :=\n Mux(cyc_A7_sqrt, ~mulAdd9Out_A>>11, 0.U) |\n zFractR0_A6_sqrt |\n Mux(cyc_A4_sqrt, sigB_PA(43, 35), 0.U) |\n zFractB_A4_div(43, 35) |\n Mux(cyc_A5_sqrt || cyc_A3, sigB_PA(52, 44), 0.U) |\n zSigma0_A2\n }\n when (cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A2) {\n nextMulAdd9B_A :=\n zFractB_A7_sqrt(50, 42) |\n zFractR0_A6_sqrt |\n Mux(cyc_A5_sqrt, sqrR0_A5_sqrt(9, 1), 0.U) |\n zFractR0_A4_div |\n Mux(cyc_A4_sqrt, hiSqrR0_A_sqrt(8, 0), 0.U) |\n Mux(cyc_A2, Cat(1.U(1.W), fractR0_A(8, 1)), 0.U)\n }\n when (cyc_A1_sqrt) {\n ER1_B_sqrt := ER1_A1_sqrt\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.latchMulAddA_0 :=\n cyc_A1 || cyc_B7_sqrt || cyc_B6_div || cyc_B4 || cyc_B3 ||\n cyc_C6_sqrt || cyc_C4 || cyc_C1\n io.mulAddA_0 :=\n Mux(cyc_A1_sqrt, ER1_A1_sqrt<<36, 0.U) | // 52:36\n Mux(cyc_B7_sqrt || cyc_A1_div, sigB_PA, 0.U) | // 52:0\n Mux(cyc_B6_div, sigA_PA, 0.U) | // 52:0\n zSigma1_B4(45, 12) | // 33:0\n//*** ONLY 30 BITS NEEDED IN CYCLE C6:\n Mux(cyc_B3 || cyc_C6_sqrt, sigXNU_B3_CX(57, 12), 0.U) | // 45:0\n Mux(cyc_C4_div, sigXN_C(57, 25)<<13, 0.U) | // 45:13\n Mux(cyc_C4_sqrt, u_C_sqrt<<15, 0.U) | // 45:15\n Mux(cyc_C1_div, sigB_PC, 0.U) | // 52:0\n zComplSigT_C1_sqrt // 53:0\n io.latchMulAddB_0 :=\n cyc_A1 || cyc_B7_sqrt || cyc_B6_sqrt || cyc_B4 ||\n cyc_C6_sqrt || cyc_C4 || cyc_C1\n io.mulAddB_0 :=\n Mux(cyc_A1, r1_A1<<36, 0.U) | // 51:36\n Mux(cyc_B7_sqrt, ESqrR1_B_sqrt<<19, 0.U) | // 50:19\n Mux(cyc_B6_sqrt, ER1_B_sqrt<<36, 0.U) | // 52:36\n zSigma1_B4 | // 45:0\n Mux(cyc_C6_sqrt, sqrSigma1_C(30, 1), 0.U) | // 29:0\n Mux(cyc_C4, sqrSigma1_C, 0.U) | // 32:0\n zComplSigT_C1 // 53:0\n\n io.usingMulAdd :=\n Cat(cyc_A4 || cyc_A3_div || cyc_A1_div ||\n cyc_B10_sqrt || cyc_B9_sqrt || cyc_B7_sqrt || cyc_B6 ||\n cyc_B5_sqrt || cyc_B3_sqrt || cyc_B2_div || cyc_B1_sqrt ||\n cyc_C4,\n cyc_A3 || cyc_A2_div ||\n cyc_B9_sqrt || cyc_B8_sqrt || cyc_B6 || cyc_B5 ||\n cyc_B4_sqrt || cyc_B2_sqrt || cyc_B1_div || cyc_C6_sqrt ||\n cyc_C3,\n cyc_A2 || cyc_A1_div ||\n cyc_B8_sqrt || cyc_B7_sqrt || cyc_B5 || cyc_B4 ||\n cyc_B3_sqrt || cyc_B1_sqrt || cyc_C5 ||\n cyc_C2,\n io.latchMulAddA_0 || cyc_B6 || cyc_B2_sqrt\n )\n\n io.mulAddC_2 :=\n Mux(cyc_B1, sigX1_B<<47, 0.U) |\n Mux(cyc_C6_sqrt, sigX1_B<<46, 0.U) |\n Mux(cyc_C4_sqrt || cyc_C2, sigXN_C<<47, 0.U) |\n Mux(cyc_E3_div && ! E_E_div, bit0FractA_PC<<53, 0.U) |\n Mux(cyc_E3_sqrt,\n (Mux(sExp_PC(0),\n sigB_PC(0)<<1,\n (sigB_PC(1) ^ sigB_PC(0)) ## sigB_PC(0)\n ) ^ ((~ sigT_E(0))<<1)\n )<<54,\n 0.U\n )\n\n val ESqrR1_B8_sqrt = io.mulAddResult_3(103, 72)\n zSigma1_B4 := Mux(cyc_B4, ~io.mulAddResult_3(90, 45), 0.U)\n val sqrSigma1_B1 = io.mulAddResult_3(79, 47)\n sigXNU_B3_CX := io.mulAddResult_3(104, 47) // x1, x2, u (sqrt), xT'\n val E_C1_div = ! io.mulAddResult_3(104)\n zComplSigT_C1 :=\n Mux((cyc_C1_div && ! E_C1_div) || cyc_C1_sqrt,\n ~io.mulAddResult_3(104, 51),\n 0.U\n ) |\n Mux(cyc_C1_div && E_C1_div, ~io.mulAddResult_3(102, 50), 0.U)\n zComplSigT_C1_sqrt :=\n Mux(cyc_C1_sqrt, ~io.mulAddResult_3(104, 51), 0.U)\n /*------------------------------------------------------------------------\n | (For square root, 'sigT_C1' will usually be >= 1, but not always.)\n *------------------------------------------------------------------------*/\n val sigT_C1 = ~zComplSigT_C1\n val remT_E2 = io.mulAddResult_3(55, 0)\n\n when (cyc_B8_sqrt) {\n ESqrR1_B_sqrt := ESqrR1_B8_sqrt\n }\n when (cyc_B3) {\n sigX1_B := sigXNU_B3_CX\n }\n when (cyc_B1) {\n sqrSigma1_C := sqrSigma1_B1\n }\n\n when (cyc_C6_sqrt || cyc_C5_div || cyc_C3_sqrt) {\n sigXN_C := sigXNU_B3_CX\n }\n when (cyc_C5_sqrt) {\n u_C_sqrt := sigXNU_B3_CX(56, 26)\n }\n when (cyc_C1) {\n E_E_div := E_C1_div\n sigT_E := sigT_C1\n }\n\n when (cyc_E2) {\n isNegRemT_E := Mux(sqrtOp_PC, remT_E2(55), remT_E2(53))\n isZeroRemT_E :=\n (remT_E2(53, 0) === 0.U) &&\n (! sqrtOp_PC || (remT_E2(55, 54) === 0.U))\n }\n\n /*------------------------------------------------------------------------\n | T is the lower-bound \"trial\" result value, with 54 bits of precision.\n | It is known that the true unrounded result is within the range of\n | (T, T + (2 ulps of 54 bits)). X is defined as the best estimate,\n | = T + (1 ulp), which is exactly in the middle of the possible range.\n *------------------------------------------------------------------------*/\n val trueLtX_E1 =\n Mux(sqrtOp_PC, ! isNegRemT_E && ! isZeroRemT_E, isNegRemT_E)\n val trueEqX_E1 = isZeroRemT_E\n\n /*------------------------------------------------------------------------\n | The inputs to these two values are stable for several clock cycles in\n | advance, so the circuitry can be minimized at the expense of speed.\n*** ANY WAY TO TELL THIS TO THE TOOLS?\n *------------------------------------------------------------------------*/\n val sExpP1_PC = sExp_PC + 1.S\n val sigTP1_E = sigT_E +& 1.U\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := leaving_PC && ! sqrtOp_PC\n io.rawOutValid_sqrt := leaving_PC && sqrtOp_PC\n io.roundingModeOut := roundingMode_PC\n io.invalidExc := majorExc_PC && isNaN_PC\n io.infiniteExc := majorExc_PC && ! isNaN_PC\n io.rawOut.isNaN := isNaN_PC\n io.rawOut.isInf := isInf_PC\n io.rawOut.isZero := isZero_PC\n io.rawOut.sign := sign_PC\n io.rawOut.sExp :=\n Mux(! sqrtOp_PC && E_E_div, sExp_PC, 0.S) |\n Mux(! sqrtOp_PC && ! E_E_div, sExpP1_PC, 0.S) |\n Mux( sqrtOp_PC, (sExp_PC>>1) +& 1024.S, 0.S)\n io.rawOut.sig := Mux(trueLtX_E1, sigT_E, sigTP1_E) ## ! trueEqX_E1\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass DivSqrtRecF64_mulAddZ31(options: Int) extends Module\n{\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val usingMulAdd = Output(Bits(4.W))\n val latchMulAddA_0 = Output(Bool())\n val mulAddA_0 = Output(UInt(54.W))\n val latchMulAddB_0 = Output(Bool())\n val mulAddB_0 = Output(UInt(54.W))\n val mulAddC_2 = Output(UInt(105.W))\n val mulAddResult_3 = Input(UInt(105.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(Bits(65.W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecF64ToRaw = Module(new DivSqrtRecF64ToRaw_mulAddZ31)\n\n io.inReady_div := divSqrtRecF64ToRaw.io.inReady_div\n io.inReady_sqrt := divSqrtRecF64ToRaw.io.inReady_sqrt\n divSqrtRecF64ToRaw.io.inValid := io.inValid\n divSqrtRecF64ToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecF64ToRaw.io.a := io.a\n divSqrtRecF64ToRaw.io.b := io.b\n divSqrtRecF64ToRaw.io.roundingMode := io.roundingMode\n\n io.usingMulAdd := divSqrtRecF64ToRaw.io.usingMulAdd\n io.latchMulAddA_0 := divSqrtRecF64ToRaw.io.latchMulAddA_0\n io.mulAddA_0 := divSqrtRecF64ToRaw.io.mulAddA_0\n io.latchMulAddB_0 := divSqrtRecF64ToRaw.io.latchMulAddB_0\n io.mulAddB_0 := divSqrtRecF64ToRaw.io.mulAddB_0\n io.mulAddC_2 := divSqrtRecF64ToRaw.io.mulAddC_2\n divSqrtRecF64ToRaw.io.mulAddResult_3 := io.mulAddResult_3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecF64ToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecF64ToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(11, 53, flRoundOpt_sigMSBitAlwaysZero))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecF64ToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecF64ToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecF64ToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecF64ToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRecF64_mulAddZ31(\n input clock,\n input reset,\n output io_inReady_div,\n output io_inReady_sqrt,\n input io_inValid,\n input io_sqrtOp,\n input [64:0] io_a,\n input [64:0] io_b,\n input [2:0] io_roundingMode,\n output [3:0] io_usingMulAdd,\n output io_latchMulAddA_0,\n output [53:0] io_mulAddA_0,\n output io_latchMulAddB_0,\n output [53:0] io_mulAddB_0,\n output [104:0] io_mulAddC_2,\n input [104:0] io_mulAddResult_3,\n output io_outValid_div,\n output io_outValid_sqrt,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire [2:0] _divSqrtRecF64ToRaw_io_roundingModeOut;\n wire _divSqrtRecF64ToRaw_io_invalidExc;\n wire _divSqrtRecF64ToRaw_io_infiniteExc;\n wire _divSqrtRecF64ToRaw_io_rawOut_isNaN;\n wire _divSqrtRecF64ToRaw_io_rawOut_isInf;\n wire _divSqrtRecF64ToRaw_io_rawOut_isZero;\n wire _divSqrtRecF64ToRaw_io_rawOut_sign;\n wire [12:0] _divSqrtRecF64ToRaw_io_rawOut_sExp;\n wire [55:0] _divSqrtRecF64ToRaw_io_rawOut_sig;\n DivSqrtRecF64ToRaw_mulAddZ31 divSqrtRecF64ToRaw (\n .clock (clock),\n .reset (reset),\n .io_inReady_div (io_inReady_div),\n .io_inReady_sqrt (io_inReady_sqrt),\n .io_inValid (io_inValid),\n .io_sqrtOp (io_sqrtOp),\n .io_a (io_a),\n .io_b (io_b),\n .io_roundingMode (io_roundingMode),\n .io_usingMulAdd (io_usingMulAdd),\n .io_latchMulAddA_0 (io_latchMulAddA_0),\n .io_mulAddA_0 (io_mulAddA_0),\n .io_latchMulAddB_0 (io_latchMulAddB_0),\n .io_mulAddB_0 (io_mulAddB_0),\n .io_mulAddC_2 (io_mulAddC_2),\n .io_mulAddResult_3 (io_mulAddResult_3),\n .io_rawOutValid_div (io_outValid_div),\n .io_rawOutValid_sqrt (io_outValid_sqrt),\n .io_roundingModeOut (_divSqrtRecF64ToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecF64ToRaw_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e11_s53_1 roundRawFNToRecFN (\n .io_invalidExc (_divSqrtRecF64ToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecF64ToRaw_io_infiniteExc),\n .io_in_isNaN (_divSqrtRecF64ToRaw_io_rawOut_isNaN),\n .io_in_isInf (_divSqrtRecF64ToRaw_io_rawOut_isInf),\n .io_in_isZero (_divSqrtRecF64ToRaw_io_rawOut_isZero),\n .io_in_sign (_divSqrtRecF64ToRaw_io_rawOut_sign),\n .io_in_sExp (_divSqrtRecF64ToRaw_io_rawOut_sExp),\n .io_in_sig (_divSqrtRecF64ToRaw_io_rawOut_sig),\n .io_roundingMode (_divSqrtRecF64ToRaw_io_roundingModeOut),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPToFP(\n input clock,\n input reset,\n input io_in_valid,\n input io_in_bits_ren2,\n input [1:0] io_in_bits_typeTagOut,\n input io_in_bits_wflags,\n input [2:0] io_in_bits_rm,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n output io_out_valid,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc,\n input io_lt\n);\n\n wire [32:0] _narrower_io_out;\n wire [4:0] _narrower_io_exceptionFlags;\n reg in_pipe_v;\n reg in_pipe_b_ren2;\n reg [1:0] in_pipe_b_typeTagOut;\n reg in_pipe_b_wflags;\n reg [2:0] in_pipe_b_rm;\n reg [64:0] in_pipe_b_in1;\n reg [64:0] in_pipe_b_in2;\n wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2;\n wire [64:0] fsgnjMux_data = _GEN ? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1) : in_pipe_b_wflags ? ((&(in_pipe_b_in1[63:61])) & (&(in_pipe_b_in2[63:61])) ? 65'hE008000000000000 : (&(in_pipe_b_in2[63:61])) | in_pipe_b_rm[0] != io_lt & ~(&(in_pipe_b_in1[63:61])) ? in_pipe_b_in1 : in_pipe_b_in2) : {in_pipe_b_rm[1] ? in_pipe_b_in1[64] ^ in_pipe_b_in2[64] : in_pipe_b_rm[0] ^ in_pipe_b_in2[64], in_pipe_b_in1[63:0]};\n reg io_out_pipe_v;\n reg [64:0] io_out_pipe_b_data;\n reg [4:0] io_out_pipe_b_exc;\n reg io_out_pipe_pipe_v;\n reg [64:0] io_out_pipe_pipe_b_data;\n reg [4:0] io_out_pipe_pipe_b_exc;\n reg io_out_pipe_pipe_pipe_v;\n reg [64:0] io_out_pipe_pipe_pipe_b_data;\n reg [4:0] io_out_pipe_pipe_pipe_b_exc;\n wire _GEN_0 = in_pipe_b_typeTagOut == 2'h0;\n wire [8:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[60:52] - 9'h100;\n always @(posedge clock) begin\n if (reset) begin\n in_pipe_v <= 1'h0;\n io_out_pipe_v <= 1'h0;\n io_out_pipe_pipe_v <= 1'h0;\n io_out_pipe_pipe_pipe_v <= 1'h0;\n end\n else begin\n in_pipe_v <= io_in_valid;\n io_out_pipe_v <= in_pipe_v;\n io_out_pipe_pipe_v <= io_out_pipe_v;\n io_out_pipe_pipe_pipe_v <= io_out_pipe_pipe_v;\n end\n if (io_in_valid) begin\n in_pipe_b_ren2 <= io_in_bits_ren2;\n in_pipe_b_typeTagOut <= io_in_bits_typeTagOut;\n in_pipe_b_wflags <= io_in_bits_wflags;\n in_pipe_b_rm <= io_in_bits_rm;\n in_pipe_b_in1 <= io_in_bits_in1;\n in_pipe_b_in2 <= io_in_bits_in2;\n end\n if (in_pipe_v) begin\n io_out_pipe_b_data <= _GEN_0 ? (_GEN ? {fsgnjMux_data[64:33], _narrower_io_out} : {fsgnjMux_data[64:33], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 | fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[5:0]} : _mux_data_expOut_commonCase_T, fsgnjMux_data[51:29]}) : fsgnjMux_data;\n io_out_pipe_b_exc <= _GEN & _GEN_0 ? _narrower_io_exceptionFlags : _GEN ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0} : in_pipe_b_wflags ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]) | (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]), 4'h0} : 5'h0;\n end\n if (io_out_pipe_v) begin\n io_out_pipe_pipe_b_data <= io_out_pipe_b_data;\n io_out_pipe_pipe_b_exc <= io_out_pipe_b_exc;\n end\n if (io_out_pipe_pipe_v) begin\n io_out_pipe_pipe_pipe_b_data <= io_out_pipe_pipe_b_data;\n io_out_pipe_pipe_pipe_b_exc <= io_out_pipe_pipe_b_exc;\n end\n end\n RecFNToRecFN narrower (\n .io_in (in_pipe_b_in1),\n .io_roundingMode (in_pipe_b_rm),\n .io_detectTininess (1'h1),\n .io_out (_narrower_io_out),\n .io_exceptionFlags (_narrower_io_exceptionFlags)\n );\n assign io_out_valid = io_out_pipe_pipe_pipe_v;\n assign io_out_bits_data = io_out_pipe_pipe_pipe_b_data;\n assign io_out_bits_exc = io_out_pipe_pipe_pipe_b_exc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_5(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.subsystem.CacheBlockBytes\nimport freechips.rocketchip.tile.HasCoreParameters\nimport freechips.rocketchip.util._\n\ncase class BHTParams(\n nEntries: Int = 512,\n counterLength: Int = 1,\n historyLength: Int = 8,\n historyBits: Int = 3)\n\ncase class BTBParams(\n nEntries: Int = 28,\n nMatchBits: Int = 14,\n nPages: Int = 6,\n nRAS: Int = 6,\n bhtParams: Option[BHTParams] = Some(BHTParams()),\n updatesOutOfOrder: Boolean = false)\n\ntrait HasBtbParameters extends HasCoreParameters { this: InstanceId =>\n val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))\n val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)\n val entries = btbParams.nEntries\n val updatesOutOfOrder = btbParams.updatesOutOfOrder\n val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages\n}\n\nabstract class BtbModule(implicit val p: Parameters) extends Module with HasBtbParameters {\n Annotated.params(this, btbParams)\n}\n\nabstract class BtbBundle(implicit val p: Parameters) extends Bundle with HasBtbParameters\n\nclass RAS(nras: Int) {\n def push(addr: UInt): Unit = {\n when (count < nras.U) { count := count + 1.U }\n val nextPos = Mux((isPow2(nras)).B || pos < (nras-1).U, pos+1.U, 0.U)\n stack(nextPos) := addr\n pos := nextPos\n }\n def peek: UInt = stack(pos)\n def pop(): Unit = when (!isEmpty) {\n count := count - 1.U\n pos := Mux((isPow2(nras)).B || pos > 0.U, pos-1.U, (nras-1).U)\n }\n def clear(): Unit = count := 0.U\n def isEmpty: Bool = count === 0.U\n\n private val count = RegInit(0.U(log2Up(nras+1).W))\n private val pos = RegInit(0.U(log2Up(nras).W))\n private val stack = Reg(Vec(nras, UInt()))\n}\n\nclass BHTResp(implicit p: Parameters) extends BtbBundle()(p) {\n val history = UInt(btbParams.bhtParams.map(_.historyLength).getOrElse(1).W)\n val value = UInt(btbParams.bhtParams.map(_.counterLength).getOrElse(1).W)\n def taken = value(0)\n def strongly_taken = value === 1.U\n}\n\n// BHT contains table of 2-bit counters and a global history register.\n// The BHT only predicts and updates when there is a BTB hit.\n// The global history:\n// - updated speculatively in fetch (if there's a BTB hit).\n// - on a mispredict, the history register is reset (again, only if BTB hit).\n// The counter table:\n// - each counter corresponds with the address of the fetch packet (\"fetch pc\").\n// - updated when a branch resolves (and BTB was a hit for that branch).\n// The updating branch must provide its \"fetch pc\".\nclass BHT(params: BHTParams)(implicit val p: Parameters) extends HasCoreParameters {\n def index(addr: UInt, history: UInt) = {\n def hashHistory(hist: UInt) = if (params.historyLength == params.historyBits) hist else {\n val k = math.sqrt(3)/2\n val i = BigDecimal(k * math.pow(2, params.historyLength)).toBigInt\n (i.U * hist)(params.historyLength-1, params.historyLength-params.historyBits)\n }\n def hashAddr(addr: UInt) = {\n val hi = addr >> log2Ceil(fetchBytes)\n hi(log2Ceil(params.nEntries)-1, 0) ^ (hi >> log2Ceil(params.nEntries))(1, 0)\n }\n hashAddr(addr) ^ (hashHistory(history) << (log2Up(params.nEntries) - params.historyBits))\n }\n def get(addr: UInt): BHTResp = {\n val res = Wire(new BHTResp)\n res.value := Mux(resetting, 0.U, table(index(addr, history)))\n res.history := history\n res\n }\n def updateTable(addr: UInt, d: BHTResp, taken: Bool): Unit = {\n wen := true.B\n when (!resetting) {\n waddr := index(addr, d.history)\n wdata := (params.counterLength match {\n case 1 => taken\n case 2 => Cat(taken ^ d.value(0), d.value === 1.U || d.value(1) && taken)\n })\n }\n }\n def resetHistory(d: BHTResp): Unit = {\n history := d.history\n }\n def updateHistory(addr: UInt, d: BHTResp, taken: Bool): Unit = {\n history := Cat(taken, d.history >> 1)\n }\n def advanceHistory(taken: Bool): Unit = {\n history := Cat(taken, history >> 1)\n }\n\n private val table = Mem(params.nEntries, UInt(params.counterLength.W))\n val history = RegInit(0.U(params.historyLength.W))\n\n private val reset_waddr = RegInit(0.U((params.nEntries.log2+1).W))\n private val resetting = !reset_waddr(params.nEntries.log2)\n private val wen = WireInit(resetting)\n private val waddr = WireInit(reset_waddr)\n private val wdata = WireInit(0.U)\n when (resetting) { reset_waddr := reset_waddr + 1.U }\n when (wen) { table(waddr) := wdata }\n}\n\nobject CFIType {\n def SZ = 2\n def apply() = UInt(SZ.W)\n def branch = 0.U\n def jump = 1.U\n def call = 2.U\n def ret = 3.U\n}\n\n// BTB update occurs during branch resolution (and only on a mispredict).\n// - \"pc\" is what future fetch PCs will tag match against.\n// - \"br_pc\" is the PC of the branch instruction.\nclass BTBUpdate(implicit p: Parameters) extends BtbBundle()(p) {\n val prediction = new BTBResp\n val pc = UInt(vaddrBits.W)\n val target = UInt(vaddrBits.W)\n val taken = Bool()\n val isValid = Bool()\n val br_pc = UInt(vaddrBits.W)\n val cfiType = CFIType()\n}\n\n// BHT update occurs during branch resolution on all conditional branches.\n// - \"pc\" is what future fetch PCs will tag match against.\nclass BHTUpdate(implicit p: Parameters) extends BtbBundle()(p) {\n val prediction = new BHTResp\n val pc = UInt(vaddrBits.W)\n val branch = Bool()\n val taken = Bool()\n val mispredict = Bool()\n}\n\nclass RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {\n val cfiType = CFIType()\n val returnAddr = UInt(vaddrBits.W)\n}\n\n// - \"bridx\" is the low-order PC bits of the predicted branch (after\n// shifting off the lowest log(inst_bytes) bits off).\n// - \"mask\" provides a mask of valid instructions (instructions are\n// masked off by the predicted taken branch from the BTB).\nclass BTBResp(implicit p: Parameters) extends BtbBundle()(p) {\n val cfiType = CFIType()\n val taken = Bool()\n val mask = Bits(fetchWidth.W)\n val bridx = Bits(log2Up(fetchWidth).W)\n val target = UInt(vaddrBits.W)\n val entry = UInt(log2Up(entries + 1).W)\n val bht = new BHTResp\n}\n\nclass BTBReq(implicit p: Parameters) extends BtbBundle()(p) {\n val addr = UInt(vaddrBits.W)\n}\n\n// fully-associative branch target buffer\n// Higher-performance processors may cause BTB updates to occur out-of-order,\n// which requires an extra CAM port for updates (to ensure no duplicates get\n// placed in BTB).\nclass BTB(implicit p: Parameters) extends BtbModule {\n val io = IO(new Bundle {\n val req = Flipped(Valid(new BTBReq))\n val resp = Valid(new BTBResp)\n val btb_update = Flipped(Valid(new BTBUpdate))\n val bht_update = Flipped(Valid(new BHTUpdate))\n val bht_advance = Flipped(Valid(new BTBResp))\n val ras_update = Flipped(Valid(new RASUpdate))\n val ras_head = Valid(UInt(vaddrBits.W))\n val flush = Input(Bool())\n })\n\n val idxs = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W)))\n val idxPages = Reg(Vec(entries, UInt(log2Up(nPages).W)))\n val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W)))\n val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W)))\n val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W)))\n val pageValid = RegInit(0.U(nPages.W))\n val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) }\n\n val isValid = RegInit(0.U(entries.W))\n val cfiType = Reg(Vec(entries, CFIType()))\n val brIdx = Reg(Vec(entries, UInt(log2Up(fetchWidth).W)))\n\n private def page(addr: UInt) = addr >> matchBits\n private def pageMatch(addr: UInt) = {\n val p = page(addr)\n pageValid & pages.map(_ === p).asUInt\n }\n private def idxMatch(addr: UInt) = {\n val idx = addr(matchBits-1, log2Up(coreInstBytes))\n idxs.map(_ === idx).asUInt & isValid\n }\n\n val r_btb_update = Pipe(io.btb_update)\n val update_target = io.req.bits.addr\n\n val pageHit = pageMatch(io.req.bits.addr)\n val idxHit = idxMatch(io.req.bits.addr)\n\n val updatePageHit = pageMatch(r_btb_update.bits.pc)\n val (updateHit, updateHitAddr) =\n if (updatesOutOfOrder) {\n val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))\n (updateHits.orR, OHToUInt(updateHits))\n } else (r_btb_update.bits.prediction.entry < entries.U, r_btb_update.bits.prediction.entry)\n\n val useUpdatePageHit = updatePageHit.orR\n val usePageHit = pageHit.orR\n val doIdxPageRepl = !useUpdatePageHit\n val nextPageRepl = RegInit(0.U(log2Ceil(nPages).W))\n val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, 0.U, UIntToOH(nextPageRepl))\n val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)\n val idxPageUpdate = OHToUInt(idxPageUpdateOH)\n val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, 0.U)\n\n val samePage = page(r_btb_update.bits.pc) === page(update_target)\n val doTgtPageRepl = !samePage && !usePageHit\n val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1)))\n val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, 0.U, tgtPageRepl))\n val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, 0.U)\n\n when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) {\n val both = doIdxPageRepl && doTgtPageRepl\n val next = nextPageRepl + Mux[UInt](both, 2.U, 1.U)\n nextPageRepl := Mux(next >= nPages.U, next(0), next)\n }\n\n val repl = new PseudoLRU(entries)\n val waddr = Mux(updateHit, updateHitAddr, repl.way)\n val r_resp = Pipe(io.resp)\n when (r_resp.valid && r_resp.bits.taken || r_btb_update.valid) {\n repl.access(Mux(r_btb_update.valid, waddr, r_resp.bits.entry))\n }\n\n when (r_btb_update.valid) {\n val mask = UIntToOH(waddr)\n idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes))\n tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes))\n idxPages(waddr) := idxPageUpdate +& 1.U // the +1 corresponds to the <<1 on io.resp.valid\n tgtPages(waddr) := tgtPageUpdate\n cfiType(waddr) := r_btb_update.bits.cfiType\n isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask)\n if (fetchWidth > 1)\n brIdx(waddr) := r_btb_update.bits.br_pc >> log2Up(coreInstBytes)\n\n require(nPages % 2 == 0)\n val idxWritesEven = !idxPageUpdate(0)\n\n def writeBank(i: Int, mod: Int, en: UInt, data: UInt) =\n for (i <- i until nPages by mod)\n when (en(i)) { pages(i) := data }\n\n writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn),\n Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))\n writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn),\n Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))\n pageValid := pageValid | tgtPageReplEn | idxPageReplEn\n }\n\n io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages))\n io.resp.bits.taken := true.B\n io.resp.bits.target := Cat(pagesMasked(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes))\n io.resp.bits.entry := OHToUInt(idxHit)\n io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else 0.U)\n io.resp.bits.mask := Cat((1.U << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, 0.U))-1.U, 1.U)\n io.resp.bits.cfiType := Mux1H(idxHit, cfiType)\n\n // if multiple entries for same PC land in BTB, zap them\n when (PopCountAtLeast(idxHit, 2)) {\n isValid := isValid & ~idxHit\n }\n when (io.flush) {\n isValid := 0.U\n }\n\n if (btbParams.bhtParams.nonEmpty) {\n val bht = new BHT(Annotated.params(this, btbParams.bhtParams.get))\n val isBranch = (idxHit & cfiType.map(_ === CFIType.branch).asUInt).orR\n val res = bht.get(io.req.bits.addr)\n when (io.bht_advance.valid) {\n bht.advanceHistory(io.bht_advance.bits.bht.taken)\n }\n when (io.bht_update.valid) {\n when (io.bht_update.bits.branch) {\n bht.updateTable(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)\n when (io.bht_update.bits.mispredict) {\n bht.updateHistory(io.bht_update.bits.pc, io.bht_update.bits.prediction, io.bht_update.bits.taken)\n }\n }.elsewhen (io.bht_update.bits.mispredict) {\n bht.resetHistory(io.bht_update.bits.prediction)\n }\n }\n when (!res.taken && isBranch) { io.resp.bits.taken := false.B }\n io.resp.bits.bht := res\n }\n\n if (btbParams.nRAS > 0) {\n val ras = new RAS(btbParams.nRAS)\n val doPeek = (idxHit & cfiType.map(_ === CFIType.ret).asUInt).orR\n io.ras_head.valid := !ras.isEmpty\n io.ras_head.bits := ras.peek\n when (!ras.isEmpty && doPeek) {\n io.resp.bits.target := ras.peek\n }\n when (io.ras_update.valid) {\n when (io.ras_update.bits.cfiType === CFIType.call) {\n ras.push(io.ras_update.bits.returnAddr)\n }.elsewhen (io.ras_update.bits.cfiType === CFIType.ret) {\n ras.pop()\n }\n }\n }\n}", + "response": "module table_512x1(\n input [8:0] R0_addr,\n input R0_en,\n input R0_clk,\n output R0_data,\n input [8:0] W0_addr,\n input W0_en,\n input W0_clk,\n input W0_data\n);\n\n reg Memory[0:511];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 1'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module dataArrayWay_2(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [63:0] RW0_wdata,\n output [63:0] RW0_rdata\n);\n\n dataArrayWay_0_ext dataArrayWay_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53(\n input io_invalidExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [12:0] io_in_sExp,\n input [55:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire roundingMode_odd = io_roundingMode == 3'h6;\n wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;\n wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]);\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);\n wire [18:0] _GEN = {roundMask_shift[18:17], roundMask_shift[20:19], roundMask_shift[22:21], roundMask_shift[24:23], roundMask_shift[26:25], roundMask_shift[28:27], roundMask_shift[30:29], roundMask_shift[32:31], roundMask_shift[34:33], roundMask_shift[36]} & 19'h55555;\n wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);\n wire [53:0] _roundMask_T_128 = _roundMask_T_1[11] ? (_roundMask_T_1[10] ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] | _roundMask_T_1[6] ? 51'h0 : ~{roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _GEN[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} & 4'h5, roundMask_shift[22], _GEN[13] | roundMask_shift[23], roundMask_shift[24], roundMask_shift[25], _GEN[10:7] | {roundMask_shift[28:27], roundMask_shift[30:29]} & 4'h5, roundMask_shift[30], _GEN[5] | roundMask_shift[31], roundMask_shift[32], roundMask_shift[33], {_GEN[2:0], 1'h0} | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, roundMask_shift[38], roundMask_shift[39], roundMask_shift[40], roundMask_shift[41], roundMask_shift[42], roundMask_shift[43], roundMask_shift[44], roundMask_shift[45], roundMask_shift[46], roundMask_shift[47], roundMask_shift[48], roundMask_shift[49], roundMask_shift[50], roundMask_shift[51], roundMask_shift[52], roundMask_shift[53], roundMask_shift[54], roundMask_shift[55], roundMask_shift[56], roundMask_shift[57], roundMask_shift[58], roundMask_shift[59], roundMask_shift[60], roundMask_shift[61], roundMask_shift[62], roundMask_shift[63]}), 3'h7} : {51'h0, _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] & _roundMask_T_1[6] ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} : 3'h0}) : 54'h0;\n wire _common_underflow_T_4 = _roundMask_T_128[0] | io_in_sig[55];\n wire [54:0] _GEN_0 = {1'h1, ~(_roundMask_T_128[53:1]), ~_common_underflow_T_4};\n wire [54:0] _GEN_1 = {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1};\n wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_0 & _GEN_1;\n wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_1;\n wire [109:0] _GEN_2 = {_roundPosBit_T, _anyRoundExtra_T};\n wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;\n wire [54:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_2) ? {1'h0, io_in_sig[55:2] | {_roundMask_T_128[53:1], _common_underflow_T_4}} + 55'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 55'h0 ? {_roundMask_T_128[53:1], _common_underflow_T_4, 1'h1} : 55'h0) : {1'h0, io_in_sig[55:2] & {~(_roundMask_T_128[53:1]), ~_common_underflow_T_4}} | (roundingMode_odd & (|_GEN_2) ? _GEN_0 & _GEN_1 : 55'h0);\n wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]};\n wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE;\n wire isNaNOut = io_invalidExc | io_in_isNaN;\n wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero;\n wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2;\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\n wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);\n wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;\n wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp;\n assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 51'h0} : io_in_sig[55] ? roundedSig[52:1] : roundedSig[51:0]) | {52{pegMaxFiniteMagOut}}};\n assign io_exceptionFlags = {io_invalidExc, 1'h0, overflow, commonCase & (common_totalUnderflow | (|_GEN_2) & io_in_sExp[12:11] != 2'h1 & (io_in_sig[55] ? _roundMask_T_128[1] : _common_underflow_T_4) & ~(~(io_in_sig[55] ? _roundMask_T_128[2] : _roundMask_T_128[1]) & (io_in_sig[55] ? roundedSig[54] : roundedSig[53]) & (|_roundPosBit_T) & (_overflow_roundMagUp_T & (io_in_sig[55] ? io_in_sig[2] : io_in_sig[1]) | roundMagUp & (|{io_in_sig[55] & io_in_sig[2], io_in_sig[1:0]})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module BranchKillableQueue_5(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [6:0] io_enq_bits_uop_uopc,\n input [31:0] io_enq_bits_uop_inst,\n input [31:0] io_enq_bits_uop_debug_inst,\n input io_enq_bits_uop_is_rvc,\n input [39:0] io_enq_bits_uop_debug_pc,\n input [2:0] io_enq_bits_uop_iq_type,\n input [9:0] io_enq_bits_uop_fu_code,\n input [3:0] io_enq_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_uop_ctrl_op_fcn,\n input io_enq_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_uop_ctrl_is_load,\n input io_enq_bits_uop_ctrl_is_sta,\n input io_enq_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_uop_iw_state,\n input io_enq_bits_uop_iw_p1_poisoned,\n input io_enq_bits_uop_iw_p2_poisoned,\n input io_enq_bits_uop_is_br,\n input io_enq_bits_uop_is_jalr,\n input io_enq_bits_uop_is_jal,\n input io_enq_bits_uop_is_sfb,\n input [7:0] io_enq_bits_uop_br_mask,\n input [2:0] io_enq_bits_uop_br_tag,\n input [3:0] io_enq_bits_uop_ftq_idx,\n input io_enq_bits_uop_edge_inst,\n input [5:0] io_enq_bits_uop_pc_lob,\n input io_enq_bits_uop_taken,\n input [19:0] io_enq_bits_uop_imm_packed,\n input [11:0] io_enq_bits_uop_csr_addr,\n input [4:0] io_enq_bits_uop_rob_idx,\n input [2:0] io_enq_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_uop_stq_idx,\n input [1:0] io_enq_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_uop_pdst,\n input [5:0] io_enq_bits_uop_prs1,\n input [5:0] io_enq_bits_uop_prs2,\n input [5:0] io_enq_bits_uop_prs3,\n input [3:0] io_enq_bits_uop_ppred,\n input io_enq_bits_uop_prs1_busy,\n input io_enq_bits_uop_prs2_busy,\n input io_enq_bits_uop_prs3_busy,\n input io_enq_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_uop_stale_pdst,\n input io_enq_bits_uop_exception,\n input [63:0] io_enq_bits_uop_exc_cause,\n input io_enq_bits_uop_bypassable,\n input [4:0] io_enq_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_uop_mem_size,\n input io_enq_bits_uop_mem_signed,\n input io_enq_bits_uop_is_fence,\n input io_enq_bits_uop_is_fencei,\n input io_enq_bits_uop_is_amo,\n input io_enq_bits_uop_uses_ldq,\n input io_enq_bits_uop_uses_stq,\n input io_enq_bits_uop_is_sys_pc2epc,\n input io_enq_bits_uop_is_unique,\n input io_enq_bits_uop_flush_on_commit,\n input io_enq_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_uop_ldst,\n input [5:0] io_enq_bits_uop_lrs1,\n input [5:0] io_enq_bits_uop_lrs2,\n input [5:0] io_enq_bits_uop_lrs3,\n input io_enq_bits_uop_ldst_val,\n input [1:0] io_enq_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_uop_lrs2_rtype,\n input io_enq_bits_uop_frs3_en,\n input io_enq_bits_uop_fp_val,\n input io_enq_bits_uop_fp_single,\n input io_enq_bits_uop_xcpt_pf_if,\n input io_enq_bits_uop_xcpt_ae_if,\n input io_enq_bits_uop_xcpt_ma_if,\n input io_enq_bits_uop_bp_debug_if,\n input io_enq_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_uop_debug_tsrc,\n input [64:0] io_enq_bits_data,\n input io_deq_ready,\n output io_deq_valid,\n output [6:0] io_deq_bits_uop_uopc,\n output [7:0] io_deq_bits_uop_br_mask,\n output [4:0] io_deq_bits_uop_rob_idx,\n output [2:0] io_deq_bits_uop_stq_idx,\n output [5:0] io_deq_bits_uop_pdst,\n output io_deq_bits_uop_is_amo,\n output io_deq_bits_uop_uses_stq,\n output [1:0] io_deq_bits_uop_dst_rtype,\n output io_deq_bits_uop_fp_val,\n output [64:0] io_deq_bits_data,\n output io_deq_bits_predicated,\n output io_deq_bits_fflags_valid,\n output [4:0] io_deq_bits_fflags_bits_uop_rob_idx,\n output [4:0] io_deq_bits_fflags_bits_flags,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_flush,\n output io_empty\n);\n\n wire [76:0] _ram_ext_R0_data;\n reg valids_0;\n reg valids_1;\n reg valids_2;\n reg [6:0] uops_0_uopc;\n reg [7:0] uops_0_br_mask;\n reg [4:0] uops_0_rob_idx;\n reg [2:0] uops_0_stq_idx;\n reg [5:0] uops_0_pdst;\n reg uops_0_is_amo;\n reg uops_0_uses_stq;\n reg [1:0] uops_0_dst_rtype;\n reg uops_0_fp_val;\n reg [6:0] uops_1_uopc;\n reg [7:0] uops_1_br_mask;\n reg [4:0] uops_1_rob_idx;\n reg [2:0] uops_1_stq_idx;\n reg [5:0] uops_1_pdst;\n reg uops_1_is_amo;\n reg uops_1_uses_stq;\n reg [1:0] uops_1_dst_rtype;\n reg uops_1_fp_val;\n reg [6:0] uops_2_uopc;\n reg [7:0] uops_2_br_mask;\n reg [4:0] uops_2_rob_idx;\n reg [2:0] uops_2_stq_idx;\n reg [5:0] uops_2_pdst;\n reg uops_2_is_amo;\n reg uops_2_uses_stq;\n reg [1:0] uops_2_dst_rtype;\n reg uops_2_fp_val;\n reg [1:0] enq_ptr_value;\n reg [1:0] deq_ptr_value;\n reg maybe_full;\n wire ptr_match = enq_ptr_value == deq_ptr_value;\n wire io_empty_0 = ptr_match & ~maybe_full;\n wire full = ptr_match & maybe_full;\n wire [3:0] _GEN = {{valids_0}, {valids_2}, {valids_1}, {valids_0}};\n wire _GEN_0 = _GEN[deq_ptr_value];\n wire [3:0][6:0] _GEN_1 = {{uops_0_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};\n wire [3:0][7:0] _GEN_2 = {{uops_0_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};\n wire [7:0] out_uop_br_mask = _GEN_2[deq_ptr_value];\n wire [3:0][4:0] _GEN_3 = {{uops_0_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};\n wire [3:0][2:0] _GEN_4 = {{uops_0_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};\n wire [3:0][5:0] _GEN_5 = {{uops_0_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};\n wire [3:0] _GEN_6 = {{uops_0_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};\n wire [3:0] _GEN_7 = {{uops_0_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};\n wire [3:0][1:0] _GEN_8 = {{uops_0_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};\n wire [3:0] _GEN_9 = {{uops_0_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};\n wire do_deq = ~io_empty_0 & (io_deq_ready | ~_GEN_0) & ~io_empty_0;\n wire do_enq = ~(io_empty_0 & io_deq_ready) & ~full & io_enq_valid;\n wire _GEN_10 = enq_ptr_value == 2'h0;\n wire _GEN_11 = do_enq & _GEN_10;\n wire _GEN_12 = enq_ptr_value == 2'h1;\n wire _GEN_13 = do_enq & _GEN_12;\n wire _GEN_14 = enq_ptr_value == 2'h2;\n wire _GEN_15 = do_enq & _GEN_14;\n wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n valids_0 <= 1'h0;\n valids_1 <= 1'h0;\n valids_2 <= 1'h0;\n enq_ptr_value <= 2'h0;\n deq_ptr_value <= 2'h0;\n maybe_full <= 1'h0;\n end\n else begin\n valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_11 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~io_flush);\n valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_13 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~io_flush);\n valids_2 <= ~(do_deq & deq_ptr_value == 2'h2) & (_GEN_15 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~io_flush);\n if (do_enq)\n enq_ptr_value <= enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1;\n if (do_deq)\n deq_ptr_value <= deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1;\n if (~(do_enq == do_deq))\n maybe_full <= do_enq;\n end\n if (_GEN_11) begin\n uops_0_uopc <= io_enq_bits_uop_uopc;\n uops_0_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_0_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_0_pdst <= io_enq_bits_uop_pdst;\n uops_0_is_amo <= io_enq_bits_uop_is_amo;\n uops_0_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_0_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_0_br_mask <= do_enq & _GEN_10 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;\n if (_GEN_13) begin\n uops_1_uopc <= io_enq_bits_uop_uopc;\n uops_1_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_1_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_1_pdst <= io_enq_bits_uop_pdst;\n uops_1_is_amo <= io_enq_bits_uop_is_amo;\n uops_1_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_1_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_1_br_mask <= do_enq & _GEN_12 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;\n if (_GEN_15) begin\n uops_2_uopc <= io_enq_bits_uop_uopc;\n uops_2_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_2_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_2_pdst <= io_enq_bits_uop_pdst;\n uops_2_is_amo <= io_enq_bits_uop_is_amo;\n uops_2_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_2_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_2_br_mask <= do_enq & _GEN_14 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;\n end\n ram_3x77 ram_ext (\n .R0_addr (deq_ptr_value),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_ram_ext_R0_data),\n .W0_addr (enq_ptr_value),\n .W0_en (do_enq),\n .W0_clk (clock),\n .W0_data ({12'h0, io_enq_bits_data})\n );\n assign io_enq_ready = ~full;\n assign io_deq_valid = io_empty_0 ? io_enq_valid : ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~io_flush;\n assign io_deq_bits_uop_uopc = io_empty_0 ? io_enq_bits_uop_uopc : _GEN_1[deq_ptr_value];\n assign io_deq_bits_uop_br_mask = io_empty_0 ? io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : out_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_deq_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_uop_rob_idx : _GEN_3[deq_ptr_value];\n assign io_deq_bits_uop_stq_idx = io_empty_0 ? io_enq_bits_uop_stq_idx : _GEN_4[deq_ptr_value];\n assign io_deq_bits_uop_pdst = io_empty_0 ? io_enq_bits_uop_pdst : _GEN_5[deq_ptr_value];\n assign io_deq_bits_uop_is_amo = io_empty_0 ? io_enq_bits_uop_is_amo : _GEN_6[deq_ptr_value];\n assign io_deq_bits_uop_uses_stq = io_empty_0 ? io_enq_bits_uop_uses_stq : _GEN_7[deq_ptr_value];\n assign io_deq_bits_uop_dst_rtype = io_empty_0 ? io_enq_bits_uop_dst_rtype : _GEN_8[deq_ptr_value];\n assign io_deq_bits_uop_fp_val = io_empty_0 ? io_enq_bits_uop_fp_val : _GEN_9[deq_ptr_value];\n assign io_deq_bits_data = io_empty_0 ? io_enq_bits_data : _ram_ext_R0_data[64:0];\n assign io_deq_bits_predicated = ~io_empty_0 & _ram_ext_R0_data[65];\n assign io_deq_bits_fflags_valid = ~io_empty_0 & _ram_ext_R0_data[66];\n assign io_deq_bits_fflags_bits_uop_rob_idx = io_empty_0 ? 5'h0 : _ram_ext_R0_data[71:67];\n assign io_deq_bits_fflags_bits_flags = io_empty_0 ? 5'h0 : _ram_ext_R0_data[76:72];\n assign io_empty = io_empty_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", + "response": "module ClockCrossingReg_w43(\n input clock,\n input [42:0] io_d,\n output [42:0] io_q,\n input io_en\n);\n\n reg [42:0] cdc_reg;\n always @(posedge clock) begin\n if (io_en)\n cdc_reg <= io_d;\n end\n assign io_q = cdc_reg;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat,log2Up}\nimport org.chipsalliance.cde.config.Parameters\n\nclass HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module\n{\n val io = IO(new Bundle {\n val requestor = Flipped(Vec(n, new HellaCacheIO))\n val mem = new HellaCacheIO\n })\n\n if (n == 1) {\n io.mem <> io.requestor.head\n } else {\n val s1_id = Reg(UInt())\n val s2_id = RegNext(s1_id)\n\n io.mem.keep_clock_enabled := io.requestor.map(_.keep_clock_enabled).reduce(_||_)\n\n io.mem.req.valid := io.requestor.map(_.req.valid).reduce(_||_)\n io.requestor(0).req.ready := io.mem.req.ready\n for (i <- 1 until n)\n io.requestor(i).req.ready := io.requestor(i-1).req.ready && !io.requestor(i-1).req.valid\n\n for (i <- n-1 to 0 by -1) {\n val req = io.requestor(i).req\n def connect_s0() = {\n io.mem.req.bits := req.bits\n io.mem.req.bits.tag := Cat(req.bits.tag, i.U(log2Up(n).W))\n s1_id := i.U\n }\n def connect_s1() = {\n io.mem.s1_kill := io.requestor(i).s1_kill\n io.mem.s1_data := io.requestor(i).s1_data\n }\n def connect_s2() = {\n io.mem.s2_kill := io.requestor(i).s2_kill\n }\n\n if (i == n-1) {\n connect_s0()\n connect_s1()\n connect_s2()\n } else {\n when (req.valid) { connect_s0() }\n when (s1_id === i.U) { connect_s1() }\n when (s2_id === i.U) { connect_s2() }\n }\n }\n\n io.mem.uncached_resp.foreach(_.ready := false.B)\n\n for (i <- 0 until n) {\n val resp = io.requestor(i).resp\n val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === i.U\n resp.valid := io.mem.resp.valid && tag_hit\n io.requestor(i).s2_xcpt := io.mem.s2_xcpt\n io.requestor(i).s2_gpa := io.mem.s2_gpa\n io.requestor(i).s2_gpa_is_pte := io.mem.s2_gpa_is_pte\n io.requestor(i).ordered := io.mem.ordered\n io.requestor(i).store_pending := io.mem.store_pending\n io.requestor(i).perf := io.mem.perf\n io.requestor(i).s2_nack := io.mem.s2_nack && s2_id === i.U\n io.requestor(i).s2_nack_cause_raw := io.mem.s2_nack_cause_raw\n io.requestor(i).s2_uncached := io.mem.s2_uncached\n io.requestor(i).s2_paddr := io.mem.s2_paddr\n io.requestor(i).clock_enabled := io.mem.clock_enabled\n resp.bits := io.mem.resp.bits\n resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n)\n\n io.requestor(i).replay_next := io.mem.replay_next\n\n io.requestor(i).uncached_resp.map { uncached_resp =>\n val uncached_tag_hit = io.mem.uncached_resp.get.bits.tag(log2Up(n)-1,0) === i.U\n uncached_resp.valid := io.mem.uncached_resp.get.valid && uncached_tag_hit\n when (uncached_resp.ready && uncached_tag_hit) {\n io.mem.uncached_resp.get.ready := true.B\n }\n uncached_resp.bits := io.mem.uncached_resp.get.bits\n uncached_resp.bits.tag := io.mem.uncached_resp.get.bits.tag >> log2Up(n)\n }\n }\n }\n}", + "response": "module HellaCacheArbiter(\n output io_requestor_0_req_ready,\n input io_requestor_0_req_valid,\n input [39:0] io_requestor_0_req_bits_addr,\n input io_requestor_0_s1_kill,\n output io_requestor_0_s2_nack,\n output io_requestor_0_resp_valid,\n output [63:0] io_requestor_0_resp_bits_data,\n output io_requestor_0_s2_xcpt_ae_ld,\n input io_mem_req_ready,\n output io_mem_req_valid,\n output [39:0] io_mem_req_bits_addr,\n output io_mem_s1_kill,\n input io_mem_s2_nack,\n input io_mem_resp_valid,\n input [63:0] io_mem_resp_bits_data,\n input io_mem_s2_xcpt_ae_ld\n);\n\n assign io_requestor_0_req_ready = io_mem_req_ready;\n assign io_requestor_0_s2_nack = io_mem_s2_nack;\n assign io_requestor_0_resp_valid = io_mem_resp_valid;\n assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data;\n assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld;\n assign io_mem_req_valid = io_requestor_0_req_valid;\n assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr;\n assign io_mem_s1_kill = io_requestor_0_s1_kill;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_2(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [47:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [47:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_0_ext table_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename Map Table\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass MapReq(val lregSz: Int) extends Bundle\n{\n val lrs1 = UInt(lregSz.W)\n val lrs2 = UInt(lregSz.W)\n val lrs3 = UInt(lregSz.W)\n val ldst = UInt(lregSz.W)\n}\n\nclass MapResp(val pregSz: Int) extends Bundle\n{\n val prs1 = UInt(pregSz.W)\n val prs2 = UInt(pregSz.W)\n val prs3 = UInt(pregSz.W)\n val stale_pdst = UInt(pregSz.W)\n}\n\nclass RemapReq(val lregSz: Int, val pregSz: Int) extends Bundle\n{\n val ldst = UInt(lregSz.W)\n val pdst = UInt(pregSz.W)\n val valid = Bool()\n}\n\nclass RenameMapTable(\n val plWidth: Int,\n val numLregs: Int,\n val numPregs: Int,\n val bypass: Boolean,\n val float: Boolean)\n (implicit p: Parameters) extends BoomModule\n{\n val pregSz = log2Ceil(numPregs)\n\n val io = IO(new BoomBundle()(p) {\n // Logical sources -> physical sources.\n val map_reqs = Input(Vec(plWidth, new MapReq(lregSz)))\n val map_resps = Output(Vec(plWidth, new MapResp(pregSz)))\n\n // Remapping an ldst to a newly allocated pdst?\n val remap_reqs = Input(Vec(plWidth, new RemapReq(lregSz, pregSz)))\n\n // Dispatching branches: need to take snapshots of table state.\n val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Signals for restoring state following misspeculation.\n val brupdate = Input(new BrUpdateInfo)\n val rollback = Input(Bool())\n })\n\n // The map table register array and its branch snapshots.\n val map_table = RegInit(VecInit(Seq.fill(numLregs){0.U(pregSz.W)}))\n val br_snapshots = Reg(Vec(maxBrCount, Vec(numLregs, UInt(pregSz.W))))\n\n // The intermediate states of the map table following modification by each pipeline slot.\n val remap_table = Wire(Vec(plWidth+1, Vec(numLregs, UInt(pregSz.W))))\n\n // Uops requesting changes to the map table.\n val remap_pdsts = io.remap_reqs map (_.pdst)\n val remap_ldsts_oh = io.remap_reqs map (req => UIntToOH(req.ldst) & Fill(numLregs, req.valid.asUInt))\n\n // Figure out the new mappings seen by each pipeline slot.\n for (i <- 0 until numLregs) {\n if (i == 0 && !float) {\n for (j <- 0 until plWidth+1) {\n remap_table(j)(i) := 0.U\n }\n } else {\n val remapped_row = (remap_ldsts_oh.map(ldst => ldst(i)) zip remap_pdsts)\n .scanLeft(map_table(i)) {case (pdst, (ldst, new_pdst)) => Mux(ldst, new_pdst, pdst)}\n\n for (j <- 0 until plWidth+1) {\n remap_table(j)(i) := remapped_row(j)\n }\n }\n }\n\n // Create snapshots of new mappings.\n for (i <- 0 until plWidth) {\n when (io.ren_br_tags(i).valid) {\n br_snapshots(io.ren_br_tags(i).bits) := remap_table(i+1)\n }\n }\n\n when (io.brupdate.b2.mispredict) {\n // Restore the map table to a branch snapshot.\n map_table := br_snapshots(io.brupdate.b2.uop.br_tag)\n } .otherwise {\n // Update mappings.\n map_table := remap_table(plWidth)\n }\n\n // Read out mappings.\n for (i <- 0 until plWidth) {\n io.map_resps(i).prs1 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs1)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs1, io.remap_reqs(k).pdst, p))\n io.map_resps(i).prs2 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs2)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs2, io.remap_reqs(k).pdst, p))\n io.map_resps(i).prs3 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs3)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs3, io.remap_reqs(k).pdst, p))\n io.map_resps(i).stale_pdst := (0 until i).foldLeft(map_table(io.map_reqs(i).ldst)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).ldst, io.remap_reqs(k).pdst, p))\n\n if (!float) io.map_resps(i).prs3 := DontCare\n }\n\n // Don't flag the creation of duplicate 'p0' mappings during rollback.\n // These cases may occur soon after reset, as all maptable entries are initialized to 'p0'.\n io.remap_reqs map (req => (req.pdst, req.valid)) foreach {case (p,r) =>\n assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, \"[maptable] Trying to write a duplicate mapping.\")}\n}", + "response": "module RenameMapTable(\n input clock,\n input reset,\n input [5:0] io_map_reqs_0_lrs1,\n input [5:0] io_map_reqs_0_lrs2,\n input [5:0] io_map_reqs_0_ldst,\n output [5:0] io_map_resps_0_prs1,\n output [5:0] io_map_resps_0_prs2,\n output [5:0] io_map_resps_0_stale_pdst,\n input [5:0] io_remap_reqs_0_ldst,\n input [5:0] io_remap_reqs_0_pdst,\n input io_remap_reqs_0_valid,\n input io_ren_br_tags_0_valid,\n input [2:0] io_ren_br_tags_0_bits,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_rollback\n);\n\n reg [5:0] map_table_1;\n reg [5:0] map_table_2;\n reg [5:0] map_table_3;\n reg [5:0] map_table_4;\n reg [5:0] map_table_5;\n reg [5:0] map_table_6;\n reg [5:0] map_table_7;\n reg [5:0] map_table_8;\n reg [5:0] map_table_9;\n reg [5:0] map_table_10;\n reg [5:0] map_table_11;\n reg [5:0] map_table_12;\n reg [5:0] map_table_13;\n reg [5:0] map_table_14;\n reg [5:0] map_table_15;\n reg [5:0] map_table_16;\n reg [5:0] map_table_17;\n reg [5:0] map_table_18;\n reg [5:0] map_table_19;\n reg [5:0] map_table_20;\n reg [5:0] map_table_21;\n reg [5:0] map_table_22;\n reg [5:0] map_table_23;\n reg [5:0] map_table_24;\n reg [5:0] map_table_25;\n reg [5:0] map_table_26;\n reg [5:0] map_table_27;\n reg [5:0] map_table_28;\n reg [5:0] map_table_29;\n reg [5:0] map_table_30;\n reg [5:0] map_table_31;\n reg [5:0] br_snapshots_0_1;\n reg [5:0] br_snapshots_0_2;\n reg [5:0] br_snapshots_0_3;\n reg [5:0] br_snapshots_0_4;\n reg [5:0] br_snapshots_0_5;\n reg [5:0] br_snapshots_0_6;\n reg [5:0] br_snapshots_0_7;\n reg [5:0] br_snapshots_0_8;\n reg [5:0] br_snapshots_0_9;\n reg [5:0] br_snapshots_0_10;\n reg [5:0] br_snapshots_0_11;\n reg [5:0] br_snapshots_0_12;\n reg [5:0] br_snapshots_0_13;\n reg [5:0] br_snapshots_0_14;\n reg [5:0] br_snapshots_0_15;\n reg [5:0] br_snapshots_0_16;\n reg [5:0] br_snapshots_0_17;\n reg [5:0] br_snapshots_0_18;\n reg [5:0] br_snapshots_0_19;\n reg [5:0] br_snapshots_0_20;\n reg [5:0] br_snapshots_0_21;\n reg [5:0] br_snapshots_0_22;\n reg [5:0] br_snapshots_0_23;\n reg [5:0] br_snapshots_0_24;\n reg [5:0] br_snapshots_0_25;\n reg [5:0] br_snapshots_0_26;\n reg [5:0] br_snapshots_0_27;\n reg [5:0] br_snapshots_0_28;\n reg [5:0] br_snapshots_0_29;\n reg [5:0] br_snapshots_0_30;\n reg [5:0] br_snapshots_0_31;\n reg [5:0] br_snapshots_1_1;\n reg [5:0] br_snapshots_1_2;\n reg [5:0] br_snapshots_1_3;\n reg [5:0] br_snapshots_1_4;\n reg [5:0] br_snapshots_1_5;\n reg [5:0] br_snapshots_1_6;\n reg [5:0] br_snapshots_1_7;\n reg [5:0] br_snapshots_1_8;\n reg [5:0] br_snapshots_1_9;\n reg [5:0] br_snapshots_1_10;\n reg [5:0] br_snapshots_1_11;\n reg [5:0] br_snapshots_1_12;\n reg [5:0] br_snapshots_1_13;\n reg [5:0] br_snapshots_1_14;\n reg [5:0] br_snapshots_1_15;\n reg [5:0] br_snapshots_1_16;\n reg [5:0] br_snapshots_1_17;\n reg [5:0] br_snapshots_1_18;\n reg [5:0] br_snapshots_1_19;\n reg [5:0] br_snapshots_1_20;\n reg [5:0] br_snapshots_1_21;\n reg [5:0] br_snapshots_1_22;\n reg [5:0] br_snapshots_1_23;\n reg [5:0] br_snapshots_1_24;\n reg [5:0] br_snapshots_1_25;\n reg [5:0] br_snapshots_1_26;\n reg [5:0] br_snapshots_1_27;\n reg [5:0] br_snapshots_1_28;\n reg [5:0] br_snapshots_1_29;\n reg [5:0] br_snapshots_1_30;\n reg [5:0] br_snapshots_1_31;\n reg [5:0] br_snapshots_2_1;\n reg [5:0] br_snapshots_2_2;\n reg [5:0] br_snapshots_2_3;\n reg [5:0] br_snapshots_2_4;\n reg [5:0] br_snapshots_2_5;\n reg [5:0] br_snapshots_2_6;\n reg [5:0] br_snapshots_2_7;\n reg [5:0] br_snapshots_2_8;\n reg [5:0] br_snapshots_2_9;\n reg [5:0] br_snapshots_2_10;\n reg [5:0] br_snapshots_2_11;\n reg [5:0] br_snapshots_2_12;\n reg [5:0] br_snapshots_2_13;\n reg [5:0] br_snapshots_2_14;\n reg [5:0] br_snapshots_2_15;\n reg [5:0] br_snapshots_2_16;\n reg [5:0] br_snapshots_2_17;\n reg [5:0] br_snapshots_2_18;\n reg [5:0] br_snapshots_2_19;\n reg [5:0] br_snapshots_2_20;\n reg [5:0] br_snapshots_2_21;\n reg [5:0] br_snapshots_2_22;\n reg [5:0] br_snapshots_2_23;\n reg [5:0] br_snapshots_2_24;\n reg [5:0] br_snapshots_2_25;\n reg [5:0] br_snapshots_2_26;\n reg [5:0] br_snapshots_2_27;\n reg [5:0] br_snapshots_2_28;\n reg [5:0] br_snapshots_2_29;\n reg [5:0] br_snapshots_2_30;\n reg [5:0] br_snapshots_2_31;\n reg [5:0] br_snapshots_3_1;\n reg [5:0] br_snapshots_3_2;\n reg [5:0] br_snapshots_3_3;\n reg [5:0] br_snapshots_3_4;\n reg [5:0] br_snapshots_3_5;\n reg [5:0] br_snapshots_3_6;\n reg [5:0] br_snapshots_3_7;\n reg [5:0] br_snapshots_3_8;\n reg [5:0] br_snapshots_3_9;\n reg [5:0] br_snapshots_3_10;\n reg [5:0] br_snapshots_3_11;\n reg [5:0] br_snapshots_3_12;\n reg [5:0] br_snapshots_3_13;\n reg [5:0] br_snapshots_3_14;\n reg [5:0] br_snapshots_3_15;\n reg [5:0] br_snapshots_3_16;\n reg [5:0] br_snapshots_3_17;\n reg [5:0] br_snapshots_3_18;\n reg [5:0] br_snapshots_3_19;\n reg [5:0] br_snapshots_3_20;\n reg [5:0] br_snapshots_3_21;\n reg [5:0] br_snapshots_3_22;\n reg [5:0] br_snapshots_3_23;\n reg [5:0] br_snapshots_3_24;\n reg [5:0] br_snapshots_3_25;\n reg [5:0] br_snapshots_3_26;\n reg [5:0] br_snapshots_3_27;\n reg [5:0] br_snapshots_3_28;\n reg [5:0] br_snapshots_3_29;\n reg [5:0] br_snapshots_3_30;\n reg [5:0] br_snapshots_3_31;\n reg [5:0] br_snapshots_4_1;\n reg [5:0] br_snapshots_4_2;\n reg [5:0] br_snapshots_4_3;\n reg [5:0] br_snapshots_4_4;\n reg [5:0] br_snapshots_4_5;\n reg [5:0] br_snapshots_4_6;\n reg [5:0] br_snapshots_4_7;\n reg [5:0] br_snapshots_4_8;\n reg [5:0] br_snapshots_4_9;\n reg [5:0] br_snapshots_4_10;\n reg [5:0] br_snapshots_4_11;\n reg [5:0] br_snapshots_4_12;\n reg [5:0] br_snapshots_4_13;\n reg [5:0] br_snapshots_4_14;\n reg [5:0] br_snapshots_4_15;\n reg [5:0] br_snapshots_4_16;\n reg [5:0] br_snapshots_4_17;\n reg [5:0] br_snapshots_4_18;\n reg [5:0] br_snapshots_4_19;\n reg [5:0] br_snapshots_4_20;\n reg [5:0] br_snapshots_4_21;\n reg [5:0] br_snapshots_4_22;\n reg [5:0] br_snapshots_4_23;\n reg [5:0] br_snapshots_4_24;\n reg [5:0] br_snapshots_4_25;\n reg [5:0] br_snapshots_4_26;\n reg [5:0] br_snapshots_4_27;\n reg [5:0] br_snapshots_4_28;\n reg [5:0] br_snapshots_4_29;\n reg [5:0] br_snapshots_4_30;\n reg [5:0] br_snapshots_4_31;\n reg [5:0] br_snapshots_5_1;\n reg [5:0] br_snapshots_5_2;\n reg [5:0] br_snapshots_5_3;\n reg [5:0] br_snapshots_5_4;\n reg [5:0] br_snapshots_5_5;\n reg [5:0] br_snapshots_5_6;\n reg [5:0] br_snapshots_5_7;\n reg [5:0] br_snapshots_5_8;\n reg [5:0] br_snapshots_5_9;\n reg [5:0] br_snapshots_5_10;\n reg [5:0] br_snapshots_5_11;\n reg [5:0] br_snapshots_5_12;\n reg [5:0] br_snapshots_5_13;\n reg [5:0] br_snapshots_5_14;\n reg [5:0] br_snapshots_5_15;\n reg [5:0] br_snapshots_5_16;\n reg [5:0] br_snapshots_5_17;\n reg [5:0] br_snapshots_5_18;\n reg [5:0] br_snapshots_5_19;\n reg [5:0] br_snapshots_5_20;\n reg [5:0] br_snapshots_5_21;\n reg [5:0] br_snapshots_5_22;\n reg [5:0] br_snapshots_5_23;\n reg [5:0] br_snapshots_5_24;\n reg [5:0] br_snapshots_5_25;\n reg [5:0] br_snapshots_5_26;\n reg [5:0] br_snapshots_5_27;\n reg [5:0] br_snapshots_5_28;\n reg [5:0] br_snapshots_5_29;\n reg [5:0] br_snapshots_5_30;\n reg [5:0] br_snapshots_5_31;\n reg [5:0] br_snapshots_6_1;\n reg [5:0] br_snapshots_6_2;\n reg [5:0] br_snapshots_6_3;\n reg [5:0] br_snapshots_6_4;\n reg [5:0] br_snapshots_6_5;\n reg [5:0] br_snapshots_6_6;\n reg [5:0] br_snapshots_6_7;\n reg [5:0] br_snapshots_6_8;\n reg [5:0] br_snapshots_6_9;\n reg [5:0] br_snapshots_6_10;\n reg [5:0] br_snapshots_6_11;\n reg [5:0] br_snapshots_6_12;\n reg [5:0] br_snapshots_6_13;\n reg [5:0] br_snapshots_6_14;\n reg [5:0] br_snapshots_6_15;\n reg [5:0] br_snapshots_6_16;\n reg [5:0] br_snapshots_6_17;\n reg [5:0] br_snapshots_6_18;\n reg [5:0] br_snapshots_6_19;\n reg [5:0] br_snapshots_6_20;\n reg [5:0] br_snapshots_6_21;\n reg [5:0] br_snapshots_6_22;\n reg [5:0] br_snapshots_6_23;\n reg [5:0] br_snapshots_6_24;\n reg [5:0] br_snapshots_6_25;\n reg [5:0] br_snapshots_6_26;\n reg [5:0] br_snapshots_6_27;\n reg [5:0] br_snapshots_6_28;\n reg [5:0] br_snapshots_6_29;\n reg [5:0] br_snapshots_6_30;\n reg [5:0] br_snapshots_6_31;\n reg [5:0] br_snapshots_7_1;\n reg [5:0] br_snapshots_7_2;\n reg [5:0] br_snapshots_7_3;\n reg [5:0] br_snapshots_7_4;\n reg [5:0] br_snapshots_7_5;\n reg [5:0] br_snapshots_7_6;\n reg [5:0] br_snapshots_7_7;\n reg [5:0] br_snapshots_7_8;\n reg [5:0] br_snapshots_7_9;\n reg [5:0] br_snapshots_7_10;\n reg [5:0] br_snapshots_7_11;\n reg [5:0] br_snapshots_7_12;\n reg [5:0] br_snapshots_7_13;\n reg [5:0] br_snapshots_7_14;\n reg [5:0] br_snapshots_7_15;\n reg [5:0] br_snapshots_7_16;\n reg [5:0] br_snapshots_7_17;\n reg [5:0] br_snapshots_7_18;\n reg [5:0] br_snapshots_7_19;\n reg [5:0] br_snapshots_7_20;\n reg [5:0] br_snapshots_7_21;\n reg [5:0] br_snapshots_7_22;\n reg [5:0] br_snapshots_7_23;\n reg [5:0] br_snapshots_7_24;\n reg [5:0] br_snapshots_7_25;\n reg [5:0] br_snapshots_7_26;\n reg [5:0] br_snapshots_7_27;\n reg [5:0] br_snapshots_7_28;\n reg [5:0] br_snapshots_7_29;\n reg [5:0] br_snapshots_7_30;\n reg [5:0] br_snapshots_7_31;\n wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {6'h0}};\n wire [7:0][5:0] _GEN_1 = {{br_snapshots_7_1}, {br_snapshots_6_1}, {br_snapshots_5_1}, {br_snapshots_4_1}, {br_snapshots_3_1}, {br_snapshots_2_1}, {br_snapshots_1_1}, {br_snapshots_0_1}};\n wire [7:0][5:0] _GEN_2 = {{br_snapshots_7_2}, {br_snapshots_6_2}, {br_snapshots_5_2}, {br_snapshots_4_2}, {br_snapshots_3_2}, {br_snapshots_2_2}, {br_snapshots_1_2}, {br_snapshots_0_2}};\n wire [7:0][5:0] _GEN_3 = {{br_snapshots_7_3}, {br_snapshots_6_3}, {br_snapshots_5_3}, {br_snapshots_4_3}, {br_snapshots_3_3}, {br_snapshots_2_3}, {br_snapshots_1_3}, {br_snapshots_0_3}};\n wire [7:0][5:0] _GEN_4 = {{br_snapshots_7_4}, {br_snapshots_6_4}, {br_snapshots_5_4}, {br_snapshots_4_4}, {br_snapshots_3_4}, {br_snapshots_2_4}, {br_snapshots_1_4}, {br_snapshots_0_4}};\n wire [7:0][5:0] _GEN_5 = {{br_snapshots_7_5}, {br_snapshots_6_5}, {br_snapshots_5_5}, {br_snapshots_4_5}, {br_snapshots_3_5}, {br_snapshots_2_5}, {br_snapshots_1_5}, {br_snapshots_0_5}};\n wire [7:0][5:0] _GEN_6 = {{br_snapshots_7_6}, {br_snapshots_6_6}, {br_snapshots_5_6}, {br_snapshots_4_6}, {br_snapshots_3_6}, {br_snapshots_2_6}, {br_snapshots_1_6}, {br_snapshots_0_6}};\n wire [7:0][5:0] _GEN_7 = {{br_snapshots_7_7}, {br_snapshots_6_7}, {br_snapshots_5_7}, {br_snapshots_4_7}, {br_snapshots_3_7}, {br_snapshots_2_7}, {br_snapshots_1_7}, {br_snapshots_0_7}};\n wire [7:0][5:0] _GEN_8 = {{br_snapshots_7_8}, {br_snapshots_6_8}, {br_snapshots_5_8}, {br_snapshots_4_8}, {br_snapshots_3_8}, {br_snapshots_2_8}, {br_snapshots_1_8}, {br_snapshots_0_8}};\n wire [7:0][5:0] _GEN_9 = {{br_snapshots_7_9}, {br_snapshots_6_9}, {br_snapshots_5_9}, {br_snapshots_4_9}, {br_snapshots_3_9}, {br_snapshots_2_9}, {br_snapshots_1_9}, {br_snapshots_0_9}};\n wire [7:0][5:0] _GEN_10 = {{br_snapshots_7_10}, {br_snapshots_6_10}, {br_snapshots_5_10}, {br_snapshots_4_10}, {br_snapshots_3_10}, {br_snapshots_2_10}, {br_snapshots_1_10}, {br_snapshots_0_10}};\n wire [7:0][5:0] _GEN_11 = {{br_snapshots_7_11}, {br_snapshots_6_11}, {br_snapshots_5_11}, {br_snapshots_4_11}, {br_snapshots_3_11}, {br_snapshots_2_11}, {br_snapshots_1_11}, {br_snapshots_0_11}};\n wire [7:0][5:0] _GEN_12 = {{br_snapshots_7_12}, {br_snapshots_6_12}, {br_snapshots_5_12}, {br_snapshots_4_12}, {br_snapshots_3_12}, {br_snapshots_2_12}, {br_snapshots_1_12}, {br_snapshots_0_12}};\n wire [7:0][5:0] _GEN_13 = {{br_snapshots_7_13}, {br_snapshots_6_13}, {br_snapshots_5_13}, {br_snapshots_4_13}, {br_snapshots_3_13}, {br_snapshots_2_13}, {br_snapshots_1_13}, {br_snapshots_0_13}};\n wire [7:0][5:0] _GEN_14 = {{br_snapshots_7_14}, {br_snapshots_6_14}, {br_snapshots_5_14}, {br_snapshots_4_14}, {br_snapshots_3_14}, {br_snapshots_2_14}, {br_snapshots_1_14}, {br_snapshots_0_14}};\n wire [7:0][5:0] _GEN_15 = {{br_snapshots_7_15}, {br_snapshots_6_15}, {br_snapshots_5_15}, {br_snapshots_4_15}, {br_snapshots_3_15}, {br_snapshots_2_15}, {br_snapshots_1_15}, {br_snapshots_0_15}};\n wire [7:0][5:0] _GEN_16 = {{br_snapshots_7_16}, {br_snapshots_6_16}, {br_snapshots_5_16}, {br_snapshots_4_16}, {br_snapshots_3_16}, {br_snapshots_2_16}, {br_snapshots_1_16}, {br_snapshots_0_16}};\n wire [7:0][5:0] _GEN_17 = {{br_snapshots_7_17}, {br_snapshots_6_17}, {br_snapshots_5_17}, {br_snapshots_4_17}, {br_snapshots_3_17}, {br_snapshots_2_17}, {br_snapshots_1_17}, {br_snapshots_0_17}};\n wire [7:0][5:0] _GEN_18 = {{br_snapshots_7_18}, {br_snapshots_6_18}, {br_snapshots_5_18}, {br_snapshots_4_18}, {br_snapshots_3_18}, {br_snapshots_2_18}, {br_snapshots_1_18}, {br_snapshots_0_18}};\n wire [7:0][5:0] _GEN_19 = {{br_snapshots_7_19}, {br_snapshots_6_19}, {br_snapshots_5_19}, {br_snapshots_4_19}, {br_snapshots_3_19}, {br_snapshots_2_19}, {br_snapshots_1_19}, {br_snapshots_0_19}};\n wire [7:0][5:0] _GEN_20 = {{br_snapshots_7_20}, {br_snapshots_6_20}, {br_snapshots_5_20}, {br_snapshots_4_20}, {br_snapshots_3_20}, {br_snapshots_2_20}, {br_snapshots_1_20}, {br_snapshots_0_20}};\n wire [7:0][5:0] _GEN_21 = {{br_snapshots_7_21}, {br_snapshots_6_21}, {br_snapshots_5_21}, {br_snapshots_4_21}, {br_snapshots_3_21}, {br_snapshots_2_21}, {br_snapshots_1_21}, {br_snapshots_0_21}};\n wire [7:0][5:0] _GEN_22 = {{br_snapshots_7_22}, {br_snapshots_6_22}, {br_snapshots_5_22}, {br_snapshots_4_22}, {br_snapshots_3_22}, {br_snapshots_2_22}, {br_snapshots_1_22}, {br_snapshots_0_22}};\n wire [7:0][5:0] _GEN_23 = {{br_snapshots_7_23}, {br_snapshots_6_23}, {br_snapshots_5_23}, {br_snapshots_4_23}, {br_snapshots_3_23}, {br_snapshots_2_23}, {br_snapshots_1_23}, {br_snapshots_0_23}};\n wire [7:0][5:0] _GEN_24 = {{br_snapshots_7_24}, {br_snapshots_6_24}, {br_snapshots_5_24}, {br_snapshots_4_24}, {br_snapshots_3_24}, {br_snapshots_2_24}, {br_snapshots_1_24}, {br_snapshots_0_24}};\n wire [7:0][5:0] _GEN_25 = {{br_snapshots_7_25}, {br_snapshots_6_25}, {br_snapshots_5_25}, {br_snapshots_4_25}, {br_snapshots_3_25}, {br_snapshots_2_25}, {br_snapshots_1_25}, {br_snapshots_0_25}};\n wire [7:0][5:0] _GEN_26 = {{br_snapshots_7_26}, {br_snapshots_6_26}, {br_snapshots_5_26}, {br_snapshots_4_26}, {br_snapshots_3_26}, {br_snapshots_2_26}, {br_snapshots_1_26}, {br_snapshots_0_26}};\n wire [7:0][5:0] _GEN_27 = {{br_snapshots_7_27}, {br_snapshots_6_27}, {br_snapshots_5_27}, {br_snapshots_4_27}, {br_snapshots_3_27}, {br_snapshots_2_27}, {br_snapshots_1_27}, {br_snapshots_0_27}};\n wire [7:0][5:0] _GEN_28 = {{br_snapshots_7_28}, {br_snapshots_6_28}, {br_snapshots_5_28}, {br_snapshots_4_28}, {br_snapshots_3_28}, {br_snapshots_2_28}, {br_snapshots_1_28}, {br_snapshots_0_28}};\n wire [7:0][5:0] _GEN_29 = {{br_snapshots_7_29}, {br_snapshots_6_29}, {br_snapshots_5_29}, {br_snapshots_4_29}, {br_snapshots_3_29}, {br_snapshots_2_29}, {br_snapshots_1_29}, {br_snapshots_0_29}};\n wire [7:0][5:0] _GEN_30 = {{br_snapshots_7_30}, {br_snapshots_6_30}, {br_snapshots_5_30}, {br_snapshots_4_30}, {br_snapshots_3_30}, {br_snapshots_2_30}, {br_snapshots_1_30}, {br_snapshots_0_30}};\n wire [7:0][5:0] _GEN_31 = {{br_snapshots_7_31}, {br_snapshots_6_31}, {br_snapshots_5_31}, {br_snapshots_4_31}, {br_snapshots_3_31}, {br_snapshots_2_31}, {br_snapshots_1_31}, {br_snapshots_0_31}};\n wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst;\n wire [30:0] _GEN_32 = _remap_ldsts_oh_T[31:1] & {31{io_remap_reqs_0_valid}};\n wire [5:0] remapped_row_1 = _GEN_32[0] ? io_remap_reqs_0_pdst : map_table_1;\n wire [5:0] remap_table_1_2 = _GEN_32[1] ? io_remap_reqs_0_pdst : map_table_2;\n wire [5:0] remap_table_1_3 = _GEN_32[2] ? io_remap_reqs_0_pdst : map_table_3;\n wire [5:0] remap_table_1_4 = _GEN_32[3] ? io_remap_reqs_0_pdst : map_table_4;\n wire [5:0] remap_table_1_5 = _GEN_32[4] ? io_remap_reqs_0_pdst : map_table_5;\n wire [5:0] remap_table_1_6 = _GEN_32[5] ? io_remap_reqs_0_pdst : map_table_6;\n wire [5:0] remap_table_1_7 = _GEN_32[6] ? io_remap_reqs_0_pdst : map_table_7;\n wire [5:0] remap_table_1_8 = _GEN_32[7] ? io_remap_reqs_0_pdst : map_table_8;\n wire [5:0] remap_table_1_9 = _GEN_32[8] ? io_remap_reqs_0_pdst : map_table_9;\n wire [5:0] remap_table_1_10 = _GEN_32[9] ? io_remap_reqs_0_pdst : map_table_10;\n wire [5:0] remap_table_1_11 = _GEN_32[10] ? io_remap_reqs_0_pdst : map_table_11;\n wire [5:0] remap_table_1_12 = _GEN_32[11] ? io_remap_reqs_0_pdst : map_table_12;\n wire [5:0] remap_table_1_13 = _GEN_32[12] ? io_remap_reqs_0_pdst : map_table_13;\n wire [5:0] remap_table_1_14 = _GEN_32[13] ? io_remap_reqs_0_pdst : map_table_14;\n wire [5:0] remap_table_1_15 = _GEN_32[14] ? io_remap_reqs_0_pdst : map_table_15;\n wire [5:0] remap_table_1_16 = _GEN_32[15] ? io_remap_reqs_0_pdst : map_table_16;\n wire [5:0] remap_table_1_17 = _GEN_32[16] ? io_remap_reqs_0_pdst : map_table_17;\n wire [5:0] remap_table_1_18 = _GEN_32[17] ? io_remap_reqs_0_pdst : map_table_18;\n wire [5:0] remap_table_1_19 = _GEN_32[18] ? io_remap_reqs_0_pdst : map_table_19;\n wire [5:0] remap_table_1_20 = _GEN_32[19] ? io_remap_reqs_0_pdst : map_table_20;\n wire [5:0] remap_table_1_21 = _GEN_32[20] ? io_remap_reqs_0_pdst : map_table_21;\n wire [5:0] remap_table_1_22 = _GEN_32[21] ? io_remap_reqs_0_pdst : map_table_22;\n wire [5:0] remap_table_1_23 = _GEN_32[22] ? io_remap_reqs_0_pdst : map_table_23;\n wire [5:0] remap_table_1_24 = _GEN_32[23] ? io_remap_reqs_0_pdst : map_table_24;\n wire [5:0] remap_table_1_25 = _GEN_32[24] ? io_remap_reqs_0_pdst : map_table_25;\n wire [5:0] remap_table_1_26 = _GEN_32[25] ? io_remap_reqs_0_pdst : map_table_26;\n wire [5:0] remap_table_1_27 = _GEN_32[26] ? io_remap_reqs_0_pdst : map_table_27;\n wire [5:0] remap_table_1_28 = _GEN_32[27] ? io_remap_reqs_0_pdst : map_table_28;\n wire [5:0] remap_table_1_29 = _GEN_32[28] ? io_remap_reqs_0_pdst : map_table_29;\n wire [5:0] remap_table_1_30 = _GEN_32[29] ? io_remap_reqs_0_pdst : map_table_30;\n wire [5:0] remap_table_1_31 = _GEN_32[30] ? io_remap_reqs_0_pdst : map_table_31;\n always @(posedge clock) begin\n if (reset) begin\n map_table_1 <= 6'h0;\n map_table_2 <= 6'h0;\n map_table_3 <= 6'h0;\n map_table_4 <= 6'h0;\n map_table_5 <= 6'h0;\n map_table_6 <= 6'h0;\n map_table_7 <= 6'h0;\n map_table_8 <= 6'h0;\n map_table_9 <= 6'h0;\n map_table_10 <= 6'h0;\n map_table_11 <= 6'h0;\n map_table_12 <= 6'h0;\n map_table_13 <= 6'h0;\n map_table_14 <= 6'h0;\n map_table_15 <= 6'h0;\n map_table_16 <= 6'h0;\n map_table_17 <= 6'h0;\n map_table_18 <= 6'h0;\n map_table_19 <= 6'h0;\n map_table_20 <= 6'h0;\n map_table_21 <= 6'h0;\n map_table_22 <= 6'h0;\n map_table_23 <= 6'h0;\n map_table_24 <= 6'h0;\n map_table_25 <= 6'h0;\n map_table_26 <= 6'h0;\n map_table_27 <= 6'h0;\n map_table_28 <= 6'h0;\n map_table_29 <= 6'h0;\n map_table_30 <= 6'h0;\n map_table_31 <= 6'h0;\n end\n else if (io_brupdate_b2_mispredict) begin\n map_table_1 <= _GEN_1[io_brupdate_b2_uop_br_tag];\n map_table_2 <= _GEN_2[io_brupdate_b2_uop_br_tag];\n map_table_3 <= _GEN_3[io_brupdate_b2_uop_br_tag];\n map_table_4 <= _GEN_4[io_brupdate_b2_uop_br_tag];\n map_table_5 <= _GEN_5[io_brupdate_b2_uop_br_tag];\n map_table_6 <= _GEN_6[io_brupdate_b2_uop_br_tag];\n map_table_7 <= _GEN_7[io_brupdate_b2_uop_br_tag];\n map_table_8 <= _GEN_8[io_brupdate_b2_uop_br_tag];\n map_table_9 <= _GEN_9[io_brupdate_b2_uop_br_tag];\n map_table_10 <= _GEN_10[io_brupdate_b2_uop_br_tag];\n map_table_11 <= _GEN_11[io_brupdate_b2_uop_br_tag];\n map_table_12 <= _GEN_12[io_brupdate_b2_uop_br_tag];\n map_table_13 <= _GEN_13[io_brupdate_b2_uop_br_tag];\n map_table_14 <= _GEN_14[io_brupdate_b2_uop_br_tag];\n map_table_15 <= _GEN_15[io_brupdate_b2_uop_br_tag];\n map_table_16 <= _GEN_16[io_brupdate_b2_uop_br_tag];\n map_table_17 <= _GEN_17[io_brupdate_b2_uop_br_tag];\n map_table_18 <= _GEN_18[io_brupdate_b2_uop_br_tag];\n map_table_19 <= _GEN_19[io_brupdate_b2_uop_br_tag];\n map_table_20 <= _GEN_20[io_brupdate_b2_uop_br_tag];\n map_table_21 <= _GEN_21[io_brupdate_b2_uop_br_tag];\n map_table_22 <= _GEN_22[io_brupdate_b2_uop_br_tag];\n map_table_23 <= _GEN_23[io_brupdate_b2_uop_br_tag];\n map_table_24 <= _GEN_24[io_brupdate_b2_uop_br_tag];\n map_table_25 <= _GEN_25[io_brupdate_b2_uop_br_tag];\n map_table_26 <= _GEN_26[io_brupdate_b2_uop_br_tag];\n map_table_27 <= _GEN_27[io_brupdate_b2_uop_br_tag];\n map_table_28 <= _GEN_28[io_brupdate_b2_uop_br_tag];\n map_table_29 <= _GEN_29[io_brupdate_b2_uop_br_tag];\n map_table_30 <= _GEN_30[io_brupdate_b2_uop_br_tag];\n map_table_31 <= _GEN_31[io_brupdate_b2_uop_br_tag];\n end\n else begin\n if (_GEN_32[0])\n map_table_1 <= io_remap_reqs_0_pdst;\n if (_GEN_32[1])\n map_table_2 <= io_remap_reqs_0_pdst;\n if (_GEN_32[2])\n map_table_3 <= io_remap_reqs_0_pdst;\n if (_GEN_32[3])\n map_table_4 <= io_remap_reqs_0_pdst;\n if (_GEN_32[4])\n map_table_5 <= io_remap_reqs_0_pdst;\n if (_GEN_32[5])\n map_table_6 <= io_remap_reqs_0_pdst;\n if (_GEN_32[6])\n map_table_7 <= io_remap_reqs_0_pdst;\n if (_GEN_32[7])\n map_table_8 <= io_remap_reqs_0_pdst;\n if (_GEN_32[8])\n map_table_9 <= io_remap_reqs_0_pdst;\n if (_GEN_32[9])\n map_table_10 <= io_remap_reqs_0_pdst;\n if (_GEN_32[10])\n map_table_11 <= io_remap_reqs_0_pdst;\n if (_GEN_32[11])\n map_table_12 <= io_remap_reqs_0_pdst;\n if (_GEN_32[12])\n map_table_13 <= io_remap_reqs_0_pdst;\n if (_GEN_32[13])\n map_table_14 <= io_remap_reqs_0_pdst;\n if (_GEN_32[14])\n map_table_15 <= io_remap_reqs_0_pdst;\n if (_GEN_32[15])\n map_table_16 <= io_remap_reqs_0_pdst;\n if (_GEN_32[16])\n map_table_17 <= io_remap_reqs_0_pdst;\n if (_GEN_32[17])\n map_table_18 <= io_remap_reqs_0_pdst;\n if (_GEN_32[18])\n map_table_19 <= io_remap_reqs_0_pdst;\n if (_GEN_32[19])\n map_table_20 <= io_remap_reqs_0_pdst;\n if (_GEN_32[20])\n map_table_21 <= io_remap_reqs_0_pdst;\n if (_GEN_32[21])\n map_table_22 <= io_remap_reqs_0_pdst;\n if (_GEN_32[22])\n map_table_23 <= io_remap_reqs_0_pdst;\n if (_GEN_32[23])\n map_table_24 <= io_remap_reqs_0_pdst;\n if (_GEN_32[24])\n map_table_25 <= io_remap_reqs_0_pdst;\n if (_GEN_32[25])\n map_table_26 <= io_remap_reqs_0_pdst;\n if (_GEN_32[26])\n map_table_27 <= io_remap_reqs_0_pdst;\n if (_GEN_32[27])\n map_table_28 <= io_remap_reqs_0_pdst;\n if (_GEN_32[28])\n map_table_29 <= io_remap_reqs_0_pdst;\n if (_GEN_32[29])\n map_table_30 <= io_remap_reqs_0_pdst;\n if (_GEN_32[30])\n map_table_31 <= io_remap_reqs_0_pdst;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h0) begin\n br_snapshots_0_1 <= remapped_row_1;\n br_snapshots_0_2 <= remap_table_1_2;\n br_snapshots_0_3 <= remap_table_1_3;\n br_snapshots_0_4 <= remap_table_1_4;\n br_snapshots_0_5 <= remap_table_1_5;\n br_snapshots_0_6 <= remap_table_1_6;\n br_snapshots_0_7 <= remap_table_1_7;\n br_snapshots_0_8 <= remap_table_1_8;\n br_snapshots_0_9 <= remap_table_1_9;\n br_snapshots_0_10 <= remap_table_1_10;\n br_snapshots_0_11 <= remap_table_1_11;\n br_snapshots_0_12 <= remap_table_1_12;\n br_snapshots_0_13 <= remap_table_1_13;\n br_snapshots_0_14 <= remap_table_1_14;\n br_snapshots_0_15 <= remap_table_1_15;\n br_snapshots_0_16 <= remap_table_1_16;\n br_snapshots_0_17 <= remap_table_1_17;\n br_snapshots_0_18 <= remap_table_1_18;\n br_snapshots_0_19 <= remap_table_1_19;\n br_snapshots_0_20 <= remap_table_1_20;\n br_snapshots_0_21 <= remap_table_1_21;\n br_snapshots_0_22 <= remap_table_1_22;\n br_snapshots_0_23 <= remap_table_1_23;\n br_snapshots_0_24 <= remap_table_1_24;\n br_snapshots_0_25 <= remap_table_1_25;\n br_snapshots_0_26 <= remap_table_1_26;\n br_snapshots_0_27 <= remap_table_1_27;\n br_snapshots_0_28 <= remap_table_1_28;\n br_snapshots_0_29 <= remap_table_1_29;\n br_snapshots_0_30 <= remap_table_1_30;\n br_snapshots_0_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h1) begin\n br_snapshots_1_1 <= remapped_row_1;\n br_snapshots_1_2 <= remap_table_1_2;\n br_snapshots_1_3 <= remap_table_1_3;\n br_snapshots_1_4 <= remap_table_1_4;\n br_snapshots_1_5 <= remap_table_1_5;\n br_snapshots_1_6 <= remap_table_1_6;\n br_snapshots_1_7 <= remap_table_1_7;\n br_snapshots_1_8 <= remap_table_1_8;\n br_snapshots_1_9 <= remap_table_1_9;\n br_snapshots_1_10 <= remap_table_1_10;\n br_snapshots_1_11 <= remap_table_1_11;\n br_snapshots_1_12 <= remap_table_1_12;\n br_snapshots_1_13 <= remap_table_1_13;\n br_snapshots_1_14 <= remap_table_1_14;\n br_snapshots_1_15 <= remap_table_1_15;\n br_snapshots_1_16 <= remap_table_1_16;\n br_snapshots_1_17 <= remap_table_1_17;\n br_snapshots_1_18 <= remap_table_1_18;\n br_snapshots_1_19 <= remap_table_1_19;\n br_snapshots_1_20 <= remap_table_1_20;\n br_snapshots_1_21 <= remap_table_1_21;\n br_snapshots_1_22 <= remap_table_1_22;\n br_snapshots_1_23 <= remap_table_1_23;\n br_snapshots_1_24 <= remap_table_1_24;\n br_snapshots_1_25 <= remap_table_1_25;\n br_snapshots_1_26 <= remap_table_1_26;\n br_snapshots_1_27 <= remap_table_1_27;\n br_snapshots_1_28 <= remap_table_1_28;\n br_snapshots_1_29 <= remap_table_1_29;\n br_snapshots_1_30 <= remap_table_1_30;\n br_snapshots_1_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h2) begin\n br_snapshots_2_1 <= remapped_row_1;\n br_snapshots_2_2 <= remap_table_1_2;\n br_snapshots_2_3 <= remap_table_1_3;\n br_snapshots_2_4 <= remap_table_1_4;\n br_snapshots_2_5 <= remap_table_1_5;\n br_snapshots_2_6 <= remap_table_1_6;\n br_snapshots_2_7 <= remap_table_1_7;\n br_snapshots_2_8 <= remap_table_1_8;\n br_snapshots_2_9 <= remap_table_1_9;\n br_snapshots_2_10 <= remap_table_1_10;\n br_snapshots_2_11 <= remap_table_1_11;\n br_snapshots_2_12 <= remap_table_1_12;\n br_snapshots_2_13 <= remap_table_1_13;\n br_snapshots_2_14 <= remap_table_1_14;\n br_snapshots_2_15 <= remap_table_1_15;\n br_snapshots_2_16 <= remap_table_1_16;\n br_snapshots_2_17 <= remap_table_1_17;\n br_snapshots_2_18 <= remap_table_1_18;\n br_snapshots_2_19 <= remap_table_1_19;\n br_snapshots_2_20 <= remap_table_1_20;\n br_snapshots_2_21 <= remap_table_1_21;\n br_snapshots_2_22 <= remap_table_1_22;\n br_snapshots_2_23 <= remap_table_1_23;\n br_snapshots_2_24 <= remap_table_1_24;\n br_snapshots_2_25 <= remap_table_1_25;\n br_snapshots_2_26 <= remap_table_1_26;\n br_snapshots_2_27 <= remap_table_1_27;\n br_snapshots_2_28 <= remap_table_1_28;\n br_snapshots_2_29 <= remap_table_1_29;\n br_snapshots_2_30 <= remap_table_1_30;\n br_snapshots_2_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h3) begin\n br_snapshots_3_1 <= remapped_row_1;\n br_snapshots_3_2 <= remap_table_1_2;\n br_snapshots_3_3 <= remap_table_1_3;\n br_snapshots_3_4 <= remap_table_1_4;\n br_snapshots_3_5 <= remap_table_1_5;\n br_snapshots_3_6 <= remap_table_1_6;\n br_snapshots_3_7 <= remap_table_1_7;\n br_snapshots_3_8 <= remap_table_1_8;\n br_snapshots_3_9 <= remap_table_1_9;\n br_snapshots_3_10 <= remap_table_1_10;\n br_snapshots_3_11 <= remap_table_1_11;\n br_snapshots_3_12 <= remap_table_1_12;\n br_snapshots_3_13 <= remap_table_1_13;\n br_snapshots_3_14 <= remap_table_1_14;\n br_snapshots_3_15 <= remap_table_1_15;\n br_snapshots_3_16 <= remap_table_1_16;\n br_snapshots_3_17 <= remap_table_1_17;\n br_snapshots_3_18 <= remap_table_1_18;\n br_snapshots_3_19 <= remap_table_1_19;\n br_snapshots_3_20 <= remap_table_1_20;\n br_snapshots_3_21 <= remap_table_1_21;\n br_snapshots_3_22 <= remap_table_1_22;\n br_snapshots_3_23 <= remap_table_1_23;\n br_snapshots_3_24 <= remap_table_1_24;\n br_snapshots_3_25 <= remap_table_1_25;\n br_snapshots_3_26 <= remap_table_1_26;\n br_snapshots_3_27 <= remap_table_1_27;\n br_snapshots_3_28 <= remap_table_1_28;\n br_snapshots_3_29 <= remap_table_1_29;\n br_snapshots_3_30 <= remap_table_1_30;\n br_snapshots_3_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h4) begin\n br_snapshots_4_1 <= remapped_row_1;\n br_snapshots_4_2 <= remap_table_1_2;\n br_snapshots_4_3 <= remap_table_1_3;\n br_snapshots_4_4 <= remap_table_1_4;\n br_snapshots_4_5 <= remap_table_1_5;\n br_snapshots_4_6 <= remap_table_1_6;\n br_snapshots_4_7 <= remap_table_1_7;\n br_snapshots_4_8 <= remap_table_1_8;\n br_snapshots_4_9 <= remap_table_1_9;\n br_snapshots_4_10 <= remap_table_1_10;\n br_snapshots_4_11 <= remap_table_1_11;\n br_snapshots_4_12 <= remap_table_1_12;\n br_snapshots_4_13 <= remap_table_1_13;\n br_snapshots_4_14 <= remap_table_1_14;\n br_snapshots_4_15 <= remap_table_1_15;\n br_snapshots_4_16 <= remap_table_1_16;\n br_snapshots_4_17 <= remap_table_1_17;\n br_snapshots_4_18 <= remap_table_1_18;\n br_snapshots_4_19 <= remap_table_1_19;\n br_snapshots_4_20 <= remap_table_1_20;\n br_snapshots_4_21 <= remap_table_1_21;\n br_snapshots_4_22 <= remap_table_1_22;\n br_snapshots_4_23 <= remap_table_1_23;\n br_snapshots_4_24 <= remap_table_1_24;\n br_snapshots_4_25 <= remap_table_1_25;\n br_snapshots_4_26 <= remap_table_1_26;\n br_snapshots_4_27 <= remap_table_1_27;\n br_snapshots_4_28 <= remap_table_1_28;\n br_snapshots_4_29 <= remap_table_1_29;\n br_snapshots_4_30 <= remap_table_1_30;\n br_snapshots_4_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h5) begin\n br_snapshots_5_1 <= remapped_row_1;\n br_snapshots_5_2 <= remap_table_1_2;\n br_snapshots_5_3 <= remap_table_1_3;\n br_snapshots_5_4 <= remap_table_1_4;\n br_snapshots_5_5 <= remap_table_1_5;\n br_snapshots_5_6 <= remap_table_1_6;\n br_snapshots_5_7 <= remap_table_1_7;\n br_snapshots_5_8 <= remap_table_1_8;\n br_snapshots_5_9 <= remap_table_1_9;\n br_snapshots_5_10 <= remap_table_1_10;\n br_snapshots_5_11 <= remap_table_1_11;\n br_snapshots_5_12 <= remap_table_1_12;\n br_snapshots_5_13 <= remap_table_1_13;\n br_snapshots_5_14 <= remap_table_1_14;\n br_snapshots_5_15 <= remap_table_1_15;\n br_snapshots_5_16 <= remap_table_1_16;\n br_snapshots_5_17 <= remap_table_1_17;\n br_snapshots_5_18 <= remap_table_1_18;\n br_snapshots_5_19 <= remap_table_1_19;\n br_snapshots_5_20 <= remap_table_1_20;\n br_snapshots_5_21 <= remap_table_1_21;\n br_snapshots_5_22 <= remap_table_1_22;\n br_snapshots_5_23 <= remap_table_1_23;\n br_snapshots_5_24 <= remap_table_1_24;\n br_snapshots_5_25 <= remap_table_1_25;\n br_snapshots_5_26 <= remap_table_1_26;\n br_snapshots_5_27 <= remap_table_1_27;\n br_snapshots_5_28 <= remap_table_1_28;\n br_snapshots_5_29 <= remap_table_1_29;\n br_snapshots_5_30 <= remap_table_1_30;\n br_snapshots_5_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h6) begin\n br_snapshots_6_1 <= remapped_row_1;\n br_snapshots_6_2 <= remap_table_1_2;\n br_snapshots_6_3 <= remap_table_1_3;\n br_snapshots_6_4 <= remap_table_1_4;\n br_snapshots_6_5 <= remap_table_1_5;\n br_snapshots_6_6 <= remap_table_1_6;\n br_snapshots_6_7 <= remap_table_1_7;\n br_snapshots_6_8 <= remap_table_1_8;\n br_snapshots_6_9 <= remap_table_1_9;\n br_snapshots_6_10 <= remap_table_1_10;\n br_snapshots_6_11 <= remap_table_1_11;\n br_snapshots_6_12 <= remap_table_1_12;\n br_snapshots_6_13 <= remap_table_1_13;\n br_snapshots_6_14 <= remap_table_1_14;\n br_snapshots_6_15 <= remap_table_1_15;\n br_snapshots_6_16 <= remap_table_1_16;\n br_snapshots_6_17 <= remap_table_1_17;\n br_snapshots_6_18 <= remap_table_1_18;\n br_snapshots_6_19 <= remap_table_1_19;\n br_snapshots_6_20 <= remap_table_1_20;\n br_snapshots_6_21 <= remap_table_1_21;\n br_snapshots_6_22 <= remap_table_1_22;\n br_snapshots_6_23 <= remap_table_1_23;\n br_snapshots_6_24 <= remap_table_1_24;\n br_snapshots_6_25 <= remap_table_1_25;\n br_snapshots_6_26 <= remap_table_1_26;\n br_snapshots_6_27 <= remap_table_1_27;\n br_snapshots_6_28 <= remap_table_1_28;\n br_snapshots_6_29 <= remap_table_1_29;\n br_snapshots_6_30 <= remap_table_1_30;\n br_snapshots_6_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & (&io_ren_br_tags_0_bits)) begin\n br_snapshots_7_1 <= remapped_row_1;\n br_snapshots_7_2 <= remap_table_1_2;\n br_snapshots_7_3 <= remap_table_1_3;\n br_snapshots_7_4 <= remap_table_1_4;\n br_snapshots_7_5 <= remap_table_1_5;\n br_snapshots_7_6 <= remap_table_1_6;\n br_snapshots_7_7 <= remap_table_1_7;\n br_snapshots_7_8 <= remap_table_1_8;\n br_snapshots_7_9 <= remap_table_1_9;\n br_snapshots_7_10 <= remap_table_1_10;\n br_snapshots_7_11 <= remap_table_1_11;\n br_snapshots_7_12 <= remap_table_1_12;\n br_snapshots_7_13 <= remap_table_1_13;\n br_snapshots_7_14 <= remap_table_1_14;\n br_snapshots_7_15 <= remap_table_1_15;\n br_snapshots_7_16 <= remap_table_1_16;\n br_snapshots_7_17 <= remap_table_1_17;\n br_snapshots_7_18 <= remap_table_1_18;\n br_snapshots_7_19 <= remap_table_1_19;\n br_snapshots_7_20 <= remap_table_1_20;\n br_snapshots_7_21 <= remap_table_1_21;\n br_snapshots_7_22 <= remap_table_1_22;\n br_snapshots_7_23 <= remap_table_1_23;\n br_snapshots_7_24 <= remap_table_1_24;\n br_snapshots_7_25 <= remap_table_1_25;\n br_snapshots_7_26 <= remap_table_1_26;\n br_snapshots_7_27 <= remap_table_1_27;\n br_snapshots_7_28 <= remap_table_1_28;\n br_snapshots_7_29 <= remap_table_1_29;\n br_snapshots_7_30 <= remap_table_1_30;\n br_snapshots_7_31 <= remap_table_1_31;\n end\n end\n assign io_map_resps_0_prs1 = _GEN[io_map_reqs_0_lrs1[4:0]];\n assign io_map_resps_0_prs2 = _GEN[io_map_reqs_0_lrs2[4:0]];\n assign io_map_resps_0_stale_pdst = _GEN[io_map_reqs_0_ldst[4:0]];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module ram_4x65(\n input [1:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [64:0] R0_data,\n input [1:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [64:0] W0_data\n);\n\n reg [64:0] Memory[0:3];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLBToBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_bits_head,\n output io_beat_bits_tail\n);\n\n assign io_beat_bits_head = 1'h1;\n assign io_beat_bits_tail = 1'h0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module mem(\n input [12:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [63:0] RW0_wdata,\n output [63:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n mem_ext mem_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.withClock\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\nimport scala.collection.mutable.ArrayBuffer\n\ncase class RocketCoreParams(\n xLen: Int = 64,\n pgLevels: Int = 3, // sv39 default\n bootFreqHz: BigInt = 0,\n useVM: Boolean = true,\n useUser: Boolean = false,\n useSupervisor: Boolean = false,\n useHypervisor: Boolean = false,\n useDebug: Boolean = true,\n useAtomics: Boolean = true,\n useAtomicsOnlyForIO: Boolean = false,\n useCompressed: Boolean = true,\n useRVE: Boolean = false,\n useConditionalZero: Boolean = false,\n useZba: Boolean = false,\n useZbb: Boolean = false,\n useZbs: Boolean = false,\n nLocalInterrupts: Int = 0,\n useNMI: Boolean = false,\n nBreakpoints: Int = 1,\n useBPWatch: Boolean = false,\n mcontextWidth: Int = 0,\n scontextWidth: Int = 0,\n nPMPs: Int = 8,\n nPerfCounters: Int = 0,\n haveBasicCounters: Boolean = true,\n haveCFlush: Boolean = false,\n misaWritable: Boolean = true,\n nL2TLBEntries: Int = 0,\n nL2TLBWays: Int = 1,\n nPTECacheEntries: Int = 8,\n mtvecInit: Option[BigInt] = Some(BigInt(0)),\n mtvecWritable: Boolean = true,\n fastLoadWord: Boolean = true,\n fastLoadByte: Boolean = false,\n branchPredictionModeCSR: Boolean = false,\n clockGate: Boolean = false,\n mvendorid: Int = 0, // 0 means non-commercial implementation\n mimpid: Int = 0x20181004, // release date in BCD\n mulDiv: Option[MulDivParams] = Some(MulDivParams()),\n fpu: Option[FPUParams] = Some(FPUParams()),\n debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB\n haveCease: Boolean = true, // non-standard CEASE instruction\n haveSimTimeout: Boolean = true, // add plusarg for simulation timeout\n vector: Option[RocketCoreVectorParams] = None\n) extends CoreParams {\n val lgPauseCycles = 5\n val haveFSDirty = false\n val pmpGranularity: Int = if (useHypervisor) 4096 else 4\n val fetchWidth: Int = if (useCompressed) 2 else 1\n // fetchWidth doubled, but coreInstBytes halved, for RVC:\n val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1)\n val retireWidth: Int = 1\n val instBits: Int = if (useCompressed) 16 else 32\n val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop\n val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace\n override val useVector = vector.isDefined\n override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)\n override def vLen = vector.map(_.vLen).getOrElse(0)\n override def eLen = vector.map(_.eLen).getOrElse(0)\n override def vfLen = vector.map(_.vfLen).getOrElse(0)\n override def vfh = vector.map(_.vfh).getOrElse(false)\n override def vExts = vector.map(_.vExts).getOrElse(Nil)\n override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)\n override val customIsaExt = Option.when(haveCease)(\"xrocket\") // CEASE instruction\n override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)\n override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs\n}\n\ntrait HasRocketCoreParameters extends HasCoreParameters {\n lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams]\n\n val fastLoadWord = rocketParams.fastLoadWord\n val fastLoadByte = rocketParams.fastLoadByte\n\n val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this\n\n require(!fastLoadByte || fastLoadWord)\n require(!rocketParams.haveFSDirty, \"rocket doesn't support setting fs dirty from outside, please disable haveFSDirty\")\n}\n\nclass RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters {\n override def bpmCSR = {\n rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0))))\n }\n\n private def haveDCache = tileParams.dcache.get.scratch.isEmpty\n\n override def chickenCSR = {\n val mask = BigInt(\n tileParams.dcache.get.clockGate.toInt << 0 |\n rocketParams.clockGate.toInt << 1 |\n rocketParams.clockGate.toInt << 2 |\n 1 << 3 | // disableSpeculativeICacheRefill\n haveDCache.toInt << 9 | // suppressCorruptOnGrantData\n tileParams.icache.get.prefetch.toInt << 17\n )\n Some(CustomCSR(chickenCSRId, mask, Some(mask)))\n }\n\n def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B)\n\n def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1))\n\n def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))\n\n // mimpid encodes a release version in the form of a BCD-encoded datestamp.\n def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))\n\n override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid\n}\n\nclass CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) {\n val buserror = Option.when(hasBeu)(Bool())\n}\n\ntrait HasRocketCoreIO extends HasRocketCoreParameters {\n implicit val p: Parameters\n def nTotalRoCCCSRs: Int\n val io = IO(new CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val reset_vector = Input(UInt(resetVectorLen.W))\n val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined))\n val imem = new FrontendIO\n val dmem = new HellaCacheIO\n val ptw = Flipped(new DatapathPTWIO())\n val fpu = Flipped(new FPUCoreIO())\n val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))\n val trace = Output(new TraceBundle)\n val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))\n val cease = Output(Bool())\n val wfi = Output(Bool())\n val traceStall = Input(Bool())\n val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None\n })\n}\n\n\nclass Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)\n with HasRocketCoreParameters\n with HasRocketCoreIO {\n def nTotalRoCCCSRs = tile.roccCSRs.flatten.size\n import ALU._\n\n val clock_en_reg = RegInit(true.B)\n val long_latency_stall = Reg(Bool())\n val id_reg_pause = Reg(Bool())\n val imem_might_request_reg = Reg(Bool())\n val clock_en = WireDefault(true.B)\n val gated_clock =\n if (!rocketParams.clockGate) clock\n else ClockGate(clock, clock_en, \"rocket_clock_gate\")\n\n class RocketImpl { // entering gated-clock domain\n\n // performance counters\n def pipelineIDToWB[T <: Data](x: T): T =\n RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid)\n val perfEvents = new EventSets(Seq(\n new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(\n (\"exception\", () => false.B),\n (\"load\", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),\n (\"store\", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),\n (\"amo\", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),\n (\"system\", () => id_ctrl.csr =/= CSR.N),\n (\"arith\", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),\n (\"branch\", () => id_ctrl.branch),\n (\"jal\", () => id_ctrl.jal),\n (\"jalr\", () => id_ctrl.jalr))\n ++ (if (!usingMulDiv) Seq() else Seq(\n (\"mul\", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV),\n (\"div\", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV)))\n ++ (if (!usingFPU) Seq() else Seq(\n (\"fp load\", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),\n (\"fp store\", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),\n (\"fp add\", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),\n (\"fp mul\", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),\n (\"fp mul-add\", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),\n (\"fp div/sqrt\", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),\n (\"fp other\", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),\n new EventSet((mask, hits) => (mask & hits).orR, Seq(\n (\"load-use interlock\", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),\n (\"long-latency interlock\", () => id_sboard_hazard),\n (\"csr interlock\", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),\n (\"I$ blocked\", () => icache_blocked),\n (\"D$ blocked\", () => id_ctrl.mem && dcache_blocked),\n (\"branch misprediction\", () => take_pc_mem && mem_direction_misprediction),\n (\"control-flow target misprediction\", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),\n (\"flush\", () => wb_reg_flush_pipe),\n (\"replay\", () => replay_wb))\n ++ (if (!usingMulDiv) Seq() else Seq(\n (\"mul/div interlock\", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))\n ++ (if (!usingFPU) Seq() else Seq(\n (\"fp interlock\", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),\n new EventSet((mask, hits) => (mask & hits).orR, Seq(\n (\"I$ miss\", () => io.imem.perf.acquire),\n (\"D$ miss\", () => io.dmem.perf.acquire),\n (\"D$ release\", () => io.dmem.perf.release),\n (\"ITLB miss\", () => io.imem.perf.tlbMiss),\n (\"DTLB miss\", () => io.dmem.perf.tlbMiss),\n (\"L2 TLB miss\", () => io.ptw.perf.l2miss)))))\n\n val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen\n val decode_table = {\n (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:\n (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:\n (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:\n (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:\n (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++:\n (usingRoCC.option(new RoCCDecode)) ++:\n (if (xLen == 32) new I32Decode else new I64Decode) +:\n (usingVM.option(new SVMDecode)) ++:\n (usingSupervisor.option(new SDecode)) ++:\n (usingHypervisor.option(new HypervisorDecode)) ++:\n ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++:\n (usingDebug.option(new DebugDecode)) ++:\n (usingNMI.option(new NMIDecode)) ++:\n (usingConditionalZero.option(new ConditionalZeroDecode)) ++:\n Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++:\n coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++:\n rocketParams.haveCease.option(new CeaseDecode) ++:\n usingVector.option(new VCFGDecode) ++:\n (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++:\n (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++:\n coreParams.useZbs.option(new ZbsDecode) ++:\n Seq(new IDecode)\n } flatMap(_.table)\n\n val ex_ctrl = Reg(new IntCtrlSigs)\n val mem_ctrl = Reg(new IntCtrlSigs)\n val wb_ctrl = Reg(new IntCtrlSigs)\n\n val ex_reg_xcpt_interrupt = Reg(Bool())\n val ex_reg_valid = Reg(Bool())\n val ex_reg_rvc = Reg(Bool())\n val ex_reg_btb_resp = Reg(new BTBResp)\n val ex_reg_xcpt = Reg(Bool())\n val ex_reg_flush_pipe = Reg(Bool())\n val ex_reg_load_use = Reg(Bool())\n val ex_reg_cause = Reg(UInt())\n val ex_reg_replay = Reg(Bool())\n val ex_reg_pc = Reg(UInt())\n val ex_reg_mem_size = Reg(UInt())\n val ex_reg_hls = Reg(Bool())\n val ex_reg_inst = Reg(Bits())\n val ex_reg_raw_inst = Reg(UInt())\n val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool()))\n val ex_reg_set_vconfig = Reg(Bool())\n\n val mem_reg_xcpt_interrupt = Reg(Bool())\n val mem_reg_valid = Reg(Bool())\n val mem_reg_rvc = Reg(Bool())\n val mem_reg_btb_resp = Reg(new BTBResp)\n val mem_reg_xcpt = Reg(Bool())\n val mem_reg_replay = Reg(Bool())\n val mem_reg_flush_pipe = Reg(Bool())\n val mem_reg_cause = Reg(UInt())\n val mem_reg_slow_bypass = Reg(Bool())\n val mem_reg_load = Reg(Bool())\n val mem_reg_store = Reg(Bool())\n val mem_reg_set_vconfig = Reg(Bool())\n val mem_reg_sfence = Reg(Bool())\n val mem_reg_pc = Reg(UInt())\n val mem_reg_inst = Reg(Bits())\n val mem_reg_mem_size = Reg(UInt())\n val mem_reg_hls_or_dv = Reg(Bool())\n val mem_reg_raw_inst = Reg(UInt())\n val mem_reg_wdata = Reg(Bits())\n val mem_reg_rs2 = Reg(Bits())\n val mem_br_taken = Reg(Bool())\n val take_pc_mem = Wire(Bool())\n val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool()))\n\n val wb_reg_valid = Reg(Bool())\n val wb_reg_xcpt = Reg(Bool())\n val wb_reg_replay = Reg(Bool())\n val wb_reg_flush_pipe = Reg(Bool())\n val wb_reg_cause = Reg(UInt())\n val wb_reg_set_vconfig = Reg(Bool())\n val wb_reg_sfence = Reg(Bool())\n val wb_reg_pc = Reg(UInt())\n val wb_reg_mem_size = Reg(UInt())\n val wb_reg_hls_or_dv = Reg(Bool())\n val wb_reg_hfence_v = Reg(Bool())\n val wb_reg_hfence_g = Reg(Bool())\n val wb_reg_inst = Reg(Bits())\n val wb_reg_raw_inst = Reg(UInt())\n val wb_reg_wdata = Reg(Bits())\n val wb_reg_rs2 = Reg(Bits())\n val take_pc_wb = Wire(Bool())\n val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool()))\n\n val take_pc_mem_wb = take_pc_wb || take_pc_mem\n val take_pc = take_pc_mem_wb\n\n // decode stage\n val ibuf = Module(new IBuf)\n val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)\n val id_raw_inst = ibuf.io.inst.map(_.bits.raw)\n val id_inst = id_expanded_inst.map(_.bits)\n ibuf.io.imem <> io.imem.resp\n ibuf.io.kill := take_pc\n\n require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)\n require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), \"Can't select both RVE and floating-point\")\n require(!(coreParams.useRVE && coreParams.useHypervisor), \"Can't select both RVE and Hypervisor\")\n val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table)\n\n val lgNXRegs = if (coreParams.useRVE) 4 else 5\n val regAddrMask = (1 << lgNXRegs) - 1\n\n def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0))\n val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3)\n val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2)\n val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1)\n val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd)\n\n val id_load_use = Wire(Bool())\n val id_reg_fence = RegInit(false.B)\n val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)\n val id_raddr = IndexedSeq(id_raddr1, id_raddr2)\n val rf = new RegFile(regAddrMask, xLen)\n val id_rs = id_raddr.map(rf.read _)\n val ctrl_killd = Wire(Bool())\n val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt\n\n val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined))\n val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)\n val id_system_insn = id_ctrl.csr === CSR.I\n val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U\n val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr))\n val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)\n val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B\n\n id_ctrl.vec := false.B\n if (usingVector) {\n val v_decode = rocketParams.vector.get.decoder(p)\n v_decode.io.inst := id_inst(0)\n v_decode.io.vconfig := csr.io.vector.get.vconfig\n when (v_decode.io.legal) {\n id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill\n id_ctrl.fp := v_decode.io.fp\n id_ctrl.rocc := false.B\n id_ctrl.branch := false.B\n id_ctrl.jal := false.B\n id_ctrl.jalr := false.B\n id_ctrl.rxs2 := v_decode.io.read_rs2\n id_ctrl.rxs1 := v_decode.io.read_rs1\n id_ctrl.mem := false.B\n id_ctrl.rfs1 := v_decode.io.read_frs1\n id_ctrl.rfs2 := false.B\n id_ctrl.rfs3 := false.B\n id_ctrl.wfd := v_decode.io.write_frd\n id_ctrl.mul := false.B\n id_ctrl.div := false.B\n id_ctrl.wxd := v_decode.io.write_rd\n id_ctrl.csr := CSR.N\n id_ctrl.fence_i := false.B\n id_ctrl.fence := false.B\n id_ctrl.amo := false.B\n id_ctrl.dp := false.B\n id_ctrl.vec := true.B\n }\n }\n\n\n val id_illegal_insn = !id_ctrl.legal ||\n (id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||\n id_ctrl.amo && !csr.io.status.isa('a'-'a') ||\n id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||\n (id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||\n id_ctrl.dp && !csr.io.status.isa('d'-'a') ||\n ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||\n id_raddr2_illegal && id_ctrl.rxs2 ||\n id_raddr1_illegal && id_ctrl.rxs1 ||\n id_waddr_illegal && id_ctrl.wxd ||\n id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||\n id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||\n !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal)\n val id_virtual_insn = id_ctrl.legal &&\n ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) ||\n (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal))\n // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)\n val id_amo_aq = id_inst(0)(26)\n val id_amo_rl = id_inst(0)(25)\n val id_fence_pred = id_inst(0)(27,24)\n val id_fence_succ = id_inst(0)(23,20)\n val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq\n val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid\n when (!id_mem_busy) { id_reg_fence := false.B }\n val id_rocc_busy = usingRoCC.B &&\n (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||\n mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)\n val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren\n val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B)\n val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||\n id_vec_busy && id_ctrl.fence ||\n id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))\n\n val bpu = Module(new BreakpointUnit(nBreakpoints))\n bpu.io.status := csr.io.status\n bpu.io.bp := csr.io.bp\n bpu.io.pc := ibuf.io.pc\n bpu.io.ea := mem_reg_wdata\n bpu.io.mcontext := csr.io.mcontext\n bpu.io.scontext := csr.io.scontext\n\n val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0\n val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1\n val (id_xcpt, id_cause) = checkExceptions(List(\n (csr.io.interrupt, csr.io.interrupt_cause),\n (bpu.io.debug_if, CSR.debugTriggerCause.U),\n (bpu.io.xcpt_if, Causes.breakpoint.U),\n (id_xcpt0.pf.inst, Causes.fetch_page_fault.U),\n (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U),\n (id_xcpt0.ae.inst, Causes.fetch_access.U),\n (id_xcpt1.pf.inst, Causes.fetch_page_fault.U),\n (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U),\n (id_xcpt1.ae.inst, Causes.fetch_access.U),\n (id_virtual_insn, Causes.virtual_instruction.U),\n (id_illegal_insn, Causes.illegal_instruction.U)))\n\n val idCoverCauses = List(\n (CSR.debugTriggerCause, \"DEBUG_TRIGGER\"),\n (Causes.breakpoint, \"BREAKPOINT\"),\n (Causes.fetch_access, \"FETCH_ACCESS\"),\n (Causes.illegal_instruction, \"ILLEGAL_INSTRUCTION\")\n ) ++ (if (usingVM) List(\n (Causes.fetch_page_fault, \"FETCH_PAGE_FAULT\")\n ) else Nil)\n coverExceptions(id_xcpt, id_cause, \"DECODE\", idCoverCauses)\n\n val dcache_bypass_data =\n if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)\n else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)\n else wb_reg_wdata\n\n // detect bypass opportunities\n val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U\n val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U\n val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U\n val bypass_sources = IndexedSeq(\n (true.B, 0.U, 0.U), // treat reading x0 as a bypass\n (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),\n (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),\n (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))\n val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))\n\n // execute stage\n val bypass_mux = bypass_sources.map(_._3)\n val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))\n val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W)))\n val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))\n val ex_rs = for (i <- 0 until id_raddr.size)\n yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))\n val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)\n val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13)\n val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq(\n A1_RS1 -> ex_rs(0).asSInt,\n A1_PC -> ex_reg_pc.asSInt,\n A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S)\n ))\n val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt\n val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq(\n A2_RS2 -> ex_rs(1).asSInt,\n A2_IMM -> ex_imm,\n A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S),\n ) ++ (if (coreParams.useZbs) Seq(\n A2_RS2OH -> ex_op2_oh,\n A2_IMMOH -> ex_op2_oh,\n ) else Nil))\n\n val (ex_new_vl, ex_new_vconfig) = if (usingVector) {\n val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(\n ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),\n !ex_reg_inst(31) -> ex_reg_inst(30,20))))\n val ex_avl = Mux(ex_ctrl.rxs1,\n Mux(ex_reg_inst(19,15) === 0.U,\n Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),\n ex_rs(0)\n ),\n ex_reg_inst(19,15))\n val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B)\n val ex_new_vconfig = Wire(new VConfig)\n ex_new_vconfig.vtype := ex_new_vtype\n ex_new_vconfig.vl := ex_new_vl\n (Some(ex_new_vl), Some(ex_new_vconfig))\n } else { (None, None) }\n\n val alu = Module(new ALU)\n alu.io.dw := ex_ctrl.alu_dw\n alu.io.fn := ex_ctrl.alu_fn\n alu.io.in2 := ex_op2.asUInt\n alu.io.in1 := ex_op1.asUInt\n\n // multiplier and divider\n val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))\n div.io.req.valid := ex_reg_valid && ex_ctrl.div\n div.io.req.bits.dw := ex_ctrl.alu_dw\n div.io.req.bits.fn := ex_ctrl.alu_fn\n div.io.req.bits.in1 := ex_rs(0)\n div.io.req.bits.in2 := ex_rs(1)\n div.io.req.bits.tag := ex_waddr\n val mul = pipelinedMul.option {\n val m = Module(new PipelinedMultiplier(xLen, 2))\n m.io.req.valid := ex_reg_valid && ex_ctrl.mul\n m.io.req.bits := div.io.req.bits\n m\n }\n\n ex_reg_valid := !ctrl_killd\n ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay\n ex_reg_xcpt := !ctrl_killd && id_xcpt\n ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt\n\n when (!ctrl_killd) {\n ex_ctrl := id_ctrl\n ex_reg_rvc := ibuf.io.inst(0).bits.rvc\n ex_ctrl.csr := id_csr\n when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B }\n when (id_fence_next) { id_reg_fence := true.B }\n when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr\n ex_ctrl.alu_fn := FN_ADD\n ex_ctrl.alu_dw := DW_XPR\n ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction\n ex_ctrl.sel_alu2 := A2_ZERO\n when (id_xcpt1.asUInt.orR) { // badaddr := PC+2\n ex_ctrl.sel_alu1 := A1_PC\n ex_ctrl.sel_alu2 := A2_SIZE\n ex_reg_rvc := true.B\n }\n when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC\n ex_ctrl.sel_alu1 := A1_PC\n ex_ctrl.sel_alu2 := A2_ZERO\n }\n }\n ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush\n ex_reg_load_use := id_load_use\n ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX)\n ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))\n when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) {\n ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U)\n }\n when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) {\n ex_ctrl.mem_cmd := M_HFENCEV\n }\n if (tile.dcache.flushOnFenceI) {\n when (id_ctrl.fence_i) {\n ex_reg_mem_size := 0.U\n }\n }\n\n for (i <- 0 until id_raddr.size) {\n val do_bypass = id_bypass_src(i).reduce(_||_)\n val bypass_src = PriorityEncoder(id_bypass_src(i))\n ex_reg_rs_bypass(i) := do_bypass\n ex_reg_rs_lsb(i) := bypass_src\n when (id_ren(i) && !do_bypass) {\n ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)\n ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)\n }\n }\n when (id_illegal_insn || id_virtual_insn) {\n val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))\n ex_reg_rs_bypass(0) := false.B\n ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)\n ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)\n }\n }\n when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {\n ex_reg_cause := id_cause\n ex_reg_inst := id_inst(0)\n ex_reg_raw_inst := id_raw_inst(0)\n ex_reg_pc := ibuf.io.pc\n ex_reg_btb_resp := ibuf.io.btb_resp\n ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) }\n ex_reg_set_vconfig := id_set_vconfig && !id_xcpt\n }\n\n // replay inst in ex stage?\n val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt\n val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid\n val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||\n ex_ctrl.div && !div.io.req.ready ||\n ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B)\n val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use\n val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use))\n val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid\n // detect 2-cycle load-use delay for LB/LH/SC\n val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U\n val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG)\n\n val (ex_xcpt, ex_cause) = checkExceptions(List(\n (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause)))\n\n val exCoverCauses = idCoverCauses\n coverExceptions(ex_xcpt, ex_cause, \"EXECUTE\", exCoverCauses)\n\n // memory stage\n val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt\n val mem_br_target = mem_reg_pc.asSInt +\n Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),\n Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),\n Mux(mem_reg_rvc, 2.S, 4.S)))\n val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt\n val mem_wrong_npc =\n Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,\n Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B))\n val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence\n val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt\n val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal\n val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal\n val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken)\n val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken\n take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence)\n\n mem_reg_valid := !ctrl_killx\n mem_reg_replay := !take_pc_mem_wb && replay_ex\n mem_reg_xcpt := !ctrl_killx && ex_xcpt\n mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt\n\n // on pipeline flushes, cause mem_npc to hold the sequential npc, which\n // will drive the W-stage npc mux\n when (mem_reg_valid && mem_reg_flush_pipe) {\n mem_reg_sfence := false.B\n }.elsewhen (ex_pc_valid) {\n mem_ctrl := ex_ctrl\n mem_reg_rvc := ex_reg_rvc\n mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)\n mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)\n mem_reg_sfence := ex_sfence\n mem_reg_btb_resp := ex_reg_btb_resp\n mem_reg_flush_pipe := ex_reg_flush_pipe\n mem_reg_slow_bypass := ex_slow_bypass\n mem_reg_wphit := ex_reg_wphit\n mem_reg_set_vconfig := ex_reg_set_vconfig\n\n mem_reg_cause := ex_cause\n mem_reg_inst := ex_reg_inst\n mem_reg_raw_inst := ex_reg_raw_inst\n mem_reg_mem_size := ex_reg_mem_size\n mem_reg_hls_or_dv := io.dmem.req.bits.dv\n mem_reg_pc := ex_reg_pc\n // IDecode ensured they are 1H\n mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out)\n mem_br_taken := alu.io.cmp_out\n\n\n when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {\n val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size)\n mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data\n }\n if (usingVector) { when (ex_reg_set_vconfig) {\n mem_reg_rs2 := ex_new_vconfig.get.asUInt\n } }\n when (ex_ctrl.jalr && csr.io.status.debug) {\n // flush I$ on D-mode JALR to effect uncached fetch without D$ flush\n mem_ctrl.fence_i := true.B\n mem_reg_flush_pipe := true.B\n }\n }\n\n val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)\n val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)\n val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(\n (mem_debug_breakpoint, CSR.debugTriggerCause.U),\n (mem_breakpoint, Causes.breakpoint.U)))\n\n val (mem_xcpt, mem_cause) = checkExceptions(List(\n (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),\n (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U),\n (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))\n\n val memCoverCauses = (exCoverCauses ++ List(\n (CSR.debugTriggerCause, \"DEBUG_TRIGGER\"),\n (Causes.breakpoint, \"BREAKPOINT\"),\n (Causes.misaligned_fetch, \"MISALIGNED_FETCH\")\n )).distinct\n coverExceptions(mem_xcpt, mem_cause, \"MEMORY\", memCoverCauses)\n\n val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port\n val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem\n val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B)\n val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B)\n val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all\n val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid\n div.io.kill := killm_common && RegNext(div.io.req.fire)\n val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem\n\n // writeback stage\n wb_reg_valid := !ctrl_killm\n wb_reg_replay := replay_mem && !take_pc_wb\n wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B)\n wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe\n when (mem_pc_valid) {\n wb_ctrl := mem_ctrl\n wb_reg_sfence := mem_reg_sfence\n wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)\n when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) {\n wb_reg_rs2 := mem_reg_rs2\n }\n wb_reg_cause := mem_cause\n wb_reg_inst := mem_reg_inst\n wb_reg_raw_inst := mem_reg_raw_inst\n wb_reg_mem_size := mem_reg_mem_size\n wb_reg_hls_or_dv := mem_reg_hls_or_dv\n wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV\n wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG\n wb_reg_pc := mem_reg_pc\n wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }\n wb_reg_set_vconfig := mem_reg_set_vconfig\n }\n\n val (wb_xcpt, wb_cause) = checkExceptions(List(\n (wb_reg_xcpt, wb_reg_cause),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U),\n (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U)\n ))\n\n val wbCoverCauses = List(\n (Causes.misaligned_store, \"MISALIGNED_STORE\"),\n (Causes.misaligned_load, \"MISALIGNED_LOAD\"),\n (Causes.store_access, \"STORE_ACCESS\"),\n (Causes.load_access, \"LOAD_ACCESS\")\n ) ++ (if(usingVM) List(\n (Causes.store_page_fault, \"STORE_PAGE_FAULT\"),\n (Causes.load_page_fault, \"LOAD_PAGE_FAULT\")\n ) else Nil) ++ (if (usingHypervisor) List(\n (Causes.store_guest_page_fault, \"STORE_GUEST_PAGE_FAULT\"),\n (Causes.load_guest_page_fault, \"LOAD_GUEST_PAGE_FAULT\"),\n ) else Nil)\n coverExceptions(wb_xcpt, wb_cause, \"WRITEBACK\", wbCoverCauses)\n\n val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt\n val wb_wxd = wb_reg_valid && wb_ctrl.wxd\n val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec\n val replay_wb_common = io.dmem.s2_nack || wb_reg_replay\n val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready\n val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall\n val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B)\n val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec\n take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe\n\n // writeback arbitration\n val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool\n val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool\n val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)\n val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data\n val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay\n\n class LLWB extends Bundle {\n val data = UInt(xLen.W)\n val tag = UInt(5.W)\n }\n\n val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec\n ll_arb.io.in.foreach(_.valid := false.B)\n ll_arb.io.in.foreach(_.bits := DontCare)\n val ll_wdata = WireInit(ll_arb.io.out.bits.data)\n val ll_waddr = WireInit(ll_arb.io.out.bits.tag)\n val ll_wen = WireInit(ll_arb.io.out.fire)\n ll_arb.io.out.ready := !wb_wxd\n\n div.io.resp.ready := ll_arb.io.in(0).ready\n ll_arb.io.in(0).valid := div.io.resp.valid\n ll_arb.io.in(0).bits.data := div.io.resp.bits.data\n ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag\n\n if (usingRoCC) {\n io.rocc.resp.ready := ll_arb.io.in(1).ready\n ll_arb.io.in(1).valid := io.rocc.resp.valid\n ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data\n ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd\n } else {\n // tie off RoCC\n io.rocc.resp.ready := false.B\n io.rocc.mem.req.ready := false.B\n }\n\n io.vector.map { v =>\n v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready)\n ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp\n ll_arb.io.in(2).bits.data := v.resp.bits.data\n ll_arb.io.in(2).bits.tag := v.resp.bits.rd\n }\n // Dont care mem since not all RoCC need accessing memory\n io.rocc.mem := DontCare\n\n when (dmem_resp_replay && dmem_resp_xpu) {\n ll_arb.io.out.ready := false.B\n ll_waddr := dmem_resp_waddr\n ll_wen := true.B\n }\n\n val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt\n val wb_wen = wb_valid && wb_ctrl.wxd\n val rf_wen = wb_wen || ll_wen\n val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)\n val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),\n Mux(ll_wen, ll_wdata,\n Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,\n Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata),\n wb_reg_wdata))))\n when (rf_wen) { rf.write(rf_waddr, rf_wdata) }\n\n // hook up control/status regfile\n csr.io.ungated_clock := clock\n csr.io.decode(0).inst := id_inst(0)\n csr.io.exception := wb_xcpt\n csr.io.cause := wb_cause\n csr.io.retire := wb_valid\n csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst)\n csr.io.interrupts := io.interrupts\n csr.io.hartid := io.hartid\n io.fpu.fcsr_rm := csr.io.fcsr_rm\n val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W))\n val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B)\n csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid\n csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid))\n io.fpu.time := csr.io.time(31,0)\n io.fpu.hartid := io.hartid\n csr.io.rocc_interrupt := io.rocc.interrupt\n csr.io.pc := wb_reg_pc\n\n val tval_dmem_addr = !wb_reg_xcpt\n val tval_any_addr = tval_dmem_addr ||\n wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U)\n val tval_inst = wb_reg_cause === Causes.illegal_instruction.U\n val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)\n csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)\n csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)\n val (htval, mhtinst_read_pseudo) = {\n val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U\n val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)\n assert(!htval_valid_imem || io.imem.gpa.valid)\n\n val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR\n val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)\n\n val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits\n // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation\n val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)\n (htval, mhtinst_read_pseudo)\n }\n\n csr.io.vector.foreach { v =>\n v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid\n v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig)\n v.set_vs_dirty := wb_valid && wb_ctrl.vec\n v.set_vstart.valid := wb_valid && wb_reg_set_vconfig\n v.set_vstart.bits := 0.U\n }\n\n io.vector.foreach { v =>\n when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) {\n csr.io.pc := v.wb.pc\n csr.io.retire := v.wb.retire\n csr.io.inst(0) := v.wb.inst\n when (v.wb.xcpt && !wb_reg_xcpt) {\n wb_xcpt := true.B\n wb_cause := v.wb.cause\n csr.io.tval := v.wb.tval\n }\n }\n v.wb.store_pending := io.dmem.store_pending\n v.wb.vxrm := csr.io.vector.get.vxrm\n v.wb.frm := csr.io.fcsr_rm\n csr.io.vector.get.set_vxsat := v.set_vxsat\n when (v.set_vconfig.valid) {\n csr.io.vector.get.set_vconfig.valid := true.B\n csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits\n }\n when (v.set_vstart.valid) {\n csr.io.vector.get.set_vstart.valid := true.B\n csr.io.vector.get.set_vstart.bits := v.set_vstart.bits\n }\n }\n\n csr.io.htval := htval\n csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo\n io.ptw.ptbr := csr.io.ptbr\n io.ptw.hgatp := csr.io.hgatp\n io.ptw.vsatp := csr.io.vsatp\n (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }\n io.ptw.status := csr.io.status\n io.ptw.hstatus := csr.io.hstatus\n io.ptw.gstatus := csr.io.gstatus\n io.ptw.pmp := csr.io.pmp\n csr.io.rw.addr := wb_reg_inst(31,20)\n csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)\n csr.io.rw.wdata := wb_reg_wdata\n\n\n io.rocc.csrs <> csr.io.roccCSRs\n io.trace.time := csr.io.time\n io.trace.insns := csr.io.trace\n if (rocketParams.debugROB.isDefined) {\n val sz = rocketParams.debugROB.get.size\n if (sz < 1) { // use unsynthesizable ROB\n val csr_trace_with_wdata = WireInit(csr.io.trace(0))\n csr_trace_with_wdata.wdata.get := rf_wdata\n val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception)\n val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)\n val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))\n\n io.vector.foreach { v => when (v.wb.retire) {\n should_wb := v.wb.rob_should_wb\n has_wb := false.B\n wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))\n }}\n\n DebugROB.pushTrace(clock, reset,\n io.hartid, csr_trace_with_wdata,\n should_wb, has_wb, wb_addr)\n\n io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)\n\n DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)\n } else { // synthesizable ROB (no FPRs)\n require(!usingVector, \"Synthesizable ROB does not support vector implementations\")\n val csr_trace_with_wdata = WireInit(csr.io.trace(0))\n csr_trace_with_wdata.wdata.get := rf_wdata\n\n val debug_rob = Module(new HardDebugROB(sz, 32))\n debug_rob.io.i_insn := csr_trace_with_wdata\n debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&\n !csr.io.trace(0).exception\n debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard\n debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)\n\n debug_rob.io.wb_val := ll_wen\n debug_rob.io.wb_tag := rf_waddr\n debug_rob.io.wb_data := rf_wdata\n\n io.trace.insns(0) := debug_rob.io.o_insn\n }\n } else {\n io.trace.insns := csr.io.trace\n }\n for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {\n iobpw.valid(0) := wphit\n iobpw.action := bp.control.action\n // tie off bpwatch valids\n iobpw.rvalid.foreach(_ := false.B)\n iobpw.wvalid.foreach(_ := false.B)\n iobpw.ivalid.foreach(_ := false.B)\n }\n\n val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1),\n (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2),\n (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr))\n val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),\n (io.fpu.dec.ren2, id_raddr2),\n (io.fpu.dec.ren3, id_raddr3),\n (io.fpu.dec.wen, id_waddr))\n\n val sboard = new Scoreboard(32, true)\n sboard.clear(ll_wen, ll_waddr)\n def id_sboard_clear_bypass(r: UInt) = {\n // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check\n if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r\n else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r\n }\n val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))\n sboard.set(wb_set_sboard && wb_wen, wb_waddr)\n\n // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.\n val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec\n val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)\n val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)\n val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)\n\n // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.\n val mem_mem_cmd_bh =\n if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass\n else true.B\n val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec\n val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)\n val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)\n val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)\n id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem\n val id_vconfig_hazard = id_ctrl.vec && (\n (ex_reg_valid && ex_reg_set_vconfig) ||\n (mem_reg_valid && mem_reg_set_vconfig) ||\n (wb_reg_valid && wb_reg_set_vconfig))\n\n // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.\n val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)\n val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)\n val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)\n\n val id_stall_fpu = if (usingFPU) {\n val fp_sboard = new Scoreboard(32)\n fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)\n val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B)\n fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag)\n fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)\n\n checkHazards(fp_hazard_targets, fp_sboard.read _)\n } else false.B\n\n val dcache_blocked = {\n // speculate that a blocked D$ will unblock the cycle after a Grant\n val blocked = Reg(Bool())\n blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack)\n blocked && !io.dmem.perf.grant\n }\n val rocc_blocked = Reg(Bool())\n rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked)\n\n val ctrl_stalld =\n id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||\n id_vconfig_hazard ||\n csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) ||\n id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy ||\n id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy ||\n id_ctrl.fp && id_stall_fpu ||\n id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses\n id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy\n id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay\n !clock_en ||\n id_do_fence ||\n csr.io.csr_stall ||\n id_reg_pause ||\n io.traceStall\n ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt\n\n io.imem.req.valid := take_pc\n io.imem.req.bits.speculative := !take_pc_wb\n io.imem.req.bits.pc :=\n Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret\n Mux(replay_wb, wb_reg_pc, // replay\n mem_npc)) // flush or branch misprediction\n io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack\n io.imem.might_request := {\n imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B)\n imem_might_request_reg\n }\n io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common)\n io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence\n io.imem.sfence.bits.rs1 := wb_reg_mem_size(0)\n io.imem.sfence.bits.rs2 := wb_reg_mem_size(1)\n io.imem.sfence.bits.addr := wb_reg_wdata\n io.imem.sfence.bits.asid := wb_reg_rs2\n io.imem.sfence.bits.hv := wb_reg_hfence_v\n io.imem.sfence.bits.hg := wb_reg_hfence_g\n io.ptw.sfence := io.imem.sfence\n\n ibuf.io.inst(0).ready := !ctrl_stalld\n\n io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)\n io.imem.btb_update.bits.isValid := mem_cfi\n io.imem.btb_update.bits.cfiType :=\n Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,\n Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat(\"b00?01\"), CFIType.ret,\n Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump,\n CFIType.branch)))\n io.imem.btb_update.bits.target := io.imem.req.bits.pc\n io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc)\n io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U)\n io.imem.btb_update.bits.prediction := mem_reg_btb_resp\n io.imem.btb_update.bits.taken := DontCare\n\n io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb\n io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc\n io.imem.bht_update.bits.taken := mem_br_taken\n io.imem.bht_update.bits.mispredict := mem_wrong_npc\n io.imem.bht_update.bits.branch := mem_ctrl.branch\n io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht\n\n // Connect RAS in Frontend\n io.imem.ras_update := DontCare\n\n io.fpu.valid := !ctrl_killd && id_ctrl.fp\n io.fpu.killx := ctrl_killx\n io.fpu.killm := killm_common\n io.fpu.inst := id_inst(0)\n io.fpu.fromint_data := ex_rs(0)\n io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu\n io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data)\n io.fpu.ll_resp_type := io.dmem.resp.bits.size\n io.fpu.ll_resp_tag := dmem_resp_waddr\n io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate\n\n io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U)\n\n io.vector.map { v =>\n when (!(dmem_resp_valid && dmem_resp_fpu)) {\n io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp\n io.fpu.ll_resp_data := v.resp.bits.data\n io.fpu.ll_resp_type := v.resp.bits.size\n io.fpu.ll_resp_tag := v.resp.bits.rd\n }\n }\n\n io.vector.foreach { v =>\n v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx\n v.ex.inst := ex_reg_inst\n v.ex.vconfig := csr.io.vector.get.vconfig\n v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart)\n v.ex.rs1 := ex_rs(0)\n v.ex.rs2 := ex_rs(1)\n v.ex.pc := ex_reg_pc\n v.mem.frs1 := io.fpu.store_data\n v.killm := killm_common\n v.status := csr.io.status\n }\n\n\n io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem\n val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)\n require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth)\n io.dmem.req.bits.tag := ex_dcache_tag\n io.dmem.req.bits.cmd := ex_ctrl.mem_cmd\n io.dmem.req.bits.size := ex_reg_mem_size\n io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))\n io.dmem.req.bits.phys := false.B\n io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)\n io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)\n io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)\n io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv\n io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)\n io.dmem.req.bits.no_alloc := DontCare\n io.dmem.req.bits.no_xcpt := DontCare\n io.dmem.req.bits.data := DontCare\n io.dmem.req.bits.mask := DontCare\n\n io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2))\n io.dmem.s1_data.mask := DontCare\n\n io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem\n io.dmem.s2_kill := false.B\n // don't let D$ go to sleep if we're probably going to use it soon\n io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall\n\n io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common\n io.rocc.exception := wb_xcpt && csr.io.status.xs.orR\n io.rocc.cmd.bits.status := csr.io.status\n io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction())\n io.rocc.cmd.bits.rs1 := wb_reg_wdata\n io.rocc.cmd.bits.rs2 := wb_reg_rs2\n\n // gate the clock\n val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc\n when (unpause) { id_reg_pause := false.B }\n io.cease := csr.io.status.cease && !clock_en_reg\n io.wfi := csr.io.status.wfi\n if (rocketParams.clockGate) {\n long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause\n clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid)\n clock_en_reg :=\n ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight\n io.ptw.customCSRs.disableCoreClockGate || // chicken bit\n !div.io.req.ready || // mul/div in flight\n usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight\n io.dmem.replay_next || // long-latency load replaying\n (!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending\n\n assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en)\n }\n\n // evaluate performance counters\n val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))\n csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }\n\n val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))\n\n coreMonitorBundle.clock := clock\n coreMonitorBundle.reset := reset\n coreMonitorBundle.hartid := io.hartid\n coreMonitorBundle.timer := csr.io.time(31,0)\n coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception\n coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen)\n coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard\n coreMonitorBundle.wrenf := false.B\n coreMonitorBundle.wrdst := wb_waddr\n coreMonitorBundle.wrdata := rf_wdata\n coreMonitorBundle.rd0src := wb_reg_inst(19,15)\n coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0)))\n coreMonitorBundle.rd1src := wb_reg_inst(24,20)\n coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1)))\n coreMonitorBundle.inst := csr.io.trace(0).insn\n coreMonitorBundle.excpt := csr.io.trace(0).exception\n coreMonitorBundle.priv_mode := csr.io.trace(0).priv\n\n if (enableCommitLog) {\n val t = csr.io.trace(0)\n val rd = wb_waddr\n val wfd = wb_ctrl.wfd\n val wxd = wb_ctrl.wxd\n val has_data = wb_wen && !wb_set_sboard\n\n when (t.valid && !t.exception) {\n when (wfd) {\n printf (\"%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\\n\", t.priv, t.iaddr, t.insn, rd, rd+32.U)\n }\n .elsewhen (wxd && rd =/= 0.U && has_data) {\n printf (\"%d 0x%x (0x%x) x%d 0x%x\\n\", t.priv, t.iaddr, t.insn, rd, rf_wdata)\n }\n .elsewhen (wxd && rd =/= 0.U && !has_data) {\n printf (\"%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\\n\", t.priv, t.iaddr, t.insn, rd, rd)\n }\n .otherwise {\n printf (\"%d 0x%x (0x%x)\\n\", t.priv, t.iaddr, t.insn)\n }\n }\n\n when (ll_wen && rf_waddr =/= 0.U) {\n printf (\"x%d p%d 0x%x\\n\", rf_waddr, rf_waddr, rf_wdata)\n }\n }\n else {\n when (csr.io.trace(0).valid) {\n printf(\"C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\\n\",\n io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,\n coreMonitorBundle.pc,\n Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),\n Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),\n coreMonitorBundle.wrenx,\n Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),\n Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),\n Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),\n Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),\n coreMonitorBundle.inst, coreMonitorBundle.inst)\n }\n }\n\n // CoreMonitorBundle for late latency writes\n val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen))\n\n xrfWriteBundle.clock := clock\n xrfWriteBundle.reset := reset\n xrfWriteBundle.hartid := io.hartid\n xrfWriteBundle.timer := csr.io.time(31,0)\n xrfWriteBundle.valid := false.B\n xrfWriteBundle.pc := 0.U\n xrfWriteBundle.wrdst := rf_waddr\n xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr))\n xrfWriteBundle.wrenf := false.B\n xrfWriteBundle.wrdata := rf_wdata\n xrfWriteBundle.rd0src := 0.U\n xrfWriteBundle.rd0val := 0.U\n xrfWriteBundle.rd1src := 0.U\n xrfWriteBundle.rd1val := 0.U\n xrfWriteBundle.inst := 0.U\n xrfWriteBundle.excpt := false.B\n xrfWriteBundle.priv_mode := csr.io.trace(0).priv\n\n if (rocketParams.haveSimTimeout) PlusArg.timeout(\n name = \"max_core_cycles\",\n docstring = \"Kill the emulation after INT rdtime cycles. Off if 0.\"\n )(csr.io.time)\n\n } // leaving gated-clock domain\n val rocketImpl = withClock (gated_clock) { new RocketImpl }\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x)))\n\n def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = {\n for ((coverCause, label) <- coverCausesLabels) {\n property.cover(exceptionValid && (cause === coverCause.U), s\"${labelPrefix}_${label}\")\n }\n }\n\n def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =\n targets.map(h => h._1 && cond(h._2)).reduce(_||_)\n\n def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {\n // efficient means to compress 64-bit VA into vaddrBits+1 bits\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))\n val b = vaddrBitsExtended-1\n val a = (a0 >> b).asSInt\n val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))\n Cat(msb, ea(b-1, 0))\n }\n\n class Scoreboard(n: Int, zero: Boolean = false)\n {\n def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))\n def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))\n def read(addr: UInt): Bool = r(addr)\n def readBypassed(addr: UInt): Bool = _next(addr)\n\n private val _r = RegInit(0.U(n.W))\n private val r = if (zero) (_r >> 1 << 1) else _r\n private var _next = r\n private var ens = false.B\n private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U)\n private def update(en: Bool, update: UInt) = {\n _next = update\n ens = ens || en\n when (ens) { _r := _next }\n }\n }\n}\n\nclass RegFile(n: Int, w: Int, zero: Boolean = false) {\n val rf = Mem(n, UInt(w.W))\n private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))\n private val reads = ArrayBuffer[(UInt,UInt)]()\n private var canRead = true\n def read(addr: UInt) = {\n require(canRead)\n reads += addr -> Wire(UInt())\n reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr))\n reads.last._2\n }\n def write(addr: UInt, data: UInt) = {\n canRead = false\n when (addr =/= 0.U) {\n access(addr) := data\n for ((raddr, rdata) <- reads)\n when (addr === raddr) { rdata := data }\n }\n }\n}\n\nobject ImmGen {\n def apply(sel: UInt, inst: UInt) = {\n val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)\n val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)\n val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt)\n val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,\n Mux(sel === IMM_UJ, inst(20).asSInt,\n Mux(sel === IMM_SB, inst(7).asSInt, sign)))\n val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))\n val b4_1 = Mux(sel === IMM_U, 0.U,\n Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),\n Mux(sel === IMM_Z, inst(19,16), inst(24,21))))\n val b0 = Mux(sel === IMM_S, inst(7),\n Mux(sel === IMM_I, inst(20),\n Mux(sel === IMM_Z, inst(15), 0.U)))\n\n Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt\n }\n}", + "response": "module rf_31x64(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [4:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [63:0] R1_data,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n reg [63:0] Memory[0:30];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 64'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRecFM_small_e11_s53(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input [64:0] io_a,\n input [64:0] io_b,\n input [2:0] io_roundingMode,\n output io_outValid_div,\n output io_outValid_sqrt,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;\n wire _divSqrtRecFNToRaw_io_invalidExc;\n wire _divSqrtRecFNToRaw_io_infiniteExc;\n wire _divSqrtRecFNToRaw_io_rawOut_isNaN;\n wire _divSqrtRecFNToRaw_io_rawOut_isInf;\n wire _divSqrtRecFNToRaw_io_rawOut_isZero;\n wire _divSqrtRecFNToRaw_io_rawOut_sign;\n wire [12:0] _divSqrtRecFNToRaw_io_rawOut_sExp;\n wire [55:0] _divSqrtRecFNToRaw_io_rawOut_sig;\n DivSqrtRecFMToRaw_small_e11_s53 divSqrtRecFNToRaw (\n .clock (clock),\n .reset (reset),\n .io_inReady (io_inReady),\n .io_inValid (io_inValid),\n .io_sqrtOp (io_sqrtOp),\n .io_a (io_a),\n .io_b (io_b),\n .io_roundingMode (io_roundingMode),\n .io_rawOutValid_div (io_outValid_div),\n .io_rawOutValid_sqrt (io_outValid_sqrt),\n .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e11_s53 roundRawFNToRecFN (\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),\n .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw10_f32_TestHarness_UNIQUIFIED(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_head = io_in_bits_flit[1];\n assign io_out_bits_tail = io_in_bits_flit[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n// See LICENSE.Berkeley for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3.{dontTouch, _}\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.bundlebridge._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.amba.AMBAProtField\nimport freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType}\nimport freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters}\nimport freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata}\nimport freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle}\n\nimport freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt}\n\nimport scala.collection.mutable.ListBuffer\n\ncase class DCacheParams(\n nSets: Int = 64,\n nWays: Int = 4,\n rowBits: Int = 64,\n subWordBits: Option[Int] = None,\n replacementPolicy: String = \"random\",\n nTLBSets: Int = 1,\n nTLBWays: Int = 32,\n nTLBBasePageSectors: Int = 4,\n nTLBSuperpages: Int = 4,\n tagECC: Option[String] = None,\n dataECC: Option[String] = None,\n dataECCBytes: Int = 1,\n nMSHRs: Int = 1,\n nSDQ: Int = 17,\n nRPQ: Int = 16,\n nMMIOs: Int = 1,\n blockBytes: Int = 64,\n separateUncachedResp: Boolean = false,\n acquireBeforeRelease: Boolean = false,\n pipelineWayMux: Boolean = false,\n clockGate: Boolean = false,\n scratch: Option[BigInt] = None) extends L1CacheParams {\n\n def tagCode: Code = Code.fromString(tagECC)\n def dataCode: Code = Code.fromString(dataECC)\n\n def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)\n\n def replacement = new RandomReplacement(nWays)\n\n def silentDrop: Boolean = !acquireBeforeRelease\n\n require((!scratch.isDefined || nWays == 1),\n \"Scratchpad only allowed in direct-mapped cache.\")\n require((!scratch.isDefined || nMSHRs == 0),\n \"Scratchpad only allowed in blocking cache.\")\n if (scratch.isEmpty)\n require(isPow2(nSets), s\"nSets($nSets) must be pow2\")\n}\n\ntrait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {\n val cacheParams = tileParams.dcache.get\n val cfg = cacheParams\n\n def wordBits = coreDataBits\n def wordBytes = coreDataBytes\n def subWordBits = cacheParams.subWordBits.getOrElse(wordBits)\n def subWordBytes = subWordBits / 8\n def wordOffBits = log2Up(wordBytes)\n def beatBytes = cacheBlockBytes / cacheDataBeats\n def beatWords = beatBytes / wordBytes\n def beatOffBits = log2Up(beatBytes)\n def idxMSB = untagBits-1\n def idxLSB = blockOffBits\n def offsetmsb = idxLSB-1\n def offsetlsb = wordOffBits\n def rowWords = rowBits/wordBits\n def doNarrowRead = coreDataBits * nWays % rowBits == 0\n def eccBytes = cacheParams.dataECCBytes\n val eccBits = cacheParams.dataECCBytes * 8\n val encBits = cacheParams.dataCode.width(eccBits)\n val encWordBits = encBits * (wordBits / eccBits)\n def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only\n def encRowBits = encDataBits*rowWords\n def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed\n def lrscBackoff = 3 // disallow LRSC reacquisition briefly\n def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant\n def nIOMSHRs = cacheParams.nMMIOs\n def maxUncachedInFlight = cacheParams.nMMIOs\n def dataScratchpadSize = cacheParams.dataScratchpadBytes\n\n require(rowBits >= coreDataBits, s\"rowBits($rowBits) < coreDataBits($coreDataBits)\")\n if (!usingDataScratchpad)\n require(rowBits == cacheDataBits, s\"rowBits($rowBits) != cacheDataBits($cacheDataBits)\")\n // would need offset addr for puts if data width < xlen\n require(xLen <= cacheDataBits, s\"xLen($xLen) > cacheDataBits($cacheDataBits)\")\n}\n\nabstract class L1HellaCacheModule(implicit val p: Parameters) extends Module\n with HasL1HellaCacheParameters\n\nabstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)\n with HasL1HellaCacheParameters\n\n/** Bundle definitions for HellaCache interfaces */\n\ntrait HasCoreMemOp extends HasL1HellaCacheParameters {\n val addr = UInt(coreMaxAddrBits.W)\n val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W))\n val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W)\n val cmd = UInt(M_SZ.W)\n val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W)\n val signed = Bool()\n val dprv = UInt(PRV.SZ.W)\n val dv = Bool()\n}\n\ntrait HasCoreData extends HasCoreParameters {\n val data = UInt(coreDataBits.W)\n val mask = UInt(coreDataBytes.W)\n}\n\nclass HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {\n val phys = Bool()\n val no_resp = Bool() // The dcache may omit generating a response for this request\n val no_alloc = Bool()\n val no_xcpt = Bool()\n}\n\nclass HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData\n\nclass HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)\n with HasCoreMemOp\n with HasCoreData {\n val replay = Bool()\n val has_data = Bool()\n val data_word_bypass = UInt(coreDataBits.W)\n val data_raw = UInt(coreDataBits.W)\n val store_data = UInt(coreDataBits.W)\n}\n\nclass AlignmentExceptions extends Bundle {\n val ld = Bool()\n val st = Bool()\n}\n\nclass HellaCacheExceptions extends Bundle {\n val ma = new AlignmentExceptions\n val pf = new AlignmentExceptions\n val gf = new AlignmentExceptions\n val ae = new AlignmentExceptions\n}\n\nclass HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData\n\nclass HellaCachePerfEvents extends Bundle {\n val acquire = Bool()\n val release = Bool()\n val grant = Bool()\n val tlbMiss = Bool()\n val blocked = Bool()\n val canAcceptStoreThenLoad = Bool()\n val canAcceptStoreThenRMW = Bool()\n val canAcceptLoadThenLoad = Bool()\n val storeBufferEmptyAfterLoad = Bool()\n val storeBufferEmptyAfterStore = Bool()\n}\n\n// interface between D$ and processor/DTLB\nclass HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {\n val req = Decoupled(new HellaCacheReq)\n val s1_kill = Output(Bool()) // kill previous cycle's req\n val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req\n val s2_nack = Input(Bool()) // req from two cycles ago is rejected\n val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint)\n val s2_kill = Output(Bool()) // kill req from two cycles ago\n val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO\n val s2_paddr = Input(UInt(paddrBits.W)) // translated address\n\n val resp = Flipped(Valid(new HellaCacheResp))\n val replay_next = Input(Bool())\n val s2_xcpt = Input(new HellaCacheExceptions)\n val s2_gpa = Input(UInt(vaddrBitsExtended.W))\n val s2_gpa_is_pte = Input(Bool())\n val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))\n val ordered = Input(Bool())\n val store_pending = Input(Bool()) // there is a store in a store buffer somewhere\n val perf = Input(new HellaCachePerfEvents())\n\n val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?\n val clock_enabled = Input(Bool()) // is D$ currently being clocked?\n}\n\n/** Base classes for Diplomatic TL2 HellaCaches */\n\nabstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule\n with HasNonDiplomaticTileParameters {\n protected val cfg = tileParams.dcache.get\n\n protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(\n name = s\"Core ${tileId} DCache\",\n sourceId = IdRange(0, 1 max cfg.nMSHRs),\n supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))\n\n protected def mmioClientParameters = Seq(TLMasterParameters.v1(\n name = s\"Core ${tileId} DCache MMIO\",\n sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),\n requestFifo = true))\n\n def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max\n\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(\n clients = cacheClientParameters ++ mmioClientParameters,\n minLatency = 1,\n requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField())))))\n\n val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())\n val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())\n\n val module: HellaCacheModule\n\n def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)\n\n def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits)\n\n require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, \"CFLUSH_D_L1 instruction requires a D$\")\n}\n\nclass HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {\n val cpu = Flipped(new HellaCacheIO)\n val ptw = new TLBPTWIO()\n val errors = new DCacheErrors\n val tlb_port = new DCacheTLBPort\n}\n\nclass HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)\n with HasL1HellaCacheParameters {\n implicit val edge: TLEdgeOut = outer.node.edges.out(0)\n val (tl_out, _) = outer.node.out(0)\n val io = IO(new HellaCacheBundle)\n val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle)\n val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle)\n dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals\n dontTouch(io.cpu.s1_data)\n\n require(rowBits == edge.bundle.dataBits)\n\n private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)\n fifoManagers.foreach { m =>\n require (m.fifoId == fifoManagers.head.fifoId,\n s\"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\\n\"+\n s\"${m.nodePath.map(_.name)}\\nversus\\n${fifoManagers.head.nodePath.map(_.name)}\")\n }\n}\n\n/** Support overriding which HellaCache is instantiated */\n\ncase object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply)\n\nobject HellaCacheFactory {\n def apply(tile: BaseTile)(p: Parameters): HellaCache = {\n if (tile.tileParams.dcache.get.nMSHRs == 0)\n new DCache(tile.tileId, tile.crossing)(p)\n else\n new NonBlockingDCache(tile.tileId)(p)\n }\n}\n\n/** Mix-ins for constructing tiles that have a HellaCache */\n\ntrait HasHellaCache { this: BaseTile =>\n val module: HasHellaCacheModule\n implicit val p: Parameters\n var nDCachePorts = 0\n lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p))\n\n tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node\n dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }\n dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }\n InModuleBody {\n dcache.module.io.tlb_port := DontCare\n }\n}\n\ntrait HasHellaCacheModule {\n val outer: HasHellaCache with HasTileParameters\n implicit val p: Parameters\n val dcachePorts = ListBuffer[HellaCacheIO]()\n val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))\n outer.dcache.module.io.cpu <> dcacheArb.io.mem\n}\n\n/** Metadata array used for all HellaCaches */\n\nclass L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {\n val coh = new ClientMetadata\n val tag = UInt(tagBits.W)\n}\n\nobject L1Metadata {\n def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {\n val meta = Wire(new L1Metadata)\n meta.tag := tag\n meta.coh := coh\n meta\n }\n}\n\nclass L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {\n val idx = UInt(idxBits.W)\n val way_en = UInt(nWays.W)\n val tag = UInt(tagBits.W)\n}\n\nclass L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {\n val data = new L1Metadata\n}\n\nclass L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {\n val rstVal = onReset()\n val io = IO(new Bundle {\n val read = Flipped(Decoupled(new L1MetaReadReq))\n val write = Flipped(Decoupled(new L1MetaWriteReq))\n val resp = Output(Vec(nWays, rstVal.cloneType))\n })\n\n val rst_cnt = RegInit(0.U(log2Up(nSets+1).W))\n val rst = rst_cnt < nSets.U\n val waddr = Mux(rst, rst_cnt, io.write.bits.idx)\n val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt\n val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools\n val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools\n when (rst) { rst_cnt := rst_cnt+1.U }\n\n val metabits = rstVal.getWidth\n val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W)))\n val wen = rst || io.write.valid\n when (wen) {\n tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)\n }\n io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))\n\n io.read.ready := !wen // so really this could be a 6T RAM\n io.write.ready := !rst\n}", + "response": "module L1MetadataArray(\n input clock,\n input reset,\n output io_read_ready,\n input io_read_valid,\n input [5:0] io_read_bits_idx,\n output io_write_ready,\n input io_write_valid,\n input [5:0] io_write_bits_idx,\n input [3:0] io_write_bits_way_en,\n input [1:0] io_write_bits_data_coh_state,\n input [19:0] io_write_bits_data_tag,\n output [1:0] io_resp_0_coh_state,\n output [19:0] io_resp_0_tag,\n output [1:0] io_resp_1_coh_state,\n output [19:0] io_resp_1_tag,\n output [1:0] io_resp_2_coh_state,\n output [19:0] io_resp_2_tag,\n output [1:0] io_resp_3_coh_state,\n output [19:0] io_resp_3_tag\n);\n\n wire tag_array_MPORT_1_en;\n wire wen;\n wire [87:0] _tag_array_RW0_rdata;\n reg [6:0] rst_cnt;\n wire [1:0] _wdata_T_coh_state = rst_cnt[6] ? io_write_bits_data_coh_state : 2'h0;\n wire [19:0] _wdata_T_tag = rst_cnt[6] ? io_write_bits_data_tag : 20'h0;\n assign wen = ~(rst_cnt[6]) | io_write_valid;\n assign tag_array_MPORT_1_en = ~wen & io_read_valid;\n always @(posedge clock) begin\n if (reset)\n rst_cnt <= 7'h0;\n else if (rst_cnt[6]) begin\n end\n else\n rst_cnt <= rst_cnt + 7'h1;\n end\n tag_array tag_array (\n .RW0_addr (wen ? (rst_cnt[6] ? io_write_bits_idx : rst_cnt[5:0]) : io_read_bits_idx),\n .RW0_en (tag_array_MPORT_1_en | wen),\n .RW0_clk (clock),\n .RW0_wmode (wen),\n .RW0_wdata ({_wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag, _wdata_T_coh_state, _wdata_T_tag}),\n .RW0_rdata (_tag_array_RW0_rdata),\n .RW0_wmask (rst_cnt[6] ? io_write_bits_way_en : 4'hF)\n );\n assign io_read_ready = ~wen;\n assign io_write_ready = rst_cnt[6];\n assign io_resp_0_coh_state = _tag_array_RW0_rdata[21:20];\n assign io_resp_0_tag = _tag_array_RW0_rdata[19:0];\n assign io_resp_1_coh_state = _tag_array_RW0_rdata[43:42];\n assign io_resp_1_tag = _tag_array_RW0_rdata[41:22];\n assign io_resp_2_coh_state = _tag_array_RW0_rdata[65:64];\n assign io_resp_2_tag = _tag_array_RW0_rdata[63:44];\n assign io_resp_3_coh_state = _tag_array_RW0_rdata[87:86];\n assign io_resp_3_tag = _tag_array_RW0_rdata[85:66];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}\nimport freechips.rocketchip.util._\n\nimport ALU._\n\nclass MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {\n val fn = Bits(SZ_ALU_FN.W)\n val dw = Bits(SZ_DW.W)\n val in1 = Bits(dataBits.W)\n val in2 = Bits(dataBits.W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierResp(dataBits: Int, tagBits: Int) extends Bundle {\n val data = Bits(dataBits.W)\n val full_data = Bits((2*dataBits).W)\n val tag = UInt(tagBits.W)\n}\n\nclass MultiplierIO(val dataBits: Int, val tagBits: Int) extends Bundle {\n val req = Flipped(Decoupled(new MultiplierReq(dataBits, tagBits)))\n val kill = Input(Bool())\n val resp = Decoupled(new MultiplierResp(dataBits, tagBits))\n}\n\ncase class MulDivParams(\n mulUnroll: Int = 1,\n divUnroll: Int = 1,\n mulEarlyOut: Boolean = false,\n divEarlyOut: Boolean = false,\n divEarlyOutGranularity: Int = 1\n)\n\nclass MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32) extends Module {\n private def minDivLatency = (cfg.divUnroll > 0).option(if (cfg.divEarlyOut) 3 else 1 + w/cfg.divUnroll)\n private def minMulLatency = (cfg.mulUnroll > 0).option(if (cfg.mulEarlyOut) 2 else w/cfg.mulUnroll)\n def minLatency: Int = (minDivLatency ++ minMulLatency).min\n\n val io = IO(new MultiplierIO(width, log2Up(nXpr)))\n val w = io.req.bits.in1.getWidth\n val mulw = if (cfg.mulUnroll == 0) w else (w + cfg.mulUnroll - 1) / cfg.mulUnroll * cfg.mulUnroll\n val fastMulW = if (cfg.mulUnroll == 0) false else w/2 > cfg.mulUnroll && w % (2*cfg.mulUnroll) == 0\n \n val s_ready :: s_neg_inputs :: s_mul :: s_div :: s_dummy :: s_neg_output :: s_done_mul :: s_done_div :: Nil = Enum(8)\n val state = RegInit(s_ready)\n \n val req = Reg(chiselTypeOf(io.req.bits))\n val count = Reg(UInt(log2Ceil(\n ((cfg.divUnroll != 0).option(w/cfg.divUnroll + 1).toSeq ++\n (cfg.mulUnroll != 0).option(mulw/cfg.mulUnroll)).reduce(_ max _)).W))\n val neg_out = Reg(Bool())\n val isHi = Reg(Bool())\n val resHi = Reg(Bool())\n val divisor = Reg(Bits((w+1).W)) // div only needs w bits\n val remainder = Reg(Bits((2*mulw+2).W)) // div only needs 2*w+1 bits\n\n val mulDecode = List(\n FN_MUL -> List(Y, N, X, X),\n FN_MULH -> List(Y, Y, Y, Y),\n FN_MULHU -> List(Y, Y, N, N),\n FN_MULHSU -> List(Y, Y, Y, N))\n val divDecode = List(\n FN_DIV -> List(N, N, Y, Y),\n FN_REM -> List(N, Y, Y, Y),\n FN_DIVU -> List(N, N, N, N),\n FN_REMU -> List(N, Y, N, N))\n val cmdMul :: cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(io.req.bits.fn, List(X, X, X, X),\n (if (cfg.divUnroll != 0) divDecode else Nil) ++ (if (cfg.mulUnroll != 0) mulDecode else Nil)).map(_.asBool)\n\n require(w == 32 || w == 64)\n def halfWidth(req: MultiplierReq) = (w > 32).B && req.dw === DW_32\n\n def sext(x: Bits, halfW: Bool, signed: Bool) = {\n val sign = signed && Mux(halfW, x(w/2-1), x(w-1))\n val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))\n (Cat(hi, x(w/2-1,0)), sign)\n }\n val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)\n val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)\n \n val subtractor = remainder(2*w,w) - divisor\n val result = Mux(resHi, remainder(2*w, w+1), remainder(w-1, 0))\n val negated_remainder = -result\n\n if (cfg.divUnroll != 0) when (state === s_neg_inputs) {\n when (remainder(w-1)) {\n remainder := negated_remainder\n }\n when (divisor(w-1)) {\n divisor := subtractor\n }\n state := s_div\n }\n if (cfg.divUnroll != 0) when (state === s_neg_output) {\n remainder := negated_remainder\n state := s_done_div\n resHi := false.B\n }\n if (cfg.mulUnroll != 0) when (state === s_mul) {\n val mulReg = Cat(remainder(2*mulw+1,w+1),remainder(w-1,0))\n val mplierSign = remainder(w)\n val mplier = mulReg(mulw-1,0)\n val accum = mulReg(2*mulw,mulw).asSInt\n val mpcand = divisor.asSInt\n val prod = Cat(mplierSign, mplier(cfg.mulUnroll-1, 0)).asSInt * mpcand + accum\n val nextMulReg = Cat(prod, mplier(mulw-1, cfg.mulUnroll))\n val nextMplierSign = count === (mulw/cfg.mulUnroll-2).U && neg_out\n\n val eOutMask = ((BigInt(-1) << mulw).S >> (count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))(mulw-1,0)\n val eOut = (cfg.mulEarlyOut).B && count =/= (mulw/cfg.mulUnroll-1).U && count =/= 0.U &&\n !isHi && (mplier & ~eOutMask) === 0.U\n val eOutRes = (mulReg >> (mulw.U - count * cfg.mulUnroll.U)(log2Up(mulw)-1,0))\n val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))\n remainder := Cat(nextMulReg1 >> w, nextMplierSign, nextMulReg1(w-1,0))\n\n count := count + 1.U\n when (eOut || count === (mulw/cfg.mulUnroll-1).U) {\n state := s_done_mul\n resHi := isHi\n }\n }\n if (cfg.divUnroll != 0) when (state === s_div) {\n val unrolls = ((0 until cfg.divUnroll) scanLeft remainder) { case (rem, i) =>\n // the special case for iteration 0 is to save HW, not for correctness\n val difference = if (i == 0) subtractor else rem(2*w,w) - divisor(w-1,0)\n val less = difference(w)\n Cat(Mux(less, rem(2*w-1,w), difference(w-1,0)), rem(w-1,0), !less)\n }.tail\n\n remainder := unrolls.last\n when (count === (w/cfg.divUnroll).U) {\n state := Mux(neg_out, s_neg_output, s_done_div)\n resHi := isHi\n if (w % cfg.divUnroll < cfg.divUnroll - 1)\n remainder := unrolls(w % cfg.divUnroll)\n }\n count := count + 1.U\n\n val divby0 = count === 0.U && !subtractor(w)\n if (cfg.divEarlyOut) {\n val align = 1 << log2Floor(cfg.divUnroll max cfg.divEarlyOutGranularity)\n val alignMask = ~((align-1).U(log2Ceil(w).W))\n val divisorMSB = Log2(divisor(w-1,0), w) & alignMask\n val dividendMSB = Log2(remainder(w-1,0), w) | ~alignMask\n val eOutPos = ~(dividendMSB - divisorMSB)\n val eOut = count === 0.U && !divby0 && eOutPos >= align.U\n when (eOut) {\n remainder := remainder(w-1,0) << eOutPos\n count := eOutPos >> log2Floor(cfg.divUnroll)\n }\n }\n when (divby0 && !isHi) { neg_out := false.B }\n }\n when (io.resp.fire || io.kill) {\n state := s_ready\n }\n when (io.req.fire) {\n state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))\n isHi := cmdHi\n resHi := false.B\n count := (if (fastMulW) Mux[UInt](cmdMul && halfWidth(io.req.bits), (w/cfg.mulUnroll/2).U, 0.U) else 0.U)\n neg_out := Mux(cmdHi, lhs_sign, lhs_sign =/= rhs_sign)\n divisor := Cat(rhs_sign, rhs_in)\n remainder := lhs_in\n req := io.req.bits\n }\n\n val outMul = (state & (s_done_mul ^ s_done_div)) === (s_done_mul & ~s_done_div)\n val loOut = Mux(fastMulW.B && halfWidth(req) && outMul, result(w-1,w/2), result(w/2-1,0))\n val hiOut = Mux(halfWidth(req), Fill(w/2, loOut(w/2-1)), result(w-1,w/2))\n io.resp.bits.tag := req.tag\n\n io.resp.bits.data := Cat(hiOut, loOut)\n io.resp.bits.full_data := Cat(remainder(2*w, w+1), remainder(w-1, 0))\n io.resp.valid := (state === s_done_mul || state === s_done_div)\n io.req.ready := state === s_ready\n}\n\nclass PipelinedMultiplier(width: Int, latency: Int, nXpr: Int = 32) extends Module with ShouldBeRetimed {\n val io = IO(new Bundle {\n val req = Flipped(Valid(new MultiplierReq(width, log2Ceil(nXpr))))\n val resp = Valid(new MultiplierResp(width, log2Ceil(nXpr)))\n })\n\n val in = Pipe(io.req)\n\n val decode = List(\n FN_MUL -> List(N, X, X),\n FN_MULH -> List(Y, Y, Y),\n FN_MULHU -> List(Y, N, N),\n FN_MULHSU -> List(Y, Y, N))\n val cmdHi :: lhsSigned :: rhsSigned :: Nil =\n DecodeLogic(in.bits.fn, List(X, X, X), decode).map(_.asBool)\n val cmdHalf = (width > 32).B && in.bits.dw === DW_32\n\n val lhs = Cat(lhsSigned && in.bits.in1(width-1), in.bits.in1).asSInt\n val rhs = Cat(rhsSigned && in.bits.in2(width-1), in.bits.in2).asSInt\n val prod = lhs * rhs\n val muxed = Mux(cmdHi, prod(2*width-1, width), Mux(cmdHalf, prod(width/2-1, 0).sextTo(width), prod(width-1, 0)))\n\n val resp = Pipe(in, latency-1)\n io.resp.valid := resp.valid\n io.resp.bits.tag := resp.bits.tag\n io.resp.bits.data := Pipe(in.valid, muxed, latency-1).bits\n io.resp.bits.full_data := Pipe(in.valid, prod, latency-1).bits.asUInt\n}", + "response": "module MulDiv(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [4:0] io_req_bits_fn,\n input io_req_bits_dw,\n input [63:0] io_req_bits_in1,\n input [63:0] io_req_bits_in2,\n input io_kill,\n input io_resp_ready,\n output io_resp_valid,\n output [63:0] io_resp_bits_data\n);\n\n reg [2:0] state;\n reg req_dw;\n reg [6:0] count;\n reg neg_out;\n reg isHi;\n reg resHi;\n reg [64:0] divisor;\n reg [129:0] remainder;\n wire [63:0] result = resHi ? remainder[128:65] : remainder[63:0];\n wire [31:0] loOut = req_dw | state[0] ? result[31:0] : result[63:32];\n wire io_resp_valid_0 = state == 3'h6 | (&state);\n wire io_req_ready_0 = state == 3'h0;\n wire [5:0] _eOutPos_T =\n {|(remainder[63:32]), (|(remainder[63:32])) ? {|(remainder[63:48]), (|(remainder[63:48])) ? {|(remainder[63:56]), (|(remainder[63:56])) ? {|(remainder[63:60]), (|(remainder[63:60])) ? (remainder[63] ? 2'h3 : remainder[62] ? 2'h2 : {1'h0, remainder[61]}) : remainder[59] ? 2'h3 : remainder[58] ? 2'h2 : {1'h0, remainder[57]}} : {|(remainder[55:52]), (|(remainder[55:52])) ? (remainder[55] ? 2'h3 : remainder[54] ? 2'h2 : {1'h0, remainder[53]}) : remainder[51] ? 2'h3 : remainder[50] ? 2'h2 : {1'h0, remainder[49]}}} : {|(remainder[47:40]), (|(remainder[47:40])) ? {|(remainder[47:44]), (|(remainder[47:44])) ? (remainder[47] ? 2'h3 : remainder[46] ? 2'h2 : {1'h0, remainder[45]}) : remainder[43] ? 2'h3 : remainder[42] ? 2'h2 : {1'h0, remainder[41]}} : {|(remainder[39:36]), (|(remainder[39:36])) ? (remainder[39] ? 2'h3 : remainder[38] ? 2'h2 : {1'h0, remainder[37]}) : remainder[35] ? 2'h3 : remainder[34] ? 2'h2 : {1'h0, remainder[33]}}}} : {|(remainder[31:16]), (|(remainder[31:16])) ? {|(remainder[31:24]), (|(remainder[31:24])) ? {|(remainder[31:28]), (|(remainder[31:28])) ? (remainder[31] ? 2'h3 : remainder[30] ? 2'h2 : {1'h0, remainder[29]}) : remainder[27] ? 2'h3 : remainder[26] ? 2'h2 : {1'h0, remainder[25]}} : {|(remainder[23:20]), (|(remainder[23:20])) ? (remainder[23] ? 2'h3 : remainder[22] ? 2'h2 : {1'h0, remainder[21]}) : remainder[19] ? 2'h3 : remainder[18] ? 2'h2 : {1'h0, remainder[17]}}} : {|(remainder[15:8]), (|(remainder[15:8])) ? {|(remainder[15:12]), (|(remainder[15:12])) ? (remainder[15] ? 2'h3 : remainder[14] ? 2'h2 : {1'h0, remainder[13]}) : remainder[11] ? 2'h3 : remainder[10] ? 2'h2 : {1'h0, remainder[9]}} : {|(remainder[7:4]), (|(remainder[7:4])) ? (remainder[7] ? 2'h3 : remainder[6] ? 2'h2 : {1'h0, remainder[5]}) : remainder[3] ? 2'h3 : remainder[2] ? 2'h2 : {1'h0, remainder[1]}}}}}\n - {|(divisor[63:32]), (|(divisor[63:32])) ? {|(divisor[63:48]), (|(divisor[63:48])) ? {|(divisor[63:56]), (|(divisor[63:56])) ? {|(divisor[63:60]), (|(divisor[63:60])) ? (divisor[63] ? 2'h3 : divisor[62] ? 2'h2 : {1'h0, divisor[61]}) : divisor[59] ? 2'h3 : divisor[58] ? 2'h2 : {1'h0, divisor[57]}} : {|(divisor[55:52]), (|(divisor[55:52])) ? (divisor[55] ? 2'h3 : divisor[54] ? 2'h2 : {1'h0, divisor[53]}) : divisor[51] ? 2'h3 : divisor[50] ? 2'h2 : {1'h0, divisor[49]}}} : {|(divisor[47:40]), (|(divisor[47:40])) ? {|(divisor[47:44]), (|(divisor[47:44])) ? (divisor[47] ? 2'h3 : divisor[46] ? 2'h2 : {1'h0, divisor[45]}) : divisor[43] ? 2'h3 : divisor[42] ? 2'h2 : {1'h0, divisor[41]}} : {|(divisor[39:36]), (|(divisor[39:36])) ? (divisor[39] ? 2'h3 : divisor[38] ? 2'h2 : {1'h0, divisor[37]}) : divisor[35] ? 2'h3 : divisor[34] ? 2'h2 : {1'h0, divisor[33]}}}} : {|(divisor[31:16]), (|(divisor[31:16])) ? {|(divisor[31:24]), (|(divisor[31:24])) ? {|(divisor[31:28]), (|(divisor[31:28])) ? (divisor[31] ? 2'h3 : divisor[30] ? 2'h2 : {1'h0, divisor[29]}) : divisor[27] ? 2'h3 : divisor[26] ? 2'h2 : {1'h0, divisor[25]}} : {|(divisor[23:20]), (|(divisor[23:20])) ? (divisor[23] ? 2'h3 : divisor[22] ? 2'h2 : {1'h0, divisor[21]}) : divisor[19] ? 2'h3 : divisor[18] ? 2'h2 : {1'h0, divisor[17]}}} : {|(divisor[15:8]), (|(divisor[15:8])) ? {|(divisor[15:12]), (|(divisor[15:12])) ? (divisor[15] ? 2'h3 : divisor[14] ? 2'h2 : {1'h0, divisor[13]}) : divisor[11] ? 2'h3 : divisor[10] ? 2'h2 : {1'h0, divisor[9]}} : {|(divisor[7:4]), (|(divisor[7:4])) ? (divisor[7] ? 2'h3 : divisor[6] ? 2'h2 : {1'h0, divisor[5]}) : divisor[3] ? 2'h3 : divisor[2] ? 2'h2 : {1'h0, divisor[1]}}}}};\n wire [65:0] _prod_T_4 = {{65{remainder[64]}}, remainder[0]} * {divisor[64], divisor} + {remainder[129], remainder[129:65]};\n wire [2:0] decoded_invInputs = ~(io_req_bits_fn[2:0]);\n wire [1:0] _decoded_andMatrixOutputs_T = {decoded_invInputs[1], decoded_invInputs[2]};\n wire [1:0] _decoded_orMatrixOutputs_T_4 = {&{io_req_bits_fn[0], decoded_invInputs[2]}, io_req_bits_fn[1]};\n wire lhs_sign = (|{decoded_invInputs[0], &_decoded_andMatrixOutputs_T}) & (io_req_bits_dw ? io_req_bits_in1[63] : io_req_bits_in1[31]);\n wire rhs_sign = (|{&_decoded_andMatrixOutputs_T, &{decoded_invInputs[0], io_req_bits_fn[2]}}) & (io_req_bits_dw ? io_req_bits_in2[63] : io_req_bits_in2[31]);\n wire [64:0] _subtractor_T_1 = remainder[128:64] - divisor;\n wire _GEN = state == 3'h1;\n wire _GEN_0 = state == 3'h5;\n wire _GEN_1 = state == 3'h2;\n wire _GEN_2 = _GEN_1 & count == 7'h3F;\n wire _GEN_3 = state == 3'h3;\n wire _GEN_4 = count == 7'h40;\n wire _eOut_T_9 = count == 7'h0;\n wire divby0 = _eOut_T_9 & ~(_subtractor_T_1[64]);\n wire _GEN_5 = io_req_ready_0 & io_req_valid;\n wire eOut_1 = _eOut_T_9 & ~divby0 & _eOutPos_T != 6'h3F;\n always @(posedge clock) begin\n if (reset)\n state <= 3'h0;\n else if (_GEN_5)\n state <= decoded_invInputs[2] ? 3'h2 : {1'h0, ~(lhs_sign | rhs_sign), 1'h1};\n else if (io_resp_ready & io_resp_valid_0 | io_kill)\n state <= 3'h0;\n else if (_GEN_3 & _GEN_4)\n state <= {1'h1, ~neg_out, 1'h1};\n else if (_GEN_2)\n state <= 3'h6;\n else if (_GEN_0)\n state <= 3'h7;\n else if (_GEN)\n state <= 3'h3;\n if (_GEN_5) begin\n req_dw <= io_req_bits_dw;\n count <= {1'h0, decoded_invInputs[2] & ~io_req_bits_dw, 5'h0};\n isHi <= |_decoded_orMatrixOutputs_T_4;\n divisor <= {rhs_sign, io_req_bits_dw ? io_req_bits_in2[63:32] : {32{rhs_sign}}, io_req_bits_in2[31:0]};\n remainder <= {66'h0, io_req_bits_dw ? io_req_bits_in1[63:32] : {32{lhs_sign}}, io_req_bits_in1[31:0]};\n end\n else begin\n if (_GEN_3) begin\n count <= eOut_1 ? {1'h0, ~_eOutPos_T} : count + 7'h1;\n remainder <= eOut_1 ? {3'h0, {63'h0, remainder[63:0]} << ~_eOutPos_T} : {1'h0, _subtractor_T_1[64] ? remainder[127:64] : _subtractor_T_1[63:0], remainder[63:0], ~(_subtractor_T_1[64])};\n end\n else if (_GEN_1) begin\n count <= count + 7'h1;\n remainder <= {_prod_T_4[65:1], count == 7'h3E & neg_out, _prod_T_4[0], remainder[63:1]};\n end\n else if (_GEN_0 | _GEN & remainder[63])\n remainder <= {66'h0, 64'h0 - result};\n if (_GEN & divisor[63])\n divisor <= _subtractor_T_1;\n end\n neg_out <= _GEN_5 ? ((|_decoded_orMatrixOutputs_T_4) ? lhs_sign : lhs_sign != rhs_sign) : ~(_GEN_3 & divby0 & ~isHi) & neg_out;\n resHi <= ~_GEN_5 & (_GEN_3 & _GEN_4 | _GEN_2 ? isHi : ~_GEN_0 & resHi);\n end\n assign io_req_ready = io_req_ready_0;\n assign io_resp_valid = io_resp_valid_0;\n assign io_resp_bits_data = {req_dw ? result[63:32] : {32{loOut[31]}}, loOut};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n// See LICENSE.Berkeley for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3.{dontTouch, _}\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.bundlebridge._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.amba.AMBAProtField\nimport freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType}\nimport freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters}\nimport freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata}\nimport freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle}\n\nimport freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt}\n\nimport scala.collection.mutable.ListBuffer\n\ncase class DCacheParams(\n nSets: Int = 64,\n nWays: Int = 4,\n rowBits: Int = 64,\n subWordBits: Option[Int] = None,\n replacementPolicy: String = \"random\",\n nTLBSets: Int = 1,\n nTLBWays: Int = 32,\n nTLBBasePageSectors: Int = 4,\n nTLBSuperpages: Int = 4,\n tagECC: Option[String] = None,\n dataECC: Option[String] = None,\n dataECCBytes: Int = 1,\n nMSHRs: Int = 1,\n nSDQ: Int = 17,\n nRPQ: Int = 16,\n nMMIOs: Int = 1,\n blockBytes: Int = 64,\n separateUncachedResp: Boolean = false,\n acquireBeforeRelease: Boolean = false,\n pipelineWayMux: Boolean = false,\n clockGate: Boolean = false,\n scratch: Option[BigInt] = None) extends L1CacheParams {\n\n def tagCode: Code = Code.fromString(tagECC)\n def dataCode: Code = Code.fromString(dataECC)\n\n def dataScratchpadBytes: Int = scratch.map(_ => nSets*blockBytes).getOrElse(0)\n\n def replacement = new RandomReplacement(nWays)\n\n def silentDrop: Boolean = !acquireBeforeRelease\n\n require((!scratch.isDefined || nWays == 1),\n \"Scratchpad only allowed in direct-mapped cache.\")\n require((!scratch.isDefined || nMSHRs == 0),\n \"Scratchpad only allowed in blocking cache.\")\n if (scratch.isEmpty)\n require(isPow2(nSets), s\"nSets($nSets) must be pow2\")\n}\n\ntrait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters {\n val cacheParams = tileParams.dcache.get\n val cfg = cacheParams\n\n def wordBits = coreDataBits\n def wordBytes = coreDataBytes\n def subWordBits = cacheParams.subWordBits.getOrElse(wordBits)\n def subWordBytes = subWordBits / 8\n def wordOffBits = log2Up(wordBytes)\n def beatBytes = cacheBlockBytes / cacheDataBeats\n def beatWords = beatBytes / wordBytes\n def beatOffBits = log2Up(beatBytes)\n def idxMSB = untagBits-1\n def idxLSB = blockOffBits\n def offsetmsb = idxLSB-1\n def offsetlsb = wordOffBits\n def rowWords = rowBits/wordBits\n def doNarrowRead = coreDataBits * nWays % rowBits == 0\n def eccBytes = cacheParams.dataECCBytes\n val eccBits = cacheParams.dataECCBytes * 8\n val encBits = cacheParams.dataCode.width(eccBits)\n val encWordBits = encBits * (wordBits / eccBits)\n def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only\n def encRowBits = encDataBits*rowWords\n def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed\n def lrscBackoff = 3 // disallow LRSC reacquisition briefly\n def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant\n def nIOMSHRs = cacheParams.nMMIOs\n def maxUncachedInFlight = cacheParams.nMMIOs\n def dataScratchpadSize = cacheParams.dataScratchpadBytes\n\n require(rowBits >= coreDataBits, s\"rowBits($rowBits) < coreDataBits($coreDataBits)\")\n if (!usingDataScratchpad)\n require(rowBits == cacheDataBits, s\"rowBits($rowBits) != cacheDataBits($cacheDataBits)\")\n // would need offset addr for puts if data width < xlen\n require(xLen <= cacheDataBits, s\"xLen($xLen) > cacheDataBits($cacheDataBits)\")\n}\n\nabstract class L1HellaCacheModule(implicit val p: Parameters) extends Module\n with HasL1HellaCacheParameters\n\nabstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)\n with HasL1HellaCacheParameters\n\n/** Bundle definitions for HellaCache interfaces */\n\ntrait HasCoreMemOp extends HasL1HellaCacheParameters {\n val addr = UInt(coreMaxAddrBits.W)\n val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W))\n val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W)\n val cmd = UInt(M_SZ.W)\n val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W)\n val signed = Bool()\n val dprv = UInt(PRV.SZ.W)\n val dv = Bool()\n}\n\ntrait HasCoreData extends HasCoreParameters {\n val data = UInt(coreDataBits.W)\n val mask = UInt(coreDataBytes.W)\n}\n\nclass HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp {\n val phys = Bool()\n val no_resp = Bool() // The dcache may omit generating a response for this request\n val no_alloc = Bool()\n val no_xcpt = Bool()\n}\n\nclass HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData\n\nclass HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)\n with HasCoreMemOp\n with HasCoreData {\n val replay = Bool()\n val has_data = Bool()\n val data_word_bypass = UInt(coreDataBits.W)\n val data_raw = UInt(coreDataBits.W)\n val store_data = UInt(coreDataBits.W)\n}\n\nclass AlignmentExceptions extends Bundle {\n val ld = Bool()\n val st = Bool()\n}\n\nclass HellaCacheExceptions extends Bundle {\n val ma = new AlignmentExceptions\n val pf = new AlignmentExceptions\n val gf = new AlignmentExceptions\n val ae = new AlignmentExceptions\n}\n\nclass HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData\n\nclass HellaCachePerfEvents extends Bundle {\n val acquire = Bool()\n val release = Bool()\n val grant = Bool()\n val tlbMiss = Bool()\n val blocked = Bool()\n val canAcceptStoreThenLoad = Bool()\n val canAcceptStoreThenRMW = Bool()\n val canAcceptLoadThenLoad = Bool()\n val storeBufferEmptyAfterLoad = Bool()\n val storeBufferEmptyAfterStore = Bool()\n}\n\n// interface between D$ and processor/DTLB\nclass HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {\n val req = Decoupled(new HellaCacheReq)\n val s1_kill = Output(Bool()) // kill previous cycle's req\n val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req\n val s2_nack = Input(Bool()) // req from two cycles ago is rejected\n val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint)\n val s2_kill = Output(Bool()) // kill req from two cycles ago\n val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO\n val s2_paddr = Input(UInt(paddrBits.W)) // translated address\n\n val resp = Flipped(Valid(new HellaCacheResp))\n val replay_next = Input(Bool())\n val s2_xcpt = Input(new HellaCacheExceptions)\n val s2_gpa = Input(UInt(vaddrBitsExtended.W))\n val s2_gpa_is_pte = Input(Bool())\n val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp)))\n val ordered = Input(Bool())\n val store_pending = Input(Bool()) // there is a store in a store buffer somewhere\n val perf = Input(new HellaCachePerfEvents())\n\n val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself?\n val clock_enabled = Input(Bool()) // is D$ currently being clocked?\n}\n\n/** Base classes for Diplomatic TL2 HellaCaches */\n\nabstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule\n with HasNonDiplomaticTileParameters {\n protected val cfg = tileParams.dcache.get\n\n protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1(\n name = s\"Core ${tileId} DCache\",\n sourceId = IdRange(0, 1 max cfg.nMSHRs),\n supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))))\n\n protected def mmioClientParameters = Seq(TLMasterParameters.v1(\n name = s\"Core ${tileId} DCache MMIO\",\n sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs),\n requestFifo = true))\n\n def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max\n\n val node = TLClientNode(Seq(TLMasterPortParameters.v1(\n clients = cacheClientParameters ++ mmioClientParameters,\n minLatency = 1,\n requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField())))))\n\n val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())\n val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]())\n\n val module: HellaCacheModule\n\n def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB || !m.executable || m.regionType >= RegionType.TRACKED || m.regionType <= RegionType.IDEMPOTENT)\n\n def canSupportCFlushLine = !usingVM || cfg.blockBytes * cfg.nSets <= (1 << pgIdxBits)\n\n require(!tileParams.core.haveCFlush || cfg.scratch.isEmpty, \"CFLUSH_D_L1 instruction requires a D$\")\n}\n\nclass HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) {\n val cpu = Flipped(new HellaCacheIO)\n val ptw = new TLBPTWIO()\n val errors = new DCacheErrors\n val tlb_port = new DCacheTLBPort\n}\n\nclass HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)\n with HasL1HellaCacheParameters {\n implicit val edge: TLEdgeOut = outer.node.edges.out(0)\n val (tl_out, _) = outer.node.out(0)\n val io = IO(new HellaCacheBundle)\n val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle)\n val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle)\n dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals\n dontTouch(io.cpu.s1_data)\n\n require(rowBits == edge.bundle.dataBits)\n\n private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile)\n fifoManagers.foreach { m =>\n require (m.fifoId == fifoManagers.head.fifoId,\n s\"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\\n\"+\n s\"${m.nodePath.map(_.name)}\\nversus\\n${fifoManagers.head.nodePath.map(_.name)}\")\n }\n}\n\n/** Support overriding which HellaCache is instantiated */\n\ncase object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply)\n\nobject HellaCacheFactory {\n def apply(tile: BaseTile)(p: Parameters): HellaCache = {\n if (tile.tileParams.dcache.get.nMSHRs == 0)\n new DCache(tile.tileId, tile.crossing)(p)\n else\n new NonBlockingDCache(tile.tileId)(p)\n }\n}\n\n/** Mix-ins for constructing tiles that have a HellaCache */\n\ntrait HasHellaCache { this: BaseTile =>\n val module: HasHellaCacheModule\n implicit val p: Parameters\n var nDCachePorts = 0\n lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p))\n\n tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node\n dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode }\n dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode }\n InModuleBody {\n dcache.module.io.tlb_port := DontCare\n }\n}\n\ntrait HasHellaCacheModule {\n val outer: HasHellaCache with HasTileParameters\n implicit val p: Parameters\n val dcachePorts = ListBuffer[HellaCacheIO]()\n val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p))\n outer.dcache.module.io.cpu <> dcacheArb.io.mem\n}\n\n/** Metadata array used for all HellaCaches */\n\nclass L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) {\n val coh = new ClientMetadata\n val tag = UInt(tagBits.W)\n}\n\nobject L1Metadata {\n def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = {\n val meta = Wire(new L1Metadata)\n meta.tag := tag\n meta.coh := coh\n meta\n }\n}\n\nclass L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {\n val idx = UInt(idxBits.W)\n val way_en = UInt(nWays.W)\n val tag = UInt(tagBits.W)\n}\n\nclass L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) {\n val data = new L1Metadata\n}\n\nclass L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) {\n val rstVal = onReset()\n val io = IO(new Bundle {\n val read = Flipped(Decoupled(new L1MetaReadReq))\n val write = Flipped(Decoupled(new L1MetaWriteReq))\n val resp = Output(Vec(nWays, rstVal.cloneType))\n })\n\n val rst_cnt = RegInit(0.U(log2Up(nSets+1).W))\n val rst = rst_cnt < nSets.U\n val waddr = Mux(rst, rst_cnt, io.write.bits.idx)\n val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt\n val wmask = Mux(rst || (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools\n val rmask = Mux(rst || (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools\n when (rst) { rst_cnt := rst_cnt+1.U }\n\n val metabits = rstVal.getWidth\n val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W)))\n val wen = rst || io.write.valid\n when (wen) {\n tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)\n }\n io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))\n\n io.read.ready := !wen // so really this could be a 6T RAM\n io.write.ready := !rst\n}", + "response": "module tag_array(\n input [5:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [87:0] RW0_wdata,\n output [87:0] RW0_rdata,\n input [3:0] RW0_wmask\n);\n\n tag_array_ext tag_array_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module dataArrayWay_0(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [63:0] RW0_wdata,\n output [63:0] RW0_rdata\n);\n\n dataArrayWay_0_ext dataArrayWay_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_4(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [51:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [51:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_1_ext table_1_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Datapath: Rename Logic\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Supports 1-cycle and 2-cycle latencies. (aka, passthrough versus registers between ren1 and ren2).\n// - ren1: read the map tables and allocate a new physical register from the freelist.\n// - ren2: read the busy table for the physical operands.\n//\n// Ren1 data is provided as an output to be fed directly into the ROB.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\n\n/**\n * IO bundle to interface with the Register Rename logic\n *\n * @param plWidth pipeline width\n * @param numIntPregs number of int physical registers\n * @param numFpPregs number of FP physical registers\n * @param numWbPorts number of int writeback ports\n * @param numWbPorts number of FP writeback ports\n */\nclass RenameStageIO(\n val plWidth: Int,\n val numPhysRegs: Int,\n val numWbPorts: Int)\n (implicit p: Parameters) extends BoomBundle\n\n\n/**\n * IO bundle to debug the rename stage\n */\nclass DebugRenameStageIO(val numPhysRegs: Int)(implicit p: Parameters) extends BoomBundle\n{\n val freelist = Bits(numPhysRegs.W)\n val isprlist = Bits(numPhysRegs.W)\n val busytable = UInt(numPhysRegs.W)\n}\n\nabstract class AbstractRenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val ren_stalls = Output(Vec(plWidth, Bool()))\n\n val kill = Input(Bool())\n\n val dec_fire = Input(Vec(plWidth, Bool())) // will commit state updates\n val dec_uops = Input(Vec(plWidth, new MicroOp()))\n\n // physical specifiers available AND busy/ready status available.\n val ren2_mask = Vec(plWidth, Output(Bool())) // mask of valid instructions\n val ren2_uops = Vec(plWidth, Output(new MicroOp()))\n\n // branch resolution (execute)\n val brupdate = Input(new BrUpdateInfo())\n\n val dis_fire = Input(Vec(coreWidth, Bool()))\n val dis_ready = Input(Bool())\n\n // wakeup ports\n val wakeups = Flipped(Vec(numWbPorts, Valid(new ExeUnitResp(xLen))))\n\n // commit stage\n val com_valids = Input(Vec(plWidth, Bool()))\n val com_uops = Input(Vec(plWidth, new MicroOp()))\n val rbk_valids = Input(Vec(plWidth, Bool()))\n val rollback = Input(Bool())\n\n val debug_rob_empty = Input(Bool())\n val debug = Output(new DebugRenameStageIO(numPhysRegs))\n })\n\n io.ren_stalls.foreach(_ := false.B)\n io.debug := DontCare\n\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp\n\n //-------------------------------------------------------------\n // Pipeline State & Wires\n\n // Stage 1\n val ren1_fire = Wire(Vec(plWidth, Bool()))\n val ren1_uops = Wire(Vec(plWidth, new MicroOp))\n\n\n // Stage 2\n val ren2_fire = io.dis_fire\n val ren2_ready = io.dis_ready\n val ren2_valids = Wire(Vec(plWidth, Bool()))\n val ren2_uops = Wire(Vec(plWidth, new MicroOp))\n val ren2_alloc_reqs = Wire(Vec(plWidth, Bool()))\n\n\n //-------------------------------------------------------------\n // pipeline registers\n\n for (w <- 0 until plWidth) {\n ren1_fire(w) := io.dec_fire(w)\n ren1_uops(w) := io.dec_uops(w)\n }\n\n for (w <- 0 until plWidth) {\n val r_valid = RegInit(false.B)\n val r_uop = Reg(new MicroOp)\n val next_uop = Wire(new MicroOp)\n\n next_uop := r_uop\n\n when (io.kill) {\n r_valid := false.B\n } .elsewhen (ren2_ready) {\n r_valid := ren1_fire(w)\n next_uop := ren1_uops(w)\n } .otherwise {\n r_valid := r_valid && !ren2_fire(w) // clear bit if uop gets dispatched\n next_uop := r_uop\n }\n\n r_uop := GetNewUopAndBrMask(BypassAllocations(next_uop, ren2_uops, ren2_alloc_reqs), io.brupdate)\n\n ren2_valids(w) := r_valid\n ren2_uops(w) := r_uop\n }\n\n //-------------------------------------------------------------\n // Outputs\n\n io.ren2_mask := ren2_valids\n\n\n}\n\n\n/**\n * Rename stage that connets the map table, free list, and busy table.\n * Can be used in both the FP pipeline and the normal execute pipeline.\n *\n * @param plWidth pipeline width\n * @param numWbPorts number of int writeback ports\n * @param numWbPorts number of FP writeback ports\n */\nclass RenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int,\n float: Boolean)\n(implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)\n{\n val pregSz = log2Ceil(numPhysRegs)\n val rtype = if (float) RT_FLT else RT_FIX\n\n //-------------------------------------------------------------\n // Helper Functions\n\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {\n val bypassed_uop = Wire(new MicroOp)\n bypassed_uop := uop\n\n val bypass_hits_rs1 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs1 }\n val bypass_hits_rs2 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs2 }\n val bypass_hits_rs3 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs3 }\n val bypass_hits_dst = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.ldst }\n\n val bypass_sel_rs1 = PriorityEncoderOH(bypass_hits_rs1.reverse).reverse\n val bypass_sel_rs2 = PriorityEncoderOH(bypass_hits_rs2.reverse).reverse\n val bypass_sel_rs3 = PriorityEncoderOH(bypass_hits_rs3.reverse).reverse\n val bypass_sel_dst = PriorityEncoderOH(bypass_hits_dst.reverse).reverse\n\n val do_bypass_rs1 = bypass_hits_rs1.reduce(_||_)\n val do_bypass_rs2 = bypass_hits_rs2.reduce(_||_)\n val do_bypass_rs3 = bypass_hits_rs3.reduce(_||_)\n val do_bypass_dst = bypass_hits_dst.reduce(_||_)\n\n val bypass_pdsts = older_uops.map(_.pdst)\n\n when (do_bypass_rs1) { bypassed_uop.prs1 := Mux1H(bypass_sel_rs1, bypass_pdsts) }\n when (do_bypass_rs2) { bypassed_uop.prs2 := Mux1H(bypass_sel_rs2, bypass_pdsts) }\n when (do_bypass_rs3) { bypassed_uop.prs3 := Mux1H(bypass_sel_rs3, bypass_pdsts) }\n when (do_bypass_dst) { bypassed_uop.stale_pdst := Mux1H(bypass_sel_dst, bypass_pdsts) }\n\n bypassed_uop.prs1_busy := uop.prs1_busy || do_bypass_rs1\n bypassed_uop.prs2_busy := uop.prs2_busy || do_bypass_rs2\n bypassed_uop.prs3_busy := uop.prs3_busy || do_bypass_rs3\n\n if (!float) {\n bypassed_uop.prs3 := DontCare\n bypassed_uop.prs3_busy := false.B\n }\n\n bypassed_uop\n }\n\n //-------------------------------------------------------------\n // Rename Structures\n\n val maptable = Module(new RenameMapTable(\n plWidth,\n 32,\n numPhysRegs,\n false,\n float))\n val freelist = Module(new RenameFreeList(\n plWidth,\n numPhysRegs,\n if (float) 32 else 31))\n val busytable = Module(new RenameBusyTable(\n plWidth,\n numPhysRegs,\n numWbPorts,\n false,\n float))\n\n\n\n val ren2_br_tags = Wire(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Commit/Rollback\n val com_valids = Wire(Vec(plWidth, Bool()))\n val rbk_valids = Wire(Vec(plWidth, Bool()))\n\n for (w <- 0 until plWidth) {\n ren2_alloc_reqs(w) := ren2_uops(w).ldst_val && ren2_uops(w).dst_rtype === rtype && ren2_fire(w)\n ren2_br_tags(w).valid := ren2_fire(w) && ren2_uops(w).allocate_brtag\n\n com_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.com_valids(w)\n rbk_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.rbk_valids(w)\n ren2_br_tags(w).bits := ren2_uops(w).br_tag\n }\n\n //-------------------------------------------------------------\n // Rename Table\n\n // Maptable inputs.\n val map_reqs = Wire(Vec(plWidth, new MapReq(lregSz)))\n val remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))\n\n // Generate maptable requests.\n for ((((ren1,ren2),com),w) <- (ren1_uops zip ren2_uops zip io.com_uops.reverse).zipWithIndex) {\n map_reqs(w).lrs1 := ren1.lrs1\n map_reqs(w).lrs2 := ren1.lrs2\n map_reqs(w).lrs3 := ren1.lrs3\n map_reqs(w).ldst := ren1.ldst\n\n remap_reqs(w).ldst := Mux(io.rollback, com.ldst , ren2.ldst)\n remap_reqs(w).pdst := Mux(io.rollback, com.stale_pdst, ren2.pdst)\n }\n ren2_alloc_reqs zip rbk_valids.reverse zip remap_reqs map {\n case ((a,r),rr) => rr.valid := a || r}\n\n // Hook up inputs.\n maptable.io.map_reqs := map_reqs\n maptable.io.remap_reqs := remap_reqs\n maptable.io.ren_br_tags := ren2_br_tags\n maptable.io.brupdate := io.brupdate\n maptable.io.rollback := io.rollback\n\n // Maptable outputs.\n for ((uop, w) <- ren1_uops.zipWithIndex) {\n val mappings = maptable.io.map_resps(w)\n\n uop.prs1 := mappings.prs1\n uop.prs2 := mappings.prs2\n uop.prs3 := mappings.prs3 // only FP has 3rd operand\n uop.stale_pdst := mappings.stale_pdst\n }\n\n\n\n //-------------------------------------------------------------\n // Free List\n\n // Freelist inputs.\n freelist.io.reqs := ren2_alloc_reqs\n freelist.io.dealloc_pregs zip com_valids zip rbk_valids map\n {case ((d,c),r) => d.valid := c || r}\n freelist.io.dealloc_pregs zip io.com_uops map\n {case (d,c) => d.bits := Mux(io.rollback, c.pdst, c.stale_pdst)}\n freelist.io.ren_br_tags := ren2_br_tags\n freelist.io.brupdate := io.brupdate\n freelist.io.debug.pipeline_empty := io.debug_rob_empty\n\n assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),\n \"[rename-stage] A uop is trying to allocate the zero physical register.\")\n\n // Freelist outputs.\n for ((uop, w) <- ren2_uops.zipWithIndex) {\n val preg = freelist.io.alloc_pregs(w).bits\n uop.pdst := Mux(uop.ldst =/= 0.U || float.B, preg, 0.U)\n }\n\n //-------------------------------------------------------------\n // Busy Table\n\n busytable.io.ren_uops := ren2_uops // expects pdst to be set up.\n busytable.io.rebusy_reqs := ren2_alloc_reqs\n busytable.io.wb_valids := io.wakeups.map(_.valid)\n busytable.io.wb_pdsts := io.wakeups.map(_.bits.uop.pdst)\n\n assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),\n \"[rename] Wakeup has wrong rtype.\")\n\n for ((uop, w) <- ren2_uops.zipWithIndex) {\n val busy = busytable.io.busy_resps(w)\n\n uop.prs1_busy := uop.lrs1_rtype === rtype && busy.prs1_busy\n uop.prs2_busy := uop.lrs2_rtype === rtype && busy.prs2_busy\n uop.prs3_busy := uop.frs3_en && busy.prs3_busy\n\n val valid = ren2_valids(w)\n assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n }\n\n //-------------------------------------------------------------\n // Outputs\n\n for (w <- 0 until plWidth) {\n val can_allocate = freelist.io.alloc_pregs(w).valid\n\n // Push back against Decode stage if Rename1 can't proceed.\n io.ren_stalls(w) := (ren2_uops(w).dst_rtype === rtype) && !can_allocate\n\n val bypassed_uop = Wire(new MicroOp)\n if (w > 0) bypassed_uop := BypassAllocations(ren2_uops(w), ren2_uops.slice(0,w), ren2_alloc_reqs.slice(0,w))\n else bypassed_uop := ren2_uops(w)\n\n io.ren2_uops(w) := GetNewUopAndBrMask(bypassed_uop, io.brupdate)\n }\n\n //-------------------------------------------------------------\n // Debug signals\n\n io.debug.freelist := freelist.io.debug.freelist\n io.debug.isprlist := freelist.io.debug.isprlist\n io.debug.busytable := busytable.io.debug.busytable\n}\n\nclass PredRenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int)\n (implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)\n{\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {\n uop\n }\n\n ren2_alloc_reqs := DontCare\n\n val busy_table = RegInit(VecInit(0.U(ftqSz.W).asBools))\n val to_busy = WireInit(VecInit(0.U(ftqSz.W).asBools))\n val unbusy = WireInit(VecInit(0.U(ftqSz.W).asBools))\n\n val current_ftq_idx = Reg(UInt(log2Ceil(ftqSz).W))\n var next_ftq_idx = current_ftq_idx\n\n for (w <- 0 until plWidth) {\n io.ren2_uops(w) := ren2_uops(w)\n\n val is_sfb_br = ren2_uops(w).is_sfb_br && ren2_fire(w)\n val is_sfb_shadow = ren2_uops(w).is_sfb_shadow && ren2_fire(w)\n\n val ftq_idx = ren2_uops(w).ftq_idx\n when (is_sfb_br) {\n io.ren2_uops(w).pdst := ftq_idx\n to_busy(ftq_idx) := true.B\n }\n next_ftq_idx = Mux(is_sfb_br, ftq_idx, next_ftq_idx)\n\n when (is_sfb_shadow) {\n io.ren2_uops(w).ppred := next_ftq_idx\n io.ren2_uops(w).ppred_busy := (busy_table(next_ftq_idx) || to_busy(next_ftq_idx)) && !unbusy(next_ftq_idx)\n }\n }\n\n for (w <- 0 until numWbPorts) {\n when (io.wakeups(w).valid) {\n unbusy(io.wakeups(w).bits.uop.pdst) := true.B\n }\n }\n\n current_ftq_idx := next_ftq_idx\n\n busy_table := ((busy_table.asUInt | to_busy.asUInt) & ~unbusy.asUInt).asBools\n}", + "response": "module RenameStage_1(\n input clock,\n input reset,\n output io_ren_stalls_0,\n input io_kill,\n input io_dec_uops_0_is_br,\n input io_dec_uops_0_is_jalr,\n input io_dec_uops_0_is_sfb,\n input [2:0] io_dec_uops_0_br_tag,\n input [5:0] io_dec_uops_0_ldst,\n input [5:0] io_dec_uops_0_lrs1,\n input [5:0] io_dec_uops_0_lrs2,\n input [5:0] io_dec_uops_0_lrs3,\n input io_dec_uops_0_ldst_val,\n input [1:0] io_dec_uops_0_dst_rtype,\n input [1:0] io_dec_uops_0_lrs1_rtype,\n input [1:0] io_dec_uops_0_lrs2_rtype,\n input io_dec_uops_0_frs3_en,\n output [5:0] io_ren2_uops_0_pdst,\n output [5:0] io_ren2_uops_0_prs1,\n output [5:0] io_ren2_uops_0_prs2,\n output [5:0] io_ren2_uops_0_prs3,\n output io_ren2_uops_0_prs1_busy,\n output io_ren2_uops_0_prs2_busy,\n output io_ren2_uops_0_prs3_busy,\n output [5:0] io_ren2_uops_0_stale_pdst,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_dis_fire_0,\n input io_dis_ready,\n input io_wakeups_0_valid,\n input [5:0] io_wakeups_0_bits_uop_pdst,\n input [1:0] io_wakeups_0_bits_uop_dst_rtype,\n input io_wakeups_1_valid,\n input [5:0] io_wakeups_1_bits_uop_pdst,\n input [1:0] io_wakeups_1_bits_uop_dst_rtype,\n input io_com_valids_0,\n input [5:0] io_com_uops_0_pdst,\n input [5:0] io_com_uops_0_stale_pdst,\n input [5:0] io_com_uops_0_ldst,\n input io_com_uops_0_ldst_val,\n input [1:0] io_com_uops_0_dst_rtype,\n input io_rbk_valids_0,\n input io_rollback,\n input io_debug_rob_empty\n);\n\n wire _busytable_io_busy_resps_0_prs1_busy;\n wire _busytable_io_busy_resps_0_prs2_busy;\n wire _busytable_io_busy_resps_0_prs3_busy;\n wire _freelist_io_alloc_pregs_0_valid;\n wire [5:0] _freelist_io_alloc_pregs_0_bits;\n wire [5:0] _maptable_io_map_resps_0_prs1;\n wire [5:0] _maptable_io_map_resps_0_prs2;\n wire [5:0] _maptable_io_map_resps_0_prs3;\n wire [5:0] _maptable_io_map_resps_0_stale_pdst;\n reg r_uop_is_br;\n reg r_uop_is_jalr;\n reg r_uop_is_sfb;\n reg [2:0] r_uop_br_tag;\n reg [5:0] r_uop_prs1;\n reg [5:0] r_uop_prs2;\n reg [5:0] r_uop_prs3;\n reg [5:0] r_uop_stale_pdst;\n reg [5:0] r_uop_ldst;\n reg [5:0] r_uop_lrs1;\n reg [5:0] r_uop_lrs2;\n reg [5:0] r_uop_lrs3;\n reg r_uop_ldst_val;\n reg [1:0] r_uop_dst_rtype;\n reg [1:0] r_uop_lrs1_rtype;\n reg [1:0] r_uop_lrs2_rtype;\n reg r_uop_frs3_en;\n wire _io_ren_stalls_0_T = r_uop_dst_rtype == 2'h1;\n wire freelist_io_reqs_0 = r_uop_ldst_val & _io_ren_stalls_0_T & io_dis_fire_0;\n wire ren2_br_tags_0_valid = io_dis_fire_0 & (r_uop_is_br & ~r_uop_is_sfb | r_uop_is_jalr);\n wire _rbk_valids_0_T = io_com_uops_0_dst_rtype == 2'h1;\n wire rbk_valids_0 = io_com_uops_0_ldst_val & _rbk_valids_0_T & io_rbk_valids_0;\n wire _GEN = io_kill | ~io_dis_ready;\n always @(posedge clock) begin\n if (_GEN) begin\n end\n else begin\n r_uop_is_br <= io_dec_uops_0_is_br;\n r_uop_is_jalr <= io_dec_uops_0_is_jalr;\n r_uop_is_sfb <= io_dec_uops_0_is_sfb;\n r_uop_br_tag <= io_dec_uops_0_br_tag;\n end\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs1 : io_dec_uops_0_lrs1))\n r_uop_prs1 <= _freelist_io_alloc_pregs_0_bits;\n else if (_GEN) begin\n end\n else\n r_uop_prs1 <= _maptable_io_map_resps_0_prs1;\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs2 : io_dec_uops_0_lrs2))\n r_uop_prs2 <= _freelist_io_alloc_pregs_0_bits;\n else if (_GEN) begin\n end\n else\n r_uop_prs2 <= _maptable_io_map_resps_0_prs2;\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs3 : io_dec_uops_0_lrs3))\n r_uop_prs3 <= _freelist_io_alloc_pregs_0_bits;\n else if (_GEN) begin\n end\n else\n r_uop_prs3 <= _maptable_io_map_resps_0_prs3;\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_ldst : io_dec_uops_0_ldst))\n r_uop_stale_pdst <= _freelist_io_alloc_pregs_0_bits;\n else if (_GEN) begin\n end\n else\n r_uop_stale_pdst <= _maptable_io_map_resps_0_stale_pdst;\n if (_GEN) begin\n end\n else begin\n r_uop_ldst <= io_dec_uops_0_ldst;\n r_uop_lrs1 <= io_dec_uops_0_lrs1;\n r_uop_lrs2 <= io_dec_uops_0_lrs2;\n r_uop_lrs3 <= io_dec_uops_0_lrs3;\n r_uop_ldst_val <= io_dec_uops_0_ldst_val;\n r_uop_dst_rtype <= io_dec_uops_0_dst_rtype;\n r_uop_lrs1_rtype <= io_dec_uops_0_lrs1_rtype;\n r_uop_lrs2_rtype <= io_dec_uops_0_lrs2_rtype;\n r_uop_frs3_en <= io_dec_uops_0_frs3_en;\n end\n end\n RenameMapTable_1 maptable (\n .clock (clock),\n .reset (reset),\n .io_map_reqs_0_lrs1 (io_dec_uops_0_lrs1),\n .io_map_reqs_0_lrs2 (io_dec_uops_0_lrs2),\n .io_map_reqs_0_lrs3 (io_dec_uops_0_lrs3),\n .io_map_reqs_0_ldst (io_dec_uops_0_ldst),\n .io_map_resps_0_prs1 (_maptable_io_map_resps_0_prs1),\n .io_map_resps_0_prs2 (_maptable_io_map_resps_0_prs2),\n .io_map_resps_0_prs3 (_maptable_io_map_resps_0_prs3),\n .io_map_resps_0_stale_pdst (_maptable_io_map_resps_0_stale_pdst),\n .io_remap_reqs_0_ldst (io_rollback ? io_com_uops_0_ldst : r_uop_ldst),\n .io_remap_reqs_0_pdst (io_rollback ? io_com_uops_0_stale_pdst : _freelist_io_alloc_pregs_0_bits),\n .io_remap_reqs_0_valid (freelist_io_reqs_0 | rbk_valids_0),\n .io_ren_br_tags_0_valid (ren2_br_tags_0_valid),\n .io_ren_br_tags_0_bits (r_uop_br_tag),\n .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),\n .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),\n .io_rollback (io_rollback)\n );\n RenameFreeList_1 freelist (\n .clock (clock),\n .reset (reset),\n .io_reqs_0 (freelist_io_reqs_0),\n .io_alloc_pregs_0_valid (_freelist_io_alloc_pregs_0_valid),\n .io_alloc_pregs_0_bits (_freelist_io_alloc_pregs_0_bits),\n .io_dealloc_pregs_0_valid (io_com_uops_0_ldst_val & _rbk_valids_0_T & io_com_valids_0 | rbk_valids_0),\n .io_dealloc_pregs_0_bits (io_rollback ? io_com_uops_0_pdst : io_com_uops_0_stale_pdst),\n .io_ren_br_tags_0_valid (ren2_br_tags_0_valid),\n .io_ren_br_tags_0_bits (r_uop_br_tag),\n .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),\n .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),\n .io_debug_pipeline_empty (io_debug_rob_empty)\n );\n RenameBusyTable_1 busytable (\n .clock (clock),\n .reset (reset),\n .io_ren_uops_0_pdst (_freelist_io_alloc_pregs_0_bits),\n .io_ren_uops_0_prs1 (r_uop_prs1),\n .io_ren_uops_0_prs2 (r_uop_prs2),\n .io_ren_uops_0_prs3 (r_uop_prs3),\n .io_busy_resps_0_prs1_busy (_busytable_io_busy_resps_0_prs1_busy),\n .io_busy_resps_0_prs2_busy (_busytable_io_busy_resps_0_prs2_busy),\n .io_busy_resps_0_prs3_busy (_busytable_io_busy_resps_0_prs3_busy),\n .io_rebusy_reqs_0 (freelist_io_reqs_0),\n .io_wb_pdsts_0 (io_wakeups_0_bits_uop_pdst),\n .io_wb_pdsts_1 (io_wakeups_1_bits_uop_pdst),\n .io_wb_valids_0 (io_wakeups_0_valid),\n .io_wb_valids_1 (io_wakeups_1_valid)\n );\n assign io_ren_stalls_0 = _io_ren_stalls_0_T & ~_freelist_io_alloc_pregs_0_valid;\n assign io_ren2_uops_0_pdst = _freelist_io_alloc_pregs_0_bits;\n assign io_ren2_uops_0_prs1 = r_uop_prs1;\n assign io_ren2_uops_0_prs2 = r_uop_prs2;\n assign io_ren2_uops_0_prs3 = r_uop_prs3;\n assign io_ren2_uops_0_prs1_busy = r_uop_lrs1_rtype == 2'h1 & _busytable_io_busy_resps_0_prs1_busy;\n assign io_ren2_uops_0_prs2_busy = r_uop_lrs2_rtype == 2'h1 & _busytable_io_busy_resps_0_prs2_busy;\n assign io_ren2_uops_0_prs3_busy = r_uop_frs3_en & _busytable_io_busy_resps_0_prs3_busy;\n assign io_ren2_uops_0_stale_pdst = r_uop_stale_pdst;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLBFromBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_7(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module BranchKillableQueue_3(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [6:0] io_enq_bits_uop_uopc,\n input [31:0] io_enq_bits_uop_inst,\n input [31:0] io_enq_bits_uop_debug_inst,\n input io_enq_bits_uop_is_rvc,\n input [39:0] io_enq_bits_uop_debug_pc,\n input [2:0] io_enq_bits_uop_iq_type,\n input [9:0] io_enq_bits_uop_fu_code,\n input [3:0] io_enq_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_uop_ctrl_op_fcn,\n input io_enq_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_uop_ctrl_is_load,\n input io_enq_bits_uop_ctrl_is_sta,\n input io_enq_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_uop_iw_state,\n input io_enq_bits_uop_iw_p1_poisoned,\n input io_enq_bits_uop_iw_p2_poisoned,\n input io_enq_bits_uop_is_br,\n input io_enq_bits_uop_is_jalr,\n input io_enq_bits_uop_is_jal,\n input io_enq_bits_uop_is_sfb,\n input [7:0] io_enq_bits_uop_br_mask,\n input [2:0] io_enq_bits_uop_br_tag,\n input [3:0] io_enq_bits_uop_ftq_idx,\n input io_enq_bits_uop_edge_inst,\n input [5:0] io_enq_bits_uop_pc_lob,\n input io_enq_bits_uop_taken,\n input [19:0] io_enq_bits_uop_imm_packed,\n input [11:0] io_enq_bits_uop_csr_addr,\n input [4:0] io_enq_bits_uop_rob_idx,\n input [2:0] io_enq_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_uop_stq_idx,\n input [1:0] io_enq_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_uop_pdst,\n input [5:0] io_enq_bits_uop_prs1,\n input [5:0] io_enq_bits_uop_prs2,\n input [5:0] io_enq_bits_uop_prs3,\n input [3:0] io_enq_bits_uop_ppred,\n input io_enq_bits_uop_prs1_busy,\n input io_enq_bits_uop_prs2_busy,\n input io_enq_bits_uop_prs3_busy,\n input io_enq_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_uop_stale_pdst,\n input io_enq_bits_uop_exception,\n input [63:0] io_enq_bits_uop_exc_cause,\n input io_enq_bits_uop_bypassable,\n input [4:0] io_enq_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_uop_mem_size,\n input io_enq_bits_uop_mem_signed,\n input io_enq_bits_uop_is_fence,\n input io_enq_bits_uop_is_fencei,\n input io_enq_bits_uop_is_amo,\n input io_enq_bits_uop_uses_ldq,\n input io_enq_bits_uop_uses_stq,\n input io_enq_bits_uop_is_sys_pc2epc,\n input io_enq_bits_uop_is_unique,\n input io_enq_bits_uop_flush_on_commit,\n input io_enq_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_uop_ldst,\n input [5:0] io_enq_bits_uop_lrs1,\n input [5:0] io_enq_bits_uop_lrs2,\n input [5:0] io_enq_bits_uop_lrs3,\n input io_enq_bits_uop_ldst_val,\n input [1:0] io_enq_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_uop_lrs2_rtype,\n input io_enq_bits_uop_frs3_en,\n input io_enq_bits_uop_fp_val,\n input io_enq_bits_uop_fp_single,\n input io_enq_bits_uop_xcpt_pf_if,\n input io_enq_bits_uop_xcpt_ae_if,\n input io_enq_bits_uop_xcpt_ma_if,\n input io_enq_bits_uop_bp_debug_if,\n input io_enq_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_uop_debug_tsrc,\n input [64:0] io_enq_bits_data,\n input io_enq_bits_fflags_valid,\n input [6:0] io_enq_bits_fflags_bits_uop_uopc,\n input [31:0] io_enq_bits_fflags_bits_uop_inst,\n input [31:0] io_enq_bits_fflags_bits_uop_debug_inst,\n input io_enq_bits_fflags_bits_uop_is_rvc,\n input [39:0] io_enq_bits_fflags_bits_uop_debug_pc,\n input [2:0] io_enq_bits_fflags_bits_uop_iq_type,\n input [9:0] io_enq_bits_fflags_bits_uop_fu_code,\n input [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn,\n input io_enq_bits_fflags_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_fflags_bits_uop_ctrl_is_load,\n input io_enq_bits_fflags_bits_uop_ctrl_is_sta,\n input io_enq_bits_fflags_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_fflags_bits_uop_iw_state,\n input io_enq_bits_fflags_bits_uop_iw_p1_poisoned,\n input io_enq_bits_fflags_bits_uop_iw_p2_poisoned,\n input io_enq_bits_fflags_bits_uop_is_br,\n input io_enq_bits_fflags_bits_uop_is_jalr,\n input io_enq_bits_fflags_bits_uop_is_jal,\n input io_enq_bits_fflags_bits_uop_is_sfb,\n input [7:0] io_enq_bits_fflags_bits_uop_br_mask,\n input [2:0] io_enq_bits_fflags_bits_uop_br_tag,\n input [3:0] io_enq_bits_fflags_bits_uop_ftq_idx,\n input io_enq_bits_fflags_bits_uop_edge_inst,\n input [5:0] io_enq_bits_fflags_bits_uop_pc_lob,\n input io_enq_bits_fflags_bits_uop_taken,\n input [19:0] io_enq_bits_fflags_bits_uop_imm_packed,\n input [11:0] io_enq_bits_fflags_bits_uop_csr_addr,\n input [4:0] io_enq_bits_fflags_bits_uop_rob_idx,\n input [2:0] io_enq_bits_fflags_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_fflags_bits_uop_stq_idx,\n input [1:0] io_enq_bits_fflags_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_fflags_bits_uop_pdst,\n input [5:0] io_enq_bits_fflags_bits_uop_prs1,\n input [5:0] io_enq_bits_fflags_bits_uop_prs2,\n input [5:0] io_enq_bits_fflags_bits_uop_prs3,\n input [3:0] io_enq_bits_fflags_bits_uop_ppred,\n input io_enq_bits_fflags_bits_uop_prs1_busy,\n input io_enq_bits_fflags_bits_uop_prs2_busy,\n input io_enq_bits_fflags_bits_uop_prs3_busy,\n input io_enq_bits_fflags_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_fflags_bits_uop_stale_pdst,\n input io_enq_bits_fflags_bits_uop_exception,\n input [63:0] io_enq_bits_fflags_bits_uop_exc_cause,\n input io_enq_bits_fflags_bits_uop_bypassable,\n input [4:0] io_enq_bits_fflags_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_fflags_bits_uop_mem_size,\n input io_enq_bits_fflags_bits_uop_mem_signed,\n input io_enq_bits_fflags_bits_uop_is_fence,\n input io_enq_bits_fflags_bits_uop_is_fencei,\n input io_enq_bits_fflags_bits_uop_is_amo,\n input io_enq_bits_fflags_bits_uop_uses_ldq,\n input io_enq_bits_fflags_bits_uop_uses_stq,\n input io_enq_bits_fflags_bits_uop_is_sys_pc2epc,\n input io_enq_bits_fflags_bits_uop_is_unique,\n input io_enq_bits_fflags_bits_uop_flush_on_commit,\n input io_enq_bits_fflags_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_fflags_bits_uop_ldst,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs1,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs2,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs3,\n input io_enq_bits_fflags_bits_uop_ldst_val,\n input [1:0] io_enq_bits_fflags_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype,\n input io_enq_bits_fflags_bits_uop_frs3_en,\n input io_enq_bits_fflags_bits_uop_fp_val,\n input io_enq_bits_fflags_bits_uop_fp_single,\n input io_enq_bits_fflags_bits_uop_xcpt_pf_if,\n input io_enq_bits_fflags_bits_uop_xcpt_ae_if,\n input io_enq_bits_fflags_bits_uop_xcpt_ma_if,\n input io_enq_bits_fflags_bits_uop_bp_debug_if,\n input io_enq_bits_fflags_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc,\n input [4:0] io_enq_bits_fflags_bits_flags,\n input io_deq_ready,\n output io_deq_valid,\n output [6:0] io_deq_bits_uop_uopc,\n output [7:0] io_deq_bits_uop_br_mask,\n output [4:0] io_deq_bits_uop_rob_idx,\n output [2:0] io_deq_bits_uop_stq_idx,\n output [5:0] io_deq_bits_uop_pdst,\n output io_deq_bits_uop_is_amo,\n output io_deq_bits_uop_uses_stq,\n output [1:0] io_deq_bits_uop_dst_rtype,\n output io_deq_bits_uop_fp_val,\n output [64:0] io_deq_bits_data,\n output io_deq_bits_predicated,\n output io_deq_bits_fflags_valid,\n output [4:0] io_deq_bits_fflags_bits_uop_rob_idx,\n output [4:0] io_deq_bits_fflags_bits_flags,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_flush,\n output io_empty\n);\n\n wire [76:0] _ram_ext_R0_data;\n reg valids_0;\n reg valids_1;\n reg valids_2;\n reg valids_3;\n reg valids_4;\n reg [6:0] uops_0_uopc;\n reg [7:0] uops_0_br_mask;\n reg [4:0] uops_0_rob_idx;\n reg [2:0] uops_0_stq_idx;\n reg [5:0] uops_0_pdst;\n reg uops_0_is_amo;\n reg uops_0_uses_stq;\n reg [1:0] uops_0_dst_rtype;\n reg uops_0_fp_val;\n reg [6:0] uops_1_uopc;\n reg [7:0] uops_1_br_mask;\n reg [4:0] uops_1_rob_idx;\n reg [2:0] uops_1_stq_idx;\n reg [5:0] uops_1_pdst;\n reg uops_1_is_amo;\n reg uops_1_uses_stq;\n reg [1:0] uops_1_dst_rtype;\n reg uops_1_fp_val;\n reg [6:0] uops_2_uopc;\n reg [7:0] uops_2_br_mask;\n reg [4:0] uops_2_rob_idx;\n reg [2:0] uops_2_stq_idx;\n reg [5:0] uops_2_pdst;\n reg uops_2_is_amo;\n reg uops_2_uses_stq;\n reg [1:0] uops_2_dst_rtype;\n reg uops_2_fp_val;\n reg [6:0] uops_3_uopc;\n reg [7:0] uops_3_br_mask;\n reg [4:0] uops_3_rob_idx;\n reg [2:0] uops_3_stq_idx;\n reg [5:0] uops_3_pdst;\n reg uops_3_is_amo;\n reg uops_3_uses_stq;\n reg [1:0] uops_3_dst_rtype;\n reg uops_3_fp_val;\n reg [6:0] uops_4_uopc;\n reg [7:0] uops_4_br_mask;\n reg [4:0] uops_4_rob_idx;\n reg [2:0] uops_4_stq_idx;\n reg [5:0] uops_4_pdst;\n reg uops_4_is_amo;\n reg uops_4_uses_stq;\n reg [1:0] uops_4_dst_rtype;\n reg uops_4_fp_val;\n reg [2:0] enq_ptr_value;\n reg [2:0] deq_ptr_value;\n reg maybe_full;\n wire ptr_match = enq_ptr_value == deq_ptr_value;\n wire io_empty_0 = ptr_match & ~maybe_full;\n wire full = ptr_match & maybe_full;\n wire [7:0] _GEN = {{valids_0}, {valids_0}, {valids_0}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}};\n wire _GEN_0 = _GEN[deq_ptr_value];\n wire [7:0][6:0] _GEN_1 = {{uops_0_uopc}, {uops_0_uopc}, {uops_0_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};\n wire [7:0][7:0] _GEN_2 = {{uops_0_br_mask}, {uops_0_br_mask}, {uops_0_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};\n wire [7:0] out_uop_br_mask = _GEN_2[deq_ptr_value];\n wire [7:0][4:0] _GEN_3 = {{uops_0_rob_idx}, {uops_0_rob_idx}, {uops_0_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};\n wire [7:0][2:0] _GEN_4 = {{uops_0_stq_idx}, {uops_0_stq_idx}, {uops_0_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};\n wire [7:0][5:0] _GEN_5 = {{uops_0_pdst}, {uops_0_pdst}, {uops_0_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};\n wire [7:0] _GEN_6 = {{uops_0_is_amo}, {uops_0_is_amo}, {uops_0_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};\n wire [7:0] _GEN_7 = {{uops_0_uses_stq}, {uops_0_uses_stq}, {uops_0_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};\n wire [7:0][1:0] _GEN_8 = {{uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_0_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};\n wire [7:0] _GEN_9 = {{uops_0_fp_val}, {uops_0_fp_val}, {uops_0_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};\n wire do_deq = ~io_empty_0 & (io_deq_ready | ~_GEN_0) & ~io_empty_0;\n wire do_enq = ~(io_empty_0 & io_deq_ready) & ~full & io_enq_valid;\n wire _GEN_10 = enq_ptr_value == 3'h0;\n wire _GEN_11 = do_enq & _GEN_10;\n wire _GEN_12 = enq_ptr_value == 3'h1;\n wire _GEN_13 = do_enq & _GEN_12;\n wire _GEN_14 = enq_ptr_value == 3'h2;\n wire _GEN_15 = do_enq & _GEN_14;\n wire _GEN_16 = enq_ptr_value == 3'h3;\n wire _GEN_17 = do_enq & _GEN_16;\n wire _GEN_18 = enq_ptr_value == 3'h4;\n wire _GEN_19 = do_enq & _GEN_18;\n wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n valids_0 <= 1'h0;\n valids_1 <= 1'h0;\n valids_2 <= 1'h0;\n valids_3 <= 1'h0;\n valids_4 <= 1'h0;\n enq_ptr_value <= 3'h0;\n deq_ptr_value <= 3'h0;\n maybe_full <= 1'h0;\n end\n else begin\n valids_0 <= ~(do_deq & deq_ptr_value == 3'h0) & (_GEN_11 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~io_flush);\n valids_1 <= ~(do_deq & deq_ptr_value == 3'h1) & (_GEN_13 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~io_flush);\n valids_2 <= ~(do_deq & deq_ptr_value == 3'h2) & (_GEN_15 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~io_flush);\n valids_3 <= ~(do_deq & deq_ptr_value == 3'h3) & (_GEN_17 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~io_flush);\n valids_4 <= ~(do_deq & deq_ptr_value == 3'h4) & (_GEN_19 | valids_4 & (io_brupdate_b1_mispredict_mask & uops_4_br_mask) == 8'h0 & ~io_flush);\n if (do_enq)\n enq_ptr_value <= enq_ptr_value == 3'h4 ? 3'h0 : enq_ptr_value + 3'h1;\n if (do_deq)\n deq_ptr_value <= deq_ptr_value == 3'h4 ? 3'h0 : deq_ptr_value + 3'h1;\n if (~(do_enq == do_deq))\n maybe_full <= do_enq;\n end\n if (_GEN_11) begin\n uops_0_uopc <= io_enq_bits_uop_uopc;\n uops_0_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_0_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_0_pdst <= io_enq_bits_uop_pdst;\n uops_0_is_amo <= io_enq_bits_uop_is_amo;\n uops_0_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_0_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_0_br_mask <= do_enq & _GEN_10 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;\n if (_GEN_13) begin\n uops_1_uopc <= io_enq_bits_uop_uopc;\n uops_1_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_1_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_1_pdst <= io_enq_bits_uop_pdst;\n uops_1_is_amo <= io_enq_bits_uop_is_amo;\n uops_1_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_1_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_1_br_mask <= do_enq & _GEN_12 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;\n if (_GEN_15) begin\n uops_2_uopc <= io_enq_bits_uop_uopc;\n uops_2_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_2_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_2_pdst <= io_enq_bits_uop_pdst;\n uops_2_is_amo <= io_enq_bits_uop_is_amo;\n uops_2_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_2_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_2_br_mask <= do_enq & _GEN_14 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;\n if (_GEN_17) begin\n uops_3_uopc <= io_enq_bits_uop_uopc;\n uops_3_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_3_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_3_pdst <= io_enq_bits_uop_pdst;\n uops_3_is_amo <= io_enq_bits_uop_is_amo;\n uops_3_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_3_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_3_br_mask <= do_enq & _GEN_16 ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;\n if (_GEN_19) begin\n uops_4_uopc <= io_enq_bits_uop_uopc;\n uops_4_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_4_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_4_pdst <= io_enq_bits_uop_pdst;\n uops_4_is_amo <= io_enq_bits_uop_is_amo;\n uops_4_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_4_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_4_br_mask <= do_enq & _GEN_18 ? _uops_br_mask_T_1 : ({8{~valids_4}} | ~io_brupdate_b1_resolve_mask) & uops_4_br_mask;\n end\n ram_5x77 ram_ext (\n .R0_addr (deq_ptr_value),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_ram_ext_R0_data),\n .W0_addr (enq_ptr_value),\n .W0_en (do_enq),\n .W0_clk (clock),\n .W0_data ({io_enq_bits_fflags_bits_flags, io_enq_bits_fflags_bits_uop_rob_idx, io_enq_bits_fflags_valid, 1'h0, io_enq_bits_data})\n );\n assign io_enq_ready = ~full;\n assign io_deq_valid = io_empty_0 ? io_enq_valid : ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~io_flush;\n assign io_deq_bits_uop_uopc = io_empty_0 ? io_enq_bits_uop_uopc : _GEN_1[deq_ptr_value];\n assign io_deq_bits_uop_br_mask = io_empty_0 ? io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : out_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_deq_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_uop_rob_idx : _GEN_3[deq_ptr_value];\n assign io_deq_bits_uop_stq_idx = io_empty_0 ? io_enq_bits_uop_stq_idx : _GEN_4[deq_ptr_value];\n assign io_deq_bits_uop_pdst = io_empty_0 ? io_enq_bits_uop_pdst : _GEN_5[deq_ptr_value];\n assign io_deq_bits_uop_is_amo = io_empty_0 ? io_enq_bits_uop_is_amo : _GEN_6[deq_ptr_value];\n assign io_deq_bits_uop_uses_stq = io_empty_0 ? io_enq_bits_uop_uses_stq : _GEN_7[deq_ptr_value];\n assign io_deq_bits_uop_dst_rtype = io_empty_0 ? io_enq_bits_uop_dst_rtype : _GEN_8[deq_ptr_value];\n assign io_deq_bits_uop_fp_val = io_empty_0 ? io_enq_bits_uop_fp_val : _GEN_9[deq_ptr_value];\n assign io_deq_bits_data = io_empty_0 ? io_enq_bits_data : _ram_ext_R0_data[64:0];\n assign io_deq_bits_predicated = ~io_empty_0 & _ram_ext_R0_data[65];\n assign io_deq_bits_fflags_valid = io_empty_0 ? io_enq_bits_fflags_valid : _ram_ext_R0_data[66];\n assign io_deq_bits_fflags_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_fflags_bits_uop_rob_idx : _ram_ext_R0_data[71:67];\n assign io_deq_bits_fflags_bits_flags = io_empty_0 ? io_enq_bits_fflags_bits_flags : _ram_ext_R0_data[76:72];\n assign io_empty = io_empty_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}", + "response": "module AsyncQueue_TestHarness_UNIQUIFIED(\n input io_enq_clock,\n input io_enq_reset,\n output io_enq_ready,\n input io_enq_valid,\n input [31:0] io_enq_bits_phit,\n input io_deq_clock,\n input io_deq_reset,\n input io_deq_ready,\n output io_deq_valid,\n output [31:0] io_deq_bits_phit\n);\n\n wire [3:0] _sink_io_async_ridx;\n wire _sink_io_async_safe_ridx_valid;\n wire _sink_io_async_safe_sink_reset_n;\n wire [31:0] _source_io_async_mem_0_phit;\n wire [31:0] _source_io_async_mem_1_phit;\n wire [31:0] _source_io_async_mem_2_phit;\n wire [31:0] _source_io_async_mem_3_phit;\n wire [31:0] _source_io_async_mem_4_phit;\n wire [31:0] _source_io_async_mem_5_phit;\n wire [31:0] _source_io_async_mem_6_phit;\n wire [31:0] _source_io_async_mem_7_phit;\n wire [3:0] _source_io_async_widx;\n wire _source_io_async_safe_widx_valid;\n wire _source_io_async_safe_source_reset_n;\n AsyncQueueSource_Phit source (\n .clock (io_enq_clock),\n .reset (io_enq_reset),\n .io_enq_ready (io_enq_ready),\n .io_enq_valid (io_enq_valid),\n .io_enq_bits_phit (io_enq_bits_phit),\n .io_async_mem_0_phit (_source_io_async_mem_0_phit),\n .io_async_mem_1_phit (_source_io_async_mem_1_phit),\n .io_async_mem_2_phit (_source_io_async_mem_2_phit),\n .io_async_mem_3_phit (_source_io_async_mem_3_phit),\n .io_async_mem_4_phit (_source_io_async_mem_4_phit),\n .io_async_mem_5_phit (_source_io_async_mem_5_phit),\n .io_async_mem_6_phit (_source_io_async_mem_6_phit),\n .io_async_mem_7_phit (_source_io_async_mem_7_phit),\n .io_async_ridx (_sink_io_async_ridx),\n .io_async_widx (_source_io_async_widx),\n .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),\n .io_async_safe_widx_valid (_source_io_async_safe_widx_valid),\n .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),\n .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)\n );\n AsyncQueueSink_Phit sink (\n .clock (io_deq_clock),\n .reset (io_deq_reset),\n .io_deq_ready (io_deq_ready),\n .io_deq_valid (io_deq_valid),\n .io_deq_bits_phit (io_deq_bits_phit),\n .io_async_mem_0_phit (_source_io_async_mem_0_phit),\n .io_async_mem_1_phit (_source_io_async_mem_1_phit),\n .io_async_mem_2_phit (_source_io_async_mem_2_phit),\n .io_async_mem_3_phit (_source_io_async_mem_3_phit),\n .io_async_mem_4_phit (_source_io_async_mem_4_phit),\n .io_async_mem_5_phit (_source_io_async_mem_5_phit),\n .io_async_mem_6_phit (_source_io_async_mem_6_phit),\n .io_async_mem_7_phit (_source_io_async_mem_7_phit),\n .io_async_ridx (_sink_io_async_ridx),\n .io_async_widx (_source_io_async_widx),\n .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),\n .io_async_safe_widx_valid (_source_io_async_safe_widx_valid),\n .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),\n .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile.FPConstants._\nimport freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket\nimport freechips.rocketchip.util.uintToBitPat\nimport boom.v3.common._\nimport boom.v3.util.{ImmGenRm, ImmGenTyp}\n\n/**\n * FP Decoder for the FPU\n *\n * TODO get rid of this decoder and move into the Decode stage? Or the RRd stage?\n * most of these signals are already created, just need to be translated\n * to the Rocket FPU-speak\n */\nclass UOPCodeFPUDecoder(implicit p: Parameters) extends BoomModule with HasFPUParameters\n{\n val io = IO(new Bundle {\n val uopc = Input(Bits(UOPC_SZ.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n // TODO change N,Y,X to BitPat(\"b1\"), BitPat(\"b0\"), and BitPat(\"b?\")\n val N = false.B\n val Y = true.B\n val X = false.B\n\n val default: List[BitPat] = List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X)\n\n val f_table: Array[(BitPat, List[BitPat])] =\n // Note: not all of these signals are used or necessary, but we're\n // constrained by the need to fit the rocket.FPU units' ctrl signals.\n // swap12 fma\n // | swap32 | div\n // | | typeTagIn | | sqrt\n // ldst | | | typeTagOut | | wflags\n // | wen | | | | from_int | | |\n // | | ren1 | | | | | to_int | | |\n // | | | ren2 | | | | | | fastpipe |\n // | | | | ren3 | | | | | | | | | |\n // | | | | | | | | | | | | | | | |\n Array(\n BitPat(uopFCLASS_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,N),\n BitPat(uopFMV_W_X) -> List(X,X,N,N,N, X,X,S,D,Y,N,N, N,N,N,N),\n BitPat(uopFMV_X_W) -> List(X,X,Y,N,N, N,X,D,S,N,Y,N, N,N,N,N),\n\n BitPat(uopFCVT_S_X) -> List(X,X,N,N,N, X,X,S,S,Y,N,N, N,N,N,Y),\n\n BitPat(uopFCVT_X_S) -> List(X,X,Y,N,N, N,X,S,S,N,Y,N, N,N,N,Y),\n\n BitPat(uopCMPR_S) -> List(X,X,Y,Y,N, N,N,S,S,N,Y,N, N,N,N,Y),\n\n BitPat(uopFSGNJ_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,N),\n\n BitPat(uopFMINMAX_S)-> List(X,X,Y,Y,N, N,N,S,S,N,N,Y, N,N,N,Y),\n\n BitPat(uopFADD_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFSUB_S) -> List(X,X,Y,Y,N, N,Y,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMUL_S) -> List(X,X,Y,Y,N, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFNMADD_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y),\n BitPat(uopFNMSUB_S) -> List(X,X,Y,Y,Y, N,N,S,S,N,N,N, Y,N,N,Y)\n )\n\n val d_table: Array[(BitPat, List[BitPat])] =\n Array(\n BitPat(uopFCLASS_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),\n BitPat(uopFMV_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,N),\n BitPat(uopFMV_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,N),\n BitPat(uopFCVT_S_D) -> List(X,X,Y,N,N, N,X,D,S,N,N,Y, N,N,N,Y),\n BitPat(uopFCVT_D_S) -> List(X,X,Y,N,N, N,X,S,D,N,N,Y, N,N,N,Y),\n\n BitPat(uopFCVT_D_X) -> List(X,X,N,N,N, X,X,D,D,Y,N,N, N,N,N,Y),\n\n BitPat(uopFCVT_X_D) -> List(X,X,Y,N,N, N,X,D,D,N,Y,N, N,N,N,Y),\n\n BitPat(uopCMPR_D) -> List(X,X,Y,Y,N, N,N,D,D,N,Y,N, N,N,N,Y),\n\n BitPat(uopFSGNJ_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,N),\n\n BitPat(uopFMINMAX_D)-> List(X,X,Y,Y,N, N,N,D,D,N,N,Y, N,N,N,Y),\n\n BitPat(uopFADD_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFSUB_D) -> List(X,X,Y,Y,N, N,Y,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFMUL_D) -> List(X,X,Y,Y,N, N,N,D,D,N,N,N, Y,N,N,Y),\n\n BitPat(uopFMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFNMADD_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y),\n BitPat(uopFNMSUB_D) -> List(X,X,Y,Y,Y, N,N,D,D,N,N,N, Y,N,N,Y)\n )\n\n// val insns = fLen match {\n// case 32 => f_table\n// case 64 => f_table ++ d_table\n// }\n val insns = f_table ++ d_table\n val decoder = rocket.DecodeLogic(io.uopc, default, insns)\n\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,\n s.div, s.sqrt, s.wflags)\n sigs zip decoder map {case(s,d) => s := d}\n s.vec := false.B\n}\n\n/**\n * FP fused multiple add decoder for the FPU\n */\nclass FMADecoder extends Module\n{\n val io = IO(new Bundle {\n val uopc = Input(UInt(UOPC_SZ.W))\n val cmd = Output(UInt(2.W))\n })\n\n val default: List[BitPat] = List(BitPat(\"b??\"))\n val table: Array[(BitPat, List[BitPat])] =\n Array(\n BitPat(uopFADD_S) -> List(BitPat(\"b00\")),\n BitPat(uopFSUB_S) -> List(BitPat(\"b01\")),\n BitPat(uopFMUL_S) -> List(BitPat(\"b00\")),\n BitPat(uopFMADD_S) -> List(BitPat(\"b00\")),\n BitPat(uopFMSUB_S) -> List(BitPat(\"b01\")),\n BitPat(uopFNMADD_S) -> List(BitPat(\"b11\")),\n BitPat(uopFNMSUB_S) -> List(BitPat(\"b10\")),\n BitPat(uopFADD_D) -> List(BitPat(\"b00\")),\n BitPat(uopFSUB_D) -> List(BitPat(\"b01\")),\n BitPat(uopFMUL_D) -> List(BitPat(\"b00\")),\n BitPat(uopFMADD_D) -> List(BitPat(\"b00\")),\n BitPat(uopFMSUB_D) -> List(BitPat(\"b01\")),\n BitPat(uopFNMADD_D) -> List(BitPat(\"b11\")),\n BitPat(uopFNMSUB_D) -> List(BitPat(\"b10\"))\n )\n\n val decoder = rocket.DecodeLogic(io.uopc, default, table)\n\n val (cmd: UInt) :: Nil = decoder\n io.cmd := cmd\n}\n\n/**\n * Bundle representing data to be sent to the FPU\n */\nclass FpuReq()(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val rs1_data = Bits(65.W)\n val rs2_data = Bits(65.W)\n val rs3_data = Bits(65.W)\n val fcsr_rm = Bits(tile.FPConstants.RM_SZ.W)\n}\n\n/**\n * FPU unit that wraps the RocketChip FPU units (which in turn wrap hardfloat)\n */\nclass FPU(implicit p: Parameters) extends BoomModule with tile.HasFPUParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(new ValidIO(new FpuReq))\n val resp = new ValidIO(new ExeUnitResp(65))\n })\n io.resp.bits := DontCare\n\n // all FP units are padded out to the same latency for easy scheduling of the write port\n val fpu_latency = dfmaLatency\n val io_req = io.req.bits\n\n val fp_decoder = Module(new UOPCodeFPUDecoder)\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io_req.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n\n def fuInput(minT: Option[tile.FType]): tile.FPInput = {\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, minT)\n req.in2 := unbox(io_req.rs2_data, tag, minT)\n req.in3 := unbox(io_req.rs3_data, tag, minT)\n when (fp_ctrl.swap23) { req.in3 := req.in2 }\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := Mux(tag === S, 0.U, 1.U) // TODO support Zfh and avoid special-case below\n when (io_req.uop.uopc === uopFMV_X_W) {\n req.fmt := 0.U\n }\n\n val fma_decoder = Module(new FMADecoder)\n fma_decoder.io.uopc := io_req.uop.uopc\n req.fmaCmd := fma_decoder.io.cmd // ex_reg_inst(3,2) | (!fp_ctrl.ren3 && ex_reg_inst(27))\n req\n }\n\n val dfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.D))\n dfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === D)\n dfma.io.in.bits := fuInput(Some(dfma.t))\n\n val sfma = Module(new tile.FPUFMAPipe(latency = fpu_latency, t = tile.FType.S))\n sfma.io.in.valid := io.req.valid && fp_ctrl.fma && (fp_ctrl.typeTagOut === S)\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new tile.FPToInt)\n fpiu.io.in.valid := io.req.valid && (fp_ctrl.toint || (fp_ctrl.fastpipe && fp_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n val fpiu_out = Pipe(RegNext(fpiu.io.in.valid && !fp_ctrl.fastpipe),\n fpiu.io.out.bits, fpu_latency-1)\n val fpiu_result = Wire(new tile.FPResult)\n fpiu_result.data := fpiu_out.bits.toint\n fpiu_result.exc := fpiu_out.bits.exc\n\n val fpmu = Module(new tile.FPToFP(fpu_latency)) // latency 2 for rocket\n fpmu.io.in.valid := io.req.valid && fp_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n val fpmu_double = Pipe(io.req.valid && fp_ctrl.fastpipe, fp_ctrl.typeTagOut === D, fpu_latency).bits\n\n // Response (all FP units have been padded out to the same latency)\n io.resp.valid := fpiu_out.valid ||\n fpmu.io.out.valid ||\n sfma.io.out.valid ||\n dfma.io.out.valid\n val fpu_out_data =\n Mux(dfma.io.out.valid, box(dfma.io.out.bits.data, true.B),\n Mux(sfma.io.out.valid, box(sfma.io.out.bits.data, false.B),\n Mux(fpiu_out.valid, fpiu_result.data,\n box(fpmu.io.out.bits.data, fpmu_double))))\n\n val fpu_out_exc =\n Mux(dfma.io.out.valid, dfma.io.out.bits.exc,\n Mux(sfma.io.out.valid, sfma.io.out.bits.exc,\n Mux(fpiu_out.valid, fpiu_result.exc,\n fpmu.io.out.bits.exc)))\n\n io.resp.bits.data := fpu_out_data\n io.resp.bits.fflags.valid := io.resp.valid\n io.resp.bits.fflags.bits.flags := fpu_out_exc\n}", + "response": "module UOPCodeFPUDecoder(\n input [6:0] io_uopc,\n output io_sigs_ren2,\n output io_sigs_ren3,\n output io_sigs_swap23,\n output [1:0] io_sigs_typeTagIn,\n output [1:0] io_sigs_typeTagOut,\n output io_sigs_fromint,\n output io_sigs_toint,\n output io_sigs_fastpipe,\n output io_sigs_fma,\n output io_sigs_wflags\n);\n\n wire [5:0] decoder_decoded_invInputs = ~(io_uopc[5:0]);\n wire [4:0] _decoder_decoded_andMatrixOutputs_T_3 = {io_uopc[0], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [3:0] _decoder_decoded_andMatrixOutputs_T_14 = {decoder_decoded_invInputs[1], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [4:0] _decoder_decoded_andMatrixOutputs_T_22 = {io_uopc[0], io_uopc[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [3:0] _decoder_decoded_andMatrixOutputs_T_25 = {io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [5:0] _decoder_decoded_andMatrixOutputs_T_27 = {io_uopc[1], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [6:0] _decoder_decoded_andMatrixOutputs_T_28 = {decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]};\n wire [5:0] _decoder_decoded_andMatrixOutputs_T_31 = {decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n wire [4:0] _decoder_decoded_andMatrixOutputs_T_32 = {decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n wire [5:0] _decoder_decoded_andMatrixOutputs_T_33 = {io_uopc[0], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n wire [5:0] _decoder_decoded_andMatrixOutputs_T_34 = {io_uopc[1], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n assign io_sigs_ren2 = |{&{decoder_decoded_invInputs[1], decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_25, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};\n assign io_sigs_ren3 = |{&{io_uopc[0], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[1], io_uopc[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};\n assign io_sigs_swap23 = |{&{io_uopc[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[2], io_uopc[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_27};\n assign io_sigs_typeTagIn = {1'h0, |{&_decoder_decoded_andMatrixOutputs_T_3, &{io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[0], io_uopc[1], decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], io_uopc[1], decoder_decoded_invInputs[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34, &{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}}};\n assign io_sigs_typeTagOut = {1'h0, |{&{decoder_decoded_invInputs[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_3, &{io_uopc[0], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[0], decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_27, &_decoder_decoded_andMatrixOutputs_T_28, &_decoder_decoded_andMatrixOutputs_T_33, &_decoder_decoded_andMatrixOutputs_T_34}};\n assign io_sigs_fromint = &{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]};\n assign io_sigs_toint = |{&{io_uopc[1], io_uopc[2], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}};\n assign io_sigs_fastpipe = |{&{decoder_decoded_invInputs[2], io_uopc[3], decoder_decoded_invInputs[4], decoder_decoded_invInputs[5], io_uopc[6]}, &{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}};\n assign io_sigs_fma = |{&{io_uopc[0], io_uopc[1], io_uopc[2], io_uopc[4], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_25, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};\n assign io_sigs_wflags = |{&{io_uopc[1], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &{io_uopc[2], io_uopc[3], decoder_decoded_invInputs[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_14, &_decoder_decoded_andMatrixOutputs_T_22, &_decoder_decoded_andMatrixOutputs_T_31, &_decoder_decoded_andMatrixOutputs_T_32};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\n\nclass DivSqrtRecF64 extends Module\n{\n val io = IO(new Bundle {\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(Bits(3.W))\n val detectTininess = Input(UInt(1.W))\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(Bits(65.W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val ds = Module(new DivSqrtRecF64_mulAddZ31(0))\n\n io.inReady_div := ds.io.inReady_div\n io.inReady_sqrt := ds.io.inReady_sqrt\n ds.io.inValid := io.inValid\n ds.io.sqrtOp := io.sqrtOp\n ds.io.a := io.a\n ds.io.b := io.b\n ds.io.roundingMode := io.roundingMode\n ds.io.detectTininess := io.detectTininess\n io.outValid_div := ds.io.outValid_div\n io.outValid_sqrt := ds.io.outValid_sqrt\n io.out := ds.io.out\n io.exceptionFlags := ds.io.exceptionFlags\n\n val mul = Module(new Mul54)\n\n mul.io.val_s0 := ds.io.usingMulAdd(0)\n mul.io.latch_a_s0 := ds.io.latchMulAddA_0\n mul.io.a_s0 := ds.io.mulAddA_0\n mul.io.latch_b_s0 := ds.io.latchMulAddB_0\n mul.io.b_s0 := ds.io.mulAddB_0\n mul.io.c_s2 := ds.io.mulAddC_2\n ds.io.mulAddResult_3 := mul.io.result_s3\n}\n\nclass Mul54 extends Module\n{\n val io = IO(new Bundle {\n val val_s0 = Input(Bool())\n val latch_a_s0 = Input(Bool())\n val a_s0 = Input(UInt(54.W))\n val latch_b_s0 = Input(Bool())\n val b_s0 = Input(UInt(54.W))\n val c_s2 = Input(UInt(105.W))\n val result_s3 = Output(UInt(105.W))\n })\n\n val val_s1 = Reg(Bool())\n val val_s2 = Reg(Bool())\n val reg_a_s1 = Reg(UInt(54.W))\n val reg_b_s1 = Reg(UInt(54.W))\n val reg_a_s2 = Reg(UInt(54.W))\n val reg_b_s2 = Reg(UInt(54.W))\n val reg_result_s3 = Reg(UInt(105.W))\n\n val_s1 := io.val_s0\n val_s2 := val_s1\n\n when (io.val_s0) {\n when (io.latch_a_s0) {\n reg_a_s1 := io.a_s0\n }\n when (io.latch_b_s0) {\n reg_b_s1 := io.b_s0\n }\n }\n\n when (val_s1) {\n reg_a_s2 := reg_a_s1\n reg_b_s2 := reg_b_s1\n }\n\n when (val_s2) {\n reg_result_s3 := (reg_a_s2 * reg_b_s2)(104,0) + io.c_s2\n }\n\n io.result_s3 := reg_result_s3\n}", + "response": "module Mul54(\n input clock,\n input io_val_s0,\n input io_latch_a_s0,\n input [53:0] io_a_s0,\n input io_latch_b_s0,\n input [53:0] io_b_s0,\n input [104:0] io_c_s2,\n output [104:0] io_result_s3\n);\n\n reg val_s1;\n reg val_s2;\n reg [53:0] reg_a_s1;\n reg [53:0] reg_b_s1;\n reg [53:0] reg_a_s2;\n reg [53:0] reg_b_s2;\n reg [104:0] reg_result_s3;\n always @(posedge clock) begin\n val_s1 <= io_val_s0;\n val_s2 <= val_s1;\n if (io_val_s0 & io_latch_a_s0)\n reg_a_s1 <= io_a_s0;\n if (io_val_s0 & io_latch_b_s0)\n reg_b_s1 <= io_b_s0;\n if (val_s1) begin\n reg_a_s2 <= reg_a_s1;\n reg_b_s2 <= reg_b_s1;\n end\n if (val_s2)\n reg_result_s3 <= {51'h0, reg_a_s2} * {51'h0, reg_b_s2} + io_c_s2;\n end\n assign io_result_s3 = reg_result_s3;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", + "response": "module ClockCrossingReg_w15(\n input clock,\n input [14:0] io_d,\n output [14:0] io_q,\n input io_en\n);\n\n reg [14:0] cdc_reg;\n always @(posedge clock) begin\n if (io_en)\n cdc_reg <= io_d;\n end\n assign io_q = cdc_reg;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module data_16x65(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [64:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [64:0] W0_data\n);\n\n reg [64:0] Memory[0:15];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2018 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Fetch Buffer\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Takes a FetchBundle and converts into a vector of MicroOps.\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.rocket.{MStatus, BP, BreakpointUnit}\n\nimport boom.v3.common._\nimport boom.v3.util.{BoolToChar, MaskUpper}\n\n/**\n * Bundle that is made up of converted MicroOps from the Fetch Bundle\n * input to the Fetch Buffer. This is handed to the Decode stage.\n */\nclass FetchBufferResp(implicit p: Parameters) extends BoomBundle\n{\n val uops = Vec(coreWidth, Valid(new MicroOp()))\n}\n\n/**\n * Buffer to hold fetched packets and convert them into a vector of MicroOps\n * to give the Decode stage\n *\n * @param num_entries effectively the number of full-sized fetch packets we can hold.\n */\nclass FetchBuffer(implicit p: Parameters) extends BoomModule\n with HasBoomCoreParameters\n with HasBoomFrontendParameters\n{\n val numEntries = numFetchBufferEntries\n val io = IO(new BoomBundle {\n val enq = Flipped(Decoupled(new FetchBundle()))\n val deq = new DecoupledIO(new FetchBufferResp())\n\n // Was the pipeline redirected? Clear/reset the fetchbuffer.\n val clear = Input(Bool())\n })\n\n require (numEntries > fetchWidth)\n require (numEntries % coreWidth == 0)\n val numRows = numEntries / coreWidth\n\n val ram = Reg(Vec(numEntries, new MicroOp))\n ram.suggestName(\"fb_uop_ram\")\n val deq_vec = Wire(Vec(numRows, Vec(coreWidth, new MicroOp)))\n\n val head = RegInit(1.U(numRows.W))\n val tail = RegInit(1.U(numEntries.W))\n\n val maybe_full = RegInit(false.B)\n\n //-------------------------------------------------------------\n // **** Enqueue Uops ****\n //-------------------------------------------------------------\n // Step 1: Convert FetchPacket into a vector of MicroOps.\n // Step 2: Generate one-hot write indices.\n // Step 3: Write MicroOps into the RAM.\n\n def rotateLeft(in: UInt, k: Int) = {\n val n = in.getWidth\n Cat(in(n-k-1,0), in(n-1, n-k))\n }\n\n val might_hit_head = (1 until fetchWidth).map(k => VecInit(rotateLeft(tail, k).asBools.zipWithIndex.filter\n {case (e,i) => i % coreWidth == 0}.map {case (e,i) => e}).asUInt).map(tail => head & tail).reduce(_|_).orR\n val at_head = (VecInit(tail.asBools.zipWithIndex.filter {case (e,i) => i % coreWidth == 0}\n .map {case (e,i) => e}).asUInt & head).orR\n val do_enq = !(at_head && maybe_full || might_hit_head)\n\n io.enq.ready := do_enq\n\n // Input microops.\n val in_mask = Wire(Vec(fetchWidth, Bool()))\n val in_uops = Wire(Vec(fetchWidth, new MicroOp()))\n\n // Step 1: Convert FetchPacket into a vector of MicroOps.\n for (b <- 0 until nBanks) {\n for (w <- 0 until bankWidth) {\n val i = (b * bankWidth) + w\n\n val pc = (bankAlign(io.enq.bits.pc) + (i << 1).U)\n\n in_uops(i) := DontCare\n in_mask(i) := io.enq.valid && io.enq.bits.mask(i)\n in_uops(i).edge_inst := false.B\n in_uops(i).debug_pc := pc\n in_uops(i).pc_lob := pc\n\n in_uops(i).is_sfb := io.enq.bits.sfbs(i) || io.enq.bits.shadowed_mask(i)\n\n if (w == 0) {\n when (io.enq.bits.edge_inst(b)) {\n in_uops(i).debug_pc := bankAlign(io.enq.bits.pc) + (b * bankBytes).U - 2.U\n in_uops(i).pc_lob := bankAlign(io.enq.bits.pc) + (b * bankBytes).U\n in_uops(i).edge_inst := true.B\n }\n }\n in_uops(i).ftq_idx := io.enq.bits.ftq_idx\n in_uops(i).inst := io.enq.bits.exp_insts(i)\n in_uops(i).debug_inst := io.enq.bits.insts(i)\n in_uops(i).is_rvc := io.enq.bits.insts(i)(1,0) =/= 3.U\n in_uops(i).taken := io.enq.bits.cfi_idx.bits === i.U && io.enq.bits.cfi_idx.valid\n\n in_uops(i).xcpt_pf_if := io.enq.bits.xcpt_pf_if\n in_uops(i).xcpt_ae_if := io.enq.bits.xcpt_ae_if\n in_uops(i).bp_debug_if := io.enq.bits.bp_debug_if_oh(i)\n in_uops(i).bp_xcpt_if := io.enq.bits.bp_xcpt_if_oh(i)\n\n in_uops(i).debug_fsrc := io.enq.bits.fsrc\n }\n }\n\n // Step 2. Generate one-hot write indices.\n val enq_idxs = Wire(Vec(fetchWidth, UInt(numEntries.W)))\n\n def inc(ptr: UInt) = {\n val n = ptr.getWidth\n Cat(ptr(n-2,0), ptr(n-1))\n }\n\n var enq_idx = tail\n for (i <- 0 until fetchWidth) {\n enq_idxs(i) := enq_idx\n enq_idx = Mux(in_mask(i), inc(enq_idx), enq_idx)\n }\n\n // Step 3: Write MicroOps into the RAM.\n for (i <- 0 until fetchWidth) {\n for (j <- 0 until numEntries) {\n when (do_enq && in_mask(i) && enq_idxs(i)(j)) {\n ram(j) := in_uops(i)\n }\n }\n }\n\n //-------------------------------------------------------------\n // **** Dequeue Uops ****\n //-------------------------------------------------------------\n\n val tail_collisions = VecInit((0 until numEntries).map(i =>\n head(i/coreWidth) && (!maybe_full || (i % coreWidth != 0).B))).asUInt & tail\n val slot_will_hit_tail = (0 until numRows).map(i => tail_collisions((i+1)*coreWidth-1, i*coreWidth)).reduce(_|_)\n val will_hit_tail = slot_will_hit_tail.orR\n\n val do_deq = io.deq.ready && !will_hit_tail\n\n val deq_valids = (~MaskUpper(slot_will_hit_tail)).asBools\n\n // Generate vec for dequeue read port.\n for (i <- 0 until numEntries) {\n deq_vec(i/coreWidth)(i%coreWidth) := ram(i)\n }\n\n io.deq.bits.uops zip deq_valids map {case (d,v) => d.valid := v}\n io.deq.bits.uops zip Mux1H(head, deq_vec) map {case (d,q) => d.bits := q}\n io.deq.valid := deq_valids.reduce(_||_)\n\n //-------------------------------------------------------------\n // **** Update State ****\n //-------------------------------------------------------------\n\n when (do_enq) {\n tail := enq_idx\n when (in_mask.reduce(_||_)) {\n maybe_full := true.B\n }\n }\n\n when (do_deq) {\n head := inc(head)\n maybe_full := false.B\n }\n\n when (io.clear) {\n head := 1.U\n tail := 1.U\n maybe_full := false.B\n }\n\n // TODO Is this necessary?\n when (reset.asBool) {\n io.deq.bits.uops map { u => u.valid := false.B }\n }\n\n}", + "response": "module FetchBuffer(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [39:0] io_enq_bits_pc,\n input io_enq_bits_edge_inst_0,\n input [31:0] io_enq_bits_insts_0,\n input [31:0] io_enq_bits_insts_1,\n input [31:0] io_enq_bits_insts_2,\n input [31:0] io_enq_bits_insts_3,\n input [31:0] io_enq_bits_exp_insts_0,\n input [31:0] io_enq_bits_exp_insts_1,\n input [31:0] io_enq_bits_exp_insts_2,\n input [31:0] io_enq_bits_exp_insts_3,\n input io_enq_bits_shadowed_mask_0,\n input io_enq_bits_shadowed_mask_1,\n input io_enq_bits_shadowed_mask_2,\n input io_enq_bits_shadowed_mask_3,\n input io_enq_bits_cfi_idx_valid,\n input [1:0] io_enq_bits_cfi_idx_bits,\n input [3:0] io_enq_bits_ftq_idx,\n input [3:0] io_enq_bits_mask,\n input io_enq_bits_xcpt_pf_if,\n input io_enq_bits_xcpt_ae_if,\n input io_enq_bits_bp_debug_if_oh_0,\n input io_enq_bits_bp_debug_if_oh_1,\n input io_enq_bits_bp_debug_if_oh_2,\n input io_enq_bits_bp_debug_if_oh_3,\n input io_enq_bits_bp_xcpt_if_oh_0,\n input io_enq_bits_bp_xcpt_if_oh_1,\n input io_enq_bits_bp_xcpt_if_oh_2,\n input io_enq_bits_bp_xcpt_if_oh_3,\n input [1:0] io_enq_bits_fsrc,\n input io_deq_ready,\n output io_deq_valid,\n output io_deq_bits_uops_0_valid,\n output [31:0] io_deq_bits_uops_0_bits_inst,\n output [31:0] io_deq_bits_uops_0_bits_debug_inst,\n output io_deq_bits_uops_0_bits_is_rvc,\n output [39:0] io_deq_bits_uops_0_bits_debug_pc,\n output io_deq_bits_uops_0_bits_is_sfb,\n output [3:0] io_deq_bits_uops_0_bits_ftq_idx,\n output io_deq_bits_uops_0_bits_edge_inst,\n output [5:0] io_deq_bits_uops_0_bits_pc_lob,\n output io_deq_bits_uops_0_bits_taken,\n output io_deq_bits_uops_0_bits_xcpt_pf_if,\n output io_deq_bits_uops_0_bits_xcpt_ae_if,\n output io_deq_bits_uops_0_bits_bp_debug_if,\n output io_deq_bits_uops_0_bits_bp_xcpt_if,\n output [1:0] io_deq_bits_uops_0_bits_debug_fsrc,\n input io_clear\n);\n\n reg [31:0] fb_uop_ram_0_inst;\n reg [31:0] fb_uop_ram_0_debug_inst;\n reg fb_uop_ram_0_is_rvc;\n reg [39:0] fb_uop_ram_0_debug_pc;\n reg fb_uop_ram_0_is_sfb;\n reg [3:0] fb_uop_ram_0_ftq_idx;\n reg fb_uop_ram_0_edge_inst;\n reg [5:0] fb_uop_ram_0_pc_lob;\n reg fb_uop_ram_0_taken;\n reg fb_uop_ram_0_xcpt_pf_if;\n reg fb_uop_ram_0_xcpt_ae_if;\n reg fb_uop_ram_0_bp_debug_if;\n reg fb_uop_ram_0_bp_xcpt_if;\n reg [1:0] fb_uop_ram_0_debug_fsrc;\n reg [31:0] fb_uop_ram_1_inst;\n reg [31:0] fb_uop_ram_1_debug_inst;\n reg fb_uop_ram_1_is_rvc;\n reg [39:0] fb_uop_ram_1_debug_pc;\n reg fb_uop_ram_1_is_sfb;\n reg [3:0] fb_uop_ram_1_ftq_idx;\n reg fb_uop_ram_1_edge_inst;\n reg [5:0] fb_uop_ram_1_pc_lob;\n reg fb_uop_ram_1_taken;\n reg fb_uop_ram_1_xcpt_pf_if;\n reg fb_uop_ram_1_xcpt_ae_if;\n reg fb_uop_ram_1_bp_debug_if;\n reg fb_uop_ram_1_bp_xcpt_if;\n reg [1:0] fb_uop_ram_1_debug_fsrc;\n reg [31:0] fb_uop_ram_2_inst;\n reg [31:0] fb_uop_ram_2_debug_inst;\n reg fb_uop_ram_2_is_rvc;\n reg [39:0] fb_uop_ram_2_debug_pc;\n reg fb_uop_ram_2_is_sfb;\n reg [3:0] fb_uop_ram_2_ftq_idx;\n reg fb_uop_ram_2_edge_inst;\n reg [5:0] fb_uop_ram_2_pc_lob;\n reg fb_uop_ram_2_taken;\n reg fb_uop_ram_2_xcpt_pf_if;\n reg fb_uop_ram_2_xcpt_ae_if;\n reg fb_uop_ram_2_bp_debug_if;\n reg fb_uop_ram_2_bp_xcpt_if;\n reg [1:0] fb_uop_ram_2_debug_fsrc;\n reg [31:0] fb_uop_ram_3_inst;\n reg [31:0] fb_uop_ram_3_debug_inst;\n reg fb_uop_ram_3_is_rvc;\n reg [39:0] fb_uop_ram_3_debug_pc;\n reg fb_uop_ram_3_is_sfb;\n reg [3:0] fb_uop_ram_3_ftq_idx;\n reg fb_uop_ram_3_edge_inst;\n reg [5:0] fb_uop_ram_3_pc_lob;\n reg fb_uop_ram_3_taken;\n reg fb_uop_ram_3_xcpt_pf_if;\n reg fb_uop_ram_3_xcpt_ae_if;\n reg fb_uop_ram_3_bp_debug_if;\n reg fb_uop_ram_3_bp_xcpt_if;\n reg [1:0] fb_uop_ram_3_debug_fsrc;\n reg [31:0] fb_uop_ram_4_inst;\n reg [31:0] fb_uop_ram_4_debug_inst;\n reg fb_uop_ram_4_is_rvc;\n reg [39:0] fb_uop_ram_4_debug_pc;\n reg fb_uop_ram_4_is_sfb;\n reg [3:0] fb_uop_ram_4_ftq_idx;\n reg fb_uop_ram_4_edge_inst;\n reg [5:0] fb_uop_ram_4_pc_lob;\n reg fb_uop_ram_4_taken;\n reg fb_uop_ram_4_xcpt_pf_if;\n reg fb_uop_ram_4_xcpt_ae_if;\n reg fb_uop_ram_4_bp_debug_if;\n reg fb_uop_ram_4_bp_xcpt_if;\n reg [1:0] fb_uop_ram_4_debug_fsrc;\n reg [31:0] fb_uop_ram_5_inst;\n reg [31:0] fb_uop_ram_5_debug_inst;\n reg fb_uop_ram_5_is_rvc;\n reg [39:0] fb_uop_ram_5_debug_pc;\n reg fb_uop_ram_5_is_sfb;\n reg [3:0] fb_uop_ram_5_ftq_idx;\n reg fb_uop_ram_5_edge_inst;\n reg [5:0] fb_uop_ram_5_pc_lob;\n reg fb_uop_ram_5_taken;\n reg fb_uop_ram_5_xcpt_pf_if;\n reg fb_uop_ram_5_xcpt_ae_if;\n reg fb_uop_ram_5_bp_debug_if;\n reg fb_uop_ram_5_bp_xcpt_if;\n reg [1:0] fb_uop_ram_5_debug_fsrc;\n reg [31:0] fb_uop_ram_6_inst;\n reg [31:0] fb_uop_ram_6_debug_inst;\n reg fb_uop_ram_6_is_rvc;\n reg [39:0] fb_uop_ram_6_debug_pc;\n reg fb_uop_ram_6_is_sfb;\n reg [3:0] fb_uop_ram_6_ftq_idx;\n reg fb_uop_ram_6_edge_inst;\n reg [5:0] fb_uop_ram_6_pc_lob;\n reg fb_uop_ram_6_taken;\n reg fb_uop_ram_6_xcpt_pf_if;\n reg fb_uop_ram_6_xcpt_ae_if;\n reg fb_uop_ram_6_bp_debug_if;\n reg fb_uop_ram_6_bp_xcpt_if;\n reg [1:0] fb_uop_ram_6_debug_fsrc;\n reg [31:0] fb_uop_ram_7_inst;\n reg [31:0] fb_uop_ram_7_debug_inst;\n reg fb_uop_ram_7_is_rvc;\n reg [39:0] fb_uop_ram_7_debug_pc;\n reg fb_uop_ram_7_is_sfb;\n reg [3:0] fb_uop_ram_7_ftq_idx;\n reg fb_uop_ram_7_edge_inst;\n reg [5:0] fb_uop_ram_7_pc_lob;\n reg fb_uop_ram_7_taken;\n reg fb_uop_ram_7_xcpt_pf_if;\n reg fb_uop_ram_7_xcpt_ae_if;\n reg fb_uop_ram_7_bp_debug_if;\n reg fb_uop_ram_7_bp_xcpt_if;\n reg [1:0] fb_uop_ram_7_debug_fsrc;\n reg [7:0] head;\n reg [7:0] tail;\n reg maybe_full;\n wire do_enq = {(|(tail & head)) & maybe_full, head & {tail[6:0], tail[7]} | head & {tail[5:0], tail[7:6]} | head & {tail[4:0], tail[7:5]}} == 9'h0;\n wire will_hit_tail = head[0] & ~maybe_full & tail[0] | head[1] & ~maybe_full & tail[1] | head[2] & ~maybe_full & tail[2] | head[3] & ~maybe_full & tail[3] | head[4] & ~maybe_full & tail[4] | head[5] & ~maybe_full & tail[5] | head[6] & ~maybe_full & tail[6] | head[7] & ~maybe_full & tail[7];\n wire do_deq = io_deq_ready & ~will_hit_tail;\n wire in_mask_0 = io_enq_valid & io_enq_bits_mask[0];\n wire [39:0] _GEN = {io_enq_bits_pc[39:3], 3'h0};\n wire [39:0] in_uops_0_debug_pc = io_enq_bits_edge_inst_0 ? _GEN - 40'h2 : {io_enq_bits_pc[39:3], 3'h0};\n wire [5:0] in_uops_0_pc_lob = {io_enq_bits_pc[5:3], 3'h0};\n wire in_uops_0_is_rvc = io_enq_bits_insts_0[1:0] != 2'h3;\n wire in_uops_0_taken = io_enq_bits_cfi_idx_bits == 2'h0 & io_enq_bits_cfi_idx_valid;\n wire [39:0] _pc_T_7 = _GEN + 40'h2;\n wire in_mask_1 = io_enq_valid & io_enq_bits_mask[1];\n wire in_uops_1_is_rvc = io_enq_bits_insts_1[1:0] != 2'h3;\n wire in_uops_1_taken = io_enq_bits_cfi_idx_bits == 2'h1 & io_enq_bits_cfi_idx_valid;\n wire [39:0] _pc_T_11 = _GEN + 40'h4;\n wire in_mask_2 = io_enq_valid & io_enq_bits_mask[2];\n wire in_uops_2_is_rvc = io_enq_bits_insts_2[1:0] != 2'h3;\n wire in_uops_2_taken = io_enq_bits_cfi_idx_bits == 2'h2 & io_enq_bits_cfi_idx_valid;\n wire [39:0] _pc_T_15 = _GEN + 40'h6;\n wire in_mask_3 = io_enq_valid & io_enq_bits_mask[3];\n wire in_uops_3_is_rvc = io_enq_bits_insts_3[1:0] != 2'h3;\n wire in_uops_3_taken = (&io_enq_bits_cfi_idx_bits) & io_enq_bits_cfi_idx_valid;\n wire [7:0] _GEN_0 = {tail[6:0], tail[7]};\n wire [7:0] enq_idxs_1 = in_mask_0 ? _GEN_0 : tail;\n wire [7:0] _GEN_1 = {enq_idxs_1[6:0], enq_idxs_1[7]};\n wire [7:0] enq_idxs_2 = in_mask_1 ? _GEN_1 : enq_idxs_1;\n wire [7:0] _GEN_2 = {enq_idxs_2[6:0], enq_idxs_2[7]};\n wire [7:0] enq_idxs_3 = in_mask_2 ? _GEN_2 : enq_idxs_2;\n wire _GEN_3 = do_enq & in_mask_0;\n wire _GEN_4 = _GEN_3 & tail[0];\n wire _GEN_5 = _GEN_3 & tail[1];\n wire _GEN_6 = _GEN_3 & tail[2];\n wire _GEN_7 = _GEN_3 & tail[3];\n wire _GEN_8 = _GEN_3 & tail[4];\n wire _GEN_9 = _GEN_3 & tail[5];\n wire _GEN_10 = _GEN_3 & tail[6];\n wire _GEN_11 = _GEN_3 & tail[7];\n wire _GEN_12 = do_enq & in_mask_1;\n wire _GEN_13 = _GEN_12 & enq_idxs_1[0];\n wire _GEN_14 = _GEN_12 & enq_idxs_1[1];\n wire _GEN_15 = _GEN_12 & enq_idxs_1[2];\n wire _GEN_16 = _GEN_12 & enq_idxs_1[3];\n wire _GEN_17 = _GEN_12 & enq_idxs_1[4];\n wire _GEN_18 = _GEN_12 & enq_idxs_1[5];\n wire _GEN_19 = _GEN_12 & enq_idxs_1[6];\n wire _GEN_20 = _GEN_12 & enq_idxs_1[7];\n wire _GEN_21 = do_enq & in_mask_2;\n wire _GEN_22 = _GEN_21 & enq_idxs_2[0];\n wire _GEN_23 = _GEN_21 & enq_idxs_2[1];\n wire _GEN_24 = _GEN_21 & enq_idxs_2[2];\n wire _GEN_25 = _GEN_21 & enq_idxs_2[3];\n wire _GEN_26 = _GEN_21 & enq_idxs_2[4];\n wire _GEN_27 = _GEN_21 & enq_idxs_2[5];\n wire _GEN_28 = _GEN_21 & enq_idxs_2[6];\n wire _GEN_29 = _GEN_21 & enq_idxs_2[7];\n wire _GEN_30 = do_enq & in_mask_3;\n wire _GEN_31 = _GEN_30 & enq_idxs_3[0];\n wire _GEN_32 = _GEN_30 & enq_idxs_3[1];\n wire _GEN_33 = _GEN_30 & enq_idxs_3[2];\n wire _GEN_34 = _GEN_30 & enq_idxs_3[3];\n wire _GEN_35 = _GEN_30 & enq_idxs_3[4];\n wire _GEN_36 = _GEN_30 & enq_idxs_3[5];\n wire _GEN_37 = _GEN_30 & enq_idxs_3[6];\n wire _GEN_38 = _GEN_30 & enq_idxs_3[7];\n always @(posedge clock) begin\n if (_GEN_31) begin\n fb_uop_ram_0_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_0_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_0_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_0_debug_pc <= _pc_T_15;\n fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_0_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_0_taken <= in_uops_3_taken;\n fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_22) begin\n fb_uop_ram_0_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_0_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_0_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_0_debug_pc <= _pc_T_11;\n fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_0_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_0_taken <= in_uops_2_taken;\n fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_13) begin\n fb_uop_ram_0_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_0_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_0_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_0_debug_pc <= _pc_T_7;\n fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_0_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_0_taken <= in_uops_1_taken;\n fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_4) begin\n fb_uop_ram_0_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_0_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_0_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_0_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_0_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_0_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_0_taken <= in_uops_0_taken;\n fb_uop_ram_0_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_0_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_31 | _GEN_22 | _GEN_13 | _GEN_4) begin\n fb_uop_ram_0_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_0_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_0_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_0_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_0_edge_inst <= ~(_GEN_31 | _GEN_22 | _GEN_13) & (_GEN_4 ? io_enq_bits_edge_inst_0 : fb_uop_ram_0_edge_inst);\n if (_GEN_32) begin\n fb_uop_ram_1_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_1_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_1_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_1_debug_pc <= _pc_T_15;\n fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_1_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_1_taken <= in_uops_3_taken;\n fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_23) begin\n fb_uop_ram_1_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_1_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_1_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_1_debug_pc <= _pc_T_11;\n fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_1_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_1_taken <= in_uops_2_taken;\n fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_14) begin\n fb_uop_ram_1_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_1_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_1_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_1_debug_pc <= _pc_T_7;\n fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_1_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_1_taken <= in_uops_1_taken;\n fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_5) begin\n fb_uop_ram_1_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_1_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_1_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_1_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_1_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_1_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_1_taken <= in_uops_0_taken;\n fb_uop_ram_1_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_1_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_32 | _GEN_23 | _GEN_14 | _GEN_5) begin\n fb_uop_ram_1_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_1_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_1_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_1_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_1_edge_inst <= ~(_GEN_32 | _GEN_23 | _GEN_14) & (_GEN_5 ? io_enq_bits_edge_inst_0 : fb_uop_ram_1_edge_inst);\n if (_GEN_33) begin\n fb_uop_ram_2_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_2_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_2_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_2_debug_pc <= _pc_T_15;\n fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_2_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_2_taken <= in_uops_3_taken;\n fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_24) begin\n fb_uop_ram_2_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_2_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_2_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_2_debug_pc <= _pc_T_11;\n fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_2_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_2_taken <= in_uops_2_taken;\n fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_15) begin\n fb_uop_ram_2_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_2_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_2_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_2_debug_pc <= _pc_T_7;\n fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_2_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_2_taken <= in_uops_1_taken;\n fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_6) begin\n fb_uop_ram_2_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_2_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_2_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_2_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_2_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_2_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_2_taken <= in_uops_0_taken;\n fb_uop_ram_2_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_2_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_33 | _GEN_24 | _GEN_15 | _GEN_6) begin\n fb_uop_ram_2_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_2_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_2_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_2_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_2_edge_inst <= ~(_GEN_33 | _GEN_24 | _GEN_15) & (_GEN_6 ? io_enq_bits_edge_inst_0 : fb_uop_ram_2_edge_inst);\n if (_GEN_34) begin\n fb_uop_ram_3_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_3_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_3_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_3_debug_pc <= _pc_T_15;\n fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_3_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_3_taken <= in_uops_3_taken;\n fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_25) begin\n fb_uop_ram_3_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_3_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_3_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_3_debug_pc <= _pc_T_11;\n fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_3_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_3_taken <= in_uops_2_taken;\n fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_16) begin\n fb_uop_ram_3_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_3_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_3_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_3_debug_pc <= _pc_T_7;\n fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_3_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_3_taken <= in_uops_1_taken;\n fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_7) begin\n fb_uop_ram_3_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_3_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_3_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_3_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_3_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_3_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_3_taken <= in_uops_0_taken;\n fb_uop_ram_3_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_3_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_34 | _GEN_25 | _GEN_16 | _GEN_7) begin\n fb_uop_ram_3_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_3_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_3_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_3_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_3_edge_inst <= ~(_GEN_34 | _GEN_25 | _GEN_16) & (_GEN_7 ? io_enq_bits_edge_inst_0 : fb_uop_ram_3_edge_inst);\n if (_GEN_35) begin\n fb_uop_ram_4_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_4_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_4_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_4_debug_pc <= _pc_T_15;\n fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_4_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_4_taken <= in_uops_3_taken;\n fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_26) begin\n fb_uop_ram_4_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_4_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_4_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_4_debug_pc <= _pc_T_11;\n fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_4_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_4_taken <= in_uops_2_taken;\n fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_17) begin\n fb_uop_ram_4_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_4_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_4_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_4_debug_pc <= _pc_T_7;\n fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_4_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_4_taken <= in_uops_1_taken;\n fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_8) begin\n fb_uop_ram_4_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_4_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_4_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_4_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_4_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_4_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_4_taken <= in_uops_0_taken;\n fb_uop_ram_4_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_4_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_35 | _GEN_26 | _GEN_17 | _GEN_8) begin\n fb_uop_ram_4_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_4_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_4_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_4_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_4_edge_inst <= ~(_GEN_35 | _GEN_26 | _GEN_17) & (_GEN_8 ? io_enq_bits_edge_inst_0 : fb_uop_ram_4_edge_inst);\n if (_GEN_36) begin\n fb_uop_ram_5_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_5_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_5_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_5_debug_pc <= _pc_T_15;\n fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_5_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_5_taken <= in_uops_3_taken;\n fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_27) begin\n fb_uop_ram_5_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_5_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_5_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_5_debug_pc <= _pc_T_11;\n fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_5_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_5_taken <= in_uops_2_taken;\n fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_18) begin\n fb_uop_ram_5_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_5_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_5_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_5_debug_pc <= _pc_T_7;\n fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_5_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_5_taken <= in_uops_1_taken;\n fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_9) begin\n fb_uop_ram_5_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_5_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_5_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_5_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_5_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_5_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_5_taken <= in_uops_0_taken;\n fb_uop_ram_5_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_5_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_36 | _GEN_27 | _GEN_18 | _GEN_9) begin\n fb_uop_ram_5_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_5_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_5_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_5_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_5_edge_inst <= ~(_GEN_36 | _GEN_27 | _GEN_18) & (_GEN_9 ? io_enq_bits_edge_inst_0 : fb_uop_ram_5_edge_inst);\n if (_GEN_37) begin\n fb_uop_ram_6_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_6_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_6_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_6_debug_pc <= _pc_T_15;\n fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_6_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_6_taken <= in_uops_3_taken;\n fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_28) begin\n fb_uop_ram_6_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_6_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_6_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_6_debug_pc <= _pc_T_11;\n fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_6_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_6_taken <= in_uops_2_taken;\n fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_19) begin\n fb_uop_ram_6_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_6_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_6_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_6_debug_pc <= _pc_T_7;\n fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_6_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_6_taken <= in_uops_1_taken;\n fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_10) begin\n fb_uop_ram_6_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_6_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_6_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_6_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_6_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_6_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_6_taken <= in_uops_0_taken;\n fb_uop_ram_6_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_6_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_37 | _GEN_28 | _GEN_19 | _GEN_10) begin\n fb_uop_ram_6_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_6_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_6_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_6_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_6_edge_inst <= ~(_GEN_37 | _GEN_28 | _GEN_19) & (_GEN_10 ? io_enq_bits_edge_inst_0 : fb_uop_ram_6_edge_inst);\n if (_GEN_38) begin\n fb_uop_ram_7_inst <= io_enq_bits_exp_insts_3;\n fb_uop_ram_7_debug_inst <= io_enq_bits_insts_3;\n fb_uop_ram_7_is_rvc <= in_uops_3_is_rvc;\n fb_uop_ram_7_debug_pc <= _pc_T_15;\n fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_3;\n fb_uop_ram_7_pc_lob <= _pc_T_15[5:0];\n fb_uop_ram_7_taken <= in_uops_3_taken;\n fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_3;\n fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_3;\n end\n else if (_GEN_29) begin\n fb_uop_ram_7_inst <= io_enq_bits_exp_insts_2;\n fb_uop_ram_7_debug_inst <= io_enq_bits_insts_2;\n fb_uop_ram_7_is_rvc <= in_uops_2_is_rvc;\n fb_uop_ram_7_debug_pc <= _pc_T_11;\n fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_2;\n fb_uop_ram_7_pc_lob <= _pc_T_11[5:0];\n fb_uop_ram_7_taken <= in_uops_2_taken;\n fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_2;\n fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_2;\n end\n else if (_GEN_20) begin\n fb_uop_ram_7_inst <= io_enq_bits_exp_insts_1;\n fb_uop_ram_7_debug_inst <= io_enq_bits_insts_1;\n fb_uop_ram_7_is_rvc <= in_uops_1_is_rvc;\n fb_uop_ram_7_debug_pc <= _pc_T_7;\n fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_1;\n fb_uop_ram_7_pc_lob <= _pc_T_7[5:0];\n fb_uop_ram_7_taken <= in_uops_1_taken;\n fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_1;\n fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_1;\n end\n else if (_GEN_11) begin\n fb_uop_ram_7_inst <= io_enq_bits_exp_insts_0;\n fb_uop_ram_7_debug_inst <= io_enq_bits_insts_0;\n fb_uop_ram_7_is_rvc <= in_uops_0_is_rvc;\n fb_uop_ram_7_debug_pc <= in_uops_0_debug_pc;\n fb_uop_ram_7_is_sfb <= io_enq_bits_shadowed_mask_0;\n fb_uop_ram_7_pc_lob <= in_uops_0_pc_lob;\n fb_uop_ram_7_taken <= in_uops_0_taken;\n fb_uop_ram_7_bp_debug_if <= io_enq_bits_bp_debug_if_oh_0;\n fb_uop_ram_7_bp_xcpt_if <= io_enq_bits_bp_xcpt_if_oh_0;\n end\n if (_GEN_38 | _GEN_29 | _GEN_20 | _GEN_11) begin\n fb_uop_ram_7_ftq_idx <= io_enq_bits_ftq_idx;\n fb_uop_ram_7_xcpt_pf_if <= io_enq_bits_xcpt_pf_if;\n fb_uop_ram_7_xcpt_ae_if <= io_enq_bits_xcpt_ae_if;\n fb_uop_ram_7_debug_fsrc <= io_enq_bits_fsrc;\n end\n fb_uop_ram_7_edge_inst <= ~(_GEN_38 | _GEN_29 | _GEN_20) & (_GEN_11 ? io_enq_bits_edge_inst_0 : fb_uop_ram_7_edge_inst);\n if (reset) begin\n head <= 8'h1;\n tail <= 8'h1;\n maybe_full <= 1'h0;\n end\n else begin\n if (io_clear) begin\n head <= 8'h1;\n tail <= 8'h1;\n end\n else begin\n if (do_deq)\n head <= {head[6:0], head[7]};\n if (do_enq) begin\n if (in_mask_3)\n tail <= {enq_idxs_3[6:0], enq_idxs_3[7]};\n else if (in_mask_2)\n tail <= _GEN_2;\n else if (in_mask_1)\n tail <= _GEN_1;\n else if (in_mask_0)\n tail <= _GEN_0;\n end\n end\n maybe_full <= ~(io_clear | do_deq) & (do_enq & (in_mask_0 | in_mask_1 | in_mask_2 | in_mask_3) | maybe_full);\n end\n end\n assign io_enq_ready = do_enq;\n assign io_deq_valid = ~will_hit_tail;\n assign io_deq_bits_uops_0_valid = ~reset & ~will_hit_tail;\n assign io_deq_bits_uops_0_bits_inst = (head[0] ? fb_uop_ram_0_inst : 32'h0) | (head[1] ? fb_uop_ram_1_inst : 32'h0) | (head[2] ? fb_uop_ram_2_inst : 32'h0) | (head[3] ? fb_uop_ram_3_inst : 32'h0) | (head[4] ? fb_uop_ram_4_inst : 32'h0) | (head[5] ? fb_uop_ram_5_inst : 32'h0) | (head[6] ? fb_uop_ram_6_inst : 32'h0) | (head[7] ? fb_uop_ram_7_inst : 32'h0);\n assign io_deq_bits_uops_0_bits_debug_inst = (head[0] ? fb_uop_ram_0_debug_inst : 32'h0) | (head[1] ? fb_uop_ram_1_debug_inst : 32'h0) | (head[2] ? fb_uop_ram_2_debug_inst : 32'h0) | (head[3] ? fb_uop_ram_3_debug_inst : 32'h0) | (head[4] ? fb_uop_ram_4_debug_inst : 32'h0) | (head[5] ? fb_uop_ram_5_debug_inst : 32'h0) | (head[6] ? fb_uop_ram_6_debug_inst : 32'h0) | (head[7] ? fb_uop_ram_7_debug_inst : 32'h0);\n assign io_deq_bits_uops_0_bits_is_rvc = head[0] & fb_uop_ram_0_is_rvc | head[1] & fb_uop_ram_1_is_rvc | head[2] & fb_uop_ram_2_is_rvc | head[3] & fb_uop_ram_3_is_rvc | head[4] & fb_uop_ram_4_is_rvc | head[5] & fb_uop_ram_5_is_rvc | head[6] & fb_uop_ram_6_is_rvc | head[7] & fb_uop_ram_7_is_rvc;\n assign io_deq_bits_uops_0_bits_debug_pc = (head[0] ? fb_uop_ram_0_debug_pc : 40'h0) | (head[1] ? fb_uop_ram_1_debug_pc : 40'h0) | (head[2] ? fb_uop_ram_2_debug_pc : 40'h0) | (head[3] ? fb_uop_ram_3_debug_pc : 40'h0) | (head[4] ? fb_uop_ram_4_debug_pc : 40'h0) | (head[5] ? fb_uop_ram_5_debug_pc : 40'h0) | (head[6] ? fb_uop_ram_6_debug_pc : 40'h0) | (head[7] ? fb_uop_ram_7_debug_pc : 40'h0);\n assign io_deq_bits_uops_0_bits_is_sfb = head[0] & fb_uop_ram_0_is_sfb | head[1] & fb_uop_ram_1_is_sfb | head[2] & fb_uop_ram_2_is_sfb | head[3] & fb_uop_ram_3_is_sfb | head[4] & fb_uop_ram_4_is_sfb | head[5] & fb_uop_ram_5_is_sfb | head[6] & fb_uop_ram_6_is_sfb | head[7] & fb_uop_ram_7_is_sfb;\n assign io_deq_bits_uops_0_bits_ftq_idx = (head[0] ? fb_uop_ram_0_ftq_idx : 4'h0) | (head[1] ? fb_uop_ram_1_ftq_idx : 4'h0) | (head[2] ? fb_uop_ram_2_ftq_idx : 4'h0) | (head[3] ? fb_uop_ram_3_ftq_idx : 4'h0) | (head[4] ? fb_uop_ram_4_ftq_idx : 4'h0) | (head[5] ? fb_uop_ram_5_ftq_idx : 4'h0) | (head[6] ? fb_uop_ram_6_ftq_idx : 4'h0) | (head[7] ? fb_uop_ram_7_ftq_idx : 4'h0);\n assign io_deq_bits_uops_0_bits_edge_inst = head[0] & fb_uop_ram_0_edge_inst | head[1] & fb_uop_ram_1_edge_inst | head[2] & fb_uop_ram_2_edge_inst | head[3] & fb_uop_ram_3_edge_inst | head[4] & fb_uop_ram_4_edge_inst | head[5] & fb_uop_ram_5_edge_inst | head[6] & fb_uop_ram_6_edge_inst | head[7] & fb_uop_ram_7_edge_inst;\n assign io_deq_bits_uops_0_bits_pc_lob = (head[0] ? fb_uop_ram_0_pc_lob : 6'h0) | (head[1] ? fb_uop_ram_1_pc_lob : 6'h0) | (head[2] ? fb_uop_ram_2_pc_lob : 6'h0) | (head[3] ? fb_uop_ram_3_pc_lob : 6'h0) | (head[4] ? fb_uop_ram_4_pc_lob : 6'h0) | (head[5] ? fb_uop_ram_5_pc_lob : 6'h0) | (head[6] ? fb_uop_ram_6_pc_lob : 6'h0) | (head[7] ? fb_uop_ram_7_pc_lob : 6'h0);\n assign io_deq_bits_uops_0_bits_taken = head[0] & fb_uop_ram_0_taken | head[1] & fb_uop_ram_1_taken | head[2] & fb_uop_ram_2_taken | head[3] & fb_uop_ram_3_taken | head[4] & fb_uop_ram_4_taken | head[5] & fb_uop_ram_5_taken | head[6] & fb_uop_ram_6_taken | head[7] & fb_uop_ram_7_taken;\n assign io_deq_bits_uops_0_bits_xcpt_pf_if = head[0] & fb_uop_ram_0_xcpt_pf_if | head[1] & fb_uop_ram_1_xcpt_pf_if | head[2] & fb_uop_ram_2_xcpt_pf_if | head[3] & fb_uop_ram_3_xcpt_pf_if | head[4] & fb_uop_ram_4_xcpt_pf_if | head[5] & fb_uop_ram_5_xcpt_pf_if | head[6] & fb_uop_ram_6_xcpt_pf_if | head[7] & fb_uop_ram_7_xcpt_pf_if;\n assign io_deq_bits_uops_0_bits_xcpt_ae_if = head[0] & fb_uop_ram_0_xcpt_ae_if | head[1] & fb_uop_ram_1_xcpt_ae_if | head[2] & fb_uop_ram_2_xcpt_ae_if | head[3] & fb_uop_ram_3_xcpt_ae_if | head[4] & fb_uop_ram_4_xcpt_ae_if | head[5] & fb_uop_ram_5_xcpt_ae_if | head[6] & fb_uop_ram_6_xcpt_ae_if | head[7] & fb_uop_ram_7_xcpt_ae_if;\n assign io_deq_bits_uops_0_bits_bp_debug_if = head[0] & fb_uop_ram_0_bp_debug_if | head[1] & fb_uop_ram_1_bp_debug_if | head[2] & fb_uop_ram_2_bp_debug_if | head[3] & fb_uop_ram_3_bp_debug_if | head[4] & fb_uop_ram_4_bp_debug_if | head[5] & fb_uop_ram_5_bp_debug_if | head[6] & fb_uop_ram_6_bp_debug_if | head[7] & fb_uop_ram_7_bp_debug_if;\n assign io_deq_bits_uops_0_bits_bp_xcpt_if = head[0] & fb_uop_ram_0_bp_xcpt_if | head[1] & fb_uop_ram_1_bp_xcpt_if | head[2] & fb_uop_ram_2_bp_xcpt_if | head[3] & fb_uop_ram_3_bp_xcpt_if | head[4] & fb_uop_ram_4_bp_xcpt_if | head[5] & fb_uop_ram_5_bp_xcpt_if | head[6] & fb_uop_ram_6_bp_xcpt_if | head[7] & fb_uop_ram_7_bp_xcpt_if;\n assign io_deq_bits_uops_0_bits_debug_fsrc = (head[0] ? fb_uop_ram_0_debug_fsrc : 2'h0) | (head[1] ? fb_uop_ram_1_debug_fsrc : 2'h0) | (head[2] ? fb_uop_ram_2_debug_fsrc : 2'h0) | (head[3] ? fb_uop_ram_3_debug_fsrc : 2'h0) | (head[4] ? fb_uop_ram_4_debug_fsrc : 2'h0) | (head[5] ? fb_uop_ram_5_debug_fsrc : 2'h0) | (head[6] ? fb_uop_ram_6_debug_fsrc : 2'h0) | (head[7] ? fb_uop_ram_7_debug_fsrc : 2'h0);\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable_3(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [11:0] table_MPORT_data_3;\n wire [11:0] table_MPORT_data_2;\n wire [11:0] table_MPORT_data_1;\n wire [11:0] table_MPORT_data_0;\n wire [47:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [7:0] reset_idx;\n wire [7:0] s1_hashed_idx = io_f1_req_pc[10:3] ^ io_f1_req_ghist[7:0] ^ io_f1_req_ghist[15:8];\n reg [7:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [19:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[19];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[19]);\n wire [7:0] update_idx = io_update_pc[10:3] ^ io_update_hist[7:0] ^ io_update_hist[15:8];\n wire [7:0] update_tag = io_update_pc[18:11] ^ io_update_hist[7:0] ^ io_update_hist[15:8];\n assign table_MPORT_data_0 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_3_ctr};\n wire _GEN = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;\n wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_1 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;\n reg [7:0] wrbypass_tags_0;\n reg [7:0] wrbypass_tags_1;\n reg [7:0] wrbypass_idxs_0;\n reg [7:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 8'h0;\n clear_u_ctr <= 20'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 8'hFF & doing_reset;\n reset_idx <= reset_idx + {7'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 20'h1 : clear_u_ctr + 20'h1;\n if (~_GEN_6 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= io_f1_req_pc[18:11] ^ io_f1_req_ghist[7:0] ^ io_f1_req_ghist[15:8];\n io_f3_resp_0_valid_REG <= _table_R0_data[11] & _table_R0_data[10:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[23] & _table_R0_data[22:15] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[14:12];\n io_f3_resp_2_valid_REG <= _table_R0_data[35] & _table_R0_data[34:27] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[26:24];\n io_f3_resp_3_valid_REG <= _table_R0_data[47] & _table_R0_data[46:39] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[38:36];\n if (_GEN_7) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_8) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_7) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_8) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_6) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us_2 hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[18:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN ? 4'hF : _GEN_0)\n );\n lo_us_2 lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[18:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_1 ? 4'hF : _GEN_0)\n );\n table_2 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module FlitToPhit_f32_p32_TestHarness_UNIQUIFIED(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_phit\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_phit = io_in_bits_flit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Register File (Abstract class and Synthesizable RegFile)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.ArrayBuffer\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * IO bundle for a register read port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = Input(UInt(addrWidth.W))\n val data = Output(UInt(dataWidth.W))\n}\n\n/**\n * IO bundle for the register write port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n}\n\n/**\n * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.\n */\nobject WritePort\n{\n def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)\n (implicit p: Parameters): Valid[RegisterFileWritePort] = {\n val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))\n\n wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype\n wport.bits.addr := enq.bits.uop.pdst\n wport.bits.data := enq.bits.data\n enq.ready := true.B\n wport\n }\n}\n\n/**\n * Register file abstract class\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nabstract class RegisterFile(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new BoomBundle {\n val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))\n val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))\n })\n\n private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)\n private val type_str = if (registerWidth == fLen+1) \"Floating Point\" else \"Integer\"\n override def toString: String = BoomCoreStringPrefix(\n \"==\" + type_str + \" Regfile==\",\n \"Num RF Read Ports : \" + numReadPorts,\n \"Num RF Write Ports : \" + numWritePorts,\n \"RF Cost (R+W)*(R+2W) : \" + rf_cost,\n \"Bypassable Units : \" + bypassableArray)\n}\n\n/**\n * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nclass RegisterFileSynthesizable(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean])\n (implicit p: Parameters)\n extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)\n{\n // --------------------------------------------------------------\n\n val regfile = Mem(numRegisters, UInt(registerWidth.W))\n\n // --------------------------------------------------------------\n // Read ports.\n\n val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))\n\n // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).\n val read_addrs = io.read_ports.map(p => RegNext(p.addr))\n\n for (i <- 0 until numReadPorts) {\n read_data(i) := regfile(read_addrs(i))\n }\n\n // --------------------------------------------------------------\n // Bypass out of the ALU's write ports.\n // We are assuming we cannot bypass a writer to a reader within the regfile memory\n // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.\n // But since these bypasses are expensive, and not all write ports need to bypass their data,\n // only perform the w->r bypass on a select number of write ports.\n\n require (bypassableArray.length == io.write_ports.length)\n\n if (bypassableArray.reduce(_||_)) {\n val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()\n io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }\n\n for (i <- 0 until numReadPorts) {\n val bypass_ens = bypassable_wports.map(x => x.valid &&\n x.bits.addr === read_addrs(i))\n\n val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))\n\n io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))\n }\n } else {\n for (i <- 0 until numReadPorts) {\n io.read_ports(i).data := read_data(i)\n }\n }\n\n // --------------------------------------------------------------\n // Write ports.\n\n for (wport <- io.write_ports) {\n when (wport.valid) {\n regfile(wport.bits.addr) := wport.bits.data\n }\n }\n\n // ensure there is only 1 writer per register (unless to preg0)\n if (numWritePorts > 1) {\n for (i <- 0 until (numWritePorts - 1)) {\n for (j <- (i + 1) until numWritePorts) {\n assert(!io.write_ports(i).valid ||\n !io.write_ports(j).valid ||\n (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||\n (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here\n \"[regfile] too many writers a register\")\n }\n }\n }\n}", + "response": "module RegisterFileSynthesizable_1(\n input clock,\n input reset,\n input [5:0] io_read_ports_0_addr,\n output [63:0] io_read_ports_0_data,\n input [5:0] io_read_ports_1_addr,\n output [63:0] io_read_ports_1_data,\n input [5:0] io_read_ports_2_addr,\n output [63:0] io_read_ports_2_data,\n input [5:0] io_read_ports_3_addr,\n output [63:0] io_read_ports_3_data,\n input io_write_ports_0_valid,\n input [5:0] io_write_ports_0_bits_addr,\n input [63:0] io_write_ports_0_bits_data,\n input io_write_ports_1_valid,\n input [5:0] io_write_ports_1_bits_addr,\n input [63:0] io_write_ports_1_bits_data\n);\n\n wire [63:0] _regfile_ext_R0_data;\n wire [63:0] _regfile_ext_R1_data;\n wire [63:0] _regfile_ext_R2_data;\n wire [63:0] _regfile_ext_R3_data;\n reg [5:0] read_addrs_0;\n reg [5:0] read_addrs_1;\n reg [5:0] read_addrs_2;\n reg [5:0] read_addrs_3;\n wire bypass_ens_0 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_0;\n wire bypass_ens_1 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_0;\n wire bypass_ens_0_1 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_1;\n wire bypass_ens_1_1 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_1;\n wire bypass_ens_0_2 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_2;\n wire bypass_ens_1_2 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_2;\n wire bypass_ens_0_3 = io_write_ports_0_valid & io_write_ports_0_bits_addr == read_addrs_3;\n wire bypass_ens_1_3 = io_write_ports_1_valid & io_write_ports_1_bits_addr == read_addrs_3;\n always @(posedge clock) begin\n read_addrs_0 <= io_read_ports_0_addr;\n read_addrs_1 <= io_read_ports_1_addr;\n read_addrs_2 <= io_read_ports_2_addr;\n read_addrs_3 <= io_read_ports_3_addr;\n end\n regfile_52x64 regfile_ext (\n .R0_addr (read_addrs_3),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_regfile_ext_R0_data),\n .R1_addr (read_addrs_2),\n .R1_en (1'h1),\n .R1_clk (clock),\n .R1_data (_regfile_ext_R1_data),\n .R2_addr (read_addrs_1),\n .R2_en (1'h1),\n .R2_clk (clock),\n .R2_data (_regfile_ext_R2_data),\n .R3_addr (read_addrs_0),\n .R3_en (1'h1),\n .R3_clk (clock),\n .R3_data (_regfile_ext_R3_data),\n .W0_addr (io_write_ports_1_bits_addr),\n .W0_en (io_write_ports_1_valid),\n .W0_clk (clock),\n .W0_data (io_write_ports_1_bits_data),\n .W1_addr (io_write_ports_0_bits_addr),\n .W1_en (io_write_ports_0_valid),\n .W1_clk (clock),\n .W1_data (io_write_ports_0_bits_data)\n );\n assign io_read_ports_0_data = bypass_ens_0 | bypass_ens_1 ? (bypass_ens_0 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R3_data;\n assign io_read_ports_1_data = bypass_ens_0_1 | bypass_ens_1_1 ? (bypass_ens_0_1 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_1 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R2_data;\n assign io_read_ports_2_data = bypass_ens_0_2 | bypass_ens_1_2 ? (bypass_ens_0_2 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_2 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R1_data;\n assign io_read_ports_3_data = bypass_ens_0_3 | bypass_ens_1_3 ? (bypass_ens_0_3 ? io_write_ports_0_bits_data : 64'h0) | (bypass_ens_1_3 ? io_write_ports_1_bits_data : 64'h0) : _regfile_ext_R0_data;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us_4(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename BusyTable\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass BusyResp extends Bundle\n{\n val prs1_busy = Bool()\n val prs2_busy = Bool()\n val prs3_busy = Bool()\n}\n\nclass RenameBusyTable(\n val plWidth: Int,\n val numPregs: Int,\n val numWbPorts: Int,\n val bypass: Boolean,\n val float: Boolean)\n (implicit p: Parameters) extends BoomModule\n{\n val pregSz = log2Ceil(numPregs)\n\n val io = IO(new BoomBundle()(p) {\n val ren_uops = Input(Vec(plWidth, new MicroOp))\n val busy_resps = Output(Vec(plWidth, new BusyResp))\n val rebusy_reqs = Input(Vec(plWidth, Bool()))\n\n val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W)))\n val wb_valids = Input(Vec(numWbPorts, Bool()))\n\n val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) }\n })\n\n val busy_table = RegInit(0.U(numPregs.W))\n // Unbusy written back registers.\n val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids)\n .map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_|_)\n // Rebusy newly allocated registers.\n val busy_table_next = busy_table_wb | (io.ren_uops zip io.rebusy_reqs)\n .map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_|_)\n\n busy_table := busy_table_next\n\n // Read the busy table.\n for (i <- 0 until plWidth) {\n val prs1_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n val prs2_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n val prs3_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n\n io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) || prs1_was_bypassed && bypass.B\n io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) || prs2_was_bypassed && bypass.B\n io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) || prs3_was_bypassed && bypass.B\n if (!float) io.busy_resps(i).prs3_busy := false.B\n }\n\n io.debug.busytable := busy_table\n}", + "response": "module RenameBusyTable_1(\n input clock,\n input reset,\n input [5:0] io_ren_uops_0_pdst,\n input [5:0] io_ren_uops_0_prs1,\n input [5:0] io_ren_uops_0_prs2,\n input [5:0] io_ren_uops_0_prs3,\n output io_busy_resps_0_prs1_busy,\n output io_busy_resps_0_prs2_busy,\n output io_busy_resps_0_prs3_busy,\n input io_rebusy_reqs_0,\n input [5:0] io_wb_pdsts_0,\n input [5:0] io_wb_pdsts_1,\n input io_wb_valids_0,\n input io_wb_valids_1\n);\n\n reg [47:0] busy_table;\n wire [47:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1;\n wire [47:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2;\n wire [47:0] _io_busy_resps_0_prs3_busy_T = busy_table >> io_ren_uops_0_prs3;\n wire [63:0] _busy_table_next_T = 64'h1 << io_ren_uops_0_pdst;\n wire [63:0] _busy_table_wb_T_3 = 64'h1 << io_wb_pdsts_1;\n wire [63:0] _busy_table_wb_T = 64'h1 << io_wb_pdsts_0;\n always @(posedge clock) begin\n if (reset)\n busy_table <= 48'h0;\n else\n busy_table <= ~(_busy_table_wb_T[47:0] & {48{io_wb_valids_0}} | _busy_table_wb_T_3[47:0] & {48{io_wb_valids_1}}) & busy_table | _busy_table_next_T[47:0] & {48{io_rebusy_reqs_0}};\n end\n assign io_busy_resps_0_prs1_busy = _io_busy_resps_0_prs1_busy_T[0];\n assign io_busy_resps_0_prs2_busy = _io_busy_resps_0_prs2_busy_T[0];\n assign io_busy_resps_0_prs3_busy = _io_busy_resps_0_prs3_busy_T[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\n\n// The control port response source\nclass SourceXRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val fail = Bool()\n}\n\nclass SourceX(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new SourceXRequest(params)))\n val x = Decoupled(new SourceXRequest(params))\n })\n\n val x = Wire(chiselTypeOf(io.x)) // ready must not depend on valid\n io.x <> Queue(x, 1)\n\n io.req.ready := x.ready\n x.valid := io.req.valid\n params.ccover(x.valid && !x.ready, \"SOURCEX_STALL\", \"Backpressure when sending a control message\")\n\n x.bits := io.req.bits\n}", + "response": "module SourceX(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n output io_x_valid\n);\n\n Queue1_SourceXRequest io_x_q (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (io_req_ready),\n .io_enq_valid (io_req_valid),\n .io_deq_valid (io_x_valid)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable_2(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [11:0] table_MPORT_data_3;\n wire [11:0] table_MPORT_data_2;\n wire [11:0] table_MPORT_data_1;\n wire [11:0] table_MPORT_data_0;\n wire [47:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [7:0] reset_idx;\n wire [7:0] s1_hashed_idx = io_f1_req_pc[10:3] ^ io_f1_req_ghist[7:0];\n reg [7:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [19:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[19];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[19]);\n wire [7:0] update_idx = io_update_pc[10:3] ^ io_update_hist[7:0];\n wire [7:0] update_tag = io_update_pc[18:11] ^ io_update_hist[7:0];\n assign table_MPORT_data_0 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 12'h0 : {1'h1, update_tag, update_wdata_3_ctr};\n wire _GEN = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN & update_hi_wdata_3;\n wire [3:0] _GEN_0 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_1 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_1 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_1 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_1 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_1 & update_lo_wdata_3;\n reg [7:0] wrbypass_tags_0;\n reg [7:0] wrbypass_tags_1;\n reg [7:0] wrbypass_idxs_0;\n reg [7:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_2 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_3 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_4 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_2) ? 3'h7 : _GEN_2 + 3'h1) : _GEN_2 == 3'h0 ? 3'h0 : _GEN_2 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_3) ? 3'h7 : _GEN_3 + 3'h1) : _GEN_3 == 3'h0 ? 3'h0 : _GEN_3 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_4) ? 3'h7 : _GEN_4 + 3'h1) : _GEN_4 == 3'h0 ? 3'h0 : _GEN_4 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire _GEN_6 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_7 = ~_GEN_6 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_8 = ~_GEN_6 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 8'h0;\n clear_u_ctr <= 20'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 8'hFF & doing_reset;\n reset_idx <= reset_idx + {7'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 20'h1 : clear_u_ctr + 20'h1;\n if (~_GEN_6 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= io_f1_req_pc[18:11] ^ io_f1_req_ghist[7:0];\n io_f3_resp_0_valid_REG <= _table_R0_data[11] & _table_R0_data[10:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[23] & _table_R0_data[22:15] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[14:12];\n io_f3_resp_2_valid_REG <= _table_R0_data[35] & _table_R0_data[34:27] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[26:24];\n io_f3_resp_3_valid_REG <= _table_R0_data[47] & _table_R0_data[46:39] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[38:36];\n if (_GEN_7) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_8) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_7) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_8) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_6) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us_1 hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[18:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN ? 4'hF : _GEN_0)\n );\n lo_us_1 lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[18:11] : update_idx),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_1 ? 4'hF : _GEN_0)\n );\n table_1 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11(\n input io_invalidExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [12:0] io_in_sExp,\n input [53:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire roundingMode_odd = io_roundingMode == 3'h6;\n wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;\n wire [13:0] sAdjustedExp = {io_in_sExp[12], io_in_sExp} - 14'h7E0;\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> ~(sAdjustedExp[5:0]));\n wire [12:0] _GEN = {1'h1, ~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~(roundMask_shift[18])};\n wire [12:0] _GEN_0 = {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], roundMask_shift[18], 1'h1};\n wire [12:0] _roundPosBit_T = io_in_sig[53:41] & _GEN & _GEN_0;\n wire [12:0] _anyRoundExtra_T = {io_in_sig[52:41], |(io_in_sig[40:0])} & _GEN_0;\n wire [25:0] _GEN_1 = {_roundPosBit_T, _anyRoundExtra_T};\n wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;\n wire [12:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_1) ? {1'h0, io_in_sig[53] | roundMask_shift[7], io_in_sig[52] | roundMask_shift[8], io_in_sig[51] | roundMask_shift[9], io_in_sig[50] | roundMask_shift[10], io_in_sig[49] | roundMask_shift[11], io_in_sig[48] | roundMask_shift[12], io_in_sig[47] | roundMask_shift[13], io_in_sig[46] | roundMask_shift[14], io_in_sig[45] | roundMask_shift[15], io_in_sig[44] | roundMask_shift[16], io_in_sig[43] | roundMask_shift[17], io_in_sig[42] | roundMask_shift[18]} + 13'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 13'h0 ? {roundMask_shift[7], roundMask_shift[8], roundMask_shift[9], roundMask_shift[10], roundMask_shift[11], roundMask_shift[12], roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], roundMask_shift[18], 1'h1} : 13'h0) : {1'h0, io_in_sig[53:42] & {~(roundMask_shift[7]), ~(roundMask_shift[8]), ~(roundMask_shift[9]), ~(roundMask_shift[10]), ~(roundMask_shift[11]), ~(roundMask_shift[12]), ~(roundMask_shift[13]), ~(roundMask_shift[14]), ~(roundMask_shift[15]), ~(roundMask_shift[16]), ~(roundMask_shift[17]), ~(roundMask_shift[18])}} | (roundingMode_odd & (|_GEN_1) ? _GEN & _GEN_0 : 13'h0);\n wire [14:0] sRoundedExp = {sAdjustedExp[13], sAdjustedExp} + {13'h0, roundedSig[12:11]};\n wire common_totalUnderflow = $signed(sRoundedExp) < 15'sh8;\n wire isNaNOut = io_invalidExc | io_in_isNaN;\n wire commonCase = ~isNaNOut & ~io_in_isInf & ~io_in_isZero;\n wire overflow = commonCase & $signed(sRoundedExp[14:4]) > 11'sh2;\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\n wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);\n wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;\n wire notNaN_isInfOut = io_in_isInf | overflow & overflow_roundMagUp;\n assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[5:0] & ~(io_in_isZero | common_totalUnderflow ? 6'h38 : 6'h0) & ~(pegMinNonzeroMagOut ? 6'h37 : 6'h0) & {1'h1, ~pegMaxFiniteMagOut, 4'hF} & {2'h3, ~notNaN_isInfOut, 3'h7} | {2'h0, pegMinNonzeroMagOut, 3'h0} | (pegMaxFiniteMagOut ? 6'h2F : 6'h0) | (notNaN_isInfOut ? 6'h30 : 6'h0) | (isNaNOut ? 6'h38 : 6'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 9'h0} : roundedSig[9:0]) | {10{pegMaxFiniteMagOut}}};\n assign io_exceptionFlags = {io_invalidExc, 1'h0, overflow, commonCase & (common_totalUnderflow | (|_GEN_1) & $signed(sAdjustedExp[13:5]) < 9'sh1 & roundMask_shift[18] & ~(~(roundMask_shift[17]) & roundedSig[11] & (|_roundPosBit_T) & (_overflow_roundMagUp_T & io_in_sig[41] | roundMagUp & (|{io_in_sig[41], |(io_in_sig[40:0])})))), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_dir(\n input [9:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [135:0] RW0_wdata,\n output [135:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n cc_dir_ext cc_dir_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_4(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}", + "response": "module OptimizationBarrier_PTE(\n input [43:0] io_x_ppn,\n input io_x_d,\n input io_x_a,\n input io_x_g,\n input io_x_u,\n input io_x_x,\n input io_x_w,\n input io_x_r,\n input io_x_v,\n output [43:0] io_y_ppn,\n output io_y_d,\n output io_y_a,\n output io_y_g,\n output io_y_u,\n output io_y_x,\n output io_y_w,\n output io_y_r,\n output io_y_v\n);\n\n assign io_y_ppn = io_x_ppn;\n assign io_y_d = io_x_d;\n assign io_y_a = io_x_a;\n assign io_y_g = io_x_g;\n assign io_y_u = io_x_u;\n assign io_y_x = io_x_x;\n assign io_y_w = io_x_w;\n assign io_y_r = io_x_r;\n assign io_y_v = io_x_v;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module ram_16x46(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [45:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [45:0] W0_data\n);\n\n reg [45:0] Memory[0:15];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 46'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPUFMAPipe_l4_f32(\n input clock,\n input reset,\n input io_in_valid,\n input io_in_bits_ren3,\n input io_in_bits_swap23,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_fmaCmd,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n input [64:0] io_in_bits_in3,\n output io_out_valid,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc\n);\n\n wire [32:0] _fma_io_out;\n wire [4:0] _fma_io_exceptionFlags;\n wire _fma_io_validout;\n reg valid;\n reg [2:0] in_rm;\n reg [1:0] in_fmaCmd;\n reg [64:0] in_in1;\n reg [64:0] in_in2;\n reg [64:0] in_in3;\n reg io_out_pipe_v;\n reg [64:0] io_out_pipe_b_data;\n reg [4:0] io_out_pipe_b_exc;\n always @(posedge clock) begin\n valid <= io_in_valid;\n if (io_in_valid) begin\n in_rm <= io_in_bits_rm;\n in_fmaCmd <= io_in_bits_fmaCmd;\n in_in1 <= io_in_bits_in1;\n in_in2 <= io_in_bits_swap23 ? 65'h80000000 : io_in_bits_in2;\n in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : {32'h0, (io_in_bits_in1[32:0] ^ io_in_bits_in2[32:0]) & 33'h100000000};\n end\n if (_fma_io_validout) begin\n io_out_pipe_b_data <= {32'h0, _fma_io_out};\n io_out_pipe_b_exc <= _fma_io_exceptionFlags;\n end\n if (reset)\n io_out_pipe_v <= 1'h0;\n else\n io_out_pipe_v <= _fma_io_validout;\n end\n MulAddRecFNPipe_l2_e8_s24 fma (\n .clock (clock),\n .reset (reset),\n .io_validin (valid),\n .io_op (in_fmaCmd),\n .io_a (in_in1[32:0]),\n .io_b (in_in2[32:0]),\n .io_c (in_in3[32:0]),\n .io_roundingMode (in_rm),\n .io_out (_fma_io_out),\n .io_exceptionFlags (_fma_io_exceptionFlags),\n .io_validout (_fma_io_validout)\n );\n assign io_out_valid = io_out_pipe_v;\n assign io_out_bits_data = io_out_pipe_b_data;\n assign io_out_bits_exc = io_out_pipe_b_exc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename Map Table\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass MapReq(val lregSz: Int) extends Bundle\n{\n val lrs1 = UInt(lregSz.W)\n val lrs2 = UInt(lregSz.W)\n val lrs3 = UInt(lregSz.W)\n val ldst = UInt(lregSz.W)\n}\n\nclass MapResp(val pregSz: Int) extends Bundle\n{\n val prs1 = UInt(pregSz.W)\n val prs2 = UInt(pregSz.W)\n val prs3 = UInt(pregSz.W)\n val stale_pdst = UInt(pregSz.W)\n}\n\nclass RemapReq(val lregSz: Int, val pregSz: Int) extends Bundle\n{\n val ldst = UInt(lregSz.W)\n val pdst = UInt(pregSz.W)\n val valid = Bool()\n}\n\nclass RenameMapTable(\n val plWidth: Int,\n val numLregs: Int,\n val numPregs: Int,\n val bypass: Boolean,\n val float: Boolean)\n (implicit p: Parameters) extends BoomModule\n{\n val pregSz = log2Ceil(numPregs)\n\n val io = IO(new BoomBundle()(p) {\n // Logical sources -> physical sources.\n val map_reqs = Input(Vec(plWidth, new MapReq(lregSz)))\n val map_resps = Output(Vec(plWidth, new MapResp(pregSz)))\n\n // Remapping an ldst to a newly allocated pdst?\n val remap_reqs = Input(Vec(plWidth, new RemapReq(lregSz, pregSz)))\n\n // Dispatching branches: need to take snapshots of table state.\n val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Signals for restoring state following misspeculation.\n val brupdate = Input(new BrUpdateInfo)\n val rollback = Input(Bool())\n })\n\n // The map table register array and its branch snapshots.\n val map_table = RegInit(VecInit(Seq.fill(numLregs){0.U(pregSz.W)}))\n val br_snapshots = Reg(Vec(maxBrCount, Vec(numLregs, UInt(pregSz.W))))\n\n // The intermediate states of the map table following modification by each pipeline slot.\n val remap_table = Wire(Vec(plWidth+1, Vec(numLregs, UInt(pregSz.W))))\n\n // Uops requesting changes to the map table.\n val remap_pdsts = io.remap_reqs map (_.pdst)\n val remap_ldsts_oh = io.remap_reqs map (req => UIntToOH(req.ldst) & Fill(numLregs, req.valid.asUInt))\n\n // Figure out the new mappings seen by each pipeline slot.\n for (i <- 0 until numLregs) {\n if (i == 0 && !float) {\n for (j <- 0 until plWidth+1) {\n remap_table(j)(i) := 0.U\n }\n } else {\n val remapped_row = (remap_ldsts_oh.map(ldst => ldst(i)) zip remap_pdsts)\n .scanLeft(map_table(i)) {case (pdst, (ldst, new_pdst)) => Mux(ldst, new_pdst, pdst)}\n\n for (j <- 0 until plWidth+1) {\n remap_table(j)(i) := remapped_row(j)\n }\n }\n }\n\n // Create snapshots of new mappings.\n for (i <- 0 until plWidth) {\n when (io.ren_br_tags(i).valid) {\n br_snapshots(io.ren_br_tags(i).bits) := remap_table(i+1)\n }\n }\n\n when (io.brupdate.b2.mispredict) {\n // Restore the map table to a branch snapshot.\n map_table := br_snapshots(io.brupdate.b2.uop.br_tag)\n } .otherwise {\n // Update mappings.\n map_table := remap_table(plWidth)\n }\n\n // Read out mappings.\n for (i <- 0 until plWidth) {\n io.map_resps(i).prs1 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs1)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs1, io.remap_reqs(k).pdst, p))\n io.map_resps(i).prs2 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs2)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs2, io.remap_reqs(k).pdst, p))\n io.map_resps(i).prs3 := (0 until i).foldLeft(map_table(io.map_reqs(i).lrs3)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).lrs3, io.remap_reqs(k).pdst, p))\n io.map_resps(i).stale_pdst := (0 until i).foldLeft(map_table(io.map_reqs(i).ldst)) ((p,k) =>\n Mux(bypass.B && io.remap_reqs(k).valid && io.remap_reqs(k).ldst === io.map_reqs(i).ldst, io.remap_reqs(k).pdst, p))\n\n if (!float) io.map_resps(i).prs3 := DontCare\n }\n\n // Don't flag the creation of duplicate 'p0' mappings during rollback.\n // These cases may occur soon after reset, as all maptable entries are initialized to 'p0'.\n io.remap_reqs map (req => (req.pdst, req.valid)) foreach {case (p,r) =>\n assert (!r || !map_table.contains(p) || p === 0.U && io.rollback, \"[maptable] Trying to write a duplicate mapping.\")}\n}", + "response": "module RenameMapTable_1(\n input clock,\n input reset,\n input [5:0] io_map_reqs_0_lrs1,\n input [5:0] io_map_reqs_0_lrs2,\n input [5:0] io_map_reqs_0_lrs3,\n input [5:0] io_map_reqs_0_ldst,\n output [5:0] io_map_resps_0_prs1,\n output [5:0] io_map_resps_0_prs2,\n output [5:0] io_map_resps_0_prs3,\n output [5:0] io_map_resps_0_stale_pdst,\n input [5:0] io_remap_reqs_0_ldst,\n input [5:0] io_remap_reqs_0_pdst,\n input io_remap_reqs_0_valid,\n input io_ren_br_tags_0_valid,\n input [2:0] io_ren_br_tags_0_bits,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_rollback\n);\n\n reg [5:0] map_table_0;\n reg [5:0] map_table_1;\n reg [5:0] map_table_2;\n reg [5:0] map_table_3;\n reg [5:0] map_table_4;\n reg [5:0] map_table_5;\n reg [5:0] map_table_6;\n reg [5:0] map_table_7;\n reg [5:0] map_table_8;\n reg [5:0] map_table_9;\n reg [5:0] map_table_10;\n reg [5:0] map_table_11;\n reg [5:0] map_table_12;\n reg [5:0] map_table_13;\n reg [5:0] map_table_14;\n reg [5:0] map_table_15;\n reg [5:0] map_table_16;\n reg [5:0] map_table_17;\n reg [5:0] map_table_18;\n reg [5:0] map_table_19;\n reg [5:0] map_table_20;\n reg [5:0] map_table_21;\n reg [5:0] map_table_22;\n reg [5:0] map_table_23;\n reg [5:0] map_table_24;\n reg [5:0] map_table_25;\n reg [5:0] map_table_26;\n reg [5:0] map_table_27;\n reg [5:0] map_table_28;\n reg [5:0] map_table_29;\n reg [5:0] map_table_30;\n reg [5:0] map_table_31;\n reg [5:0] br_snapshots_0_0;\n reg [5:0] br_snapshots_0_1;\n reg [5:0] br_snapshots_0_2;\n reg [5:0] br_snapshots_0_3;\n reg [5:0] br_snapshots_0_4;\n reg [5:0] br_snapshots_0_5;\n reg [5:0] br_snapshots_0_6;\n reg [5:0] br_snapshots_0_7;\n reg [5:0] br_snapshots_0_8;\n reg [5:0] br_snapshots_0_9;\n reg [5:0] br_snapshots_0_10;\n reg [5:0] br_snapshots_0_11;\n reg [5:0] br_snapshots_0_12;\n reg [5:0] br_snapshots_0_13;\n reg [5:0] br_snapshots_0_14;\n reg [5:0] br_snapshots_0_15;\n reg [5:0] br_snapshots_0_16;\n reg [5:0] br_snapshots_0_17;\n reg [5:0] br_snapshots_0_18;\n reg [5:0] br_snapshots_0_19;\n reg [5:0] br_snapshots_0_20;\n reg [5:0] br_snapshots_0_21;\n reg [5:0] br_snapshots_0_22;\n reg [5:0] br_snapshots_0_23;\n reg [5:0] br_snapshots_0_24;\n reg [5:0] br_snapshots_0_25;\n reg [5:0] br_snapshots_0_26;\n reg [5:0] br_snapshots_0_27;\n reg [5:0] br_snapshots_0_28;\n reg [5:0] br_snapshots_0_29;\n reg [5:0] br_snapshots_0_30;\n reg [5:0] br_snapshots_0_31;\n reg [5:0] br_snapshots_1_0;\n reg [5:0] br_snapshots_1_1;\n reg [5:0] br_snapshots_1_2;\n reg [5:0] br_snapshots_1_3;\n reg [5:0] br_snapshots_1_4;\n reg [5:0] br_snapshots_1_5;\n reg [5:0] br_snapshots_1_6;\n reg [5:0] br_snapshots_1_7;\n reg [5:0] br_snapshots_1_8;\n reg [5:0] br_snapshots_1_9;\n reg [5:0] br_snapshots_1_10;\n reg [5:0] br_snapshots_1_11;\n reg [5:0] br_snapshots_1_12;\n reg [5:0] br_snapshots_1_13;\n reg [5:0] br_snapshots_1_14;\n reg [5:0] br_snapshots_1_15;\n reg [5:0] br_snapshots_1_16;\n reg [5:0] br_snapshots_1_17;\n reg [5:0] br_snapshots_1_18;\n reg [5:0] br_snapshots_1_19;\n reg [5:0] br_snapshots_1_20;\n reg [5:0] br_snapshots_1_21;\n reg [5:0] br_snapshots_1_22;\n reg [5:0] br_snapshots_1_23;\n reg [5:0] br_snapshots_1_24;\n reg [5:0] br_snapshots_1_25;\n reg [5:0] br_snapshots_1_26;\n reg [5:0] br_snapshots_1_27;\n reg [5:0] br_snapshots_1_28;\n reg [5:0] br_snapshots_1_29;\n reg [5:0] br_snapshots_1_30;\n reg [5:0] br_snapshots_1_31;\n reg [5:0] br_snapshots_2_0;\n reg [5:0] br_snapshots_2_1;\n reg [5:0] br_snapshots_2_2;\n reg [5:0] br_snapshots_2_3;\n reg [5:0] br_snapshots_2_4;\n reg [5:0] br_snapshots_2_5;\n reg [5:0] br_snapshots_2_6;\n reg [5:0] br_snapshots_2_7;\n reg [5:0] br_snapshots_2_8;\n reg [5:0] br_snapshots_2_9;\n reg [5:0] br_snapshots_2_10;\n reg [5:0] br_snapshots_2_11;\n reg [5:0] br_snapshots_2_12;\n reg [5:0] br_snapshots_2_13;\n reg [5:0] br_snapshots_2_14;\n reg [5:0] br_snapshots_2_15;\n reg [5:0] br_snapshots_2_16;\n reg [5:0] br_snapshots_2_17;\n reg [5:0] br_snapshots_2_18;\n reg [5:0] br_snapshots_2_19;\n reg [5:0] br_snapshots_2_20;\n reg [5:0] br_snapshots_2_21;\n reg [5:0] br_snapshots_2_22;\n reg [5:0] br_snapshots_2_23;\n reg [5:0] br_snapshots_2_24;\n reg [5:0] br_snapshots_2_25;\n reg [5:0] br_snapshots_2_26;\n reg [5:0] br_snapshots_2_27;\n reg [5:0] br_snapshots_2_28;\n reg [5:0] br_snapshots_2_29;\n reg [5:0] br_snapshots_2_30;\n reg [5:0] br_snapshots_2_31;\n reg [5:0] br_snapshots_3_0;\n reg [5:0] br_snapshots_3_1;\n reg [5:0] br_snapshots_3_2;\n reg [5:0] br_snapshots_3_3;\n reg [5:0] br_snapshots_3_4;\n reg [5:0] br_snapshots_3_5;\n reg [5:0] br_snapshots_3_6;\n reg [5:0] br_snapshots_3_7;\n reg [5:0] br_snapshots_3_8;\n reg [5:0] br_snapshots_3_9;\n reg [5:0] br_snapshots_3_10;\n reg [5:0] br_snapshots_3_11;\n reg [5:0] br_snapshots_3_12;\n reg [5:0] br_snapshots_3_13;\n reg [5:0] br_snapshots_3_14;\n reg [5:0] br_snapshots_3_15;\n reg [5:0] br_snapshots_3_16;\n reg [5:0] br_snapshots_3_17;\n reg [5:0] br_snapshots_3_18;\n reg [5:0] br_snapshots_3_19;\n reg [5:0] br_snapshots_3_20;\n reg [5:0] br_snapshots_3_21;\n reg [5:0] br_snapshots_3_22;\n reg [5:0] br_snapshots_3_23;\n reg [5:0] br_snapshots_3_24;\n reg [5:0] br_snapshots_3_25;\n reg [5:0] br_snapshots_3_26;\n reg [5:0] br_snapshots_3_27;\n reg [5:0] br_snapshots_3_28;\n reg [5:0] br_snapshots_3_29;\n reg [5:0] br_snapshots_3_30;\n reg [5:0] br_snapshots_3_31;\n reg [5:0] br_snapshots_4_0;\n reg [5:0] br_snapshots_4_1;\n reg [5:0] br_snapshots_4_2;\n reg [5:0] br_snapshots_4_3;\n reg [5:0] br_snapshots_4_4;\n reg [5:0] br_snapshots_4_5;\n reg [5:0] br_snapshots_4_6;\n reg [5:0] br_snapshots_4_7;\n reg [5:0] br_snapshots_4_8;\n reg [5:0] br_snapshots_4_9;\n reg [5:0] br_snapshots_4_10;\n reg [5:0] br_snapshots_4_11;\n reg [5:0] br_snapshots_4_12;\n reg [5:0] br_snapshots_4_13;\n reg [5:0] br_snapshots_4_14;\n reg [5:0] br_snapshots_4_15;\n reg [5:0] br_snapshots_4_16;\n reg [5:0] br_snapshots_4_17;\n reg [5:0] br_snapshots_4_18;\n reg [5:0] br_snapshots_4_19;\n reg [5:0] br_snapshots_4_20;\n reg [5:0] br_snapshots_4_21;\n reg [5:0] br_snapshots_4_22;\n reg [5:0] br_snapshots_4_23;\n reg [5:0] br_snapshots_4_24;\n reg [5:0] br_snapshots_4_25;\n reg [5:0] br_snapshots_4_26;\n reg [5:0] br_snapshots_4_27;\n reg [5:0] br_snapshots_4_28;\n reg [5:0] br_snapshots_4_29;\n reg [5:0] br_snapshots_4_30;\n reg [5:0] br_snapshots_4_31;\n reg [5:0] br_snapshots_5_0;\n reg [5:0] br_snapshots_5_1;\n reg [5:0] br_snapshots_5_2;\n reg [5:0] br_snapshots_5_3;\n reg [5:0] br_snapshots_5_4;\n reg [5:0] br_snapshots_5_5;\n reg [5:0] br_snapshots_5_6;\n reg [5:0] br_snapshots_5_7;\n reg [5:0] br_snapshots_5_8;\n reg [5:0] br_snapshots_5_9;\n reg [5:0] br_snapshots_5_10;\n reg [5:0] br_snapshots_5_11;\n reg [5:0] br_snapshots_5_12;\n reg [5:0] br_snapshots_5_13;\n reg [5:0] br_snapshots_5_14;\n reg [5:0] br_snapshots_5_15;\n reg [5:0] br_snapshots_5_16;\n reg [5:0] br_snapshots_5_17;\n reg [5:0] br_snapshots_5_18;\n reg [5:0] br_snapshots_5_19;\n reg [5:0] br_snapshots_5_20;\n reg [5:0] br_snapshots_5_21;\n reg [5:0] br_snapshots_5_22;\n reg [5:0] br_snapshots_5_23;\n reg [5:0] br_snapshots_5_24;\n reg [5:0] br_snapshots_5_25;\n reg [5:0] br_snapshots_5_26;\n reg [5:0] br_snapshots_5_27;\n reg [5:0] br_snapshots_5_28;\n reg [5:0] br_snapshots_5_29;\n reg [5:0] br_snapshots_5_30;\n reg [5:0] br_snapshots_5_31;\n reg [5:0] br_snapshots_6_0;\n reg [5:0] br_snapshots_6_1;\n reg [5:0] br_snapshots_6_2;\n reg [5:0] br_snapshots_6_3;\n reg [5:0] br_snapshots_6_4;\n reg [5:0] br_snapshots_6_5;\n reg [5:0] br_snapshots_6_6;\n reg [5:0] br_snapshots_6_7;\n reg [5:0] br_snapshots_6_8;\n reg [5:0] br_snapshots_6_9;\n reg [5:0] br_snapshots_6_10;\n reg [5:0] br_snapshots_6_11;\n reg [5:0] br_snapshots_6_12;\n reg [5:0] br_snapshots_6_13;\n reg [5:0] br_snapshots_6_14;\n reg [5:0] br_snapshots_6_15;\n reg [5:0] br_snapshots_6_16;\n reg [5:0] br_snapshots_6_17;\n reg [5:0] br_snapshots_6_18;\n reg [5:0] br_snapshots_6_19;\n reg [5:0] br_snapshots_6_20;\n reg [5:0] br_snapshots_6_21;\n reg [5:0] br_snapshots_6_22;\n reg [5:0] br_snapshots_6_23;\n reg [5:0] br_snapshots_6_24;\n reg [5:0] br_snapshots_6_25;\n reg [5:0] br_snapshots_6_26;\n reg [5:0] br_snapshots_6_27;\n reg [5:0] br_snapshots_6_28;\n reg [5:0] br_snapshots_6_29;\n reg [5:0] br_snapshots_6_30;\n reg [5:0] br_snapshots_6_31;\n reg [5:0] br_snapshots_7_0;\n reg [5:0] br_snapshots_7_1;\n reg [5:0] br_snapshots_7_2;\n reg [5:0] br_snapshots_7_3;\n reg [5:0] br_snapshots_7_4;\n reg [5:0] br_snapshots_7_5;\n reg [5:0] br_snapshots_7_6;\n reg [5:0] br_snapshots_7_7;\n reg [5:0] br_snapshots_7_8;\n reg [5:0] br_snapshots_7_9;\n reg [5:0] br_snapshots_7_10;\n reg [5:0] br_snapshots_7_11;\n reg [5:0] br_snapshots_7_12;\n reg [5:0] br_snapshots_7_13;\n reg [5:0] br_snapshots_7_14;\n reg [5:0] br_snapshots_7_15;\n reg [5:0] br_snapshots_7_16;\n reg [5:0] br_snapshots_7_17;\n reg [5:0] br_snapshots_7_18;\n reg [5:0] br_snapshots_7_19;\n reg [5:0] br_snapshots_7_20;\n reg [5:0] br_snapshots_7_21;\n reg [5:0] br_snapshots_7_22;\n reg [5:0] br_snapshots_7_23;\n reg [5:0] br_snapshots_7_24;\n reg [5:0] br_snapshots_7_25;\n reg [5:0] br_snapshots_7_26;\n reg [5:0] br_snapshots_7_27;\n reg [5:0] br_snapshots_7_28;\n reg [5:0] br_snapshots_7_29;\n reg [5:0] br_snapshots_7_30;\n reg [5:0] br_snapshots_7_31;\n wire [31:0][5:0] _GEN = {{map_table_31}, {map_table_30}, {map_table_29}, {map_table_28}, {map_table_27}, {map_table_26}, {map_table_25}, {map_table_24}, {map_table_23}, {map_table_22}, {map_table_21}, {map_table_20}, {map_table_19}, {map_table_18}, {map_table_17}, {map_table_16}, {map_table_15}, {map_table_14}, {map_table_13}, {map_table_12}, {map_table_11}, {map_table_10}, {map_table_9}, {map_table_8}, {map_table_7}, {map_table_6}, {map_table_5}, {map_table_4}, {map_table_3}, {map_table_2}, {map_table_1}, {map_table_0}};\n wire [7:0][5:0] _GEN_0 = {{br_snapshots_7_0}, {br_snapshots_6_0}, {br_snapshots_5_0}, {br_snapshots_4_0}, {br_snapshots_3_0}, {br_snapshots_2_0}, {br_snapshots_1_0}, {br_snapshots_0_0}};\n wire [7:0][5:0] _GEN_1 = {{br_snapshots_7_1}, {br_snapshots_6_1}, {br_snapshots_5_1}, {br_snapshots_4_1}, {br_snapshots_3_1}, {br_snapshots_2_1}, {br_snapshots_1_1}, {br_snapshots_0_1}};\n wire [7:0][5:0] _GEN_2 = {{br_snapshots_7_2}, {br_snapshots_6_2}, {br_snapshots_5_2}, {br_snapshots_4_2}, {br_snapshots_3_2}, {br_snapshots_2_2}, {br_snapshots_1_2}, {br_snapshots_0_2}};\n wire [7:0][5:0] _GEN_3 = {{br_snapshots_7_3}, {br_snapshots_6_3}, {br_snapshots_5_3}, {br_snapshots_4_3}, {br_snapshots_3_3}, {br_snapshots_2_3}, {br_snapshots_1_3}, {br_snapshots_0_3}};\n wire [7:0][5:0] _GEN_4 = {{br_snapshots_7_4}, {br_snapshots_6_4}, {br_snapshots_5_4}, {br_snapshots_4_4}, {br_snapshots_3_4}, {br_snapshots_2_4}, {br_snapshots_1_4}, {br_snapshots_0_4}};\n wire [7:0][5:0] _GEN_5 = {{br_snapshots_7_5}, {br_snapshots_6_5}, {br_snapshots_5_5}, {br_snapshots_4_5}, {br_snapshots_3_5}, {br_snapshots_2_5}, {br_snapshots_1_5}, {br_snapshots_0_5}};\n wire [7:0][5:0] _GEN_6 = {{br_snapshots_7_6}, {br_snapshots_6_6}, {br_snapshots_5_6}, {br_snapshots_4_6}, {br_snapshots_3_6}, {br_snapshots_2_6}, {br_snapshots_1_6}, {br_snapshots_0_6}};\n wire [7:0][5:0] _GEN_7 = {{br_snapshots_7_7}, {br_snapshots_6_7}, {br_snapshots_5_7}, {br_snapshots_4_7}, {br_snapshots_3_7}, {br_snapshots_2_7}, {br_snapshots_1_7}, {br_snapshots_0_7}};\n wire [7:0][5:0] _GEN_8 = {{br_snapshots_7_8}, {br_snapshots_6_8}, {br_snapshots_5_8}, {br_snapshots_4_8}, {br_snapshots_3_8}, {br_snapshots_2_8}, {br_snapshots_1_8}, {br_snapshots_0_8}};\n wire [7:0][5:0] _GEN_9 = {{br_snapshots_7_9}, {br_snapshots_6_9}, {br_snapshots_5_9}, {br_snapshots_4_9}, {br_snapshots_3_9}, {br_snapshots_2_9}, {br_snapshots_1_9}, {br_snapshots_0_9}};\n wire [7:0][5:0] _GEN_10 = {{br_snapshots_7_10}, {br_snapshots_6_10}, {br_snapshots_5_10}, {br_snapshots_4_10}, {br_snapshots_3_10}, {br_snapshots_2_10}, {br_snapshots_1_10}, {br_snapshots_0_10}};\n wire [7:0][5:0] _GEN_11 = {{br_snapshots_7_11}, {br_snapshots_6_11}, {br_snapshots_5_11}, {br_snapshots_4_11}, {br_snapshots_3_11}, {br_snapshots_2_11}, {br_snapshots_1_11}, {br_snapshots_0_11}};\n wire [7:0][5:0] _GEN_12 = {{br_snapshots_7_12}, {br_snapshots_6_12}, {br_snapshots_5_12}, {br_snapshots_4_12}, {br_snapshots_3_12}, {br_snapshots_2_12}, {br_snapshots_1_12}, {br_snapshots_0_12}};\n wire [7:0][5:0] _GEN_13 = {{br_snapshots_7_13}, {br_snapshots_6_13}, {br_snapshots_5_13}, {br_snapshots_4_13}, {br_snapshots_3_13}, {br_snapshots_2_13}, {br_snapshots_1_13}, {br_snapshots_0_13}};\n wire [7:0][5:0] _GEN_14 = {{br_snapshots_7_14}, {br_snapshots_6_14}, {br_snapshots_5_14}, {br_snapshots_4_14}, {br_snapshots_3_14}, {br_snapshots_2_14}, {br_snapshots_1_14}, {br_snapshots_0_14}};\n wire [7:0][5:0] _GEN_15 = {{br_snapshots_7_15}, {br_snapshots_6_15}, {br_snapshots_5_15}, {br_snapshots_4_15}, {br_snapshots_3_15}, {br_snapshots_2_15}, {br_snapshots_1_15}, {br_snapshots_0_15}};\n wire [7:0][5:0] _GEN_16 = {{br_snapshots_7_16}, {br_snapshots_6_16}, {br_snapshots_5_16}, {br_snapshots_4_16}, {br_snapshots_3_16}, {br_snapshots_2_16}, {br_snapshots_1_16}, {br_snapshots_0_16}};\n wire [7:0][5:0] _GEN_17 = {{br_snapshots_7_17}, {br_snapshots_6_17}, {br_snapshots_5_17}, {br_snapshots_4_17}, {br_snapshots_3_17}, {br_snapshots_2_17}, {br_snapshots_1_17}, {br_snapshots_0_17}};\n wire [7:0][5:0] _GEN_18 = {{br_snapshots_7_18}, {br_snapshots_6_18}, {br_snapshots_5_18}, {br_snapshots_4_18}, {br_snapshots_3_18}, {br_snapshots_2_18}, {br_snapshots_1_18}, {br_snapshots_0_18}};\n wire [7:0][5:0] _GEN_19 = {{br_snapshots_7_19}, {br_snapshots_6_19}, {br_snapshots_5_19}, {br_snapshots_4_19}, {br_snapshots_3_19}, {br_snapshots_2_19}, {br_snapshots_1_19}, {br_snapshots_0_19}};\n wire [7:0][5:0] _GEN_20 = {{br_snapshots_7_20}, {br_snapshots_6_20}, {br_snapshots_5_20}, {br_snapshots_4_20}, {br_snapshots_3_20}, {br_snapshots_2_20}, {br_snapshots_1_20}, {br_snapshots_0_20}};\n wire [7:0][5:0] _GEN_21 = {{br_snapshots_7_21}, {br_snapshots_6_21}, {br_snapshots_5_21}, {br_snapshots_4_21}, {br_snapshots_3_21}, {br_snapshots_2_21}, {br_snapshots_1_21}, {br_snapshots_0_21}};\n wire [7:0][5:0] _GEN_22 = {{br_snapshots_7_22}, {br_snapshots_6_22}, {br_snapshots_5_22}, {br_snapshots_4_22}, {br_snapshots_3_22}, {br_snapshots_2_22}, {br_snapshots_1_22}, {br_snapshots_0_22}};\n wire [7:0][5:0] _GEN_23 = {{br_snapshots_7_23}, {br_snapshots_6_23}, {br_snapshots_5_23}, {br_snapshots_4_23}, {br_snapshots_3_23}, {br_snapshots_2_23}, {br_snapshots_1_23}, {br_snapshots_0_23}};\n wire [7:0][5:0] _GEN_24 = {{br_snapshots_7_24}, {br_snapshots_6_24}, {br_snapshots_5_24}, {br_snapshots_4_24}, {br_snapshots_3_24}, {br_snapshots_2_24}, {br_snapshots_1_24}, {br_snapshots_0_24}};\n wire [7:0][5:0] _GEN_25 = {{br_snapshots_7_25}, {br_snapshots_6_25}, {br_snapshots_5_25}, {br_snapshots_4_25}, {br_snapshots_3_25}, {br_snapshots_2_25}, {br_snapshots_1_25}, {br_snapshots_0_25}};\n wire [7:0][5:0] _GEN_26 = {{br_snapshots_7_26}, {br_snapshots_6_26}, {br_snapshots_5_26}, {br_snapshots_4_26}, {br_snapshots_3_26}, {br_snapshots_2_26}, {br_snapshots_1_26}, {br_snapshots_0_26}};\n wire [7:0][5:0] _GEN_27 = {{br_snapshots_7_27}, {br_snapshots_6_27}, {br_snapshots_5_27}, {br_snapshots_4_27}, {br_snapshots_3_27}, {br_snapshots_2_27}, {br_snapshots_1_27}, {br_snapshots_0_27}};\n wire [7:0][5:0] _GEN_28 = {{br_snapshots_7_28}, {br_snapshots_6_28}, {br_snapshots_5_28}, {br_snapshots_4_28}, {br_snapshots_3_28}, {br_snapshots_2_28}, {br_snapshots_1_28}, {br_snapshots_0_28}};\n wire [7:0][5:0] _GEN_29 = {{br_snapshots_7_29}, {br_snapshots_6_29}, {br_snapshots_5_29}, {br_snapshots_4_29}, {br_snapshots_3_29}, {br_snapshots_2_29}, {br_snapshots_1_29}, {br_snapshots_0_29}};\n wire [7:0][5:0] _GEN_30 = {{br_snapshots_7_30}, {br_snapshots_6_30}, {br_snapshots_5_30}, {br_snapshots_4_30}, {br_snapshots_3_30}, {br_snapshots_2_30}, {br_snapshots_1_30}, {br_snapshots_0_30}};\n wire [7:0][5:0] _GEN_31 = {{br_snapshots_7_31}, {br_snapshots_6_31}, {br_snapshots_5_31}, {br_snapshots_4_31}, {br_snapshots_3_31}, {br_snapshots_2_31}, {br_snapshots_1_31}, {br_snapshots_0_31}};\n wire [63:0] _remap_ldsts_oh_T = 64'h1 << io_remap_reqs_0_ldst;\n wire [31:0] _GEN_32 = _remap_ldsts_oh_T[31:0] & {32{io_remap_reqs_0_valid}};\n wire [5:0] remapped_row_1 = _GEN_32[0] ? io_remap_reqs_0_pdst : map_table_0;\n wire [5:0] remap_table_1_1 = _GEN_32[1] ? io_remap_reqs_0_pdst : map_table_1;\n wire [5:0] remap_table_1_2 = _GEN_32[2] ? io_remap_reqs_0_pdst : map_table_2;\n wire [5:0] remap_table_1_3 = _GEN_32[3] ? io_remap_reqs_0_pdst : map_table_3;\n wire [5:0] remap_table_1_4 = _GEN_32[4] ? io_remap_reqs_0_pdst : map_table_4;\n wire [5:0] remap_table_1_5 = _GEN_32[5] ? io_remap_reqs_0_pdst : map_table_5;\n wire [5:0] remap_table_1_6 = _GEN_32[6] ? io_remap_reqs_0_pdst : map_table_6;\n wire [5:0] remap_table_1_7 = _GEN_32[7] ? io_remap_reqs_0_pdst : map_table_7;\n wire [5:0] remap_table_1_8 = _GEN_32[8] ? io_remap_reqs_0_pdst : map_table_8;\n wire [5:0] remap_table_1_9 = _GEN_32[9] ? io_remap_reqs_0_pdst : map_table_9;\n wire [5:0] remap_table_1_10 = _GEN_32[10] ? io_remap_reqs_0_pdst : map_table_10;\n wire [5:0] remap_table_1_11 = _GEN_32[11] ? io_remap_reqs_0_pdst : map_table_11;\n wire [5:0] remap_table_1_12 = _GEN_32[12] ? io_remap_reqs_0_pdst : map_table_12;\n wire [5:0] remap_table_1_13 = _GEN_32[13] ? io_remap_reqs_0_pdst : map_table_13;\n wire [5:0] remap_table_1_14 = _GEN_32[14] ? io_remap_reqs_0_pdst : map_table_14;\n wire [5:0] remap_table_1_15 = _GEN_32[15] ? io_remap_reqs_0_pdst : map_table_15;\n wire [5:0] remap_table_1_16 = _GEN_32[16] ? io_remap_reqs_0_pdst : map_table_16;\n wire [5:0] remap_table_1_17 = _GEN_32[17] ? io_remap_reqs_0_pdst : map_table_17;\n wire [5:0] remap_table_1_18 = _GEN_32[18] ? io_remap_reqs_0_pdst : map_table_18;\n wire [5:0] remap_table_1_19 = _GEN_32[19] ? io_remap_reqs_0_pdst : map_table_19;\n wire [5:0] remap_table_1_20 = _GEN_32[20] ? io_remap_reqs_0_pdst : map_table_20;\n wire [5:0] remap_table_1_21 = _GEN_32[21] ? io_remap_reqs_0_pdst : map_table_21;\n wire [5:0] remap_table_1_22 = _GEN_32[22] ? io_remap_reqs_0_pdst : map_table_22;\n wire [5:0] remap_table_1_23 = _GEN_32[23] ? io_remap_reqs_0_pdst : map_table_23;\n wire [5:0] remap_table_1_24 = _GEN_32[24] ? io_remap_reqs_0_pdst : map_table_24;\n wire [5:0] remap_table_1_25 = _GEN_32[25] ? io_remap_reqs_0_pdst : map_table_25;\n wire [5:0] remap_table_1_26 = _GEN_32[26] ? io_remap_reqs_0_pdst : map_table_26;\n wire [5:0] remap_table_1_27 = _GEN_32[27] ? io_remap_reqs_0_pdst : map_table_27;\n wire [5:0] remap_table_1_28 = _GEN_32[28] ? io_remap_reqs_0_pdst : map_table_28;\n wire [5:0] remap_table_1_29 = _GEN_32[29] ? io_remap_reqs_0_pdst : map_table_29;\n wire [5:0] remap_table_1_30 = _GEN_32[30] ? io_remap_reqs_0_pdst : map_table_30;\n wire [5:0] remap_table_1_31 = _GEN_32[31] ? io_remap_reqs_0_pdst : map_table_31;\n always @(posedge clock) begin\n if (reset) begin\n map_table_0 <= 6'h0;\n map_table_1 <= 6'h0;\n map_table_2 <= 6'h0;\n map_table_3 <= 6'h0;\n map_table_4 <= 6'h0;\n map_table_5 <= 6'h0;\n map_table_6 <= 6'h0;\n map_table_7 <= 6'h0;\n map_table_8 <= 6'h0;\n map_table_9 <= 6'h0;\n map_table_10 <= 6'h0;\n map_table_11 <= 6'h0;\n map_table_12 <= 6'h0;\n map_table_13 <= 6'h0;\n map_table_14 <= 6'h0;\n map_table_15 <= 6'h0;\n map_table_16 <= 6'h0;\n map_table_17 <= 6'h0;\n map_table_18 <= 6'h0;\n map_table_19 <= 6'h0;\n map_table_20 <= 6'h0;\n map_table_21 <= 6'h0;\n map_table_22 <= 6'h0;\n map_table_23 <= 6'h0;\n map_table_24 <= 6'h0;\n map_table_25 <= 6'h0;\n map_table_26 <= 6'h0;\n map_table_27 <= 6'h0;\n map_table_28 <= 6'h0;\n map_table_29 <= 6'h0;\n map_table_30 <= 6'h0;\n map_table_31 <= 6'h0;\n end\n else if (io_brupdate_b2_mispredict) begin\n map_table_0 <= _GEN_0[io_brupdate_b2_uop_br_tag];\n map_table_1 <= _GEN_1[io_brupdate_b2_uop_br_tag];\n map_table_2 <= _GEN_2[io_brupdate_b2_uop_br_tag];\n map_table_3 <= _GEN_3[io_brupdate_b2_uop_br_tag];\n map_table_4 <= _GEN_4[io_brupdate_b2_uop_br_tag];\n map_table_5 <= _GEN_5[io_brupdate_b2_uop_br_tag];\n map_table_6 <= _GEN_6[io_brupdate_b2_uop_br_tag];\n map_table_7 <= _GEN_7[io_brupdate_b2_uop_br_tag];\n map_table_8 <= _GEN_8[io_brupdate_b2_uop_br_tag];\n map_table_9 <= _GEN_9[io_brupdate_b2_uop_br_tag];\n map_table_10 <= _GEN_10[io_brupdate_b2_uop_br_tag];\n map_table_11 <= _GEN_11[io_brupdate_b2_uop_br_tag];\n map_table_12 <= _GEN_12[io_brupdate_b2_uop_br_tag];\n map_table_13 <= _GEN_13[io_brupdate_b2_uop_br_tag];\n map_table_14 <= _GEN_14[io_brupdate_b2_uop_br_tag];\n map_table_15 <= _GEN_15[io_brupdate_b2_uop_br_tag];\n map_table_16 <= _GEN_16[io_brupdate_b2_uop_br_tag];\n map_table_17 <= _GEN_17[io_brupdate_b2_uop_br_tag];\n map_table_18 <= _GEN_18[io_brupdate_b2_uop_br_tag];\n map_table_19 <= _GEN_19[io_brupdate_b2_uop_br_tag];\n map_table_20 <= _GEN_20[io_brupdate_b2_uop_br_tag];\n map_table_21 <= _GEN_21[io_brupdate_b2_uop_br_tag];\n map_table_22 <= _GEN_22[io_brupdate_b2_uop_br_tag];\n map_table_23 <= _GEN_23[io_brupdate_b2_uop_br_tag];\n map_table_24 <= _GEN_24[io_brupdate_b2_uop_br_tag];\n map_table_25 <= _GEN_25[io_brupdate_b2_uop_br_tag];\n map_table_26 <= _GEN_26[io_brupdate_b2_uop_br_tag];\n map_table_27 <= _GEN_27[io_brupdate_b2_uop_br_tag];\n map_table_28 <= _GEN_28[io_brupdate_b2_uop_br_tag];\n map_table_29 <= _GEN_29[io_brupdate_b2_uop_br_tag];\n map_table_30 <= _GEN_30[io_brupdate_b2_uop_br_tag];\n map_table_31 <= _GEN_31[io_brupdate_b2_uop_br_tag];\n end\n else begin\n if (_GEN_32[0])\n map_table_0 <= io_remap_reqs_0_pdst;\n if (_GEN_32[1])\n map_table_1 <= io_remap_reqs_0_pdst;\n if (_GEN_32[2])\n map_table_2 <= io_remap_reqs_0_pdst;\n if (_GEN_32[3])\n map_table_3 <= io_remap_reqs_0_pdst;\n if (_GEN_32[4])\n map_table_4 <= io_remap_reqs_0_pdst;\n if (_GEN_32[5])\n map_table_5 <= io_remap_reqs_0_pdst;\n if (_GEN_32[6])\n map_table_6 <= io_remap_reqs_0_pdst;\n if (_GEN_32[7])\n map_table_7 <= io_remap_reqs_0_pdst;\n if (_GEN_32[8])\n map_table_8 <= io_remap_reqs_0_pdst;\n if (_GEN_32[9])\n map_table_9 <= io_remap_reqs_0_pdst;\n if (_GEN_32[10])\n map_table_10 <= io_remap_reqs_0_pdst;\n if (_GEN_32[11])\n map_table_11 <= io_remap_reqs_0_pdst;\n if (_GEN_32[12])\n map_table_12 <= io_remap_reqs_0_pdst;\n if (_GEN_32[13])\n map_table_13 <= io_remap_reqs_0_pdst;\n if (_GEN_32[14])\n map_table_14 <= io_remap_reqs_0_pdst;\n if (_GEN_32[15])\n map_table_15 <= io_remap_reqs_0_pdst;\n if (_GEN_32[16])\n map_table_16 <= io_remap_reqs_0_pdst;\n if (_GEN_32[17])\n map_table_17 <= io_remap_reqs_0_pdst;\n if (_GEN_32[18])\n map_table_18 <= io_remap_reqs_0_pdst;\n if (_GEN_32[19])\n map_table_19 <= io_remap_reqs_0_pdst;\n if (_GEN_32[20])\n map_table_20 <= io_remap_reqs_0_pdst;\n if (_GEN_32[21])\n map_table_21 <= io_remap_reqs_0_pdst;\n if (_GEN_32[22])\n map_table_22 <= io_remap_reqs_0_pdst;\n if (_GEN_32[23])\n map_table_23 <= io_remap_reqs_0_pdst;\n if (_GEN_32[24])\n map_table_24 <= io_remap_reqs_0_pdst;\n if (_GEN_32[25])\n map_table_25 <= io_remap_reqs_0_pdst;\n if (_GEN_32[26])\n map_table_26 <= io_remap_reqs_0_pdst;\n if (_GEN_32[27])\n map_table_27 <= io_remap_reqs_0_pdst;\n if (_GEN_32[28])\n map_table_28 <= io_remap_reqs_0_pdst;\n if (_GEN_32[29])\n map_table_29 <= io_remap_reqs_0_pdst;\n if (_GEN_32[30])\n map_table_30 <= io_remap_reqs_0_pdst;\n if (_GEN_32[31])\n map_table_31 <= io_remap_reqs_0_pdst;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h0) begin\n br_snapshots_0_0 <= remapped_row_1;\n br_snapshots_0_1 <= remap_table_1_1;\n br_snapshots_0_2 <= remap_table_1_2;\n br_snapshots_0_3 <= remap_table_1_3;\n br_snapshots_0_4 <= remap_table_1_4;\n br_snapshots_0_5 <= remap_table_1_5;\n br_snapshots_0_6 <= remap_table_1_6;\n br_snapshots_0_7 <= remap_table_1_7;\n br_snapshots_0_8 <= remap_table_1_8;\n br_snapshots_0_9 <= remap_table_1_9;\n br_snapshots_0_10 <= remap_table_1_10;\n br_snapshots_0_11 <= remap_table_1_11;\n br_snapshots_0_12 <= remap_table_1_12;\n br_snapshots_0_13 <= remap_table_1_13;\n br_snapshots_0_14 <= remap_table_1_14;\n br_snapshots_0_15 <= remap_table_1_15;\n br_snapshots_0_16 <= remap_table_1_16;\n br_snapshots_0_17 <= remap_table_1_17;\n br_snapshots_0_18 <= remap_table_1_18;\n br_snapshots_0_19 <= remap_table_1_19;\n br_snapshots_0_20 <= remap_table_1_20;\n br_snapshots_0_21 <= remap_table_1_21;\n br_snapshots_0_22 <= remap_table_1_22;\n br_snapshots_0_23 <= remap_table_1_23;\n br_snapshots_0_24 <= remap_table_1_24;\n br_snapshots_0_25 <= remap_table_1_25;\n br_snapshots_0_26 <= remap_table_1_26;\n br_snapshots_0_27 <= remap_table_1_27;\n br_snapshots_0_28 <= remap_table_1_28;\n br_snapshots_0_29 <= remap_table_1_29;\n br_snapshots_0_30 <= remap_table_1_30;\n br_snapshots_0_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h1) begin\n br_snapshots_1_0 <= remapped_row_1;\n br_snapshots_1_1 <= remap_table_1_1;\n br_snapshots_1_2 <= remap_table_1_2;\n br_snapshots_1_3 <= remap_table_1_3;\n br_snapshots_1_4 <= remap_table_1_4;\n br_snapshots_1_5 <= remap_table_1_5;\n br_snapshots_1_6 <= remap_table_1_6;\n br_snapshots_1_7 <= remap_table_1_7;\n br_snapshots_1_8 <= remap_table_1_8;\n br_snapshots_1_9 <= remap_table_1_9;\n br_snapshots_1_10 <= remap_table_1_10;\n br_snapshots_1_11 <= remap_table_1_11;\n br_snapshots_1_12 <= remap_table_1_12;\n br_snapshots_1_13 <= remap_table_1_13;\n br_snapshots_1_14 <= remap_table_1_14;\n br_snapshots_1_15 <= remap_table_1_15;\n br_snapshots_1_16 <= remap_table_1_16;\n br_snapshots_1_17 <= remap_table_1_17;\n br_snapshots_1_18 <= remap_table_1_18;\n br_snapshots_1_19 <= remap_table_1_19;\n br_snapshots_1_20 <= remap_table_1_20;\n br_snapshots_1_21 <= remap_table_1_21;\n br_snapshots_1_22 <= remap_table_1_22;\n br_snapshots_1_23 <= remap_table_1_23;\n br_snapshots_1_24 <= remap_table_1_24;\n br_snapshots_1_25 <= remap_table_1_25;\n br_snapshots_1_26 <= remap_table_1_26;\n br_snapshots_1_27 <= remap_table_1_27;\n br_snapshots_1_28 <= remap_table_1_28;\n br_snapshots_1_29 <= remap_table_1_29;\n br_snapshots_1_30 <= remap_table_1_30;\n br_snapshots_1_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h2) begin\n br_snapshots_2_0 <= remapped_row_1;\n br_snapshots_2_1 <= remap_table_1_1;\n br_snapshots_2_2 <= remap_table_1_2;\n br_snapshots_2_3 <= remap_table_1_3;\n br_snapshots_2_4 <= remap_table_1_4;\n br_snapshots_2_5 <= remap_table_1_5;\n br_snapshots_2_6 <= remap_table_1_6;\n br_snapshots_2_7 <= remap_table_1_7;\n br_snapshots_2_8 <= remap_table_1_8;\n br_snapshots_2_9 <= remap_table_1_9;\n br_snapshots_2_10 <= remap_table_1_10;\n br_snapshots_2_11 <= remap_table_1_11;\n br_snapshots_2_12 <= remap_table_1_12;\n br_snapshots_2_13 <= remap_table_1_13;\n br_snapshots_2_14 <= remap_table_1_14;\n br_snapshots_2_15 <= remap_table_1_15;\n br_snapshots_2_16 <= remap_table_1_16;\n br_snapshots_2_17 <= remap_table_1_17;\n br_snapshots_2_18 <= remap_table_1_18;\n br_snapshots_2_19 <= remap_table_1_19;\n br_snapshots_2_20 <= remap_table_1_20;\n br_snapshots_2_21 <= remap_table_1_21;\n br_snapshots_2_22 <= remap_table_1_22;\n br_snapshots_2_23 <= remap_table_1_23;\n br_snapshots_2_24 <= remap_table_1_24;\n br_snapshots_2_25 <= remap_table_1_25;\n br_snapshots_2_26 <= remap_table_1_26;\n br_snapshots_2_27 <= remap_table_1_27;\n br_snapshots_2_28 <= remap_table_1_28;\n br_snapshots_2_29 <= remap_table_1_29;\n br_snapshots_2_30 <= remap_table_1_30;\n br_snapshots_2_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h3) begin\n br_snapshots_3_0 <= remapped_row_1;\n br_snapshots_3_1 <= remap_table_1_1;\n br_snapshots_3_2 <= remap_table_1_2;\n br_snapshots_3_3 <= remap_table_1_3;\n br_snapshots_3_4 <= remap_table_1_4;\n br_snapshots_3_5 <= remap_table_1_5;\n br_snapshots_3_6 <= remap_table_1_6;\n br_snapshots_3_7 <= remap_table_1_7;\n br_snapshots_3_8 <= remap_table_1_8;\n br_snapshots_3_9 <= remap_table_1_9;\n br_snapshots_3_10 <= remap_table_1_10;\n br_snapshots_3_11 <= remap_table_1_11;\n br_snapshots_3_12 <= remap_table_1_12;\n br_snapshots_3_13 <= remap_table_1_13;\n br_snapshots_3_14 <= remap_table_1_14;\n br_snapshots_3_15 <= remap_table_1_15;\n br_snapshots_3_16 <= remap_table_1_16;\n br_snapshots_3_17 <= remap_table_1_17;\n br_snapshots_3_18 <= remap_table_1_18;\n br_snapshots_3_19 <= remap_table_1_19;\n br_snapshots_3_20 <= remap_table_1_20;\n br_snapshots_3_21 <= remap_table_1_21;\n br_snapshots_3_22 <= remap_table_1_22;\n br_snapshots_3_23 <= remap_table_1_23;\n br_snapshots_3_24 <= remap_table_1_24;\n br_snapshots_3_25 <= remap_table_1_25;\n br_snapshots_3_26 <= remap_table_1_26;\n br_snapshots_3_27 <= remap_table_1_27;\n br_snapshots_3_28 <= remap_table_1_28;\n br_snapshots_3_29 <= remap_table_1_29;\n br_snapshots_3_30 <= remap_table_1_30;\n br_snapshots_3_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h4) begin\n br_snapshots_4_0 <= remapped_row_1;\n br_snapshots_4_1 <= remap_table_1_1;\n br_snapshots_4_2 <= remap_table_1_2;\n br_snapshots_4_3 <= remap_table_1_3;\n br_snapshots_4_4 <= remap_table_1_4;\n br_snapshots_4_5 <= remap_table_1_5;\n br_snapshots_4_6 <= remap_table_1_6;\n br_snapshots_4_7 <= remap_table_1_7;\n br_snapshots_4_8 <= remap_table_1_8;\n br_snapshots_4_9 <= remap_table_1_9;\n br_snapshots_4_10 <= remap_table_1_10;\n br_snapshots_4_11 <= remap_table_1_11;\n br_snapshots_4_12 <= remap_table_1_12;\n br_snapshots_4_13 <= remap_table_1_13;\n br_snapshots_4_14 <= remap_table_1_14;\n br_snapshots_4_15 <= remap_table_1_15;\n br_snapshots_4_16 <= remap_table_1_16;\n br_snapshots_4_17 <= remap_table_1_17;\n br_snapshots_4_18 <= remap_table_1_18;\n br_snapshots_4_19 <= remap_table_1_19;\n br_snapshots_4_20 <= remap_table_1_20;\n br_snapshots_4_21 <= remap_table_1_21;\n br_snapshots_4_22 <= remap_table_1_22;\n br_snapshots_4_23 <= remap_table_1_23;\n br_snapshots_4_24 <= remap_table_1_24;\n br_snapshots_4_25 <= remap_table_1_25;\n br_snapshots_4_26 <= remap_table_1_26;\n br_snapshots_4_27 <= remap_table_1_27;\n br_snapshots_4_28 <= remap_table_1_28;\n br_snapshots_4_29 <= remap_table_1_29;\n br_snapshots_4_30 <= remap_table_1_30;\n br_snapshots_4_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h5) begin\n br_snapshots_5_0 <= remapped_row_1;\n br_snapshots_5_1 <= remap_table_1_1;\n br_snapshots_5_2 <= remap_table_1_2;\n br_snapshots_5_3 <= remap_table_1_3;\n br_snapshots_5_4 <= remap_table_1_4;\n br_snapshots_5_5 <= remap_table_1_5;\n br_snapshots_5_6 <= remap_table_1_6;\n br_snapshots_5_7 <= remap_table_1_7;\n br_snapshots_5_8 <= remap_table_1_8;\n br_snapshots_5_9 <= remap_table_1_9;\n br_snapshots_5_10 <= remap_table_1_10;\n br_snapshots_5_11 <= remap_table_1_11;\n br_snapshots_5_12 <= remap_table_1_12;\n br_snapshots_5_13 <= remap_table_1_13;\n br_snapshots_5_14 <= remap_table_1_14;\n br_snapshots_5_15 <= remap_table_1_15;\n br_snapshots_5_16 <= remap_table_1_16;\n br_snapshots_5_17 <= remap_table_1_17;\n br_snapshots_5_18 <= remap_table_1_18;\n br_snapshots_5_19 <= remap_table_1_19;\n br_snapshots_5_20 <= remap_table_1_20;\n br_snapshots_5_21 <= remap_table_1_21;\n br_snapshots_5_22 <= remap_table_1_22;\n br_snapshots_5_23 <= remap_table_1_23;\n br_snapshots_5_24 <= remap_table_1_24;\n br_snapshots_5_25 <= remap_table_1_25;\n br_snapshots_5_26 <= remap_table_1_26;\n br_snapshots_5_27 <= remap_table_1_27;\n br_snapshots_5_28 <= remap_table_1_28;\n br_snapshots_5_29 <= remap_table_1_29;\n br_snapshots_5_30 <= remap_table_1_30;\n br_snapshots_5_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & io_ren_br_tags_0_bits == 3'h6) begin\n br_snapshots_6_0 <= remapped_row_1;\n br_snapshots_6_1 <= remap_table_1_1;\n br_snapshots_6_2 <= remap_table_1_2;\n br_snapshots_6_3 <= remap_table_1_3;\n br_snapshots_6_4 <= remap_table_1_4;\n br_snapshots_6_5 <= remap_table_1_5;\n br_snapshots_6_6 <= remap_table_1_6;\n br_snapshots_6_7 <= remap_table_1_7;\n br_snapshots_6_8 <= remap_table_1_8;\n br_snapshots_6_9 <= remap_table_1_9;\n br_snapshots_6_10 <= remap_table_1_10;\n br_snapshots_6_11 <= remap_table_1_11;\n br_snapshots_6_12 <= remap_table_1_12;\n br_snapshots_6_13 <= remap_table_1_13;\n br_snapshots_6_14 <= remap_table_1_14;\n br_snapshots_6_15 <= remap_table_1_15;\n br_snapshots_6_16 <= remap_table_1_16;\n br_snapshots_6_17 <= remap_table_1_17;\n br_snapshots_6_18 <= remap_table_1_18;\n br_snapshots_6_19 <= remap_table_1_19;\n br_snapshots_6_20 <= remap_table_1_20;\n br_snapshots_6_21 <= remap_table_1_21;\n br_snapshots_6_22 <= remap_table_1_22;\n br_snapshots_6_23 <= remap_table_1_23;\n br_snapshots_6_24 <= remap_table_1_24;\n br_snapshots_6_25 <= remap_table_1_25;\n br_snapshots_6_26 <= remap_table_1_26;\n br_snapshots_6_27 <= remap_table_1_27;\n br_snapshots_6_28 <= remap_table_1_28;\n br_snapshots_6_29 <= remap_table_1_29;\n br_snapshots_6_30 <= remap_table_1_30;\n br_snapshots_6_31 <= remap_table_1_31;\n end\n if (io_ren_br_tags_0_valid & (&io_ren_br_tags_0_bits)) begin\n br_snapshots_7_0 <= remapped_row_1;\n br_snapshots_7_1 <= remap_table_1_1;\n br_snapshots_7_2 <= remap_table_1_2;\n br_snapshots_7_3 <= remap_table_1_3;\n br_snapshots_7_4 <= remap_table_1_4;\n br_snapshots_7_5 <= remap_table_1_5;\n br_snapshots_7_6 <= remap_table_1_6;\n br_snapshots_7_7 <= remap_table_1_7;\n br_snapshots_7_8 <= remap_table_1_8;\n br_snapshots_7_9 <= remap_table_1_9;\n br_snapshots_7_10 <= remap_table_1_10;\n br_snapshots_7_11 <= remap_table_1_11;\n br_snapshots_7_12 <= remap_table_1_12;\n br_snapshots_7_13 <= remap_table_1_13;\n br_snapshots_7_14 <= remap_table_1_14;\n br_snapshots_7_15 <= remap_table_1_15;\n br_snapshots_7_16 <= remap_table_1_16;\n br_snapshots_7_17 <= remap_table_1_17;\n br_snapshots_7_18 <= remap_table_1_18;\n br_snapshots_7_19 <= remap_table_1_19;\n br_snapshots_7_20 <= remap_table_1_20;\n br_snapshots_7_21 <= remap_table_1_21;\n br_snapshots_7_22 <= remap_table_1_22;\n br_snapshots_7_23 <= remap_table_1_23;\n br_snapshots_7_24 <= remap_table_1_24;\n br_snapshots_7_25 <= remap_table_1_25;\n br_snapshots_7_26 <= remap_table_1_26;\n br_snapshots_7_27 <= remap_table_1_27;\n br_snapshots_7_28 <= remap_table_1_28;\n br_snapshots_7_29 <= remap_table_1_29;\n br_snapshots_7_30 <= remap_table_1_30;\n br_snapshots_7_31 <= remap_table_1_31;\n end\n end\n assign io_map_resps_0_prs1 = _GEN[io_map_reqs_0_lrs1[4:0]];\n assign io_map_resps_0_prs2 = _GEN[io_map_reqs_0_lrs2[4:0]];\n assign io_map_resps_0_prs3 = _GEN[io_map_reqs_0_lrs3[4:0]];\n assign io_map_resps_0_stale_pdst = _GEN[io_map_reqs_0_ldst[4:0]];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n/** This black-boxes an Async Reset\n * (or Set)\n * Register.\n * \n * Because Chisel doesn't support\n * parameterized black boxes, \n * we unfortunately have to \n * instantiate a number of these.\n * \n * We also have to hard-code the set/\n * reset behavior.\n * \n * Do not confuse an asynchronous\n * reset signal with an asynchronously\n * reset reg. You should still \n * properly synchronize your reset \n * deassertion.\n * \n * @param d Data input\n * @param q Data Output\n * @param clk Clock Input\n * @param rst Reset Input\n * @param en Write Enable Input\n * \n */\n\nclass AsyncResetReg(resetValue: Int = 0) extends RawModule {\n val io = IO(new Bundle {\n val d = Input(Bool())\n val q = Output(Bool())\n val en = Input(Bool())\n\n val clk = Input(Clock())\n val rst = Input(Reset())\n })\n\n val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nclass SimpleRegIO(val w: Int) extends Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n}\n\nclass AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {\n override def desiredName = s\"AsyncResetRegVec_w${w}_i${init}\"\n\n val io = IO(new SimpleRegIO(w))\n\n val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nobject AsyncResetReg {\n // Create Single Registers\n def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {\n val reg = Module(new AsyncResetReg(if (init) 1 else 0))\n reg.io.d := d\n reg.io.clk := clk\n reg.io.rst := rst\n reg.io.en := true.B\n name.foreach(reg.suggestName(_))\n reg.io.q\n }\n\n def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)\n def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))\n\n // Create Vectors of Registers\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {\n val w = updateData.getWidth max resetData.bitLength\n val reg = Module(new AsyncResetRegVec(w, resetData))\n name.foreach(reg.suggestName(_))\n reg.io.d := updateData\n reg.io.en := enable\n reg.io.q\n }\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,\n resetData, enable, Some(name))\n\n\n def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))\n\n def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)\n def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))\n\n def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)\n def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))\n}", + "response": "module AsyncResetRegVec_w2_i0(\n input clock,\n input reset,\n input [1:0] io_d,\n output [1:0] io_q\n);\n\n reg [1:0] reg_0;\n always @(posedge clock or posedge reset) begin\n if (reset)\n reg_0 <= 2'h0;\n else\n reg_0 <= io_d;\n end\n assign io_q = reg_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_1(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport scala.collection.SortedMap\n\nimport chisel3._\nimport org.chipsalliance.cde.config.Parameters\n\n/** JTAG signals, viewed from the master side\n */\nclass JTAGIO(hasTRSTn: Boolean = false) extends Bundle {\n val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None\n val TCK = Output(Clock())\n val TMS = Output(Bool())\n val TDI = Output(Bool())\n val TDO = Input(new Tristate())\n\n}\n\n/** JTAG block output signals.\n */\nclass JtagOutput(irLength: Int) extends Bundle {\n val state = Output(JtagState.State.chiselType()) // state, transitions on TCK rising edge\n val instruction = Output(UInt(irLength.W)) // current active instruction\n val tapIsInTestLogicReset = Output(Bool()) // synchronously asserted in Test-Logic-Reset state, should NOT hold the FSM in reset\n\n}\n\nclass JtagControl extends Bundle {\n val jtag_reset = Input(AsyncReset())\n}\n\n/** Aggregate JTAG block IO.\n */\nclass JtagBlockIO(irLength: Int, hasIdcode:Boolean = true) extends Bundle {\n\n val jtag = Flipped(new JTAGIO())\n val control = new JtagControl\n val output = new JtagOutput(irLength)\n val idcode = if (hasIdcode) Some(Input(new JTAGIdcodeBundle())) else None\n\n}\n\n/** Internal controller block IO with data shift outputs.\n */\nclass JtagControllerIO(irLength: Int) extends JtagBlockIO(irLength, false) {\n val dataChainOut = Output(new ShifterIO)\n val dataChainIn = Input(new ShifterIO)\n\n}\n\n/** JTAG TAP controller internal block, responsible for instruction decode and data register chain\n * control signal generation.\n *\n * Misc notes:\n * - Figure 6-3 and 6-4 provides examples with timing behavior\n */\nclass JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val p: Parameters) extends Module {\n require(irLength >= 2) // 7.1.1a\n\n val io = IO(new JtagControllerIO(irLength))\n\n val tdo = Wire(Bool()) // 4.4.1c TDI should appear here uninverted after shifting\n val tdo_driven = Wire(Bool())\n\n val clock_falling = WireInit((!clock.asUInt).asClock)\n\n val tapIsInTestLogicReset = Wire(Bool())\n\n //\n // JTAG state machine\n //\n\n val currState = Wire(JtagState.State.chiselType())\n\n // At this point, the TRSTn should already have been\n // combined with any POR, and it should also be\n // synchronized to TCK.\n require(!io.jtag.TRSTn.isDefined, \"TRSTn should be absorbed into jtckPOReset outside of JtagTapController.\")\n withReset(io.control.jtag_reset) {\n val stateMachine = Module(new JtagStateMachine)\n stateMachine.suggestName(\"stateMachine\")\n stateMachine.io.tms := io.jtag.TMS\n currState := stateMachine.io.currState\n io.output.state := stateMachine.io.currState\n // 4.5.1a TDO changes on falling edge of TCK, 6.1.2.1d driver active on first TCK falling edge in ShiftIR and ShiftDR states\n withClock(clock_falling) {\n val TDOdata = RegNext(next=tdo, init=false.B).suggestName(\"tdoReg\")\n val TDOdriven = RegNext(next=tdo_driven, init=false.B).suggestName(\"tdoeReg\")\n io.jtag.TDO.data := TDOdata\n io.jtag.TDO.driven := TDOdriven\n }\n }\n\n //\n // Instruction Register\n //\n // 7.1.1d IR shifter two LSBs must be b01 pattern\n // TODO: 7.1.1d allow design-specific IR bits, 7.1.1e (rec) should be a fixed pattern\n // 7.2.1a behavior of instruction register and shifters\n val irChain = Module(CaptureUpdateChain(UInt(irLength.W)))\n irChain.suggestName(\"irChain\")\n irChain.io.chainIn.shift := currState === JtagState.ShiftIR.U\n irChain.io.chainIn.data := io.jtag.TDI\n irChain.io.chainIn.capture := currState === JtagState.CaptureIR.U\n irChain.io.chainIn.update := currState === JtagState.UpdateIR.U\n irChain.io.capture.bits := \"b01\".U\n\n withClockAndReset(clock_falling, io.control.jtag_reset) {\n val activeInstruction = RegInit(initialInstruction.U(irLength.W))\n when (tapIsInTestLogicReset) {\n activeInstruction := initialInstruction.U\n }.elsewhen (currState === JtagState.UpdateIR.U) {\n activeInstruction := irChain.io.update.bits\n }\n io.output.instruction := activeInstruction\n }\n\n tapIsInTestLogicReset := currState === JtagState.TestLogicReset.U\n io.output.tapIsInTestLogicReset := tapIsInTestLogicReset\n\n //\n // Data Register\n //\n io.dataChainOut.shift := currState === JtagState.ShiftDR.U\n io.dataChainOut.data := io.jtag.TDI\n io.dataChainOut.capture := currState === JtagState.CaptureDR.U\n io.dataChainOut.update := currState === JtagState.UpdateDR.U\n\n //\n // Output Control\n //\n when (currState === JtagState.ShiftDR.U) {\n tdo := io.dataChainIn.data\n tdo_driven := true.B\n } .elsewhen (currState === JtagState.ShiftIR.U) {\n tdo := irChain.io.chainOut.data\n tdo_driven := true.B\n } .otherwise {\n // Needed when using chisel3._ (See #1160)\n tdo := DontCare\n tdo_driven := false.B\n }\n}\n\nobject JtagTapGenerator {\n /** JTAG TAP generator, enclosed module must be clocked from TCK and reset from output of this\n * block.\n *\n * @param irLength length, in bits, of instruction register, must be at least 2\n * @param instructions map of instruction codes to data register chains that select that data\n * register; multiple instructions may map to the same data chain\n * @param idcode optional idcode instruction. idcode UInt will come from outside this core.\n *\n * @note all other instruction codes (not part of instructions or idcode) map to BYPASS\n * @note initial instruction is idcode (if supported), otherwise all ones BYPASS\n *\n * Usage notes:\n * - 4.3.1b TMS must appear high when undriven\n * - 4.3.1c (rec) minimize load presented by TMS\n * - 4.4.1b TDI must appear high when undriven\n * - 4.5.1b TDO must be inactive except when shifting data (undriven? 6.1.2)\n * - 6.1.3.1b TAP controller must not be (re-?)initialized by system reset (allows\n * boundary-scan testing of reset pin)\n * - 6.1 TAP controller can be initialized by a on-chip power on reset generator, the same one\n * that would initialize system logic\n *\n * TODO:\n * - support concatenated scan chains\n */\n def apply(irLength: Int, instructions: Map[BigInt, Chain], icode: Option[BigInt] = None)(implicit p: Parameters): JtagBlockIO = {\n\n val internalIo = Wire(new JtagBlockIO(irLength, icode.isDefined))\n\n\n // Create IDCODE chain if needed\n val allInstructions = icode match {\n case (Some(icode)) => {\n require(!(instructions contains icode), \"instructions may not contain IDCODE\")\n val idcodeChain = Module(CaptureChain(new JTAGIdcodeBundle()))\n idcodeChain.suggestName(\"idcodeChain\")\n val i = internalIo.idcode.get.asUInt\n assert(i % 2.U === 1.U, \"LSB must be set in IDCODE, see 12.1.1d\")\n assert(((i >> 1) & ((1.U << 11) - 1.U)) =/= JtagIdcode.dummyMfrId.U,\n \"IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b\")\n idcodeChain.io.capture.bits := internalIo.idcode.get\n instructions + (icode -> idcodeChain)\n\n }\n case None => instructions\n }\n\n val bypassIcode = (BigInt(1) << irLength) - 1 // required BYPASS instruction\n val initialInstruction = icode.getOrElse(bypassIcode) // 7.2.1e load IDCODE or BYPASS instruction after entry into TestLogicReset\n\n require(!(allInstructions contains bypassIcode), \"instructions may not contain BYPASS code\")\n\n val controllerInternal = Module(new JtagTapController(irLength, initialInstruction))\n\n val unusedChainOut = Wire(new ShifterIO) // De-selected chain output\n unusedChainOut.shift := false.B\n unusedChainOut.data := false.B\n unusedChainOut.capture := false.B\n unusedChainOut.update := false.B\n\n val bypassChain = Module(JtagBypassChain())\n\n // The Great Data Register Chain Mux\n bypassChain.io.chainIn := controllerInternal.io.dataChainOut // for simplicity, doesn't visibly affect anything else\n require(allInstructions.size > 0, \"Seriously? JTAG TAP with no instructions?\")\n\n // Need to ensure that this mapping is ordered to produce deterministic verilog,\n // and neither Map nor groupBy are deterministic.\n // Therefore, we first sort by IDCODE, then sort the groups by the first IDCODE in each group.\n val chainToIcode = (SortedMap(allInstructions.toList:_*).groupBy { case (icode, chain) => chain } map {\n case (chain, icodeToChain) => chain -> icodeToChain.keys\n }).toList.sortBy(_._2.head)\n\n val chainToSelect = chainToIcode map {\n case (chain, icodes) => {\n assume(icodes.size > 0)\n val icodeSelects = icodes map { controllerInternal.io.output.instruction === _.asUInt(irLength.W) }\n chain -> icodeSelects.reduceLeft(_||_)\n }\n }\n\n controllerInternal.io.dataChainIn := bypassChain.io.chainOut // default\n\n def foldOutSelect(res: WhenContext, x: (Chain, Bool)): WhenContext = {\n val (chain, select) = x\n // Continue the WhenContext with if this chain is selected\n res.elsewhen(select) {\n controllerInternal.io.dataChainIn := chain.io.chainOut\n }\n }\n\n val emptyWhen = when (false.B) { } // Empty WhenContext to start things off\n chainToSelect.toSeq.foldLeft(emptyWhen)(foldOutSelect).otherwise {\n controllerInternal.io.dataChainIn := bypassChain.io.chainOut\n }\n\n def mapInSelect(x: (Chain, Bool)): Unit = {\n val (chain, select) = x\n when (select) {\n chain.io.chainIn := controllerInternal.io.dataChainOut\n } .otherwise {\n chain.io.chainIn := unusedChainOut\n }\n }\n\n chainToSelect.map(mapInSelect)\n\n internalIo.jtag <> controllerInternal.io.jtag\n internalIo.control <> controllerInternal.io.control\n internalIo.output <> controllerInternal.io.output\n\n internalIo\n }\n\n}", + "response": "module JtagTapController(\n input clock,\n input reset,\n input io_jtag_TMS,\n input io_jtag_TDI,\n output io_jtag_TDO_data,\n input io_control_jtag_reset,\n output [4:0] io_output_instruction,\n output io_output_tapIsInTestLogicReset,\n output io_dataChainOut_shift,\n output io_dataChainOut_data,\n output io_dataChainOut_capture,\n output io_dataChainOut_update,\n input io_dataChainIn_data\n);\n\n wire _irChain_io_chainOut_data;\n wire [4:0] _irChain_io_update_bits;\n wire [3:0] _stateMachine_io_currState;\n wire clock_falling = ~clock;\n reg tdoReg;\n wire irChain_io_chainIn_update = _stateMachine_io_currState == 4'hD;\n reg [4:0] activeInstruction;\n wire io_dataChainOut_shift_0 = _stateMachine_io_currState == 4'h2;\n always @(posedge clock_falling or posedge io_control_jtag_reset) begin\n if (io_control_jtag_reset) begin\n tdoReg <= 1'h0;\n activeInstruction <= 5'h1;\n end\n else begin\n tdoReg <= io_dataChainOut_shift_0 ? io_dataChainIn_data : _irChain_io_chainOut_data;\n if (&_stateMachine_io_currState)\n activeInstruction <= 5'h1;\n else if (irChain_io_chainIn_update)\n activeInstruction <= _irChain_io_update_bits;\n end\n end\n JtagStateMachine stateMachine (\n .clock (clock),\n .reset (io_control_jtag_reset),\n .io_tms (io_jtag_TMS),\n .io_currState (_stateMachine_io_currState)\n );\n CaptureUpdateChain_UInt5_To_UInt5 irChain (\n .clock (clock),\n .reset (reset),\n .io_chainIn_shift (_stateMachine_io_currState == 4'hA),\n .io_chainIn_data (io_jtag_TDI),\n .io_chainIn_capture (_stateMachine_io_currState == 4'hE),\n .io_chainIn_update (irChain_io_chainIn_update),\n .io_chainOut_data (_irChain_io_chainOut_data),\n .io_update_bits (_irChain_io_update_bits)\n );\n assign io_jtag_TDO_data = tdoReg;\n assign io_output_instruction = activeInstruction;\n assign io_output_tapIsInTestLogicReset = &_stateMachine_io_currState;\n assign io_dataChainOut_shift = io_dataChainOut_shift_0;\n assign io_dataChainOut_data = io_jtag_TDI;\n assign io_dataChainOut_capture = _stateMachine_io_currState == 4'h6;\n assign io_dataChainOut_update = _stateMachine_io_currState == 4'h5;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename BusyTable\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass BusyResp extends Bundle\n{\n val prs1_busy = Bool()\n val prs2_busy = Bool()\n val prs3_busy = Bool()\n}\n\nclass RenameBusyTable(\n val plWidth: Int,\n val numPregs: Int,\n val numWbPorts: Int,\n val bypass: Boolean,\n val float: Boolean)\n (implicit p: Parameters) extends BoomModule\n{\n val pregSz = log2Ceil(numPregs)\n\n val io = IO(new BoomBundle()(p) {\n val ren_uops = Input(Vec(plWidth, new MicroOp))\n val busy_resps = Output(Vec(plWidth, new BusyResp))\n val rebusy_reqs = Input(Vec(plWidth, Bool()))\n\n val wb_pdsts = Input(Vec(numWbPorts, UInt(pregSz.W)))\n val wb_valids = Input(Vec(numWbPorts, Bool()))\n\n val debug = new Bundle { val busytable = Output(Bits(numPregs.W)) }\n })\n\n val busy_table = RegInit(0.U(numPregs.W))\n // Unbusy written back registers.\n val busy_table_wb = busy_table & ~(io.wb_pdsts zip io.wb_valids)\n .map {case (pdst, valid) => UIntToOH(pdst) & Fill(numPregs, valid.asUInt)}.reduce(_|_)\n // Rebusy newly allocated registers.\n val busy_table_next = busy_table_wb | (io.ren_uops zip io.rebusy_reqs)\n .map {case (uop, req) => UIntToOH(uop.pdst) & Fill(numPregs, req.asUInt)}.reduce(_|_)\n\n busy_table := busy_table_next\n\n // Read the busy table.\n for (i <- 0 until plWidth) {\n val prs1_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs1 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n val prs2_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs2 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n val prs3_was_bypassed = (0 until i).map(j =>\n io.ren_uops(i).lrs3 === io.ren_uops(j).ldst && io.rebusy_reqs(j)).foldLeft(false.B)(_||_)\n\n io.busy_resps(i).prs1_busy := busy_table(io.ren_uops(i).prs1) || prs1_was_bypassed && bypass.B\n io.busy_resps(i).prs2_busy := busy_table(io.ren_uops(i).prs2) || prs2_was_bypassed && bypass.B\n io.busy_resps(i).prs3_busy := busy_table(io.ren_uops(i).prs3) || prs3_was_bypassed && bypass.B\n if (!float) io.busy_resps(i).prs3_busy := false.B\n }\n\n io.debug.busytable := busy_table\n}", + "response": "module RenameBusyTable(\n input clock,\n input reset,\n input [5:0] io_ren_uops_0_pdst,\n input [5:0] io_ren_uops_0_prs1,\n input [5:0] io_ren_uops_0_prs2,\n output io_busy_resps_0_prs1_busy,\n output io_busy_resps_0_prs2_busy,\n input io_rebusy_reqs_0,\n input [5:0] io_wb_pdsts_0,\n input [5:0] io_wb_pdsts_1,\n input [5:0] io_wb_pdsts_2,\n input io_wb_valids_0,\n input io_wb_valids_1,\n input io_wb_valids_2\n);\n\n reg [51:0] busy_table;\n wire [51:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1;\n wire [51:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2;\n wire [63:0] _busy_table_next_T = 64'h1 << io_ren_uops_0_pdst;\n wire [63:0] _busy_table_wb_T_6 = 64'h1 << io_wb_pdsts_2;\n wire [63:0] _busy_table_wb_T_3 = 64'h1 << io_wb_pdsts_1;\n wire [63:0] _busy_table_wb_T = 64'h1 << io_wb_pdsts_0;\n always @(posedge clock) begin\n if (reset)\n busy_table <= 52'h0;\n else\n busy_table <= ~(_busy_table_wb_T[51:0] & {52{io_wb_valids_0}} | _busy_table_wb_T_3[51:0] & {52{io_wb_valids_1}} | _busy_table_wb_T_6[51:0] & {52{io_wb_valids_2}}) & busy_table | _busy_table_next_T[51:0] & {52{io_rebusy_reqs_0}};\n end\n assign io_busy_resps_0_prs1_busy = _io_busy_resps_0_prs1_busy_T[0];\n assign io_busy_resps_0_prs2_busy = _io_busy_resps_0_prs2_busy_T[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Re-order Buffer\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Bank the ROB, such that each \"dispatch\" group gets its own row of the ROB,\n// and each instruction in the dispatch group goes to a different bank.\n// We can compress out the PC by only saving the high-order bits!\n//\n// ASSUMPTIONS:\n// - dispatch groups are aligned to the PC.\n//\n// NOTES:\n// - Currently we do not compress out bubbles in the ROB.\n// - Exceptions are only taken when at the head of the commit bundle --\n// this helps deal with loads, stores, and refetch instructions.\n\npackage boom.v3.exu\n\nimport scala.math.ceil\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\n\nimport boom.v3.common._\nimport boom.v3.util._\n\n/**\n * IO bundle to interact with the ROB\n *\n * @param numWakeupPorts number of wakeup ports to the rob\n * @param numFpuPorts number of fpu ports that will write back fflags\n */\nclass RobIo(\n val numWakeupPorts: Int,\n val numFpuPorts: Int\n )(implicit p: Parameters) extends BoomBundle\n{\n // Decode Stage\n // (Allocate, write instruction to ROB).\n val enq_valids = Input(Vec(coreWidth, Bool()))\n val enq_uops = Input(Vec(coreWidth, new MicroOp()))\n val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,\n // and stalling on the rest of it (don't\n // advance the tail ptr)\n\n val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))\n\n val rob_tail_idx = Output(UInt(robAddrSz.W))\n val rob_pnr_idx = Output(UInt(robAddrSz.W))\n val rob_head_idx = Output(UInt(robAddrSz.W))\n\n // Handle Branch Misspeculations\n val brupdate = Input(new BrUpdateInfo())\n\n // Write-back Stage\n // (Update of ROB)\n // Instruction is no longer busy and can be committed\n val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))\n\n // Unbusying ports for stores.\n // +1 for fpstdata\n val lsu_clr_bsy = Input(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))\n\n // Port for unmarking loads/stores as speculation hazards..\n val lsu_clr_unsafe = Input(Vec(memWidth, Valid(UInt(robAddrSz.W))))\n\n\n // Track side-effects for debug purposes.\n // Also need to know when loads write back, whereas we don't need loads to unbusy.\n val debug_wb_valids = Input(Vec(numWakeupPorts, Bool()))\n val debug_wb_wdata = Input(Vec(numWakeupPorts, Bits(xLen.W)))\n\n val fflags = Flipped(Vec(numFpuPorts, new ValidIO(new FFlagsResp())))\n val lxcpt = Input(Valid(new Exception())) // LSU\n val csr_replay = Input(Valid(new Exception()))\n\n // Commit stage (free resources; also used for rollback).\n val commit = Output(new CommitSignals())\n\n // tell the LSU that the head of the ROB is a load\n // (some loads can only execute once they are at the head of the ROB).\n val com_load_is_at_rob_head = Output(Bool())\n\n // Communicate exceptions to the CSRFile\n val com_xcpt = Valid(new CommitExceptionSignals())\n\n // Let the CSRFile stall us (e.g., wfi).\n val csr_stall = Input(Bool())\n\n // Flush signals (including exceptions, pipeline replays, and memory ordering failures)\n // to send to the frontend for redirection.\n val flush = Valid(new CommitExceptionSignals)\n\n // Stall Decode as appropriate\n val empty = Output(Bool())\n val ready = Output(Bool()) // ROB is busy unrolling rename state...\n\n // Stall the frontend if we know we will redirect the PC\n val flush_frontend = Output(Bool())\n\n\n val debug_tsc = Input(UInt(xLen.W))\n}\n\n/**\n * Bundle to send commit signals across processor\n */\nclass CommitSignals(implicit p: Parameters) extends BoomBundle\n{\n val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn\n val arch_valids = Vec(retireWidth, Bool())\n val uops = Vec(retireWidth, new MicroOp())\n val fflags = Valid(UInt(5.W))\n\n // These come a cycle later\n val debug_insts = Vec(retireWidth, UInt(32.W))\n\n // Perform rollback of rename state (in conjuction with commit.uops).\n val rbk_valids = Vec(retireWidth, Bool())\n val rollback = Bool()\n\n val debug_wdata = Vec(retireWidth, UInt(xLen.W))\n}\n\n/**\n * Bundle to communicate exceptions to CSRFile\n *\n * TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).\n */\nclass CommitExceptionSignals(implicit p: Parameters) extends BoomBundle\n{\n val ftq_idx = UInt(log2Ceil(ftqSz).W)\n val edge_inst = Bool()\n val is_rvc = Bool()\n val pc_lob = UInt(log2Ceil(icBlockBytes).W)\n val cause = UInt(xLen.W)\n val badvaddr = UInt(xLen.W)\n// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)\n// so the FTQ can drive the frontend with the correct redirected PC.\n val flush_typ = FlushTypes()\n}\n\n/**\n * Tell the frontend the type of flush so it can set up the next PC properly.\n */\nobject FlushTypes\n{\n def SZ = 3\n def apply() = UInt(SZ.W)\n def none = 0.U\n def xcpt = 1.U // An exception occurred.\n def eret = (2+1).U // Execute an environment return instruction.\n def refetch = 2.U // Flush and refetch the head instruction.\n def next = 4.U // Flush and fetch the next instruction.\n\n def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U\n def useSamePC(typ: UInt): Bool = typ === refetch\n def usePCplus4(typ: UInt): Bool = typ === next\n\n def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {\n val ret =\n Mux(!valid, none,\n Mux(i_eret, eret,\n Mux(i_xcpt, xcpt,\n Mux(i_refetch, refetch,\n next))))\n ret\n }\n}\n\n/**\n * Bundle of signals indicating that an exception occurred\n */\nclass Exception(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)\n val badvaddr = UInt(coreMaxAddrBits.W)\n}\n\n/**\n * Bundle for debug ROB signals\n * These should not be synthesized!\n */\nclass DebugRobSignals(implicit p: Parameters) extends BoomBundle\n{\n val state = UInt()\n val rob_head = UInt(robAddrSz.W)\n val rob_pnr = UInt(robAddrSz.W)\n val xcpt_val = Bool()\n val xcpt_uop = new MicroOp()\n val xcpt_badvaddr = UInt(xLen.W)\n}\n\n/**\n * Reorder Buffer to keep track of dependencies and inflight instructions\n *\n * @param numWakeupPorts number of wakeup ports to the ROB\n * @param numFpuPorts number of FPU units that will write back fflags\n */\nclass Rob(\n val numWakeupPorts: Int,\n val numFpuPorts: Int\n )(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new RobIo(numWakeupPorts, numFpuPorts))\n\n // ROB Finite State Machine\n val s_reset :: s_normal :: s_rollback :: s_wait_till_empty :: Nil = Enum(4)\n val rob_state = RegInit(s_reset)\n\n //commit entries at the head, and unwind exceptions from the tail\n val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)\n val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)\n\n val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))\n val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)\n\n val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))\n val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))\n val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)\n\n val com_idx = Mux(rob_state === s_rollback, rob_tail, rob_head)\n\n\n val maybe_full = RegInit(false.B)\n val full = Wire(Bool())\n val empty = Wire(Bool())\n\n val will_commit = Wire(Vec(coreWidth, Bool()))\n val can_commit = Wire(Vec(coreWidth, Bool()))\n val can_throw_exception = Wire(Vec(coreWidth, Bool()))\n\n val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?\n val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?\n val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)\n val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))\n val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))\n val rob_head_fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))\n\n val exception_thrown = Wire(Bool())\n\n // exception info\n // TODO compress xcpt cause size. Most bits in the middle are zero.\n val r_xcpt_val = RegInit(false.B)\n val r_xcpt_uop = Reg(new MicroOp())\n val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))\n io.flush_frontend := r_xcpt_val\n\n //--------------------------------------------------\n // Utility\n\n def GetRowIdx(rob_idx: UInt): UInt = {\n if (coreWidth == 1) return rob_idx\n else return rob_idx >> log2Ceil(coreWidth).U\n }\n def GetBankIdx(rob_idx: UInt): UInt = {\n if(coreWidth == 1) { return 0.U }\n else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }\n }\n\n // **************************************************************************\n // Debug\n\n class DebugRobBundle extends BoomBundle\n {\n val valid = Bool()\n val busy = Bool()\n val unsafe = Bool()\n val uop = new MicroOp()\n val exception = Bool()\n }\n val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))\n debug_entry := DontCare // override in statements below\n\n // **************************************************************************\n // --------------------------------------------------------------------------\n // **************************************************************************\n\n // Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.\n val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))\n\n // Used for trace port, for debug purposes only\n val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))\n val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))\n val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))\n rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)\n val rob_debug_inst_rdata = rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))\n\n val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))\n\n for (w <- 0 until coreWidth) {\n def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)\n\n // one bank\n val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))\n val rob_bsy = Reg(Vec(numRobRows, Bool()))\n val rob_unsafe = Reg(Vec(numRobRows, Bool()))\n val rob_uop = Reg(Vec(numRobRows, new MicroOp()))\n val rob_exception = Reg(Vec(numRobRows, Bool()))\n val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?\n\n val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))\n\n //-----------------------------------------------\n // Dispatch: Add Entry to ROB\n\n rob_debug_inst_wmask(w) := io.enq_valids(w)\n rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst\n\n when (io.enq_valids(w)) {\n rob_val(rob_tail) := true.B\n rob_bsy(rob_tail) := !(io.enq_uops(w).is_fence ||\n io.enq_uops(w).is_fencei)\n rob_unsafe(rob_tail) := io.enq_uops(w).unsafe\n rob_uop(rob_tail) := io.enq_uops(w)\n rob_exception(rob_tail) := io.enq_uops(w).exception\n rob_predicated(rob_tail) := false.B\n rob_fflags(w)(rob_tail) := 0.U\n\n assert (rob_val(rob_tail) === false.B, \"[rob] overwriting a valid entry.\")\n assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)\n } .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {\n rob_uop(rob_tail).debug_inst := BUBBLE // just for debug purposes\n }\n\n //-----------------------------------------------\n // Writeback\n\n for (i <- 0 until numWakeupPorts) {\n val wb_resp = io.wb_resps(i)\n val wb_uop = wb_resp.bits.uop\n val row_idx = GetRowIdx(wb_uop.rob_idx)\n when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {\n rob_bsy(row_idx) := false.B\n rob_unsafe(row_idx) := false.B\n rob_predicated(row_idx) := wb_resp.bits.predicated\n }\n // TODO check that fflags aren't overwritten\n // TODO check that the wb is to a valid ROB entry, give it a time stamp\n// assert (!(wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx)) &&\n// wb_uop.fp_val && !(wb_uop.is_load || wb_uop.is_store) &&\n// rob_exc_cause(row_idx) =/= 0.U),\n// \"FP instruction writing back exc bits is overriding an existing exception.\")\n }\n\n // Stores have a separate method to clear busy bits\n for (clr_rob_idx <- io.lsu_clr_bsy) {\n when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {\n val cidx = GetRowIdx(clr_rob_idx.bits)\n rob_bsy(cidx) := false.B\n rob_unsafe(cidx) := false.B\n assert (rob_val(cidx) === true.B, \"[rob] store writing back to invalid entry.\")\n assert (rob_bsy(cidx) === true.B, \"[rob] store writing back to a not-busy entry.\")\n }\n }\n for (clr <- io.lsu_clr_unsafe) {\n when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {\n val cidx = GetRowIdx(clr.bits)\n rob_unsafe(cidx) := false.B\n }\n }\n\n\n //-----------------------------------------------\n // Accruing fflags\n for (i <- 0 until numFpuPorts) {\n val fflag_uop = io.fflags(i).bits.uop\n when (io.fflags(i).valid && MatchBank(GetBankIdx(fflag_uop.rob_idx))) {\n rob_fflags(w)(GetRowIdx(fflag_uop.rob_idx)) := io.fflags(i).bits.flags\n }\n }\n\n //-----------------------------------------------------\n // Exceptions\n // (the cause bits are compressed and stored elsewhere)\n\n when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {\n rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B\n when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {\n // In the case of a mem-ordering failure, the failing load will have been marked safe already.\n assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),\n \"An instruction marked as safe is causing an exception\")\n }\n }\n\n when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {\n rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B\n }\n can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)\n\n //-----------------------------------------------\n // Commit or Rollback\n\n // Can this instruction commit? (the check for exceptions/rob_state happens later).\n can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall\n\n\n // use the same \"com_uop\" for both rollback AND commit\n // Perform Commit\n io.commit.valids(w) := will_commit(w)\n io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(com_idx)\n io.commit.uops(w) := rob_uop(com_idx)\n io.commit.debug_insts(w) := rob_debug_inst_rdata(w)\n\n // We unbusy branches in b1, but its easier to mark the taken/provider src in b2,\n // when the branch might be committing\n when (io.brupdate.b2.mispredict &&\n MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&\n GetRowIdx(io.brupdate.b2.uop.rob_idx) === com_idx) {\n io.commit.uops(w).debug_fsrc := BSRC_C\n io.commit.uops(w).taken := io.brupdate.b2.taken\n }\n\n\n // Don't attempt to rollback the tail's row when the rob is full.\n val rbk_row = rob_state === s_rollback && !full\n\n io.commit.rbk_valids(w) := rbk_row && rob_val(com_idx) && !(enableCommitMapTable.B)\n io.commit.rollback := (rob_state === s_rollback)\n\n assert (!(io.commit.valids.reduce(_||_) && io.commit.rbk_valids.reduce(_||_)),\n \"com_valids and rbk_valids are mutually exclusive\")\n\n when (rbk_row) {\n rob_val(com_idx) := false.B\n rob_exception(com_idx) := false.B\n }\n\n if (enableCommitMapTable) {\n when (RegNext(exception_thrown)) {\n for (i <- 0 until numRobRows) {\n rob_val(i) := false.B\n rob_bsy(i) := false.B\n rob_uop(i).debug_inst := BUBBLE\n }\n }\n }\n\n // -----------------------------------------------\n // Kill speculated entries on branch mispredict\n for (i <- 0 until numRobRows) {\n val br_mask = rob_uop(i).br_mask\n\n //kill instruction if mispredict & br mask match\n when (IsKilledByBranch(io.brupdate, br_mask))\n {\n rob_val(i) := false.B\n rob_uop(i.U).debug_inst := BUBBLE\n } .elsewhen (rob_val(i)) {\n // clear speculation bit even on correct speculation\n rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)\n }\n }\n\n\n // Debug signal to figure out which prediction structure\n // or core resolved a branch correctly\n when (io.brupdate.b2.mispredict &&\n MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {\n rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C\n rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken\n }\n\n // -----------------------------------------------\n // Commit\n when (will_commit(w)) {\n rob_val(rob_head) := false.B\n }\n\n // -----------------------------------------------\n // Outputs\n rob_head_vals(w) := rob_val(rob_head)\n rob_tail_vals(w) := rob_val(rob_tail)\n rob_head_fflags(w) := rob_fflags(w)(rob_head)\n rob_head_uses_stq(w) := rob_uop(rob_head).uses_stq\n rob_head_uses_ldq(w) := rob_uop(rob_head).uses_ldq\n\n //------------------------------------------------\n // Invalid entries are safe; thrown exceptions are unsafe.\n for (i <- 0 until numRobRows) {\n rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))\n }\n // Read unsafe status of PNR row.\n rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))\n\n // -----------------------------------------------\n // debugging write ports that should not be synthesized\n when (will_commit(w)) {\n rob_uop(rob_head).debug_inst := BUBBLE\n } .elsewhen (rbk_row)\n {\n rob_uop(rob_tail).debug_inst := BUBBLE\n }\n\n //--------------------------------------------------\n // Debug: for debug purposes, track side-effects to all register destinations\n\n for (i <- 0 until numWakeupPorts) {\n val rob_idx = io.wb_resps(i).bits.uop.rob_idx\n when (io.debug_wb_valids(i) && MatchBank(GetBankIdx(rob_idx))) {\n rob_debug_wdata(GetRowIdx(rob_idx)) := io.debug_wb_wdata(i)\n }\n val temp_uop = rob_uop(GetRowIdx(rob_idx))\n\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n !rob_val(GetRowIdx(rob_idx))),\n \"[rob] writeback (\" + i + \") occurred to an invalid ROB entry.\")\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n !rob_bsy(GetRowIdx(rob_idx))),\n \"[rob] writeback (\" + i + \") occurred to a not-busy ROB entry.\")\n assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n temp_uop.ldst_val && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),\n \"[rob] writeback (\" + i + \") occurred to the wrong pdst.\")\n }\n io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)\n\n } //for (w <- 0 until coreWidth)\n\n // **************************************************************************\n // --------------------------------------------------------------------------\n // **************************************************************************\n\n // -----------------------------------------------\n // Commit Logic\n // need to take a \"can_commit\" array, and let the first can_commits commit\n // previous instructions may block the commit of younger instructions in the commit bundle\n // e.g., exception, or (valid && busy).\n // Finally, don't throw an exception if there are instructions in front of\n // it that want to commit (only throw exception when head of the bundle).\n\n var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))\n var will_throw_exception = false.B\n var block_xcpt = false.B\n\n for (w <- 0 until coreWidth) {\n will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception\n\n will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit\n block_commit = (rob_head_vals(w) &&\n (!can_commit(w) || can_throw_exception(w))) || block_commit\n block_xcpt = will_commit(w)\n }\n\n // Note: exception must be in the commit bundle.\n // Note: exception must be the first valid instruction in the commit bundle.\n exception_thrown := will_throw_exception\n val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)\n io.com_xcpt.valid := exception_thrown && !is_mini_exception\n io.com_xcpt.bits := DontCare\n io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause\n\n io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)\n val insn_sys_pc2epc =\n rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})\n\n val refetch_inst = exception_thrown || insn_sys_pc2epc\n val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)\n io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx\n io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst\n io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc\n io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob\n\n val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}\n val flush_commit = flush_commit_mask.reduce(_|_)\n val flush_val = exception_thrown || flush_commit\n\n assert(!(PopCount(flush_commit_mask) > 1.U),\n \"[rob] Can't commit multiple flush_on_commit instructions on one cycle\")\n\n val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))\n\n // delay a cycle for critical path considerations\n io.flush.valid := flush_val\n io.flush.bits := DontCare\n io.flush.bits.ftq_idx := flush_uop.ftq_idx\n io.flush.bits.pc_lob := flush_uop.pc_lob\n io.flush.bits.edge_inst := flush_uop.edge_inst\n io.flush.bits.is_rvc := flush_uop.is_rvc\n io.flush.bits.flush_typ := FlushTypes.getType(flush_val,\n exception_thrown && !is_mini_exception,\n flush_commit && flush_uop.uopc === uopERET,\n refetch_inst)\n\n\n // -----------------------------------------------\n // FP Exceptions\n // send fflags bits to the CSRFile to accrue\n\n val fflags_val = Wire(Vec(coreWidth, Bool()))\n val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))\n\n for (w <- 0 until coreWidth) {\n fflags_val(w) :=\n io.commit.valids(w) &&\n io.commit.uops(w).fp_val &&\n !io.commit.uops(w).uses_stq\n\n fflags(w) := Mux(fflags_val(w), rob_head_fflags(w), 0.U)\n\n assert (!(io.commit.valids(w) &&\n !io.commit.uops(w).fp_val &&\n rob_head_fflags(w) =/= 0.U),\n \"Committed non-FP instruction has non-zero fflag bits.\")\n assert (!(io.commit.valids(w) &&\n io.commit.uops(w).fp_val &&\n (io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&\n rob_head_fflags(w) =/= 0.U),\n \"Committed FP load or store has non-zero fflag bits.\")\n }\n io.commit.fflags.valid := fflags_val.reduce(_|_)\n io.commit.fflags.bits := fflags.reduce(_|_)\n\n // -----------------------------------------------\n // Exception Tracking Logic\n // only store the oldest exception, since only one can happen!\n\n val next_xcpt_uop = Wire(new MicroOp())\n next_xcpt_uop := r_xcpt_uop\n val enq_xcpts = Wire(Vec(coreWidth, Bool()))\n for (i <- 0 until coreWidth) {\n enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception\n }\n\n when (!(io.flush.valid || exception_thrown) && rob_state =/= s_rollback) {\n\n val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid\n val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)\n val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)\n\n when (new_xcpt_valid) {\n when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {\n r_xcpt_val := true.B\n next_xcpt_uop := new_xcpt.uop\n next_xcpt_uop.exc_cause := new_xcpt.cause\n r_xcpt_badvaddr := new_xcpt.badvaddr\n }\n } .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {\n val idx = enq_xcpts.indexWhere{i: Bool => i}\n\n // if no exception yet, dispatch exception wins\n r_xcpt_val := true.B\n next_xcpt_uop := io.enq_uops(idx)\n r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob\n\n }\n }\n\n r_xcpt_uop := next_xcpt_uop\n r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)\n when (io.flush.valid || IsKilledByBranch(io.brupdate, next_xcpt_uop)) {\n r_xcpt_val := false.B\n }\n\n assert (!(exception_thrown && !r_xcpt_val),\n \"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause\")\n\n assert (!(empty && r_xcpt_val),\n \"ROB is empty, but believes it has an outstanding exception.\")\n\n assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),\n \"ROB is throwing an exception, but the stored exception information's \" +\n \"rob_idx does not match the rob_head\")\n\n // -----------------------------------------------\n // ROB Head Logic\n\n // remember if we're still waiting on the rest of the dispatch packet, and prevent\n // the rob_head from advancing if it commits a partial parket before we\n // dispatch the rest of it.\n // update when committed ALL valid instructions in commit_bundle\n\n val rob_deq = WireInit(false.B)\n val r_partial_row = RegInit(false.B)\n\n when (io.enq_valids.reduce(_|_)) {\n r_partial_row := io.enq_partial_stall\n }\n\n val finished_committing_row =\n (io.commit.valids.asUInt =/= 0.U) &&\n ((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&\n !(r_partial_row && rob_head === rob_tail && !maybe_full)\n\n when (finished_committing_row) {\n rob_head := WrapInc(rob_head, numRobRows)\n rob_head_lsb := 0.U\n rob_deq := true.B\n } .otherwise {\n rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))\n }\n\n // -----------------------------------------------\n // ROB Point-of-No-Return (PNR) Logic\n // Acts as a second head, but only waits on busy instructions which might cause misspeculation.\n // TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?\n // Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.\n // Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.\n\n if (enableFastPNR) {\n val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)\n val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,\n AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),\n rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))\n rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)\n if (coreWidth > 1)\n rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)\n } else {\n // Distinguish between PNR being at head/tail when ROB is full.\n // Works the same as maybe_full tracking for the ROB tail.\n val pnr_maybe_at_tail = RegInit(false.B)\n\n val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty\n val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))\n when (empty && io.enq_valids.asUInt =/= 0.U) {\n // Unforunately for us, the ROB does not use its entries in monotonically\n // increasing order, even in the case of no exceptions. The edge case\n // arises when partial rows are enqueued and committed, leaving an empty\n // ROB.\n rob_pnr := rob_head\n rob_pnr_lsb := PriorityEncoder(io.enq_valids)\n } .elsewhen (safe_to_inc && do_inc_row) {\n rob_pnr := WrapInc(rob_pnr, numRobRows)\n rob_pnr_lsb := 0.U\n } .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail || (full && !pnr_maybe_at_tail))) {\n rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)\n } .elsewhen (safe_to_inc && !full && !empty) {\n rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))\n } .elsewhen (full && pnr_maybe_at_tail) {\n rob_pnr_lsb := 0.U\n }\n\n pnr_maybe_at_tail := !rob_deq && (do_inc_row || pnr_maybe_at_tail)\n }\n\n // Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.\n assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)\n\n // PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.\n assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)\n\n // -----------------------------------------------\n // ROB Tail Logic\n\n val rob_enq = WireInit(false.B)\n\n when (rob_state === s_rollback && (rob_tail =/= rob_head || maybe_full)) {\n // Rollback a row\n rob_tail := WrapDec(rob_tail, numRobRows)\n rob_tail_lsb := (coreWidth-1).U\n rob_deq := true.B\n } .elsewhen (rob_state === s_rollback && (rob_tail === rob_head) && !maybe_full) {\n // Rollback an entry\n rob_tail_lsb := rob_head_lsb\n } .elsewhen (io.brupdate.b2.mispredict) {\n rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)\n rob_tail_lsb := 0.U\n } .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {\n rob_tail := WrapInc(rob_tail, numRobRows)\n rob_tail_lsb := 0.U\n rob_enq := true.B\n } .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {\n rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))\n }\n\n\n if (enableCommitMapTable) {\n when (RegNext(exception_thrown)) {\n rob_tail := 0.U\n rob_tail_lsb := 0.U\n rob_head := 0.U\n rob_pnr := 0.U\n rob_pnr_lsb := 0.U\n }\n }\n\n // -----------------------------------------------\n // Full/Empty Logic\n // The ROB can be completely full, but only if it did not dispatch a row in the prior cycle.\n // I.E. at least one entry will be empty when in a steady state of dispatching and committing a row each cycle.\n // TODO should we add an extra 'parity bit' onto the ROB pointers to simplify this logic?\n\n maybe_full := !rob_deq && (rob_enq || maybe_full) || io.brupdate.b1.mispredict_mask =/= 0.U\n full := rob_tail === rob_head && maybe_full\n empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)\n\n io.rob_head_idx := rob_head_idx\n io.rob_tail_idx := rob_tail_idx\n io.rob_pnr_idx := rob_pnr_idx\n io.empty := empty\n io.ready := (rob_state === s_normal) && !full && !r_xcpt_val\n\n //-----------------------------------------------\n //-----------------------------------------------\n //-----------------------------------------------\n\n // ROB FSM\n if (!enableCommitMapTable) {\n switch (rob_state) {\n is (s_reset) {\n rob_state := s_normal\n }\n is (s_normal) {\n // Delay rollback 2 cycles so branch mispredictions can drain\n when (RegNext(RegNext(exception_thrown))) {\n rob_state := s_rollback\n } .otherwise {\n for (w <- 0 until coreWidth) {\n when (io.enq_valids(w) && io.enq_uops(w).is_unique) {\n rob_state := s_wait_till_empty\n }\n }\n }\n }\n is (s_rollback) {\n when (empty) {\n rob_state := s_normal\n }\n }\n is (s_wait_till_empty) {\n when (RegNext(exception_thrown)) {\n rob_state := s_rollback\n } .elsewhen (empty) {\n rob_state := s_normal\n }\n }\n }\n } else {\n switch (rob_state) {\n is (s_reset) {\n rob_state := s_normal\n }\n is (s_normal) {\n when (exception_thrown) {\n ; //rob_state := s_rollback\n } .otherwise {\n for (w <- 0 until coreWidth) {\n when (io.enq_valids(w) && io.enq_uops(w).is_unique) {\n rob_state := s_wait_till_empty\n }\n }\n }\n }\n is (s_rollback) {\n when (rob_tail_idx === rob_head_idx) {\n rob_state := s_normal\n }\n }\n is (s_wait_till_empty) {\n when (exception_thrown) {\n ; //rob_state := s_rollback\n } .elsewhen (rob_tail === rob_head) {\n rob_state := s_normal\n }\n }\n }\n }\n\n // -----------------------------------------------\n // Outputs\n\n io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&\n !will_commit.reduce(_||_))\n\n\n\n override def toString: String = BoomCoreStringPrefix(\n \"==ROB==\",\n \"Machine Width : \" + coreWidth,\n \"Rob Entries : \" + numRobEntries,\n \"Rob Rows : \" + numRobRows,\n \"Rob Row size : \" + log2Ceil(numRobRows),\n \"log2Ceil(coreWidth): \" + log2Ceil(coreWidth),\n \"FPU FFlag Ports : \" + numFpuPorts)\n}", + "response": "module rob_debug_inst_mem_0(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [31:0] W0_data\n);\n\n rob_debug_inst_mem_0_ext rob_debug_inst_mem_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (/* unused */),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module head_40x6(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data,\n input [5:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [5:0] W1_data\n);\n\n reg [5:0] Memory[0:39];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPUFMAPipe_l4_f64(\n input clock,\n input reset,\n input io_in_valid,\n input io_in_bits_ren3,\n input io_in_bits_swap23,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_fmaCmd,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n input [64:0] io_in_bits_in3,\n output io_out_valid,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc\n);\n\n wire [64:0] _fma_io_out;\n wire [4:0] _fma_io_exceptionFlags;\n wire _fma_io_validout;\n reg valid;\n reg [2:0] in_rm;\n reg [1:0] in_fmaCmd;\n reg [64:0] in_in1;\n reg [64:0] in_in2;\n reg [64:0] in_in3;\n reg io_out_pipe_v;\n reg [64:0] io_out_pipe_b_data;\n reg [4:0] io_out_pipe_b_exc;\n always @(posedge clock) begin\n valid <= io_in_valid;\n if (io_in_valid) begin\n in_rm <= io_in_bits_rm;\n in_fmaCmd <= io_in_bits_fmaCmd;\n in_in1 <= io_in_bits_in1;\n in_in2 <= io_in_bits_swap23 ? 65'h8000000000000000 : io_in_bits_in2;\n in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : (io_in_bits_in1 ^ io_in_bits_in2) & 65'h10000000000000000;\n end\n if (_fma_io_validout) begin\n io_out_pipe_b_data <= ({65{_fma_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _fma_io_out;\n io_out_pipe_b_exc <= _fma_io_exceptionFlags;\n end\n if (reset)\n io_out_pipe_v <= 1'h0;\n else\n io_out_pipe_v <= _fma_io_validout;\n end\n MulAddRecFNPipe_l2_e11_s53 fma (\n .clock (clock),\n .reset (reset),\n .io_validin (valid),\n .io_op (in_fmaCmd),\n .io_a (in_in1),\n .io_b (in_in2),\n .io_c (in_in3),\n .io_roundingMode (in_rm),\n .io_out (_fma_io_out),\n .io_exceptionFlags (_fma_io_exceptionFlags),\n .io_validout (_fma_io_validout)\n );\n assign io_out_valid = io_out_pipe_v;\n assign io_out_bits_data = io_out_pipe_b_data;\n assign io_out_bits_exc = io_out_pipe_b_exc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_preMul_e11_s53(\n input [1:0] io_op,\n input [64:0] io_a,\n input [64:0] io_b,\n input [64:0] io_c,\n output [52:0] io_mulAddA,\n output [52:0] io_mulAddB,\n output [105:0] io_mulAddC,\n output io_toPostMul_isSigNaNAny,\n output io_toPostMul_isNaNAOrB,\n output io_toPostMul_isInfA,\n output io_toPostMul_isZeroA,\n output io_toPostMul_isInfB,\n output io_toPostMul_isZeroB,\n output io_toPostMul_signProd,\n output io_toPostMul_isNaNC,\n output io_toPostMul_isInfC,\n output io_toPostMul_isZeroC,\n output [12:0] io_toPostMul_sExpSum,\n output io_toPostMul_doSubMags,\n output io_toPostMul_CIsDominant,\n output [5:0] io_toPostMul_CDom_CAlignDist,\n output [54:0] io_toPostMul_highAlignedSigC,\n output io_toPostMul_bit0AlignedSigC\n);\n\n wire rawA_isNaN = (&(io_a[63:62])) & io_a[61];\n wire rawB_isNaN = (&(io_b[63:62])) & io_b[61];\n wire rawC_isNaN = (&(io_c[63:62])) & io_c[61];\n wire signProd = io_a[64] ^ io_b[64] ^ io_op[1];\n wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8;\n wire doSubMags = signProd ^ io_c[64] ^ io_op[0];\n wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]};\n wire isMinCAlign = ~(|(io_a[63:61])) | ~(|(io_b[63:61])) | $signed(_sNatCAlignDist_T) < 14'sh0;\n wire CIsDominant = (|(io_c[63:61])) & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36);\n wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1;\n wire [164:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[63:61])), ~(io_c[51:0])} : {1'h0, |(io_c[63:61]), io_c[51:0]}, {111{doSubMags}}}) >>> CAlignDist);\n wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> CAlignDist[7:2]);\n wire [12:0] _GEN = {|(io_c[51:48]), |(io_c[47:44]), |(io_c[43:40]), |(io_c[39:36]), |(io_c[35:32]), |(io_c[31:28]), |(io_c[27:24]), |(io_c[23:20]), |(io_c[19:16]), |(io_c[15:12]), |(io_c[11:8]), |(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[24], reduced4CExtra_shift[25], reduced4CExtra_shift[26], reduced4CExtra_shift[27], reduced4CExtra_shift[28], reduced4CExtra_shift[29], reduced4CExtra_shift[30], reduced4CExtra_shift[31], reduced4CExtra_shift[32], reduced4CExtra_shift[33], reduced4CExtra_shift[34], reduced4CExtra_shift[35], reduced4CExtra_shift[36]};\n assign io_mulAddA = {|(io_a[63:61]), io_a[51:0]};\n assign io_mulAddB = {|(io_b[63:61]), io_b[51:0]};\n assign io_mulAddC = mainAlignedSigC[108:3];\n assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]);\n assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;\n assign io_toPostMul_isInfA = (&(io_a[63:62])) & ~(io_a[61]);\n assign io_toPostMul_isZeroA = ~(|(io_a[63:61]));\n assign io_toPostMul_isInfB = (&(io_b[63:62])) & ~(io_b[61]);\n assign io_toPostMul_isZeroB = ~(|(io_b[63:61]));\n assign io_toPostMul_signProd = signProd;\n assign io_toPostMul_isNaNC = rawC_isNaN;\n assign io_toPostMul_isInfC = (&(io_c[63:62])) & ~(io_c[61]);\n assign io_toPostMul_isZeroC = ~(|(io_c[63:61]));\n assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35;\n assign io_toPostMul_doSubMags = doSubMags;\n assign io_toPostMul_CIsDominant = CIsDominant;\n assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0];\n assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109];\n assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 13'h0 : (|{mainAlignedSigC[2:0], _GEN});\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitArbiter_p32_f32_n5_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n output io_in_0_ready,\n input io_in_0_valid,\n input [31:0] io_in_0_bits_phit,\n output io_in_1_ready,\n input io_in_1_valid,\n input [31:0] io_in_1_bits_phit,\n output io_in_2_ready,\n input io_in_2_valid,\n input [31:0] io_in_2_bits_phit,\n output io_in_3_ready,\n input io_in_3_valid,\n input [31:0] io_in_3_bits_phit,\n output io_in_4_ready,\n input io_in_4_valid,\n input [31:0] io_in_4_bits_phit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_phit\n);\n\n reg beat;\n reg [2:0] chosen_reg;\n wire [2:0] chosen_prio = io_in_0_valid ? 3'h0 : io_in_1_valid ? 3'h1 : io_in_2_valid ? 3'h2 : io_in_3_valid ? 3'h3 : 3'h4;\n wire [2:0] chosen = beat ? chosen_reg : chosen_prio;\n wire [7:0] _GEN = {{io_in_0_valid}, {io_in_0_valid}, {io_in_0_valid}, {io_in_4_valid}, {io_in_3_valid}, {io_in_2_valid}, {io_in_1_valid}, {io_in_0_valid}};\n wire [7:0][31:0] _GEN_0 = {{io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_4_bits_phit}, {io_in_3_bits_phit}, {io_in_2_bits_phit}, {io_in_1_bits_phit}, {io_in_0_bits_phit}};\n wire _GEN_1 = io_out_ready & _GEN[chosen];\n always @(posedge clock) begin\n if (reset)\n beat <= 1'h0;\n else if (_GEN_1)\n beat <= ~beat & beat - 1'h1;\n if (_GEN_1 & ~beat)\n chosen_reg <= chosen_prio;\n end\n assign io_in_0_ready = io_out_ready & beat & chosen_reg == 3'h0;\n assign io_in_1_ready = io_out_ready & beat & chosen_reg == 3'h1;\n assign io_in_2_ready = io_out_ready & beat & chosen_reg == 3'h2;\n assign io_in_3_ready = io_out_ready & beat & chosen_reg == 3'h3;\n assign io_in_4_ready = io_out_ready & beat & chosen_reg == 3'h4;\n assign io_out_valid = _GEN[chosen];\n assign io_out_bits_phit = beat ? _GEN_0[chosen] : {29'h0, chosen};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Out-of-Order Load/Store Unit\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ).\n//\n// Stores are sent to memory at (well, after) commit, loads are executed\n// optimstically ASAP. If a misspeculation was discovered, the pipeline is\n// cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match,\n// the Load can receive its data by forwarding data out of the Store Queue.\n//\n// Currently, loads are sent to memory immediately, and in parallel do an\n// associative search of the STQ, on entering the LSU. If a hit on the STQ\n// search, the memory request is killed on the next cycle, and if the STQ entry\n// is valid, the store data is forwarded to the load (delayed to match the\n// load-use delay to delay with the write-port structural hazard). If the store\n// data is not present, or it's only a partial match (SB->LH), the load is put\n// to sleep in the LDQ.\n//\n// Memory ordering violations are detected by stores at their addr-gen time by\n// associatively searching the LDQ for newer loads that have been issued to\n// memory.\n//\n// The store queue contains both speculated and committed stores.\n//\n// Only one port to memory... loads and stores have to fight for it, West Side\n// Story style.\n//\n// TODO:\n// - Add predicting structure for ordering failures\n// - currently won't STD forward if DMEM is busy\n// - ability to turn off things if VM is disabled\n// - reconsider port count of the wakeup, retry stuff\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util.Str\n\nimport boom.v3.common._\nimport boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp}\nimport boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask}\n\nclass LSUExeIO(implicit p: Parameters) extends BoomBundle()(p)\n{\n // The \"resp\" of the maddrcalc is really a \"req\" to the LSU\n val req = Flipped(new ValidIO(new FuncUnitResp(xLen)))\n // Send load data to regfiles\n val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen))\n val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen?\n}\n\nclass BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = UInt(coreMaxAddrBits.W)\n val data = Bits(coreDataBits.W)\n val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ\n}\n\nclass BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val data = Bits(coreDataBits.W)\n val is_hella = Bool()\n}\n\nclass LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)\n{\n // In LSU's dmem stage, send the request\n val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq)))\n // In LSU's LCAM search stage, kill if order fail (or forwarding possible)\n val s1_kill = Output(Vec(memWidth, Bool()))\n // Get a request any cycle\n val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp)))\n // In our response stage, if we get a nack, we need to reexecute\n val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq)))\n\n val brupdate = Output(new BrUpdateInfo)\n val exception = Output(Bool())\n val rob_pnr_idx = Output(UInt(robAddrSz.W))\n val rob_head_idx = Output(UInt(robAddrSz.W))\n\n val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle)))\n\n // Clears prefetching MSHRs\n val force_order = Output(Bool())\n val ordered = Input(Bool())\n\n val perf = Input(new Bundle {\n val acquire = Bool()\n val release = Bool()\n })\n\n}\n\nclass LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)\n{\n val exe = Vec(memWidth, new LSUExeIO)\n\n val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp)))\n val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W)))\n val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W)))\n\n val ldq_full = Output(Vec(coreWidth, Bool()))\n val stq_full = Output(Vec(coreWidth, Bool()))\n\n val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen)))\n\n val commit = Input(new CommitSignals)\n val commit_load_at_rob_head = Input(Bool())\n\n // Stores clear busy bit when stdata is received\n // memWidth for int, 1 for fp (to avoid back-pressure fpstdat)\n val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))\n\n // Speculatively safe load (barring memory ordering failure)\n val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W))))\n\n // Tell the DCache to clear prefetches/speculating misses\n val fence_dmem = Input(Bool())\n\n // Speculatively tell the IQs that we'll get load data back next cycle\n val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W))))\n // Tell the IQs that the load we speculated last cycle was misspeculated\n val ld_miss = Output(Bool())\n\n val brupdate = Input(new BrUpdateInfo)\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n val exception = Input(Bool())\n\n val fencei_rdy = Output(Bool())\n\n val lxcpt = Output(Valid(new Exception))\n\n val tsc_reg = Input(UInt())\n\n val perf = Output(new Bundle {\n val acquire = Bool()\n val release = Bool()\n val tlbMiss = Bool()\n })\n}\n\nclass LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)\n{\n val ptw = new rocket.TLBPTWIO\n val core = new LSUCoreIO\n val dmem = new LSUDMemIO\n\n val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO)\n}\n\nclass LDQEntry(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = Valid(UInt(coreMaxAddrBits.W))\n val addr_is_virtual = Bool() // Virtual address, we got a TLB miss\n val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute\n\n val executed = Bool() // load sent to memory, reset by NACKs\n val succeeded = Bool()\n val order_fail = Bool()\n val observed = Bool()\n\n val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us\n val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us\n\n val forward_std_val = Bool()\n val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from?\n\n val debug_wb_data = UInt(xLen.W)\n}\n\nclass STQEntry(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = Valid(UInt(coreMaxAddrBits.W))\n val addr_is_virtual = Bool() // Virtual address, we got a TLB miss\n val data = Valid(UInt(xLen.W))\n\n val committed = Bool() // committed by ROB\n val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore\n\n val debug_wb_data = UInt(xLen.W)\n}\n\nclass LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)\n with rocket.HasL1HellaCacheParameters\n{\n val io = IO(new LSUIO)\n io.hellacache := DontCare\n\n\n val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry)))\n val stq = Reg(Vec(numStqEntries, Valid(new STQEntry)))\n\n\n\n val ldq_head = Reg(UInt(ldqAddrSz.W))\n val ldq_tail = Reg(UInt(ldqAddrSz.W))\n val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory)\n val stq_tail = Reg(UInt(stqAddrSz.W))\n val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit\n val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute\n\n\n // If we got a mispredict, the tail will be misaligned for 1 extra cycle\n assert (io.core.brupdate.b2.mispredict ||\n stq(stq_execute_head).valid ||\n stq_head === stq_execute_head ||\n stq_tail === stq_execute_head,\n \"stq_execute_head got off track.\")\n\n val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7)\n // s1 : do TLB, if success and not killed, fire request go to h_s2\n // store s1_data to register\n // if tlb miss, go to s2_nack\n // if don't get TLB, go to s2_nack\n // store tlb xcpt\n // s2 : If kill, go to dead\n // If tlb xcpt, send tlb xcpt, go to dead\n // s2_nack : send nack, go to dead\n // wait : wait for response, if nack, go to replay\n // replay : refire request, use already translated address\n // dead : wait for response, ignore it\n val hella_state = RegInit(h_ready)\n val hella_req = Reg(new rocket.HellaCacheReq)\n val hella_data = Reg(new rocket.HellaCacheWriteData)\n val hella_paddr = Reg(UInt(paddrBits.W))\n val hella_xcpt = Reg(new rocket.HellaCacheExceptions)\n\n\n val dtlb = Module(new NBDTLB(\n instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays)))\n\n io.ptw <> dtlb.io.ptw\n io.core.perf.tlbMiss := io.ptw.req.fire\n io.core.perf.acquire := io.dmem.perf.acquire\n io.core.perf.release := io.dmem.perf.release\n\n\n\n val clear_store = WireInit(false.B)\n val live_store_mask = RegInit(0.U(numStqEntries.W))\n var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head),\n live_store_mask)\n\n\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Enqueue new entries\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // This is a newer store than existing loads, so clear the bit in all the store dependency masks\n for (i <- 0 until numLdqEntries)\n {\n when (clear_store)\n {\n ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head)\n }\n }\n\n // Decode stage\n var ld_enq_idx = ldq_tail\n var st_enq_idx = stq_tail\n\n val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U\n\n var ldq_full = Bool()\n var stq_full = Bool()\n\n for (w <- 0 until coreWidth)\n {\n ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head\n io.core.ldq_full(w) := ldq_full\n io.core.dis_ldq_idx(w) := ld_enq_idx\n\n stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head\n io.core.stq_full(w) := stq_full\n io.core.dis_stq_idx(w) := st_enq_idx\n\n val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception\n val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception\n when (dis_ld_val)\n {\n ldq(ld_enq_idx).valid := true.B\n ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits\n ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx\n ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask\n\n ldq(ld_enq_idx).bits.addr.valid := false.B\n ldq(ld_enq_idx).bits.executed := false.B\n ldq(ld_enq_idx).bits.succeeded := false.B\n ldq(ld_enq_idx).bits.order_fail := false.B\n ldq(ld_enq_idx).bits.observed := false.B\n ldq(ld_enq_idx).bits.forward_std_val := false.B\n\n assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n assert (!ldq(ld_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting ldq entries\")\n }\n .elsewhen (dis_st_val)\n {\n stq(st_enq_idx).valid := true.B\n stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits\n stq(st_enq_idx).bits.addr.valid := false.B\n stq(st_enq_idx).bits.data.valid := false.B\n stq(st_enq_idx).bits.committed := false.B\n stq(st_enq_idx).bits.succeeded := false.B\n\n assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n assert (!stq(st_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting stq entries\")\n }\n\n ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries),\n ld_enq_idx)\n\n next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx),\n next_live_store_mask)\n st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries),\n st_enq_idx)\n\n assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n }\n\n ldq_tail := ld_enq_idx\n stq_tail := st_enq_idx\n\n io.dmem.force_order := io.core.fence_dmem\n io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Execute stage (access TLB, send requests to Memory)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // We can only report 1 exception per cycle.\n // Just be sure to report the youngest one\n val mem_xcpt_valid = Wire(Bool())\n val mem_xcpt_cause = Wire(UInt())\n val mem_xcpt_uop = Wire(new MicroOp)\n val mem_xcpt_vaddr = Wire(UInt())\n\n\n //---------------------------------------\n // Can-fire logic and wakeup/retry select\n //\n // First we determine what operations are waiting to execute.\n // These are the \"can_fire\"/\"will_fire\" signals\n\n val will_fire_load_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_stad_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_sta_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_std_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_sfence = Wire(Vec(memWidth, Bool()))\n val will_fire_hella_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool()))\n val will_fire_release = Wire(Vec(memWidth, Bool()))\n val will_fire_load_retry = Wire(Vec(memWidth, Bool()))\n val will_fire_sta_retry = Wire(Vec(memWidth, Bool()))\n val will_fire_store_commit = Wire(Vec(memWidth, Bool()))\n val will_fire_load_wakeup = Wire(Vec(memWidth, Bool()))\n\n val exe_req = WireInit(VecInit(io.core.exe.map(_.req)))\n // Sfence goes through all pipes\n for (i <- 0 until memWidth) {\n when (io.core.exe(i).req.bits.sfence.valid) {\n exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req })\n }\n }\n\n // -------------------------------\n // Assorted signals for scheduling\n\n // Don't wakeup a load if we just sent it last cycle or two cycles ago\n // The block_load_mask may be wrong, but the executing_load mask must be accurate\n val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))\n val p1_block_load_mask = RegNext(block_load_mask)\n val p2_block_load_mask = RegNext(p1_block_load_mask)\n\n // Prioritize emptying the store queue when it is almost full\n val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head ||\n WrapInc(st_enq_idx, numStqEntries) === stq_head)\n\n // The store at the commit head needs the DCache to appear ordered\n // Delay firing load wakeups and retries now\n val store_needs_order = WireInit(false.B)\n\n val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx)\n val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i)))\n\n val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx)\n val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i)))\n\n val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => {\n val e = ldq(i).bits\n val block = block_load_mask(i) || p1_block_load_mask(i)\n e.addr.valid && e.addr_is_virtual && !block\n }), ldq_head))\n val ldq_retry_e = ldq(ldq_retry_idx)\n\n val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => {\n val e = stq(i).bits\n e.addr.valid && e.addr_is_virtual\n }), stq_commit_head))\n val stq_retry_e = stq(stq_retry_idx)\n\n val stq_commit_e = stq(stq_execute_head)\n\n val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> {\n val e = ldq(i).bits\n val block = block_load_mask(i) || p1_block_load_mask(i)\n e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block\n }), ldq_head))\n val ldq_wakeup_e = ldq(ldq_wakeup_idx)\n\n // -----------------------\n // Determine what can fire\n\n // Can we fire a incoming load\n val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load)\n\n // Can we fire an incoming store addrgen + store datagen\n val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta\n && exe_req(w).bits.uop.ctrl.is_std)\n\n // Can we fire an incoming store addrgen\n val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta\n && !exe_req(w).bits.uop.ctrl.is_std)\n\n // Can we fire an incoming store datagen\n val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std\n && !exe_req(w).bits.uop.ctrl.is_sta)\n\n // Can we fire an incoming sfence\n val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid)\n\n // Can we fire a request from dcache to release a line\n // This needs to go through LDQ search to mark loads as dangerous\n val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid)\n io.dmem.release.ready := will_fire_release.reduce(_||_)\n\n // Can we retry a load that missed in the TLB\n val can_fire_load_retry = widthMap(w =>\n ( ldq_retry_e.valid &&\n ldq_retry_e.bits.addr.valid &&\n ldq_retry_e.bits.addr_is_virtual &&\n !p1_block_load_mask(ldq_retry_idx) &&\n !p2_block_load_mask(ldq_retry_idx) &&\n RegNext(dtlb.io.miss_rdy) &&\n !store_needs_order &&\n (w == memWidth-1).B && // TODO: Is this best scheduling?\n !ldq_retry_e.bits.order_fail))\n\n // Can we retry a store addrgen that missed in the TLB\n // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this\n val can_fire_sta_retry = widthMap(w =>\n ( stq_retry_e.valid &&\n stq_retry_e.bits.addr.valid &&\n stq_retry_e.bits.addr_is_virtual &&\n (w == memWidth-1).B &&\n RegNext(dtlb.io.miss_rdy) &&\n !(widthMap(i => (i != w).B &&\n can_fire_std_incoming(i) &&\n stq_incoming_idx(i) === stq_retry_idx).reduce(_||_))\n ))\n // Can we commit a store\n val can_fire_store_commit = widthMap(w =>\n ( stq_commit_e.valid &&\n !stq_commit_e.bits.uop.is_fence &&\n !mem_xcpt_valid &&\n !stq_commit_e.bits.uop.exception &&\n (w == 0).B &&\n (stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo &&\n stq_commit_e.bits.addr.valid &&\n !stq_commit_e.bits.addr_is_virtual &&\n stq_commit_e.bits.data.valid))))\n\n // Can we wakeup a load that was nack'd\n val block_load_wakeup = WireInit(false.B)\n val can_fire_load_wakeup = widthMap(w =>\n ( ldq_wakeup_e.valid &&\n ldq_wakeup_e.bits.addr.valid &&\n !ldq_wakeup_e.bits.succeeded &&\n !ldq_wakeup_e.bits.addr_is_virtual &&\n !ldq_wakeup_e.bits.executed &&\n !ldq_wakeup_e.bits.order_fail &&\n !p1_block_load_mask(ldq_wakeup_idx) &&\n !p2_block_load_mask(ldq_wakeup_idx) &&\n !store_needs_order &&\n !block_load_wakeup &&\n (w == memWidth-1).B &&\n (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head &&\n ldq_head === ldq_wakeup_idx &&\n ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U))))\n\n // Can we fire an incoming hellacache request\n val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller\n\n // Can we fire a hellacache request that the dcache nack'd\n val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller\n\n //---------------------------------------------------------\n // Controller logic. Arbitrate which request actually fires\n\n val exe_tlb_valid = Wire(Vec(memWidth, Bool()))\n for (w <- 0 until memWidth) {\n var tlb_avail = true.B\n var dc_avail = true.B\n var lcam_avail = true.B\n var rob_avail = true.B\n\n def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = {\n val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) &&\n !(uses_lcam.B && !lcam_avail) &&\n !(uses_dc.B && !dc_avail) &&\n !(uses_rob.B && !rob_avail)\n tlb_avail = tlb_avail && !(will_fire && uses_tlb.B)\n lcam_avail = lcam_avail && !(will_fire && uses_lcam.B)\n dc_avail = dc_avail && !(will_fire && uses_dc.B)\n rob_avail = rob_avail && !(will_fire && uses_rob.B)\n dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals\n will_fire\n }\n\n // The order of these statements is the priority\n // Some restrictions\n // - Incoming ops must get precedence, can't backpresure memaddrgen\n // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation)\n // Notes on performance\n // - Prioritize releases, this speeds up cache line writebacks and refills\n // - Store commits are lowest priority, since they don't \"block\" younger instructions unless stq fills up\n will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM\n will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB\n will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB\n will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB\n will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB\n will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM\n will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC\n will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC\n will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM\n will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority\n will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1\n will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC\n\n\n assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w))))\n\n when (will_fire_load_wakeup(w)) {\n block_load_mask(ldq_wakeup_idx) := true.B\n } .elsewhen (will_fire_load_incoming(w)) {\n block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B\n } .elsewhen (will_fire_load_retry(w)) {\n block_load_mask(ldq_retry_idx) := true.B\n }\n exe_tlb_valid(w) := !tlb_avail\n }\n assert((memWidth == 1).B ||\n (!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) &&\n !will_fire_hella_incoming.reduce(_&&_) &&\n !will_fire_hella_wakeup.reduce(_&&_) &&\n !will_fire_load_retry.reduce(_&&_) &&\n !will_fire_sta_retry.reduce(_&&_) &&\n !will_fire_store_commit.reduce(_&&_) &&\n !will_fire_load_wakeup.reduce(_&&_)),\n \"Some operations is proceeding down multiple pipes\")\n\n require(memWidth <= 2)\n\n //--------------------------------------------\n // TLB Access\n\n assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),\n \"SFENCE through hella interface not supported\")\n\n val exe_tlb_uop = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) , exe_req(w).bits.uop,\n Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop,\n Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop,\n Mux(will_fire_hella_incoming(w) , NullMicroOp,\n NullMicroOp)))))\n\n val exe_tlb_vaddr = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) , exe_req(w).bits.addr,\n Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr,\n Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits,\n Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits,\n Mux(will_fire_hella_incoming(w) , hella_req.addr,\n 0.U))))))\n\n val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq)))\n for (w <- 0 until memWidth) {\n when (will_fire_sfence(w)) {\n exe_sfence := exe_req(w).bits.sfence\n }\n }\n\n val exe_size = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) ||\n will_fire_load_retry (w) ||\n will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size,\n Mux(will_fire_hella_incoming(w) , hella_req.size,\n 0.U)))\n val exe_cmd = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) ||\n will_fire_load_retry (w) ||\n will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd,\n Mux(will_fire_hella_incoming(w) , hella_req.cmd,\n 0.U)))\n\n val exe_passthr= widthMap(w =>\n Mux(will_fire_hella_incoming(w) , hella_req.phys,\n false.B))\n val exe_kill = widthMap(w =>\n Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill,\n false.B))\n for (w <- 0 until memWidth) {\n dtlb.io.req(w).valid := exe_tlb_valid(w)\n dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w)\n dtlb.io.req(w).bits.size := exe_size(w)\n dtlb.io.req(w).bits.cmd := exe_cmd(w)\n dtlb.io.req(w).bits.passthrough := exe_passthr(w)\n dtlb.io.req(w).bits.v := io.ptw.status.v\n dtlb.io.req(w).bits.prv := io.ptw.status.prv\n }\n dtlb.io.kill := exe_kill.reduce(_||_)\n dtlb.io.sfence := exe_sfence\n\n // exceptions\n val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc\n val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc\n val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq)\n val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq)\n val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq)\n val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq)\n\n // TODO check for xcpt_if and verify that never happens on non-speculative instructions.\n val mem_xcpt_valids = RegNext(widthMap(w =>\n (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) &&\n !io.core.exception &&\n !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w))))\n val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w))))\n val mem_xcpt_causes = RegNext(widthMap(w =>\n Mux(ma_ld(w), rocket.Causes.misaligned_load.U,\n Mux(ma_st(w), rocket.Causes.misaligned_store.U,\n Mux(pf_ld(w), rocket.Causes.load_page_fault.U,\n Mux(pf_st(w), rocket.Causes.store_page_fault.U,\n Mux(ae_ld(w), rocket.Causes.load_access.U,\n rocket.Causes.store_access.U)))))))\n val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr)\n\n for (w <- 0 until memWidth) {\n assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), \"Fence is pretending to talk to the TLB\")\n assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) &&\n exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid &&\n !(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)),\n \"A uop that's not a load or store-address is throwing a memory exception.\")\n }\n\n mem_xcpt_valid := mem_xcpt_valids.reduce(_||_)\n mem_xcpt_cause := mem_xcpt_causes(0)\n mem_xcpt_uop := mem_xcpt_uops(0)\n mem_xcpt_vaddr := mem_xcpt_vaddrs(0)\n var xcpt_found = mem_xcpt_valids(0)\n var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx\n for (w <- 1 until memWidth) {\n val is_older = WireInit(false.B)\n when (mem_xcpt_valids(w) &&\n (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) {\n is_older := true.B\n mem_xcpt_cause := mem_xcpt_causes(w)\n mem_xcpt_uop := mem_xcpt_uops(w)\n mem_xcpt_vaddr := mem_xcpt_vaddrs(w)\n }\n xcpt_found = xcpt_found || mem_xcpt_valids(w)\n oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx)\n }\n\n val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready))\n val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits),\n exe_tlb_vaddr(w)(corePgIdxBits-1,0)))\n val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable))\n\n for (w <- 0 until memWidth) {\n assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, \"[lsu] paddrs should match.\")\n\n when (mem_xcpt_valids(w))\n {\n assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) ||\n will_fire_load_retry(w) || will_fire_sta_retry(w)))\n // Technically only faulting AMOs need this\n assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)\n when (mem_xcpt_uops(w).uses_ldq)\n {\n ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B\n }\n .otherwise\n {\n stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B\n }\n }\n }\n\n\n\n //------------------------------\n // Issue Someting to Memory\n //\n // A memory op can come from many different places\n // The address either was freshly translated, or we are\n // reading a physical address from the LDQ,STQ, or the HellaCache adapter\n\n\n // defaults\n io.dmem.brupdate := io.core.brupdate\n io.dmem.exception := io.core.exception\n io.dmem.rob_head_idx := io.core.rob_head_idx\n io.dmem.rob_pnr_idx := io.core.rob_pnr_idx\n\n val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq)))\n io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_)\n io.dmem.req.bits := dmem_req\n val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire)\n\n val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))\n\n\n for (w <- 0 until memWidth) {\n dmem_req(w).valid := false.B\n dmem_req(w).bits.uop := NullMicroOp\n dmem_req(w).bits.addr := 0.U\n dmem_req(w).bits.data := 0.U\n dmem_req(w).bits.is_hella := false.B\n\n io.dmem.s1_kill(w) := false.B\n\n when (will_fire_load_incoming(w)) {\n dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.uop := exe_tlb_uop(w)\n\n s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w)\n assert(!ldq_incoming_e(w).bits.executed)\n } .elsewhen (will_fire_load_retry(w)) {\n dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.uop := exe_tlb_uop(w)\n\n s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w)\n assert(!ldq_retry_e.bits.executed)\n } .elsewhen (will_fire_store_commit(w)) {\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n stq_commit_e.bits.uop.mem_size, 0.U,\n stq_commit_e.bits.data.bits,\n coreDataBytes)).data\n dmem_req(w).bits.uop := stq_commit_e.bits.uop\n\n stq_execute_head := Mux(dmem_req_fire(w),\n WrapInc(stq_execute_head, numStqEntries),\n stq_execute_head)\n\n stq(stq_execute_head).bits.succeeded := false.B\n } .elsewhen (will_fire_load_wakeup(w)) {\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits\n dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop\n\n s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w)\n\n assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)\n } .elsewhen (will_fire_hella_incoming(w)) {\n assert(hella_state === h_s1)\n\n dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n hella_req.size, 0.U,\n io.hellacache.s1_data.data,\n coreDataBytes)).data\n dmem_req(w).bits.uop.mem_cmd := hella_req.cmd\n dmem_req(w).bits.uop.mem_size := hella_req.size\n dmem_req(w).bits.uop.mem_signed := hella_req.signed\n dmem_req(w).bits.is_hella := true.B\n\n hella_paddr := exe_tlb_paddr(w)\n }\n .elsewhen (will_fire_hella_wakeup(w))\n {\n assert(hella_state === h_replay)\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := hella_paddr\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n hella_req.size, 0.U,\n hella_data.data,\n coreDataBytes)).data\n dmem_req(w).bits.uop.mem_cmd := hella_req.cmd\n dmem_req(w).bits.uop.mem_size := hella_req.size\n dmem_req(w).bits.uop.mem_signed := hella_req.signed\n dmem_req(w).bits.is_hella := true.B\n }\n\n //-------------------------------------------------------------\n // Write Addr into the LAQ/SAQ\n when (will_fire_load_incoming(w) || will_fire_load_retry(w))\n {\n val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx)\n ldq(ldq_idx).bits.addr.valid := true.B\n ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))\n ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst\n ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w)\n ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w)\n\n assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid),\n \"[lsu] Incoming load is overwriting a valid address\")\n }\n\n when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w))\n {\n val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w),\n stq_incoming_idx(w), stq_retry_idx)\n\n stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing!\n stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))\n stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs\n stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w)\n\n assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid),\n \"[lsu] Incoming store is overwriting a valid address\")\n\n }\n\n //-------------------------------------------------------------\n // Write data into the STQ\n if (w == 0)\n io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w)\n val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B\n when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire)\n {\n val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),\n stq_incoming_idx(w),\n io.core.fp_stdata.bits.uop.stq_idx)\n stq(sidx).bits.data.valid := true.B\n stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),\n exe_req(w).bits.data,\n io.core.fp_stdata.bits.data)\n assert(!(stq(sidx).bits.data.valid),\n \"[lsu] Incoming store is overwriting a valid data entry\")\n }\n }\n val will_fire_stdf_incoming = io.core.fp_stdata.fire\n require (xLen >= fLen) // for correct SDQ size\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Cache Access Cycle (Mem)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Note the DCache may not have accepted our request\n\n val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop))\n val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop)\n\n val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w)))\n val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w)))\n val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w)))\n val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w)))\n val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed)\n val fired_sfence = RegNext(will_fire_sfence)\n val fired_release = RegNext(will_fire_release)\n val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop)))\n val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop)))\n val fired_store_commit = RegNext(will_fire_store_commit)\n val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop)))\n val fired_hella_incoming = RegNext(will_fire_hella_incoming)\n val fired_hella_wakeup = RegNext(will_fire_hella_wakeup)\n\n val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop)))\n val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w))))\n val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w))))\n val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e))\n val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e))\n val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e))\n val mem_ldq_e = widthMap(w =>\n Mux(fired_load_incoming(w), mem_ldq_incoming_e(w),\n Mux(fired_load_retry (w), mem_ldq_retry_e,\n Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry))))))\n val mem_stq_e = widthMap(w =>\n Mux(fired_stad_incoming(w) ||\n fired_sta_incoming (w), mem_stq_incoming_e(w),\n Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry)))))\n val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop))\n\n\n val mem_tlb_miss = RegNext(exe_tlb_miss)\n val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable)\n val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr))\n\n // Task 1: Clr ROB busy bit\n val clr_bsy_valid = RegInit(widthMap(w => false.B))\n val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W)))\n val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W)))\n\n for (w <- 0 until memWidth) {\n clr_bsy_valid (w) := false.B\n clr_bsy_rob_idx (w) := 0.U\n clr_bsy_brmask (w) := 0.U\n\n\n when (fired_stad_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_sta_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n mem_stq_incoming_e(w).bits.data.valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_std_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n mem_stq_incoming_e(w).bits.addr.valid &&\n !mem_stq_incoming_e(w).bits.addr_is_virtual &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_sfence(w)) {\n clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob\n clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w))\n } .elsewhen (fired_sta_retry(w)) {\n clr_bsy_valid (w) := mem_stq_retry_e.valid &&\n mem_stq_retry_e.bits.data.valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_retry_e.bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop)\n }\n\n io.core.clr_bsy(w).valid := clr_bsy_valid(w) &&\n !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) &&\n !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))\n io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w)\n }\n\n val stdf_clr_bsy_valid = RegInit(false.B)\n val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W))\n val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W))\n stdf_clr_bsy_valid := false.B\n stdf_clr_bsy_rob_idx := 0.U\n stdf_clr_bsy_brmask := 0.U\n when (fired_stdf_incoming) {\n val s_idx = mem_stdf_uop.stq_idx\n stdf_clr_bsy_valid := stq(s_idx).valid &&\n stq(s_idx).bits.addr.valid &&\n !stq(s_idx).bits.addr_is_virtual &&\n !stq(s_idx).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stdf_uop)\n stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx\n stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop)\n }\n\n\n\n io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid &&\n !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) &&\n !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))\n io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx\n\n\n\n // Task 2: Do LD-LD. ST-LD searches for ordering failures\n // Do LD-ST search for forwarding opportunities\n // We have the opportunity to kill a request we sent last cycle. Use it wisely!\n\n // We translated a store last cycle\n val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w))\n // We translated a load last cycle\n val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) ||\n fired_load_wakeup(w))\n // We are making a local line visible to other harts\n val do_release_search = widthMap(w => fired_release(w))\n\n // Store addrs don't go to memory yet, get it from the TLB response\n // Load wakeups don't go through TLB, get it through memory\n // Load incoming and load retries go through both\n\n val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w),\n RegNext(exe_tlb_paddr(w)),\n Mux(fired_release(w), RegNext(io.dmem.release.bits.address),\n mem_paddr(w))))\n val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop,\n Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp)))\n\n val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size))\n val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask)\n val lcam_is_release = widthMap(w => fired_release(w))\n val lcam_ldq_idx = widthMap(w =>\n Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx,\n Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx),\n Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U))))\n val lcam_stq_idx = widthMap(w =>\n Mux(fired_stad_incoming(w) ||\n fired_sta_incoming (w), mem_incoming_uop(w).stq_idx,\n Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U)))\n\n val can_forward = WireInit(widthMap(w =>\n Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w),\n !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable)))\n\n // Mask of stores which we conflict on address with\n val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))\n // Mask of stores which we can forward from\n val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))\n\n val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception)\n val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage\n\n val s1_executing_loads = RegNext(s0_executing_loads)\n val s1_set_execute = WireInit(s1_executing_loads)\n\n val mem_forward_valid = Wire(Vec(memWidth, Bool()))\n val mem_forward_ldq_idx = lcam_ldq_idx\n val mem_forward_ld_addr = lcam_addr\n val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W)))\n\n val wb_forward_valid = RegNext(mem_forward_valid)\n val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx)\n val wb_forward_ld_addr = RegNext(mem_forward_ld_addr)\n val wb_forward_stq_idx = RegNext(mem_forward_stq_idx)\n\n for (i <- 0 until numLdqEntries) {\n val l_valid = ldq(i).valid\n val l_bits = ldq(i).bits\n val l_addr = ldq(i).bits.addr.bits\n val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size)\n\n val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U)\n val l_is_forwarding = l_forwarders.reduce(_||_)\n val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx)\n\n\n val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits)\n val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3))\n val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask)\n val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR)\n\n // Searcher is a store\n for (w <- 0 until memWidth) {\n\n when (do_release_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n block_addr_matches(w)) {\n // This load has been observed, so if a younger load to the same address has not\n // executed yet, this load must be squashed\n ldq(i).bits.observed := true.B\n } .elsewhen (do_st_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n (l_bits.executed || l_bits.succeeded || l_is_forwarding) &&\n !l_bits.addr_is_virtual &&\n l_bits.st_dep_mask(lcam_stq_idx(w)) &&\n dword_addr_matches(w) &&\n mask_overlap(w)) {\n\n val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx)\n // We are older than this load, which overlapped us.\n when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed\n ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok\n ldq(i).bits.order_fail := true.B\n failed_loads(i) := true.B\n }\n } .elsewhen (do_ld_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n !l_bits.addr_is_virtual &&\n dword_addr_matches(w) &&\n mask_overlap(w)) {\n val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head)\n when (searcher_is_older) {\n when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) &&\n !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it\n l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us\n ldq(i).bits.order_fail := true.B\n failed_loads(i) := true.B\n }\n } .elsewhen (lcam_ldq_idx(w) =/= i.U) {\n // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response\n // we need to kill ourselves, and prevent forwarding\n val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i))\n when (!(l_bits.executed || l_bits.succeeded) || older_nacked) {\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n can_forward(w) := false.B\n }\n }\n }\n }\n }\n\n for (i <- 0 until numStqEntries) {\n val s_addr = stq(i).bits.addr.bits\n val s_uop = stq(i).bits.uop\n val dword_addr_matches = widthMap(w =>\n ( stq(i).bits.addr.valid &&\n !stq(i).bits.addr_is_virtual &&\n (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3))))\n val write_mask = GenByteMask(s_addr, s_uop.mem_size)\n for (w <- 0 until memWidth) {\n when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) {\n when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w))\n {\n ldst_addr_matches(w)(i) := true.B\n ldst_forward_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w))\n {\n ldst_addr_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n .elsewhen (s_uop.is_fence || s_uop.is_amo)\n {\n ldst_addr_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n }\n }\n }\n\n // Set execute bit in LDQ\n for (i <- 0 until numLdqEntries) {\n when (s1_set_execute(i)) { ldq(i).bits.executed := true.B }\n }\n\n // Find the youngest store which the load is dependent on\n val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) }\n for (w <- 0 until memWidth) {\n forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt\n forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx\n }\n val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx)\n\n // Forward if st-ld forwarding is possible from the writemask and loadmask\n mem_forward_valid := widthMap(w =>\n (ldst_forward_matches(w)(forwarding_idx(w)) &&\n !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) &&\n !io.core.exception && !RegNext(io.core.exception)))\n mem_forward_stq_idx := forwarding_idx\n\n // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits\n // On a 2W machine, load wakeups and store commits occupy separate pipelines,\n // so only add this logic for 1-w LSU\n if (memWidth == 1) {\n // Wakeups may repeatedly find a st->ld addr conflict and fail to forward,\n // repeated wakeups may block the store from ever committing\n // Disallow load wakeups 1 cycle after this happens to allow the stores to drain\n when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) {\n block_load_wakeup := true.B\n }\n\n // If stores remain blocked for 15 cycles, block load wakeups to get a store through\n val store_blocked_counter = Reg(UInt(4.W))\n when (will_fire_store_commit(0) || !can_fire_store_commit(0)) {\n store_blocked_counter := 0.U\n } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) {\n store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U)\n }\n when (store_blocked_counter === 15.U) {\n block_load_wakeup := true.B\n }\n }\n\n\n // Task 3: Clr unsafe bit in ROB for succesful translations\n // Delay this a cycle to avoid going ahead of the exception broadcast\n // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups\n for (w <- 0 until memWidth) {\n io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B\n io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx)\n }\n\n // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load\n // TODO encapsulate this in an age-based priority-encoder\n // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head)\n // ++ failed_loads)).asUInt)\n val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i =>\n failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt\n val l_idx = PriorityEncoder(temp_bits)\n\n // one exception port, but multiple causes!\n // - 1) the incoming store-address finds a faulting load (it is by definition younger)\n // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent.\n val r_xcpt_valid = RegInit(false.B)\n val r_xcpt = Reg(new Exception)\n\n val ld_xcpt_valid = failed_loads.reduce(_|_)\n val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop\n\n val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid\n\n val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop)\n\n r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) &&\n !io.core.exception &&\n !IsKilledByBranch(io.core.brupdate, xcpt_uop)\n r_xcpt.uop := xcpt_uop\n r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop)\n r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING)\n r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead?\n\n io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop)\n io.core.lxcpt.bits := r_xcpt\n\n // Task 4: Speculatively wakeup loads 1 cycle before they come back\n for (w <- 0 until memWidth) {\n io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B &&\n fired_load_incoming(w) &&\n !mem_incoming_uop(w).fp_val &&\n mem_incoming_uop(w).pdst =/= 0.U\n io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst\n }\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Writeback Cycle (St->Ld Forwarding Path)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Handle Memory Responses and nacks\n //----------------------------------\n for (w <- 0 until memWidth) {\n io.core.exe(w).iresp.valid := false.B\n io.core.exe(w).iresp.bits := DontCare\n io.core.exe(w).fresp.valid := false.B\n io.core.exe(w).fresp.bits := DontCare\n }\n\n val dmem_resp_fired = WireInit(widthMap(w => false.B))\n\n for (w <- 0 until memWidth) {\n // Handle nacks\n when (io.dmem.nack(w).valid)\n {\n // We have to re-execute this!\n when (io.dmem.nack(w).bits.is_hella)\n {\n assert(hella_state === h_wait || hella_state === h_dead)\n }\n .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq)\n {\n assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed)\n ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B\n nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B\n }\n .otherwise\n {\n assert(io.dmem.nack(w).bits.uop.uses_stq)\n when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) {\n stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx\n }\n }\n }\n // Handle the response\n when (io.dmem.resp(w).valid)\n {\n when (io.dmem.resp(w).bits.uop.uses_ldq)\n {\n assert(!io.dmem.resp(w).bits.is_hella)\n val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx\n val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX\n val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT\n\n io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop\n io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop\n io.core.exe(w).iresp.valid := send_iresp\n io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data\n io.core.exe(w).fresp.valid := send_fresp\n io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data\n\n assert(send_iresp ^ send_fresp)\n dmem_resp_fired(w) := true.B\n\n ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid\n ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data\n }\n .elsewhen (io.dmem.resp(w).bits.uop.uses_stq)\n {\n assert(!io.dmem.resp(w).bits.is_hella)\n stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B\n when (io.dmem.resp(w).bits.uop.is_amo) {\n dmem_resp_fired(w) := true.B\n io.core.exe(w).iresp.valid := true.B\n io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop\n io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data\n\n stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data\n }\n }\n }\n\n\n when (dmem_resp_fired(w) && wb_forward_valid(w))\n {\n // Twiddle thumbs. Can't forward because dcache response takes precedence\n }\n .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w))\n {\n val f_idx = wb_forward_ldq_idx(w)\n val forward_uop = ldq(f_idx).bits.uop\n val stq_e = stq(wb_forward_stq_idx(w))\n val data_ready = stq_e.bits.data.valid\n val live = !IsKilledByBranch(io.core.brupdate, forward_uop)\n val storegen = new freechips.rocketchip.rocket.StoreGen(\n stq_e.bits.uop.mem_size, stq_e.bits.addr.bits,\n stq_e.bits.data.bits, coreDataBytes)\n val loadgen = new freechips.rocketchip.rocket.LoadGen(\n forward_uop.mem_size, forward_uop.mem_signed,\n wb_forward_ld_addr(w),\n storegen.data, false.B, coreDataBytes)\n\n io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live\n io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live\n io.core.exe(w).iresp.bits.uop := forward_uop\n io.core.exe(w).fresp.bits.uop := forward_uop\n io.core.exe(w).iresp.bits.data := loadgen.data\n io.core.exe(w).fresp.bits.data := loadgen.data\n\n when (data_ready && live) {\n ldq(f_idx).bits.succeeded := data_ready\n ldq(f_idx).bits.forward_std_val := true.B\n ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w)\n\n ldq(f_idx).bits.debug_wb_data := loadgen.data\n }\n }\n }\n\n // Initially assume the speculative load wakeup failed\n io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_))\n val spec_ld_succeed = widthMap(w =>\n !RegNext(io.core.spec_ld_wakeup(w).valid) ||\n (io.core.exe(w).iresp.valid &&\n io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx)\n )\n ).reduce(_&&_)\n when (spec_ld_succeed) {\n io.core.ld_miss := false.B\n }\n\n\n //-------------------------------------------------------------\n // Kill speculated entries on branch mispredict\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Kill stores\n val st_brkilled_mask = Wire(Vec(numStqEntries, Bool()))\n for (i <- 0 until numStqEntries)\n {\n st_brkilled_mask(i) := false.B\n\n when (stq(i).valid)\n {\n stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask)\n\n when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop))\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n st_brkilled_mask(i) := true.B\n }\n }\n\n assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n \"Branch is trying to clear a committed store.\")\n }\n\n // Kill loads\n for (i <- 0 until numLdqEntries)\n {\n when (ldq(i).valid)\n {\n ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask)\n when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop))\n {\n ldq(i).valid := false.B\n ldq(i).bits.addr.valid := false.B\n }\n }\n }\n\n //-------------------------------------------------------------\n when (io.core.brupdate.b2.mispredict && !io.core.exception)\n {\n stq_tail := io.core.brupdate.b2.uop.stq_idx\n ldq_tail := io.core.brupdate.b2.uop.ldq_idx\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // dequeue old entries on commit\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n var temp_stq_commit_head = stq_commit_head\n var temp_ldq_head = ldq_head\n for (w <- 0 until coreWidth)\n {\n val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq\n val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq\n val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head)\n when (commit_store)\n {\n stq(idx).bits.committed := true.B\n } .elsewhen (commit_load) {\n assert (ldq(idx).valid, \"[lsu] trying to commit an un-allocated load entry.\")\n assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,\n \"[lsu] trying to commit an un-executed load entry.\")\n\n ldq(idx).valid := false.B\n ldq(idx).bits.addr.valid := false.B\n ldq(idx).bits.executed := false.B\n ldq(idx).bits.succeeded := false.B\n ldq(idx).bits.order_fail := false.B\n ldq(idx).bits.forward_std_val := false.B\n\n }\n\n if (MEMTRACE_PRINTF) {\n when (commit_store || commit_load) {\n val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop)\n val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits)\n val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U)\n val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data)\n printf(\"MT %x %x %x %x %x %x %x\\n\",\n io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata)\n }\n }\n\n temp_stq_commit_head = Mux(commit_store,\n WrapInc(temp_stq_commit_head, numStqEntries),\n temp_stq_commit_head)\n\n temp_ldq_head = Mux(commit_load,\n WrapInc(temp_ldq_head, numLdqEntries),\n temp_ldq_head)\n }\n stq_commit_head := temp_stq_commit_head\n ldq_head := temp_ldq_head\n\n // store has been committed AND successfully sent data to memory\n when (stq(stq_head).valid && stq(stq_head).bits.committed)\n {\n when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) {\n io.dmem.force_order := true.B\n store_needs_order := true.B\n }\n clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered,\n stq(stq_head).bits.succeeded)\n }\n\n when (clear_store)\n {\n stq(stq_head).valid := false.B\n stq(stq_head).bits.addr.valid := false.B\n stq(stq_head).bits.data.valid := false.B\n stq(stq_head).bits.succeeded := false.B\n stq(stq_head).bits.committed := false.B\n\n stq_head := WrapInc(stq_head, numStqEntries)\n when (stq(stq_head).bits.uop.is_fence)\n {\n stq_execute_head := WrapInc(stq_execute_head, numStqEntries)\n }\n }\n\n\n // -----------------------\n // Hellacache interface\n // We need to time things like a HellaCache would\n io.hellacache.req.ready := false.B\n io.hellacache.s2_nack := false.B\n io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions)\n io.hellacache.resp.valid := false.B\n io.hellacache.store_pending := stq.map(_.valid).reduce(_||_)\n when (hella_state === h_ready) {\n io.hellacache.req.ready := true.B\n when (io.hellacache.req.fire) {\n hella_req := io.hellacache.req.bits\n hella_state := h_s1\n }\n } .elsewhen (hella_state === h_s1) {\n can_fire_hella_incoming(memWidth-1) := true.B\n\n hella_data := io.hellacache.s1_data\n hella_xcpt := dtlb.io.resp(memWidth-1)\n\n when (io.hellacache.s1_kill) {\n when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_dead\n } .otherwise {\n hella_state := h_ready\n }\n } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_s2\n } .otherwise {\n hella_state := h_s2_nack\n }\n } .elsewhen (hella_state === h_s2_nack) {\n io.hellacache.s2_nack := true.B\n hella_state := h_ready\n } .elsewhen (hella_state === h_s2) {\n io.hellacache.s2_xcpt := hella_xcpt\n when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) {\n hella_state := h_dead\n } .otherwise {\n hella_state := h_wait\n }\n } .elsewhen (hella_state === h_wait) {\n for (w <- 0 until memWidth) {\n when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {\n hella_state := h_ready\n\n io.hellacache.resp.valid := true.B\n io.hellacache.resp.bits.addr := hella_req.addr\n io.hellacache.resp.bits.tag := hella_req.tag\n io.hellacache.resp.bits.cmd := hella_req.cmd\n io.hellacache.resp.bits.signed := hella_req.signed\n io.hellacache.resp.bits.size := hella_req.size\n io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data\n } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) {\n hella_state := h_replay\n }\n }\n } .elsewhen (hella_state === h_replay) {\n can_fire_hella_wakeup(memWidth-1) := true.B\n\n when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_wait\n }\n } .elsewhen (hella_state === h_dead) {\n for (w <- 0 until memWidth) {\n when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {\n hella_state := h_ready\n }\n }\n }\n\n //-------------------------------------------------------------\n // Exception / Reset\n\n // for the live_store_mask, need to kill stores that haven't been committed\n val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B)))\n\n when (reset.asBool || io.core.exception)\n {\n ldq_head := 0.U\n ldq_tail := 0.U\n\n when (reset.asBool)\n {\n stq_head := 0.U\n stq_tail := 0.U\n stq_commit_head := 0.U\n stq_execute_head := 0.U\n\n for (i <- 0 until numStqEntries)\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n stq(i).bits.uop := NullMicroOp\n }\n }\n .otherwise // exception\n {\n stq_tail := stq_commit_head\n\n for (i <- 0 until numStqEntries)\n {\n when (!stq(i).bits.committed && !stq(i).bits.succeeded)\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n st_exc_killed_mask(i) := true.B\n }\n }\n }\n\n for (i <- 0 until numLdqEntries)\n {\n ldq(i).valid := false.B\n ldq(i).bits.addr.valid := false.B\n ldq(i).bits.executed := false.B\n }\n }\n\n //-------------------------------------------------------------\n // Live Store Mask\n // track a bit-array of stores that are alive\n // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries)\n\n // TODO is this the most efficient way to compute the live store mask?\n live_store_mask := next_live_store_mask &\n ~(st_brkilled_mask.asUInt) &\n ~(st_exc_killed_mask.asUInt)\n\n\n}\n\n/**\n * Object to take an address and generate an 8-bit mask of which bytes within a\n * double-word.\n */\nobject GenByteMask\n{\n def apply(addr: UInt, size: UInt): UInt =\n {\n val mask = Wire(UInt(8.W))\n mask := MuxCase(255.U(8.W), Array(\n (size === 0.U) -> (1.U(8.W) << addr(2,0)),\n (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)),\n (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)),\n (size === 3.U) -> 255.U(8.W)))\n mask\n }\n}\n\n/**\n * ...\n */\nclass ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p)\n{\n val io = IO(new Bundle\n {\n val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match\n // between the load and the SAQ\n val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get \"age\"\n\n val forwarding_val = Output(Bool())\n val forwarding_idx = Output(UInt(stqAddrSz.W))\n })\n\n // generating mask that zeroes out anything younger than tail\n val age_mask = Wire(Vec(num_entries, Bool()))\n for (i <- 0 until num_entries)\n {\n age_mask(i) := true.B\n when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >=\n {\n age_mask(i) := false.B\n }\n }\n\n // Priority encoder with moving tail: double length\n val matches = Wire(UInt((2*num_entries).W))\n matches := Cat(io.addr_matches & age_mask.asUInt,\n io.addr_matches)\n\n val found_match = Wire(Bool())\n found_match := false.B\n io.forwarding_idx := 0.U\n\n // look for youngest, approach from the oldest side, let the last one found stick\n for (i <- 0 until (2*num_entries))\n {\n when (matches(i))\n {\n found_match := true.B\n io.forwarding_idx := (i % num_entries).U\n }\n }\n\n io.forwarding_val := found_match\n}", + "response": "module LSU(\n input clock,\n input reset,\n input io_ptw_req_ready,\n output io_ptw_req_valid,\n output io_ptw_req_bits_valid,\n output [26:0] io_ptw_req_bits_bits_addr,\n input io_ptw_resp_valid,\n input io_ptw_resp_bits_ae_final,\n input [43:0] io_ptw_resp_bits_pte_ppn,\n input io_ptw_resp_bits_pte_d,\n input io_ptw_resp_bits_pte_a,\n input io_ptw_resp_bits_pte_g,\n input io_ptw_resp_bits_pte_u,\n input io_ptw_resp_bits_pte_x,\n input io_ptw_resp_bits_pte_w,\n input io_ptw_resp_bits_pte_r,\n input io_ptw_resp_bits_pte_v,\n input [1:0] io_ptw_resp_bits_level,\n input io_ptw_resp_bits_homogeneous,\n input [3:0] io_ptw_ptbr_mode,\n input [1:0] io_ptw_status_dprv,\n input io_ptw_status_mxr,\n input io_ptw_status_sum,\n input io_ptw_pmp_0_cfg_l,\n input [1:0] io_ptw_pmp_0_cfg_a,\n input io_ptw_pmp_0_cfg_x,\n input io_ptw_pmp_0_cfg_w,\n input io_ptw_pmp_0_cfg_r,\n input [29:0] io_ptw_pmp_0_addr,\n input [31:0] io_ptw_pmp_0_mask,\n input io_ptw_pmp_1_cfg_l,\n input [1:0] io_ptw_pmp_1_cfg_a,\n input io_ptw_pmp_1_cfg_x,\n input io_ptw_pmp_1_cfg_w,\n input io_ptw_pmp_1_cfg_r,\n input [29:0] io_ptw_pmp_1_addr,\n input [31:0] io_ptw_pmp_1_mask,\n input io_ptw_pmp_2_cfg_l,\n input [1:0] io_ptw_pmp_2_cfg_a,\n input io_ptw_pmp_2_cfg_x,\n input io_ptw_pmp_2_cfg_w,\n input io_ptw_pmp_2_cfg_r,\n input [29:0] io_ptw_pmp_2_addr,\n input [31:0] io_ptw_pmp_2_mask,\n input io_ptw_pmp_3_cfg_l,\n input [1:0] io_ptw_pmp_3_cfg_a,\n input io_ptw_pmp_3_cfg_x,\n input io_ptw_pmp_3_cfg_w,\n input io_ptw_pmp_3_cfg_r,\n input [29:0] io_ptw_pmp_3_addr,\n input [31:0] io_ptw_pmp_3_mask,\n input io_ptw_pmp_4_cfg_l,\n input [1:0] io_ptw_pmp_4_cfg_a,\n input io_ptw_pmp_4_cfg_x,\n input io_ptw_pmp_4_cfg_w,\n input io_ptw_pmp_4_cfg_r,\n input [29:0] io_ptw_pmp_4_addr,\n input [31:0] io_ptw_pmp_4_mask,\n input io_ptw_pmp_5_cfg_l,\n input [1:0] io_ptw_pmp_5_cfg_a,\n input io_ptw_pmp_5_cfg_x,\n input io_ptw_pmp_5_cfg_w,\n input io_ptw_pmp_5_cfg_r,\n input [29:0] io_ptw_pmp_5_addr,\n input [31:0] io_ptw_pmp_5_mask,\n input io_ptw_pmp_6_cfg_l,\n input [1:0] io_ptw_pmp_6_cfg_a,\n input io_ptw_pmp_6_cfg_x,\n input io_ptw_pmp_6_cfg_w,\n input io_ptw_pmp_6_cfg_r,\n input [29:0] io_ptw_pmp_6_addr,\n input [31:0] io_ptw_pmp_6_mask,\n input io_ptw_pmp_7_cfg_l,\n input [1:0] io_ptw_pmp_7_cfg_a,\n input io_ptw_pmp_7_cfg_x,\n input io_ptw_pmp_7_cfg_w,\n input io_ptw_pmp_7_cfg_r,\n input [29:0] io_ptw_pmp_7_addr,\n input [31:0] io_ptw_pmp_7_mask,\n input io_core_exe_0_req_valid,\n input [6:0] io_core_exe_0_req_bits_uop_uopc,\n input [31:0] io_core_exe_0_req_bits_uop_inst,\n input [31:0] io_core_exe_0_req_bits_uop_debug_inst,\n input io_core_exe_0_req_bits_uop_is_rvc,\n input [39:0] io_core_exe_0_req_bits_uop_debug_pc,\n input [2:0] io_core_exe_0_req_bits_uop_iq_type,\n input [9:0] io_core_exe_0_req_bits_uop_fu_code,\n input [3:0] io_core_exe_0_req_bits_uop_ctrl_br_type,\n input [1:0] io_core_exe_0_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_core_exe_0_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_core_exe_0_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_core_exe_0_req_bits_uop_ctrl_op_fcn,\n input io_core_exe_0_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_core_exe_0_req_bits_uop_ctrl_csr_cmd,\n input io_core_exe_0_req_bits_uop_ctrl_is_load,\n input io_core_exe_0_req_bits_uop_ctrl_is_sta,\n input io_core_exe_0_req_bits_uop_ctrl_is_std,\n input [1:0] io_core_exe_0_req_bits_uop_iw_state,\n input io_core_exe_0_req_bits_uop_is_br,\n input io_core_exe_0_req_bits_uop_is_jalr,\n input io_core_exe_0_req_bits_uop_is_jal,\n input io_core_exe_0_req_bits_uop_is_sfb,\n input [7:0] io_core_exe_0_req_bits_uop_br_mask,\n input [2:0] io_core_exe_0_req_bits_uop_br_tag,\n input [3:0] io_core_exe_0_req_bits_uop_ftq_idx,\n input io_core_exe_0_req_bits_uop_edge_inst,\n input [5:0] io_core_exe_0_req_bits_uop_pc_lob,\n input io_core_exe_0_req_bits_uop_taken,\n input [19:0] io_core_exe_0_req_bits_uop_imm_packed,\n input [11:0] io_core_exe_0_req_bits_uop_csr_addr,\n input [4:0] io_core_exe_0_req_bits_uop_rob_idx,\n input [2:0] io_core_exe_0_req_bits_uop_ldq_idx,\n input [2:0] io_core_exe_0_req_bits_uop_stq_idx,\n input [1:0] io_core_exe_0_req_bits_uop_rxq_idx,\n input [5:0] io_core_exe_0_req_bits_uop_pdst,\n input [5:0] io_core_exe_0_req_bits_uop_prs1,\n input [5:0] io_core_exe_0_req_bits_uop_prs2,\n input [5:0] io_core_exe_0_req_bits_uop_prs3,\n input [3:0] io_core_exe_0_req_bits_uop_ppred,\n input io_core_exe_0_req_bits_uop_prs1_busy,\n input io_core_exe_0_req_bits_uop_prs2_busy,\n input io_core_exe_0_req_bits_uop_prs3_busy,\n input io_core_exe_0_req_bits_uop_ppred_busy,\n input [5:0] io_core_exe_0_req_bits_uop_stale_pdst,\n input io_core_exe_0_req_bits_uop_exception,\n input [63:0] io_core_exe_0_req_bits_uop_exc_cause,\n input io_core_exe_0_req_bits_uop_bypassable,\n input [4:0] io_core_exe_0_req_bits_uop_mem_cmd,\n input [1:0] io_core_exe_0_req_bits_uop_mem_size,\n input io_core_exe_0_req_bits_uop_mem_signed,\n input io_core_exe_0_req_bits_uop_is_fence,\n input io_core_exe_0_req_bits_uop_is_fencei,\n input io_core_exe_0_req_bits_uop_is_amo,\n input io_core_exe_0_req_bits_uop_uses_ldq,\n input io_core_exe_0_req_bits_uop_uses_stq,\n input io_core_exe_0_req_bits_uop_is_sys_pc2epc,\n input io_core_exe_0_req_bits_uop_is_unique,\n input io_core_exe_0_req_bits_uop_flush_on_commit,\n input io_core_exe_0_req_bits_uop_ldst_is_rs1,\n input [5:0] io_core_exe_0_req_bits_uop_ldst,\n input [5:0] io_core_exe_0_req_bits_uop_lrs1,\n input [5:0] io_core_exe_0_req_bits_uop_lrs2,\n input [5:0] io_core_exe_0_req_bits_uop_lrs3,\n input io_core_exe_0_req_bits_uop_ldst_val,\n input [1:0] io_core_exe_0_req_bits_uop_dst_rtype,\n input [1:0] io_core_exe_0_req_bits_uop_lrs1_rtype,\n input [1:0] io_core_exe_0_req_bits_uop_lrs2_rtype,\n input io_core_exe_0_req_bits_uop_frs3_en,\n input io_core_exe_0_req_bits_uop_fp_val,\n input io_core_exe_0_req_bits_uop_fp_single,\n input io_core_exe_0_req_bits_uop_xcpt_pf_if,\n input io_core_exe_0_req_bits_uop_xcpt_ae_if,\n input io_core_exe_0_req_bits_uop_xcpt_ma_if,\n input io_core_exe_0_req_bits_uop_bp_debug_if,\n input io_core_exe_0_req_bits_uop_bp_xcpt_if,\n input [1:0] io_core_exe_0_req_bits_uop_debug_fsrc,\n input [1:0] io_core_exe_0_req_bits_uop_debug_tsrc,\n input [63:0] io_core_exe_0_req_bits_data,\n input [39:0] io_core_exe_0_req_bits_addr,\n input io_core_exe_0_req_bits_mxcpt_valid,\n input io_core_exe_0_req_bits_sfence_valid,\n input io_core_exe_0_req_bits_sfence_bits_rs1,\n input io_core_exe_0_req_bits_sfence_bits_rs2,\n input [38:0] io_core_exe_0_req_bits_sfence_bits_addr,\n output io_core_exe_0_iresp_valid,\n output [4:0] io_core_exe_0_iresp_bits_uop_rob_idx,\n output [5:0] io_core_exe_0_iresp_bits_uop_pdst,\n output io_core_exe_0_iresp_bits_uop_is_amo,\n output io_core_exe_0_iresp_bits_uop_uses_stq,\n output [1:0] io_core_exe_0_iresp_bits_uop_dst_rtype,\n output [63:0] io_core_exe_0_iresp_bits_data,\n output io_core_exe_0_fresp_valid,\n output [6:0] io_core_exe_0_fresp_bits_uop_uopc,\n output [7:0] io_core_exe_0_fresp_bits_uop_br_mask,\n output [4:0] io_core_exe_0_fresp_bits_uop_rob_idx,\n output [2:0] io_core_exe_0_fresp_bits_uop_stq_idx,\n output [5:0] io_core_exe_0_fresp_bits_uop_pdst,\n output [1:0] io_core_exe_0_fresp_bits_uop_mem_size,\n output io_core_exe_0_fresp_bits_uop_is_amo,\n output io_core_exe_0_fresp_bits_uop_uses_stq,\n output [1:0] io_core_exe_0_fresp_bits_uop_dst_rtype,\n output io_core_exe_0_fresp_bits_uop_fp_val,\n output [64:0] io_core_exe_0_fresp_bits_data,\n input io_core_dis_uops_0_valid,\n input [6:0] io_core_dis_uops_0_bits_uopc,\n input [31:0] io_core_dis_uops_0_bits_inst,\n input [31:0] io_core_dis_uops_0_bits_debug_inst,\n input io_core_dis_uops_0_bits_is_rvc,\n input [39:0] io_core_dis_uops_0_bits_debug_pc,\n input [2:0] io_core_dis_uops_0_bits_iq_type,\n input [9:0] io_core_dis_uops_0_bits_fu_code,\n input [3:0] io_core_dis_uops_0_bits_ctrl_br_type,\n input [1:0] io_core_dis_uops_0_bits_ctrl_op1_sel,\n input [2:0] io_core_dis_uops_0_bits_ctrl_op2_sel,\n input [2:0] io_core_dis_uops_0_bits_ctrl_imm_sel,\n input [4:0] io_core_dis_uops_0_bits_ctrl_op_fcn,\n input io_core_dis_uops_0_bits_ctrl_fcn_dw,\n input [2:0] io_core_dis_uops_0_bits_ctrl_csr_cmd,\n input io_core_dis_uops_0_bits_ctrl_is_load,\n input io_core_dis_uops_0_bits_ctrl_is_sta,\n input io_core_dis_uops_0_bits_ctrl_is_std,\n input [1:0] io_core_dis_uops_0_bits_iw_state,\n input io_core_dis_uops_0_bits_iw_p1_poisoned,\n input io_core_dis_uops_0_bits_iw_p2_poisoned,\n input io_core_dis_uops_0_bits_is_br,\n input io_core_dis_uops_0_bits_is_jalr,\n input io_core_dis_uops_0_bits_is_jal,\n input io_core_dis_uops_0_bits_is_sfb,\n input [7:0] io_core_dis_uops_0_bits_br_mask,\n input [2:0] io_core_dis_uops_0_bits_br_tag,\n input [3:0] io_core_dis_uops_0_bits_ftq_idx,\n input io_core_dis_uops_0_bits_edge_inst,\n input [5:0] io_core_dis_uops_0_bits_pc_lob,\n input io_core_dis_uops_0_bits_taken,\n input [19:0] io_core_dis_uops_0_bits_imm_packed,\n input [11:0] io_core_dis_uops_0_bits_csr_addr,\n input [4:0] io_core_dis_uops_0_bits_rob_idx,\n input [2:0] io_core_dis_uops_0_bits_ldq_idx,\n input [2:0] io_core_dis_uops_0_bits_stq_idx,\n input [1:0] io_core_dis_uops_0_bits_rxq_idx,\n input [5:0] io_core_dis_uops_0_bits_pdst,\n input [5:0] io_core_dis_uops_0_bits_prs1,\n input [5:0] io_core_dis_uops_0_bits_prs2,\n input [5:0] io_core_dis_uops_0_bits_prs3,\n input io_core_dis_uops_0_bits_prs1_busy,\n input io_core_dis_uops_0_bits_prs2_busy,\n input io_core_dis_uops_0_bits_prs3_busy,\n input [5:0] io_core_dis_uops_0_bits_stale_pdst,\n input io_core_dis_uops_0_bits_exception,\n input [63:0] io_core_dis_uops_0_bits_exc_cause,\n input io_core_dis_uops_0_bits_bypassable,\n input [4:0] io_core_dis_uops_0_bits_mem_cmd,\n input [1:0] io_core_dis_uops_0_bits_mem_size,\n input io_core_dis_uops_0_bits_mem_signed,\n input io_core_dis_uops_0_bits_is_fence,\n input io_core_dis_uops_0_bits_is_fencei,\n input io_core_dis_uops_0_bits_is_amo,\n input io_core_dis_uops_0_bits_uses_ldq,\n input io_core_dis_uops_0_bits_uses_stq,\n input io_core_dis_uops_0_bits_is_sys_pc2epc,\n input io_core_dis_uops_0_bits_is_unique,\n input io_core_dis_uops_0_bits_flush_on_commit,\n input io_core_dis_uops_0_bits_ldst_is_rs1,\n input [5:0] io_core_dis_uops_0_bits_ldst,\n input [5:0] io_core_dis_uops_0_bits_lrs1,\n input [5:0] io_core_dis_uops_0_bits_lrs2,\n input [5:0] io_core_dis_uops_0_bits_lrs3,\n input io_core_dis_uops_0_bits_ldst_val,\n input [1:0] io_core_dis_uops_0_bits_dst_rtype,\n input [1:0] io_core_dis_uops_0_bits_lrs1_rtype,\n input [1:0] io_core_dis_uops_0_bits_lrs2_rtype,\n input io_core_dis_uops_0_bits_frs3_en,\n input io_core_dis_uops_0_bits_fp_val,\n input io_core_dis_uops_0_bits_fp_single,\n input io_core_dis_uops_0_bits_xcpt_pf_if,\n input io_core_dis_uops_0_bits_xcpt_ae_if,\n input io_core_dis_uops_0_bits_xcpt_ma_if,\n input io_core_dis_uops_0_bits_bp_debug_if,\n input io_core_dis_uops_0_bits_bp_xcpt_if,\n input [1:0] io_core_dis_uops_0_bits_debug_fsrc,\n input [1:0] io_core_dis_uops_0_bits_debug_tsrc,\n output [2:0] io_core_dis_ldq_idx_0,\n output [2:0] io_core_dis_stq_idx_0,\n output io_core_ldq_full_0,\n output io_core_stq_full_0,\n output io_core_fp_stdata_ready,\n input io_core_fp_stdata_valid,\n input [7:0] io_core_fp_stdata_bits_uop_br_mask,\n input [4:0] io_core_fp_stdata_bits_uop_rob_idx,\n input [2:0] io_core_fp_stdata_bits_uop_stq_idx,\n input [63:0] io_core_fp_stdata_bits_data,\n input io_core_commit_valids_0,\n input io_core_commit_uops_0_uses_ldq,\n input io_core_commit_uops_0_uses_stq,\n input io_core_commit_load_at_rob_head,\n output io_core_clr_bsy_0_valid,\n output [4:0] io_core_clr_bsy_0_bits,\n output io_core_clr_bsy_1_valid,\n output [4:0] io_core_clr_bsy_1_bits,\n input io_core_fence_dmem,\n output io_core_spec_ld_wakeup_0_valid,\n output [5:0] io_core_spec_ld_wakeup_0_bits,\n output io_core_ld_miss,\n input [7:0] io_core_brupdate_b1_resolve_mask,\n input [7:0] io_core_brupdate_b1_mispredict_mask,\n input [2:0] io_core_brupdate_b2_uop_ldq_idx,\n input [2:0] io_core_brupdate_b2_uop_stq_idx,\n input io_core_brupdate_b2_mispredict,\n input [4:0] io_core_rob_head_idx,\n input io_core_exception,\n output io_core_fencei_rdy,\n output io_core_lxcpt_valid,\n output [7:0] io_core_lxcpt_bits_uop_br_mask,\n output [4:0] io_core_lxcpt_bits_uop_rob_idx,\n output [4:0] io_core_lxcpt_bits_cause,\n output [39:0] io_core_lxcpt_bits_badvaddr,\n output io_core_perf_acquire,\n output io_core_perf_release,\n output io_core_perf_tlbMiss,\n input io_dmem_req_ready,\n output io_dmem_req_valid,\n output io_dmem_req_bits_0_valid,\n output [6:0] io_dmem_req_bits_0_bits_uop_uopc,\n output [31:0] io_dmem_req_bits_0_bits_uop_inst,\n output [31:0] io_dmem_req_bits_0_bits_uop_debug_inst,\n output io_dmem_req_bits_0_bits_uop_is_rvc,\n output [39:0] io_dmem_req_bits_0_bits_uop_debug_pc,\n output [2:0] io_dmem_req_bits_0_bits_uop_iq_type,\n output [9:0] io_dmem_req_bits_0_bits_uop_fu_code,\n output [3:0] io_dmem_req_bits_0_bits_uop_ctrl_br_type,\n output [1:0] io_dmem_req_bits_0_bits_uop_ctrl_op1_sel,\n output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_op2_sel,\n output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_imm_sel,\n output [4:0] io_dmem_req_bits_0_bits_uop_ctrl_op_fcn,\n output io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw,\n output [2:0] io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd,\n output io_dmem_req_bits_0_bits_uop_ctrl_is_load,\n output io_dmem_req_bits_0_bits_uop_ctrl_is_sta,\n output io_dmem_req_bits_0_bits_uop_ctrl_is_std,\n output [1:0] io_dmem_req_bits_0_bits_uop_iw_state,\n output io_dmem_req_bits_0_bits_uop_iw_p1_poisoned,\n output io_dmem_req_bits_0_bits_uop_iw_p2_poisoned,\n output io_dmem_req_bits_0_bits_uop_is_br,\n output io_dmem_req_bits_0_bits_uop_is_jalr,\n output io_dmem_req_bits_0_bits_uop_is_jal,\n output io_dmem_req_bits_0_bits_uop_is_sfb,\n output [7:0] io_dmem_req_bits_0_bits_uop_br_mask,\n output [2:0] io_dmem_req_bits_0_bits_uop_br_tag,\n output [3:0] io_dmem_req_bits_0_bits_uop_ftq_idx,\n output io_dmem_req_bits_0_bits_uop_edge_inst,\n output [5:0] io_dmem_req_bits_0_bits_uop_pc_lob,\n output io_dmem_req_bits_0_bits_uop_taken,\n output [19:0] io_dmem_req_bits_0_bits_uop_imm_packed,\n output [11:0] io_dmem_req_bits_0_bits_uop_csr_addr,\n output [4:0] io_dmem_req_bits_0_bits_uop_rob_idx,\n output [2:0] io_dmem_req_bits_0_bits_uop_ldq_idx,\n output [2:0] io_dmem_req_bits_0_bits_uop_stq_idx,\n output [1:0] io_dmem_req_bits_0_bits_uop_rxq_idx,\n output [5:0] io_dmem_req_bits_0_bits_uop_pdst,\n output [5:0] io_dmem_req_bits_0_bits_uop_prs1,\n output [5:0] io_dmem_req_bits_0_bits_uop_prs2,\n output [5:0] io_dmem_req_bits_0_bits_uop_prs3,\n output [3:0] io_dmem_req_bits_0_bits_uop_ppred,\n output io_dmem_req_bits_0_bits_uop_prs1_busy,\n output io_dmem_req_bits_0_bits_uop_prs2_busy,\n output io_dmem_req_bits_0_bits_uop_prs3_busy,\n output io_dmem_req_bits_0_bits_uop_ppred_busy,\n output [5:0] io_dmem_req_bits_0_bits_uop_stale_pdst,\n output io_dmem_req_bits_0_bits_uop_exception,\n output [63:0] io_dmem_req_bits_0_bits_uop_exc_cause,\n output io_dmem_req_bits_0_bits_uop_bypassable,\n output [4:0] io_dmem_req_bits_0_bits_uop_mem_cmd,\n output [1:0] io_dmem_req_bits_0_bits_uop_mem_size,\n output io_dmem_req_bits_0_bits_uop_mem_signed,\n output io_dmem_req_bits_0_bits_uop_is_fence,\n output io_dmem_req_bits_0_bits_uop_is_fencei,\n output io_dmem_req_bits_0_bits_uop_is_amo,\n output io_dmem_req_bits_0_bits_uop_uses_ldq,\n output io_dmem_req_bits_0_bits_uop_uses_stq,\n output io_dmem_req_bits_0_bits_uop_is_sys_pc2epc,\n output io_dmem_req_bits_0_bits_uop_is_unique,\n output io_dmem_req_bits_0_bits_uop_flush_on_commit,\n output io_dmem_req_bits_0_bits_uop_ldst_is_rs1,\n output [5:0] io_dmem_req_bits_0_bits_uop_ldst,\n output [5:0] io_dmem_req_bits_0_bits_uop_lrs1,\n output [5:0] io_dmem_req_bits_0_bits_uop_lrs2,\n output [5:0] io_dmem_req_bits_0_bits_uop_lrs3,\n output io_dmem_req_bits_0_bits_uop_ldst_val,\n output [1:0] io_dmem_req_bits_0_bits_uop_dst_rtype,\n output [1:0] io_dmem_req_bits_0_bits_uop_lrs1_rtype,\n output [1:0] io_dmem_req_bits_0_bits_uop_lrs2_rtype,\n output io_dmem_req_bits_0_bits_uop_frs3_en,\n output io_dmem_req_bits_0_bits_uop_fp_val,\n output io_dmem_req_bits_0_bits_uop_fp_single,\n output io_dmem_req_bits_0_bits_uop_xcpt_pf_if,\n output io_dmem_req_bits_0_bits_uop_xcpt_ae_if,\n output io_dmem_req_bits_0_bits_uop_xcpt_ma_if,\n output io_dmem_req_bits_0_bits_uop_bp_debug_if,\n output io_dmem_req_bits_0_bits_uop_bp_xcpt_if,\n output [1:0] io_dmem_req_bits_0_bits_uop_debug_fsrc,\n output [1:0] io_dmem_req_bits_0_bits_uop_debug_tsrc,\n output [39:0] io_dmem_req_bits_0_bits_addr,\n output [63:0] io_dmem_req_bits_0_bits_data,\n output io_dmem_req_bits_0_bits_is_hella,\n output io_dmem_s1_kill_0,\n input io_dmem_resp_0_valid,\n input [2:0] io_dmem_resp_0_bits_uop_ldq_idx,\n input [2:0] io_dmem_resp_0_bits_uop_stq_idx,\n input io_dmem_resp_0_bits_uop_is_amo,\n input io_dmem_resp_0_bits_uop_uses_ldq,\n input io_dmem_resp_0_bits_uop_uses_stq,\n input [63:0] io_dmem_resp_0_bits_data,\n input io_dmem_resp_0_bits_is_hella,\n input io_dmem_nack_0_valid,\n input [2:0] io_dmem_nack_0_bits_uop_ldq_idx,\n input [2:0] io_dmem_nack_0_bits_uop_stq_idx,\n input io_dmem_nack_0_bits_uop_uses_ldq,\n input io_dmem_nack_0_bits_uop_uses_stq,\n input io_dmem_nack_0_bits_is_hella,\n output [7:0] io_dmem_brupdate_b1_resolve_mask,\n output [7:0] io_dmem_brupdate_b1_mispredict_mask,\n output io_dmem_exception,\n output io_dmem_release_ready,\n input io_dmem_release_valid,\n input [31:0] io_dmem_release_bits_address,\n output io_dmem_force_order,\n input io_dmem_ordered,\n input io_dmem_perf_acquire,\n input io_dmem_perf_release,\n output io_hellacache_req_ready,\n input io_hellacache_req_valid,\n input [39:0] io_hellacache_req_bits_addr,\n input io_hellacache_s1_kill,\n output io_hellacache_s2_nack,\n output io_hellacache_resp_valid,\n output [63:0] io_hellacache_resp_bits_data,\n output io_hellacache_s2_xcpt_ae_ld\n);\n\n wire _GEN;\n wire _GEN_0;\n wire store_needs_order;\n wire nacking_loads_7;\n wire nacking_loads_6;\n wire nacking_loads_5;\n wire nacking_loads_4;\n wire nacking_loads_3;\n wire nacking_loads_2;\n wire nacking_loads_1;\n wire nacking_loads_0;\n wire block_load_wakeup;\n wire _GEN_1;\n wire _GEN_2;\n reg mem_xcpt_valids_0;\n wire _will_fire_store_commit_0_T_2;\n wire [2:0] _forwarding_age_logic_0_io_forwarding_idx;\n wire _dtlb_io_miss_rdy;\n wire _dtlb_io_resp_0_miss;\n wire [31:0] _dtlb_io_resp_0_paddr;\n wire _dtlb_io_resp_0_pf_ld;\n wire _dtlb_io_resp_0_pf_st;\n wire _dtlb_io_resp_0_ae_ld;\n wire _dtlb_io_resp_0_ae_st;\n wire _dtlb_io_resp_0_ma_ld;\n wire _dtlb_io_resp_0_ma_st;\n wire _dtlb_io_resp_0_cacheable;\n wire _dtlb_io_ptw_req_valid;\n reg ldq_0_valid;\n reg [6:0] ldq_0_bits_uop_uopc;\n reg [31:0] ldq_0_bits_uop_inst;\n reg [31:0] ldq_0_bits_uop_debug_inst;\n reg ldq_0_bits_uop_is_rvc;\n reg [39:0] ldq_0_bits_uop_debug_pc;\n reg [2:0] ldq_0_bits_uop_iq_type;\n reg [9:0] ldq_0_bits_uop_fu_code;\n reg [3:0] ldq_0_bits_uop_ctrl_br_type;\n reg [1:0] ldq_0_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_0_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_0_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_0_bits_uop_ctrl_op_fcn;\n reg ldq_0_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_0_bits_uop_ctrl_csr_cmd;\n reg ldq_0_bits_uop_ctrl_is_load;\n reg ldq_0_bits_uop_ctrl_is_sta;\n reg ldq_0_bits_uop_ctrl_is_std;\n reg [1:0] ldq_0_bits_uop_iw_state;\n reg ldq_0_bits_uop_iw_p1_poisoned;\n reg ldq_0_bits_uop_iw_p2_poisoned;\n reg ldq_0_bits_uop_is_br;\n reg ldq_0_bits_uop_is_jalr;\n reg ldq_0_bits_uop_is_jal;\n reg ldq_0_bits_uop_is_sfb;\n reg [7:0] ldq_0_bits_uop_br_mask;\n reg [2:0] ldq_0_bits_uop_br_tag;\n reg [3:0] ldq_0_bits_uop_ftq_idx;\n reg ldq_0_bits_uop_edge_inst;\n reg [5:0] ldq_0_bits_uop_pc_lob;\n reg ldq_0_bits_uop_taken;\n reg [19:0] ldq_0_bits_uop_imm_packed;\n reg [11:0] ldq_0_bits_uop_csr_addr;\n reg [4:0] ldq_0_bits_uop_rob_idx;\n reg [2:0] ldq_0_bits_uop_ldq_idx;\n reg [2:0] ldq_0_bits_uop_stq_idx;\n reg [1:0] ldq_0_bits_uop_rxq_idx;\n reg [5:0] ldq_0_bits_uop_pdst;\n reg [5:0] ldq_0_bits_uop_prs1;\n reg [5:0] ldq_0_bits_uop_prs2;\n reg [5:0] ldq_0_bits_uop_prs3;\n reg ldq_0_bits_uop_prs1_busy;\n reg ldq_0_bits_uop_prs2_busy;\n reg ldq_0_bits_uop_prs3_busy;\n reg [5:0] ldq_0_bits_uop_stale_pdst;\n reg ldq_0_bits_uop_exception;\n reg [63:0] ldq_0_bits_uop_exc_cause;\n reg ldq_0_bits_uop_bypassable;\n reg [4:0] ldq_0_bits_uop_mem_cmd;\n reg [1:0] ldq_0_bits_uop_mem_size;\n reg ldq_0_bits_uop_mem_signed;\n reg ldq_0_bits_uop_is_fence;\n reg ldq_0_bits_uop_is_fencei;\n reg ldq_0_bits_uop_is_amo;\n reg ldq_0_bits_uop_uses_ldq;\n reg ldq_0_bits_uop_uses_stq;\n reg ldq_0_bits_uop_is_sys_pc2epc;\n reg ldq_0_bits_uop_is_unique;\n reg ldq_0_bits_uop_flush_on_commit;\n reg ldq_0_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_0_bits_uop_ldst;\n reg [5:0] ldq_0_bits_uop_lrs1;\n reg [5:0] ldq_0_bits_uop_lrs2;\n reg [5:0] ldq_0_bits_uop_lrs3;\n reg ldq_0_bits_uop_ldst_val;\n reg [1:0] ldq_0_bits_uop_dst_rtype;\n reg [1:0] ldq_0_bits_uop_lrs1_rtype;\n reg [1:0] ldq_0_bits_uop_lrs2_rtype;\n reg ldq_0_bits_uop_frs3_en;\n reg ldq_0_bits_uop_fp_val;\n reg ldq_0_bits_uop_fp_single;\n reg ldq_0_bits_uop_xcpt_pf_if;\n reg ldq_0_bits_uop_xcpt_ae_if;\n reg ldq_0_bits_uop_xcpt_ma_if;\n reg ldq_0_bits_uop_bp_debug_if;\n reg ldq_0_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_0_bits_uop_debug_fsrc;\n reg [1:0] ldq_0_bits_uop_debug_tsrc;\n reg ldq_0_bits_addr_valid;\n reg [39:0] ldq_0_bits_addr_bits;\n reg ldq_0_bits_addr_is_virtual;\n reg ldq_0_bits_addr_is_uncacheable;\n reg ldq_0_bits_executed;\n reg ldq_0_bits_succeeded;\n reg ldq_0_bits_order_fail;\n reg ldq_0_bits_observed;\n reg [7:0] ldq_0_bits_st_dep_mask;\n reg [2:0] ldq_0_bits_youngest_stq_idx;\n reg ldq_0_bits_forward_std_val;\n reg [2:0] ldq_0_bits_forward_stq_idx;\n reg ldq_1_valid;\n reg [6:0] ldq_1_bits_uop_uopc;\n reg [31:0] ldq_1_bits_uop_inst;\n reg [31:0] ldq_1_bits_uop_debug_inst;\n reg ldq_1_bits_uop_is_rvc;\n reg [39:0] ldq_1_bits_uop_debug_pc;\n reg [2:0] ldq_1_bits_uop_iq_type;\n reg [9:0] ldq_1_bits_uop_fu_code;\n reg [3:0] ldq_1_bits_uop_ctrl_br_type;\n reg [1:0] ldq_1_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_1_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_1_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_1_bits_uop_ctrl_op_fcn;\n reg ldq_1_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_1_bits_uop_ctrl_csr_cmd;\n reg ldq_1_bits_uop_ctrl_is_load;\n reg ldq_1_bits_uop_ctrl_is_sta;\n reg ldq_1_bits_uop_ctrl_is_std;\n reg [1:0] ldq_1_bits_uop_iw_state;\n reg ldq_1_bits_uop_iw_p1_poisoned;\n reg ldq_1_bits_uop_iw_p2_poisoned;\n reg ldq_1_bits_uop_is_br;\n reg ldq_1_bits_uop_is_jalr;\n reg ldq_1_bits_uop_is_jal;\n reg ldq_1_bits_uop_is_sfb;\n reg [7:0] ldq_1_bits_uop_br_mask;\n reg [2:0] ldq_1_bits_uop_br_tag;\n reg [3:0] ldq_1_bits_uop_ftq_idx;\n reg ldq_1_bits_uop_edge_inst;\n reg [5:0] ldq_1_bits_uop_pc_lob;\n reg ldq_1_bits_uop_taken;\n reg [19:0] ldq_1_bits_uop_imm_packed;\n reg [11:0] ldq_1_bits_uop_csr_addr;\n reg [4:0] ldq_1_bits_uop_rob_idx;\n reg [2:0] ldq_1_bits_uop_ldq_idx;\n reg [2:0] ldq_1_bits_uop_stq_idx;\n reg [1:0] ldq_1_bits_uop_rxq_idx;\n reg [5:0] ldq_1_bits_uop_pdst;\n reg [5:0] ldq_1_bits_uop_prs1;\n reg [5:0] ldq_1_bits_uop_prs2;\n reg [5:0] ldq_1_bits_uop_prs3;\n reg ldq_1_bits_uop_prs1_busy;\n reg ldq_1_bits_uop_prs2_busy;\n reg ldq_1_bits_uop_prs3_busy;\n reg [5:0] ldq_1_bits_uop_stale_pdst;\n reg ldq_1_bits_uop_exception;\n reg [63:0] ldq_1_bits_uop_exc_cause;\n reg ldq_1_bits_uop_bypassable;\n reg [4:0] ldq_1_bits_uop_mem_cmd;\n reg [1:0] ldq_1_bits_uop_mem_size;\n reg ldq_1_bits_uop_mem_signed;\n reg ldq_1_bits_uop_is_fence;\n reg ldq_1_bits_uop_is_fencei;\n reg ldq_1_bits_uop_is_amo;\n reg ldq_1_bits_uop_uses_ldq;\n reg ldq_1_bits_uop_uses_stq;\n reg ldq_1_bits_uop_is_sys_pc2epc;\n reg ldq_1_bits_uop_is_unique;\n reg ldq_1_bits_uop_flush_on_commit;\n reg ldq_1_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_1_bits_uop_ldst;\n reg [5:0] ldq_1_bits_uop_lrs1;\n reg [5:0] ldq_1_bits_uop_lrs2;\n reg [5:0] ldq_1_bits_uop_lrs3;\n reg ldq_1_bits_uop_ldst_val;\n reg [1:0] ldq_1_bits_uop_dst_rtype;\n reg [1:0] ldq_1_bits_uop_lrs1_rtype;\n reg [1:0] ldq_1_bits_uop_lrs2_rtype;\n reg ldq_1_bits_uop_frs3_en;\n reg ldq_1_bits_uop_fp_val;\n reg ldq_1_bits_uop_fp_single;\n reg ldq_1_bits_uop_xcpt_pf_if;\n reg ldq_1_bits_uop_xcpt_ae_if;\n reg ldq_1_bits_uop_xcpt_ma_if;\n reg ldq_1_bits_uop_bp_debug_if;\n reg ldq_1_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_1_bits_uop_debug_fsrc;\n reg [1:0] ldq_1_bits_uop_debug_tsrc;\n reg ldq_1_bits_addr_valid;\n reg [39:0] ldq_1_bits_addr_bits;\n reg ldq_1_bits_addr_is_virtual;\n reg ldq_1_bits_addr_is_uncacheable;\n reg ldq_1_bits_executed;\n reg ldq_1_bits_succeeded;\n reg ldq_1_bits_order_fail;\n reg ldq_1_bits_observed;\n reg [7:0] ldq_1_bits_st_dep_mask;\n reg [2:0] ldq_1_bits_youngest_stq_idx;\n reg ldq_1_bits_forward_std_val;\n reg [2:0] ldq_1_bits_forward_stq_idx;\n reg ldq_2_valid;\n reg [6:0] ldq_2_bits_uop_uopc;\n reg [31:0] ldq_2_bits_uop_inst;\n reg [31:0] ldq_2_bits_uop_debug_inst;\n reg ldq_2_bits_uop_is_rvc;\n reg [39:0] ldq_2_bits_uop_debug_pc;\n reg [2:0] ldq_2_bits_uop_iq_type;\n reg [9:0] ldq_2_bits_uop_fu_code;\n reg [3:0] ldq_2_bits_uop_ctrl_br_type;\n reg [1:0] ldq_2_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_2_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_2_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_2_bits_uop_ctrl_op_fcn;\n reg ldq_2_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_2_bits_uop_ctrl_csr_cmd;\n reg ldq_2_bits_uop_ctrl_is_load;\n reg ldq_2_bits_uop_ctrl_is_sta;\n reg ldq_2_bits_uop_ctrl_is_std;\n reg [1:0] ldq_2_bits_uop_iw_state;\n reg ldq_2_bits_uop_iw_p1_poisoned;\n reg ldq_2_bits_uop_iw_p2_poisoned;\n reg ldq_2_bits_uop_is_br;\n reg ldq_2_bits_uop_is_jalr;\n reg ldq_2_bits_uop_is_jal;\n reg ldq_2_bits_uop_is_sfb;\n reg [7:0] ldq_2_bits_uop_br_mask;\n reg [2:0] ldq_2_bits_uop_br_tag;\n reg [3:0] ldq_2_bits_uop_ftq_idx;\n reg ldq_2_bits_uop_edge_inst;\n reg [5:0] ldq_2_bits_uop_pc_lob;\n reg ldq_2_bits_uop_taken;\n reg [19:0] ldq_2_bits_uop_imm_packed;\n reg [11:0] ldq_2_bits_uop_csr_addr;\n reg [4:0] ldq_2_bits_uop_rob_idx;\n reg [2:0] ldq_2_bits_uop_ldq_idx;\n reg [2:0] ldq_2_bits_uop_stq_idx;\n reg [1:0] ldq_2_bits_uop_rxq_idx;\n reg [5:0] ldq_2_bits_uop_pdst;\n reg [5:0] ldq_2_bits_uop_prs1;\n reg [5:0] ldq_2_bits_uop_prs2;\n reg [5:0] ldq_2_bits_uop_prs3;\n reg ldq_2_bits_uop_prs1_busy;\n reg ldq_2_bits_uop_prs2_busy;\n reg ldq_2_bits_uop_prs3_busy;\n reg [5:0] ldq_2_bits_uop_stale_pdst;\n reg ldq_2_bits_uop_exception;\n reg [63:0] ldq_2_bits_uop_exc_cause;\n reg ldq_2_bits_uop_bypassable;\n reg [4:0] ldq_2_bits_uop_mem_cmd;\n reg [1:0] ldq_2_bits_uop_mem_size;\n reg ldq_2_bits_uop_mem_signed;\n reg ldq_2_bits_uop_is_fence;\n reg ldq_2_bits_uop_is_fencei;\n reg ldq_2_bits_uop_is_amo;\n reg ldq_2_bits_uop_uses_ldq;\n reg ldq_2_bits_uop_uses_stq;\n reg ldq_2_bits_uop_is_sys_pc2epc;\n reg ldq_2_bits_uop_is_unique;\n reg ldq_2_bits_uop_flush_on_commit;\n reg ldq_2_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_2_bits_uop_ldst;\n reg [5:0] ldq_2_bits_uop_lrs1;\n reg [5:0] ldq_2_bits_uop_lrs2;\n reg [5:0] ldq_2_bits_uop_lrs3;\n reg ldq_2_bits_uop_ldst_val;\n reg [1:0] ldq_2_bits_uop_dst_rtype;\n reg [1:0] ldq_2_bits_uop_lrs1_rtype;\n reg [1:0] ldq_2_bits_uop_lrs2_rtype;\n reg ldq_2_bits_uop_frs3_en;\n reg ldq_2_bits_uop_fp_val;\n reg ldq_2_bits_uop_fp_single;\n reg ldq_2_bits_uop_xcpt_pf_if;\n reg ldq_2_bits_uop_xcpt_ae_if;\n reg ldq_2_bits_uop_xcpt_ma_if;\n reg ldq_2_bits_uop_bp_debug_if;\n reg ldq_2_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_2_bits_uop_debug_fsrc;\n reg [1:0] ldq_2_bits_uop_debug_tsrc;\n reg ldq_2_bits_addr_valid;\n reg [39:0] ldq_2_bits_addr_bits;\n reg ldq_2_bits_addr_is_virtual;\n reg ldq_2_bits_addr_is_uncacheable;\n reg ldq_2_bits_executed;\n reg ldq_2_bits_succeeded;\n reg ldq_2_bits_order_fail;\n reg ldq_2_bits_observed;\n reg [7:0] ldq_2_bits_st_dep_mask;\n reg [2:0] ldq_2_bits_youngest_stq_idx;\n reg ldq_2_bits_forward_std_val;\n reg [2:0] ldq_2_bits_forward_stq_idx;\n reg ldq_3_valid;\n reg [6:0] ldq_3_bits_uop_uopc;\n reg [31:0] ldq_3_bits_uop_inst;\n reg [31:0] ldq_3_bits_uop_debug_inst;\n reg ldq_3_bits_uop_is_rvc;\n reg [39:0] ldq_3_bits_uop_debug_pc;\n reg [2:0] ldq_3_bits_uop_iq_type;\n reg [9:0] ldq_3_bits_uop_fu_code;\n reg [3:0] ldq_3_bits_uop_ctrl_br_type;\n reg [1:0] ldq_3_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_3_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_3_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_3_bits_uop_ctrl_op_fcn;\n reg ldq_3_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_3_bits_uop_ctrl_csr_cmd;\n reg ldq_3_bits_uop_ctrl_is_load;\n reg ldq_3_bits_uop_ctrl_is_sta;\n reg ldq_3_bits_uop_ctrl_is_std;\n reg [1:0] ldq_3_bits_uop_iw_state;\n reg ldq_3_bits_uop_iw_p1_poisoned;\n reg ldq_3_bits_uop_iw_p2_poisoned;\n reg ldq_3_bits_uop_is_br;\n reg ldq_3_bits_uop_is_jalr;\n reg ldq_3_bits_uop_is_jal;\n reg ldq_3_bits_uop_is_sfb;\n reg [7:0] ldq_3_bits_uop_br_mask;\n reg [2:0] ldq_3_bits_uop_br_tag;\n reg [3:0] ldq_3_bits_uop_ftq_idx;\n reg ldq_3_bits_uop_edge_inst;\n reg [5:0] ldq_3_bits_uop_pc_lob;\n reg ldq_3_bits_uop_taken;\n reg [19:0] ldq_3_bits_uop_imm_packed;\n reg [11:0] ldq_3_bits_uop_csr_addr;\n reg [4:0] ldq_3_bits_uop_rob_idx;\n reg [2:0] ldq_3_bits_uop_ldq_idx;\n reg [2:0] ldq_3_bits_uop_stq_idx;\n reg [1:0] ldq_3_bits_uop_rxq_idx;\n reg [5:0] ldq_3_bits_uop_pdst;\n reg [5:0] ldq_3_bits_uop_prs1;\n reg [5:0] ldq_3_bits_uop_prs2;\n reg [5:0] ldq_3_bits_uop_prs3;\n reg ldq_3_bits_uop_prs1_busy;\n reg ldq_3_bits_uop_prs2_busy;\n reg ldq_3_bits_uop_prs3_busy;\n reg [5:0] ldq_3_bits_uop_stale_pdst;\n reg ldq_3_bits_uop_exception;\n reg [63:0] ldq_3_bits_uop_exc_cause;\n reg ldq_3_bits_uop_bypassable;\n reg [4:0] ldq_3_bits_uop_mem_cmd;\n reg [1:0] ldq_3_bits_uop_mem_size;\n reg ldq_3_bits_uop_mem_signed;\n reg ldq_3_bits_uop_is_fence;\n reg ldq_3_bits_uop_is_fencei;\n reg ldq_3_bits_uop_is_amo;\n reg ldq_3_bits_uop_uses_ldq;\n reg ldq_3_bits_uop_uses_stq;\n reg ldq_3_bits_uop_is_sys_pc2epc;\n reg ldq_3_bits_uop_is_unique;\n reg ldq_3_bits_uop_flush_on_commit;\n reg ldq_3_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_3_bits_uop_ldst;\n reg [5:0] ldq_3_bits_uop_lrs1;\n reg [5:0] ldq_3_bits_uop_lrs2;\n reg [5:0] ldq_3_bits_uop_lrs3;\n reg ldq_3_bits_uop_ldst_val;\n reg [1:0] ldq_3_bits_uop_dst_rtype;\n reg [1:0] ldq_3_bits_uop_lrs1_rtype;\n reg [1:0] ldq_3_bits_uop_lrs2_rtype;\n reg ldq_3_bits_uop_frs3_en;\n reg ldq_3_bits_uop_fp_val;\n reg ldq_3_bits_uop_fp_single;\n reg ldq_3_bits_uop_xcpt_pf_if;\n reg ldq_3_bits_uop_xcpt_ae_if;\n reg ldq_3_bits_uop_xcpt_ma_if;\n reg ldq_3_bits_uop_bp_debug_if;\n reg ldq_3_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_3_bits_uop_debug_fsrc;\n reg [1:0] ldq_3_bits_uop_debug_tsrc;\n reg ldq_3_bits_addr_valid;\n reg [39:0] ldq_3_bits_addr_bits;\n reg ldq_3_bits_addr_is_virtual;\n reg ldq_3_bits_addr_is_uncacheable;\n reg ldq_3_bits_executed;\n reg ldq_3_bits_succeeded;\n reg ldq_3_bits_order_fail;\n reg ldq_3_bits_observed;\n reg [7:0] ldq_3_bits_st_dep_mask;\n reg [2:0] ldq_3_bits_youngest_stq_idx;\n reg ldq_3_bits_forward_std_val;\n reg [2:0] ldq_3_bits_forward_stq_idx;\n reg ldq_4_valid;\n reg [6:0] ldq_4_bits_uop_uopc;\n reg [31:0] ldq_4_bits_uop_inst;\n reg [31:0] ldq_4_bits_uop_debug_inst;\n reg ldq_4_bits_uop_is_rvc;\n reg [39:0] ldq_4_bits_uop_debug_pc;\n reg [2:0] ldq_4_bits_uop_iq_type;\n reg [9:0] ldq_4_bits_uop_fu_code;\n reg [3:0] ldq_4_bits_uop_ctrl_br_type;\n reg [1:0] ldq_4_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_4_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_4_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_4_bits_uop_ctrl_op_fcn;\n reg ldq_4_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_4_bits_uop_ctrl_csr_cmd;\n reg ldq_4_bits_uop_ctrl_is_load;\n reg ldq_4_bits_uop_ctrl_is_sta;\n reg ldq_4_bits_uop_ctrl_is_std;\n reg [1:0] ldq_4_bits_uop_iw_state;\n reg ldq_4_bits_uop_iw_p1_poisoned;\n reg ldq_4_bits_uop_iw_p2_poisoned;\n reg ldq_4_bits_uop_is_br;\n reg ldq_4_bits_uop_is_jalr;\n reg ldq_4_bits_uop_is_jal;\n reg ldq_4_bits_uop_is_sfb;\n reg [7:0] ldq_4_bits_uop_br_mask;\n reg [2:0] ldq_4_bits_uop_br_tag;\n reg [3:0] ldq_4_bits_uop_ftq_idx;\n reg ldq_4_bits_uop_edge_inst;\n reg [5:0] ldq_4_bits_uop_pc_lob;\n reg ldq_4_bits_uop_taken;\n reg [19:0] ldq_4_bits_uop_imm_packed;\n reg [11:0] ldq_4_bits_uop_csr_addr;\n reg [4:0] ldq_4_bits_uop_rob_idx;\n reg [2:0] ldq_4_bits_uop_ldq_idx;\n reg [2:0] ldq_4_bits_uop_stq_idx;\n reg [1:0] ldq_4_bits_uop_rxq_idx;\n reg [5:0] ldq_4_bits_uop_pdst;\n reg [5:0] ldq_4_bits_uop_prs1;\n reg [5:0] ldq_4_bits_uop_prs2;\n reg [5:0] ldq_4_bits_uop_prs3;\n reg ldq_4_bits_uop_prs1_busy;\n reg ldq_4_bits_uop_prs2_busy;\n reg ldq_4_bits_uop_prs3_busy;\n reg [5:0] ldq_4_bits_uop_stale_pdst;\n reg ldq_4_bits_uop_exception;\n reg [63:0] ldq_4_bits_uop_exc_cause;\n reg ldq_4_bits_uop_bypassable;\n reg [4:0] ldq_4_bits_uop_mem_cmd;\n reg [1:0] ldq_4_bits_uop_mem_size;\n reg ldq_4_bits_uop_mem_signed;\n reg ldq_4_bits_uop_is_fence;\n reg ldq_4_bits_uop_is_fencei;\n reg ldq_4_bits_uop_is_amo;\n reg ldq_4_bits_uop_uses_ldq;\n reg ldq_4_bits_uop_uses_stq;\n reg ldq_4_bits_uop_is_sys_pc2epc;\n reg ldq_4_bits_uop_is_unique;\n reg ldq_4_bits_uop_flush_on_commit;\n reg ldq_4_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_4_bits_uop_ldst;\n reg [5:0] ldq_4_bits_uop_lrs1;\n reg [5:0] ldq_4_bits_uop_lrs2;\n reg [5:0] ldq_4_bits_uop_lrs3;\n reg ldq_4_bits_uop_ldst_val;\n reg [1:0] ldq_4_bits_uop_dst_rtype;\n reg [1:0] ldq_4_bits_uop_lrs1_rtype;\n reg [1:0] ldq_4_bits_uop_lrs2_rtype;\n reg ldq_4_bits_uop_frs3_en;\n reg ldq_4_bits_uop_fp_val;\n reg ldq_4_bits_uop_fp_single;\n reg ldq_4_bits_uop_xcpt_pf_if;\n reg ldq_4_bits_uop_xcpt_ae_if;\n reg ldq_4_bits_uop_xcpt_ma_if;\n reg ldq_4_bits_uop_bp_debug_if;\n reg ldq_4_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_4_bits_uop_debug_fsrc;\n reg [1:0] ldq_4_bits_uop_debug_tsrc;\n reg ldq_4_bits_addr_valid;\n reg [39:0] ldq_4_bits_addr_bits;\n reg ldq_4_bits_addr_is_virtual;\n reg ldq_4_bits_addr_is_uncacheable;\n reg ldq_4_bits_executed;\n reg ldq_4_bits_succeeded;\n reg ldq_4_bits_order_fail;\n reg ldq_4_bits_observed;\n reg [7:0] ldq_4_bits_st_dep_mask;\n reg [2:0] ldq_4_bits_youngest_stq_idx;\n reg ldq_4_bits_forward_std_val;\n reg [2:0] ldq_4_bits_forward_stq_idx;\n reg ldq_5_valid;\n reg [6:0] ldq_5_bits_uop_uopc;\n reg [31:0] ldq_5_bits_uop_inst;\n reg [31:0] ldq_5_bits_uop_debug_inst;\n reg ldq_5_bits_uop_is_rvc;\n reg [39:0] ldq_5_bits_uop_debug_pc;\n reg [2:0] ldq_5_bits_uop_iq_type;\n reg [9:0] ldq_5_bits_uop_fu_code;\n reg [3:0] ldq_5_bits_uop_ctrl_br_type;\n reg [1:0] ldq_5_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_5_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_5_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_5_bits_uop_ctrl_op_fcn;\n reg ldq_5_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_5_bits_uop_ctrl_csr_cmd;\n reg ldq_5_bits_uop_ctrl_is_load;\n reg ldq_5_bits_uop_ctrl_is_sta;\n reg ldq_5_bits_uop_ctrl_is_std;\n reg [1:0] ldq_5_bits_uop_iw_state;\n reg ldq_5_bits_uop_iw_p1_poisoned;\n reg ldq_5_bits_uop_iw_p2_poisoned;\n reg ldq_5_bits_uop_is_br;\n reg ldq_5_bits_uop_is_jalr;\n reg ldq_5_bits_uop_is_jal;\n reg ldq_5_bits_uop_is_sfb;\n reg [7:0] ldq_5_bits_uop_br_mask;\n reg [2:0] ldq_5_bits_uop_br_tag;\n reg [3:0] ldq_5_bits_uop_ftq_idx;\n reg ldq_5_bits_uop_edge_inst;\n reg [5:0] ldq_5_bits_uop_pc_lob;\n reg ldq_5_bits_uop_taken;\n reg [19:0] ldq_5_bits_uop_imm_packed;\n reg [11:0] ldq_5_bits_uop_csr_addr;\n reg [4:0] ldq_5_bits_uop_rob_idx;\n reg [2:0] ldq_5_bits_uop_ldq_idx;\n reg [2:0] ldq_5_bits_uop_stq_idx;\n reg [1:0] ldq_5_bits_uop_rxq_idx;\n reg [5:0] ldq_5_bits_uop_pdst;\n reg [5:0] ldq_5_bits_uop_prs1;\n reg [5:0] ldq_5_bits_uop_prs2;\n reg [5:0] ldq_5_bits_uop_prs3;\n reg ldq_5_bits_uop_prs1_busy;\n reg ldq_5_bits_uop_prs2_busy;\n reg ldq_5_bits_uop_prs3_busy;\n reg [5:0] ldq_5_bits_uop_stale_pdst;\n reg ldq_5_bits_uop_exception;\n reg [63:0] ldq_5_bits_uop_exc_cause;\n reg ldq_5_bits_uop_bypassable;\n reg [4:0] ldq_5_bits_uop_mem_cmd;\n reg [1:0] ldq_5_bits_uop_mem_size;\n reg ldq_5_bits_uop_mem_signed;\n reg ldq_5_bits_uop_is_fence;\n reg ldq_5_bits_uop_is_fencei;\n reg ldq_5_bits_uop_is_amo;\n reg ldq_5_bits_uop_uses_ldq;\n reg ldq_5_bits_uop_uses_stq;\n reg ldq_5_bits_uop_is_sys_pc2epc;\n reg ldq_5_bits_uop_is_unique;\n reg ldq_5_bits_uop_flush_on_commit;\n reg ldq_5_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_5_bits_uop_ldst;\n reg [5:0] ldq_5_bits_uop_lrs1;\n reg [5:0] ldq_5_bits_uop_lrs2;\n reg [5:0] ldq_5_bits_uop_lrs3;\n reg ldq_5_bits_uop_ldst_val;\n reg [1:0] ldq_5_bits_uop_dst_rtype;\n reg [1:0] ldq_5_bits_uop_lrs1_rtype;\n reg [1:0] ldq_5_bits_uop_lrs2_rtype;\n reg ldq_5_bits_uop_frs3_en;\n reg ldq_5_bits_uop_fp_val;\n reg ldq_5_bits_uop_fp_single;\n reg ldq_5_bits_uop_xcpt_pf_if;\n reg ldq_5_bits_uop_xcpt_ae_if;\n reg ldq_5_bits_uop_xcpt_ma_if;\n reg ldq_5_bits_uop_bp_debug_if;\n reg ldq_5_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_5_bits_uop_debug_fsrc;\n reg [1:0] ldq_5_bits_uop_debug_tsrc;\n reg ldq_5_bits_addr_valid;\n reg [39:0] ldq_5_bits_addr_bits;\n reg ldq_5_bits_addr_is_virtual;\n reg ldq_5_bits_addr_is_uncacheable;\n reg ldq_5_bits_executed;\n reg ldq_5_bits_succeeded;\n reg ldq_5_bits_order_fail;\n reg ldq_5_bits_observed;\n reg [7:0] ldq_5_bits_st_dep_mask;\n reg [2:0] ldq_5_bits_youngest_stq_idx;\n reg ldq_5_bits_forward_std_val;\n reg [2:0] ldq_5_bits_forward_stq_idx;\n reg ldq_6_valid;\n reg [6:0] ldq_6_bits_uop_uopc;\n reg [31:0] ldq_6_bits_uop_inst;\n reg [31:0] ldq_6_bits_uop_debug_inst;\n reg ldq_6_bits_uop_is_rvc;\n reg [39:0] ldq_6_bits_uop_debug_pc;\n reg [2:0] ldq_6_bits_uop_iq_type;\n reg [9:0] ldq_6_bits_uop_fu_code;\n reg [3:0] ldq_6_bits_uop_ctrl_br_type;\n reg [1:0] ldq_6_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_6_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_6_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_6_bits_uop_ctrl_op_fcn;\n reg ldq_6_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_6_bits_uop_ctrl_csr_cmd;\n reg ldq_6_bits_uop_ctrl_is_load;\n reg ldq_6_bits_uop_ctrl_is_sta;\n reg ldq_6_bits_uop_ctrl_is_std;\n reg [1:0] ldq_6_bits_uop_iw_state;\n reg ldq_6_bits_uop_iw_p1_poisoned;\n reg ldq_6_bits_uop_iw_p2_poisoned;\n reg ldq_6_bits_uop_is_br;\n reg ldq_6_bits_uop_is_jalr;\n reg ldq_6_bits_uop_is_jal;\n reg ldq_6_bits_uop_is_sfb;\n reg [7:0] ldq_6_bits_uop_br_mask;\n reg [2:0] ldq_6_bits_uop_br_tag;\n reg [3:0] ldq_6_bits_uop_ftq_idx;\n reg ldq_6_bits_uop_edge_inst;\n reg [5:0] ldq_6_bits_uop_pc_lob;\n reg ldq_6_bits_uop_taken;\n reg [19:0] ldq_6_bits_uop_imm_packed;\n reg [11:0] ldq_6_bits_uop_csr_addr;\n reg [4:0] ldq_6_bits_uop_rob_idx;\n reg [2:0] ldq_6_bits_uop_ldq_idx;\n reg [2:0] ldq_6_bits_uop_stq_idx;\n reg [1:0] ldq_6_bits_uop_rxq_idx;\n reg [5:0] ldq_6_bits_uop_pdst;\n reg [5:0] ldq_6_bits_uop_prs1;\n reg [5:0] ldq_6_bits_uop_prs2;\n reg [5:0] ldq_6_bits_uop_prs3;\n reg ldq_6_bits_uop_prs1_busy;\n reg ldq_6_bits_uop_prs2_busy;\n reg ldq_6_bits_uop_prs3_busy;\n reg [5:0] ldq_6_bits_uop_stale_pdst;\n reg ldq_6_bits_uop_exception;\n reg [63:0] ldq_6_bits_uop_exc_cause;\n reg ldq_6_bits_uop_bypassable;\n reg [4:0] ldq_6_bits_uop_mem_cmd;\n reg [1:0] ldq_6_bits_uop_mem_size;\n reg ldq_6_bits_uop_mem_signed;\n reg ldq_6_bits_uop_is_fence;\n reg ldq_6_bits_uop_is_fencei;\n reg ldq_6_bits_uop_is_amo;\n reg ldq_6_bits_uop_uses_ldq;\n reg ldq_6_bits_uop_uses_stq;\n reg ldq_6_bits_uop_is_sys_pc2epc;\n reg ldq_6_bits_uop_is_unique;\n reg ldq_6_bits_uop_flush_on_commit;\n reg ldq_6_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_6_bits_uop_ldst;\n reg [5:0] ldq_6_bits_uop_lrs1;\n reg [5:0] ldq_6_bits_uop_lrs2;\n reg [5:0] ldq_6_bits_uop_lrs3;\n reg ldq_6_bits_uop_ldst_val;\n reg [1:0] ldq_6_bits_uop_dst_rtype;\n reg [1:0] ldq_6_bits_uop_lrs1_rtype;\n reg [1:0] ldq_6_bits_uop_lrs2_rtype;\n reg ldq_6_bits_uop_frs3_en;\n reg ldq_6_bits_uop_fp_val;\n reg ldq_6_bits_uop_fp_single;\n reg ldq_6_bits_uop_xcpt_pf_if;\n reg ldq_6_bits_uop_xcpt_ae_if;\n reg ldq_6_bits_uop_xcpt_ma_if;\n reg ldq_6_bits_uop_bp_debug_if;\n reg ldq_6_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_6_bits_uop_debug_fsrc;\n reg [1:0] ldq_6_bits_uop_debug_tsrc;\n reg ldq_6_bits_addr_valid;\n reg [39:0] ldq_6_bits_addr_bits;\n reg ldq_6_bits_addr_is_virtual;\n reg ldq_6_bits_addr_is_uncacheable;\n reg ldq_6_bits_executed;\n reg ldq_6_bits_succeeded;\n reg ldq_6_bits_order_fail;\n reg ldq_6_bits_observed;\n reg [7:0] ldq_6_bits_st_dep_mask;\n reg [2:0] ldq_6_bits_youngest_stq_idx;\n reg ldq_6_bits_forward_std_val;\n reg [2:0] ldq_6_bits_forward_stq_idx;\n reg ldq_7_valid;\n reg [6:0] ldq_7_bits_uop_uopc;\n reg [31:0] ldq_7_bits_uop_inst;\n reg [31:0] ldq_7_bits_uop_debug_inst;\n reg ldq_7_bits_uop_is_rvc;\n reg [39:0] ldq_7_bits_uop_debug_pc;\n reg [2:0] ldq_7_bits_uop_iq_type;\n reg [9:0] ldq_7_bits_uop_fu_code;\n reg [3:0] ldq_7_bits_uop_ctrl_br_type;\n reg [1:0] ldq_7_bits_uop_ctrl_op1_sel;\n reg [2:0] ldq_7_bits_uop_ctrl_op2_sel;\n reg [2:0] ldq_7_bits_uop_ctrl_imm_sel;\n reg [4:0] ldq_7_bits_uop_ctrl_op_fcn;\n reg ldq_7_bits_uop_ctrl_fcn_dw;\n reg [2:0] ldq_7_bits_uop_ctrl_csr_cmd;\n reg ldq_7_bits_uop_ctrl_is_load;\n reg ldq_7_bits_uop_ctrl_is_sta;\n reg ldq_7_bits_uop_ctrl_is_std;\n reg [1:0] ldq_7_bits_uop_iw_state;\n reg ldq_7_bits_uop_iw_p1_poisoned;\n reg ldq_7_bits_uop_iw_p2_poisoned;\n reg ldq_7_bits_uop_is_br;\n reg ldq_7_bits_uop_is_jalr;\n reg ldq_7_bits_uop_is_jal;\n reg ldq_7_bits_uop_is_sfb;\n reg [7:0] ldq_7_bits_uop_br_mask;\n reg [2:0] ldq_7_bits_uop_br_tag;\n reg [3:0] ldq_7_bits_uop_ftq_idx;\n reg ldq_7_bits_uop_edge_inst;\n reg [5:0] ldq_7_bits_uop_pc_lob;\n reg ldq_7_bits_uop_taken;\n reg [19:0] ldq_7_bits_uop_imm_packed;\n reg [11:0] ldq_7_bits_uop_csr_addr;\n reg [4:0] ldq_7_bits_uop_rob_idx;\n reg [2:0] ldq_7_bits_uop_ldq_idx;\n reg [2:0] ldq_7_bits_uop_stq_idx;\n reg [1:0] ldq_7_bits_uop_rxq_idx;\n reg [5:0] ldq_7_bits_uop_pdst;\n reg [5:0] ldq_7_bits_uop_prs1;\n reg [5:0] ldq_7_bits_uop_prs2;\n reg [5:0] ldq_7_bits_uop_prs3;\n reg ldq_7_bits_uop_prs1_busy;\n reg ldq_7_bits_uop_prs2_busy;\n reg ldq_7_bits_uop_prs3_busy;\n reg [5:0] ldq_7_bits_uop_stale_pdst;\n reg ldq_7_bits_uop_exception;\n reg [63:0] ldq_7_bits_uop_exc_cause;\n reg ldq_7_bits_uop_bypassable;\n reg [4:0] ldq_7_bits_uop_mem_cmd;\n reg [1:0] ldq_7_bits_uop_mem_size;\n reg ldq_7_bits_uop_mem_signed;\n reg ldq_7_bits_uop_is_fence;\n reg ldq_7_bits_uop_is_fencei;\n reg ldq_7_bits_uop_is_amo;\n reg ldq_7_bits_uop_uses_ldq;\n reg ldq_7_bits_uop_uses_stq;\n reg ldq_7_bits_uop_is_sys_pc2epc;\n reg ldq_7_bits_uop_is_unique;\n reg ldq_7_bits_uop_flush_on_commit;\n reg ldq_7_bits_uop_ldst_is_rs1;\n reg [5:0] ldq_7_bits_uop_ldst;\n reg [5:0] ldq_7_bits_uop_lrs1;\n reg [5:0] ldq_7_bits_uop_lrs2;\n reg [5:0] ldq_7_bits_uop_lrs3;\n reg ldq_7_bits_uop_ldst_val;\n reg [1:0] ldq_7_bits_uop_dst_rtype;\n reg [1:0] ldq_7_bits_uop_lrs1_rtype;\n reg [1:0] ldq_7_bits_uop_lrs2_rtype;\n reg ldq_7_bits_uop_frs3_en;\n reg ldq_7_bits_uop_fp_val;\n reg ldq_7_bits_uop_fp_single;\n reg ldq_7_bits_uop_xcpt_pf_if;\n reg ldq_7_bits_uop_xcpt_ae_if;\n reg ldq_7_bits_uop_xcpt_ma_if;\n reg ldq_7_bits_uop_bp_debug_if;\n reg ldq_7_bits_uop_bp_xcpt_if;\n reg [1:0] ldq_7_bits_uop_debug_fsrc;\n reg [1:0] ldq_7_bits_uop_debug_tsrc;\n reg ldq_7_bits_addr_valid;\n reg [39:0] ldq_7_bits_addr_bits;\n reg ldq_7_bits_addr_is_virtual;\n reg ldq_7_bits_addr_is_uncacheable;\n reg ldq_7_bits_executed;\n reg ldq_7_bits_succeeded;\n reg ldq_7_bits_order_fail;\n reg ldq_7_bits_observed;\n reg [7:0] ldq_7_bits_st_dep_mask;\n reg [2:0] ldq_7_bits_youngest_stq_idx;\n reg ldq_7_bits_forward_std_val;\n reg [2:0] ldq_7_bits_forward_stq_idx;\n reg stq_0_valid;\n reg [6:0] stq_0_bits_uop_uopc;\n reg [31:0] stq_0_bits_uop_inst;\n reg [31:0] stq_0_bits_uop_debug_inst;\n reg stq_0_bits_uop_is_rvc;\n reg [39:0] stq_0_bits_uop_debug_pc;\n reg [2:0] stq_0_bits_uop_iq_type;\n reg [9:0] stq_0_bits_uop_fu_code;\n reg [3:0] stq_0_bits_uop_ctrl_br_type;\n reg [1:0] stq_0_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_0_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_0_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_0_bits_uop_ctrl_op_fcn;\n reg stq_0_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_0_bits_uop_ctrl_csr_cmd;\n reg stq_0_bits_uop_ctrl_is_load;\n reg stq_0_bits_uop_ctrl_is_sta;\n reg stq_0_bits_uop_ctrl_is_std;\n reg [1:0] stq_0_bits_uop_iw_state;\n reg stq_0_bits_uop_iw_p1_poisoned;\n reg stq_0_bits_uop_iw_p2_poisoned;\n reg stq_0_bits_uop_is_br;\n reg stq_0_bits_uop_is_jalr;\n reg stq_0_bits_uop_is_jal;\n reg stq_0_bits_uop_is_sfb;\n reg [7:0] stq_0_bits_uop_br_mask;\n reg [2:0] stq_0_bits_uop_br_tag;\n reg [3:0] stq_0_bits_uop_ftq_idx;\n reg stq_0_bits_uop_edge_inst;\n reg [5:0] stq_0_bits_uop_pc_lob;\n reg stq_0_bits_uop_taken;\n reg [19:0] stq_0_bits_uop_imm_packed;\n reg [11:0] stq_0_bits_uop_csr_addr;\n reg [4:0] stq_0_bits_uop_rob_idx;\n reg [2:0] stq_0_bits_uop_ldq_idx;\n reg [2:0] stq_0_bits_uop_stq_idx;\n reg [1:0] stq_0_bits_uop_rxq_idx;\n reg [5:0] stq_0_bits_uop_pdst;\n reg [5:0] stq_0_bits_uop_prs1;\n reg [5:0] stq_0_bits_uop_prs2;\n reg [5:0] stq_0_bits_uop_prs3;\n reg [3:0] stq_0_bits_uop_ppred;\n reg stq_0_bits_uop_prs1_busy;\n reg stq_0_bits_uop_prs2_busy;\n reg stq_0_bits_uop_prs3_busy;\n reg stq_0_bits_uop_ppred_busy;\n reg [5:0] stq_0_bits_uop_stale_pdst;\n reg stq_0_bits_uop_exception;\n reg [63:0] stq_0_bits_uop_exc_cause;\n reg stq_0_bits_uop_bypassable;\n reg [4:0] stq_0_bits_uop_mem_cmd;\n reg [1:0] stq_0_bits_uop_mem_size;\n reg stq_0_bits_uop_mem_signed;\n reg stq_0_bits_uop_is_fence;\n reg stq_0_bits_uop_is_fencei;\n reg stq_0_bits_uop_is_amo;\n reg stq_0_bits_uop_uses_ldq;\n reg stq_0_bits_uop_uses_stq;\n reg stq_0_bits_uop_is_sys_pc2epc;\n reg stq_0_bits_uop_is_unique;\n reg stq_0_bits_uop_flush_on_commit;\n reg stq_0_bits_uop_ldst_is_rs1;\n reg [5:0] stq_0_bits_uop_ldst;\n reg [5:0] stq_0_bits_uop_lrs1;\n reg [5:0] stq_0_bits_uop_lrs2;\n reg [5:0] stq_0_bits_uop_lrs3;\n reg stq_0_bits_uop_ldst_val;\n reg [1:0] stq_0_bits_uop_dst_rtype;\n reg [1:0] stq_0_bits_uop_lrs1_rtype;\n reg [1:0] stq_0_bits_uop_lrs2_rtype;\n reg stq_0_bits_uop_frs3_en;\n reg stq_0_bits_uop_fp_val;\n reg stq_0_bits_uop_fp_single;\n reg stq_0_bits_uop_xcpt_pf_if;\n reg stq_0_bits_uop_xcpt_ae_if;\n reg stq_0_bits_uop_xcpt_ma_if;\n reg stq_0_bits_uop_bp_debug_if;\n reg stq_0_bits_uop_bp_xcpt_if;\n reg [1:0] stq_0_bits_uop_debug_fsrc;\n reg [1:0] stq_0_bits_uop_debug_tsrc;\n reg stq_0_bits_addr_valid;\n reg [39:0] stq_0_bits_addr_bits;\n reg stq_0_bits_addr_is_virtual;\n reg stq_0_bits_data_valid;\n reg [63:0] stq_0_bits_data_bits;\n reg stq_0_bits_committed;\n reg stq_0_bits_succeeded;\n reg stq_1_valid;\n reg [6:0] stq_1_bits_uop_uopc;\n reg [31:0] stq_1_bits_uop_inst;\n reg [31:0] stq_1_bits_uop_debug_inst;\n reg stq_1_bits_uop_is_rvc;\n reg [39:0] stq_1_bits_uop_debug_pc;\n reg [2:0] stq_1_bits_uop_iq_type;\n reg [9:0] stq_1_bits_uop_fu_code;\n reg [3:0] stq_1_bits_uop_ctrl_br_type;\n reg [1:0] stq_1_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_1_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_1_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_1_bits_uop_ctrl_op_fcn;\n reg stq_1_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_1_bits_uop_ctrl_csr_cmd;\n reg stq_1_bits_uop_ctrl_is_load;\n reg stq_1_bits_uop_ctrl_is_sta;\n reg stq_1_bits_uop_ctrl_is_std;\n reg [1:0] stq_1_bits_uop_iw_state;\n reg stq_1_bits_uop_iw_p1_poisoned;\n reg stq_1_bits_uop_iw_p2_poisoned;\n reg stq_1_bits_uop_is_br;\n reg stq_1_bits_uop_is_jalr;\n reg stq_1_bits_uop_is_jal;\n reg stq_1_bits_uop_is_sfb;\n reg [7:0] stq_1_bits_uop_br_mask;\n reg [2:0] stq_1_bits_uop_br_tag;\n reg [3:0] stq_1_bits_uop_ftq_idx;\n reg stq_1_bits_uop_edge_inst;\n reg [5:0] stq_1_bits_uop_pc_lob;\n reg stq_1_bits_uop_taken;\n reg [19:0] stq_1_bits_uop_imm_packed;\n reg [11:0] stq_1_bits_uop_csr_addr;\n reg [4:0] stq_1_bits_uop_rob_idx;\n reg [2:0] stq_1_bits_uop_ldq_idx;\n reg [2:0] stq_1_bits_uop_stq_idx;\n reg [1:0] stq_1_bits_uop_rxq_idx;\n reg [5:0] stq_1_bits_uop_pdst;\n reg [5:0] stq_1_bits_uop_prs1;\n reg [5:0] stq_1_bits_uop_prs2;\n reg [5:0] stq_1_bits_uop_prs3;\n reg [3:0] stq_1_bits_uop_ppred;\n reg stq_1_bits_uop_prs1_busy;\n reg stq_1_bits_uop_prs2_busy;\n reg stq_1_bits_uop_prs3_busy;\n reg stq_1_bits_uop_ppred_busy;\n reg [5:0] stq_1_bits_uop_stale_pdst;\n reg stq_1_bits_uop_exception;\n reg [63:0] stq_1_bits_uop_exc_cause;\n reg stq_1_bits_uop_bypassable;\n reg [4:0] stq_1_bits_uop_mem_cmd;\n reg [1:0] stq_1_bits_uop_mem_size;\n reg stq_1_bits_uop_mem_signed;\n reg stq_1_bits_uop_is_fence;\n reg stq_1_bits_uop_is_fencei;\n reg stq_1_bits_uop_is_amo;\n reg stq_1_bits_uop_uses_ldq;\n reg stq_1_bits_uop_uses_stq;\n reg stq_1_bits_uop_is_sys_pc2epc;\n reg stq_1_bits_uop_is_unique;\n reg stq_1_bits_uop_flush_on_commit;\n reg stq_1_bits_uop_ldst_is_rs1;\n reg [5:0] stq_1_bits_uop_ldst;\n reg [5:0] stq_1_bits_uop_lrs1;\n reg [5:0] stq_1_bits_uop_lrs2;\n reg [5:0] stq_1_bits_uop_lrs3;\n reg stq_1_bits_uop_ldst_val;\n reg [1:0] stq_1_bits_uop_dst_rtype;\n reg [1:0] stq_1_bits_uop_lrs1_rtype;\n reg [1:0] stq_1_bits_uop_lrs2_rtype;\n reg stq_1_bits_uop_frs3_en;\n reg stq_1_bits_uop_fp_val;\n reg stq_1_bits_uop_fp_single;\n reg stq_1_bits_uop_xcpt_pf_if;\n reg stq_1_bits_uop_xcpt_ae_if;\n reg stq_1_bits_uop_xcpt_ma_if;\n reg stq_1_bits_uop_bp_debug_if;\n reg stq_1_bits_uop_bp_xcpt_if;\n reg [1:0] stq_1_bits_uop_debug_fsrc;\n reg [1:0] stq_1_bits_uop_debug_tsrc;\n reg stq_1_bits_addr_valid;\n reg [39:0] stq_1_bits_addr_bits;\n reg stq_1_bits_addr_is_virtual;\n reg stq_1_bits_data_valid;\n reg [63:0] stq_1_bits_data_bits;\n reg stq_1_bits_committed;\n reg stq_1_bits_succeeded;\n reg stq_2_valid;\n reg [6:0] stq_2_bits_uop_uopc;\n reg [31:0] stq_2_bits_uop_inst;\n reg [31:0] stq_2_bits_uop_debug_inst;\n reg stq_2_bits_uop_is_rvc;\n reg [39:0] stq_2_bits_uop_debug_pc;\n reg [2:0] stq_2_bits_uop_iq_type;\n reg [9:0] stq_2_bits_uop_fu_code;\n reg [3:0] stq_2_bits_uop_ctrl_br_type;\n reg [1:0] stq_2_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_2_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_2_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_2_bits_uop_ctrl_op_fcn;\n reg stq_2_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_2_bits_uop_ctrl_csr_cmd;\n reg stq_2_bits_uop_ctrl_is_load;\n reg stq_2_bits_uop_ctrl_is_sta;\n reg stq_2_bits_uop_ctrl_is_std;\n reg [1:0] stq_2_bits_uop_iw_state;\n reg stq_2_bits_uop_iw_p1_poisoned;\n reg stq_2_bits_uop_iw_p2_poisoned;\n reg stq_2_bits_uop_is_br;\n reg stq_2_bits_uop_is_jalr;\n reg stq_2_bits_uop_is_jal;\n reg stq_2_bits_uop_is_sfb;\n reg [7:0] stq_2_bits_uop_br_mask;\n reg [2:0] stq_2_bits_uop_br_tag;\n reg [3:0] stq_2_bits_uop_ftq_idx;\n reg stq_2_bits_uop_edge_inst;\n reg [5:0] stq_2_bits_uop_pc_lob;\n reg stq_2_bits_uop_taken;\n reg [19:0] stq_2_bits_uop_imm_packed;\n reg [11:0] stq_2_bits_uop_csr_addr;\n reg [4:0] stq_2_bits_uop_rob_idx;\n reg [2:0] stq_2_bits_uop_ldq_idx;\n reg [2:0] stq_2_bits_uop_stq_idx;\n reg [1:0] stq_2_bits_uop_rxq_idx;\n reg [5:0] stq_2_bits_uop_pdst;\n reg [5:0] stq_2_bits_uop_prs1;\n reg [5:0] stq_2_bits_uop_prs2;\n reg [5:0] stq_2_bits_uop_prs3;\n reg [3:0] stq_2_bits_uop_ppred;\n reg stq_2_bits_uop_prs1_busy;\n reg stq_2_bits_uop_prs2_busy;\n reg stq_2_bits_uop_prs3_busy;\n reg stq_2_bits_uop_ppred_busy;\n reg [5:0] stq_2_bits_uop_stale_pdst;\n reg stq_2_bits_uop_exception;\n reg [63:0] stq_2_bits_uop_exc_cause;\n reg stq_2_bits_uop_bypassable;\n reg [4:0] stq_2_bits_uop_mem_cmd;\n reg [1:0] stq_2_bits_uop_mem_size;\n reg stq_2_bits_uop_mem_signed;\n reg stq_2_bits_uop_is_fence;\n reg stq_2_bits_uop_is_fencei;\n reg stq_2_bits_uop_is_amo;\n reg stq_2_bits_uop_uses_ldq;\n reg stq_2_bits_uop_uses_stq;\n reg stq_2_bits_uop_is_sys_pc2epc;\n reg stq_2_bits_uop_is_unique;\n reg stq_2_bits_uop_flush_on_commit;\n reg stq_2_bits_uop_ldst_is_rs1;\n reg [5:0] stq_2_bits_uop_ldst;\n reg [5:0] stq_2_bits_uop_lrs1;\n reg [5:0] stq_2_bits_uop_lrs2;\n reg [5:0] stq_2_bits_uop_lrs3;\n reg stq_2_bits_uop_ldst_val;\n reg [1:0] stq_2_bits_uop_dst_rtype;\n reg [1:0] stq_2_bits_uop_lrs1_rtype;\n reg [1:0] stq_2_bits_uop_lrs2_rtype;\n reg stq_2_bits_uop_frs3_en;\n reg stq_2_bits_uop_fp_val;\n reg stq_2_bits_uop_fp_single;\n reg stq_2_bits_uop_xcpt_pf_if;\n reg stq_2_bits_uop_xcpt_ae_if;\n reg stq_2_bits_uop_xcpt_ma_if;\n reg stq_2_bits_uop_bp_debug_if;\n reg stq_2_bits_uop_bp_xcpt_if;\n reg [1:0] stq_2_bits_uop_debug_fsrc;\n reg [1:0] stq_2_bits_uop_debug_tsrc;\n reg stq_2_bits_addr_valid;\n reg [39:0] stq_2_bits_addr_bits;\n reg stq_2_bits_addr_is_virtual;\n reg stq_2_bits_data_valid;\n reg [63:0] stq_2_bits_data_bits;\n reg stq_2_bits_committed;\n reg stq_2_bits_succeeded;\n reg stq_3_valid;\n reg [6:0] stq_3_bits_uop_uopc;\n reg [31:0] stq_3_bits_uop_inst;\n reg [31:0] stq_3_bits_uop_debug_inst;\n reg stq_3_bits_uop_is_rvc;\n reg [39:0] stq_3_bits_uop_debug_pc;\n reg [2:0] stq_3_bits_uop_iq_type;\n reg [9:0] stq_3_bits_uop_fu_code;\n reg [3:0] stq_3_bits_uop_ctrl_br_type;\n reg [1:0] stq_3_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_3_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_3_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_3_bits_uop_ctrl_op_fcn;\n reg stq_3_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_3_bits_uop_ctrl_csr_cmd;\n reg stq_3_bits_uop_ctrl_is_load;\n reg stq_3_bits_uop_ctrl_is_sta;\n reg stq_3_bits_uop_ctrl_is_std;\n reg [1:0] stq_3_bits_uop_iw_state;\n reg stq_3_bits_uop_iw_p1_poisoned;\n reg stq_3_bits_uop_iw_p2_poisoned;\n reg stq_3_bits_uop_is_br;\n reg stq_3_bits_uop_is_jalr;\n reg stq_3_bits_uop_is_jal;\n reg stq_3_bits_uop_is_sfb;\n reg [7:0] stq_3_bits_uop_br_mask;\n reg [2:0] stq_3_bits_uop_br_tag;\n reg [3:0] stq_3_bits_uop_ftq_idx;\n reg stq_3_bits_uop_edge_inst;\n reg [5:0] stq_3_bits_uop_pc_lob;\n reg stq_3_bits_uop_taken;\n reg [19:0] stq_3_bits_uop_imm_packed;\n reg [11:0] stq_3_bits_uop_csr_addr;\n reg [4:0] stq_3_bits_uop_rob_idx;\n reg [2:0] stq_3_bits_uop_ldq_idx;\n reg [2:0] stq_3_bits_uop_stq_idx;\n reg [1:0] stq_3_bits_uop_rxq_idx;\n reg [5:0] stq_3_bits_uop_pdst;\n reg [5:0] stq_3_bits_uop_prs1;\n reg [5:0] stq_3_bits_uop_prs2;\n reg [5:0] stq_3_bits_uop_prs3;\n reg [3:0] stq_3_bits_uop_ppred;\n reg stq_3_bits_uop_prs1_busy;\n reg stq_3_bits_uop_prs2_busy;\n reg stq_3_bits_uop_prs3_busy;\n reg stq_3_bits_uop_ppred_busy;\n reg [5:0] stq_3_bits_uop_stale_pdst;\n reg stq_3_bits_uop_exception;\n reg [63:0] stq_3_bits_uop_exc_cause;\n reg stq_3_bits_uop_bypassable;\n reg [4:0] stq_3_bits_uop_mem_cmd;\n reg [1:0] stq_3_bits_uop_mem_size;\n reg stq_3_bits_uop_mem_signed;\n reg stq_3_bits_uop_is_fence;\n reg stq_3_bits_uop_is_fencei;\n reg stq_3_bits_uop_is_amo;\n reg stq_3_bits_uop_uses_ldq;\n reg stq_3_bits_uop_uses_stq;\n reg stq_3_bits_uop_is_sys_pc2epc;\n reg stq_3_bits_uop_is_unique;\n reg stq_3_bits_uop_flush_on_commit;\n reg stq_3_bits_uop_ldst_is_rs1;\n reg [5:0] stq_3_bits_uop_ldst;\n reg [5:0] stq_3_bits_uop_lrs1;\n reg [5:0] stq_3_bits_uop_lrs2;\n reg [5:0] stq_3_bits_uop_lrs3;\n reg stq_3_bits_uop_ldst_val;\n reg [1:0] stq_3_bits_uop_dst_rtype;\n reg [1:0] stq_3_bits_uop_lrs1_rtype;\n reg [1:0] stq_3_bits_uop_lrs2_rtype;\n reg stq_3_bits_uop_frs3_en;\n reg stq_3_bits_uop_fp_val;\n reg stq_3_bits_uop_fp_single;\n reg stq_3_bits_uop_xcpt_pf_if;\n reg stq_3_bits_uop_xcpt_ae_if;\n reg stq_3_bits_uop_xcpt_ma_if;\n reg stq_3_bits_uop_bp_debug_if;\n reg stq_3_bits_uop_bp_xcpt_if;\n reg [1:0] stq_3_bits_uop_debug_fsrc;\n reg [1:0] stq_3_bits_uop_debug_tsrc;\n reg stq_3_bits_addr_valid;\n reg [39:0] stq_3_bits_addr_bits;\n reg stq_3_bits_addr_is_virtual;\n reg stq_3_bits_data_valid;\n reg [63:0] stq_3_bits_data_bits;\n reg stq_3_bits_committed;\n reg stq_3_bits_succeeded;\n reg stq_4_valid;\n reg [6:0] stq_4_bits_uop_uopc;\n reg [31:0] stq_4_bits_uop_inst;\n reg [31:0] stq_4_bits_uop_debug_inst;\n reg stq_4_bits_uop_is_rvc;\n reg [39:0] stq_4_bits_uop_debug_pc;\n reg [2:0] stq_4_bits_uop_iq_type;\n reg [9:0] stq_4_bits_uop_fu_code;\n reg [3:0] stq_4_bits_uop_ctrl_br_type;\n reg [1:0] stq_4_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_4_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_4_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_4_bits_uop_ctrl_op_fcn;\n reg stq_4_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_4_bits_uop_ctrl_csr_cmd;\n reg stq_4_bits_uop_ctrl_is_load;\n reg stq_4_bits_uop_ctrl_is_sta;\n reg stq_4_bits_uop_ctrl_is_std;\n reg [1:0] stq_4_bits_uop_iw_state;\n reg stq_4_bits_uop_iw_p1_poisoned;\n reg stq_4_bits_uop_iw_p2_poisoned;\n reg stq_4_bits_uop_is_br;\n reg stq_4_bits_uop_is_jalr;\n reg stq_4_bits_uop_is_jal;\n reg stq_4_bits_uop_is_sfb;\n reg [7:0] stq_4_bits_uop_br_mask;\n reg [2:0] stq_4_bits_uop_br_tag;\n reg [3:0] stq_4_bits_uop_ftq_idx;\n reg stq_4_bits_uop_edge_inst;\n reg [5:0] stq_4_bits_uop_pc_lob;\n reg stq_4_bits_uop_taken;\n reg [19:0] stq_4_bits_uop_imm_packed;\n reg [11:0] stq_4_bits_uop_csr_addr;\n reg [4:0] stq_4_bits_uop_rob_idx;\n reg [2:0] stq_4_bits_uop_ldq_idx;\n reg [2:0] stq_4_bits_uop_stq_idx;\n reg [1:0] stq_4_bits_uop_rxq_idx;\n reg [5:0] stq_4_bits_uop_pdst;\n reg [5:0] stq_4_bits_uop_prs1;\n reg [5:0] stq_4_bits_uop_prs2;\n reg [5:0] stq_4_bits_uop_prs3;\n reg [3:0] stq_4_bits_uop_ppred;\n reg stq_4_bits_uop_prs1_busy;\n reg stq_4_bits_uop_prs2_busy;\n reg stq_4_bits_uop_prs3_busy;\n reg stq_4_bits_uop_ppred_busy;\n reg [5:0] stq_4_bits_uop_stale_pdst;\n reg stq_4_bits_uop_exception;\n reg [63:0] stq_4_bits_uop_exc_cause;\n reg stq_4_bits_uop_bypassable;\n reg [4:0] stq_4_bits_uop_mem_cmd;\n reg [1:0] stq_4_bits_uop_mem_size;\n reg stq_4_bits_uop_mem_signed;\n reg stq_4_bits_uop_is_fence;\n reg stq_4_bits_uop_is_fencei;\n reg stq_4_bits_uop_is_amo;\n reg stq_4_bits_uop_uses_ldq;\n reg stq_4_bits_uop_uses_stq;\n reg stq_4_bits_uop_is_sys_pc2epc;\n reg stq_4_bits_uop_is_unique;\n reg stq_4_bits_uop_flush_on_commit;\n reg stq_4_bits_uop_ldst_is_rs1;\n reg [5:0] stq_4_bits_uop_ldst;\n reg [5:0] stq_4_bits_uop_lrs1;\n reg [5:0] stq_4_bits_uop_lrs2;\n reg [5:0] stq_4_bits_uop_lrs3;\n reg stq_4_bits_uop_ldst_val;\n reg [1:0] stq_4_bits_uop_dst_rtype;\n reg [1:0] stq_4_bits_uop_lrs1_rtype;\n reg [1:0] stq_4_bits_uop_lrs2_rtype;\n reg stq_4_bits_uop_frs3_en;\n reg stq_4_bits_uop_fp_val;\n reg stq_4_bits_uop_fp_single;\n reg stq_4_bits_uop_xcpt_pf_if;\n reg stq_4_bits_uop_xcpt_ae_if;\n reg stq_4_bits_uop_xcpt_ma_if;\n reg stq_4_bits_uop_bp_debug_if;\n reg stq_4_bits_uop_bp_xcpt_if;\n reg [1:0] stq_4_bits_uop_debug_fsrc;\n reg [1:0] stq_4_bits_uop_debug_tsrc;\n reg stq_4_bits_addr_valid;\n reg [39:0] stq_4_bits_addr_bits;\n reg stq_4_bits_addr_is_virtual;\n reg stq_4_bits_data_valid;\n reg [63:0] stq_4_bits_data_bits;\n reg stq_4_bits_committed;\n reg stq_4_bits_succeeded;\n reg stq_5_valid;\n reg [6:0] stq_5_bits_uop_uopc;\n reg [31:0] stq_5_bits_uop_inst;\n reg [31:0] stq_5_bits_uop_debug_inst;\n reg stq_5_bits_uop_is_rvc;\n reg [39:0] stq_5_bits_uop_debug_pc;\n reg [2:0] stq_5_bits_uop_iq_type;\n reg [9:0] stq_5_bits_uop_fu_code;\n reg [3:0] stq_5_bits_uop_ctrl_br_type;\n reg [1:0] stq_5_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_5_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_5_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_5_bits_uop_ctrl_op_fcn;\n reg stq_5_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_5_bits_uop_ctrl_csr_cmd;\n reg stq_5_bits_uop_ctrl_is_load;\n reg stq_5_bits_uop_ctrl_is_sta;\n reg stq_5_bits_uop_ctrl_is_std;\n reg [1:0] stq_5_bits_uop_iw_state;\n reg stq_5_bits_uop_iw_p1_poisoned;\n reg stq_5_bits_uop_iw_p2_poisoned;\n reg stq_5_bits_uop_is_br;\n reg stq_5_bits_uop_is_jalr;\n reg stq_5_bits_uop_is_jal;\n reg stq_5_bits_uop_is_sfb;\n reg [7:0] stq_5_bits_uop_br_mask;\n reg [2:0] stq_5_bits_uop_br_tag;\n reg [3:0] stq_5_bits_uop_ftq_idx;\n reg stq_5_bits_uop_edge_inst;\n reg [5:0] stq_5_bits_uop_pc_lob;\n reg stq_5_bits_uop_taken;\n reg [19:0] stq_5_bits_uop_imm_packed;\n reg [11:0] stq_5_bits_uop_csr_addr;\n reg [4:0] stq_5_bits_uop_rob_idx;\n reg [2:0] stq_5_bits_uop_ldq_idx;\n reg [2:0] stq_5_bits_uop_stq_idx;\n reg [1:0] stq_5_bits_uop_rxq_idx;\n reg [5:0] stq_5_bits_uop_pdst;\n reg [5:0] stq_5_bits_uop_prs1;\n reg [5:0] stq_5_bits_uop_prs2;\n reg [5:0] stq_5_bits_uop_prs3;\n reg [3:0] stq_5_bits_uop_ppred;\n reg stq_5_bits_uop_prs1_busy;\n reg stq_5_bits_uop_prs2_busy;\n reg stq_5_bits_uop_prs3_busy;\n reg stq_5_bits_uop_ppred_busy;\n reg [5:0] stq_5_bits_uop_stale_pdst;\n reg stq_5_bits_uop_exception;\n reg [63:0] stq_5_bits_uop_exc_cause;\n reg stq_5_bits_uop_bypassable;\n reg [4:0] stq_5_bits_uop_mem_cmd;\n reg [1:0] stq_5_bits_uop_mem_size;\n reg stq_5_bits_uop_mem_signed;\n reg stq_5_bits_uop_is_fence;\n reg stq_5_bits_uop_is_fencei;\n reg stq_5_bits_uop_is_amo;\n reg stq_5_bits_uop_uses_ldq;\n reg stq_5_bits_uop_uses_stq;\n reg stq_5_bits_uop_is_sys_pc2epc;\n reg stq_5_bits_uop_is_unique;\n reg stq_5_bits_uop_flush_on_commit;\n reg stq_5_bits_uop_ldst_is_rs1;\n reg [5:0] stq_5_bits_uop_ldst;\n reg [5:0] stq_5_bits_uop_lrs1;\n reg [5:0] stq_5_bits_uop_lrs2;\n reg [5:0] stq_5_bits_uop_lrs3;\n reg stq_5_bits_uop_ldst_val;\n reg [1:0] stq_5_bits_uop_dst_rtype;\n reg [1:0] stq_5_bits_uop_lrs1_rtype;\n reg [1:0] stq_5_bits_uop_lrs2_rtype;\n reg stq_5_bits_uop_frs3_en;\n reg stq_5_bits_uop_fp_val;\n reg stq_5_bits_uop_fp_single;\n reg stq_5_bits_uop_xcpt_pf_if;\n reg stq_5_bits_uop_xcpt_ae_if;\n reg stq_5_bits_uop_xcpt_ma_if;\n reg stq_5_bits_uop_bp_debug_if;\n reg stq_5_bits_uop_bp_xcpt_if;\n reg [1:0] stq_5_bits_uop_debug_fsrc;\n reg [1:0] stq_5_bits_uop_debug_tsrc;\n reg stq_5_bits_addr_valid;\n reg [39:0] stq_5_bits_addr_bits;\n reg stq_5_bits_addr_is_virtual;\n reg stq_5_bits_data_valid;\n reg [63:0] stq_5_bits_data_bits;\n reg stq_5_bits_committed;\n reg stq_5_bits_succeeded;\n reg stq_6_valid;\n reg [6:0] stq_6_bits_uop_uopc;\n reg [31:0] stq_6_bits_uop_inst;\n reg [31:0] stq_6_bits_uop_debug_inst;\n reg stq_6_bits_uop_is_rvc;\n reg [39:0] stq_6_bits_uop_debug_pc;\n reg [2:0] stq_6_bits_uop_iq_type;\n reg [9:0] stq_6_bits_uop_fu_code;\n reg [3:0] stq_6_bits_uop_ctrl_br_type;\n reg [1:0] stq_6_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_6_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_6_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_6_bits_uop_ctrl_op_fcn;\n reg stq_6_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_6_bits_uop_ctrl_csr_cmd;\n reg stq_6_bits_uop_ctrl_is_load;\n reg stq_6_bits_uop_ctrl_is_sta;\n reg stq_6_bits_uop_ctrl_is_std;\n reg [1:0] stq_6_bits_uop_iw_state;\n reg stq_6_bits_uop_iw_p1_poisoned;\n reg stq_6_bits_uop_iw_p2_poisoned;\n reg stq_6_bits_uop_is_br;\n reg stq_6_bits_uop_is_jalr;\n reg stq_6_bits_uop_is_jal;\n reg stq_6_bits_uop_is_sfb;\n reg [7:0] stq_6_bits_uop_br_mask;\n reg [2:0] stq_6_bits_uop_br_tag;\n reg [3:0] stq_6_bits_uop_ftq_idx;\n reg stq_6_bits_uop_edge_inst;\n reg [5:0] stq_6_bits_uop_pc_lob;\n reg stq_6_bits_uop_taken;\n reg [19:0] stq_6_bits_uop_imm_packed;\n reg [11:0] stq_6_bits_uop_csr_addr;\n reg [4:0] stq_6_bits_uop_rob_idx;\n reg [2:0] stq_6_bits_uop_ldq_idx;\n reg [2:0] stq_6_bits_uop_stq_idx;\n reg [1:0] stq_6_bits_uop_rxq_idx;\n reg [5:0] stq_6_bits_uop_pdst;\n reg [5:0] stq_6_bits_uop_prs1;\n reg [5:0] stq_6_bits_uop_prs2;\n reg [5:0] stq_6_bits_uop_prs3;\n reg [3:0] stq_6_bits_uop_ppred;\n reg stq_6_bits_uop_prs1_busy;\n reg stq_6_bits_uop_prs2_busy;\n reg stq_6_bits_uop_prs3_busy;\n reg stq_6_bits_uop_ppred_busy;\n reg [5:0] stq_6_bits_uop_stale_pdst;\n reg stq_6_bits_uop_exception;\n reg [63:0] stq_6_bits_uop_exc_cause;\n reg stq_6_bits_uop_bypassable;\n reg [4:0] stq_6_bits_uop_mem_cmd;\n reg [1:0] stq_6_bits_uop_mem_size;\n reg stq_6_bits_uop_mem_signed;\n reg stq_6_bits_uop_is_fence;\n reg stq_6_bits_uop_is_fencei;\n reg stq_6_bits_uop_is_amo;\n reg stq_6_bits_uop_uses_ldq;\n reg stq_6_bits_uop_uses_stq;\n reg stq_6_bits_uop_is_sys_pc2epc;\n reg stq_6_bits_uop_is_unique;\n reg stq_6_bits_uop_flush_on_commit;\n reg stq_6_bits_uop_ldst_is_rs1;\n reg [5:0] stq_6_bits_uop_ldst;\n reg [5:0] stq_6_bits_uop_lrs1;\n reg [5:0] stq_6_bits_uop_lrs2;\n reg [5:0] stq_6_bits_uop_lrs3;\n reg stq_6_bits_uop_ldst_val;\n reg [1:0] stq_6_bits_uop_dst_rtype;\n reg [1:0] stq_6_bits_uop_lrs1_rtype;\n reg [1:0] stq_6_bits_uop_lrs2_rtype;\n reg stq_6_bits_uop_frs3_en;\n reg stq_6_bits_uop_fp_val;\n reg stq_6_bits_uop_fp_single;\n reg stq_6_bits_uop_xcpt_pf_if;\n reg stq_6_bits_uop_xcpt_ae_if;\n reg stq_6_bits_uop_xcpt_ma_if;\n reg stq_6_bits_uop_bp_debug_if;\n reg stq_6_bits_uop_bp_xcpt_if;\n reg [1:0] stq_6_bits_uop_debug_fsrc;\n reg [1:0] stq_6_bits_uop_debug_tsrc;\n reg stq_6_bits_addr_valid;\n reg [39:0] stq_6_bits_addr_bits;\n reg stq_6_bits_addr_is_virtual;\n reg stq_6_bits_data_valid;\n reg [63:0] stq_6_bits_data_bits;\n reg stq_6_bits_committed;\n reg stq_6_bits_succeeded;\n reg stq_7_valid;\n reg [6:0] stq_7_bits_uop_uopc;\n reg [31:0] stq_7_bits_uop_inst;\n reg [31:0] stq_7_bits_uop_debug_inst;\n reg stq_7_bits_uop_is_rvc;\n reg [39:0] stq_7_bits_uop_debug_pc;\n reg [2:0] stq_7_bits_uop_iq_type;\n reg [9:0] stq_7_bits_uop_fu_code;\n reg [3:0] stq_7_bits_uop_ctrl_br_type;\n reg [1:0] stq_7_bits_uop_ctrl_op1_sel;\n reg [2:0] stq_7_bits_uop_ctrl_op2_sel;\n reg [2:0] stq_7_bits_uop_ctrl_imm_sel;\n reg [4:0] stq_7_bits_uop_ctrl_op_fcn;\n reg stq_7_bits_uop_ctrl_fcn_dw;\n reg [2:0] stq_7_bits_uop_ctrl_csr_cmd;\n reg stq_7_bits_uop_ctrl_is_load;\n reg stq_7_bits_uop_ctrl_is_sta;\n reg stq_7_bits_uop_ctrl_is_std;\n reg [1:0] stq_7_bits_uop_iw_state;\n reg stq_7_bits_uop_iw_p1_poisoned;\n reg stq_7_bits_uop_iw_p2_poisoned;\n reg stq_7_bits_uop_is_br;\n reg stq_7_bits_uop_is_jalr;\n reg stq_7_bits_uop_is_jal;\n reg stq_7_bits_uop_is_sfb;\n reg [7:0] stq_7_bits_uop_br_mask;\n reg [2:0] stq_7_bits_uop_br_tag;\n reg [3:0] stq_7_bits_uop_ftq_idx;\n reg stq_7_bits_uop_edge_inst;\n reg [5:0] stq_7_bits_uop_pc_lob;\n reg stq_7_bits_uop_taken;\n reg [19:0] stq_7_bits_uop_imm_packed;\n reg [11:0] stq_7_bits_uop_csr_addr;\n reg [4:0] stq_7_bits_uop_rob_idx;\n reg [2:0] stq_7_bits_uop_ldq_idx;\n reg [2:0] stq_7_bits_uop_stq_idx;\n reg [1:0] stq_7_bits_uop_rxq_idx;\n reg [5:0] stq_7_bits_uop_pdst;\n reg [5:0] stq_7_bits_uop_prs1;\n reg [5:0] stq_7_bits_uop_prs2;\n reg [5:0] stq_7_bits_uop_prs3;\n reg [3:0] stq_7_bits_uop_ppred;\n reg stq_7_bits_uop_prs1_busy;\n reg stq_7_bits_uop_prs2_busy;\n reg stq_7_bits_uop_prs3_busy;\n reg stq_7_bits_uop_ppred_busy;\n reg [5:0] stq_7_bits_uop_stale_pdst;\n reg stq_7_bits_uop_exception;\n reg [63:0] stq_7_bits_uop_exc_cause;\n reg stq_7_bits_uop_bypassable;\n reg [4:0] stq_7_bits_uop_mem_cmd;\n reg [1:0] stq_7_bits_uop_mem_size;\n reg stq_7_bits_uop_mem_signed;\n reg stq_7_bits_uop_is_fence;\n reg stq_7_bits_uop_is_fencei;\n reg stq_7_bits_uop_is_amo;\n reg stq_7_bits_uop_uses_ldq;\n reg stq_7_bits_uop_uses_stq;\n reg stq_7_bits_uop_is_sys_pc2epc;\n reg stq_7_bits_uop_is_unique;\n reg stq_7_bits_uop_flush_on_commit;\n reg stq_7_bits_uop_ldst_is_rs1;\n reg [5:0] stq_7_bits_uop_ldst;\n reg [5:0] stq_7_bits_uop_lrs1;\n reg [5:0] stq_7_bits_uop_lrs2;\n reg [5:0] stq_7_bits_uop_lrs3;\n reg stq_7_bits_uop_ldst_val;\n reg [1:0] stq_7_bits_uop_dst_rtype;\n reg [1:0] stq_7_bits_uop_lrs1_rtype;\n reg [1:0] stq_7_bits_uop_lrs2_rtype;\n reg stq_7_bits_uop_frs3_en;\n reg stq_7_bits_uop_fp_val;\n reg stq_7_bits_uop_fp_single;\n reg stq_7_bits_uop_xcpt_pf_if;\n reg stq_7_bits_uop_xcpt_ae_if;\n reg stq_7_bits_uop_xcpt_ma_if;\n reg stq_7_bits_uop_bp_debug_if;\n reg stq_7_bits_uop_bp_xcpt_if;\n reg [1:0] stq_7_bits_uop_debug_fsrc;\n reg [1:0] stq_7_bits_uop_debug_tsrc;\n reg stq_7_bits_addr_valid;\n reg [39:0] stq_7_bits_addr_bits;\n reg stq_7_bits_addr_is_virtual;\n reg stq_7_bits_data_valid;\n reg [63:0] stq_7_bits_data_bits;\n reg stq_7_bits_committed;\n reg stq_7_bits_succeeded;\n reg [2:0] ldq_head;\n reg [2:0] ldq_tail;\n reg [2:0] stq_head;\n reg [2:0] stq_tail;\n reg [2:0] stq_commit_head;\n reg [2:0] stq_execute_head;\n wire [7:0] _GEN_3 = {{stq_7_valid}, {stq_6_valid}, {stq_5_valid}, {stq_4_valid}, {stq_3_valid}, {stq_2_valid}, {stq_1_valid}, {stq_0_valid}};\n wire _GEN_4 = _GEN_3[stq_execute_head];\n wire [7:0][6:0] _GEN_5 = {{stq_7_bits_uop_uopc}, {stq_6_bits_uop_uopc}, {stq_5_bits_uop_uopc}, {stq_4_bits_uop_uopc}, {stq_3_bits_uop_uopc}, {stq_2_bits_uop_uopc}, {stq_1_bits_uop_uopc}, {stq_0_bits_uop_uopc}};\n wire [7:0][31:0] _GEN_6 = {{stq_7_bits_uop_inst}, {stq_6_bits_uop_inst}, {stq_5_bits_uop_inst}, {stq_4_bits_uop_inst}, {stq_3_bits_uop_inst}, {stq_2_bits_uop_inst}, {stq_1_bits_uop_inst}, {stq_0_bits_uop_inst}};\n wire [7:0][31:0] _GEN_7 = {{stq_7_bits_uop_debug_inst}, {stq_6_bits_uop_debug_inst}, {stq_5_bits_uop_debug_inst}, {stq_4_bits_uop_debug_inst}, {stq_3_bits_uop_debug_inst}, {stq_2_bits_uop_debug_inst}, {stq_1_bits_uop_debug_inst}, {stq_0_bits_uop_debug_inst}};\n wire [7:0] _GEN_8 = {{stq_7_bits_uop_is_rvc}, {stq_6_bits_uop_is_rvc}, {stq_5_bits_uop_is_rvc}, {stq_4_bits_uop_is_rvc}, {stq_3_bits_uop_is_rvc}, {stq_2_bits_uop_is_rvc}, {stq_1_bits_uop_is_rvc}, {stq_0_bits_uop_is_rvc}};\n wire [7:0][39:0] _GEN_9 = {{stq_7_bits_uop_debug_pc}, {stq_6_bits_uop_debug_pc}, {stq_5_bits_uop_debug_pc}, {stq_4_bits_uop_debug_pc}, {stq_3_bits_uop_debug_pc}, {stq_2_bits_uop_debug_pc}, {stq_1_bits_uop_debug_pc}, {stq_0_bits_uop_debug_pc}};\n wire [7:0][2:0] _GEN_10 = {{stq_7_bits_uop_iq_type}, {stq_6_bits_uop_iq_type}, {stq_5_bits_uop_iq_type}, {stq_4_bits_uop_iq_type}, {stq_3_bits_uop_iq_type}, {stq_2_bits_uop_iq_type}, {stq_1_bits_uop_iq_type}, {stq_0_bits_uop_iq_type}};\n wire [7:0][9:0] _GEN_11 = {{stq_7_bits_uop_fu_code}, {stq_6_bits_uop_fu_code}, {stq_5_bits_uop_fu_code}, {stq_4_bits_uop_fu_code}, {stq_3_bits_uop_fu_code}, {stq_2_bits_uop_fu_code}, {stq_1_bits_uop_fu_code}, {stq_0_bits_uop_fu_code}};\n wire [7:0][3:0] _GEN_12 = {{stq_7_bits_uop_ctrl_br_type}, {stq_6_bits_uop_ctrl_br_type}, {stq_5_bits_uop_ctrl_br_type}, {stq_4_bits_uop_ctrl_br_type}, {stq_3_bits_uop_ctrl_br_type}, {stq_2_bits_uop_ctrl_br_type}, {stq_1_bits_uop_ctrl_br_type}, {stq_0_bits_uop_ctrl_br_type}};\n wire [7:0][1:0] _GEN_13 = {{stq_7_bits_uop_ctrl_op1_sel}, {stq_6_bits_uop_ctrl_op1_sel}, {stq_5_bits_uop_ctrl_op1_sel}, {stq_4_bits_uop_ctrl_op1_sel}, {stq_3_bits_uop_ctrl_op1_sel}, {stq_2_bits_uop_ctrl_op1_sel}, {stq_1_bits_uop_ctrl_op1_sel}, {stq_0_bits_uop_ctrl_op1_sel}};\n wire [7:0][2:0] _GEN_14 = {{stq_7_bits_uop_ctrl_op2_sel}, {stq_6_bits_uop_ctrl_op2_sel}, {stq_5_bits_uop_ctrl_op2_sel}, {stq_4_bits_uop_ctrl_op2_sel}, {stq_3_bits_uop_ctrl_op2_sel}, {stq_2_bits_uop_ctrl_op2_sel}, {stq_1_bits_uop_ctrl_op2_sel}, {stq_0_bits_uop_ctrl_op2_sel}};\n wire [7:0][2:0] _GEN_15 = {{stq_7_bits_uop_ctrl_imm_sel}, {stq_6_bits_uop_ctrl_imm_sel}, {stq_5_bits_uop_ctrl_imm_sel}, {stq_4_bits_uop_ctrl_imm_sel}, {stq_3_bits_uop_ctrl_imm_sel}, {stq_2_bits_uop_ctrl_imm_sel}, {stq_1_bits_uop_ctrl_imm_sel}, {stq_0_bits_uop_ctrl_imm_sel}};\n wire [7:0][4:0] _GEN_16 = {{stq_7_bits_uop_ctrl_op_fcn}, {stq_6_bits_uop_ctrl_op_fcn}, {stq_5_bits_uop_ctrl_op_fcn}, {stq_4_bits_uop_ctrl_op_fcn}, {stq_3_bits_uop_ctrl_op_fcn}, {stq_2_bits_uop_ctrl_op_fcn}, {stq_1_bits_uop_ctrl_op_fcn}, {stq_0_bits_uop_ctrl_op_fcn}};\n wire [7:0] _GEN_17 = {{stq_7_bits_uop_ctrl_fcn_dw}, {stq_6_bits_uop_ctrl_fcn_dw}, {stq_5_bits_uop_ctrl_fcn_dw}, {stq_4_bits_uop_ctrl_fcn_dw}, {stq_3_bits_uop_ctrl_fcn_dw}, {stq_2_bits_uop_ctrl_fcn_dw}, {stq_1_bits_uop_ctrl_fcn_dw}, {stq_0_bits_uop_ctrl_fcn_dw}};\n wire [7:0][2:0] _GEN_18 = {{stq_7_bits_uop_ctrl_csr_cmd}, {stq_6_bits_uop_ctrl_csr_cmd}, {stq_5_bits_uop_ctrl_csr_cmd}, {stq_4_bits_uop_ctrl_csr_cmd}, {stq_3_bits_uop_ctrl_csr_cmd}, {stq_2_bits_uop_ctrl_csr_cmd}, {stq_1_bits_uop_ctrl_csr_cmd}, {stq_0_bits_uop_ctrl_csr_cmd}};\n wire [7:0] _GEN_19 = {{stq_7_bits_uop_ctrl_is_load}, {stq_6_bits_uop_ctrl_is_load}, {stq_5_bits_uop_ctrl_is_load}, {stq_4_bits_uop_ctrl_is_load}, {stq_3_bits_uop_ctrl_is_load}, {stq_2_bits_uop_ctrl_is_load}, {stq_1_bits_uop_ctrl_is_load}, {stq_0_bits_uop_ctrl_is_load}};\n wire [7:0] _GEN_20 = {{stq_7_bits_uop_ctrl_is_sta}, {stq_6_bits_uop_ctrl_is_sta}, {stq_5_bits_uop_ctrl_is_sta}, {stq_4_bits_uop_ctrl_is_sta}, {stq_3_bits_uop_ctrl_is_sta}, {stq_2_bits_uop_ctrl_is_sta}, {stq_1_bits_uop_ctrl_is_sta}, {stq_0_bits_uop_ctrl_is_sta}};\n wire [7:0] _GEN_21 = {{stq_7_bits_uop_ctrl_is_std}, {stq_6_bits_uop_ctrl_is_std}, {stq_5_bits_uop_ctrl_is_std}, {stq_4_bits_uop_ctrl_is_std}, {stq_3_bits_uop_ctrl_is_std}, {stq_2_bits_uop_ctrl_is_std}, {stq_1_bits_uop_ctrl_is_std}, {stq_0_bits_uop_ctrl_is_std}};\n wire [7:0][1:0] _GEN_22 = {{stq_7_bits_uop_iw_state}, {stq_6_bits_uop_iw_state}, {stq_5_bits_uop_iw_state}, {stq_4_bits_uop_iw_state}, {stq_3_bits_uop_iw_state}, {stq_2_bits_uop_iw_state}, {stq_1_bits_uop_iw_state}, {stq_0_bits_uop_iw_state}};\n wire [7:0] _GEN_23 = {{stq_7_bits_uop_iw_p1_poisoned}, {stq_6_bits_uop_iw_p1_poisoned}, {stq_5_bits_uop_iw_p1_poisoned}, {stq_4_bits_uop_iw_p1_poisoned}, {stq_3_bits_uop_iw_p1_poisoned}, {stq_2_bits_uop_iw_p1_poisoned}, {stq_1_bits_uop_iw_p1_poisoned}, {stq_0_bits_uop_iw_p1_poisoned}};\n wire [7:0] _GEN_24 = {{stq_7_bits_uop_iw_p2_poisoned}, {stq_6_bits_uop_iw_p2_poisoned}, {stq_5_bits_uop_iw_p2_poisoned}, {stq_4_bits_uop_iw_p2_poisoned}, {stq_3_bits_uop_iw_p2_poisoned}, {stq_2_bits_uop_iw_p2_poisoned}, {stq_1_bits_uop_iw_p2_poisoned}, {stq_0_bits_uop_iw_p2_poisoned}};\n wire [7:0] _GEN_25 = {{stq_7_bits_uop_is_br}, {stq_6_bits_uop_is_br}, {stq_5_bits_uop_is_br}, {stq_4_bits_uop_is_br}, {stq_3_bits_uop_is_br}, {stq_2_bits_uop_is_br}, {stq_1_bits_uop_is_br}, {stq_0_bits_uop_is_br}};\n wire [7:0] _GEN_26 = {{stq_7_bits_uop_is_jalr}, {stq_6_bits_uop_is_jalr}, {stq_5_bits_uop_is_jalr}, {stq_4_bits_uop_is_jalr}, {stq_3_bits_uop_is_jalr}, {stq_2_bits_uop_is_jalr}, {stq_1_bits_uop_is_jalr}, {stq_0_bits_uop_is_jalr}};\n wire [7:0] _GEN_27 = {{stq_7_bits_uop_is_jal}, {stq_6_bits_uop_is_jal}, {stq_5_bits_uop_is_jal}, {stq_4_bits_uop_is_jal}, {stq_3_bits_uop_is_jal}, {stq_2_bits_uop_is_jal}, {stq_1_bits_uop_is_jal}, {stq_0_bits_uop_is_jal}};\n wire [7:0] _GEN_28 = {{stq_7_bits_uop_is_sfb}, {stq_6_bits_uop_is_sfb}, {stq_5_bits_uop_is_sfb}, {stq_4_bits_uop_is_sfb}, {stq_3_bits_uop_is_sfb}, {stq_2_bits_uop_is_sfb}, {stq_1_bits_uop_is_sfb}, {stq_0_bits_uop_is_sfb}};\n wire [7:0][7:0] _GEN_29 = {{stq_7_bits_uop_br_mask}, {stq_6_bits_uop_br_mask}, {stq_5_bits_uop_br_mask}, {stq_4_bits_uop_br_mask}, {stq_3_bits_uop_br_mask}, {stq_2_bits_uop_br_mask}, {stq_1_bits_uop_br_mask}, {stq_0_bits_uop_br_mask}};\n wire [7:0][2:0] _GEN_30 = {{stq_7_bits_uop_br_tag}, {stq_6_bits_uop_br_tag}, {stq_5_bits_uop_br_tag}, {stq_4_bits_uop_br_tag}, {stq_3_bits_uop_br_tag}, {stq_2_bits_uop_br_tag}, {stq_1_bits_uop_br_tag}, {stq_0_bits_uop_br_tag}};\n wire [7:0][3:0] _GEN_31 = {{stq_7_bits_uop_ftq_idx}, {stq_6_bits_uop_ftq_idx}, {stq_5_bits_uop_ftq_idx}, {stq_4_bits_uop_ftq_idx}, {stq_3_bits_uop_ftq_idx}, {stq_2_bits_uop_ftq_idx}, {stq_1_bits_uop_ftq_idx}, {stq_0_bits_uop_ftq_idx}};\n wire [7:0] _GEN_32 = {{stq_7_bits_uop_edge_inst}, {stq_6_bits_uop_edge_inst}, {stq_5_bits_uop_edge_inst}, {stq_4_bits_uop_edge_inst}, {stq_3_bits_uop_edge_inst}, {stq_2_bits_uop_edge_inst}, {stq_1_bits_uop_edge_inst}, {stq_0_bits_uop_edge_inst}};\n wire [7:0][5:0] _GEN_33 = {{stq_7_bits_uop_pc_lob}, {stq_6_bits_uop_pc_lob}, {stq_5_bits_uop_pc_lob}, {stq_4_bits_uop_pc_lob}, {stq_3_bits_uop_pc_lob}, {stq_2_bits_uop_pc_lob}, {stq_1_bits_uop_pc_lob}, {stq_0_bits_uop_pc_lob}};\n wire [7:0] _GEN_34 = {{stq_7_bits_uop_taken}, {stq_6_bits_uop_taken}, {stq_5_bits_uop_taken}, {stq_4_bits_uop_taken}, {stq_3_bits_uop_taken}, {stq_2_bits_uop_taken}, {stq_1_bits_uop_taken}, {stq_0_bits_uop_taken}};\n wire [7:0][19:0] _GEN_35 = {{stq_7_bits_uop_imm_packed}, {stq_6_bits_uop_imm_packed}, {stq_5_bits_uop_imm_packed}, {stq_4_bits_uop_imm_packed}, {stq_3_bits_uop_imm_packed}, {stq_2_bits_uop_imm_packed}, {stq_1_bits_uop_imm_packed}, {stq_0_bits_uop_imm_packed}};\n wire [7:0][11:0] _GEN_36 = {{stq_7_bits_uop_csr_addr}, {stq_6_bits_uop_csr_addr}, {stq_5_bits_uop_csr_addr}, {stq_4_bits_uop_csr_addr}, {stq_3_bits_uop_csr_addr}, {stq_2_bits_uop_csr_addr}, {stq_1_bits_uop_csr_addr}, {stq_0_bits_uop_csr_addr}};\n wire [7:0][4:0] _GEN_37 = {{stq_7_bits_uop_rob_idx}, {stq_6_bits_uop_rob_idx}, {stq_5_bits_uop_rob_idx}, {stq_4_bits_uop_rob_idx}, {stq_3_bits_uop_rob_idx}, {stq_2_bits_uop_rob_idx}, {stq_1_bits_uop_rob_idx}, {stq_0_bits_uop_rob_idx}};\n wire [7:0][2:0] _GEN_38 = {{stq_7_bits_uop_ldq_idx}, {stq_6_bits_uop_ldq_idx}, {stq_5_bits_uop_ldq_idx}, {stq_4_bits_uop_ldq_idx}, {stq_3_bits_uop_ldq_idx}, {stq_2_bits_uop_ldq_idx}, {stq_1_bits_uop_ldq_idx}, {stq_0_bits_uop_ldq_idx}};\n wire [7:0][2:0] _GEN_39 = {{stq_7_bits_uop_stq_idx}, {stq_6_bits_uop_stq_idx}, {stq_5_bits_uop_stq_idx}, {stq_4_bits_uop_stq_idx}, {stq_3_bits_uop_stq_idx}, {stq_2_bits_uop_stq_idx}, {stq_1_bits_uop_stq_idx}, {stq_0_bits_uop_stq_idx}};\n wire [7:0][1:0] _GEN_40 = {{stq_7_bits_uop_rxq_idx}, {stq_6_bits_uop_rxq_idx}, {stq_5_bits_uop_rxq_idx}, {stq_4_bits_uop_rxq_idx}, {stq_3_bits_uop_rxq_idx}, {stq_2_bits_uop_rxq_idx}, {stq_1_bits_uop_rxq_idx}, {stq_0_bits_uop_rxq_idx}};\n wire [7:0][5:0] _GEN_41 = {{stq_7_bits_uop_pdst}, {stq_6_bits_uop_pdst}, {stq_5_bits_uop_pdst}, {stq_4_bits_uop_pdst}, {stq_3_bits_uop_pdst}, {stq_2_bits_uop_pdst}, {stq_1_bits_uop_pdst}, {stq_0_bits_uop_pdst}};\n wire [7:0][5:0] _GEN_42 = {{stq_7_bits_uop_prs1}, {stq_6_bits_uop_prs1}, {stq_5_bits_uop_prs1}, {stq_4_bits_uop_prs1}, {stq_3_bits_uop_prs1}, {stq_2_bits_uop_prs1}, {stq_1_bits_uop_prs1}, {stq_0_bits_uop_prs1}};\n wire [7:0][5:0] _GEN_43 = {{stq_7_bits_uop_prs2}, {stq_6_bits_uop_prs2}, {stq_5_bits_uop_prs2}, {stq_4_bits_uop_prs2}, {stq_3_bits_uop_prs2}, {stq_2_bits_uop_prs2}, {stq_1_bits_uop_prs2}, {stq_0_bits_uop_prs2}};\n wire [7:0][5:0] _GEN_44 = {{stq_7_bits_uop_prs3}, {stq_6_bits_uop_prs3}, {stq_5_bits_uop_prs3}, {stq_4_bits_uop_prs3}, {stq_3_bits_uop_prs3}, {stq_2_bits_uop_prs3}, {stq_1_bits_uop_prs3}, {stq_0_bits_uop_prs3}};\n wire [7:0][3:0] _GEN_45 = {{stq_7_bits_uop_ppred}, {stq_6_bits_uop_ppred}, {stq_5_bits_uop_ppred}, {stq_4_bits_uop_ppred}, {stq_3_bits_uop_ppred}, {stq_2_bits_uop_ppred}, {stq_1_bits_uop_ppred}, {stq_0_bits_uop_ppred}};\n wire [7:0] _GEN_46 = {{stq_7_bits_uop_prs1_busy}, {stq_6_bits_uop_prs1_busy}, {stq_5_bits_uop_prs1_busy}, {stq_4_bits_uop_prs1_busy}, {stq_3_bits_uop_prs1_busy}, {stq_2_bits_uop_prs1_busy}, {stq_1_bits_uop_prs1_busy}, {stq_0_bits_uop_prs1_busy}};\n wire [7:0] _GEN_47 = {{stq_7_bits_uop_prs2_busy}, {stq_6_bits_uop_prs2_busy}, {stq_5_bits_uop_prs2_busy}, {stq_4_bits_uop_prs2_busy}, {stq_3_bits_uop_prs2_busy}, {stq_2_bits_uop_prs2_busy}, {stq_1_bits_uop_prs2_busy}, {stq_0_bits_uop_prs2_busy}};\n wire [7:0] _GEN_48 = {{stq_7_bits_uop_prs3_busy}, {stq_6_bits_uop_prs3_busy}, {stq_5_bits_uop_prs3_busy}, {stq_4_bits_uop_prs3_busy}, {stq_3_bits_uop_prs3_busy}, {stq_2_bits_uop_prs3_busy}, {stq_1_bits_uop_prs3_busy}, {stq_0_bits_uop_prs3_busy}};\n wire [7:0] _GEN_49 = {{stq_7_bits_uop_ppred_busy}, {stq_6_bits_uop_ppred_busy}, {stq_5_bits_uop_ppred_busy}, {stq_4_bits_uop_ppred_busy}, {stq_3_bits_uop_ppred_busy}, {stq_2_bits_uop_ppred_busy}, {stq_1_bits_uop_ppred_busy}, {stq_0_bits_uop_ppred_busy}};\n wire [7:0][5:0] _GEN_50 = {{stq_7_bits_uop_stale_pdst}, {stq_6_bits_uop_stale_pdst}, {stq_5_bits_uop_stale_pdst}, {stq_4_bits_uop_stale_pdst}, {stq_3_bits_uop_stale_pdst}, {stq_2_bits_uop_stale_pdst}, {stq_1_bits_uop_stale_pdst}, {stq_0_bits_uop_stale_pdst}};\n wire [7:0] _GEN_51 = {{stq_7_bits_uop_exception}, {stq_6_bits_uop_exception}, {stq_5_bits_uop_exception}, {stq_4_bits_uop_exception}, {stq_3_bits_uop_exception}, {stq_2_bits_uop_exception}, {stq_1_bits_uop_exception}, {stq_0_bits_uop_exception}};\n wire _GEN_52 = _GEN_51[stq_execute_head];\n wire [7:0][63:0] _GEN_53 = {{stq_7_bits_uop_exc_cause}, {stq_6_bits_uop_exc_cause}, {stq_5_bits_uop_exc_cause}, {stq_4_bits_uop_exc_cause}, {stq_3_bits_uop_exc_cause}, {stq_2_bits_uop_exc_cause}, {stq_1_bits_uop_exc_cause}, {stq_0_bits_uop_exc_cause}};\n wire [7:0] _GEN_54 = {{stq_7_bits_uop_bypassable}, {stq_6_bits_uop_bypassable}, {stq_5_bits_uop_bypassable}, {stq_4_bits_uop_bypassable}, {stq_3_bits_uop_bypassable}, {stq_2_bits_uop_bypassable}, {stq_1_bits_uop_bypassable}, {stq_0_bits_uop_bypassable}};\n wire [7:0][4:0] _GEN_55 = {{stq_7_bits_uop_mem_cmd}, {stq_6_bits_uop_mem_cmd}, {stq_5_bits_uop_mem_cmd}, {stq_4_bits_uop_mem_cmd}, {stq_3_bits_uop_mem_cmd}, {stq_2_bits_uop_mem_cmd}, {stq_1_bits_uop_mem_cmd}, {stq_0_bits_uop_mem_cmd}};\n wire [7:0][1:0] _GEN_56 = {{stq_7_bits_uop_mem_size}, {stq_6_bits_uop_mem_size}, {stq_5_bits_uop_mem_size}, {stq_4_bits_uop_mem_size}, {stq_3_bits_uop_mem_size}, {stq_2_bits_uop_mem_size}, {stq_1_bits_uop_mem_size}, {stq_0_bits_uop_mem_size}};\n wire [1:0] dmem_req_0_bits_data_size = _GEN_56[stq_execute_head];\n wire [7:0] _GEN_57 = {{stq_7_bits_uop_mem_signed}, {stq_6_bits_uop_mem_signed}, {stq_5_bits_uop_mem_signed}, {stq_4_bits_uop_mem_signed}, {stq_3_bits_uop_mem_signed}, {stq_2_bits_uop_mem_signed}, {stq_1_bits_uop_mem_signed}, {stq_0_bits_uop_mem_signed}};\n wire [7:0] _GEN_58 = {{stq_7_bits_uop_is_fence}, {stq_6_bits_uop_is_fence}, {stq_5_bits_uop_is_fence}, {stq_4_bits_uop_is_fence}, {stq_3_bits_uop_is_fence}, {stq_2_bits_uop_is_fence}, {stq_1_bits_uop_is_fence}, {stq_0_bits_uop_is_fence}};\n wire _GEN_59 = _GEN_58[stq_execute_head];\n wire [7:0] _GEN_60 = {{stq_7_bits_uop_is_fencei}, {stq_6_bits_uop_is_fencei}, {stq_5_bits_uop_is_fencei}, {stq_4_bits_uop_is_fencei}, {stq_3_bits_uop_is_fencei}, {stq_2_bits_uop_is_fencei}, {stq_1_bits_uop_is_fencei}, {stq_0_bits_uop_is_fencei}};\n wire [7:0] _GEN_61 = {{stq_7_bits_uop_is_amo}, {stq_6_bits_uop_is_amo}, {stq_5_bits_uop_is_amo}, {stq_4_bits_uop_is_amo}, {stq_3_bits_uop_is_amo}, {stq_2_bits_uop_is_amo}, {stq_1_bits_uop_is_amo}, {stq_0_bits_uop_is_amo}};\n wire _GEN_62 = _GEN_61[stq_execute_head];\n wire [7:0] _GEN_63 = {{stq_7_bits_uop_uses_ldq}, {stq_6_bits_uop_uses_ldq}, {stq_5_bits_uop_uses_ldq}, {stq_4_bits_uop_uses_ldq}, {stq_3_bits_uop_uses_ldq}, {stq_2_bits_uop_uses_ldq}, {stq_1_bits_uop_uses_ldq}, {stq_0_bits_uop_uses_ldq}};\n wire [7:0] _GEN_64 = {{stq_7_bits_uop_uses_stq}, {stq_6_bits_uop_uses_stq}, {stq_5_bits_uop_uses_stq}, {stq_4_bits_uop_uses_stq}, {stq_3_bits_uop_uses_stq}, {stq_2_bits_uop_uses_stq}, {stq_1_bits_uop_uses_stq}, {stq_0_bits_uop_uses_stq}};\n wire [7:0] _GEN_65 = {{stq_7_bits_uop_is_sys_pc2epc}, {stq_6_bits_uop_is_sys_pc2epc}, {stq_5_bits_uop_is_sys_pc2epc}, {stq_4_bits_uop_is_sys_pc2epc}, {stq_3_bits_uop_is_sys_pc2epc}, {stq_2_bits_uop_is_sys_pc2epc}, {stq_1_bits_uop_is_sys_pc2epc}, {stq_0_bits_uop_is_sys_pc2epc}};\n wire [7:0] _GEN_66 = {{stq_7_bits_uop_is_unique}, {stq_6_bits_uop_is_unique}, {stq_5_bits_uop_is_unique}, {stq_4_bits_uop_is_unique}, {stq_3_bits_uop_is_unique}, {stq_2_bits_uop_is_unique}, {stq_1_bits_uop_is_unique}, {stq_0_bits_uop_is_unique}};\n wire [7:0] _GEN_67 = {{stq_7_bits_uop_flush_on_commit}, {stq_6_bits_uop_flush_on_commit}, {stq_5_bits_uop_flush_on_commit}, {stq_4_bits_uop_flush_on_commit}, {stq_3_bits_uop_flush_on_commit}, {stq_2_bits_uop_flush_on_commit}, {stq_1_bits_uop_flush_on_commit}, {stq_0_bits_uop_flush_on_commit}};\n wire [7:0] _GEN_68 = {{stq_7_bits_uop_ldst_is_rs1}, {stq_6_bits_uop_ldst_is_rs1}, {stq_5_bits_uop_ldst_is_rs1}, {stq_4_bits_uop_ldst_is_rs1}, {stq_3_bits_uop_ldst_is_rs1}, {stq_2_bits_uop_ldst_is_rs1}, {stq_1_bits_uop_ldst_is_rs1}, {stq_0_bits_uop_ldst_is_rs1}};\n wire [7:0][5:0] _GEN_69 = {{stq_7_bits_uop_ldst}, {stq_6_bits_uop_ldst}, {stq_5_bits_uop_ldst}, {stq_4_bits_uop_ldst}, {stq_3_bits_uop_ldst}, {stq_2_bits_uop_ldst}, {stq_1_bits_uop_ldst}, {stq_0_bits_uop_ldst}};\n wire [7:0][5:0] _GEN_70 = {{stq_7_bits_uop_lrs1}, {stq_6_bits_uop_lrs1}, {stq_5_bits_uop_lrs1}, {stq_4_bits_uop_lrs1}, {stq_3_bits_uop_lrs1}, {stq_2_bits_uop_lrs1}, {stq_1_bits_uop_lrs1}, {stq_0_bits_uop_lrs1}};\n wire [7:0][5:0] _GEN_71 = {{stq_7_bits_uop_lrs2}, {stq_6_bits_uop_lrs2}, {stq_5_bits_uop_lrs2}, {stq_4_bits_uop_lrs2}, {stq_3_bits_uop_lrs2}, {stq_2_bits_uop_lrs2}, {stq_1_bits_uop_lrs2}, {stq_0_bits_uop_lrs2}};\n wire [7:0][5:0] _GEN_72 = {{stq_7_bits_uop_lrs3}, {stq_6_bits_uop_lrs3}, {stq_5_bits_uop_lrs3}, {stq_4_bits_uop_lrs3}, {stq_3_bits_uop_lrs3}, {stq_2_bits_uop_lrs3}, {stq_1_bits_uop_lrs3}, {stq_0_bits_uop_lrs3}};\n wire [7:0] _GEN_73 = {{stq_7_bits_uop_ldst_val}, {stq_6_bits_uop_ldst_val}, {stq_5_bits_uop_ldst_val}, {stq_4_bits_uop_ldst_val}, {stq_3_bits_uop_ldst_val}, {stq_2_bits_uop_ldst_val}, {stq_1_bits_uop_ldst_val}, {stq_0_bits_uop_ldst_val}};\n wire [7:0][1:0] _GEN_74 = {{stq_7_bits_uop_dst_rtype}, {stq_6_bits_uop_dst_rtype}, {stq_5_bits_uop_dst_rtype}, {stq_4_bits_uop_dst_rtype}, {stq_3_bits_uop_dst_rtype}, {stq_2_bits_uop_dst_rtype}, {stq_1_bits_uop_dst_rtype}, {stq_0_bits_uop_dst_rtype}};\n wire [7:0][1:0] _GEN_75 = {{stq_7_bits_uop_lrs1_rtype}, {stq_6_bits_uop_lrs1_rtype}, {stq_5_bits_uop_lrs1_rtype}, {stq_4_bits_uop_lrs1_rtype}, {stq_3_bits_uop_lrs1_rtype}, {stq_2_bits_uop_lrs1_rtype}, {stq_1_bits_uop_lrs1_rtype}, {stq_0_bits_uop_lrs1_rtype}};\n wire [7:0][1:0] _GEN_76 = {{stq_7_bits_uop_lrs2_rtype}, {stq_6_bits_uop_lrs2_rtype}, {stq_5_bits_uop_lrs2_rtype}, {stq_4_bits_uop_lrs2_rtype}, {stq_3_bits_uop_lrs2_rtype}, {stq_2_bits_uop_lrs2_rtype}, {stq_1_bits_uop_lrs2_rtype}, {stq_0_bits_uop_lrs2_rtype}};\n wire [7:0] _GEN_77 = {{stq_7_bits_uop_frs3_en}, {stq_6_bits_uop_frs3_en}, {stq_5_bits_uop_frs3_en}, {stq_4_bits_uop_frs3_en}, {stq_3_bits_uop_frs3_en}, {stq_2_bits_uop_frs3_en}, {stq_1_bits_uop_frs3_en}, {stq_0_bits_uop_frs3_en}};\n wire [7:0] _GEN_78 = {{stq_7_bits_uop_fp_val}, {stq_6_bits_uop_fp_val}, {stq_5_bits_uop_fp_val}, {stq_4_bits_uop_fp_val}, {stq_3_bits_uop_fp_val}, {stq_2_bits_uop_fp_val}, {stq_1_bits_uop_fp_val}, {stq_0_bits_uop_fp_val}};\n wire [7:0] _GEN_79 = {{stq_7_bits_uop_fp_single}, {stq_6_bits_uop_fp_single}, {stq_5_bits_uop_fp_single}, {stq_4_bits_uop_fp_single}, {stq_3_bits_uop_fp_single}, {stq_2_bits_uop_fp_single}, {stq_1_bits_uop_fp_single}, {stq_0_bits_uop_fp_single}};\n wire [7:0] _GEN_80 = {{stq_7_bits_uop_xcpt_pf_if}, {stq_6_bits_uop_xcpt_pf_if}, {stq_5_bits_uop_xcpt_pf_if}, {stq_4_bits_uop_xcpt_pf_if}, {stq_3_bits_uop_xcpt_pf_if}, {stq_2_bits_uop_xcpt_pf_if}, {stq_1_bits_uop_xcpt_pf_if}, {stq_0_bits_uop_xcpt_pf_if}};\n wire [7:0] _GEN_81 = {{stq_7_bits_uop_xcpt_ae_if}, {stq_6_bits_uop_xcpt_ae_if}, {stq_5_bits_uop_xcpt_ae_if}, {stq_4_bits_uop_xcpt_ae_if}, {stq_3_bits_uop_xcpt_ae_if}, {stq_2_bits_uop_xcpt_ae_if}, {stq_1_bits_uop_xcpt_ae_if}, {stq_0_bits_uop_xcpt_ae_if}};\n wire [7:0] _GEN_82 = {{stq_7_bits_uop_xcpt_ma_if}, {stq_6_bits_uop_xcpt_ma_if}, {stq_5_bits_uop_xcpt_ma_if}, {stq_4_bits_uop_xcpt_ma_if}, {stq_3_bits_uop_xcpt_ma_if}, {stq_2_bits_uop_xcpt_ma_if}, {stq_1_bits_uop_xcpt_ma_if}, {stq_0_bits_uop_xcpt_ma_if}};\n wire [7:0] _GEN_83 = {{stq_7_bits_uop_bp_debug_if}, {stq_6_bits_uop_bp_debug_if}, {stq_5_bits_uop_bp_debug_if}, {stq_4_bits_uop_bp_debug_if}, {stq_3_bits_uop_bp_debug_if}, {stq_2_bits_uop_bp_debug_if}, {stq_1_bits_uop_bp_debug_if}, {stq_0_bits_uop_bp_debug_if}};\n wire [7:0] _GEN_84 = {{stq_7_bits_uop_bp_xcpt_if}, {stq_6_bits_uop_bp_xcpt_if}, {stq_5_bits_uop_bp_xcpt_if}, {stq_4_bits_uop_bp_xcpt_if}, {stq_3_bits_uop_bp_xcpt_if}, {stq_2_bits_uop_bp_xcpt_if}, {stq_1_bits_uop_bp_xcpt_if}, {stq_0_bits_uop_bp_xcpt_if}};\n wire [7:0][1:0] _GEN_85 = {{stq_7_bits_uop_debug_fsrc}, {stq_6_bits_uop_debug_fsrc}, {stq_5_bits_uop_debug_fsrc}, {stq_4_bits_uop_debug_fsrc}, {stq_3_bits_uop_debug_fsrc}, {stq_2_bits_uop_debug_fsrc}, {stq_1_bits_uop_debug_fsrc}, {stq_0_bits_uop_debug_fsrc}};\n wire [7:0][1:0] _GEN_86 = {{stq_7_bits_uop_debug_tsrc}, {stq_6_bits_uop_debug_tsrc}, {stq_5_bits_uop_debug_tsrc}, {stq_4_bits_uop_debug_tsrc}, {stq_3_bits_uop_debug_tsrc}, {stq_2_bits_uop_debug_tsrc}, {stq_1_bits_uop_debug_tsrc}, {stq_0_bits_uop_debug_tsrc}};\n wire [7:0] _GEN_87 = {{stq_7_bits_addr_valid}, {stq_6_bits_addr_valid}, {stq_5_bits_addr_valid}, {stq_4_bits_addr_valid}, {stq_3_bits_addr_valid}, {stq_2_bits_addr_valid}, {stq_1_bits_addr_valid}, {stq_0_bits_addr_valid}};\n wire [7:0][39:0] _GEN_88 = {{stq_7_bits_addr_bits}, {stq_6_bits_addr_bits}, {stq_5_bits_addr_bits}, {stq_4_bits_addr_bits}, {stq_3_bits_addr_bits}, {stq_2_bits_addr_bits}, {stq_1_bits_addr_bits}, {stq_0_bits_addr_bits}};\n wire [7:0] _GEN_89 = {{stq_7_bits_addr_is_virtual}, {stq_6_bits_addr_is_virtual}, {stq_5_bits_addr_is_virtual}, {stq_4_bits_addr_is_virtual}, {stq_3_bits_addr_is_virtual}, {stq_2_bits_addr_is_virtual}, {stq_1_bits_addr_is_virtual}, {stq_0_bits_addr_is_virtual}};\n wire [7:0] _GEN_90 = {{stq_7_bits_data_valid}, {stq_6_bits_data_valid}, {stq_5_bits_data_valid}, {stq_4_bits_data_valid}, {stq_3_bits_data_valid}, {stq_2_bits_data_valid}, {stq_1_bits_data_valid}, {stq_0_bits_data_valid}};\n wire [7:0][63:0] _GEN_91 = {{stq_7_bits_data_bits}, {stq_6_bits_data_bits}, {stq_5_bits_data_bits}, {stq_4_bits_data_bits}, {stq_3_bits_data_bits}, {stq_2_bits_data_bits}, {stq_1_bits_data_bits}, {stq_0_bits_data_bits}};\n wire [63:0] _GEN_92 = _GEN_91[stq_execute_head];\n wire [7:0] _GEN_93 = {{stq_7_bits_committed}, {stq_6_bits_committed}, {stq_5_bits_committed}, {stq_4_bits_committed}, {stq_3_bits_committed}, {stq_2_bits_committed}, {stq_1_bits_committed}, {stq_0_bits_committed}};\n reg [2:0] hella_state;\n reg [39:0] hella_req_addr;\n reg [63:0] hella_data_data;\n reg [31:0] hella_paddr;\n reg hella_xcpt_ma_ld;\n reg hella_xcpt_ma_st;\n reg hella_xcpt_pf_ld;\n reg hella_xcpt_pf_st;\n reg hella_xcpt_gf_ld;\n reg hella_xcpt_gf_st;\n reg hella_xcpt_ae_ld;\n reg hella_xcpt_ae_st;\n reg [7:0] live_store_mask;\n wire [2:0] _GEN_94 = ldq_tail + 3'h1;\n wire [2:0] _GEN_95 = stq_tail + 3'h1;\n wire dis_ld_val = io_core_dis_uops_0_valid & io_core_dis_uops_0_bits_uses_ldq & ~io_core_dis_uops_0_bits_exception;\n wire dis_st_val = io_core_dis_uops_0_valid & io_core_dis_uops_0_bits_uses_stq & ~io_core_dis_uops_0_bits_exception;\n wire [7:0] _GEN_96 = {{ldq_7_valid}, {ldq_6_valid}, {ldq_5_valid}, {ldq_4_valid}, {ldq_3_valid}, {ldq_2_valid}, {ldq_1_valid}, {ldq_0_valid}};\n reg p1_block_load_mask_0;\n reg p1_block_load_mask_1;\n reg p1_block_load_mask_2;\n reg p1_block_load_mask_3;\n reg p1_block_load_mask_4;\n reg p1_block_load_mask_5;\n reg p1_block_load_mask_6;\n reg p1_block_load_mask_7;\n reg p2_block_load_mask_0;\n reg p2_block_load_mask_1;\n reg p2_block_load_mask_2;\n reg p2_block_load_mask_3;\n reg p2_block_load_mask_4;\n reg p2_block_load_mask_5;\n reg p2_block_load_mask_6;\n reg p2_block_load_mask_7;\n wire [7:0][7:0] _GEN_97 = {{ldq_7_bits_uop_br_mask}, {ldq_6_bits_uop_br_mask}, {ldq_5_bits_uop_br_mask}, {ldq_4_bits_uop_br_mask}, {ldq_3_bits_uop_br_mask}, {ldq_2_bits_uop_br_mask}, {ldq_1_bits_uop_br_mask}, {ldq_0_bits_uop_br_mask}};\n wire [7:0][2:0] _GEN_98 = {{ldq_7_bits_uop_stq_idx}, {ldq_6_bits_uop_stq_idx}, {ldq_5_bits_uop_stq_idx}, {ldq_4_bits_uop_stq_idx}, {ldq_3_bits_uop_stq_idx}, {ldq_2_bits_uop_stq_idx}, {ldq_1_bits_uop_stq_idx}, {ldq_0_bits_uop_stq_idx}};\n wire [7:0][1:0] _GEN_99 = {{ldq_7_bits_uop_mem_size}, {ldq_6_bits_uop_mem_size}, {ldq_5_bits_uop_mem_size}, {ldq_4_bits_uop_mem_size}, {ldq_3_bits_uop_mem_size}, {ldq_2_bits_uop_mem_size}, {ldq_1_bits_uop_mem_size}, {ldq_0_bits_uop_mem_size}};\n wire [7:0] _GEN_100 = {{ldq_7_bits_addr_valid}, {ldq_6_bits_addr_valid}, {ldq_5_bits_addr_valid}, {ldq_4_bits_addr_valid}, {ldq_3_bits_addr_valid}, {ldq_2_bits_addr_valid}, {ldq_1_bits_addr_valid}, {ldq_0_bits_addr_valid}};\n wire [7:0] _GEN_101 = {{ldq_7_bits_executed}, {ldq_6_bits_executed}, {ldq_5_bits_executed}, {ldq_4_bits_executed}, {ldq_3_bits_executed}, {ldq_2_bits_executed}, {ldq_1_bits_executed}, {ldq_0_bits_executed}};\n wire [7:0][7:0] _GEN_102 = {{ldq_7_bits_st_dep_mask}, {ldq_6_bits_st_dep_mask}, {ldq_5_bits_st_dep_mask}, {ldq_4_bits_st_dep_mask}, {ldq_3_bits_st_dep_mask}, {ldq_2_bits_st_dep_mask}, {ldq_1_bits_st_dep_mask}, {ldq_0_bits_st_dep_mask}};\n reg [2:0] ldq_retry_idx;\n reg [2:0] stq_retry_idx;\n reg [2:0] ldq_wakeup_idx;\n wire will_fire_load_incoming_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_load;\n wire _can_fire_sta_incoming_T = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_sta;\n wire [7:0][6:0] _GEN_103 = {{ldq_7_bits_uop_uopc}, {ldq_6_bits_uop_uopc}, {ldq_5_bits_uop_uopc}, {ldq_4_bits_uop_uopc}, {ldq_3_bits_uop_uopc}, {ldq_2_bits_uop_uopc}, {ldq_1_bits_uop_uopc}, {ldq_0_bits_uop_uopc}};\n wire [7:0][31:0] _GEN_104 = {{ldq_7_bits_uop_inst}, {ldq_6_bits_uop_inst}, {ldq_5_bits_uop_inst}, {ldq_4_bits_uop_inst}, {ldq_3_bits_uop_inst}, {ldq_2_bits_uop_inst}, {ldq_1_bits_uop_inst}, {ldq_0_bits_uop_inst}};\n wire [7:0][31:0] _GEN_105 = {{ldq_7_bits_uop_debug_inst}, {ldq_6_bits_uop_debug_inst}, {ldq_5_bits_uop_debug_inst}, {ldq_4_bits_uop_debug_inst}, {ldq_3_bits_uop_debug_inst}, {ldq_2_bits_uop_debug_inst}, {ldq_1_bits_uop_debug_inst}, {ldq_0_bits_uop_debug_inst}};\n wire [7:0] _GEN_106 = {{ldq_7_bits_uop_is_rvc}, {ldq_6_bits_uop_is_rvc}, {ldq_5_bits_uop_is_rvc}, {ldq_4_bits_uop_is_rvc}, {ldq_3_bits_uop_is_rvc}, {ldq_2_bits_uop_is_rvc}, {ldq_1_bits_uop_is_rvc}, {ldq_0_bits_uop_is_rvc}};\n wire [7:0][39:0] _GEN_107 = {{ldq_7_bits_uop_debug_pc}, {ldq_6_bits_uop_debug_pc}, {ldq_5_bits_uop_debug_pc}, {ldq_4_bits_uop_debug_pc}, {ldq_3_bits_uop_debug_pc}, {ldq_2_bits_uop_debug_pc}, {ldq_1_bits_uop_debug_pc}, {ldq_0_bits_uop_debug_pc}};\n wire [7:0][2:0] _GEN_108 = {{ldq_7_bits_uop_iq_type}, {ldq_6_bits_uop_iq_type}, {ldq_5_bits_uop_iq_type}, {ldq_4_bits_uop_iq_type}, {ldq_3_bits_uop_iq_type}, {ldq_2_bits_uop_iq_type}, {ldq_1_bits_uop_iq_type}, {ldq_0_bits_uop_iq_type}};\n wire [7:0][9:0] _GEN_109 = {{ldq_7_bits_uop_fu_code}, {ldq_6_bits_uop_fu_code}, {ldq_5_bits_uop_fu_code}, {ldq_4_bits_uop_fu_code}, {ldq_3_bits_uop_fu_code}, {ldq_2_bits_uop_fu_code}, {ldq_1_bits_uop_fu_code}, {ldq_0_bits_uop_fu_code}};\n wire [7:0][3:0] _GEN_110 = {{ldq_7_bits_uop_ctrl_br_type}, {ldq_6_bits_uop_ctrl_br_type}, {ldq_5_bits_uop_ctrl_br_type}, {ldq_4_bits_uop_ctrl_br_type}, {ldq_3_bits_uop_ctrl_br_type}, {ldq_2_bits_uop_ctrl_br_type}, {ldq_1_bits_uop_ctrl_br_type}, {ldq_0_bits_uop_ctrl_br_type}};\n wire [7:0][1:0] _GEN_111 = {{ldq_7_bits_uop_ctrl_op1_sel}, {ldq_6_bits_uop_ctrl_op1_sel}, {ldq_5_bits_uop_ctrl_op1_sel}, {ldq_4_bits_uop_ctrl_op1_sel}, {ldq_3_bits_uop_ctrl_op1_sel}, {ldq_2_bits_uop_ctrl_op1_sel}, {ldq_1_bits_uop_ctrl_op1_sel}, {ldq_0_bits_uop_ctrl_op1_sel}};\n wire [7:0][2:0] _GEN_112 = {{ldq_7_bits_uop_ctrl_op2_sel}, {ldq_6_bits_uop_ctrl_op2_sel}, {ldq_5_bits_uop_ctrl_op2_sel}, {ldq_4_bits_uop_ctrl_op2_sel}, {ldq_3_bits_uop_ctrl_op2_sel}, {ldq_2_bits_uop_ctrl_op2_sel}, {ldq_1_bits_uop_ctrl_op2_sel}, {ldq_0_bits_uop_ctrl_op2_sel}};\n wire [7:0][2:0] _GEN_113 = {{ldq_7_bits_uop_ctrl_imm_sel}, {ldq_6_bits_uop_ctrl_imm_sel}, {ldq_5_bits_uop_ctrl_imm_sel}, {ldq_4_bits_uop_ctrl_imm_sel}, {ldq_3_bits_uop_ctrl_imm_sel}, {ldq_2_bits_uop_ctrl_imm_sel}, {ldq_1_bits_uop_ctrl_imm_sel}, {ldq_0_bits_uop_ctrl_imm_sel}};\n wire [7:0][4:0] _GEN_114 = {{ldq_7_bits_uop_ctrl_op_fcn}, {ldq_6_bits_uop_ctrl_op_fcn}, {ldq_5_bits_uop_ctrl_op_fcn}, {ldq_4_bits_uop_ctrl_op_fcn}, {ldq_3_bits_uop_ctrl_op_fcn}, {ldq_2_bits_uop_ctrl_op_fcn}, {ldq_1_bits_uop_ctrl_op_fcn}, {ldq_0_bits_uop_ctrl_op_fcn}};\n wire [7:0] _GEN_115 = {{ldq_7_bits_uop_ctrl_fcn_dw}, {ldq_6_bits_uop_ctrl_fcn_dw}, {ldq_5_bits_uop_ctrl_fcn_dw}, {ldq_4_bits_uop_ctrl_fcn_dw}, {ldq_3_bits_uop_ctrl_fcn_dw}, {ldq_2_bits_uop_ctrl_fcn_dw}, {ldq_1_bits_uop_ctrl_fcn_dw}, {ldq_0_bits_uop_ctrl_fcn_dw}};\n wire [7:0][2:0] _GEN_116 = {{ldq_7_bits_uop_ctrl_csr_cmd}, {ldq_6_bits_uop_ctrl_csr_cmd}, {ldq_5_bits_uop_ctrl_csr_cmd}, {ldq_4_bits_uop_ctrl_csr_cmd}, {ldq_3_bits_uop_ctrl_csr_cmd}, {ldq_2_bits_uop_ctrl_csr_cmd}, {ldq_1_bits_uop_ctrl_csr_cmd}, {ldq_0_bits_uop_ctrl_csr_cmd}};\n wire [7:0] _GEN_117 = {{ldq_7_bits_uop_ctrl_is_load}, {ldq_6_bits_uop_ctrl_is_load}, {ldq_5_bits_uop_ctrl_is_load}, {ldq_4_bits_uop_ctrl_is_load}, {ldq_3_bits_uop_ctrl_is_load}, {ldq_2_bits_uop_ctrl_is_load}, {ldq_1_bits_uop_ctrl_is_load}, {ldq_0_bits_uop_ctrl_is_load}};\n wire [7:0] _GEN_118 = {{ldq_7_bits_uop_ctrl_is_sta}, {ldq_6_bits_uop_ctrl_is_sta}, {ldq_5_bits_uop_ctrl_is_sta}, {ldq_4_bits_uop_ctrl_is_sta}, {ldq_3_bits_uop_ctrl_is_sta}, {ldq_2_bits_uop_ctrl_is_sta}, {ldq_1_bits_uop_ctrl_is_sta}, {ldq_0_bits_uop_ctrl_is_sta}};\n wire [7:0] _GEN_119 = {{ldq_7_bits_uop_ctrl_is_std}, {ldq_6_bits_uop_ctrl_is_std}, {ldq_5_bits_uop_ctrl_is_std}, {ldq_4_bits_uop_ctrl_is_std}, {ldq_3_bits_uop_ctrl_is_std}, {ldq_2_bits_uop_ctrl_is_std}, {ldq_1_bits_uop_ctrl_is_std}, {ldq_0_bits_uop_ctrl_is_std}};\n wire [7:0][1:0] _GEN_120 = {{ldq_7_bits_uop_iw_state}, {ldq_6_bits_uop_iw_state}, {ldq_5_bits_uop_iw_state}, {ldq_4_bits_uop_iw_state}, {ldq_3_bits_uop_iw_state}, {ldq_2_bits_uop_iw_state}, {ldq_1_bits_uop_iw_state}, {ldq_0_bits_uop_iw_state}};\n wire [7:0] _GEN_121 = {{ldq_7_bits_uop_iw_p1_poisoned}, {ldq_6_bits_uop_iw_p1_poisoned}, {ldq_5_bits_uop_iw_p1_poisoned}, {ldq_4_bits_uop_iw_p1_poisoned}, {ldq_3_bits_uop_iw_p1_poisoned}, {ldq_2_bits_uop_iw_p1_poisoned}, {ldq_1_bits_uop_iw_p1_poisoned}, {ldq_0_bits_uop_iw_p1_poisoned}};\n wire [7:0] _GEN_122 = {{ldq_7_bits_uop_iw_p2_poisoned}, {ldq_6_bits_uop_iw_p2_poisoned}, {ldq_5_bits_uop_iw_p2_poisoned}, {ldq_4_bits_uop_iw_p2_poisoned}, {ldq_3_bits_uop_iw_p2_poisoned}, {ldq_2_bits_uop_iw_p2_poisoned}, {ldq_1_bits_uop_iw_p2_poisoned}, {ldq_0_bits_uop_iw_p2_poisoned}};\n wire [7:0] _GEN_123 = {{ldq_7_bits_uop_is_br}, {ldq_6_bits_uop_is_br}, {ldq_5_bits_uop_is_br}, {ldq_4_bits_uop_is_br}, {ldq_3_bits_uop_is_br}, {ldq_2_bits_uop_is_br}, {ldq_1_bits_uop_is_br}, {ldq_0_bits_uop_is_br}};\n wire [7:0] _GEN_124 = {{ldq_7_bits_uop_is_jalr}, {ldq_6_bits_uop_is_jalr}, {ldq_5_bits_uop_is_jalr}, {ldq_4_bits_uop_is_jalr}, {ldq_3_bits_uop_is_jalr}, {ldq_2_bits_uop_is_jalr}, {ldq_1_bits_uop_is_jalr}, {ldq_0_bits_uop_is_jalr}};\n wire [7:0] _GEN_125 = {{ldq_7_bits_uop_is_jal}, {ldq_6_bits_uop_is_jal}, {ldq_5_bits_uop_is_jal}, {ldq_4_bits_uop_is_jal}, {ldq_3_bits_uop_is_jal}, {ldq_2_bits_uop_is_jal}, {ldq_1_bits_uop_is_jal}, {ldq_0_bits_uop_is_jal}};\n wire [7:0] _GEN_126 = {{ldq_7_bits_uop_is_sfb}, {ldq_6_bits_uop_is_sfb}, {ldq_5_bits_uop_is_sfb}, {ldq_4_bits_uop_is_sfb}, {ldq_3_bits_uop_is_sfb}, {ldq_2_bits_uop_is_sfb}, {ldq_1_bits_uop_is_sfb}, {ldq_0_bits_uop_is_sfb}};\n wire [7:0] _GEN_127 = _GEN_97[ldq_retry_idx];\n wire [7:0][2:0] _GEN_128 = {{ldq_7_bits_uop_br_tag}, {ldq_6_bits_uop_br_tag}, {ldq_5_bits_uop_br_tag}, {ldq_4_bits_uop_br_tag}, {ldq_3_bits_uop_br_tag}, {ldq_2_bits_uop_br_tag}, {ldq_1_bits_uop_br_tag}, {ldq_0_bits_uop_br_tag}};\n wire [7:0][3:0] _GEN_129 = {{ldq_7_bits_uop_ftq_idx}, {ldq_6_bits_uop_ftq_idx}, {ldq_5_bits_uop_ftq_idx}, {ldq_4_bits_uop_ftq_idx}, {ldq_3_bits_uop_ftq_idx}, {ldq_2_bits_uop_ftq_idx}, {ldq_1_bits_uop_ftq_idx}, {ldq_0_bits_uop_ftq_idx}};\n wire [7:0] _GEN_130 = {{ldq_7_bits_uop_edge_inst}, {ldq_6_bits_uop_edge_inst}, {ldq_5_bits_uop_edge_inst}, {ldq_4_bits_uop_edge_inst}, {ldq_3_bits_uop_edge_inst}, {ldq_2_bits_uop_edge_inst}, {ldq_1_bits_uop_edge_inst}, {ldq_0_bits_uop_edge_inst}};\n wire [7:0][5:0] _GEN_131 = {{ldq_7_bits_uop_pc_lob}, {ldq_6_bits_uop_pc_lob}, {ldq_5_bits_uop_pc_lob}, {ldq_4_bits_uop_pc_lob}, {ldq_3_bits_uop_pc_lob}, {ldq_2_bits_uop_pc_lob}, {ldq_1_bits_uop_pc_lob}, {ldq_0_bits_uop_pc_lob}};\n wire [7:0] _GEN_132 = {{ldq_7_bits_uop_taken}, {ldq_6_bits_uop_taken}, {ldq_5_bits_uop_taken}, {ldq_4_bits_uop_taken}, {ldq_3_bits_uop_taken}, {ldq_2_bits_uop_taken}, {ldq_1_bits_uop_taken}, {ldq_0_bits_uop_taken}};\n wire [7:0][19:0] _GEN_133 = {{ldq_7_bits_uop_imm_packed}, {ldq_6_bits_uop_imm_packed}, {ldq_5_bits_uop_imm_packed}, {ldq_4_bits_uop_imm_packed}, {ldq_3_bits_uop_imm_packed}, {ldq_2_bits_uop_imm_packed}, {ldq_1_bits_uop_imm_packed}, {ldq_0_bits_uop_imm_packed}};\n wire [7:0][11:0] _GEN_134 = {{ldq_7_bits_uop_csr_addr}, {ldq_6_bits_uop_csr_addr}, {ldq_5_bits_uop_csr_addr}, {ldq_4_bits_uop_csr_addr}, {ldq_3_bits_uop_csr_addr}, {ldq_2_bits_uop_csr_addr}, {ldq_1_bits_uop_csr_addr}, {ldq_0_bits_uop_csr_addr}};\n wire [7:0][4:0] _GEN_135 = {{ldq_7_bits_uop_rob_idx}, {ldq_6_bits_uop_rob_idx}, {ldq_5_bits_uop_rob_idx}, {ldq_4_bits_uop_rob_idx}, {ldq_3_bits_uop_rob_idx}, {ldq_2_bits_uop_rob_idx}, {ldq_1_bits_uop_rob_idx}, {ldq_0_bits_uop_rob_idx}};\n wire [7:0][2:0] _GEN_136 = {{ldq_7_bits_uop_ldq_idx}, {ldq_6_bits_uop_ldq_idx}, {ldq_5_bits_uop_ldq_idx}, {ldq_4_bits_uop_ldq_idx}, {ldq_3_bits_uop_ldq_idx}, {ldq_2_bits_uop_ldq_idx}, {ldq_1_bits_uop_ldq_idx}, {ldq_0_bits_uop_ldq_idx}};\n wire [2:0] mem_ldq_retry_e_out_bits_uop_stq_idx = _GEN_98[ldq_retry_idx];\n wire [7:0][1:0] _GEN_137 = {{ldq_7_bits_uop_rxq_idx}, {ldq_6_bits_uop_rxq_idx}, {ldq_5_bits_uop_rxq_idx}, {ldq_4_bits_uop_rxq_idx}, {ldq_3_bits_uop_rxq_idx}, {ldq_2_bits_uop_rxq_idx}, {ldq_1_bits_uop_rxq_idx}, {ldq_0_bits_uop_rxq_idx}};\n wire [7:0][5:0] _GEN_138 = {{ldq_7_bits_uop_pdst}, {ldq_6_bits_uop_pdst}, {ldq_5_bits_uop_pdst}, {ldq_4_bits_uop_pdst}, {ldq_3_bits_uop_pdst}, {ldq_2_bits_uop_pdst}, {ldq_1_bits_uop_pdst}, {ldq_0_bits_uop_pdst}};\n wire [5:0] _GEN_139 = _GEN_138[ldq_retry_idx];\n wire [7:0][5:0] _GEN_140 = {{ldq_7_bits_uop_prs1}, {ldq_6_bits_uop_prs1}, {ldq_5_bits_uop_prs1}, {ldq_4_bits_uop_prs1}, {ldq_3_bits_uop_prs1}, {ldq_2_bits_uop_prs1}, {ldq_1_bits_uop_prs1}, {ldq_0_bits_uop_prs1}};\n wire [7:0][5:0] _GEN_141 = {{ldq_7_bits_uop_prs2}, {ldq_6_bits_uop_prs2}, {ldq_5_bits_uop_prs2}, {ldq_4_bits_uop_prs2}, {ldq_3_bits_uop_prs2}, {ldq_2_bits_uop_prs2}, {ldq_1_bits_uop_prs2}, {ldq_0_bits_uop_prs2}};\n wire [7:0][5:0] _GEN_142 = {{ldq_7_bits_uop_prs3}, {ldq_6_bits_uop_prs3}, {ldq_5_bits_uop_prs3}, {ldq_4_bits_uop_prs3}, {ldq_3_bits_uop_prs3}, {ldq_2_bits_uop_prs3}, {ldq_1_bits_uop_prs3}, {ldq_0_bits_uop_prs3}};\n wire [7:0] _GEN_143 = {{ldq_7_bits_uop_prs1_busy}, {ldq_6_bits_uop_prs1_busy}, {ldq_5_bits_uop_prs1_busy}, {ldq_4_bits_uop_prs1_busy}, {ldq_3_bits_uop_prs1_busy}, {ldq_2_bits_uop_prs1_busy}, {ldq_1_bits_uop_prs1_busy}, {ldq_0_bits_uop_prs1_busy}};\n wire [7:0] _GEN_144 = {{ldq_7_bits_uop_prs2_busy}, {ldq_6_bits_uop_prs2_busy}, {ldq_5_bits_uop_prs2_busy}, {ldq_4_bits_uop_prs2_busy}, {ldq_3_bits_uop_prs2_busy}, {ldq_2_bits_uop_prs2_busy}, {ldq_1_bits_uop_prs2_busy}, {ldq_0_bits_uop_prs2_busy}};\n wire [7:0] _GEN_145 = {{ldq_7_bits_uop_prs3_busy}, {ldq_6_bits_uop_prs3_busy}, {ldq_5_bits_uop_prs3_busy}, {ldq_4_bits_uop_prs3_busy}, {ldq_3_bits_uop_prs3_busy}, {ldq_2_bits_uop_prs3_busy}, {ldq_1_bits_uop_prs3_busy}, {ldq_0_bits_uop_prs3_busy}};\n wire [7:0][5:0] _GEN_146 = {{ldq_7_bits_uop_stale_pdst}, {ldq_6_bits_uop_stale_pdst}, {ldq_5_bits_uop_stale_pdst}, {ldq_4_bits_uop_stale_pdst}, {ldq_3_bits_uop_stale_pdst}, {ldq_2_bits_uop_stale_pdst}, {ldq_1_bits_uop_stale_pdst}, {ldq_0_bits_uop_stale_pdst}};\n wire [7:0] _GEN_147 = {{ldq_7_bits_uop_exception}, {ldq_6_bits_uop_exception}, {ldq_5_bits_uop_exception}, {ldq_4_bits_uop_exception}, {ldq_3_bits_uop_exception}, {ldq_2_bits_uop_exception}, {ldq_1_bits_uop_exception}, {ldq_0_bits_uop_exception}};\n wire [7:0][63:0] _GEN_148 = {{ldq_7_bits_uop_exc_cause}, {ldq_6_bits_uop_exc_cause}, {ldq_5_bits_uop_exc_cause}, {ldq_4_bits_uop_exc_cause}, {ldq_3_bits_uop_exc_cause}, {ldq_2_bits_uop_exc_cause}, {ldq_1_bits_uop_exc_cause}, {ldq_0_bits_uop_exc_cause}};\n wire [7:0] _GEN_149 = {{ldq_7_bits_uop_bypassable}, {ldq_6_bits_uop_bypassable}, {ldq_5_bits_uop_bypassable}, {ldq_4_bits_uop_bypassable}, {ldq_3_bits_uop_bypassable}, {ldq_2_bits_uop_bypassable}, {ldq_1_bits_uop_bypassable}, {ldq_0_bits_uop_bypassable}};\n wire [7:0][4:0] _GEN_150 = {{ldq_7_bits_uop_mem_cmd}, {ldq_6_bits_uop_mem_cmd}, {ldq_5_bits_uop_mem_cmd}, {ldq_4_bits_uop_mem_cmd}, {ldq_3_bits_uop_mem_cmd}, {ldq_2_bits_uop_mem_cmd}, {ldq_1_bits_uop_mem_cmd}, {ldq_0_bits_uop_mem_cmd}};\n wire [1:0] mem_ldq_retry_e_out_bits_uop_mem_size = _GEN_99[ldq_retry_idx];\n wire [7:0] _GEN_151 = {{ldq_7_bits_uop_mem_signed}, {ldq_6_bits_uop_mem_signed}, {ldq_5_bits_uop_mem_signed}, {ldq_4_bits_uop_mem_signed}, {ldq_3_bits_uop_mem_signed}, {ldq_2_bits_uop_mem_signed}, {ldq_1_bits_uop_mem_signed}, {ldq_0_bits_uop_mem_signed}};\n wire [7:0] _GEN_152 = {{ldq_7_bits_uop_is_fence}, {ldq_6_bits_uop_is_fence}, {ldq_5_bits_uop_is_fence}, {ldq_4_bits_uop_is_fence}, {ldq_3_bits_uop_is_fence}, {ldq_2_bits_uop_is_fence}, {ldq_1_bits_uop_is_fence}, {ldq_0_bits_uop_is_fence}};\n wire [7:0] _GEN_153 = {{ldq_7_bits_uop_is_fencei}, {ldq_6_bits_uop_is_fencei}, {ldq_5_bits_uop_is_fencei}, {ldq_4_bits_uop_is_fencei}, {ldq_3_bits_uop_is_fencei}, {ldq_2_bits_uop_is_fencei}, {ldq_1_bits_uop_is_fencei}, {ldq_0_bits_uop_is_fencei}};\n wire [7:0] _GEN_154 = {{ldq_7_bits_uop_is_amo}, {ldq_6_bits_uop_is_amo}, {ldq_5_bits_uop_is_amo}, {ldq_4_bits_uop_is_amo}, {ldq_3_bits_uop_is_amo}, {ldq_2_bits_uop_is_amo}, {ldq_1_bits_uop_is_amo}, {ldq_0_bits_uop_is_amo}};\n wire [7:0] _GEN_155 = {{ldq_7_bits_uop_uses_ldq}, {ldq_6_bits_uop_uses_ldq}, {ldq_5_bits_uop_uses_ldq}, {ldq_4_bits_uop_uses_ldq}, {ldq_3_bits_uop_uses_ldq}, {ldq_2_bits_uop_uses_ldq}, {ldq_1_bits_uop_uses_ldq}, {ldq_0_bits_uop_uses_ldq}};\n wire [7:0] _GEN_156 = {{ldq_7_bits_uop_uses_stq}, {ldq_6_bits_uop_uses_stq}, {ldq_5_bits_uop_uses_stq}, {ldq_4_bits_uop_uses_stq}, {ldq_3_bits_uop_uses_stq}, {ldq_2_bits_uop_uses_stq}, {ldq_1_bits_uop_uses_stq}, {ldq_0_bits_uop_uses_stq}};\n wire [7:0] _GEN_157 = {{ldq_7_bits_uop_is_sys_pc2epc}, {ldq_6_bits_uop_is_sys_pc2epc}, {ldq_5_bits_uop_is_sys_pc2epc}, {ldq_4_bits_uop_is_sys_pc2epc}, {ldq_3_bits_uop_is_sys_pc2epc}, {ldq_2_bits_uop_is_sys_pc2epc}, {ldq_1_bits_uop_is_sys_pc2epc}, {ldq_0_bits_uop_is_sys_pc2epc}};\n wire [7:0] _GEN_158 = {{ldq_7_bits_uop_is_unique}, {ldq_6_bits_uop_is_unique}, {ldq_5_bits_uop_is_unique}, {ldq_4_bits_uop_is_unique}, {ldq_3_bits_uop_is_unique}, {ldq_2_bits_uop_is_unique}, {ldq_1_bits_uop_is_unique}, {ldq_0_bits_uop_is_unique}};\n wire [7:0] _GEN_159 = {{ldq_7_bits_uop_flush_on_commit}, {ldq_6_bits_uop_flush_on_commit}, {ldq_5_bits_uop_flush_on_commit}, {ldq_4_bits_uop_flush_on_commit}, {ldq_3_bits_uop_flush_on_commit}, {ldq_2_bits_uop_flush_on_commit}, {ldq_1_bits_uop_flush_on_commit}, {ldq_0_bits_uop_flush_on_commit}};\n wire [7:0] _GEN_160 = {{ldq_7_bits_uop_ldst_is_rs1}, {ldq_6_bits_uop_ldst_is_rs1}, {ldq_5_bits_uop_ldst_is_rs1}, {ldq_4_bits_uop_ldst_is_rs1}, {ldq_3_bits_uop_ldst_is_rs1}, {ldq_2_bits_uop_ldst_is_rs1}, {ldq_1_bits_uop_ldst_is_rs1}, {ldq_0_bits_uop_ldst_is_rs1}};\n wire [7:0][5:0] _GEN_161 = {{ldq_7_bits_uop_ldst}, {ldq_6_bits_uop_ldst}, {ldq_5_bits_uop_ldst}, {ldq_4_bits_uop_ldst}, {ldq_3_bits_uop_ldst}, {ldq_2_bits_uop_ldst}, {ldq_1_bits_uop_ldst}, {ldq_0_bits_uop_ldst}};\n wire [7:0][5:0] _GEN_162 = {{ldq_7_bits_uop_lrs1}, {ldq_6_bits_uop_lrs1}, {ldq_5_bits_uop_lrs1}, {ldq_4_bits_uop_lrs1}, {ldq_3_bits_uop_lrs1}, {ldq_2_bits_uop_lrs1}, {ldq_1_bits_uop_lrs1}, {ldq_0_bits_uop_lrs1}};\n wire [7:0][5:0] _GEN_163 = {{ldq_7_bits_uop_lrs2}, {ldq_6_bits_uop_lrs2}, {ldq_5_bits_uop_lrs2}, {ldq_4_bits_uop_lrs2}, {ldq_3_bits_uop_lrs2}, {ldq_2_bits_uop_lrs2}, {ldq_1_bits_uop_lrs2}, {ldq_0_bits_uop_lrs2}};\n wire [7:0][5:0] _GEN_164 = {{ldq_7_bits_uop_lrs3}, {ldq_6_bits_uop_lrs3}, {ldq_5_bits_uop_lrs3}, {ldq_4_bits_uop_lrs3}, {ldq_3_bits_uop_lrs3}, {ldq_2_bits_uop_lrs3}, {ldq_1_bits_uop_lrs3}, {ldq_0_bits_uop_lrs3}};\n wire [7:0] _GEN_165 = {{ldq_7_bits_uop_ldst_val}, {ldq_6_bits_uop_ldst_val}, {ldq_5_bits_uop_ldst_val}, {ldq_4_bits_uop_ldst_val}, {ldq_3_bits_uop_ldst_val}, {ldq_2_bits_uop_ldst_val}, {ldq_1_bits_uop_ldst_val}, {ldq_0_bits_uop_ldst_val}};\n wire [7:0][1:0] _GEN_166 = {{ldq_7_bits_uop_dst_rtype}, {ldq_6_bits_uop_dst_rtype}, {ldq_5_bits_uop_dst_rtype}, {ldq_4_bits_uop_dst_rtype}, {ldq_3_bits_uop_dst_rtype}, {ldq_2_bits_uop_dst_rtype}, {ldq_1_bits_uop_dst_rtype}, {ldq_0_bits_uop_dst_rtype}};\n wire [7:0][1:0] _GEN_167 = {{ldq_7_bits_uop_lrs1_rtype}, {ldq_6_bits_uop_lrs1_rtype}, {ldq_5_bits_uop_lrs1_rtype}, {ldq_4_bits_uop_lrs1_rtype}, {ldq_3_bits_uop_lrs1_rtype}, {ldq_2_bits_uop_lrs1_rtype}, {ldq_1_bits_uop_lrs1_rtype}, {ldq_0_bits_uop_lrs1_rtype}};\n wire [7:0][1:0] _GEN_168 = {{ldq_7_bits_uop_lrs2_rtype}, {ldq_6_bits_uop_lrs2_rtype}, {ldq_5_bits_uop_lrs2_rtype}, {ldq_4_bits_uop_lrs2_rtype}, {ldq_3_bits_uop_lrs2_rtype}, {ldq_2_bits_uop_lrs2_rtype}, {ldq_1_bits_uop_lrs2_rtype}, {ldq_0_bits_uop_lrs2_rtype}};\n wire [7:0] _GEN_169 = {{ldq_7_bits_uop_frs3_en}, {ldq_6_bits_uop_frs3_en}, {ldq_5_bits_uop_frs3_en}, {ldq_4_bits_uop_frs3_en}, {ldq_3_bits_uop_frs3_en}, {ldq_2_bits_uop_frs3_en}, {ldq_1_bits_uop_frs3_en}, {ldq_0_bits_uop_frs3_en}};\n wire [7:0] _GEN_170 = {{ldq_7_bits_uop_fp_val}, {ldq_6_bits_uop_fp_val}, {ldq_5_bits_uop_fp_val}, {ldq_4_bits_uop_fp_val}, {ldq_3_bits_uop_fp_val}, {ldq_2_bits_uop_fp_val}, {ldq_1_bits_uop_fp_val}, {ldq_0_bits_uop_fp_val}};\n wire [7:0] _GEN_171 = {{ldq_7_bits_uop_fp_single}, {ldq_6_bits_uop_fp_single}, {ldq_5_bits_uop_fp_single}, {ldq_4_bits_uop_fp_single}, {ldq_3_bits_uop_fp_single}, {ldq_2_bits_uop_fp_single}, {ldq_1_bits_uop_fp_single}, {ldq_0_bits_uop_fp_single}};\n wire [7:0] _GEN_172 = {{ldq_7_bits_uop_xcpt_pf_if}, {ldq_6_bits_uop_xcpt_pf_if}, {ldq_5_bits_uop_xcpt_pf_if}, {ldq_4_bits_uop_xcpt_pf_if}, {ldq_3_bits_uop_xcpt_pf_if}, {ldq_2_bits_uop_xcpt_pf_if}, {ldq_1_bits_uop_xcpt_pf_if}, {ldq_0_bits_uop_xcpt_pf_if}};\n wire [7:0] _GEN_173 = {{ldq_7_bits_uop_xcpt_ae_if}, {ldq_6_bits_uop_xcpt_ae_if}, {ldq_5_bits_uop_xcpt_ae_if}, {ldq_4_bits_uop_xcpt_ae_if}, {ldq_3_bits_uop_xcpt_ae_if}, {ldq_2_bits_uop_xcpt_ae_if}, {ldq_1_bits_uop_xcpt_ae_if}, {ldq_0_bits_uop_xcpt_ae_if}};\n wire [7:0] _GEN_174 = {{ldq_7_bits_uop_xcpt_ma_if}, {ldq_6_bits_uop_xcpt_ma_if}, {ldq_5_bits_uop_xcpt_ma_if}, {ldq_4_bits_uop_xcpt_ma_if}, {ldq_3_bits_uop_xcpt_ma_if}, {ldq_2_bits_uop_xcpt_ma_if}, {ldq_1_bits_uop_xcpt_ma_if}, {ldq_0_bits_uop_xcpt_ma_if}};\n wire [7:0] _GEN_175 = {{ldq_7_bits_uop_bp_debug_if}, {ldq_6_bits_uop_bp_debug_if}, {ldq_5_bits_uop_bp_debug_if}, {ldq_4_bits_uop_bp_debug_if}, {ldq_3_bits_uop_bp_debug_if}, {ldq_2_bits_uop_bp_debug_if}, {ldq_1_bits_uop_bp_debug_if}, {ldq_0_bits_uop_bp_debug_if}};\n wire [7:0] _GEN_176 = {{ldq_7_bits_uop_bp_xcpt_if}, {ldq_6_bits_uop_bp_xcpt_if}, {ldq_5_bits_uop_bp_xcpt_if}, {ldq_4_bits_uop_bp_xcpt_if}, {ldq_3_bits_uop_bp_xcpt_if}, {ldq_2_bits_uop_bp_xcpt_if}, {ldq_1_bits_uop_bp_xcpt_if}, {ldq_0_bits_uop_bp_xcpt_if}};\n wire [7:0][1:0] _GEN_177 = {{ldq_7_bits_uop_debug_fsrc}, {ldq_6_bits_uop_debug_fsrc}, {ldq_5_bits_uop_debug_fsrc}, {ldq_4_bits_uop_debug_fsrc}, {ldq_3_bits_uop_debug_fsrc}, {ldq_2_bits_uop_debug_fsrc}, {ldq_1_bits_uop_debug_fsrc}, {ldq_0_bits_uop_debug_fsrc}};\n wire [7:0][1:0] _GEN_178 = {{ldq_7_bits_uop_debug_tsrc}, {ldq_6_bits_uop_debug_tsrc}, {ldq_5_bits_uop_debug_tsrc}, {ldq_4_bits_uop_debug_tsrc}, {ldq_3_bits_uop_debug_tsrc}, {ldq_2_bits_uop_debug_tsrc}, {ldq_1_bits_uop_debug_tsrc}, {ldq_0_bits_uop_debug_tsrc}};\n wire [7:0][39:0] _GEN_179 = {{ldq_7_bits_addr_bits}, {ldq_6_bits_addr_bits}, {ldq_5_bits_addr_bits}, {ldq_4_bits_addr_bits}, {ldq_3_bits_addr_bits}, {ldq_2_bits_addr_bits}, {ldq_1_bits_addr_bits}, {ldq_0_bits_addr_bits}};\n wire [39:0] _GEN_180 = _GEN_179[ldq_retry_idx];\n wire [7:0] _GEN_181 = {{ldq_7_bits_addr_is_virtual}, {ldq_6_bits_addr_is_virtual}, {ldq_5_bits_addr_is_virtual}, {ldq_4_bits_addr_is_virtual}, {ldq_3_bits_addr_is_virtual}, {ldq_2_bits_addr_is_virtual}, {ldq_1_bits_addr_is_virtual}, {ldq_0_bits_addr_is_virtual}};\n wire [7:0] _GEN_182 = {{ldq_7_bits_order_fail}, {ldq_6_bits_order_fail}, {ldq_5_bits_order_fail}, {ldq_4_bits_order_fail}, {ldq_3_bits_order_fail}, {ldq_2_bits_order_fail}, {ldq_1_bits_order_fail}, {ldq_0_bits_order_fail}};\n wire [7:0] _GEN_183 = {{p1_block_load_mask_7}, {p1_block_load_mask_6}, {p1_block_load_mask_5}, {p1_block_load_mask_4}, {p1_block_load_mask_3}, {p1_block_load_mask_2}, {p1_block_load_mask_1}, {p1_block_load_mask_0}};\n wire [7:0] _GEN_184 = {{p2_block_load_mask_7}, {p2_block_load_mask_6}, {p2_block_load_mask_5}, {p2_block_load_mask_4}, {p2_block_load_mask_3}, {p2_block_load_mask_2}, {p2_block_load_mask_1}, {p2_block_load_mask_0}};\n reg can_fire_load_retry_REG;\n wire _GEN_185 = _GEN_3[stq_retry_idx];\n wire [7:0] _GEN_186 = _GEN_29[stq_retry_idx];\n wire [4:0] mem_stq_retry_e_out_bits_uop_rob_idx = _GEN_37[stq_retry_idx];\n wire [2:0] mem_stq_retry_e_out_bits_uop_stq_idx = _GEN_39[stq_retry_idx];\n wire [5:0] _GEN_187 = _GEN_41[stq_retry_idx];\n wire [1:0] mem_stq_retry_e_out_bits_uop_mem_size = _GEN_56[stq_retry_idx];\n wire mem_stq_retry_e_out_bits_uop_is_amo = _GEN_61[stq_retry_idx];\n wire [39:0] _GEN_188 = _GEN_88[stq_retry_idx];\n reg can_fire_sta_retry_REG;\n wire can_fire_store_commit_0 = _GEN_4 & ~_GEN_59 & ~mem_xcpt_valids_0 & ~_GEN_52 & (_GEN_93[stq_execute_head] | _GEN_62 & _GEN_87[stq_execute_head] & ~_GEN_89[stq_execute_head] & _GEN_90[stq_execute_head]);\n wire [7:0] _GEN_189 = _GEN_97[ldq_wakeup_idx];\n wire [2:0] mem_ldq_wakeup_e_out_bits_uop_stq_idx = _GEN_98[ldq_wakeup_idx];\n wire [1:0] mem_ldq_wakeup_e_out_bits_uop_mem_size = _GEN_99[ldq_wakeup_idx];\n wire _GEN_190 = _GEN_181[ldq_wakeup_idx];\n wire [7:0] _GEN_191 = {{ldq_7_bits_addr_is_uncacheable}, {ldq_6_bits_addr_is_uncacheable}, {ldq_5_bits_addr_is_uncacheable}, {ldq_4_bits_addr_is_uncacheable}, {ldq_3_bits_addr_is_uncacheable}, {ldq_2_bits_addr_is_uncacheable}, {ldq_1_bits_addr_is_uncacheable}, {ldq_0_bits_addr_is_uncacheable}};\n wire _GEN_192 = _GEN_101[ldq_wakeup_idx];\n wire [7:0] _GEN_193 = {{ldq_7_bits_succeeded}, {ldq_6_bits_succeeded}, {ldq_5_bits_succeeded}, {ldq_4_bits_succeeded}, {ldq_3_bits_succeeded}, {ldq_2_bits_succeeded}, {ldq_1_bits_succeeded}, {ldq_0_bits_succeeded}};\n wire [7:0] mem_ldq_wakeup_e_out_bits_st_dep_mask = _GEN_102[ldq_wakeup_idx];\n wire will_fire_stad_incoming_0_will_fire = _can_fire_sta_incoming_T & io_core_exe_0_req_bits_uop_ctrl_is_std & ~will_fire_load_incoming_0_will_fire & ~will_fire_load_incoming_0_will_fire;\n wire _will_fire_sta_incoming_0_will_fire_T_2 = ~will_fire_load_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;\n wire _will_fire_sta_incoming_0_will_fire_T_6 = ~will_fire_load_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;\n wire will_fire_sta_incoming_0_will_fire = _can_fire_sta_incoming_T & ~io_core_exe_0_req_bits_uop_ctrl_is_std & _will_fire_sta_incoming_0_will_fire_T_2 & _will_fire_sta_incoming_0_will_fire_T_6 & ~will_fire_stad_incoming_0_will_fire;\n wire _will_fire_sfence_0_will_fire_T_2 = _will_fire_sta_incoming_0_will_fire_T_2 & ~will_fire_sta_incoming_0_will_fire;\n wire _will_fire_release_0_will_fire_T_6 = _will_fire_sta_incoming_0_will_fire_T_6 & ~will_fire_sta_incoming_0_will_fire;\n wire _will_fire_std_incoming_0_will_fire_T_14 = ~will_fire_stad_incoming_0_will_fire & ~will_fire_sta_incoming_0_will_fire;\n wire will_fire_std_incoming_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_uop_ctrl_is_std & ~io_core_exe_0_req_bits_uop_ctrl_is_sta & _will_fire_std_incoming_0_will_fire_T_14;\n wire _will_fire_sfence_0_will_fire_T_14 = _will_fire_std_incoming_0_will_fire_T_14 & ~will_fire_std_incoming_0_will_fire;\n wire will_fire_sfence_0_will_fire = io_core_exe_0_req_valid & io_core_exe_0_req_bits_sfence_valid & _will_fire_sfence_0_will_fire_T_2 & _will_fire_sfence_0_will_fire_T_14;\n wire _will_fire_hella_incoming_0_will_fire_T_2 = _will_fire_sfence_0_will_fire_T_2 & ~will_fire_sfence_0_will_fire;\n wire will_fire_release_0_will_fire = io_dmem_release_valid & _will_fire_release_0_will_fire_T_6;\n wire _will_fire_load_retry_0_will_fire_T_6 = _will_fire_release_0_will_fire_T_6 & ~will_fire_release_0_will_fire;\n wire will_fire_hella_incoming_0_will_fire = _GEN_0 & _GEN_2 & _will_fire_hella_incoming_0_will_fire_T_2 & ~will_fire_load_incoming_0_will_fire;\n wire _will_fire_load_retry_0_will_fire_T_2 = _will_fire_hella_incoming_0_will_fire_T_2 & ~will_fire_hella_incoming_0_will_fire;\n wire _will_fire_hella_wakeup_0_will_fire_T_10 = ~will_fire_load_incoming_0_will_fire & ~will_fire_hella_incoming_0_will_fire;\n wire will_fire_hella_wakeup_0_will_fire = _GEN & _GEN_1 & _will_fire_hella_wakeup_0_will_fire_T_10;\n wire _will_fire_load_retry_0_will_fire_T_10 = _will_fire_hella_wakeup_0_will_fire_T_10 & ~will_fire_hella_wakeup_0_will_fire;\n wire will_fire_load_retry_0_will_fire = _GEN_96[ldq_retry_idx] & _GEN_100[ldq_retry_idx] & _GEN_181[ldq_retry_idx] & ~_GEN_183[ldq_retry_idx] & ~_GEN_184[ldq_retry_idx] & can_fire_load_retry_REG & ~store_needs_order & ~_GEN_182[ldq_retry_idx] & _will_fire_load_retry_0_will_fire_T_2 & _will_fire_load_retry_0_will_fire_T_6 & _will_fire_load_retry_0_will_fire_T_10;\n wire _will_fire_sta_retry_0_will_fire_T_2 = _will_fire_load_retry_0_will_fire_T_2 & ~will_fire_load_retry_0_will_fire;\n wire _will_fire_sta_retry_0_will_fire_T_6 = _will_fire_load_retry_0_will_fire_T_6 & ~will_fire_load_retry_0_will_fire;\n wire _will_fire_load_wakeup_0_will_fire_T_10 = _will_fire_load_retry_0_will_fire_T_10 & ~will_fire_load_retry_0_will_fire;\n wire will_fire_sta_retry_0_will_fire = _GEN_185 & _GEN_87[stq_retry_idx] & _GEN_89[stq_retry_idx] & can_fire_sta_retry_REG & _will_fire_sta_retry_0_will_fire_T_2 & _will_fire_sta_retry_0_will_fire_T_6 & _will_fire_sfence_0_will_fire_T_14 & ~will_fire_sfence_0_will_fire;\n assign _will_fire_store_commit_0_T_2 = _will_fire_sta_retry_0_will_fire_T_2 & ~will_fire_sta_retry_0_will_fire;\n wire will_fire_load_wakeup_0_will_fire = _GEN_96[ldq_wakeup_idx] & _GEN_100[ldq_wakeup_idx] & ~_GEN_193[ldq_wakeup_idx] & ~_GEN_190 & ~_GEN_192 & ~_GEN_182[ldq_wakeup_idx] & ~_GEN_183[ldq_wakeup_idx] & ~_GEN_184[ldq_wakeup_idx] & ~store_needs_order & ~block_load_wakeup & (~_GEN_191[ldq_wakeup_idx] | io_core_commit_load_at_rob_head & ldq_head == ldq_wakeup_idx & mem_ldq_wakeup_e_out_bits_st_dep_mask == 8'h0) & _will_fire_sta_retry_0_will_fire_T_6 & ~will_fire_sta_retry_0_will_fire & _will_fire_load_wakeup_0_will_fire_T_10;\n wire will_fire_store_commit_0_will_fire = can_fire_store_commit_0 & _will_fire_load_wakeup_0_will_fire_T_10 & ~will_fire_load_wakeup_0_will_fire;\n wire _exe_cmd_T = will_fire_load_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;\n wire _GEN_194 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire;\n wire _GEN_195 = ldq_wakeup_idx == 3'h0;\n wire _GEN_196 = ldq_wakeup_idx == 3'h1;\n wire _GEN_197 = ldq_wakeup_idx == 3'h2;\n wire _GEN_198 = ldq_wakeup_idx == 3'h3;\n wire _GEN_199 = ldq_wakeup_idx == 3'h4;\n wire _GEN_200 = ldq_wakeup_idx == 3'h5;\n wire _GEN_201 = ldq_wakeup_idx == 3'h6;\n wire _GEN_202 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h0;\n wire _GEN_203 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h1;\n wire _GEN_204 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h2;\n wire _GEN_205 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h3;\n wire _GEN_206 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h4;\n wire _GEN_207 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h5;\n wire _GEN_208 = io_core_exe_0_req_bits_uop_ldq_idx == 3'h6;\n wire _GEN_209 = ldq_retry_idx == 3'h0;\n wire block_load_mask_0 = will_fire_load_wakeup_0_will_fire ? _GEN_195 : will_fire_load_incoming_0_will_fire ? _GEN_202 : will_fire_load_retry_0_will_fire & _GEN_209;\n wire _GEN_210 = ldq_retry_idx == 3'h1;\n wire block_load_mask_1 = will_fire_load_wakeup_0_will_fire ? _GEN_196 : will_fire_load_incoming_0_will_fire ? _GEN_203 : will_fire_load_retry_0_will_fire & _GEN_210;\n wire _GEN_211 = ldq_retry_idx == 3'h2;\n wire block_load_mask_2 = will_fire_load_wakeup_0_will_fire ? _GEN_197 : will_fire_load_incoming_0_will_fire ? _GEN_204 : will_fire_load_retry_0_will_fire & _GEN_211;\n wire _GEN_212 = ldq_retry_idx == 3'h3;\n wire block_load_mask_3 = will_fire_load_wakeup_0_will_fire ? _GEN_198 : will_fire_load_incoming_0_will_fire ? _GEN_205 : will_fire_load_retry_0_will_fire & _GEN_212;\n wire _GEN_213 = ldq_retry_idx == 3'h4;\n wire block_load_mask_4 = will_fire_load_wakeup_0_will_fire ? _GEN_199 : will_fire_load_incoming_0_will_fire ? _GEN_206 : will_fire_load_retry_0_will_fire & _GEN_213;\n wire _GEN_214 = ldq_retry_idx == 3'h5;\n wire block_load_mask_5 = will_fire_load_wakeup_0_will_fire ? _GEN_200 : will_fire_load_incoming_0_will_fire ? _GEN_207 : will_fire_load_retry_0_will_fire & _GEN_214;\n wire _GEN_215 = ldq_retry_idx == 3'h6;\n wire block_load_mask_6 = will_fire_load_wakeup_0_will_fire ? _GEN_201 : will_fire_load_incoming_0_will_fire ? _GEN_208 : will_fire_load_retry_0_will_fire & _GEN_215;\n wire block_load_mask_7 = will_fire_load_wakeup_0_will_fire ? (&ldq_wakeup_idx) : will_fire_load_incoming_0_will_fire ? (&io_core_exe_0_req_bits_uop_ldq_idx) : will_fire_load_retry_0_will_fire & (&ldq_retry_idx);\n wire _exe_tlb_uop_T_2 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire;\n wire [5:0] _exe_tlb_uop_T_4_pdst = will_fire_sta_retry_0_will_fire ? _GEN_187 : 6'h0;\n wire exe_tlb_uop_0_ctrl_is_load = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_load : will_fire_load_retry_0_will_fire ? _GEN_117[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_19[stq_retry_idx];\n wire exe_tlb_uop_0_ctrl_is_sta = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_sta : will_fire_load_retry_0_will_fire ? _GEN_118[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_20[stq_retry_idx];\n wire [7:0] exe_tlb_uop_0_br_mask = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_br_mask : will_fire_load_retry_0_will_fire ? _GEN_127 : will_fire_sta_retry_0_will_fire ? _GEN_186 : 8'h0;\n wire [4:0] exe_tlb_uop_0_rob_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_rob_idx : will_fire_load_retry_0_will_fire ? _GEN_135[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_rob_idx : 5'h0;\n wire [2:0] exe_tlb_uop_0_ldq_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldq_idx : will_fire_load_retry_0_will_fire ? _GEN_136[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_38[stq_retry_idx] : 3'h0;\n wire [2:0] exe_tlb_uop_0_stq_idx = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_stq_idx : will_fire_load_retry_0_will_fire ? mem_ldq_retry_e_out_bits_uop_stq_idx : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_stq_idx : 3'h0;\n wire [4:0] exe_tlb_uop_0_mem_cmd = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_cmd : will_fire_load_retry_0_will_fire ? _GEN_150[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_55[stq_retry_idx] : 5'h0;\n wire [1:0] exe_tlb_uop_0_mem_size = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_size : will_fire_load_retry_0_will_fire ? mem_ldq_retry_e_out_bits_uop_mem_size : will_fire_sta_retry_0_will_fire ? mem_stq_retry_e_out_bits_uop_mem_size : 2'h0;\n wire exe_tlb_uop_0_is_fence = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_fence : will_fire_load_retry_0_will_fire ? _GEN_152[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_58[stq_retry_idx];\n wire exe_tlb_uop_0_uses_ldq = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uses_ldq : will_fire_load_retry_0_will_fire ? _GEN_155[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_63[stq_retry_idx];\n wire exe_tlb_uop_0_uses_stq = _exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uses_stq : will_fire_load_retry_0_will_fire ? _GEN_156[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_64[stq_retry_idx];\n wire _exe_tlb_vaddr_T_1 = _exe_cmd_T | will_fire_sta_incoming_0_will_fire;\n wire [39:0] _exe_tlb_vaddr_T_2 = will_fire_hella_incoming_0_will_fire ? hella_req_addr : 40'h0;\n wire [39:0] _exe_tlb_vaddr_T_3 = will_fire_sta_retry_0_will_fire ? _GEN_188 : _exe_tlb_vaddr_T_2;\n wire [39:0] _GEN_216 = {1'h0, io_core_exe_0_req_bits_sfence_bits_addr};\n wire [39:0] exe_tlb_vaddr_0 = _exe_tlb_vaddr_T_1 ? io_core_exe_0_req_bits_addr : will_fire_sfence_0_will_fire ? _GEN_216 : will_fire_load_retry_0_will_fire ? _GEN_180 : _exe_tlb_vaddr_T_3;\n wire _stq_idx_T = will_fire_sta_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;\n reg [7:0] mem_xcpt_uops_0_br_mask;\n reg [4:0] mem_xcpt_uops_0_rob_idx;\n reg [2:0] mem_xcpt_uops_0_ldq_idx;\n reg [2:0] mem_xcpt_uops_0_stq_idx;\n reg mem_xcpt_uops_0_uses_ldq;\n reg mem_xcpt_uops_0_uses_stq;\n reg [3:0] mem_xcpt_causes_0;\n reg [39:0] mem_xcpt_vaddrs_0;\n wire exe_tlb_miss_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_miss;\n wire [31:0] exe_tlb_paddr_0 = {_dtlb_io_resp_0_paddr[31:12], exe_tlb_vaddr_0[11:0]};\n reg REG;\n wire [39:0] _GEN_217 = {8'h0, _dtlb_io_resp_0_paddr[31:12], exe_tlb_vaddr_0[11:0]};\n wire [3:0][63:0] _GEN_218 = {{_GEN_92}, {{2{_GEN_92[31:0]}}}, {{2{{2{_GEN_92[15:0]}}}}}, {{2{{2{{2{_GEN_92[7:0]}}}}}}}};\n wire _GEN_219 = will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire;\n assign _GEN_2 = hella_state == 3'h1;\n wire _GEN_220 = will_fire_store_commit_0_will_fire | will_fire_load_wakeup_0_will_fire;\n assign _GEN_1 = hella_state == 3'h5;\n wire dmem_req_0_valid = will_fire_load_incoming_0_will_fire ? ~exe_tlb_miss_0 & _dtlb_io_resp_0_cacheable : will_fire_load_retry_0_will_fire ? ~exe_tlb_miss_0 & _dtlb_io_resp_0_cacheable : _GEN_220 | (will_fire_hella_incoming_0_will_fire ? ~io_hellacache_s1_kill : will_fire_hella_wakeup_0_will_fire);\n wire [39:0] dmem_req_0_bits_addr = will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire ? _GEN_217 : will_fire_store_commit_0_will_fire ? _GEN_88[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_179[ldq_wakeup_idx] : will_fire_hella_incoming_0_will_fire ? _GEN_217 : will_fire_hella_wakeup_0_will_fire ? {8'h0, hella_paddr} : 40'h0;\n wire _GEN_221 = _stq_idx_T | will_fire_sta_retry_0_will_fire;\n wire io_core_fp_stdata_ready_0 = ~will_fire_std_incoming_0_will_fire & ~will_fire_stad_incoming_0_will_fire;\n wire fp_stdata_fire = io_core_fp_stdata_ready_0 & io_core_fp_stdata_valid;\n wire _stq_bits_data_bits_T = will_fire_std_incoming_0_will_fire | will_fire_stad_incoming_0_will_fire;\n wire _GEN_222 = _stq_bits_data_bits_T | fp_stdata_fire;\n wire [2:0] sidx = _stq_bits_data_bits_T ? io_core_exe_0_req_bits_uop_stq_idx : io_core_fp_stdata_bits_uop_stq_idx;\n reg fired_load_incoming_REG;\n reg fired_stad_incoming_REG;\n reg fired_sta_incoming_REG;\n reg fired_std_incoming_REG;\n reg fired_stdf_incoming;\n reg fired_sfence_0;\n reg fired_release_0;\n reg fired_load_retry_REG;\n reg fired_sta_retry_REG;\n reg fired_load_wakeup_REG;\n reg [7:0] mem_incoming_uop_0_br_mask;\n reg [4:0] mem_incoming_uop_0_rob_idx;\n reg [2:0] mem_incoming_uop_0_ldq_idx;\n reg [2:0] mem_incoming_uop_0_stq_idx;\n reg [5:0] mem_incoming_uop_0_pdst;\n reg mem_incoming_uop_0_fp_val;\n reg [7:0] mem_ldq_incoming_e_0_bits_uop_br_mask;\n reg [2:0] mem_ldq_incoming_e_0_bits_uop_stq_idx;\n reg [1:0] mem_ldq_incoming_e_0_bits_uop_mem_size;\n reg [7:0] mem_ldq_incoming_e_0_bits_st_dep_mask;\n reg mem_stq_incoming_e_0_valid;\n reg [7:0] mem_stq_incoming_e_0_bits_uop_br_mask;\n reg [4:0] mem_stq_incoming_e_0_bits_uop_rob_idx;\n reg [2:0] mem_stq_incoming_e_0_bits_uop_stq_idx;\n reg [1:0] mem_stq_incoming_e_0_bits_uop_mem_size;\n reg mem_stq_incoming_e_0_bits_uop_is_amo;\n reg mem_stq_incoming_e_0_bits_addr_valid;\n reg mem_stq_incoming_e_0_bits_addr_is_virtual;\n reg mem_stq_incoming_e_0_bits_data_valid;\n reg [7:0] mem_ldq_wakeup_e_bits_uop_br_mask;\n reg [2:0] mem_ldq_wakeup_e_bits_uop_stq_idx;\n reg [1:0] mem_ldq_wakeup_e_bits_uop_mem_size;\n reg [7:0] mem_ldq_wakeup_e_bits_st_dep_mask;\n reg [7:0] mem_ldq_retry_e_bits_uop_br_mask;\n reg [2:0] mem_ldq_retry_e_bits_uop_stq_idx;\n reg [1:0] mem_ldq_retry_e_bits_uop_mem_size;\n reg [7:0] mem_ldq_retry_e_bits_st_dep_mask;\n reg mem_stq_retry_e_valid;\n reg [7:0] mem_stq_retry_e_bits_uop_br_mask;\n reg [4:0] mem_stq_retry_e_bits_uop_rob_idx;\n reg [2:0] mem_stq_retry_e_bits_uop_stq_idx;\n reg [1:0] mem_stq_retry_e_bits_uop_mem_size;\n reg mem_stq_retry_e_bits_uop_is_amo;\n reg mem_stq_retry_e_bits_data_valid;\n wire [7:0] lcam_st_dep_mask_0 = fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_st_dep_mask : fired_load_retry_REG ? mem_ldq_retry_e_bits_st_dep_mask : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_st_dep_mask : 8'h0;\n wire _lcam_stq_idx_T = fired_stad_incoming_REG | fired_sta_incoming_REG;\n reg [7:0] mem_stdf_uop_br_mask;\n reg [4:0] mem_stdf_uop_rob_idx;\n reg [2:0] mem_stdf_uop_stq_idx;\n reg mem_tlb_miss_0;\n reg mem_tlb_uncacheable_0;\n reg [39:0] mem_paddr_0;\n reg clr_bsy_valid_0;\n reg [4:0] clr_bsy_rob_idx_0;\n reg [7:0] clr_bsy_brmask_0;\n reg io_core_clr_bsy_0_valid_REG;\n reg io_core_clr_bsy_0_valid_REG_1;\n reg io_core_clr_bsy_0_valid_REG_2;\n reg stdf_clr_bsy_valid;\n reg [4:0] stdf_clr_bsy_rob_idx;\n reg [7:0] stdf_clr_bsy_brmask;\n reg io_core_clr_bsy_1_valid_REG;\n reg io_core_clr_bsy_1_valid_REG_1;\n reg io_core_clr_bsy_1_valid_REG_2;\n wire do_st_search_0 = (_lcam_stq_idx_T | fired_sta_retry_REG) & ~mem_tlb_miss_0;\n wire _can_forward_T = fired_load_incoming_REG | fired_load_retry_REG;\n wire do_ld_search_0 = _can_forward_T & ~mem_tlb_miss_0 | fired_load_wakeup_REG;\n reg [31:0] lcam_addr_REG;\n reg [31:0] lcam_addr_REG_1;\n wire [39:0] lcam_addr_0 = _lcam_stq_idx_T | fired_sta_retry_REG ? {8'h0, lcam_addr_REG} : fired_release_0 ? {8'h0, lcam_addr_REG_1} : mem_paddr_0;\n wire [14:0] _lcam_mask_mask_T_2 = 15'h1 << lcam_addr_0[2:0];\n wire [14:0] _lcam_mask_mask_T_6 = 15'h3 << {12'h0, lcam_addr_0[2:1], 1'h0};\n wire [3:0][7:0] _GEN_223 = {{8'hFF}, {lcam_addr_0[2] ? 8'hF0 : 8'hF}, {_lcam_mask_mask_T_6[7:0]}, {_lcam_mask_mask_T_2[7:0]}};\n wire [7:0] lcam_mask_0 = _GEN_223[do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_mem_size : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_mem_size : 2'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_mem_size : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_mem_size : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_mem_size : 2'h0) : 2'h0];\n reg [2:0] lcam_ldq_idx_REG;\n reg [2:0] lcam_ldq_idx_REG_1;\n wire [2:0] lcam_ldq_idx_0 = fired_load_incoming_REG ? mem_incoming_uop_0_ldq_idx : fired_load_wakeup_REG ? lcam_ldq_idx_REG : fired_load_retry_REG ? lcam_ldq_idx_REG_1 : 3'h0;\n reg [2:0] lcam_stq_idx_REG;\n wire [2:0] lcam_stq_idx_0 = _lcam_stq_idx_T ? mem_incoming_uop_0_stq_idx : fired_sta_retry_REG ? lcam_stq_idx_REG : 3'h0;\n reg s1_executing_loads_0;\n reg s1_executing_loads_1;\n reg s1_executing_loads_2;\n reg s1_executing_loads_3;\n reg s1_executing_loads_4;\n reg s1_executing_loads_5;\n reg s1_executing_loads_6;\n reg s1_executing_loads_7;\n reg wb_forward_valid_0;\n reg [2:0] wb_forward_ldq_idx_0;\n reg [39:0] wb_forward_ld_addr_0;\n reg [2:0] wb_forward_stq_idx_0;\n wire [14:0] _l_mask_mask_T_2 = 15'h1 << ldq_0_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_6 = 15'h3 << {12'h0, ldq_0_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_224 = {{8'hFF}, {ldq_0_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_6[7:0]}, {_l_mask_mask_T_2[7:0]}};\n wire l_forwarders_0 = wb_forward_valid_0 & ~(|wb_forward_ldq_idx_0);\n wire block_addr_matches_0 = lcam_addr_0[39:6] == ldq_0_bits_addr_bits[39:6];\n wire dword_addr_matches_0 = block_addr_matches_0 & lcam_addr_0[5:3] == ldq_0_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T = _GEN_224[ldq_0_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_225 = fired_release_0 & ldq_0_valid & ldq_0_bits_addr_valid & block_addr_matches_0;\n wire _GEN_226 = ldq_0_bits_executed | ldq_0_bits_succeeded;\n wire _GEN_227 = _GEN_226 | l_forwarders_0;\n wire [7:0] _GEN_228 = {5'h0, lcam_stq_idx_0};\n wire [7:0] _GEN_229 = ldq_0_bits_st_dep_mask >> _GEN_228;\n wire _GEN_230 = do_st_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & _GEN_227 & ~ldq_0_bits_addr_is_virtual & _GEN_229[0] & dword_addr_matches_0 & (|_mask_overlap_T);\n wire _GEN_231 = do_ld_search_0 & ldq_0_valid & ldq_0_bits_addr_valid & ~ldq_0_bits_addr_is_virtual & dword_addr_matches_0 & (|_mask_overlap_T);\n wire searcher_is_older = lcam_ldq_idx_0 < ldq_head ^ (|ldq_head);\n reg older_nacked_REG;\n wire _GEN_232 = ~_GEN_226 | nacking_loads_0 | older_nacked_REG;\n wire _GEN_233 = _GEN_225 | _GEN_230;\n wire _GEN_234 = lcam_ldq_idx_0 == 3'h1;\n wire _GEN_235 = lcam_ldq_idx_0 == 3'h2;\n wire _GEN_236 = lcam_ldq_idx_0 == 3'h3;\n wire _GEN_237 = lcam_ldq_idx_0 == 3'h4;\n wire _GEN_238 = lcam_ldq_idx_0 == 3'h5;\n wire _GEN_239 = lcam_ldq_idx_0 == 3'h6;\n reg io_dmem_s1_kill_0_REG;\n wire _GEN_240 = (|lcam_ldq_idx_0) & _GEN_232;\n wire [14:0] _l_mask_mask_T_17 = 15'h1 << ldq_1_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_21 = 15'h3 << {12'h0, ldq_1_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_241 = {{8'hFF}, {ldq_1_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_21[7:0]}, {_l_mask_mask_T_17[7:0]}};\n wire l_forwarders_1_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h1;\n wire block_addr_matches_1_0 = lcam_addr_0[39:6] == ldq_1_bits_addr_bits[39:6];\n wire dword_addr_matches_1_0 = block_addr_matches_1_0 & lcam_addr_0[5:3] == ldq_1_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_2 = _GEN_241[ldq_1_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_242 = fired_release_0 & ldq_1_valid & ldq_1_bits_addr_valid & block_addr_matches_1_0;\n wire _GEN_243 = ldq_1_bits_executed | ldq_1_bits_succeeded;\n wire _GEN_244 = _GEN_243 | l_forwarders_1_0;\n wire [7:0] _GEN_245 = ldq_1_bits_st_dep_mask >> _GEN_228;\n wire _GEN_246 = do_st_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & _GEN_244 & ~ldq_1_bits_addr_is_virtual & _GEN_245[0] & dword_addr_matches_1_0 & (|_mask_overlap_T_2);\n wire _GEN_247 = do_ld_search_0 & ldq_1_valid & ldq_1_bits_addr_valid & ~ldq_1_bits_addr_is_virtual & dword_addr_matches_1_0 & (|_mask_overlap_T_2);\n wire searcher_is_older_1 = lcam_ldq_idx_0 == 3'h0 ^ lcam_ldq_idx_0 < ldq_head ^ (|(ldq_head[2:1]));\n reg older_nacked_REG_1;\n wire _GEN_248 = ~_GEN_243 | nacking_loads_1 | older_nacked_REG_1;\n wire _GEN_249 = searcher_is_older_1 | _GEN_234;\n wire _GEN_250 = _GEN_242 | _GEN_246;\n reg io_dmem_s1_kill_0_REG_1;\n wire _GEN_251 = _GEN_250 | ~_GEN_247 | _GEN_249 | ~_GEN_248;\n wire [14:0] _l_mask_mask_T_32 = 15'h1 << ldq_2_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_36 = 15'h3 << {12'h0, ldq_2_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_252 = {{8'hFF}, {ldq_2_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_36[7:0]}, {_l_mask_mask_T_32[7:0]}};\n wire l_forwarders_2_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h2;\n wire block_addr_matches_2_0 = lcam_addr_0[39:6] == ldq_2_bits_addr_bits[39:6];\n wire dword_addr_matches_2_0 = block_addr_matches_2_0 & lcam_addr_0[5:3] == ldq_2_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_4 = _GEN_252[ldq_2_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_253 = fired_release_0 & ldq_2_valid & ldq_2_bits_addr_valid & block_addr_matches_2_0;\n wire _GEN_254 = ldq_2_bits_executed | ldq_2_bits_succeeded;\n wire _GEN_255 = _GEN_254 | l_forwarders_2_0;\n wire [7:0] _GEN_256 = ldq_2_bits_st_dep_mask >> _GEN_228;\n wire _GEN_257 = do_st_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & _GEN_255 & ~ldq_2_bits_addr_is_virtual & _GEN_256[0] & dword_addr_matches_2_0 & (|_mask_overlap_T_4);\n wire _GEN_258 = do_ld_search_0 & ldq_2_valid & ldq_2_bits_addr_valid & ~ldq_2_bits_addr_is_virtual & dword_addr_matches_2_0 & (|_mask_overlap_T_4);\n wire searcher_is_older_2 = lcam_ldq_idx_0 < 3'h2 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head > 3'h2;\n reg older_nacked_REG_2;\n wire _GEN_259 = ~_GEN_254 | nacking_loads_2 | older_nacked_REG_2;\n wire _GEN_260 = searcher_is_older_2 | _GEN_235;\n wire _GEN_261 = _GEN_253 | _GEN_257;\n reg io_dmem_s1_kill_0_REG_2;\n wire _GEN_262 = _GEN_261 | ~_GEN_258 | _GEN_260 | ~_GEN_259;\n wire [14:0] _l_mask_mask_T_47 = 15'h1 << ldq_3_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_51 = 15'h3 << {12'h0, ldq_3_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_263 = {{8'hFF}, {ldq_3_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_51[7:0]}, {_l_mask_mask_T_47[7:0]}};\n wire l_forwarders_3_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h3;\n wire block_addr_matches_3_0 = lcam_addr_0[39:6] == ldq_3_bits_addr_bits[39:6];\n wire dword_addr_matches_3_0 = block_addr_matches_3_0 & lcam_addr_0[5:3] == ldq_3_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_6 = _GEN_263[ldq_3_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_264 = fired_release_0 & ldq_3_valid & ldq_3_bits_addr_valid & block_addr_matches_3_0;\n wire _GEN_265 = ldq_3_bits_executed | ldq_3_bits_succeeded;\n wire _GEN_266 = _GEN_265 | l_forwarders_3_0;\n wire [7:0] _GEN_267 = ldq_3_bits_st_dep_mask >> _GEN_228;\n wire _GEN_268 = do_st_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & _GEN_266 & ~ldq_3_bits_addr_is_virtual & _GEN_267[0] & dword_addr_matches_3_0 & (|_mask_overlap_T_6);\n wire _GEN_269 = do_ld_search_0 & ldq_3_valid & ldq_3_bits_addr_valid & ~ldq_3_bits_addr_is_virtual & dword_addr_matches_3_0 & (|_mask_overlap_T_6);\n wire searcher_is_older_3 = lcam_ldq_idx_0 < 3'h3 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head[2];\n reg older_nacked_REG_3;\n wire _GEN_270 = ~_GEN_265 | nacking_loads_3 | older_nacked_REG_3;\n wire _GEN_271 = searcher_is_older_3 | _GEN_236;\n wire _GEN_272 = _GEN_264 | _GEN_268;\n reg io_dmem_s1_kill_0_REG_3;\n wire _GEN_273 = _GEN_272 | ~_GEN_269 | _GEN_271 | ~_GEN_270;\n wire [14:0] _l_mask_mask_T_62 = 15'h1 << ldq_4_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_66 = 15'h3 << {12'h0, ldq_4_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_274 = {{8'hFF}, {ldq_4_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_66[7:0]}, {_l_mask_mask_T_62[7:0]}};\n wire l_forwarders_4_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h4;\n wire block_addr_matches_4_0 = lcam_addr_0[39:6] == ldq_4_bits_addr_bits[39:6];\n wire dword_addr_matches_4_0 = block_addr_matches_4_0 & lcam_addr_0[5:3] == ldq_4_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_8 = _GEN_274[ldq_4_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_275 = fired_release_0 & ldq_4_valid & ldq_4_bits_addr_valid & block_addr_matches_4_0;\n wire _GEN_276 = ldq_4_bits_executed | ldq_4_bits_succeeded;\n wire _GEN_277 = _GEN_276 | l_forwarders_4_0;\n wire [7:0] _GEN_278 = ldq_4_bits_st_dep_mask >> _GEN_228;\n wire _GEN_279 = do_st_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & _GEN_277 & ~ldq_4_bits_addr_is_virtual & _GEN_278[0] & dword_addr_matches_4_0 & (|_mask_overlap_T_8);\n wire _GEN_280 = do_ld_search_0 & ldq_4_valid & ldq_4_bits_addr_valid & ~ldq_4_bits_addr_is_virtual & dword_addr_matches_4_0 & (|_mask_overlap_T_8);\n wire searcher_is_older_4 = lcam_ldq_idx_0[2] ^ ldq_head > 3'h4 ^ lcam_ldq_idx_0 >= ldq_head;\n reg older_nacked_REG_4;\n wire _GEN_281 = ~_GEN_276 | nacking_loads_4 | older_nacked_REG_4;\n wire _GEN_282 = searcher_is_older_4 | _GEN_237;\n wire _GEN_283 = _GEN_275 | _GEN_279;\n reg io_dmem_s1_kill_0_REG_4;\n wire _GEN_284 = _GEN_283 | ~_GEN_280 | _GEN_282 | ~_GEN_281;\n wire [14:0] _l_mask_mask_T_77 = 15'h1 << ldq_5_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_81 = 15'h3 << {12'h0, ldq_5_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_285 = {{8'hFF}, {ldq_5_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_81[7:0]}, {_l_mask_mask_T_77[7:0]}};\n wire l_forwarders_5_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h5;\n wire block_addr_matches_5_0 = lcam_addr_0[39:6] == ldq_5_bits_addr_bits[39:6];\n wire dword_addr_matches_5_0 = block_addr_matches_5_0 & lcam_addr_0[5:3] == ldq_5_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_10 = _GEN_285[ldq_5_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_286 = fired_release_0 & ldq_5_valid & ldq_5_bits_addr_valid & block_addr_matches_5_0;\n wire _GEN_287 = ldq_5_bits_executed | ldq_5_bits_succeeded;\n wire _GEN_288 = _GEN_287 | l_forwarders_5_0;\n wire [7:0] _GEN_289 = ldq_5_bits_st_dep_mask >> _GEN_228;\n wire _GEN_290 = do_st_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & _GEN_288 & ~ldq_5_bits_addr_is_virtual & _GEN_289[0] & dword_addr_matches_5_0 & (|_mask_overlap_T_10);\n wire _GEN_291 = do_ld_search_0 & ldq_5_valid & ldq_5_bits_addr_valid & ~ldq_5_bits_addr_is_virtual & dword_addr_matches_5_0 & (|_mask_overlap_T_10);\n wire searcher_is_older_5 = lcam_ldq_idx_0 < 3'h5 ^ lcam_ldq_idx_0 < ldq_head ^ ldq_head > 3'h5;\n reg older_nacked_REG_5;\n wire _GEN_292 = ~_GEN_287 | nacking_loads_5 | older_nacked_REG_5;\n wire _GEN_293 = searcher_is_older_5 | _GEN_238;\n wire _GEN_294 = _GEN_286 | _GEN_290;\n reg io_dmem_s1_kill_0_REG_5;\n wire _GEN_295 = _GEN_294 | ~_GEN_291 | _GEN_293 | ~_GEN_292;\n wire [14:0] _l_mask_mask_T_92 = 15'h1 << ldq_6_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_96 = 15'h3 << {12'h0, ldq_6_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_296 = {{8'hFF}, {ldq_6_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_96[7:0]}, {_l_mask_mask_T_92[7:0]}};\n wire l_forwarders_6_0 = wb_forward_valid_0 & wb_forward_ldq_idx_0 == 3'h6;\n wire block_addr_matches_6_0 = lcam_addr_0[39:6] == ldq_6_bits_addr_bits[39:6];\n wire dword_addr_matches_6_0 = block_addr_matches_6_0 & lcam_addr_0[5:3] == ldq_6_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_12 = _GEN_296[ldq_6_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_297 = fired_release_0 & ldq_6_valid & ldq_6_bits_addr_valid & block_addr_matches_6_0;\n wire _GEN_298 = ldq_6_bits_executed | ldq_6_bits_succeeded;\n wire _GEN_299 = _GEN_298 | l_forwarders_6_0;\n wire [7:0] _GEN_300 = ldq_6_bits_st_dep_mask >> _GEN_228;\n wire _GEN_301 = do_st_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & _GEN_299 & ~ldq_6_bits_addr_is_virtual & _GEN_300[0] & dword_addr_matches_6_0 & (|_mask_overlap_T_12);\n wire _GEN_302 = do_ld_search_0 & ldq_6_valid & ldq_6_bits_addr_valid & ~ldq_6_bits_addr_is_virtual & dword_addr_matches_6_0 & (|_mask_overlap_T_12);\n wire searcher_is_older_6 = lcam_ldq_idx_0[2:1] != 2'h3 ^ lcam_ldq_idx_0 < ldq_head ^ (&ldq_head);\n reg older_nacked_REG_6;\n wire _GEN_303 = ~_GEN_298 | nacking_loads_6 | older_nacked_REG_6;\n wire _GEN_304 = searcher_is_older_6 | _GEN_239;\n wire _GEN_305 = _GEN_297 | _GEN_301;\n reg io_dmem_s1_kill_0_REG_6;\n wire _GEN_306 = _GEN_305 | ~_GEN_302 | _GEN_304 | ~_GEN_303;\n wire [14:0] _l_mask_mask_T_107 = 15'h1 << ldq_7_bits_addr_bits[2:0];\n wire [14:0] _l_mask_mask_T_111 = 15'h3 << {12'h0, ldq_7_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_307 = {{8'hFF}, {ldq_7_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_l_mask_mask_T_111[7:0]}, {_l_mask_mask_T_107[7:0]}};\n wire l_forwarders_7_0 = wb_forward_valid_0 & (&wb_forward_ldq_idx_0);\n wire block_addr_matches_7_0 = lcam_addr_0[39:6] == ldq_7_bits_addr_bits[39:6];\n wire dword_addr_matches_7_0 = block_addr_matches_7_0 & lcam_addr_0[5:3] == ldq_7_bits_addr_bits[5:3];\n wire [7:0] _mask_overlap_T_14 = _GEN_307[ldq_7_bits_uop_mem_size] & lcam_mask_0;\n wire _GEN_308 = fired_release_0 & ldq_7_valid & ldq_7_bits_addr_valid & block_addr_matches_7_0;\n wire _GEN_309 = ldq_7_bits_executed | ldq_7_bits_succeeded;\n wire _GEN_310 = _GEN_309 | l_forwarders_7_0;\n wire [7:0] _GEN_311 = ldq_7_bits_st_dep_mask >> _GEN_228;\n wire _GEN_312 = do_st_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & _GEN_310 & ~ldq_7_bits_addr_is_virtual & _GEN_311[0] & dword_addr_matches_7_0 & (|_mask_overlap_T_14);\n wire _GEN_313 = do_ld_search_0 & ldq_7_valid & ldq_7_bits_addr_valid & ~ldq_7_bits_addr_is_virtual & dword_addr_matches_7_0 & (|_mask_overlap_T_14);\n wire searcher_is_older_7 = lcam_ldq_idx_0 != 3'h7 ^ lcam_ldq_idx_0 < ldq_head;\n reg older_nacked_REG_7;\n wire _GEN_314 = ~_GEN_309 | nacking_loads_7 | older_nacked_REG_7;\n wire _GEN_315 = _GEN_308 | _GEN_312;\n reg io_dmem_s1_kill_0_REG_7;\n wire _GEN_316 = _GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314);\n wire _GEN_317 = _GEN_316 ? (_GEN_306 ? (_GEN_295 ? (_GEN_284 ? (_GEN_273 ? (_GEN_262 ? (_GEN_251 ? ~_GEN_233 & _GEN_231 & ~searcher_is_older & _GEN_240 & io_dmem_s1_kill_0_REG : io_dmem_s1_kill_0_REG_1) : io_dmem_s1_kill_0_REG_2) : io_dmem_s1_kill_0_REG_3) : io_dmem_s1_kill_0_REG_4) : io_dmem_s1_kill_0_REG_5) : io_dmem_s1_kill_0_REG_6) : io_dmem_s1_kill_0_REG_7;\n wire can_forward_0 = _GEN_316 & _GEN_306 & _GEN_295 & _GEN_284 & _GEN_273 & _GEN_262 & _GEN_251 & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~_GEN_240) & (_can_forward_T ? ~mem_tlb_uncacheable_0 : ~_GEN_191[lcam_ldq_idx_0]);\n wire dword_addr_matches_8_0 = stq_0_bits_addr_valid & ~stq_0_bits_addr_is_virtual & stq_0_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_2 = 15'h1 << stq_0_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_6 = 15'h3 << {12'h0, stq_0_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_318 = {{8'hFF}, {stq_0_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_6[7:0]}, {_write_mask_mask_T_2[7:0]}};\n wire _GEN_319 = do_ld_search_0 & stq_0_valid & lcam_st_dep_mask_0[0];\n wire [7:0] _GEN_320 = lcam_mask_0 & _GEN_318[stq_0_bits_uop_mem_size];\n wire _GEN_321 = _GEN_320 == lcam_mask_0 & ~stq_0_bits_uop_is_fence & ~stq_0_bits_uop_is_amo & dword_addr_matches_8_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_8;\n wire _GEN_322 = (|_GEN_320) & dword_addr_matches_8_0;\n reg io_dmem_s1_kill_0_REG_9;\n wire _GEN_323 = stq_0_bits_uop_is_fence | stq_0_bits_uop_is_amo;\n wire ldst_addr_matches_0_0 = _GEN_319 & (_GEN_321 | _GEN_322 | _GEN_323);\n reg io_dmem_s1_kill_0_REG_10;\n wire _GEN_324 = _GEN_319 ? (_GEN_321 ? io_dmem_s1_kill_0_REG_8 : _GEN_322 ? io_dmem_s1_kill_0_REG_9 : _GEN_323 ? io_dmem_s1_kill_0_REG_10 : _GEN_317) : _GEN_317;\n wire dword_addr_matches_9_0 = stq_1_bits_addr_valid & ~stq_1_bits_addr_is_virtual & stq_1_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_17 = 15'h1 << stq_1_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_21 = 15'h3 << {12'h0, stq_1_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_325 = {{8'hFF}, {stq_1_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_21[7:0]}, {_write_mask_mask_T_17[7:0]}};\n wire _GEN_326 = do_ld_search_0 & stq_1_valid & lcam_st_dep_mask_0[1];\n wire [7:0] _GEN_327 = lcam_mask_0 & _GEN_325[stq_1_bits_uop_mem_size];\n wire _GEN_328 = _GEN_327 == lcam_mask_0 & ~stq_1_bits_uop_is_fence & ~stq_1_bits_uop_is_amo & dword_addr_matches_9_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_11;\n wire _GEN_329 = (|_GEN_327) & dword_addr_matches_9_0;\n reg io_dmem_s1_kill_0_REG_12;\n wire _GEN_330 = stq_1_bits_uop_is_fence | stq_1_bits_uop_is_amo;\n wire ldst_addr_matches_0_1 = _GEN_326 & (_GEN_328 | _GEN_329 | _GEN_330);\n reg io_dmem_s1_kill_0_REG_13;\n wire _GEN_331 = _GEN_326 ? (_GEN_328 ? io_dmem_s1_kill_0_REG_11 : _GEN_329 ? io_dmem_s1_kill_0_REG_12 : _GEN_330 ? io_dmem_s1_kill_0_REG_13 : _GEN_324) : _GEN_324;\n wire dword_addr_matches_10_0 = stq_2_bits_addr_valid & ~stq_2_bits_addr_is_virtual & stq_2_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_32 = 15'h1 << stq_2_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_36 = 15'h3 << {12'h0, stq_2_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_332 = {{8'hFF}, {stq_2_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_36[7:0]}, {_write_mask_mask_T_32[7:0]}};\n wire _GEN_333 = do_ld_search_0 & stq_2_valid & lcam_st_dep_mask_0[2];\n wire [7:0] _GEN_334 = lcam_mask_0 & _GEN_332[stq_2_bits_uop_mem_size];\n wire _GEN_335 = _GEN_334 == lcam_mask_0 & ~stq_2_bits_uop_is_fence & ~stq_2_bits_uop_is_amo & dword_addr_matches_10_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_14;\n wire _GEN_336 = (|_GEN_334) & dword_addr_matches_10_0;\n reg io_dmem_s1_kill_0_REG_15;\n wire _GEN_337 = stq_2_bits_uop_is_fence | stq_2_bits_uop_is_amo;\n wire ldst_addr_matches_0_2 = _GEN_333 & (_GEN_335 | _GEN_336 | _GEN_337);\n reg io_dmem_s1_kill_0_REG_16;\n wire _GEN_338 = _GEN_333 ? (_GEN_335 ? io_dmem_s1_kill_0_REG_14 : _GEN_336 ? io_dmem_s1_kill_0_REG_15 : _GEN_337 ? io_dmem_s1_kill_0_REG_16 : _GEN_331) : _GEN_331;\n wire dword_addr_matches_11_0 = stq_3_bits_addr_valid & ~stq_3_bits_addr_is_virtual & stq_3_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_47 = 15'h1 << stq_3_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_51 = 15'h3 << {12'h0, stq_3_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_339 = {{8'hFF}, {stq_3_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_51[7:0]}, {_write_mask_mask_T_47[7:0]}};\n wire _GEN_340 = do_ld_search_0 & stq_3_valid & lcam_st_dep_mask_0[3];\n wire [7:0] _GEN_341 = lcam_mask_0 & _GEN_339[stq_3_bits_uop_mem_size];\n wire _GEN_342 = _GEN_341 == lcam_mask_0 & ~stq_3_bits_uop_is_fence & ~stq_3_bits_uop_is_amo & dword_addr_matches_11_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_17;\n wire _GEN_343 = (|_GEN_341) & dword_addr_matches_11_0;\n reg io_dmem_s1_kill_0_REG_18;\n wire _GEN_344 = stq_3_bits_uop_is_fence | stq_3_bits_uop_is_amo;\n wire ldst_addr_matches_0_3 = _GEN_340 & (_GEN_342 | _GEN_343 | _GEN_344);\n reg io_dmem_s1_kill_0_REG_19;\n wire _GEN_345 = _GEN_340 ? (_GEN_342 ? io_dmem_s1_kill_0_REG_17 : _GEN_343 ? io_dmem_s1_kill_0_REG_18 : _GEN_344 ? io_dmem_s1_kill_0_REG_19 : _GEN_338) : _GEN_338;\n wire dword_addr_matches_12_0 = stq_4_bits_addr_valid & ~stq_4_bits_addr_is_virtual & stq_4_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_62 = 15'h1 << stq_4_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_66 = 15'h3 << {12'h0, stq_4_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_346 = {{8'hFF}, {stq_4_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_66[7:0]}, {_write_mask_mask_T_62[7:0]}};\n wire _GEN_347 = do_ld_search_0 & stq_4_valid & lcam_st_dep_mask_0[4];\n wire [7:0] _GEN_348 = lcam_mask_0 & _GEN_346[stq_4_bits_uop_mem_size];\n wire _GEN_349 = _GEN_348 == lcam_mask_0 & ~stq_4_bits_uop_is_fence & ~stq_4_bits_uop_is_amo & dword_addr_matches_12_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_20;\n wire _GEN_350 = (|_GEN_348) & dword_addr_matches_12_0;\n reg io_dmem_s1_kill_0_REG_21;\n wire _GEN_351 = stq_4_bits_uop_is_fence | stq_4_bits_uop_is_amo;\n wire ldst_addr_matches_0_4 = _GEN_347 & (_GEN_349 | _GEN_350 | _GEN_351);\n reg io_dmem_s1_kill_0_REG_22;\n wire _GEN_352 = _GEN_347 ? (_GEN_349 ? io_dmem_s1_kill_0_REG_20 : _GEN_350 ? io_dmem_s1_kill_0_REG_21 : _GEN_351 ? io_dmem_s1_kill_0_REG_22 : _GEN_345) : _GEN_345;\n wire dword_addr_matches_13_0 = stq_5_bits_addr_valid & ~stq_5_bits_addr_is_virtual & stq_5_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_77 = 15'h1 << stq_5_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_81 = 15'h3 << {12'h0, stq_5_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_353 = {{8'hFF}, {stq_5_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_81[7:0]}, {_write_mask_mask_T_77[7:0]}};\n wire _GEN_354 = do_ld_search_0 & stq_5_valid & lcam_st_dep_mask_0[5];\n wire [7:0] _GEN_355 = lcam_mask_0 & _GEN_353[stq_5_bits_uop_mem_size];\n wire _GEN_356 = _GEN_355 == lcam_mask_0 & ~stq_5_bits_uop_is_fence & ~stq_5_bits_uop_is_amo & dword_addr_matches_13_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_23;\n wire _GEN_357 = (|_GEN_355) & dword_addr_matches_13_0;\n reg io_dmem_s1_kill_0_REG_24;\n wire _GEN_358 = stq_5_bits_uop_is_fence | stq_5_bits_uop_is_amo;\n wire ldst_addr_matches_0_5 = _GEN_354 & (_GEN_356 | _GEN_357 | _GEN_358);\n reg io_dmem_s1_kill_0_REG_25;\n wire _GEN_359 = _GEN_354 ? (_GEN_356 ? io_dmem_s1_kill_0_REG_23 : _GEN_357 ? io_dmem_s1_kill_0_REG_24 : _GEN_358 ? io_dmem_s1_kill_0_REG_25 : _GEN_352) : _GEN_352;\n wire dword_addr_matches_14_0 = stq_6_bits_addr_valid & ~stq_6_bits_addr_is_virtual & stq_6_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_92 = 15'h1 << stq_6_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_96 = 15'h3 << {12'h0, stq_6_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_360 = {{8'hFF}, {stq_6_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_96[7:0]}, {_write_mask_mask_T_92[7:0]}};\n wire _GEN_361 = do_ld_search_0 & stq_6_valid & lcam_st_dep_mask_0[6];\n wire [7:0] _GEN_362 = lcam_mask_0 & _GEN_360[stq_6_bits_uop_mem_size];\n wire _GEN_363 = _GEN_362 == lcam_mask_0 & ~stq_6_bits_uop_is_fence & ~stq_6_bits_uop_is_amo & dword_addr_matches_14_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_26;\n wire _GEN_364 = (|_GEN_362) & dword_addr_matches_14_0;\n reg io_dmem_s1_kill_0_REG_27;\n wire _GEN_365 = stq_6_bits_uop_is_fence | stq_6_bits_uop_is_amo;\n wire ldst_addr_matches_0_6 = _GEN_361 & (_GEN_363 | _GEN_364 | _GEN_365);\n reg io_dmem_s1_kill_0_REG_28;\n wire _GEN_366 = _GEN_361 ? (_GEN_363 ? io_dmem_s1_kill_0_REG_26 : _GEN_364 ? io_dmem_s1_kill_0_REG_27 : _GEN_365 ? io_dmem_s1_kill_0_REG_28 : _GEN_359) : _GEN_359;\n wire dword_addr_matches_15_0 = stq_7_bits_addr_valid & ~stq_7_bits_addr_is_virtual & stq_7_bits_addr_bits[31:3] == lcam_addr_0[31:3];\n wire [14:0] _write_mask_mask_T_107 = 15'h1 << stq_7_bits_addr_bits[2:0];\n wire [14:0] _write_mask_mask_T_111 = 15'h3 << {12'h0, stq_7_bits_addr_bits[2:1], 1'h0};\n wire [3:0][7:0] _GEN_367 = {{8'hFF}, {stq_7_bits_addr_bits[2] ? 8'hF0 : 8'hF}, {_write_mask_mask_T_111[7:0]}, {_write_mask_mask_T_107[7:0]}};\n wire _GEN_368 = do_ld_search_0 & stq_7_valid & lcam_st_dep_mask_0[7];\n wire [7:0] _GEN_369 = lcam_mask_0 & _GEN_367[stq_7_bits_uop_mem_size];\n wire _GEN_370 = _GEN_369 == lcam_mask_0 & ~stq_7_bits_uop_is_fence & ~stq_7_bits_uop_is_amo & dword_addr_matches_15_0 & can_forward_0;\n reg io_dmem_s1_kill_0_REG_29;\n wire _GEN_371 = (|_GEN_369) & dword_addr_matches_15_0;\n reg io_dmem_s1_kill_0_REG_30;\n wire _GEN_372 = stq_7_bits_uop_is_fence | stq_7_bits_uop_is_amo;\n wire ldst_addr_matches_0_7 = _GEN_368 & (_GEN_370 | _GEN_371 | _GEN_372);\n reg io_dmem_s1_kill_0_REG_31;\n reg REG_1;\n reg REG_2;\n reg [3:0] store_blocked_counter;\n assign block_load_wakeup = (&store_blocked_counter) | REG_2;\n reg r_xcpt_valid;\n reg [7:0] r_xcpt_uop_br_mask;\n reg [4:0] r_xcpt_uop_rob_idx;\n reg [4:0] r_xcpt_cause;\n reg [39:0] r_xcpt_badvaddr;\n wire io_core_spec_ld_wakeup_0_valid_0 = fired_load_incoming_REG & ~mem_incoming_uop_0_fp_val & (|mem_incoming_uop_0_pdst);\n wire _GEN_373 = io_dmem_nack_0_valid & io_dmem_nack_0_bits_is_hella;\n wire _GEN_374 = hella_state == 3'h4;\n wire _GEN_375 = hella_state == 3'h6;\n wire _GEN_376 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella;\n wire _GEN_377 = _GEN_376 & io_dmem_nack_0_bits_uop_uses_ldq & ~reset;\n wire _GEN_378 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h0;\n wire _GEN_379 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h1;\n wire _GEN_380 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h2;\n wire _GEN_381 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h3;\n wire _GEN_382 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h4;\n wire _GEN_383 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h5;\n wire _GEN_384 = io_dmem_nack_0_bits_uop_ldq_idx == 3'h6;\n assign nacking_loads_0 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_378;\n assign nacking_loads_1 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_379;\n assign nacking_loads_2 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_380;\n assign nacking_loads_3 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_381;\n assign nacking_loads_4 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_382;\n assign nacking_loads_5 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_383;\n assign nacking_loads_6 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & _GEN_384;\n assign nacking_loads_7 = io_dmem_nack_0_valid & ~io_dmem_nack_0_bits_is_hella & io_dmem_nack_0_bits_uop_uses_ldq & (&io_dmem_nack_0_bits_uop_ldq_idx);\n wire _GEN_385 = io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq;\n wire send_iresp = _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] == 2'h0;\n wire send_fresp = _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] == 2'h1;\n wire _GEN_386 = io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_is_amo;\n wire dmem_resp_fired_0 = io_dmem_resp_0_valid & (io_dmem_resp_0_bits_uop_uses_ldq | _GEN_386);\n wire _GEN_387 = dmem_resp_fired_0 & wb_forward_valid_0;\n wire _GEN_388 = ~dmem_resp_fired_0 & wb_forward_valid_0;\n wire [7:0] _GEN_389 = _GEN_97[wb_forward_ldq_idx_0];\n wire [4:0] _GEN_390 = _GEN_135[wb_forward_ldq_idx_0];\n wire [5:0] _GEN_391 = _GEN_138[wb_forward_ldq_idx_0];\n wire [1:0] size_1 = _GEN_99[wb_forward_ldq_idx_0];\n wire _GEN_392 = _GEN_151[wb_forward_ldq_idx_0];\n wire _GEN_393 = _GEN_154[wb_forward_ldq_idx_0];\n wire _GEN_394 = _GEN_156[wb_forward_ldq_idx_0];\n wire [1:0] _GEN_395 = _GEN_166[wb_forward_ldq_idx_0];\n wire live = (io_core_brupdate_b1_mispredict_mask & _GEN_389) == 8'h0;\n wire _GEN_396 = _GEN_90[wb_forward_stq_idx_0];\n wire [63:0] _GEN_397 = _GEN_91[wb_forward_stq_idx_0];\n wire [3:0][63:0] _GEN_398 = {{_GEN_397}, {{2{_GEN_397[31:0]}}}, {{2{{2{_GEN_397[15:0]}}}}}, {{2{{2{{2{_GEN_397[7:0]}}}}}}}};\n wire [63:0] _GEN_399 = _GEN_398[_GEN_56[wb_forward_stq_idx_0]];\n wire _GEN_400 = _GEN_387 | ~_GEN_388;\n wire io_core_exe_0_iresp_valid_0 = _GEN_400 ? io_dmem_resp_0_valid & (io_dmem_resp_0_bits_uop_uses_ldq ? send_iresp : _GEN_386) : _GEN_395 == 2'h0 & _GEN_396 & live;\n wire io_core_exe_0_fresp_valid_0 = _GEN_400 ? _GEN_385 & send_fresp : _GEN_395 == 2'h1 & _GEN_396 & live;\n wire [31:0] io_core_exe_0_iresp_bits_data_zeroed = wb_forward_ld_addr_0[2] ? _GEN_399[63:32] : _GEN_399[31:0];\n wire _ldq_bits_debug_wb_data_T_1 = size_1 == 2'h2;\n wire [15:0] io_core_exe_0_iresp_bits_data_zeroed_1 = wb_forward_ld_addr_0[1] ? io_core_exe_0_iresp_bits_data_zeroed[31:16] : io_core_exe_0_iresp_bits_data_zeroed[15:0];\n wire _ldq_bits_debug_wb_data_T_9 = size_1 == 2'h1;\n wire [7:0] io_core_exe_0_iresp_bits_data_zeroed_2 = wb_forward_ld_addr_0[0] ? io_core_exe_0_iresp_bits_data_zeroed_1[15:8] : io_core_exe_0_iresp_bits_data_zeroed_1[7:0];\n wire _ldq_bits_debug_wb_data_T_17 = size_1 == 2'h0;\n wire [31:0] io_core_exe_0_fresp_bits_data_zeroed = wb_forward_ld_addr_0[2] ? _GEN_399[63:32] : _GEN_399[31:0];\n wire [15:0] io_core_exe_0_fresp_bits_data_zeroed_1 = wb_forward_ld_addr_0[1] ? io_core_exe_0_fresp_bits_data_zeroed[31:16] : io_core_exe_0_fresp_bits_data_zeroed[15:0];\n wire [7:0] io_core_exe_0_fresp_bits_data_zeroed_2 = wb_forward_ld_addr_0[0] ? io_core_exe_0_fresp_bits_data_zeroed_1[15:8] : io_core_exe_0_fresp_bits_data_zeroed_1[7:0];\n reg io_core_ld_miss_REG;\n reg spec_ld_succeed_REG;\n reg [2:0] spec_ld_succeed_REG_1;\n wire [7:0] _GEN_401 = io_core_brupdate_b1_mispredict_mask & stq_0_bits_uop_br_mask;\n wire _GEN_402 = stq_0_valid & (|_GEN_401);\n wire [7:0] _GEN_403 = io_core_brupdate_b1_mispredict_mask & stq_1_bits_uop_br_mask;\n wire _GEN_404 = stq_1_valid & (|_GEN_403);\n wire [7:0] _GEN_405 = io_core_brupdate_b1_mispredict_mask & stq_2_bits_uop_br_mask;\n wire _GEN_406 = stq_2_valid & (|_GEN_405);\n wire [7:0] _GEN_407 = io_core_brupdate_b1_mispredict_mask & stq_3_bits_uop_br_mask;\n wire _GEN_408 = stq_3_valid & (|_GEN_407);\n wire [7:0] _GEN_409 = io_core_brupdate_b1_mispredict_mask & stq_4_bits_uop_br_mask;\n wire _GEN_410 = stq_4_valid & (|_GEN_409);\n wire [7:0] _GEN_411 = io_core_brupdate_b1_mispredict_mask & stq_5_bits_uop_br_mask;\n wire _GEN_412 = stq_5_valid & (|_GEN_411);\n wire [7:0] _GEN_413 = io_core_brupdate_b1_mispredict_mask & stq_6_bits_uop_br_mask;\n wire _GEN_414 = stq_6_valid & (|_GEN_413);\n wire [7:0] _GEN_415 = io_core_brupdate_b1_mispredict_mask & stq_7_bits_uop_br_mask;\n wire _GEN_416 = stq_7_valid & (|_GEN_415);\n wire commit_store = io_core_commit_valids_0 & io_core_commit_uops_0_uses_stq;\n wire commit_load = io_core_commit_valids_0 & io_core_commit_uops_0_uses_ldq;\n wire [2:0] idx = commit_store ? stq_commit_head : ldq_head;\n wire _GEN_417 = ~commit_store & commit_load & ~reset;\n wire _GEN_425 = _GEN_58[stq_head];\n wire [7:0] _GEN_426 = {{stq_7_bits_succeeded}, {stq_6_bits_succeeded}, {stq_5_bits_succeeded}, {stq_4_bits_succeeded}, {stq_3_bits_succeeded}, {stq_2_bits_succeeded}, {stq_1_bits_succeeded}, {stq_0_bits_succeeded}};\n wire _GEN_427 = _GEN_3[stq_head] & _GEN_93[stq_head];\n wire _GEN_428 = _GEN_425 & ~io_dmem_ordered;\n assign store_needs_order = _GEN_427 & _GEN_428;\n wire clear_store = _GEN_427 & (_GEN_425 ? io_dmem_ordered : _GEN_426[stq_head]);\n wire io_hellacache_req_ready_0 = hella_state == 3'h0;\n assign _GEN_0 = ~io_hellacache_req_ready_0;\n wire _GEN_429 = hella_state == 3'h3;\n wire _GEN_430 = io_hellacache_req_ready_0 | _GEN_2;\n wire _GEN_431 = hella_state == 3'h2;\n wire _GEN_432 = io_dmem_resp_0_valid & io_dmem_resp_0_bits_is_hella;\n assign _GEN = ~(io_hellacache_req_ready_0 | _GEN_2 | _GEN_429 | _GEN_431 | _GEN_374);\n wire [2:0] _GEN_433 = _GEN_375 & _GEN_432 ? 3'h0 : hella_state;\n wire [7:0] _ldq_7_bits_st_dep_mask_T = 8'h1 << stq_head;\n wire [7:0] _GEN_434 = {8{~clear_store}};\n wire [7:0] next_live_store_mask = (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & live_store_mask;\n wire _GEN_435 = dis_ld_val & ldq_tail == 3'h0;\n wire _GEN_436 = _GEN_435 | ldq_0_valid;\n wire _GEN_437 = dis_ld_val & ldq_tail == 3'h1;\n wire _GEN_438 = _GEN_437 | ldq_1_valid;\n wire _GEN_439 = dis_ld_val & ldq_tail == 3'h2;\n wire _GEN_440 = _GEN_439 | ldq_2_valid;\n wire _GEN_441 = dis_ld_val & ldq_tail == 3'h3;\n wire _GEN_442 = _GEN_441 | ldq_3_valid;\n wire _GEN_443 = dis_ld_val & ldq_tail == 3'h4;\n wire _GEN_444 = _GEN_443 | ldq_4_valid;\n wire _GEN_445 = dis_ld_val & ldq_tail == 3'h5;\n wire _GEN_446 = _GEN_445 | ldq_5_valid;\n wire _GEN_447 = dis_ld_val & ldq_tail == 3'h6;\n wire _GEN_448 = _GEN_447 | ldq_6_valid;\n wire _GEN_449 = dis_ld_val & (&ldq_tail);\n wire _GEN_450 = _GEN_449 | ldq_7_valid;\n wire _GEN_451 = ~_GEN_435 & ldq_0_bits_order_fail;\n wire _GEN_452 = ~_GEN_437 & ldq_1_bits_order_fail;\n wire _GEN_453 = ~_GEN_439 & ldq_2_bits_order_fail;\n wire _GEN_454 = ~_GEN_441 & ldq_3_bits_order_fail;\n wire _GEN_455 = ~_GEN_443 & ldq_4_bits_order_fail;\n wire _GEN_456 = ~_GEN_445 & ldq_5_bits_order_fail;\n wire _GEN_457 = ~_GEN_447 & ldq_6_bits_order_fail;\n wire _GEN_458 = ~_GEN_449 & ldq_7_bits_order_fail;\n wire _GEN_459 = dis_st_val & stq_tail == 3'h0;\n wire _GEN_460 = ~dis_ld_val & _GEN_459 | stq_0_valid;\n wire _GEN_461 = dis_st_val & stq_tail == 3'h1;\n wire _GEN_462 = ~dis_ld_val & _GEN_461 | stq_1_valid;\n wire _GEN_463 = dis_st_val & stq_tail == 3'h2;\n wire _GEN_464 = ~dis_ld_val & _GEN_463 | stq_2_valid;\n wire _GEN_465 = dis_st_val & stq_tail == 3'h3;\n wire _GEN_466 = ~dis_ld_val & _GEN_465 | stq_3_valid;\n wire _GEN_467 = dis_st_val & stq_tail == 3'h4;\n wire _GEN_468 = ~dis_ld_val & _GEN_467 | stq_4_valid;\n wire _GEN_469 = dis_st_val & stq_tail == 3'h5;\n wire _GEN_470 = ~dis_ld_val & _GEN_469 | stq_5_valid;\n wire _GEN_471 = dis_st_val & stq_tail == 3'h6;\n wire _GEN_472 = ~dis_ld_val & _GEN_471 | stq_6_valid;\n wire _GEN_473 = dis_st_val & (&stq_tail);\n wire _GEN_474 = ~dis_ld_val & _GEN_473 | stq_7_valid;\n wire _GEN_475 = dis_ld_val | ~_GEN_459;\n wire _GEN_476 = dis_ld_val | ~_GEN_461;\n wire _GEN_477 = dis_ld_val | ~_GEN_463;\n wire _GEN_478 = dis_ld_val | ~_GEN_465;\n wire _GEN_479 = dis_ld_val | ~_GEN_467;\n wire _GEN_480 = dis_ld_val | ~_GEN_469;\n wire _GEN_481 = dis_ld_val | ~_GEN_471;\n wire _GEN_482 = dis_ld_val | ~_GEN_473;\n wire ldq_retry_idx_block = block_load_mask_0 | p1_block_load_mask_0;\n wire _ldq_retry_idx_T_2 = ldq_0_bits_addr_valid & ldq_0_bits_addr_is_virtual & ~ldq_retry_idx_block;\n wire ldq_retry_idx_block_1 = block_load_mask_1 | p1_block_load_mask_1;\n wire _ldq_retry_idx_T_5 = ldq_1_bits_addr_valid & ldq_1_bits_addr_is_virtual & ~ldq_retry_idx_block_1;\n wire ldq_retry_idx_block_2 = block_load_mask_2 | p1_block_load_mask_2;\n wire _ldq_retry_idx_T_8 = ldq_2_bits_addr_valid & ldq_2_bits_addr_is_virtual & ~ldq_retry_idx_block_2;\n wire ldq_retry_idx_block_3 = block_load_mask_3 | p1_block_load_mask_3;\n wire _ldq_retry_idx_T_11 = ldq_3_bits_addr_valid & ldq_3_bits_addr_is_virtual & ~ldq_retry_idx_block_3;\n wire ldq_retry_idx_block_4 = block_load_mask_4 | p1_block_load_mask_4;\n wire _ldq_retry_idx_T_14 = ldq_4_bits_addr_valid & ldq_4_bits_addr_is_virtual & ~ldq_retry_idx_block_4;\n wire ldq_retry_idx_block_5 = block_load_mask_5 | p1_block_load_mask_5;\n wire _ldq_retry_idx_T_17 = ldq_5_bits_addr_valid & ldq_5_bits_addr_is_virtual & ~ldq_retry_idx_block_5;\n wire ldq_retry_idx_block_6 = block_load_mask_6 | p1_block_load_mask_6;\n wire _ldq_retry_idx_T_20 = ldq_6_bits_addr_valid & ldq_6_bits_addr_is_virtual & ~ldq_retry_idx_block_6;\n wire ldq_retry_idx_block_7 = block_load_mask_7 | p1_block_load_mask_7;\n wire _temp_bits_T = ldq_head == 3'h0;\n wire _temp_bits_T_2 = ldq_head < 3'h2;\n wire _temp_bits_T_4 = ldq_head < 3'h3;\n wire _temp_bits_T_8 = ldq_head < 3'h5;\n wire _temp_bits_T_10 = ldq_head[2:1] != 2'h3;\n wire _temp_bits_T_12 = ldq_head != 3'h7;\n wire _stq_retry_idx_T = stq_0_bits_addr_valid & stq_0_bits_addr_is_virtual;\n wire _stq_retry_idx_T_1 = stq_1_bits_addr_valid & stq_1_bits_addr_is_virtual;\n wire _stq_retry_idx_T_2 = stq_2_bits_addr_valid & stq_2_bits_addr_is_virtual;\n wire _stq_retry_idx_T_3 = stq_3_bits_addr_valid & stq_3_bits_addr_is_virtual;\n wire _stq_retry_idx_T_4 = stq_4_bits_addr_valid & stq_4_bits_addr_is_virtual;\n wire _stq_retry_idx_T_5 = stq_5_bits_addr_valid & stq_5_bits_addr_is_virtual;\n wire _stq_retry_idx_T_6 = stq_6_bits_addr_valid & stq_6_bits_addr_is_virtual;\n wire _ldq_wakeup_idx_T_7 = ldq_0_bits_addr_valid & ~ldq_0_bits_executed & ~ldq_0_bits_succeeded & ~ldq_0_bits_addr_is_virtual & ~ldq_retry_idx_block;\n wire _ldq_wakeup_idx_T_15 = ldq_1_bits_addr_valid & ~ldq_1_bits_executed & ~ldq_1_bits_succeeded & ~ldq_1_bits_addr_is_virtual & ~ldq_retry_idx_block_1;\n wire _ldq_wakeup_idx_T_23 = ldq_2_bits_addr_valid & ~ldq_2_bits_executed & ~ldq_2_bits_succeeded & ~ldq_2_bits_addr_is_virtual & ~ldq_retry_idx_block_2;\n wire _ldq_wakeup_idx_T_31 = ldq_3_bits_addr_valid & ~ldq_3_bits_executed & ~ldq_3_bits_succeeded & ~ldq_3_bits_addr_is_virtual & ~ldq_retry_idx_block_3;\n wire _ldq_wakeup_idx_T_39 = ldq_4_bits_addr_valid & ~ldq_4_bits_executed & ~ldq_4_bits_succeeded & ~ldq_4_bits_addr_is_virtual & ~ldq_retry_idx_block_4;\n wire _ldq_wakeup_idx_T_47 = ldq_5_bits_addr_valid & ~ldq_5_bits_executed & ~ldq_5_bits_succeeded & ~ldq_5_bits_addr_is_virtual & ~ldq_retry_idx_block_5;\n wire _ldq_wakeup_idx_T_55 = ldq_6_bits_addr_valid & ~ldq_6_bits_executed & ~ldq_6_bits_succeeded & ~ldq_6_bits_addr_is_virtual & ~ldq_retry_idx_block_6;\n wire ma_ld_0 = will_fire_load_incoming_0_will_fire & io_core_exe_0_req_bits_mxcpt_valid;\n wire ma_st_0 = _stq_idx_T & io_core_exe_0_req_bits_mxcpt_valid;\n wire pf_ld_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_pf_ld & exe_tlb_uop_0_uses_ldq;\n wire pf_st_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_pf_st & exe_tlb_uop_0_uses_stq;\n wire ae_ld_0 = ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_ae_ld & exe_tlb_uop_0_uses_ldq;\n wire dmem_req_fire_0 = dmem_req_0_valid & io_dmem_req_ready;\n wire [2:0] ldq_idx = will_fire_load_incoming_0_will_fire ? io_core_exe_0_req_bits_uop_ldq_idx : ldq_retry_idx;\n wire _GEN_483 = _GEN_219 & ldq_idx == 3'h0;\n wire _GEN_484 = _GEN_483 | ~_GEN_435 & ldq_0_bits_addr_valid;\n wire _GEN_485 = _GEN_219 & ldq_idx == 3'h1;\n wire _GEN_486 = _GEN_485 | ~_GEN_437 & ldq_1_bits_addr_valid;\n wire _GEN_487 = _GEN_219 & ldq_idx == 3'h2;\n wire _GEN_488 = _GEN_487 | ~_GEN_439 & ldq_2_bits_addr_valid;\n wire _GEN_489 = _GEN_219 & ldq_idx == 3'h3;\n wire _GEN_490 = _GEN_489 | ~_GEN_441 & ldq_3_bits_addr_valid;\n wire _GEN_491 = _GEN_219 & ldq_idx == 3'h4;\n wire _GEN_492 = _GEN_491 | ~_GEN_443 & ldq_4_bits_addr_valid;\n wire _GEN_493 = _GEN_219 & ldq_idx == 3'h5;\n wire _GEN_494 = _GEN_493 | ~_GEN_445 & ldq_5_bits_addr_valid;\n wire _GEN_495 = _GEN_219 & ldq_idx == 3'h6;\n wire _GEN_496 = _GEN_495 | ~_GEN_447 & ldq_6_bits_addr_valid;\n wire _GEN_497 = _GEN_219 & (&ldq_idx);\n wire _GEN_498 = _GEN_497 | ~_GEN_449 & ldq_7_bits_addr_valid;\n wire _ldq_bits_addr_is_uncacheable_T_1 = ~_dtlb_io_resp_0_cacheable & ~exe_tlb_miss_0;\n wire [2:0] stq_idx = _stq_idx_T ? io_core_exe_0_req_bits_uop_stq_idx : stq_retry_idx;\n wire _GEN_499 = _GEN_221 & stq_idx == 3'h0;\n wire _GEN_500 = _GEN_499 ? ~pf_st_0 : _GEN_475 & stq_0_bits_addr_valid;\n wire _GEN_501 = _GEN_221 & stq_idx == 3'h1;\n wire _GEN_502 = _GEN_501 ? ~pf_st_0 : _GEN_476 & stq_1_bits_addr_valid;\n wire _GEN_503 = _GEN_221 & stq_idx == 3'h2;\n wire _GEN_504 = _GEN_503 ? ~pf_st_0 : _GEN_477 & stq_2_bits_addr_valid;\n wire _GEN_505 = _GEN_221 & stq_idx == 3'h3;\n wire _GEN_506 = _GEN_505 ? ~pf_st_0 : _GEN_478 & stq_3_bits_addr_valid;\n wire _GEN_507 = _GEN_221 & stq_idx == 3'h4;\n wire _GEN_508 = _GEN_507 ? ~pf_st_0 : _GEN_479 & stq_4_bits_addr_valid;\n wire _GEN_509 = _GEN_221 & stq_idx == 3'h5;\n wire _GEN_510 = _GEN_509 ? ~pf_st_0 : _GEN_480 & stq_5_bits_addr_valid;\n wire _GEN_511 = _GEN_221 & stq_idx == 3'h6;\n wire _GEN_512 = _GEN_511 ? ~pf_st_0 : _GEN_481 & stq_6_bits_addr_valid;\n wire _GEN_513 = _GEN_221 & (&stq_idx);\n wire _GEN_514 = _GEN_513 ? ~pf_st_0 : _GEN_482 & stq_7_bits_addr_valid;\n wire _GEN_515 = _GEN_222 & sidx == 3'h0;\n wire _GEN_516 = _GEN_515 | _GEN_475 & stq_0_bits_data_valid;\n wire _GEN_517 = _GEN_222 & sidx == 3'h1;\n wire _GEN_518 = _GEN_517 | _GEN_476 & stq_1_bits_data_valid;\n wire _GEN_519 = _GEN_222 & sidx == 3'h2;\n wire _GEN_520 = _GEN_519 | _GEN_477 & stq_2_bits_data_valid;\n wire _GEN_521 = _GEN_222 & sidx == 3'h3;\n wire _GEN_522 = _GEN_521 | _GEN_478 & stq_3_bits_data_valid;\n wire _GEN_523 = _GEN_222 & sidx == 3'h4;\n wire _GEN_524 = _GEN_523 | _GEN_479 & stq_4_bits_data_valid;\n wire _GEN_525 = _GEN_222 & sidx == 3'h5;\n wire _GEN_526 = _GEN_525 | _GEN_480 & stq_5_bits_data_valid;\n wire _GEN_527 = _GEN_222 & sidx == 3'h6;\n wire _GEN_528 = _GEN_527 | _GEN_481 & stq_6_bits_data_valid;\n wire _GEN_529 = _GEN_222 & (&sidx);\n wire _GEN_530 = _GEN_529 | _GEN_482 & stq_7_bits_data_valid;\n wire [63:0] _stq_bits_data_bits_T_1 = _stq_bits_data_bits_T ? io_core_exe_0_req_bits_data : io_core_fp_stdata_bits_data;\n wire _fired_std_incoming_T = (io_core_brupdate_b1_mispredict_mask & io_core_exe_0_req_bits_uop_br_mask) == 8'h0;\n wire [7:0] _mem_stq_retry_e_out_valid_T = io_core_brupdate_b1_mispredict_mask & _GEN_186;\n wire [2:0] l_forward_stq_idx = l_forwarders_0 ? wb_forward_stq_idx_0 : ldq_0_bits_forward_stq_idx;\n wire _GEN_531 = ~ldq_0_bits_forward_std_val | l_forward_stq_idx != lcam_stq_idx_0 & (l_forward_stq_idx < lcam_stq_idx_0 ^ l_forward_stq_idx < ldq_0_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_0_bits_youngest_stq_idx);\n wire _GEN_532 = _GEN_227 & ~s1_executing_loads_0 & ldq_0_bits_observed;\n wire failed_loads_0 = ~_GEN_225 & (_GEN_230 ? _GEN_531 : _GEN_231 & searcher_is_older & _GEN_532);\n wire [2:0] l_forward_stq_idx_1 = l_forwarders_1_0 ? wb_forward_stq_idx_0 : ldq_1_bits_forward_stq_idx;\n wire _GEN_533 = ~ldq_1_bits_forward_std_val | l_forward_stq_idx_1 != lcam_stq_idx_0 & (l_forward_stq_idx_1 < lcam_stq_idx_0 ^ l_forward_stq_idx_1 < ldq_1_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_1_bits_youngest_stq_idx);\n wire _GEN_534 = _GEN_244 & ~s1_executing_loads_1 & ldq_1_bits_observed;\n wire failed_loads_1 = ~_GEN_242 & (_GEN_246 ? _GEN_533 : _GEN_247 & searcher_is_older_1 & _GEN_534);\n wire [2:0] l_forward_stq_idx_2 = l_forwarders_2_0 ? wb_forward_stq_idx_0 : ldq_2_bits_forward_stq_idx;\n wire _GEN_535 = ~ldq_2_bits_forward_std_val | l_forward_stq_idx_2 != lcam_stq_idx_0 & (l_forward_stq_idx_2 < lcam_stq_idx_0 ^ l_forward_stq_idx_2 < ldq_2_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_2_bits_youngest_stq_idx);\n wire _GEN_536 = _GEN_255 & ~s1_executing_loads_2 & ldq_2_bits_observed;\n wire failed_loads_2 = ~_GEN_253 & (_GEN_257 ? _GEN_535 : _GEN_258 & searcher_is_older_2 & _GEN_536);\n wire [2:0] l_forward_stq_idx_3 = l_forwarders_3_0 ? wb_forward_stq_idx_0 : ldq_3_bits_forward_stq_idx;\n wire _GEN_537 = ~ldq_3_bits_forward_std_val | l_forward_stq_idx_3 != lcam_stq_idx_0 & (l_forward_stq_idx_3 < lcam_stq_idx_0 ^ l_forward_stq_idx_3 < ldq_3_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_3_bits_youngest_stq_idx);\n wire _GEN_538 = _GEN_266 & ~s1_executing_loads_3 & ldq_3_bits_observed;\n wire failed_loads_3 = ~_GEN_264 & (_GEN_268 ? _GEN_537 : _GEN_269 & searcher_is_older_3 & _GEN_538);\n wire [2:0] l_forward_stq_idx_4 = l_forwarders_4_0 ? wb_forward_stq_idx_0 : ldq_4_bits_forward_stq_idx;\n wire _GEN_539 = ~ldq_4_bits_forward_std_val | l_forward_stq_idx_4 != lcam_stq_idx_0 & (l_forward_stq_idx_4 < lcam_stq_idx_0 ^ l_forward_stq_idx_4 < ldq_4_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_4_bits_youngest_stq_idx);\n wire _GEN_540 = _GEN_277 & ~s1_executing_loads_4 & ldq_4_bits_observed;\n wire failed_loads_4 = ~_GEN_275 & (_GEN_279 ? _GEN_539 : _GEN_280 & searcher_is_older_4 & _GEN_540);\n wire [2:0] l_forward_stq_idx_5 = l_forwarders_5_0 ? wb_forward_stq_idx_0 : ldq_5_bits_forward_stq_idx;\n wire _GEN_541 = ~ldq_5_bits_forward_std_val | l_forward_stq_idx_5 != lcam_stq_idx_0 & (l_forward_stq_idx_5 < lcam_stq_idx_0 ^ l_forward_stq_idx_5 < ldq_5_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_5_bits_youngest_stq_idx);\n wire _GEN_542 = _GEN_288 & ~s1_executing_loads_5 & ldq_5_bits_observed;\n wire failed_loads_5 = ~_GEN_286 & (_GEN_290 ? _GEN_541 : _GEN_291 & searcher_is_older_5 & _GEN_542);\n wire [2:0] l_forward_stq_idx_6 = l_forwarders_6_0 ? wb_forward_stq_idx_0 : ldq_6_bits_forward_stq_idx;\n wire _GEN_543 = ~ldq_6_bits_forward_std_val | l_forward_stq_idx_6 != lcam_stq_idx_0 & (l_forward_stq_idx_6 < lcam_stq_idx_0 ^ l_forward_stq_idx_6 < ldq_6_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_6_bits_youngest_stq_idx);\n wire _GEN_544 = _GEN_299 & ~s1_executing_loads_6 & ldq_6_bits_observed;\n wire failed_loads_6 = ~_GEN_297 & (_GEN_301 ? _GEN_543 : _GEN_302 & searcher_is_older_6 & _GEN_544);\n wire _GEN_545 = (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & (&lcam_ldq_idx_0))) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & (&lcam_ldq_idx_0))) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & (&lcam_ldq_idx_0))) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & (&lcam_ldq_idx_0))) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & (&lcam_ldq_idx_0))) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & (&lcam_ldq_idx_0))) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & (&lcam_ldq_idx_0))) & s1_executing_loads_7;\n wire [2:0] l_forward_stq_idx_7 = l_forwarders_7_0 ? wb_forward_stq_idx_0 : ldq_7_bits_forward_stq_idx;\n wire _GEN_546 = ~ldq_7_bits_forward_std_val | l_forward_stq_idx_7 != lcam_stq_idx_0 & (l_forward_stq_idx_7 < lcam_stq_idx_0 ^ l_forward_stq_idx_7 < ldq_7_bits_youngest_stq_idx ^ lcam_stq_idx_0 < ldq_7_bits_youngest_stq_idx);\n wire _GEN_547 = _GEN_310 & ~s1_executing_loads_7 & ldq_7_bits_observed;\n wire failed_loads_7 = ~_GEN_308 & (_GEN_312 ? _GEN_546 : _GEN_313 & searcher_is_older_7 & _GEN_547);\n wire _GEN_548 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & ~(|lcam_ldq_idx_0))) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & ~(|lcam_ldq_idx_0))) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & ~(|lcam_ldq_idx_0))) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & ~(|lcam_ldq_idx_0))) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & ~(|lcam_ldq_idx_0))) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & ~(|lcam_ldq_idx_0))) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & ~(|lcam_ldq_idx_0))) & s1_executing_loads_0;\n wire _GEN_549 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_234)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_234)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_234)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_234)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_234)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_234)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_234)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_234)) & s1_executing_loads_1;\n wire _GEN_550 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_235)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_235)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_235)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_235)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_235)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_235)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_235)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_235)) & s1_executing_loads_2;\n wire _GEN_551 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_236)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_236)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_236)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_236)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_236)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_236)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_236)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_236)) & s1_executing_loads_3;\n wire _GEN_552 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_237)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_237)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_237)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_237)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_237)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_237)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_237)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_237)) & s1_executing_loads_4;\n wire _GEN_553 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_238)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_238)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_238)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_238)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_238)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_238)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_238)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_238)) & s1_executing_loads_5;\n wire _GEN_554 = (_GEN_315 | ~_GEN_313 | searcher_is_older_7 | ~(~(&lcam_ldq_idx_0) & _GEN_314 & _GEN_239)) & (_GEN_305 | ~_GEN_302 | _GEN_304 | ~(_GEN_303 & _GEN_239)) & (_GEN_294 | ~_GEN_291 | _GEN_293 | ~(_GEN_292 & _GEN_239)) & (_GEN_283 | ~_GEN_280 | _GEN_282 | ~(_GEN_281 & _GEN_239)) & (_GEN_272 | ~_GEN_269 | _GEN_271 | ~(_GEN_270 & _GEN_239)) & (_GEN_261 | ~_GEN_258 | _GEN_260 | ~(_GEN_259 & _GEN_239)) & (_GEN_250 | ~_GEN_247 | _GEN_249 | ~(_GEN_248 & _GEN_239)) & (_GEN_233 | ~_GEN_231 | searcher_is_older | ~((|lcam_ldq_idx_0) & _GEN_232 & _GEN_239)) & s1_executing_loads_6;\n wire _GEN_555 = _GEN_321 | _GEN_322;\n wire _GEN_556 = _GEN_319 ? (_GEN_555 ? (|lcam_ldq_idx_0) & _GEN_548 : ~(_GEN_323 & ~(|lcam_ldq_idx_0)) & _GEN_548) : _GEN_548;\n wire _GEN_557 = _GEN_319 ? (_GEN_555 ? ~_GEN_234 & _GEN_549 : ~(_GEN_323 & _GEN_234) & _GEN_549) : _GEN_549;\n wire _GEN_558 = _GEN_319 ? (_GEN_555 ? ~_GEN_235 & _GEN_550 : ~(_GEN_323 & _GEN_235) & _GEN_550) : _GEN_550;\n wire _GEN_559 = _GEN_319 ? (_GEN_555 ? ~_GEN_236 & _GEN_551 : ~(_GEN_323 & _GEN_236) & _GEN_551) : _GEN_551;\n wire _GEN_560 = _GEN_319 ? (_GEN_555 ? ~_GEN_237 & _GEN_552 : ~(_GEN_323 & _GEN_237) & _GEN_552) : _GEN_552;\n wire _GEN_561 = _GEN_319 ? (_GEN_555 ? ~_GEN_238 & _GEN_553 : ~(_GEN_323 & _GEN_238) & _GEN_553) : _GEN_553;\n wire _GEN_562 = _GEN_319 ? (_GEN_555 ? ~_GEN_239 & _GEN_554 : ~(_GEN_323 & _GEN_239) & _GEN_554) : _GEN_554;\n wire _GEN_563 = _GEN_319 ? (_GEN_555 ? ~(&lcam_ldq_idx_0) & _GEN_545 : ~(_GEN_323 & (&lcam_ldq_idx_0)) & _GEN_545) : _GEN_545;\n wire _GEN_564 = _GEN_328 | _GEN_329;\n wire _GEN_565 = _GEN_326 ? (_GEN_564 ? (|lcam_ldq_idx_0) & _GEN_556 : ~(_GEN_330 & ~(|lcam_ldq_idx_0)) & _GEN_556) : _GEN_556;\n wire _GEN_566 = _GEN_326 ? (_GEN_564 ? ~_GEN_234 & _GEN_557 : ~(_GEN_330 & _GEN_234) & _GEN_557) : _GEN_557;\n wire _GEN_567 = _GEN_326 ? (_GEN_564 ? ~_GEN_235 & _GEN_558 : ~(_GEN_330 & _GEN_235) & _GEN_558) : _GEN_558;\n wire _GEN_568 = _GEN_326 ? (_GEN_564 ? ~_GEN_236 & _GEN_559 : ~(_GEN_330 & _GEN_236) & _GEN_559) : _GEN_559;\n wire _GEN_569 = _GEN_326 ? (_GEN_564 ? ~_GEN_237 & _GEN_560 : ~(_GEN_330 & _GEN_237) & _GEN_560) : _GEN_560;\n wire _GEN_570 = _GEN_326 ? (_GEN_564 ? ~_GEN_238 & _GEN_561 : ~(_GEN_330 & _GEN_238) & _GEN_561) : _GEN_561;\n wire _GEN_571 = _GEN_326 ? (_GEN_564 ? ~_GEN_239 & _GEN_562 : ~(_GEN_330 & _GEN_239) & _GEN_562) : _GEN_562;\n wire _GEN_572 = _GEN_326 ? (_GEN_564 ? ~(&lcam_ldq_idx_0) & _GEN_563 : ~(_GEN_330 & (&lcam_ldq_idx_0)) & _GEN_563) : _GEN_563;\n wire _GEN_573 = _GEN_335 | _GEN_336;\n wire _GEN_574 = _GEN_333 ? (_GEN_573 ? (|lcam_ldq_idx_0) & _GEN_565 : ~(_GEN_337 & ~(|lcam_ldq_idx_0)) & _GEN_565) : _GEN_565;\n wire _GEN_575 = _GEN_333 ? (_GEN_573 ? ~_GEN_234 & _GEN_566 : ~(_GEN_337 & _GEN_234) & _GEN_566) : _GEN_566;\n wire _GEN_576 = _GEN_333 ? (_GEN_573 ? ~_GEN_235 & _GEN_567 : ~(_GEN_337 & _GEN_235) & _GEN_567) : _GEN_567;\n wire _GEN_577 = _GEN_333 ? (_GEN_573 ? ~_GEN_236 & _GEN_568 : ~(_GEN_337 & _GEN_236) & _GEN_568) : _GEN_568;\n wire _GEN_578 = _GEN_333 ? (_GEN_573 ? ~_GEN_237 & _GEN_569 : ~(_GEN_337 & _GEN_237) & _GEN_569) : _GEN_569;\n wire _GEN_579 = _GEN_333 ? (_GEN_573 ? ~_GEN_238 & _GEN_570 : ~(_GEN_337 & _GEN_238) & _GEN_570) : _GEN_570;\n wire _GEN_580 = _GEN_333 ? (_GEN_573 ? ~_GEN_239 & _GEN_571 : ~(_GEN_337 & _GEN_239) & _GEN_571) : _GEN_571;\n wire _GEN_581 = _GEN_333 ? (_GEN_573 ? ~(&lcam_ldq_idx_0) & _GEN_572 : ~(_GEN_337 & (&lcam_ldq_idx_0)) & _GEN_572) : _GEN_572;\n wire _GEN_582 = _GEN_342 | _GEN_343;\n wire _GEN_583 = _GEN_340 ? (_GEN_582 ? (|lcam_ldq_idx_0) & _GEN_574 : ~(_GEN_344 & ~(|lcam_ldq_idx_0)) & _GEN_574) : _GEN_574;\n wire _GEN_584 = _GEN_340 ? (_GEN_582 ? ~_GEN_234 & _GEN_575 : ~(_GEN_344 & _GEN_234) & _GEN_575) : _GEN_575;\n wire _GEN_585 = _GEN_340 ? (_GEN_582 ? ~_GEN_235 & _GEN_576 : ~(_GEN_344 & _GEN_235) & _GEN_576) : _GEN_576;\n wire _GEN_586 = _GEN_340 ? (_GEN_582 ? ~_GEN_236 & _GEN_577 : ~(_GEN_344 & _GEN_236) & _GEN_577) : _GEN_577;\n wire _GEN_587 = _GEN_340 ? (_GEN_582 ? ~_GEN_237 & _GEN_578 : ~(_GEN_344 & _GEN_237) & _GEN_578) : _GEN_578;\n wire _GEN_588 = _GEN_340 ? (_GEN_582 ? ~_GEN_238 & _GEN_579 : ~(_GEN_344 & _GEN_238) & _GEN_579) : _GEN_579;\n wire _GEN_589 = _GEN_340 ? (_GEN_582 ? ~_GEN_239 & _GEN_580 : ~(_GEN_344 & _GEN_239) & _GEN_580) : _GEN_580;\n wire _GEN_590 = _GEN_340 ? (_GEN_582 ? ~(&lcam_ldq_idx_0) & _GEN_581 : ~(_GEN_344 & (&lcam_ldq_idx_0)) & _GEN_581) : _GEN_581;\n wire _GEN_591 = _GEN_349 | _GEN_350;\n wire _GEN_592 = _GEN_347 ? (_GEN_591 ? (|lcam_ldq_idx_0) & _GEN_583 : ~(_GEN_351 & ~(|lcam_ldq_idx_0)) & _GEN_583) : _GEN_583;\n wire _GEN_593 = _GEN_347 ? (_GEN_591 ? ~_GEN_234 & _GEN_584 : ~(_GEN_351 & _GEN_234) & _GEN_584) : _GEN_584;\n wire _GEN_594 = _GEN_347 ? (_GEN_591 ? ~_GEN_235 & _GEN_585 : ~(_GEN_351 & _GEN_235) & _GEN_585) : _GEN_585;\n wire _GEN_595 = _GEN_347 ? (_GEN_591 ? ~_GEN_236 & _GEN_586 : ~(_GEN_351 & _GEN_236) & _GEN_586) : _GEN_586;\n wire _GEN_596 = _GEN_347 ? (_GEN_591 ? ~_GEN_237 & _GEN_587 : ~(_GEN_351 & _GEN_237) & _GEN_587) : _GEN_587;\n wire _GEN_597 = _GEN_347 ? (_GEN_591 ? ~_GEN_238 & _GEN_588 : ~(_GEN_351 & _GEN_238) & _GEN_588) : _GEN_588;\n wire _GEN_598 = _GEN_347 ? (_GEN_591 ? ~_GEN_239 & _GEN_589 : ~(_GEN_351 & _GEN_239) & _GEN_589) : _GEN_589;\n wire _GEN_599 = _GEN_347 ? (_GEN_591 ? ~(&lcam_ldq_idx_0) & _GEN_590 : ~(_GEN_351 & (&lcam_ldq_idx_0)) & _GEN_590) : _GEN_590;\n wire _GEN_600 = _GEN_356 | _GEN_357;\n wire _GEN_601 = _GEN_354 ? (_GEN_600 ? (|lcam_ldq_idx_0) & _GEN_592 : ~(_GEN_358 & ~(|lcam_ldq_idx_0)) & _GEN_592) : _GEN_592;\n wire _GEN_602 = _GEN_354 ? (_GEN_600 ? ~_GEN_234 & _GEN_593 : ~(_GEN_358 & _GEN_234) & _GEN_593) : _GEN_593;\n wire _GEN_603 = _GEN_354 ? (_GEN_600 ? ~_GEN_235 & _GEN_594 : ~(_GEN_358 & _GEN_235) & _GEN_594) : _GEN_594;\n wire _GEN_604 = _GEN_354 ? (_GEN_600 ? ~_GEN_236 & _GEN_595 : ~(_GEN_358 & _GEN_236) & _GEN_595) : _GEN_595;\n wire _GEN_605 = _GEN_354 ? (_GEN_600 ? ~_GEN_237 & _GEN_596 : ~(_GEN_358 & _GEN_237) & _GEN_596) : _GEN_596;\n wire _GEN_606 = _GEN_354 ? (_GEN_600 ? ~_GEN_238 & _GEN_597 : ~(_GEN_358 & _GEN_238) & _GEN_597) : _GEN_597;\n wire _GEN_607 = _GEN_354 ? (_GEN_600 ? ~_GEN_239 & _GEN_598 : ~(_GEN_358 & _GEN_239) & _GEN_598) : _GEN_598;\n wire _GEN_608 = _GEN_354 ? (_GEN_600 ? ~(&lcam_ldq_idx_0) & _GEN_599 : ~(_GEN_358 & (&lcam_ldq_idx_0)) & _GEN_599) : _GEN_599;\n wire _GEN_609 = _GEN_363 | _GEN_364;\n wire _GEN_610 = _GEN_361 ? (_GEN_609 ? (|lcam_ldq_idx_0) & _GEN_601 : ~(_GEN_365 & ~(|lcam_ldq_idx_0)) & _GEN_601) : _GEN_601;\n wire _GEN_611 = _GEN_361 ? (_GEN_609 ? ~_GEN_234 & _GEN_602 : ~(_GEN_365 & _GEN_234) & _GEN_602) : _GEN_602;\n wire _GEN_612 = _GEN_361 ? (_GEN_609 ? ~_GEN_235 & _GEN_603 : ~(_GEN_365 & _GEN_235) & _GEN_603) : _GEN_603;\n wire _GEN_613 = _GEN_361 ? (_GEN_609 ? ~_GEN_236 & _GEN_604 : ~(_GEN_365 & _GEN_236) & _GEN_604) : _GEN_604;\n wire _GEN_614 = _GEN_361 ? (_GEN_609 ? ~_GEN_237 & _GEN_605 : ~(_GEN_365 & _GEN_237) & _GEN_605) : _GEN_605;\n wire _GEN_615 = _GEN_361 ? (_GEN_609 ? ~_GEN_238 & _GEN_606 : ~(_GEN_365 & _GEN_238) & _GEN_606) : _GEN_606;\n wire _GEN_616 = _GEN_361 ? (_GEN_609 ? ~_GEN_239 & _GEN_607 : ~(_GEN_365 & _GEN_239) & _GEN_607) : _GEN_607;\n wire _GEN_617 = _GEN_361 ? (_GEN_609 ? ~(&lcam_ldq_idx_0) & _GEN_608 : ~(_GEN_365 & (&lcam_ldq_idx_0)) & _GEN_608) : _GEN_608;\n wire _GEN_618 = _GEN_370 | _GEN_371;\n wire [7:0] _GEN_619 = {{_GEN_368 & _GEN_370}, {_GEN_361 & _GEN_363}, {_GEN_354 & _GEN_356}, {_GEN_347 & _GEN_349}, {_GEN_340 & _GEN_342}, {_GEN_333 & _GEN_335}, {_GEN_326 & _GEN_328}, {_GEN_319 & _GEN_321}};\n wire mem_forward_valid_0 = _GEN_619[_forwarding_age_logic_0_io_forwarding_idx] & (io_core_brupdate_b1_mispredict_mask & (do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_br_mask : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_br_mask : 8'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_br_mask : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_br_mask : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_br_mask : 8'h0) : 8'h0)) == 8'h0 & ~io_core_exception & ~REG_1;\n wire [2:0] l_idx = failed_loads_0 & _temp_bits_T ? 3'h0 : failed_loads_1 & _temp_bits_T_2 ? 3'h1 : failed_loads_2 & _temp_bits_T_4 ? 3'h2 : failed_loads_3 & ~(ldq_head[2]) ? 3'h3 : failed_loads_4 & _temp_bits_T_8 ? 3'h4 : failed_loads_5 & _temp_bits_T_10 ? 3'h5 : failed_loads_6 & _temp_bits_T_12 ? 3'h6 : failed_loads_7 ? 3'h7 : failed_loads_0 ? 3'h0 : failed_loads_1 ? 3'h1 : failed_loads_2 ? 3'h2 : failed_loads_3 ? 3'h3 : failed_loads_4 ? 3'h4 : failed_loads_5 ? 3'h5 : {2'h3, ~failed_loads_6};\n wire ld_xcpt_valid = failed_loads_0 | failed_loads_1 | failed_loads_2 | failed_loads_3 | failed_loads_4 | failed_loads_5 | failed_loads_6 | failed_loads_7;\n wire use_mem_xcpt = mem_xcpt_valids_0 & (mem_xcpt_uops_0_rob_idx < _GEN_135[l_idx] ^ mem_xcpt_uops_0_rob_idx < io_core_rob_head_idx ^ _GEN_135[l_idx] < io_core_rob_head_idx) | ~ld_xcpt_valid;\n wire [7:0] xcpt_uop_br_mask = use_mem_xcpt ? mem_xcpt_uops_0_br_mask : _GEN_97[l_idx];\n wire _ldq_bits_succeeded_T = io_core_exe_0_iresp_valid_0 | io_core_exe_0_fresp_valid_0;\n wire _GEN_620 = _GEN_396 & live;\n wire _GEN_621 = _GEN_388 & _GEN_620 & ~(|wb_forward_ldq_idx_0);\n wire _GEN_622 = _GEN_387 | ~_GEN_621;\n wire _GEN_623 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h1;\n wire _GEN_624 = _GEN_387 | ~_GEN_623;\n wire _GEN_625 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h2;\n wire _GEN_626 = _GEN_387 | ~_GEN_625;\n wire _GEN_627 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h3;\n wire _GEN_628 = _GEN_387 | ~_GEN_627;\n wire _GEN_629 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h4;\n wire _GEN_630 = _GEN_387 | ~_GEN_629;\n wire _GEN_631 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h5;\n wire _GEN_632 = _GEN_387 | ~_GEN_631;\n wire _GEN_633 = _GEN_388 & _GEN_620 & wb_forward_ldq_idx_0 == 3'h6;\n wire _GEN_634 = _GEN_387 | ~_GEN_633;\n wire _GEN_635 = _GEN_388 & _GEN_620 & (&wb_forward_ldq_idx_0);\n wire _GEN_636 = _GEN_387 | ~_GEN_635;\n wire _GEN_637 = ldq_0_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_0_bits_uop_br_mask));\n wire _GEN_638 = ldq_1_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_1_bits_uop_br_mask));\n wire _GEN_639 = ldq_2_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_2_bits_uop_br_mask));\n wire _GEN_640 = ldq_3_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_3_bits_uop_br_mask));\n wire _GEN_641 = ldq_4_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_4_bits_uop_br_mask));\n wire _GEN_642 = ldq_5_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_5_bits_uop_br_mask));\n wire _GEN_643 = ldq_6_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_6_bits_uop_br_mask));\n wire _GEN_644 = ldq_7_valid & (|(io_core_brupdate_b1_mispredict_mask & ldq_7_bits_uop_br_mask));\n wire _GEN_645 = idx == 3'h0;\n wire _GEN_646 = idx == 3'h1;\n wire _GEN_647 = idx == 3'h2;\n wire _GEN_648 = idx == 3'h3;\n wire _GEN_649 = idx == 3'h4;\n wire _GEN_650 = idx == 3'h5;\n wire _GEN_651 = idx == 3'h6;\n wire _GEN_652 = _GEN_645 | _GEN_637;\n wire _GEN_653 = commit_store | ~commit_load;\n wire _GEN_654 = _GEN_646 | _GEN_638;\n wire _GEN_655 = _GEN_647 | _GEN_639;\n wire _GEN_656 = _GEN_648 | _GEN_640;\n wire _GEN_657 = _GEN_649 | _GEN_641;\n wire _GEN_658 = _GEN_650 | _GEN_642;\n wire _GEN_659 = _GEN_651 | _GEN_643;\n wire _GEN_660 = (&idx) | _GEN_644;\n wire _GEN_661 = commit_store | ~(commit_load & _GEN_645);\n wire _GEN_662 = commit_store | ~(commit_load & _GEN_646);\n wire _GEN_663 = commit_store | ~(commit_load & _GEN_647);\n wire _GEN_664 = commit_store | ~(commit_load & _GEN_648);\n wire _GEN_665 = commit_store | ~(commit_load & _GEN_649);\n wire _GEN_666 = commit_store | ~(commit_load & _GEN_650);\n wire _GEN_667 = commit_store | ~(commit_load & _GEN_651);\n wire _GEN_668 = commit_store | ~(commit_load & (&idx));\n wire _GEN_669 = stq_head == 3'h0;\n wire _GEN_670 = _GEN_669 | _GEN_402;\n wire _GEN_671 = stq_head == 3'h1;\n wire _GEN_672 = _GEN_671 | _GEN_404;\n wire _GEN_673 = stq_head == 3'h2;\n wire _GEN_674 = _GEN_673 | _GEN_406;\n wire _GEN_675 = stq_head == 3'h3;\n wire _GEN_676 = _GEN_675 | _GEN_408;\n wire _GEN_677 = stq_head == 3'h4;\n wire _GEN_678 = _GEN_677 | _GEN_410;\n wire _GEN_679 = stq_head == 3'h5;\n wire _GEN_680 = _GEN_679 | _GEN_412;\n wire _GEN_681 = stq_head == 3'h6;\n wire _GEN_682 = _GEN_681 | _GEN_414;\n wire _GEN_683 = (&stq_head) | _GEN_416;\n wire _GEN_684 = clear_store & _GEN_669;\n wire _GEN_685 = clear_store & _GEN_671;\n wire _GEN_686 = clear_store & _GEN_673;\n wire _GEN_687 = clear_store & _GEN_675;\n wire _GEN_688 = clear_store & _GEN_677;\n wire _GEN_689 = clear_store & _GEN_679;\n wire _GEN_690 = clear_store & _GEN_681;\n wire _GEN_691 = clear_store & (&stq_head);\n wire _GEN_692 = io_hellacache_req_ready_0 & io_hellacache_req_valid;\n wire _GEN_693 = io_hellacache_req_ready_0 | ~_GEN_2;\n wire _GEN_694 = reset | io_core_exception;\n wire _GEN_695 = _GEN_694 & reset;\n wire _GEN_696 = ~stq_0_bits_committed & ~stq_0_bits_succeeded;\n wire _GEN_697 = _GEN_694 & (reset | _GEN_696);\n wire _GEN_698 = ~stq_1_bits_committed & ~stq_1_bits_succeeded;\n wire _GEN_699 = _GEN_694 & (reset | _GEN_698);\n wire _GEN_700 = ~stq_2_bits_committed & ~stq_2_bits_succeeded;\n wire _GEN_701 = _GEN_694 & (reset | _GEN_700);\n wire _GEN_702 = ~stq_3_bits_committed & ~stq_3_bits_succeeded;\n wire _GEN_703 = _GEN_694 & (reset | _GEN_702);\n wire _GEN_704 = ~stq_4_bits_committed & ~stq_4_bits_succeeded;\n wire _GEN_705 = _GEN_694 & (reset | _GEN_704);\n wire _GEN_706 = ~stq_5_bits_committed & ~stq_5_bits_succeeded;\n wire _GEN_707 = _GEN_694 & (reset | _GEN_706);\n wire _GEN_708 = ~stq_6_bits_committed & ~stq_6_bits_succeeded;\n wire _GEN_709 = _GEN_694 & (reset | _GEN_708);\n wire _GEN_710 = ~stq_7_bits_committed & ~stq_7_bits_succeeded;\n wire _GEN_711 = _GEN_694 & (reset | _GEN_710);\n wire _GEN_712 = will_fire_hella_incoming_0_will_fire & dmem_req_fire_0;\n wire [7:0][2:0] _GEN_713 = {{_GEN_433}, {_GEN_433}, {will_fire_hella_wakeup_0_will_fire & dmem_req_fire_0 ? 3'h4 : hella_state}, {_GEN_432 ? 3'h0 : _GEN_373 ? 3'h5 : hella_state}, {3'h0}, {{1'h1, |{hella_xcpt_ma_ld, hella_xcpt_ma_st, hella_xcpt_pf_ld, hella_xcpt_pf_st, hella_xcpt_gf_ld, hella_xcpt_gf_st, hella_xcpt_ae_ld, hella_xcpt_ae_st}, 1'h0}}, {io_hellacache_s1_kill ? (_GEN_712 ? 3'h6 : 3'h0) : {2'h1, ~_GEN_712}}, {_GEN_692 ? 3'h1 : hella_state}};\n always @(posedge clock) begin\n if (_GEN_377)\n assert__assert_23: assert(_GEN_101[io_dmem_nack_0_bits_uop_ldq_idx]);\n if (_GEN_417)\n assert__assert_36: assert(_GEN_96[idx]);\n ldq_0_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_637 & _GEN_436 : ~_GEN_652 & _GEN_436);\n if (_GEN_435) begin\n ldq_0_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_0_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_0_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_0_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_0_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_0_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_0_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_0_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_0_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_0_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_0_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_0_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_0_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_0_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_0_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_0_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_0_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_0_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_0_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_0_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_0_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_0_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_0_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_0_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_0_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_0_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_0_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_0_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_0_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_0_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_0_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_0_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_0_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_0_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_0_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_0_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_0_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_0_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_0_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_0_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_0_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_0_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_0_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_0_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_0_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_0_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_0_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_0_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_0_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_0_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_0_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_0_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_0_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_0_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_0_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_0_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_0_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_0_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_0_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_0_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_0_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_0_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_0_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_0_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_0_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_0_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_0_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_0_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_0_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_0_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_0_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_0_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_0_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_0_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_0_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_0_valid)\n ldq_0_bits_uop_br_mask <= ldq_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_435)\n ldq_0_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_483) begin\n if (_exe_tlb_uop_T_2)\n ldq_0_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_0_bits_uop_pdst <= _GEN_139;\n else\n ldq_0_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_0_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_0_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_0_bits_addr_bits <= _GEN_180;\n else\n ldq_0_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_0_bits_addr_bits <= _GEN_217;\n ldq_0_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_0_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_435)\n ldq_0_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_0_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h0 | (_GEN_435 ? io_core_dis_uops_0_bits_exception : ldq_0_bits_uop_exception);\n ldq_0_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_637 & _GEN_484 : ~_GEN_652 & _GEN_484);\n ldq_0_bits_executed <= ~_GEN_694 & _GEN_661 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_378)) & ((_GEN_368 ? (_GEN_618 ? (|lcam_ldq_idx_0) & _GEN_610 : ~(_GEN_372 & ~(|lcam_ldq_idx_0)) & _GEN_610) : _GEN_610) | ~_GEN_435 & ldq_0_bits_executed);\n ldq_0_bits_succeeded <= _GEN_661 & (_GEN_622 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h0 ? _ldq_bits_succeeded_T : ~_GEN_435 & ldq_0_bits_succeeded) : _GEN_396);\n ldq_0_bits_order_fail <= _GEN_661 & (_GEN_225 ? _GEN_451 : _GEN_230 ? _GEN_531 | _GEN_451 : _GEN_231 & searcher_is_older & _GEN_532 | _GEN_451);\n ldq_0_bits_observed <= _GEN_225 | ~_GEN_435 & ldq_0_bits_observed;\n ldq_0_bits_st_dep_mask <= _GEN_435 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_0_bits_st_dep_mask;\n ldq_0_bits_forward_std_val <= _GEN_661 & (~_GEN_387 & _GEN_621 | ~_GEN_435 & ldq_0_bits_forward_std_val);\n if (_GEN_622) begin\n end\n else\n ldq_0_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_1_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_638 & _GEN_438 : ~_GEN_654 & _GEN_438);\n if (_GEN_437) begin\n ldq_1_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_1_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_1_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_1_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_1_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_1_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_1_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_1_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_1_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_1_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_1_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_1_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_1_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_1_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_1_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_1_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_1_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_1_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_1_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_1_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_1_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_1_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_1_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_1_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_1_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_1_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_1_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_1_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_1_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_1_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_1_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_1_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_1_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_1_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_1_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_1_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_1_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_1_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_1_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_1_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_1_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_1_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_1_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_1_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_1_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_1_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_1_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_1_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_1_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_1_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_1_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_1_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_1_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_1_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_1_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_1_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_1_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_1_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_1_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_1_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_1_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_1_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_1_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_1_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_1_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_1_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_1_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_1_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_1_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_1_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_1_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_1_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_1_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_1_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_1_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_1_valid)\n ldq_1_bits_uop_br_mask <= ldq_1_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_437)\n ldq_1_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_485) begin\n if (_exe_tlb_uop_T_2)\n ldq_1_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_1_bits_uop_pdst <= _GEN_139;\n else\n ldq_1_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_1_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_1_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_1_bits_addr_bits <= _GEN_180;\n else\n ldq_1_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_1_bits_addr_bits <= _GEN_217;\n ldq_1_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_1_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_437)\n ldq_1_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_1_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h1 | (_GEN_437 ? io_core_dis_uops_0_bits_exception : ldq_1_bits_uop_exception);\n ldq_1_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_638 & _GEN_486 : ~_GEN_654 & _GEN_486);\n ldq_1_bits_executed <= ~_GEN_694 & _GEN_662 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_379)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_234 & _GEN_611 : ~(_GEN_372 & _GEN_234) & _GEN_611) : _GEN_611) | ~_GEN_437 & ldq_1_bits_executed);\n ldq_1_bits_succeeded <= _GEN_662 & (_GEN_624 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h1 ? _ldq_bits_succeeded_T : ~_GEN_437 & ldq_1_bits_succeeded) : _GEN_396);\n ldq_1_bits_order_fail <= _GEN_662 & (_GEN_242 ? _GEN_452 : _GEN_246 ? _GEN_533 | _GEN_452 : _GEN_247 & searcher_is_older_1 & _GEN_534 | _GEN_452);\n ldq_1_bits_observed <= _GEN_242 | ~_GEN_437 & ldq_1_bits_observed;\n ldq_1_bits_st_dep_mask <= _GEN_437 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_1_bits_st_dep_mask;\n ldq_1_bits_forward_std_val <= _GEN_662 & (~_GEN_387 & _GEN_623 | ~_GEN_437 & ldq_1_bits_forward_std_val);\n if (_GEN_624) begin\n end\n else\n ldq_1_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_2_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_639 & _GEN_440 : ~_GEN_655 & _GEN_440);\n if (_GEN_439) begin\n ldq_2_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_2_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_2_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_2_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_2_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_2_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_2_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_2_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_2_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_2_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_2_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_2_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_2_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_2_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_2_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_2_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_2_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_2_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_2_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_2_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_2_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_2_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_2_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_2_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_2_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_2_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_2_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_2_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_2_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_2_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_2_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_2_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_2_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_2_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_2_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_2_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_2_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_2_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_2_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_2_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_2_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_2_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_2_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_2_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_2_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_2_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_2_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_2_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_2_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_2_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_2_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_2_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_2_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_2_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_2_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_2_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_2_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_2_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_2_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_2_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_2_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_2_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_2_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_2_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_2_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_2_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_2_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_2_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_2_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_2_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_2_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_2_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_2_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_2_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_2_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_2_valid)\n ldq_2_bits_uop_br_mask <= ldq_2_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_439)\n ldq_2_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_487) begin\n if (_exe_tlb_uop_T_2)\n ldq_2_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_2_bits_uop_pdst <= _GEN_139;\n else\n ldq_2_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_2_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_2_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_2_bits_addr_bits <= _GEN_180;\n else\n ldq_2_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_2_bits_addr_bits <= _GEN_217;\n ldq_2_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_2_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_439)\n ldq_2_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_2_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h2 | (_GEN_439 ? io_core_dis_uops_0_bits_exception : ldq_2_bits_uop_exception);\n ldq_2_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_639 & _GEN_488 : ~_GEN_655 & _GEN_488);\n ldq_2_bits_executed <= ~_GEN_694 & _GEN_663 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_380)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_235 & _GEN_612 : ~(_GEN_372 & _GEN_235) & _GEN_612) : _GEN_612) | ~_GEN_439 & ldq_2_bits_executed);\n ldq_2_bits_succeeded <= _GEN_663 & (_GEN_626 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h2 ? _ldq_bits_succeeded_T : ~_GEN_439 & ldq_2_bits_succeeded) : _GEN_396);\n ldq_2_bits_order_fail <= _GEN_663 & (_GEN_253 ? _GEN_453 : _GEN_257 ? _GEN_535 | _GEN_453 : _GEN_258 & searcher_is_older_2 & _GEN_536 | _GEN_453);\n ldq_2_bits_observed <= _GEN_253 | ~_GEN_439 & ldq_2_bits_observed;\n ldq_2_bits_st_dep_mask <= _GEN_439 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_2_bits_st_dep_mask;\n ldq_2_bits_forward_std_val <= _GEN_663 & (~_GEN_387 & _GEN_625 | ~_GEN_439 & ldq_2_bits_forward_std_val);\n if (_GEN_626) begin\n end\n else\n ldq_2_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_3_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_640 & _GEN_442 : ~_GEN_656 & _GEN_442);\n if (_GEN_441) begin\n ldq_3_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_3_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_3_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_3_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_3_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_3_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_3_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_3_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_3_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_3_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_3_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_3_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_3_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_3_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_3_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_3_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_3_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_3_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_3_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_3_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_3_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_3_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_3_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_3_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_3_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_3_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_3_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_3_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_3_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_3_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_3_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_3_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_3_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_3_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_3_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_3_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_3_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_3_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_3_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_3_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_3_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_3_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_3_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_3_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_3_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_3_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_3_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_3_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_3_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_3_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_3_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_3_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_3_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_3_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_3_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_3_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_3_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_3_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_3_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_3_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_3_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_3_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_3_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_3_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_3_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_3_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_3_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_3_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_3_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_3_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_3_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_3_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_3_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_3_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_3_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_3_valid)\n ldq_3_bits_uop_br_mask <= ldq_3_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_441)\n ldq_3_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_489) begin\n if (_exe_tlb_uop_T_2)\n ldq_3_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_3_bits_uop_pdst <= _GEN_139;\n else\n ldq_3_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_3_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_3_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_3_bits_addr_bits <= _GEN_180;\n else\n ldq_3_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_3_bits_addr_bits <= _GEN_217;\n ldq_3_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_3_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_441)\n ldq_3_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_3_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h3 | (_GEN_441 ? io_core_dis_uops_0_bits_exception : ldq_3_bits_uop_exception);\n ldq_3_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_640 & _GEN_490 : ~_GEN_656 & _GEN_490);\n ldq_3_bits_executed <= ~_GEN_694 & _GEN_664 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_381)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_236 & _GEN_613 : ~(_GEN_372 & _GEN_236) & _GEN_613) : _GEN_613) | ~_GEN_441 & ldq_3_bits_executed);\n ldq_3_bits_succeeded <= _GEN_664 & (_GEN_628 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h3 ? _ldq_bits_succeeded_T : ~_GEN_441 & ldq_3_bits_succeeded) : _GEN_396);\n ldq_3_bits_order_fail <= _GEN_664 & (_GEN_264 ? _GEN_454 : _GEN_268 ? _GEN_537 | _GEN_454 : _GEN_269 & searcher_is_older_3 & _GEN_538 | _GEN_454);\n ldq_3_bits_observed <= _GEN_264 | ~_GEN_441 & ldq_3_bits_observed;\n ldq_3_bits_st_dep_mask <= _GEN_441 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_3_bits_st_dep_mask;\n ldq_3_bits_forward_std_val <= _GEN_664 & (~_GEN_387 & _GEN_627 | ~_GEN_441 & ldq_3_bits_forward_std_val);\n if (_GEN_628) begin\n end\n else\n ldq_3_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_4_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_641 & _GEN_444 : ~_GEN_657 & _GEN_444);\n if (_GEN_443) begin\n ldq_4_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_4_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_4_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_4_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_4_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_4_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_4_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_4_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_4_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_4_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_4_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_4_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_4_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_4_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_4_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_4_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_4_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_4_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_4_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_4_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_4_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_4_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_4_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_4_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_4_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_4_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_4_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_4_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_4_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_4_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_4_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_4_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_4_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_4_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_4_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_4_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_4_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_4_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_4_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_4_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_4_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_4_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_4_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_4_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_4_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_4_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_4_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_4_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_4_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_4_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_4_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_4_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_4_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_4_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_4_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_4_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_4_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_4_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_4_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_4_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_4_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_4_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_4_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_4_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_4_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_4_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_4_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_4_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_4_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_4_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_4_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_4_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_4_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_4_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_4_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_4_valid)\n ldq_4_bits_uop_br_mask <= ldq_4_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_443)\n ldq_4_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_491) begin\n if (_exe_tlb_uop_T_2)\n ldq_4_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_4_bits_uop_pdst <= _GEN_139;\n else\n ldq_4_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_4_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_4_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_4_bits_addr_bits <= _GEN_180;\n else\n ldq_4_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_4_bits_addr_bits <= _GEN_217;\n ldq_4_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_4_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_443)\n ldq_4_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_4_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h4 | (_GEN_443 ? io_core_dis_uops_0_bits_exception : ldq_4_bits_uop_exception);\n ldq_4_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_641 & _GEN_492 : ~_GEN_657 & _GEN_492);\n ldq_4_bits_executed <= ~_GEN_694 & _GEN_665 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_382)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_237 & _GEN_614 : ~(_GEN_372 & _GEN_237) & _GEN_614) : _GEN_614) | ~_GEN_443 & ldq_4_bits_executed);\n ldq_4_bits_succeeded <= _GEN_665 & (_GEN_630 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h4 ? _ldq_bits_succeeded_T : ~_GEN_443 & ldq_4_bits_succeeded) : _GEN_396);\n ldq_4_bits_order_fail <= _GEN_665 & (_GEN_275 ? _GEN_455 : _GEN_279 ? _GEN_539 | _GEN_455 : _GEN_280 & searcher_is_older_4 & _GEN_540 | _GEN_455);\n ldq_4_bits_observed <= _GEN_275 | ~_GEN_443 & ldq_4_bits_observed;\n ldq_4_bits_st_dep_mask <= _GEN_443 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_4_bits_st_dep_mask;\n ldq_4_bits_forward_std_val <= _GEN_665 & (~_GEN_387 & _GEN_629 | ~_GEN_443 & ldq_4_bits_forward_std_val);\n if (_GEN_630) begin\n end\n else\n ldq_4_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_5_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_642 & _GEN_446 : ~_GEN_658 & _GEN_446);\n if (_GEN_445) begin\n ldq_5_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_5_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_5_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_5_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_5_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_5_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_5_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_5_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_5_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_5_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_5_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_5_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_5_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_5_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_5_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_5_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_5_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_5_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_5_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_5_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_5_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_5_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_5_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_5_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_5_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_5_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_5_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_5_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_5_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_5_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_5_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_5_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_5_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_5_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_5_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_5_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_5_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_5_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_5_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_5_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_5_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_5_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_5_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_5_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_5_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_5_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_5_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_5_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_5_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_5_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_5_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_5_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_5_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_5_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_5_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_5_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_5_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_5_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_5_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_5_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_5_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_5_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_5_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_5_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_5_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_5_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_5_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_5_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_5_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_5_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_5_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_5_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_5_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_5_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_5_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_5_valid)\n ldq_5_bits_uop_br_mask <= ldq_5_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_445)\n ldq_5_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_493) begin\n if (_exe_tlb_uop_T_2)\n ldq_5_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_5_bits_uop_pdst <= _GEN_139;\n else\n ldq_5_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_5_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_5_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_5_bits_addr_bits <= _GEN_180;\n else\n ldq_5_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_5_bits_addr_bits <= _GEN_217;\n ldq_5_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_5_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_445)\n ldq_5_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_5_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h5 | (_GEN_445 ? io_core_dis_uops_0_bits_exception : ldq_5_bits_uop_exception);\n ldq_5_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_642 & _GEN_494 : ~_GEN_658 & _GEN_494);\n ldq_5_bits_executed <= ~_GEN_694 & _GEN_666 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_383)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_238 & _GEN_615 : ~(_GEN_372 & _GEN_238) & _GEN_615) : _GEN_615) | ~_GEN_445 & ldq_5_bits_executed);\n ldq_5_bits_succeeded <= _GEN_666 & (_GEN_632 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h5 ? _ldq_bits_succeeded_T : ~_GEN_445 & ldq_5_bits_succeeded) : _GEN_396);\n ldq_5_bits_order_fail <= _GEN_666 & (_GEN_286 ? _GEN_456 : _GEN_290 ? _GEN_541 | _GEN_456 : _GEN_291 & searcher_is_older_5 & _GEN_542 | _GEN_456);\n ldq_5_bits_observed <= _GEN_286 | ~_GEN_445 & ldq_5_bits_observed;\n ldq_5_bits_st_dep_mask <= _GEN_445 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_5_bits_st_dep_mask;\n ldq_5_bits_forward_std_val <= _GEN_666 & (~_GEN_387 & _GEN_631 | ~_GEN_445 & ldq_5_bits_forward_std_val);\n if (_GEN_632) begin\n end\n else\n ldq_5_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_6_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_643 & _GEN_448 : ~_GEN_659 & _GEN_448);\n if (_GEN_447) begin\n ldq_6_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_6_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_6_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_6_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_6_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_6_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_6_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_6_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_6_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_6_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_6_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_6_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_6_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_6_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_6_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_6_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_6_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_6_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_6_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_6_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_6_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_6_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_6_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_6_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_6_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_6_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_6_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_6_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_6_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_6_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_6_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_6_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_6_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_6_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_6_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_6_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_6_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_6_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_6_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_6_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_6_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_6_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_6_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_6_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_6_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_6_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_6_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_6_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_6_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_6_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_6_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_6_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_6_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_6_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_6_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_6_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_6_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_6_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_6_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_6_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_6_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_6_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_6_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_6_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_6_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_6_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_6_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_6_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_6_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_6_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_6_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_6_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_6_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_6_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_6_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_6_valid)\n ldq_6_bits_uop_br_mask <= ldq_6_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_447)\n ldq_6_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_495) begin\n if (_exe_tlb_uop_T_2)\n ldq_6_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_6_bits_uop_pdst <= _GEN_139;\n else\n ldq_6_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_6_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_6_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_6_bits_addr_bits <= _GEN_180;\n else\n ldq_6_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_6_bits_addr_bits <= _GEN_217;\n ldq_6_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_6_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_447)\n ldq_6_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_6_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_ldq_idx == 3'h6 | (_GEN_447 ? io_core_dis_uops_0_bits_exception : ldq_6_bits_uop_exception);\n ldq_6_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_643 & _GEN_496 : ~_GEN_659 & _GEN_496);\n ldq_6_bits_executed <= ~_GEN_694 & _GEN_667 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & _GEN_384)) & ((_GEN_368 ? (_GEN_618 ? ~_GEN_239 & _GEN_616 : ~(_GEN_372 & _GEN_239) & _GEN_616) : _GEN_616) | ~_GEN_447 & ldq_6_bits_executed);\n ldq_6_bits_succeeded <= _GEN_667 & (_GEN_634 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_ldq_idx == 3'h6 ? _ldq_bits_succeeded_T : ~_GEN_447 & ldq_6_bits_succeeded) : _GEN_396);\n ldq_6_bits_order_fail <= _GEN_667 & (_GEN_297 ? _GEN_457 : _GEN_301 ? _GEN_543 | _GEN_457 : _GEN_302 & searcher_is_older_6 & _GEN_544 | _GEN_457);\n ldq_6_bits_observed <= _GEN_297 | ~_GEN_447 & ldq_6_bits_observed;\n ldq_6_bits_st_dep_mask <= _GEN_447 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_6_bits_st_dep_mask;\n ldq_6_bits_forward_std_val <= _GEN_667 & (~_GEN_387 & _GEN_633 | ~_GEN_447 & ldq_6_bits_forward_std_val);\n if (_GEN_634) begin\n end\n else\n ldq_6_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n ldq_7_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_644 & _GEN_450 : ~_GEN_660 & _GEN_450);\n if (_GEN_449) begin\n ldq_7_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n ldq_7_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n ldq_7_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n ldq_7_bits_uop_is_rvc <= io_core_dis_uops_0_bits_is_rvc;\n ldq_7_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n ldq_7_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n ldq_7_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n ldq_7_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n ldq_7_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n ldq_7_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n ldq_7_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n ldq_7_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n ldq_7_bits_uop_ctrl_fcn_dw <= io_core_dis_uops_0_bits_ctrl_fcn_dw;\n ldq_7_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n ldq_7_bits_uop_ctrl_is_load <= io_core_dis_uops_0_bits_ctrl_is_load;\n ldq_7_bits_uop_ctrl_is_sta <= io_core_dis_uops_0_bits_ctrl_is_sta;\n ldq_7_bits_uop_ctrl_is_std <= io_core_dis_uops_0_bits_ctrl_is_std;\n ldq_7_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n ldq_7_bits_uop_iw_p1_poisoned <= io_core_dis_uops_0_bits_iw_p1_poisoned;\n ldq_7_bits_uop_iw_p2_poisoned <= io_core_dis_uops_0_bits_iw_p2_poisoned;\n ldq_7_bits_uop_is_br <= io_core_dis_uops_0_bits_is_br;\n ldq_7_bits_uop_is_jalr <= io_core_dis_uops_0_bits_is_jalr;\n ldq_7_bits_uop_is_jal <= io_core_dis_uops_0_bits_is_jal;\n ldq_7_bits_uop_is_sfb <= io_core_dis_uops_0_bits_is_sfb;\n ldq_7_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n ldq_7_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n ldq_7_bits_uop_edge_inst <= io_core_dis_uops_0_bits_edge_inst;\n ldq_7_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n ldq_7_bits_uop_taken <= io_core_dis_uops_0_bits_taken;\n ldq_7_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n ldq_7_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n ldq_7_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n ldq_7_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n ldq_7_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n ldq_7_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n ldq_7_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n ldq_7_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n ldq_7_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n ldq_7_bits_uop_prs1_busy <= io_core_dis_uops_0_bits_prs1_busy;\n ldq_7_bits_uop_prs2_busy <= io_core_dis_uops_0_bits_prs2_busy;\n ldq_7_bits_uop_prs3_busy <= io_core_dis_uops_0_bits_prs3_busy;\n ldq_7_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n ldq_7_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n ldq_7_bits_uop_bypassable <= io_core_dis_uops_0_bits_bypassable;\n ldq_7_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n ldq_7_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n ldq_7_bits_uop_mem_signed <= io_core_dis_uops_0_bits_mem_signed;\n ldq_7_bits_uop_is_fence <= io_core_dis_uops_0_bits_is_fence;\n ldq_7_bits_uop_is_fencei <= io_core_dis_uops_0_bits_is_fencei;\n ldq_7_bits_uop_is_amo <= io_core_dis_uops_0_bits_is_amo;\n ldq_7_bits_uop_uses_ldq <= io_core_dis_uops_0_bits_uses_ldq;\n ldq_7_bits_uop_uses_stq <= io_core_dis_uops_0_bits_uses_stq;\n ldq_7_bits_uop_is_sys_pc2epc <= io_core_dis_uops_0_bits_is_sys_pc2epc;\n ldq_7_bits_uop_is_unique <= io_core_dis_uops_0_bits_is_unique;\n ldq_7_bits_uop_flush_on_commit <= io_core_dis_uops_0_bits_flush_on_commit;\n ldq_7_bits_uop_ldst_is_rs1 <= io_core_dis_uops_0_bits_ldst_is_rs1;\n ldq_7_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n ldq_7_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n ldq_7_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n ldq_7_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n ldq_7_bits_uop_ldst_val <= io_core_dis_uops_0_bits_ldst_val;\n ldq_7_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n ldq_7_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n ldq_7_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n ldq_7_bits_uop_frs3_en <= io_core_dis_uops_0_bits_frs3_en;\n ldq_7_bits_uop_fp_val <= io_core_dis_uops_0_bits_fp_val;\n ldq_7_bits_uop_fp_single <= io_core_dis_uops_0_bits_fp_single;\n ldq_7_bits_uop_xcpt_pf_if <= io_core_dis_uops_0_bits_xcpt_pf_if;\n ldq_7_bits_uop_xcpt_ae_if <= io_core_dis_uops_0_bits_xcpt_ae_if;\n ldq_7_bits_uop_xcpt_ma_if <= io_core_dis_uops_0_bits_xcpt_ma_if;\n ldq_7_bits_uop_bp_debug_if <= io_core_dis_uops_0_bits_bp_debug_if;\n ldq_7_bits_uop_bp_xcpt_if <= io_core_dis_uops_0_bits_bp_xcpt_if;\n ldq_7_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n ldq_7_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n ldq_7_bits_youngest_stq_idx <= stq_tail;\n end\n if (ldq_7_valid)\n ldq_7_bits_uop_br_mask <= ldq_7_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_449)\n ldq_7_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_497) begin\n if (_exe_tlb_uop_T_2)\n ldq_7_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n ldq_7_bits_uop_pdst <= _GEN_139;\n else\n ldq_7_bits_uop_pdst <= _exe_tlb_uop_T_4_pdst;\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n ldq_7_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n ldq_7_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n ldq_7_bits_addr_bits <= _GEN_180;\n else\n ldq_7_bits_addr_bits <= _exe_tlb_vaddr_T_3;\n end\n else\n ldq_7_bits_addr_bits <= _GEN_217;\n ldq_7_bits_addr_is_virtual <= exe_tlb_miss_0;\n ldq_7_bits_addr_is_uncacheable <= _ldq_bits_addr_is_uncacheable_T_1;\n end\n else if (_GEN_449)\n ldq_7_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n ldq_7_bits_uop_exception <= mem_xcpt_valids_0 & mem_xcpt_uops_0_uses_ldq & (&mem_xcpt_uops_0_ldq_idx) | (_GEN_449 ? io_core_dis_uops_0_bits_exception : ldq_7_bits_uop_exception);\n ldq_7_bits_addr_valid <= ~_GEN_694 & (_GEN_653 ? ~_GEN_644 & _GEN_498 : ~_GEN_660 & _GEN_498);\n ldq_7_bits_executed <= ~_GEN_694 & _GEN_668 & (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | ~(io_dmem_nack_0_bits_uop_uses_ldq & (&io_dmem_nack_0_bits_uop_ldq_idx))) & ((_GEN_368 ? (_GEN_618 ? ~(&lcam_ldq_idx_0) & _GEN_617 : ~(_GEN_372 & (&lcam_ldq_idx_0)) & _GEN_617) : _GEN_617) | ~_GEN_449 & ldq_7_bits_executed);\n ldq_7_bits_succeeded <= _GEN_668 & (_GEN_636 ? (io_dmem_resp_0_valid & io_dmem_resp_0_bits_uop_uses_ldq & (&io_dmem_resp_0_bits_uop_ldq_idx) ? _ldq_bits_succeeded_T : ~_GEN_449 & ldq_7_bits_succeeded) : _GEN_396);\n ldq_7_bits_order_fail <= _GEN_668 & (_GEN_308 ? _GEN_458 : _GEN_312 ? _GEN_546 | _GEN_458 : _GEN_313 & searcher_is_older_7 & _GEN_547 | _GEN_458);\n ldq_7_bits_observed <= _GEN_308 | ~_GEN_449 & ldq_7_bits_observed;\n ldq_7_bits_st_dep_mask <= _GEN_449 ? next_live_store_mask : (_GEN_434 | ~_ldq_7_bits_st_dep_mask_T) & ldq_7_bits_st_dep_mask;\n ldq_7_bits_forward_std_val <= _GEN_668 & (~_GEN_387 & _GEN_635 | ~_GEN_449 & ldq_7_bits_forward_std_val);\n if (_GEN_636) begin\n end\n else\n ldq_7_bits_forward_stq_idx <= wb_forward_stq_idx_0;\n stq_0_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_460 : ~_GEN_402 & _GEN_460);\n if (_GEN_695) begin\n stq_0_bits_uop_uopc <= 7'h0;\n stq_0_bits_uop_inst <= 32'h0;\n stq_0_bits_uop_debug_inst <= 32'h0;\n stq_0_bits_uop_debug_pc <= 40'h0;\n stq_0_bits_uop_iq_type <= 3'h0;\n stq_0_bits_uop_fu_code <= 10'h0;\n stq_0_bits_uop_ctrl_br_type <= 4'h0;\n stq_0_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_0_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_0_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_0_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_0_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_0_bits_uop_iw_state <= 2'h0;\n stq_0_bits_uop_br_mask <= 8'h0;\n stq_0_bits_uop_br_tag <= 3'h0;\n stq_0_bits_uop_ftq_idx <= 4'h0;\n stq_0_bits_uop_pc_lob <= 6'h0;\n stq_0_bits_uop_imm_packed <= 20'h0;\n stq_0_bits_uop_csr_addr <= 12'h0;\n stq_0_bits_uop_rob_idx <= 5'h0;\n stq_0_bits_uop_ldq_idx <= 3'h0;\n stq_0_bits_uop_stq_idx <= 3'h0;\n stq_0_bits_uop_rxq_idx <= 2'h0;\n stq_0_bits_uop_pdst <= 6'h0;\n stq_0_bits_uop_prs1 <= 6'h0;\n stq_0_bits_uop_prs2 <= 6'h0;\n stq_0_bits_uop_prs3 <= 6'h0;\n stq_0_bits_uop_stale_pdst <= 6'h0;\n stq_0_bits_uop_exc_cause <= 64'h0;\n stq_0_bits_uop_mem_cmd <= 5'h0;\n stq_0_bits_uop_mem_size <= 2'h0;\n stq_0_bits_uop_ldst <= 6'h0;\n stq_0_bits_uop_lrs1 <= 6'h0;\n stq_0_bits_uop_lrs2 <= 6'h0;\n stq_0_bits_uop_lrs3 <= 6'h0;\n stq_0_bits_uop_dst_rtype <= 2'h2;\n stq_0_bits_uop_lrs1_rtype <= 2'h0;\n stq_0_bits_uop_lrs2_rtype <= 2'h0;\n stq_0_bits_uop_debug_fsrc <= 2'h0;\n stq_0_bits_uop_debug_tsrc <= 2'h0;\n stq_1_bits_uop_uopc <= 7'h0;\n stq_1_bits_uop_inst <= 32'h0;\n stq_1_bits_uop_debug_inst <= 32'h0;\n stq_1_bits_uop_debug_pc <= 40'h0;\n stq_1_bits_uop_iq_type <= 3'h0;\n stq_1_bits_uop_fu_code <= 10'h0;\n stq_1_bits_uop_ctrl_br_type <= 4'h0;\n stq_1_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_1_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_1_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_1_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_1_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_1_bits_uop_iw_state <= 2'h0;\n stq_1_bits_uop_br_mask <= 8'h0;\n stq_1_bits_uop_br_tag <= 3'h0;\n stq_1_bits_uop_ftq_idx <= 4'h0;\n stq_1_bits_uop_pc_lob <= 6'h0;\n stq_1_bits_uop_imm_packed <= 20'h0;\n stq_1_bits_uop_csr_addr <= 12'h0;\n stq_1_bits_uop_rob_idx <= 5'h0;\n stq_1_bits_uop_ldq_idx <= 3'h0;\n stq_1_bits_uop_stq_idx <= 3'h0;\n stq_1_bits_uop_rxq_idx <= 2'h0;\n stq_1_bits_uop_pdst <= 6'h0;\n stq_1_bits_uop_prs1 <= 6'h0;\n stq_1_bits_uop_prs2 <= 6'h0;\n stq_1_bits_uop_prs3 <= 6'h0;\n stq_1_bits_uop_stale_pdst <= 6'h0;\n stq_1_bits_uop_exc_cause <= 64'h0;\n stq_1_bits_uop_mem_cmd <= 5'h0;\n stq_1_bits_uop_mem_size <= 2'h0;\n stq_1_bits_uop_ldst <= 6'h0;\n stq_1_bits_uop_lrs1 <= 6'h0;\n stq_1_bits_uop_lrs2 <= 6'h0;\n stq_1_bits_uop_lrs3 <= 6'h0;\n stq_1_bits_uop_dst_rtype <= 2'h2;\n stq_1_bits_uop_lrs1_rtype <= 2'h0;\n stq_1_bits_uop_lrs2_rtype <= 2'h0;\n stq_1_bits_uop_debug_fsrc <= 2'h0;\n stq_1_bits_uop_debug_tsrc <= 2'h0;\n stq_2_bits_uop_uopc <= 7'h0;\n stq_2_bits_uop_inst <= 32'h0;\n stq_2_bits_uop_debug_inst <= 32'h0;\n stq_2_bits_uop_debug_pc <= 40'h0;\n stq_2_bits_uop_iq_type <= 3'h0;\n stq_2_bits_uop_fu_code <= 10'h0;\n stq_2_bits_uop_ctrl_br_type <= 4'h0;\n stq_2_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_2_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_2_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_2_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_2_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_2_bits_uop_iw_state <= 2'h0;\n stq_2_bits_uop_br_mask <= 8'h0;\n stq_2_bits_uop_br_tag <= 3'h0;\n stq_2_bits_uop_ftq_idx <= 4'h0;\n stq_2_bits_uop_pc_lob <= 6'h0;\n stq_2_bits_uop_imm_packed <= 20'h0;\n stq_2_bits_uop_csr_addr <= 12'h0;\n stq_2_bits_uop_rob_idx <= 5'h0;\n stq_2_bits_uop_ldq_idx <= 3'h0;\n stq_2_bits_uop_stq_idx <= 3'h0;\n stq_2_bits_uop_rxq_idx <= 2'h0;\n stq_2_bits_uop_pdst <= 6'h0;\n stq_2_bits_uop_prs1 <= 6'h0;\n stq_2_bits_uop_prs2 <= 6'h0;\n stq_2_bits_uop_prs3 <= 6'h0;\n stq_2_bits_uop_stale_pdst <= 6'h0;\n stq_2_bits_uop_exc_cause <= 64'h0;\n stq_2_bits_uop_mem_cmd <= 5'h0;\n stq_2_bits_uop_mem_size <= 2'h0;\n stq_2_bits_uop_ldst <= 6'h0;\n stq_2_bits_uop_lrs1 <= 6'h0;\n stq_2_bits_uop_lrs2 <= 6'h0;\n stq_2_bits_uop_lrs3 <= 6'h0;\n stq_2_bits_uop_dst_rtype <= 2'h2;\n stq_2_bits_uop_lrs1_rtype <= 2'h0;\n stq_2_bits_uop_lrs2_rtype <= 2'h0;\n stq_2_bits_uop_debug_fsrc <= 2'h0;\n stq_2_bits_uop_debug_tsrc <= 2'h0;\n stq_3_bits_uop_uopc <= 7'h0;\n stq_3_bits_uop_inst <= 32'h0;\n stq_3_bits_uop_debug_inst <= 32'h0;\n stq_3_bits_uop_debug_pc <= 40'h0;\n stq_3_bits_uop_iq_type <= 3'h0;\n stq_3_bits_uop_fu_code <= 10'h0;\n stq_3_bits_uop_ctrl_br_type <= 4'h0;\n stq_3_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_3_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_3_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_3_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_3_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_3_bits_uop_iw_state <= 2'h0;\n stq_3_bits_uop_br_mask <= 8'h0;\n stq_3_bits_uop_br_tag <= 3'h0;\n stq_3_bits_uop_ftq_idx <= 4'h0;\n stq_3_bits_uop_pc_lob <= 6'h0;\n stq_3_bits_uop_imm_packed <= 20'h0;\n stq_3_bits_uop_csr_addr <= 12'h0;\n stq_3_bits_uop_rob_idx <= 5'h0;\n stq_3_bits_uop_ldq_idx <= 3'h0;\n stq_3_bits_uop_stq_idx <= 3'h0;\n stq_3_bits_uop_rxq_idx <= 2'h0;\n stq_3_bits_uop_pdst <= 6'h0;\n stq_3_bits_uop_prs1 <= 6'h0;\n stq_3_bits_uop_prs2 <= 6'h0;\n stq_3_bits_uop_prs3 <= 6'h0;\n stq_3_bits_uop_stale_pdst <= 6'h0;\n stq_3_bits_uop_exc_cause <= 64'h0;\n stq_3_bits_uop_mem_cmd <= 5'h0;\n stq_3_bits_uop_mem_size <= 2'h0;\n stq_3_bits_uop_ldst <= 6'h0;\n stq_3_bits_uop_lrs1 <= 6'h0;\n stq_3_bits_uop_lrs2 <= 6'h0;\n stq_3_bits_uop_lrs3 <= 6'h0;\n stq_3_bits_uop_dst_rtype <= 2'h2;\n stq_3_bits_uop_lrs1_rtype <= 2'h0;\n stq_3_bits_uop_lrs2_rtype <= 2'h0;\n stq_3_bits_uop_debug_fsrc <= 2'h0;\n stq_3_bits_uop_debug_tsrc <= 2'h0;\n stq_4_bits_uop_uopc <= 7'h0;\n stq_4_bits_uop_inst <= 32'h0;\n stq_4_bits_uop_debug_inst <= 32'h0;\n stq_4_bits_uop_debug_pc <= 40'h0;\n stq_4_bits_uop_iq_type <= 3'h0;\n stq_4_bits_uop_fu_code <= 10'h0;\n stq_4_bits_uop_ctrl_br_type <= 4'h0;\n stq_4_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_4_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_4_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_4_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_4_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_4_bits_uop_iw_state <= 2'h0;\n stq_4_bits_uop_br_mask <= 8'h0;\n stq_4_bits_uop_br_tag <= 3'h0;\n stq_4_bits_uop_ftq_idx <= 4'h0;\n stq_4_bits_uop_pc_lob <= 6'h0;\n stq_4_bits_uop_imm_packed <= 20'h0;\n stq_4_bits_uop_csr_addr <= 12'h0;\n stq_4_bits_uop_rob_idx <= 5'h0;\n stq_4_bits_uop_ldq_idx <= 3'h0;\n stq_4_bits_uop_stq_idx <= 3'h0;\n stq_4_bits_uop_rxq_idx <= 2'h0;\n stq_4_bits_uop_pdst <= 6'h0;\n stq_4_bits_uop_prs1 <= 6'h0;\n stq_4_bits_uop_prs2 <= 6'h0;\n stq_4_bits_uop_prs3 <= 6'h0;\n stq_4_bits_uop_stale_pdst <= 6'h0;\n stq_4_bits_uop_exc_cause <= 64'h0;\n stq_4_bits_uop_mem_cmd <= 5'h0;\n stq_4_bits_uop_mem_size <= 2'h0;\n stq_4_bits_uop_ldst <= 6'h0;\n stq_4_bits_uop_lrs1 <= 6'h0;\n stq_4_bits_uop_lrs2 <= 6'h0;\n stq_4_bits_uop_lrs3 <= 6'h0;\n stq_4_bits_uop_dst_rtype <= 2'h2;\n stq_4_bits_uop_lrs1_rtype <= 2'h0;\n stq_4_bits_uop_lrs2_rtype <= 2'h0;\n stq_4_bits_uop_debug_fsrc <= 2'h0;\n stq_4_bits_uop_debug_tsrc <= 2'h0;\n stq_5_bits_uop_uopc <= 7'h0;\n stq_5_bits_uop_inst <= 32'h0;\n stq_5_bits_uop_debug_inst <= 32'h0;\n stq_5_bits_uop_debug_pc <= 40'h0;\n stq_5_bits_uop_iq_type <= 3'h0;\n stq_5_bits_uop_fu_code <= 10'h0;\n stq_5_bits_uop_ctrl_br_type <= 4'h0;\n stq_5_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_5_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_5_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_5_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_5_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_5_bits_uop_iw_state <= 2'h0;\n stq_5_bits_uop_br_mask <= 8'h0;\n stq_5_bits_uop_br_tag <= 3'h0;\n stq_5_bits_uop_ftq_idx <= 4'h0;\n stq_5_bits_uop_pc_lob <= 6'h0;\n stq_5_bits_uop_imm_packed <= 20'h0;\n stq_5_bits_uop_csr_addr <= 12'h0;\n stq_5_bits_uop_rob_idx <= 5'h0;\n stq_5_bits_uop_ldq_idx <= 3'h0;\n stq_5_bits_uop_stq_idx <= 3'h0;\n stq_5_bits_uop_rxq_idx <= 2'h0;\n stq_5_bits_uop_pdst <= 6'h0;\n stq_5_bits_uop_prs1 <= 6'h0;\n stq_5_bits_uop_prs2 <= 6'h0;\n stq_5_bits_uop_prs3 <= 6'h0;\n stq_5_bits_uop_stale_pdst <= 6'h0;\n stq_5_bits_uop_exc_cause <= 64'h0;\n stq_5_bits_uop_mem_cmd <= 5'h0;\n stq_5_bits_uop_mem_size <= 2'h0;\n stq_5_bits_uop_ldst <= 6'h0;\n stq_5_bits_uop_lrs1 <= 6'h0;\n stq_5_bits_uop_lrs2 <= 6'h0;\n stq_5_bits_uop_lrs3 <= 6'h0;\n stq_5_bits_uop_dst_rtype <= 2'h2;\n stq_5_bits_uop_lrs1_rtype <= 2'h0;\n stq_5_bits_uop_lrs2_rtype <= 2'h0;\n stq_5_bits_uop_debug_fsrc <= 2'h0;\n stq_5_bits_uop_debug_tsrc <= 2'h0;\n stq_6_bits_uop_uopc <= 7'h0;\n stq_6_bits_uop_inst <= 32'h0;\n stq_6_bits_uop_debug_inst <= 32'h0;\n stq_6_bits_uop_debug_pc <= 40'h0;\n stq_6_bits_uop_iq_type <= 3'h0;\n stq_6_bits_uop_fu_code <= 10'h0;\n stq_6_bits_uop_ctrl_br_type <= 4'h0;\n stq_6_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_6_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_6_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_6_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_6_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_6_bits_uop_iw_state <= 2'h0;\n stq_6_bits_uop_br_mask <= 8'h0;\n stq_6_bits_uop_br_tag <= 3'h0;\n stq_6_bits_uop_ftq_idx <= 4'h0;\n stq_6_bits_uop_pc_lob <= 6'h0;\n stq_6_bits_uop_imm_packed <= 20'h0;\n stq_6_bits_uop_csr_addr <= 12'h0;\n stq_6_bits_uop_rob_idx <= 5'h0;\n stq_6_bits_uop_ldq_idx <= 3'h0;\n stq_6_bits_uop_stq_idx <= 3'h0;\n stq_6_bits_uop_rxq_idx <= 2'h0;\n stq_6_bits_uop_pdst <= 6'h0;\n stq_6_bits_uop_prs1 <= 6'h0;\n stq_6_bits_uop_prs2 <= 6'h0;\n stq_6_bits_uop_prs3 <= 6'h0;\n stq_6_bits_uop_stale_pdst <= 6'h0;\n stq_6_bits_uop_exc_cause <= 64'h0;\n stq_6_bits_uop_mem_cmd <= 5'h0;\n stq_6_bits_uop_mem_size <= 2'h0;\n stq_6_bits_uop_ldst <= 6'h0;\n stq_6_bits_uop_lrs1 <= 6'h0;\n stq_6_bits_uop_lrs2 <= 6'h0;\n stq_6_bits_uop_lrs3 <= 6'h0;\n stq_6_bits_uop_dst_rtype <= 2'h2;\n stq_6_bits_uop_lrs1_rtype <= 2'h0;\n stq_6_bits_uop_lrs2_rtype <= 2'h0;\n stq_6_bits_uop_debug_fsrc <= 2'h0;\n stq_6_bits_uop_debug_tsrc <= 2'h0;\n stq_7_bits_uop_uopc <= 7'h0;\n stq_7_bits_uop_inst <= 32'h0;\n stq_7_bits_uop_debug_inst <= 32'h0;\n stq_7_bits_uop_debug_pc <= 40'h0;\n stq_7_bits_uop_iq_type <= 3'h0;\n stq_7_bits_uop_fu_code <= 10'h0;\n stq_7_bits_uop_ctrl_br_type <= 4'h0;\n stq_7_bits_uop_ctrl_op1_sel <= 2'h0;\n stq_7_bits_uop_ctrl_op2_sel <= 3'h0;\n stq_7_bits_uop_ctrl_imm_sel <= 3'h0;\n stq_7_bits_uop_ctrl_op_fcn <= 5'h0;\n stq_7_bits_uop_ctrl_csr_cmd <= 3'h0;\n stq_7_bits_uop_iw_state <= 2'h0;\n stq_7_bits_uop_br_mask <= 8'h0;\n stq_7_bits_uop_br_tag <= 3'h0;\n stq_7_bits_uop_ftq_idx <= 4'h0;\n stq_7_bits_uop_pc_lob <= 6'h0;\n stq_7_bits_uop_imm_packed <= 20'h0;\n stq_7_bits_uop_csr_addr <= 12'h0;\n stq_7_bits_uop_rob_idx <= 5'h0;\n stq_7_bits_uop_ldq_idx <= 3'h0;\n stq_7_bits_uop_stq_idx <= 3'h0;\n stq_7_bits_uop_rxq_idx <= 2'h0;\n stq_7_bits_uop_pdst <= 6'h0;\n stq_7_bits_uop_prs1 <= 6'h0;\n stq_7_bits_uop_prs2 <= 6'h0;\n stq_7_bits_uop_prs3 <= 6'h0;\n stq_7_bits_uop_stale_pdst <= 6'h0;\n stq_7_bits_uop_exc_cause <= 64'h0;\n stq_7_bits_uop_mem_cmd <= 5'h0;\n stq_7_bits_uop_mem_size <= 2'h0;\n stq_7_bits_uop_ldst <= 6'h0;\n stq_7_bits_uop_lrs1 <= 6'h0;\n stq_7_bits_uop_lrs2 <= 6'h0;\n stq_7_bits_uop_lrs3 <= 6'h0;\n stq_7_bits_uop_dst_rtype <= 2'h2;\n stq_7_bits_uop_lrs1_rtype <= 2'h0;\n stq_7_bits_uop_lrs2_rtype <= 2'h0;\n stq_7_bits_uop_debug_fsrc <= 2'h0;\n stq_7_bits_uop_debug_tsrc <= 2'h0;\n stq_head <= 3'h0;\n stq_commit_head <= 3'h0;\n stq_execute_head <= 3'h0;\n end\n else begin\n if (_GEN_475) begin\n end\n else begin\n stq_0_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_0_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_0_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_0_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_0_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_0_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_0_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_0_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_0_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_0_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_0_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_0_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_0_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_0_valid)\n stq_0_bits_uop_br_mask <= stq_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_475) begin\n end\n else\n stq_0_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_475) begin\n end\n else begin\n stq_0_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_0_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_0_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_0_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_0_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_0_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_0_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_0_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_0_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_499) begin\n if (_exe_tlb_uop_T_2)\n stq_0_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_0_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_0_bits_uop_pdst <= _GEN_187;\n else\n stq_0_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_475) begin\n end\n else\n stq_0_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_475) begin\n end\n else begin\n stq_0_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_0_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_0_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_0_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_0_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_0_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_0_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_0_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_0_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_0_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_0_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_0_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_0_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_0_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_0_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_0_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_476) begin\n end\n else begin\n stq_1_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_1_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_1_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_1_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_1_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_1_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_1_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_1_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_1_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_1_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_1_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_1_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_1_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_1_valid)\n stq_1_bits_uop_br_mask <= stq_1_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_476) begin\n end\n else\n stq_1_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_476) begin\n end\n else begin\n stq_1_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_1_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_1_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_1_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_1_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_1_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_1_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_1_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_1_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_501) begin\n if (_exe_tlb_uop_T_2)\n stq_1_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_1_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_1_bits_uop_pdst <= _GEN_187;\n else\n stq_1_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_476) begin\n end\n else\n stq_1_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_476) begin\n end\n else begin\n stq_1_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_1_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_1_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_1_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_1_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_1_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_1_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_1_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_1_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_1_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_1_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_1_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_1_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_1_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_1_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_1_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_477) begin\n end\n else begin\n stq_2_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_2_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_2_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_2_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_2_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_2_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_2_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_2_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_2_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_2_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_2_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_2_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_2_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_2_valid)\n stq_2_bits_uop_br_mask <= stq_2_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_477) begin\n end\n else\n stq_2_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_477) begin\n end\n else begin\n stq_2_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_2_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_2_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_2_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_2_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_2_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_2_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_2_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_2_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_503) begin\n if (_exe_tlb_uop_T_2)\n stq_2_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_2_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_2_bits_uop_pdst <= _GEN_187;\n else\n stq_2_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_477) begin\n end\n else\n stq_2_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_477) begin\n end\n else begin\n stq_2_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_2_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_2_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_2_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_2_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_2_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_2_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_2_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_2_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_2_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_2_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_2_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_2_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_2_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_2_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_2_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_478) begin\n end\n else begin\n stq_3_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_3_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_3_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_3_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_3_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_3_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_3_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_3_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_3_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_3_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_3_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_3_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_3_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_3_valid)\n stq_3_bits_uop_br_mask <= stq_3_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_478) begin\n end\n else\n stq_3_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_478) begin\n end\n else begin\n stq_3_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_3_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_3_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_3_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_3_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_3_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_3_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_3_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_3_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_505) begin\n if (_exe_tlb_uop_T_2)\n stq_3_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_3_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_3_bits_uop_pdst <= _GEN_187;\n else\n stq_3_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_478) begin\n end\n else\n stq_3_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_478) begin\n end\n else begin\n stq_3_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_3_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_3_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_3_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_3_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_3_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_3_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_3_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_3_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_3_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_3_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_3_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_3_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_3_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_3_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_3_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_479) begin\n end\n else begin\n stq_4_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_4_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_4_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_4_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_4_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_4_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_4_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_4_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_4_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_4_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_4_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_4_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_4_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_4_valid)\n stq_4_bits_uop_br_mask <= stq_4_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_479) begin\n end\n else\n stq_4_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_479) begin\n end\n else begin\n stq_4_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_4_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_4_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_4_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_4_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_4_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_4_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_4_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_4_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_507) begin\n if (_exe_tlb_uop_T_2)\n stq_4_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_4_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_4_bits_uop_pdst <= _GEN_187;\n else\n stq_4_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_479) begin\n end\n else\n stq_4_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_479) begin\n end\n else begin\n stq_4_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_4_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_4_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_4_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_4_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_4_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_4_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_4_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_4_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_4_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_4_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_4_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_4_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_4_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_4_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_4_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_480) begin\n end\n else begin\n stq_5_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_5_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_5_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_5_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_5_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_5_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_5_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_5_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_5_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_5_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_5_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_5_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_5_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_5_valid)\n stq_5_bits_uop_br_mask <= stq_5_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_480) begin\n end\n else\n stq_5_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_480) begin\n end\n else begin\n stq_5_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_5_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_5_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_5_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_5_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_5_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_5_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_5_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_5_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_509) begin\n if (_exe_tlb_uop_T_2)\n stq_5_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_5_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_5_bits_uop_pdst <= _GEN_187;\n else\n stq_5_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_480) begin\n end\n else\n stq_5_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_480) begin\n end\n else begin\n stq_5_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_5_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_5_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_5_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_5_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_5_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_5_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_5_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_5_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_5_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_5_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_5_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_5_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_5_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_5_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_5_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_481) begin\n end\n else begin\n stq_6_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_6_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_6_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_6_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_6_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_6_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_6_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_6_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_6_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_6_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_6_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_6_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_6_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_6_valid)\n stq_6_bits_uop_br_mask <= stq_6_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_481) begin\n end\n else\n stq_6_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_481) begin\n end\n else begin\n stq_6_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_6_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_6_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_6_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_6_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_6_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_6_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_6_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_6_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_511) begin\n if (_exe_tlb_uop_T_2)\n stq_6_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_6_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_6_bits_uop_pdst <= _GEN_187;\n else\n stq_6_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_481) begin\n end\n else\n stq_6_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_481) begin\n end\n else begin\n stq_6_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_6_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_6_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_6_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_6_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_6_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_6_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_6_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_6_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_6_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_6_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_6_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_6_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_6_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_6_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_6_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (_GEN_482) begin\n end\n else begin\n stq_7_bits_uop_uopc <= io_core_dis_uops_0_bits_uopc;\n stq_7_bits_uop_inst <= io_core_dis_uops_0_bits_inst;\n stq_7_bits_uop_debug_inst <= io_core_dis_uops_0_bits_debug_inst;\n stq_7_bits_uop_debug_pc <= io_core_dis_uops_0_bits_debug_pc;\n stq_7_bits_uop_iq_type <= io_core_dis_uops_0_bits_iq_type;\n stq_7_bits_uop_fu_code <= io_core_dis_uops_0_bits_fu_code;\n stq_7_bits_uop_ctrl_br_type <= io_core_dis_uops_0_bits_ctrl_br_type;\n stq_7_bits_uop_ctrl_op1_sel <= io_core_dis_uops_0_bits_ctrl_op1_sel;\n stq_7_bits_uop_ctrl_op2_sel <= io_core_dis_uops_0_bits_ctrl_op2_sel;\n stq_7_bits_uop_ctrl_imm_sel <= io_core_dis_uops_0_bits_ctrl_imm_sel;\n stq_7_bits_uop_ctrl_op_fcn <= io_core_dis_uops_0_bits_ctrl_op_fcn;\n stq_7_bits_uop_ctrl_csr_cmd <= io_core_dis_uops_0_bits_ctrl_csr_cmd;\n stq_7_bits_uop_iw_state <= io_core_dis_uops_0_bits_iw_state;\n end\n if (stq_7_valid)\n stq_7_bits_uop_br_mask <= stq_7_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n else if (_GEN_482) begin\n end\n else\n stq_7_bits_uop_br_mask <= io_core_dis_uops_0_bits_br_mask;\n if (_GEN_482) begin\n end\n else begin\n stq_7_bits_uop_br_tag <= io_core_dis_uops_0_bits_br_tag;\n stq_7_bits_uop_ftq_idx <= io_core_dis_uops_0_bits_ftq_idx;\n stq_7_bits_uop_pc_lob <= io_core_dis_uops_0_bits_pc_lob;\n stq_7_bits_uop_imm_packed <= io_core_dis_uops_0_bits_imm_packed;\n stq_7_bits_uop_csr_addr <= io_core_dis_uops_0_bits_csr_addr;\n stq_7_bits_uop_rob_idx <= io_core_dis_uops_0_bits_rob_idx;\n stq_7_bits_uop_ldq_idx <= io_core_dis_uops_0_bits_ldq_idx;\n stq_7_bits_uop_stq_idx <= io_core_dis_uops_0_bits_stq_idx;\n stq_7_bits_uop_rxq_idx <= io_core_dis_uops_0_bits_rxq_idx;\n end\n if (_GEN_513) begin\n if (_exe_tlb_uop_T_2)\n stq_7_bits_uop_pdst <= io_core_exe_0_req_bits_uop_pdst;\n else if (will_fire_load_retry_0_will_fire)\n stq_7_bits_uop_pdst <= _GEN_139;\n else if (will_fire_sta_retry_0_will_fire)\n stq_7_bits_uop_pdst <= _GEN_187;\n else\n stq_7_bits_uop_pdst <= 6'h0;\n end\n else if (_GEN_482) begin\n end\n else\n stq_7_bits_uop_pdst <= io_core_dis_uops_0_bits_pdst;\n if (_GEN_482) begin\n end\n else begin\n stq_7_bits_uop_prs1 <= io_core_dis_uops_0_bits_prs1;\n stq_7_bits_uop_prs2 <= io_core_dis_uops_0_bits_prs2;\n stq_7_bits_uop_prs3 <= io_core_dis_uops_0_bits_prs3;\n stq_7_bits_uop_stale_pdst <= io_core_dis_uops_0_bits_stale_pdst;\n stq_7_bits_uop_exc_cause <= io_core_dis_uops_0_bits_exc_cause;\n stq_7_bits_uop_mem_cmd <= io_core_dis_uops_0_bits_mem_cmd;\n stq_7_bits_uop_mem_size <= io_core_dis_uops_0_bits_mem_size;\n stq_7_bits_uop_ldst <= io_core_dis_uops_0_bits_ldst;\n stq_7_bits_uop_lrs1 <= io_core_dis_uops_0_bits_lrs1;\n stq_7_bits_uop_lrs2 <= io_core_dis_uops_0_bits_lrs2;\n stq_7_bits_uop_lrs3 <= io_core_dis_uops_0_bits_lrs3;\n stq_7_bits_uop_dst_rtype <= io_core_dis_uops_0_bits_dst_rtype;\n stq_7_bits_uop_lrs1_rtype <= io_core_dis_uops_0_bits_lrs1_rtype;\n stq_7_bits_uop_lrs2_rtype <= io_core_dis_uops_0_bits_lrs2_rtype;\n stq_7_bits_uop_debug_fsrc <= io_core_dis_uops_0_bits_debug_fsrc;\n stq_7_bits_uop_debug_tsrc <= io_core_dis_uops_0_bits_debug_tsrc;\n end\n if (clear_store)\n stq_head <= stq_head + 3'h1;\n if (commit_store)\n stq_commit_head <= stq_commit_head + 3'h1;\n if (clear_store & _GEN_425)\n stq_execute_head <= stq_execute_head + 3'h1;\n else if (~io_dmem_nack_0_valid | io_dmem_nack_0_bits_is_hella | io_dmem_nack_0_bits_uop_uses_ldq | io_dmem_nack_0_bits_uop_stq_idx < stq_head ^ stq_execute_head < stq_head ^ io_dmem_nack_0_bits_uop_stq_idx >= stq_execute_head) begin\n if (_GEN_219 | ~(will_fire_store_commit_0_will_fire & dmem_req_fire_0)) begin\n end\n else\n stq_execute_head <= stq_execute_head + 3'h1;\n end\n else\n stq_execute_head <= io_dmem_nack_0_bits_uop_stq_idx;\n end\n stq_0_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_0_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_0_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_0_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_0_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_0_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_0_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_0_bits_uop_is_br <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_0_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_0_bits_uop_is_jal <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_0_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_0_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_0_bits_uop_taken <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_475)\n stq_0_bits_uop_ppred <= 4'h0;\n stq_0_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_0_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_0_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_0_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_475 & stq_0_bits_uop_ppred_busy;\n stq_0_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h0 | (_GEN_475 ? stq_0_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_0_bits_uop_bypassable <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_0_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_0_bits_uop_is_fence <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_0_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_0_bits_uop_is_amo <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_0_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_0_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_0_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_0_bits_uop_is_unique <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_0_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_0_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_0_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_0_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_0_bits_uop_fp_val <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_0_bits_uop_fp_single <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_0_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_0_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_0_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_0_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_0_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_475 ? stq_0_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_0_bits_addr_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_500 : ~_GEN_402 & _GEN_500);\n if (_GEN_499) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_0_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_0_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_0_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_0_bits_addr_bits <= _GEN_188;\n else\n stq_0_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_0_bits_addr_bits <= _GEN_217;\n stq_0_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_0_bits_data_valid <= ~_GEN_697 & (clear_store ? ~_GEN_670 & _GEN_516 : ~_GEN_402 & _GEN_516);\n if (_GEN_515)\n stq_0_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_0_bits_committed <= ~_GEN_684 & (commit_store & _GEN_645 | _GEN_475 & stq_0_bits_committed);\n stq_0_bits_succeeded <= ~_GEN_684 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h0 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h0)) & _GEN_475 & stq_0_bits_succeeded);\n stq_1_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_462 : ~_GEN_404 & _GEN_462);\n stq_1_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_1_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_1_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_1_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_1_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_1_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_1_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_1_bits_uop_is_br <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_1_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_1_bits_uop_is_jal <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_1_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_1_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_1_bits_uop_taken <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_476)\n stq_1_bits_uop_ppred <= 4'h0;\n stq_1_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_1_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_1_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_1_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_476 & stq_1_bits_uop_ppred_busy;\n stq_1_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h1 | (_GEN_476 ? stq_1_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_1_bits_uop_bypassable <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_1_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_1_bits_uop_is_fence <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_1_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_1_bits_uop_is_amo <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_1_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_1_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_1_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_1_bits_uop_is_unique <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_1_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_1_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_1_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_1_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_1_bits_uop_fp_val <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_1_bits_uop_fp_single <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_1_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_1_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_1_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_1_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_1_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_476 ? stq_1_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_1_bits_addr_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_502 : ~_GEN_404 & _GEN_502);\n if (_GEN_501) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_1_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_1_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_1_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_1_bits_addr_bits <= _GEN_188;\n else\n stq_1_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_1_bits_addr_bits <= _GEN_217;\n stq_1_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_1_bits_data_valid <= ~_GEN_699 & (clear_store ? ~_GEN_672 & _GEN_518 : ~_GEN_404 & _GEN_518);\n if (_GEN_517)\n stq_1_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_1_bits_committed <= ~_GEN_685 & (commit_store & _GEN_646 | _GEN_476 & stq_1_bits_committed);\n stq_1_bits_succeeded <= ~_GEN_685 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h1 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h1)) & _GEN_476 & stq_1_bits_succeeded);\n stq_2_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_464 : ~_GEN_406 & _GEN_464);\n stq_2_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_2_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_2_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_2_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_2_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_2_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_2_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_2_bits_uop_is_br <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_2_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_2_bits_uop_is_jal <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_2_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_2_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_2_bits_uop_taken <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_477)\n stq_2_bits_uop_ppred <= 4'h0;\n stq_2_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_2_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_2_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_2_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_477 & stq_2_bits_uop_ppred_busy;\n stq_2_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h2 | (_GEN_477 ? stq_2_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_2_bits_uop_bypassable <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_2_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_2_bits_uop_is_fence <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_2_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_2_bits_uop_is_amo <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_2_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_2_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_2_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_2_bits_uop_is_unique <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_2_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_2_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_2_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_2_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_2_bits_uop_fp_val <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_2_bits_uop_fp_single <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_2_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_2_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_2_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_2_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_2_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_477 ? stq_2_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_2_bits_addr_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_504 : ~_GEN_406 & _GEN_504);\n if (_GEN_503) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_2_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_2_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_2_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_2_bits_addr_bits <= _GEN_188;\n else\n stq_2_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_2_bits_addr_bits <= _GEN_217;\n stq_2_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_2_bits_data_valid <= ~_GEN_701 & (clear_store ? ~_GEN_674 & _GEN_520 : ~_GEN_406 & _GEN_520);\n if (_GEN_519)\n stq_2_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_2_bits_committed <= ~_GEN_686 & (commit_store & _GEN_647 | _GEN_477 & stq_2_bits_committed);\n stq_2_bits_succeeded <= ~_GEN_686 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h2 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h2)) & _GEN_477 & stq_2_bits_succeeded);\n stq_3_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_466 : ~_GEN_408 & _GEN_466);\n stq_3_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_3_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_3_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_3_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_3_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_3_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_3_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_3_bits_uop_is_br <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_3_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_3_bits_uop_is_jal <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_3_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_3_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_3_bits_uop_taken <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_478)\n stq_3_bits_uop_ppred <= 4'h0;\n stq_3_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_3_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_3_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_3_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_478 & stq_3_bits_uop_ppred_busy;\n stq_3_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h3 | (_GEN_478 ? stq_3_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_3_bits_uop_bypassable <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_3_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_3_bits_uop_is_fence <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_3_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_3_bits_uop_is_amo <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_3_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_3_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_3_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_3_bits_uop_is_unique <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_3_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_3_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_3_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_3_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_3_bits_uop_fp_val <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_3_bits_uop_fp_single <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_3_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_3_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_3_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_3_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_3_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_478 ? stq_3_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_3_bits_addr_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_506 : ~_GEN_408 & _GEN_506);\n if (_GEN_505) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_3_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_3_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_3_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_3_bits_addr_bits <= _GEN_188;\n else\n stq_3_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_3_bits_addr_bits <= _GEN_217;\n stq_3_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_3_bits_data_valid <= ~_GEN_703 & (clear_store ? ~_GEN_676 & _GEN_522 : ~_GEN_408 & _GEN_522);\n if (_GEN_521)\n stq_3_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_3_bits_committed <= ~_GEN_687 & (commit_store & _GEN_648 | _GEN_478 & stq_3_bits_committed);\n stq_3_bits_succeeded <= ~_GEN_687 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h3 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h3)) & _GEN_478 & stq_3_bits_succeeded);\n stq_4_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_468 : ~_GEN_410 & _GEN_468);\n stq_4_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_4_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_4_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_4_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_4_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_4_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_4_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_4_bits_uop_is_br <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_4_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_4_bits_uop_is_jal <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_4_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_4_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_4_bits_uop_taken <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_479)\n stq_4_bits_uop_ppred <= 4'h0;\n stq_4_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_4_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_4_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_4_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_479 & stq_4_bits_uop_ppred_busy;\n stq_4_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h4 | (_GEN_479 ? stq_4_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_4_bits_uop_bypassable <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_4_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_4_bits_uop_is_fence <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_4_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_4_bits_uop_is_amo <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_4_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_4_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_4_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_4_bits_uop_is_unique <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_4_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_4_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_4_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_4_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_4_bits_uop_fp_val <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_4_bits_uop_fp_single <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_4_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_4_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_4_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_4_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_4_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_479 ? stq_4_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_4_bits_addr_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_508 : ~_GEN_410 & _GEN_508);\n if (_GEN_507) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_4_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_4_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_4_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_4_bits_addr_bits <= _GEN_188;\n else\n stq_4_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_4_bits_addr_bits <= _GEN_217;\n stq_4_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_4_bits_data_valid <= ~_GEN_705 & (clear_store ? ~_GEN_678 & _GEN_524 : ~_GEN_410 & _GEN_524);\n if (_GEN_523)\n stq_4_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_4_bits_committed <= ~_GEN_688 & (commit_store & _GEN_649 | _GEN_479 & stq_4_bits_committed);\n stq_4_bits_succeeded <= ~_GEN_688 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h4 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h4)) & _GEN_479 & stq_4_bits_succeeded);\n stq_5_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_470 : ~_GEN_412 & _GEN_470);\n stq_5_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_5_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_5_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_5_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_5_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_5_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_5_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_5_bits_uop_is_br <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_5_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_5_bits_uop_is_jal <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_5_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_5_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_5_bits_uop_taken <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_480)\n stq_5_bits_uop_ppred <= 4'h0;\n stq_5_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_5_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_5_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_5_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_480 & stq_5_bits_uop_ppred_busy;\n stq_5_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h5 | (_GEN_480 ? stq_5_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_5_bits_uop_bypassable <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_5_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_5_bits_uop_is_fence <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_5_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_5_bits_uop_is_amo <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_5_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_5_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_5_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_5_bits_uop_is_unique <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_5_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_5_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_5_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_5_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_5_bits_uop_fp_val <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_5_bits_uop_fp_single <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_5_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_5_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_5_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_5_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_5_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_480 ? stq_5_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_5_bits_addr_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_510 : ~_GEN_412 & _GEN_510);\n if (_GEN_509) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_5_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_5_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_5_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_5_bits_addr_bits <= _GEN_188;\n else\n stq_5_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_5_bits_addr_bits <= _GEN_217;\n stq_5_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_5_bits_data_valid <= ~_GEN_707 & (clear_store ? ~_GEN_680 & _GEN_526 : ~_GEN_412 & _GEN_526);\n if (_GEN_525)\n stq_5_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_5_bits_committed <= ~_GEN_689 & (commit_store & _GEN_650 | _GEN_480 & stq_5_bits_committed);\n stq_5_bits_succeeded <= ~_GEN_689 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h5 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h5)) & _GEN_480 & stq_5_bits_succeeded);\n stq_6_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_472 : ~_GEN_414 & _GEN_472);\n stq_6_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_6_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_6_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_6_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_6_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_6_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_6_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_6_bits_uop_is_br <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_6_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_6_bits_uop_is_jal <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_6_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_6_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_6_bits_uop_taken <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_481)\n stq_6_bits_uop_ppred <= 4'h0;\n stq_6_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_6_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_6_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_6_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_481 & stq_6_bits_uop_ppred_busy;\n stq_6_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & mem_xcpt_uops_0_stq_idx == 3'h6 | (_GEN_481 ? stq_6_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_6_bits_uop_bypassable <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_6_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_6_bits_uop_is_fence <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_6_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_6_bits_uop_is_amo <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_6_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_6_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_6_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_6_bits_uop_is_unique <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_6_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_6_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_6_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_6_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_6_bits_uop_fp_val <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_6_bits_uop_fp_single <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_6_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_6_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_6_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_6_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_6_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_481 ? stq_6_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_6_bits_addr_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_512 : ~_GEN_414 & _GEN_512);\n if (_GEN_511) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_6_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_6_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_6_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_6_bits_addr_bits <= _GEN_188;\n else\n stq_6_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_6_bits_addr_bits <= _GEN_217;\n stq_6_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_6_bits_data_valid <= ~_GEN_709 & (clear_store ? ~_GEN_682 & _GEN_528 : ~_GEN_414 & _GEN_528);\n if (_GEN_527)\n stq_6_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_6_bits_committed <= ~_GEN_690 & (commit_store & _GEN_651 | _GEN_481 & stq_6_bits_committed);\n stq_6_bits_succeeded <= ~_GEN_690 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & io_dmem_resp_0_bits_uop_stq_idx == 3'h6 | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & stq_execute_head == 3'h6)) & _GEN_481 & stq_6_bits_succeeded);\n stq_7_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_474 : ~_GEN_416 & _GEN_474);\n stq_7_bits_uop_is_rvc <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_rvc : io_core_dis_uops_0_bits_is_rvc);\n stq_7_bits_uop_ctrl_fcn_dw <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_fcn_dw : io_core_dis_uops_0_bits_ctrl_fcn_dw);\n stq_7_bits_uop_ctrl_is_load <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_load : io_core_dis_uops_0_bits_ctrl_is_load);\n stq_7_bits_uop_ctrl_is_sta <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_sta : io_core_dis_uops_0_bits_ctrl_is_sta);\n stq_7_bits_uop_ctrl_is_std <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ctrl_is_std : io_core_dis_uops_0_bits_ctrl_is_std);\n stq_7_bits_uop_iw_p1_poisoned <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_iw_p1_poisoned : io_core_dis_uops_0_bits_iw_p1_poisoned);\n stq_7_bits_uop_iw_p2_poisoned <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_iw_p2_poisoned : io_core_dis_uops_0_bits_iw_p2_poisoned);\n stq_7_bits_uop_is_br <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_br : io_core_dis_uops_0_bits_is_br);\n stq_7_bits_uop_is_jalr <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_jalr : io_core_dis_uops_0_bits_is_jalr);\n stq_7_bits_uop_is_jal <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_jal : io_core_dis_uops_0_bits_is_jal);\n stq_7_bits_uop_is_sfb <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_sfb : io_core_dis_uops_0_bits_is_sfb);\n stq_7_bits_uop_edge_inst <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_edge_inst : io_core_dis_uops_0_bits_edge_inst);\n stq_7_bits_uop_taken <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_taken : io_core_dis_uops_0_bits_taken);\n if (_GEN_695 | ~_GEN_482)\n stq_7_bits_uop_ppred <= 4'h0;\n stq_7_bits_uop_prs1_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs1_busy : io_core_dis_uops_0_bits_prs1_busy);\n stq_7_bits_uop_prs2_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs2_busy : io_core_dis_uops_0_bits_prs2_busy);\n stq_7_bits_uop_prs3_busy <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_prs3_busy : io_core_dis_uops_0_bits_prs3_busy);\n stq_7_bits_uop_ppred_busy <= ~_GEN_695 & _GEN_482 & stq_7_bits_uop_ppred_busy;\n stq_7_bits_uop_exception <= ~_GEN_695 & (mem_xcpt_valids_0 & ~mem_xcpt_uops_0_uses_ldq & (&mem_xcpt_uops_0_stq_idx) | (_GEN_482 ? stq_7_bits_uop_exception : io_core_dis_uops_0_bits_exception));\n stq_7_bits_uop_bypassable <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bypassable : io_core_dis_uops_0_bits_bypassable);\n stq_7_bits_uop_mem_signed <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_mem_signed : io_core_dis_uops_0_bits_mem_signed);\n stq_7_bits_uop_is_fence <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_fence : io_core_dis_uops_0_bits_is_fence);\n stq_7_bits_uop_is_fencei <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_fencei : io_core_dis_uops_0_bits_is_fencei);\n stq_7_bits_uop_is_amo <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_amo : io_core_dis_uops_0_bits_is_amo);\n stq_7_bits_uop_uses_ldq <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_uses_ldq : io_core_dis_uops_0_bits_uses_ldq);\n stq_7_bits_uop_uses_stq <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_uses_stq : io_core_dis_uops_0_bits_uses_stq);\n stq_7_bits_uop_is_sys_pc2epc <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_sys_pc2epc : io_core_dis_uops_0_bits_is_sys_pc2epc);\n stq_7_bits_uop_is_unique <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_is_unique : io_core_dis_uops_0_bits_is_unique);\n stq_7_bits_uop_flush_on_commit <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_flush_on_commit : io_core_dis_uops_0_bits_flush_on_commit);\n stq_7_bits_uop_ldst_is_rs1 <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ldst_is_rs1 : io_core_dis_uops_0_bits_ldst_is_rs1);\n stq_7_bits_uop_ldst_val <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_ldst_val : io_core_dis_uops_0_bits_ldst_val);\n stq_7_bits_uop_frs3_en <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_frs3_en : io_core_dis_uops_0_bits_frs3_en);\n stq_7_bits_uop_fp_val <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_fp_val : io_core_dis_uops_0_bits_fp_val);\n stq_7_bits_uop_fp_single <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_fp_single : io_core_dis_uops_0_bits_fp_single);\n stq_7_bits_uop_xcpt_pf_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_pf_if : io_core_dis_uops_0_bits_xcpt_pf_if);\n stq_7_bits_uop_xcpt_ae_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_ae_if : io_core_dis_uops_0_bits_xcpt_ae_if);\n stq_7_bits_uop_xcpt_ma_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_xcpt_ma_if : io_core_dis_uops_0_bits_xcpt_ma_if);\n stq_7_bits_uop_bp_debug_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bp_debug_if : io_core_dis_uops_0_bits_bp_debug_if);\n stq_7_bits_uop_bp_xcpt_if <= ~_GEN_695 & (_GEN_482 ? stq_7_bits_uop_bp_xcpt_if : io_core_dis_uops_0_bits_bp_xcpt_if);\n stq_7_bits_addr_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_514 : ~_GEN_416 & _GEN_514);\n if (_GEN_513) begin\n if (exe_tlb_miss_0) begin\n if (_exe_tlb_vaddr_T_1)\n stq_7_bits_addr_bits <= io_core_exe_0_req_bits_addr;\n else if (will_fire_sfence_0_will_fire)\n stq_7_bits_addr_bits <= _GEN_216;\n else if (will_fire_load_retry_0_will_fire)\n stq_7_bits_addr_bits <= _GEN_180;\n else if (will_fire_sta_retry_0_will_fire)\n stq_7_bits_addr_bits <= _GEN_188;\n else\n stq_7_bits_addr_bits <= _exe_tlb_vaddr_T_2;\n end\n else\n stq_7_bits_addr_bits <= _GEN_217;\n stq_7_bits_addr_is_virtual <= exe_tlb_miss_0;\n end\n stq_7_bits_data_valid <= ~_GEN_711 & (clear_store ? ~_GEN_683 & _GEN_530 : ~_GEN_416 & _GEN_530);\n if (_GEN_529)\n stq_7_bits_data_bits <= _stq_bits_data_bits_T_1;\n stq_7_bits_committed <= ~_GEN_691 & (commit_store & (&idx) | _GEN_482 & stq_7_bits_committed);\n stq_7_bits_succeeded <= ~_GEN_691 & (io_dmem_resp_0_valid & ~io_dmem_resp_0_bits_uop_uses_ldq & io_dmem_resp_0_bits_uop_uses_stq & (&io_dmem_resp_0_bits_uop_stq_idx) | (_GEN_219 | ~(will_fire_store_commit_0_will_fire & (&stq_execute_head))) & _GEN_482 & stq_7_bits_succeeded);\n if (_GEN_694) begin\n ldq_head <= 3'h0;\n ldq_tail <= 3'h0;\n stq_tail <= reset ? 3'h0 : stq_commit_head;\n end\n else begin\n if (commit_load)\n ldq_head <= ldq_head + 3'h1;\n if (io_core_brupdate_b2_mispredict & ~io_core_exception) begin\n ldq_tail <= io_core_brupdate_b2_uop_ldq_idx;\n stq_tail <= io_core_brupdate_b2_uop_stq_idx;\n end\n else begin\n if (dis_ld_val)\n ldq_tail <= _GEN_94;\n if (dis_st_val)\n stq_tail <= _GEN_95;\n end\n end\n if (_GEN_692)\n hella_req_addr <= io_hellacache_req_bits_addr;\n if (_GEN_693) begin\n end\n else\n hella_data_data <= 64'h0;\n if (will_fire_load_incoming_0_will_fire | will_fire_load_retry_0_will_fire | _GEN_220 | ~will_fire_hella_incoming_0_will_fire) begin\n end\n else\n hella_paddr <= exe_tlb_paddr_0;\n if (_GEN_693) begin\n end\n else begin\n hella_xcpt_ma_ld <= _dtlb_io_resp_0_ma_ld;\n hella_xcpt_ma_st <= _dtlb_io_resp_0_ma_st;\n hella_xcpt_pf_ld <= _dtlb_io_resp_0_pf_ld;\n hella_xcpt_pf_st <= _dtlb_io_resp_0_pf_st;\n end\n hella_xcpt_gf_ld <= _GEN_693 & hella_xcpt_gf_ld;\n hella_xcpt_gf_st <= _GEN_693 & hella_xcpt_gf_st;\n if (_GEN_693) begin\n end\n else begin\n hella_xcpt_ae_ld <= _dtlb_io_resp_0_ae_ld;\n hella_xcpt_ae_st <= _dtlb_io_resp_0_ae_st;\n end\n p1_block_load_mask_0 <= block_load_mask_0;\n p1_block_load_mask_1 <= block_load_mask_1;\n p1_block_load_mask_2 <= block_load_mask_2;\n p1_block_load_mask_3 <= block_load_mask_3;\n p1_block_load_mask_4 <= block_load_mask_4;\n p1_block_load_mask_5 <= block_load_mask_5;\n p1_block_load_mask_6 <= block_load_mask_6;\n p1_block_load_mask_7 <= block_load_mask_7;\n p2_block_load_mask_0 <= p1_block_load_mask_0;\n p2_block_load_mask_1 <= p1_block_load_mask_1;\n p2_block_load_mask_2 <= p1_block_load_mask_2;\n p2_block_load_mask_3 <= p1_block_load_mask_3;\n p2_block_load_mask_4 <= p1_block_load_mask_4;\n p2_block_load_mask_5 <= p1_block_load_mask_5;\n p2_block_load_mask_6 <= p1_block_load_mask_6;\n p2_block_load_mask_7 <= p1_block_load_mask_7;\n ldq_retry_idx <= _ldq_retry_idx_T_2 & _temp_bits_T ? 3'h0 : _ldq_retry_idx_T_5 & _temp_bits_T_2 ? 3'h1 : _ldq_retry_idx_T_8 & _temp_bits_T_4 ? 3'h2 : _ldq_retry_idx_T_11 & ~(ldq_head[2]) ? 3'h3 : _ldq_retry_idx_T_14 & _temp_bits_T_8 ? 3'h4 : _ldq_retry_idx_T_17 & _temp_bits_T_10 ? 3'h5 : _ldq_retry_idx_T_20 & _temp_bits_T_12 ? 3'h6 : ldq_7_bits_addr_valid & ldq_7_bits_addr_is_virtual & ~ldq_retry_idx_block_7 ? 3'h7 : _ldq_retry_idx_T_2 ? 3'h0 : _ldq_retry_idx_T_5 ? 3'h1 : _ldq_retry_idx_T_8 ? 3'h2 : _ldq_retry_idx_T_11 ? 3'h3 : _ldq_retry_idx_T_14 ? 3'h4 : _ldq_retry_idx_T_17 ? 3'h5 : {2'h3, ~_ldq_retry_idx_T_20};\n stq_retry_idx <= _stq_retry_idx_T & stq_commit_head == 3'h0 ? 3'h0 : _stq_retry_idx_T_1 & stq_commit_head < 3'h2 ? 3'h1 : _stq_retry_idx_T_2 & stq_commit_head < 3'h3 ? 3'h2 : _stq_retry_idx_T_3 & ~(stq_commit_head[2]) ? 3'h3 : _stq_retry_idx_T_4 & stq_commit_head < 3'h5 ? 3'h4 : _stq_retry_idx_T_5 & stq_commit_head[2:1] != 2'h3 ? 3'h5 : _stq_retry_idx_T_6 & stq_commit_head != 3'h7 ? 3'h6 : stq_7_bits_addr_valid & stq_7_bits_addr_is_virtual ? 3'h7 : _stq_retry_idx_T ? 3'h0 : _stq_retry_idx_T_1 ? 3'h1 : _stq_retry_idx_T_2 ? 3'h2 : _stq_retry_idx_T_3 ? 3'h3 : _stq_retry_idx_T_4 ? 3'h4 : _stq_retry_idx_T_5 ? 3'h5 : {2'h3, ~_stq_retry_idx_T_6};\n ldq_wakeup_idx <= _ldq_wakeup_idx_T_7 & _temp_bits_T ? 3'h0 : _ldq_wakeup_idx_T_15 & _temp_bits_T_2 ? 3'h1 : _ldq_wakeup_idx_T_23 & _temp_bits_T_4 ? 3'h2 : _ldq_wakeup_idx_T_31 & ~(ldq_head[2]) ? 3'h3 : _ldq_wakeup_idx_T_39 & _temp_bits_T_8 ? 3'h4 : _ldq_wakeup_idx_T_47 & _temp_bits_T_10 ? 3'h5 : _ldq_wakeup_idx_T_55 & _temp_bits_T_12 ? 3'h6 : ldq_7_bits_addr_valid & ~ldq_7_bits_executed & ~ldq_7_bits_succeeded & ~ldq_7_bits_addr_is_virtual & ~ldq_retry_idx_block_7 ? 3'h7 : _ldq_wakeup_idx_T_7 ? 3'h0 : _ldq_wakeup_idx_T_15 ? 3'h1 : _ldq_wakeup_idx_T_23 ? 3'h2 : _ldq_wakeup_idx_T_31 ? 3'h3 : _ldq_wakeup_idx_T_39 ? 3'h4 : _ldq_wakeup_idx_T_47 ? 3'h5 : {2'h3, ~_ldq_wakeup_idx_T_55};\n can_fire_load_retry_REG <= _dtlb_io_miss_rdy;\n can_fire_sta_retry_REG <= _dtlb_io_miss_rdy;\n mem_xcpt_valids_0 <= (pf_ld_0 | pf_st_0 | ae_ld_0 | ~_will_fire_store_commit_0_T_2 & _dtlb_io_resp_0_ae_st & exe_tlb_uop_0_uses_stq | ma_ld_0 | ma_st_0) & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & exe_tlb_uop_0_br_mask) == 8'h0;\n mem_xcpt_uops_0_br_mask <= exe_tlb_uop_0_br_mask & ~io_core_brupdate_b1_resolve_mask;\n mem_xcpt_uops_0_rob_idx <= exe_tlb_uop_0_rob_idx;\n mem_xcpt_uops_0_ldq_idx <= exe_tlb_uop_0_ldq_idx;\n mem_xcpt_uops_0_stq_idx <= exe_tlb_uop_0_stq_idx;\n mem_xcpt_uops_0_uses_ldq <= exe_tlb_uop_0_uses_ldq;\n mem_xcpt_uops_0_uses_stq <= exe_tlb_uop_0_uses_stq;\n mem_xcpt_causes_0 <= ma_ld_0 ? 4'h4 : ma_st_0 ? 4'h6 : pf_ld_0 ? 4'hD : pf_st_0 ? 4'hF : {2'h1, ~ae_ld_0, 1'h1};\n mem_xcpt_vaddrs_0 <= exe_tlb_vaddr_0;\n REG <= _GEN_194 | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire;\n fired_load_incoming_REG <= will_fire_load_incoming_0_will_fire & _fired_std_incoming_T;\n fired_stad_incoming_REG <= will_fire_stad_incoming_0_will_fire & _fired_std_incoming_T;\n fired_sta_incoming_REG <= will_fire_sta_incoming_0_will_fire & _fired_std_incoming_T;\n fired_std_incoming_REG <= will_fire_std_incoming_0_will_fire & _fired_std_incoming_T;\n fired_stdf_incoming <= fp_stdata_fire & (io_core_brupdate_b1_mispredict_mask & io_core_fp_stdata_bits_uop_br_mask) == 8'h0;\n fired_sfence_0 <= will_fire_sfence_0_will_fire;\n fired_release_0 <= will_fire_release_0_will_fire;\n fired_load_retry_REG <= will_fire_load_retry_0_will_fire & (io_core_brupdate_b1_mispredict_mask & _GEN_127) == 8'h0;\n fired_sta_retry_REG <= will_fire_sta_retry_0_will_fire & _mem_stq_retry_e_out_valid_T == 8'h0;\n fired_load_wakeup_REG <= will_fire_load_wakeup_0_will_fire & (io_core_brupdate_b1_mispredict_mask & _GEN_189) == 8'h0;\n mem_incoming_uop_0_br_mask <= io_core_exe_0_req_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n mem_incoming_uop_0_rob_idx <= io_core_exe_0_req_bits_uop_rob_idx;\n mem_incoming_uop_0_ldq_idx <= io_core_exe_0_req_bits_uop_ldq_idx;\n mem_incoming_uop_0_stq_idx <= io_core_exe_0_req_bits_uop_stq_idx;\n mem_incoming_uop_0_pdst <= io_core_exe_0_req_bits_uop_pdst;\n mem_incoming_uop_0_fp_val <= io_core_exe_0_req_bits_uop_fp_val;\n mem_ldq_incoming_e_0_bits_uop_br_mask <= _GEN_97[io_core_exe_0_req_bits_uop_ldq_idx] & ~io_core_brupdate_b1_resolve_mask;\n mem_ldq_incoming_e_0_bits_uop_stq_idx <= _GEN_98[io_core_exe_0_req_bits_uop_ldq_idx];\n mem_ldq_incoming_e_0_bits_uop_mem_size <= _GEN_99[io_core_exe_0_req_bits_uop_ldq_idx];\n mem_ldq_incoming_e_0_bits_st_dep_mask <= _GEN_102[io_core_exe_0_req_bits_uop_ldq_idx];\n mem_stq_incoming_e_0_valid <= _GEN_3[io_core_exe_0_req_bits_uop_stq_idx] & (io_core_brupdate_b1_mispredict_mask & _GEN_29[io_core_exe_0_req_bits_uop_stq_idx]) == 8'h0;\n mem_stq_incoming_e_0_bits_uop_br_mask <= _GEN_29[io_core_exe_0_req_bits_uop_stq_idx] & ~io_core_brupdate_b1_resolve_mask;\n mem_stq_incoming_e_0_bits_uop_rob_idx <= _GEN_37[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_uop_stq_idx <= _GEN_39[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_uop_mem_size <= _GEN_56[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_uop_is_amo <= _GEN_61[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_addr_valid <= _GEN_87[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_addr_is_virtual <= _GEN_89[io_core_exe_0_req_bits_uop_stq_idx];\n mem_stq_incoming_e_0_bits_data_valid <= _GEN_90[io_core_exe_0_req_bits_uop_stq_idx];\n mem_ldq_wakeup_e_bits_uop_br_mask <= _GEN_189 & ~io_core_brupdate_b1_resolve_mask;\n mem_ldq_wakeup_e_bits_uop_stq_idx <= mem_ldq_wakeup_e_out_bits_uop_stq_idx;\n mem_ldq_wakeup_e_bits_uop_mem_size <= mem_ldq_wakeup_e_out_bits_uop_mem_size;\n mem_ldq_wakeup_e_bits_st_dep_mask <= mem_ldq_wakeup_e_out_bits_st_dep_mask;\n mem_ldq_retry_e_bits_uop_br_mask <= _GEN_127 & ~io_core_brupdate_b1_resolve_mask;\n mem_ldq_retry_e_bits_uop_stq_idx <= mem_ldq_retry_e_out_bits_uop_stq_idx;\n mem_ldq_retry_e_bits_uop_mem_size <= mem_ldq_retry_e_out_bits_uop_mem_size;\n mem_ldq_retry_e_bits_st_dep_mask <= _GEN_102[ldq_retry_idx];\n mem_stq_retry_e_valid <= _GEN_185 & _mem_stq_retry_e_out_valid_T == 8'h0;\n mem_stq_retry_e_bits_uop_br_mask <= _GEN_186 & ~io_core_brupdate_b1_resolve_mask;\n mem_stq_retry_e_bits_uop_rob_idx <= mem_stq_retry_e_out_bits_uop_rob_idx;\n mem_stq_retry_e_bits_uop_stq_idx <= mem_stq_retry_e_out_bits_uop_stq_idx;\n mem_stq_retry_e_bits_uop_mem_size <= mem_stq_retry_e_out_bits_uop_mem_size;\n mem_stq_retry_e_bits_uop_is_amo <= mem_stq_retry_e_out_bits_uop_is_amo;\n mem_stq_retry_e_bits_data_valid <= _GEN_90[stq_retry_idx];\n mem_stdf_uop_br_mask <= io_core_fp_stdata_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n mem_stdf_uop_rob_idx <= io_core_fp_stdata_bits_uop_rob_idx;\n mem_stdf_uop_stq_idx <= io_core_fp_stdata_bits_uop_stq_idx;\n mem_tlb_miss_0 <= exe_tlb_miss_0;\n mem_tlb_uncacheable_0 <= ~_dtlb_io_resp_0_cacheable;\n mem_paddr_0 <= dmem_req_0_bits_addr;\n clr_bsy_rob_idx_0 <= fired_stad_incoming_REG | fired_sta_incoming_REG | fired_std_incoming_REG ? mem_stq_incoming_e_0_bits_uop_rob_idx : fired_sfence_0 ? mem_incoming_uop_0_rob_idx : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_rob_idx : 5'h0;\n clr_bsy_brmask_0 <= fired_stad_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sta_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_std_incoming_REG ? mem_stq_incoming_e_0_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sfence_0 ? mem_incoming_uop_0_br_mask & ~io_core_brupdate_b1_resolve_mask : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : 8'h0;\n io_core_clr_bsy_0_valid_REG <= io_core_exception;\n io_core_clr_bsy_0_valid_REG_1 <= io_core_exception;\n io_core_clr_bsy_0_valid_REG_2 <= io_core_clr_bsy_0_valid_REG_1;\n stdf_clr_bsy_rob_idx <= fired_stdf_incoming ? mem_stdf_uop_rob_idx : 5'h0;\n stdf_clr_bsy_brmask <= fired_stdf_incoming ? mem_stdf_uop_br_mask & ~io_core_brupdate_b1_resolve_mask : 8'h0;\n io_core_clr_bsy_1_valid_REG <= io_core_exception;\n io_core_clr_bsy_1_valid_REG_1 <= io_core_exception;\n io_core_clr_bsy_1_valid_REG_2 <= io_core_clr_bsy_1_valid_REG_1;\n lcam_addr_REG <= exe_tlb_paddr_0;\n lcam_addr_REG_1 <= io_dmem_release_bits_address;\n lcam_ldq_idx_REG <= ldq_wakeup_idx;\n lcam_ldq_idx_REG_1 <= ldq_retry_idx;\n lcam_stq_idx_REG <= stq_retry_idx;\n s1_executing_loads_0 <= will_fire_load_incoming_0_will_fire ? _GEN_202 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_209 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_195 & dmem_req_fire_0;\n s1_executing_loads_1 <= will_fire_load_incoming_0_will_fire ? _GEN_203 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_210 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_196 & dmem_req_fire_0;\n s1_executing_loads_2 <= will_fire_load_incoming_0_will_fire ? _GEN_204 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_211 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_197 & dmem_req_fire_0;\n s1_executing_loads_3 <= will_fire_load_incoming_0_will_fire ? _GEN_205 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_212 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_198 & dmem_req_fire_0;\n s1_executing_loads_4 <= will_fire_load_incoming_0_will_fire ? _GEN_206 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_213 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_199 & dmem_req_fire_0;\n s1_executing_loads_5 <= will_fire_load_incoming_0_will_fire ? _GEN_207 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_214 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_200 & dmem_req_fire_0;\n s1_executing_loads_6 <= will_fire_load_incoming_0_will_fire ? _GEN_208 & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? _GEN_215 & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & _GEN_201 & dmem_req_fire_0;\n s1_executing_loads_7 <= will_fire_load_incoming_0_will_fire ? (&io_core_exe_0_req_bits_uop_ldq_idx) & dmem_req_fire_0 : will_fire_load_retry_0_will_fire ? (&ldq_retry_idx) & dmem_req_fire_0 : ~will_fire_store_commit_0_will_fire & will_fire_load_wakeup_0_will_fire & (&ldq_wakeup_idx) & dmem_req_fire_0;\n wb_forward_valid_0 <= mem_forward_valid_0;\n wb_forward_ldq_idx_0 <= lcam_ldq_idx_0;\n wb_forward_ld_addr_0 <= lcam_addr_0;\n wb_forward_stq_idx_0 <= _forwarding_age_logic_0_io_forwarding_idx;\n older_nacked_REG <= nacking_loads_0;\n io_dmem_s1_kill_0_REG <= dmem_req_fire_0;\n older_nacked_REG_1 <= nacking_loads_1;\n io_dmem_s1_kill_0_REG_1 <= dmem_req_fire_0;\n older_nacked_REG_2 <= nacking_loads_2;\n io_dmem_s1_kill_0_REG_2 <= dmem_req_fire_0;\n older_nacked_REG_3 <= nacking_loads_3;\n io_dmem_s1_kill_0_REG_3 <= dmem_req_fire_0;\n older_nacked_REG_4 <= nacking_loads_4;\n io_dmem_s1_kill_0_REG_4 <= dmem_req_fire_0;\n older_nacked_REG_5 <= nacking_loads_5;\n io_dmem_s1_kill_0_REG_5 <= dmem_req_fire_0;\n older_nacked_REG_6 <= nacking_loads_6;\n io_dmem_s1_kill_0_REG_6 <= dmem_req_fire_0;\n older_nacked_REG_7 <= nacking_loads_7;\n io_dmem_s1_kill_0_REG_7 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_8 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_9 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_10 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_11 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_12 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_13 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_14 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_15 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_16 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_17 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_18 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_19 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_20 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_21 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_22 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_23 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_24 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_25 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_26 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_27 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_28 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_29 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_30 <= dmem_req_fire_0;\n io_dmem_s1_kill_0_REG_31 <= dmem_req_fire_0;\n REG_1 <= io_core_exception;\n REG_2 <= (ldst_addr_matches_0_0 | ldst_addr_matches_0_1 | ldst_addr_matches_0_2 | ldst_addr_matches_0_3 | ldst_addr_matches_0_4 | ldst_addr_matches_0_5 | ldst_addr_matches_0_6 | ldst_addr_matches_0_7) & ~mem_forward_valid_0;\n if (will_fire_store_commit_0_will_fire | ~can_fire_store_commit_0)\n store_blocked_counter <= 4'h0;\n else if (can_fire_store_commit_0 & ~will_fire_store_commit_0_will_fire)\n store_blocked_counter <= (&store_blocked_counter) ? 4'hF : store_blocked_counter + 4'h1;\n r_xcpt_uop_br_mask <= xcpt_uop_br_mask & ~io_core_brupdate_b1_resolve_mask;\n r_xcpt_uop_rob_idx <= use_mem_xcpt ? mem_xcpt_uops_0_rob_idx : _GEN_135[l_idx];\n r_xcpt_cause <= use_mem_xcpt ? {1'h0, mem_xcpt_causes_0} : 5'h10;\n r_xcpt_badvaddr <= mem_xcpt_vaddrs_0;\n io_core_ld_miss_REG <= io_core_spec_ld_wakeup_0_valid_0;\n spec_ld_succeed_REG <= io_core_spec_ld_wakeup_0_valid_0;\n spec_ld_succeed_REG_1 <= mem_incoming_uop_0_ldq_idx;\n if (reset) begin\n hella_state <= 3'h0;\n live_store_mask <= 8'h0;\n clr_bsy_valid_0 <= 1'h0;\n stdf_clr_bsy_valid <= 1'h0;\n r_xcpt_valid <= 1'h0;\n end\n else begin\n hella_state <= _GEN_713[hella_state];\n live_store_mask <= ({8{dis_st_val}} & 8'h1 << stq_tail | next_live_store_mask) & ~{stq_7_valid & (|_GEN_415), stq_6_valid & (|_GEN_413), stq_5_valid & (|_GEN_411), stq_4_valid & (|_GEN_409), stq_3_valid & (|_GEN_407), stq_2_valid & (|_GEN_405), stq_1_valid & (|_GEN_403), stq_0_valid & (|_GEN_401)} & ~{_GEN_694 & ~reset & _GEN_710, _GEN_694 & ~reset & _GEN_708, _GEN_694 & ~reset & _GEN_706, _GEN_694 & ~reset & _GEN_704, _GEN_694 & ~reset & _GEN_702, _GEN_694 & ~reset & _GEN_700, _GEN_694 & ~reset & _GEN_698, _GEN_694 & ~reset & _GEN_696};\n clr_bsy_valid_0 <= fired_stad_incoming_REG ? mem_stq_incoming_e_0_valid & ~mem_tlb_miss_0 & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_sta_incoming_REG ? mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_data_valid & ~mem_tlb_miss_0 & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_std_incoming_REG ? mem_stq_incoming_e_0_valid & mem_stq_incoming_e_0_bits_addr_valid & ~mem_stq_incoming_e_0_bits_addr_is_virtual & ~mem_stq_incoming_e_0_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_incoming_e_0_bits_uop_br_mask) == 8'h0 : fired_sfence_0 | fired_sta_retry_REG & mem_stq_retry_e_valid & mem_stq_retry_e_bits_data_valid & ~mem_tlb_miss_0 & ~mem_stq_retry_e_bits_uop_is_amo & (io_core_brupdate_b1_mispredict_mask & mem_stq_retry_e_bits_uop_br_mask) == 8'h0;\n stdf_clr_bsy_valid <= fired_stdf_incoming & _GEN_3[mem_stdf_uop_stq_idx] & _GEN_87[mem_stdf_uop_stq_idx] & ~_GEN_89[mem_stdf_uop_stq_idx] & ~_GEN_61[mem_stdf_uop_stq_idx] & (io_core_brupdate_b1_mispredict_mask & mem_stdf_uop_br_mask) == 8'h0;\n r_xcpt_valid <= (ld_xcpt_valid | mem_xcpt_valids_0) & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & xcpt_uop_br_mask) == 8'h0;\n end\n end\n NBDTLB dtlb (\n .clock (clock),\n .reset (reset),\n .io_req_0_valid (~_will_fire_store_commit_0_T_2),\n .io_req_0_bits_vaddr (exe_tlb_vaddr_0),\n .io_req_0_bits_passthrough (will_fire_hella_incoming_0_will_fire),\n .io_req_0_bits_size (_exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire ? exe_tlb_uop_0_mem_size : {2{will_fire_hella_incoming_0_will_fire}}),\n .io_req_0_bits_cmd (_exe_cmd_T | will_fire_sta_incoming_0_will_fire | will_fire_sfence_0_will_fire | will_fire_load_retry_0_will_fire | will_fire_sta_retry_0_will_fire ? exe_tlb_uop_0_mem_cmd : 5'h0),\n .io_miss_rdy (_dtlb_io_miss_rdy),\n .io_resp_0_miss (_dtlb_io_resp_0_miss),\n .io_resp_0_paddr (_dtlb_io_resp_0_paddr),\n .io_resp_0_pf_ld (_dtlb_io_resp_0_pf_ld),\n .io_resp_0_pf_st (_dtlb_io_resp_0_pf_st),\n .io_resp_0_ae_ld (_dtlb_io_resp_0_ae_ld),\n .io_resp_0_ae_st (_dtlb_io_resp_0_ae_st),\n .io_resp_0_ma_ld (_dtlb_io_resp_0_ma_ld),\n .io_resp_0_ma_st (_dtlb_io_resp_0_ma_st),\n .io_resp_0_cacheable (_dtlb_io_resp_0_cacheable),\n .io_sfence_valid (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_valid),\n .io_sfence_bits_rs1 (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_bits_rs1),\n .io_sfence_bits_rs2 (will_fire_sfence_0_will_fire & io_core_exe_0_req_bits_sfence_bits_rs2),\n .io_sfence_bits_addr (will_fire_sfence_0_will_fire ? io_core_exe_0_req_bits_sfence_bits_addr : 39'h0),\n .io_ptw_req_ready (io_ptw_req_ready),\n .io_ptw_req_valid (_dtlb_io_ptw_req_valid),\n .io_ptw_req_bits_valid (io_ptw_req_bits_valid),\n .io_ptw_req_bits_bits_addr (io_ptw_req_bits_bits_addr),\n .io_ptw_resp_valid (io_ptw_resp_valid),\n .io_ptw_resp_bits_ae_final (io_ptw_resp_bits_ae_final),\n .io_ptw_resp_bits_pte_ppn (io_ptw_resp_bits_pte_ppn),\n .io_ptw_resp_bits_pte_d (io_ptw_resp_bits_pte_d),\n .io_ptw_resp_bits_pte_a (io_ptw_resp_bits_pte_a),\n .io_ptw_resp_bits_pte_g (io_ptw_resp_bits_pte_g),\n .io_ptw_resp_bits_pte_u (io_ptw_resp_bits_pte_u),\n .io_ptw_resp_bits_pte_x (io_ptw_resp_bits_pte_x),\n .io_ptw_resp_bits_pte_w (io_ptw_resp_bits_pte_w),\n .io_ptw_resp_bits_pte_r (io_ptw_resp_bits_pte_r),\n .io_ptw_resp_bits_pte_v (io_ptw_resp_bits_pte_v),\n .io_ptw_resp_bits_level (io_ptw_resp_bits_level),\n .io_ptw_resp_bits_homogeneous (io_ptw_resp_bits_homogeneous),\n .io_ptw_ptbr_mode (io_ptw_ptbr_mode),\n .io_ptw_status_dprv (io_ptw_status_dprv),\n .io_ptw_status_mxr (io_ptw_status_mxr),\n .io_ptw_status_sum (io_ptw_status_sum),\n .io_ptw_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l),\n .io_ptw_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a),\n .io_ptw_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x),\n .io_ptw_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w),\n .io_ptw_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r),\n .io_ptw_pmp_0_addr (io_ptw_pmp_0_addr),\n .io_ptw_pmp_0_mask (io_ptw_pmp_0_mask),\n .io_ptw_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l),\n .io_ptw_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a),\n .io_ptw_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x),\n .io_ptw_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w),\n .io_ptw_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r),\n .io_ptw_pmp_1_addr (io_ptw_pmp_1_addr),\n .io_ptw_pmp_1_mask (io_ptw_pmp_1_mask),\n .io_ptw_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l),\n .io_ptw_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a),\n .io_ptw_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x),\n .io_ptw_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w),\n .io_ptw_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r),\n .io_ptw_pmp_2_addr (io_ptw_pmp_2_addr),\n .io_ptw_pmp_2_mask (io_ptw_pmp_2_mask),\n .io_ptw_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l),\n .io_ptw_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a),\n .io_ptw_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x),\n .io_ptw_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w),\n .io_ptw_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r),\n .io_ptw_pmp_3_addr (io_ptw_pmp_3_addr),\n .io_ptw_pmp_3_mask (io_ptw_pmp_3_mask),\n .io_ptw_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l),\n .io_ptw_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a),\n .io_ptw_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x),\n .io_ptw_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w),\n .io_ptw_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r),\n .io_ptw_pmp_4_addr (io_ptw_pmp_4_addr),\n .io_ptw_pmp_4_mask (io_ptw_pmp_4_mask),\n .io_ptw_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l),\n .io_ptw_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a),\n .io_ptw_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x),\n .io_ptw_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w),\n .io_ptw_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r),\n .io_ptw_pmp_5_addr (io_ptw_pmp_5_addr),\n .io_ptw_pmp_5_mask (io_ptw_pmp_5_mask),\n .io_ptw_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l),\n .io_ptw_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a),\n .io_ptw_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x),\n .io_ptw_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w),\n .io_ptw_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r),\n .io_ptw_pmp_6_addr (io_ptw_pmp_6_addr),\n .io_ptw_pmp_6_mask (io_ptw_pmp_6_mask),\n .io_ptw_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l),\n .io_ptw_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a),\n .io_ptw_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x),\n .io_ptw_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w),\n .io_ptw_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r),\n .io_ptw_pmp_7_addr (io_ptw_pmp_7_addr),\n .io_ptw_pmp_7_mask (io_ptw_pmp_7_mask),\n .io_kill (will_fire_hella_incoming_0_will_fire & io_hellacache_s1_kill)\n );\n ForwardingAgeLogic forwarding_age_logic_0 (\n .io_addr_matches ({ldst_addr_matches_0_7, ldst_addr_matches_0_6, ldst_addr_matches_0_5, ldst_addr_matches_0_4, ldst_addr_matches_0_3, ldst_addr_matches_0_2, ldst_addr_matches_0_1, ldst_addr_matches_0_0}),\n .io_youngest_st_idx (do_st_search_0 ? (_lcam_stq_idx_T ? mem_stq_incoming_e_0_bits_uop_stq_idx : fired_sta_retry_REG ? mem_stq_retry_e_bits_uop_stq_idx : 3'h0) : do_ld_search_0 ? (fired_load_incoming_REG ? mem_ldq_incoming_e_0_bits_uop_stq_idx : fired_load_retry_REG ? mem_ldq_retry_e_bits_uop_stq_idx : fired_load_wakeup_REG ? mem_ldq_wakeup_e_bits_uop_stq_idx : 3'h0) : 3'h0),\n .io_forwarding_idx (_forwarding_age_logic_0_io_forwarding_idx)\n );\n assign io_ptw_req_valid = _dtlb_io_ptw_req_valid;\n assign io_core_exe_0_iresp_valid = io_core_exe_0_iresp_valid_0;\n assign io_core_exe_0_iresp_bits_uop_rob_idx = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_37[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_390;\n assign io_core_exe_0_iresp_bits_uop_pdst = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_41[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_391;\n assign io_core_exe_0_iresp_bits_uop_is_amo = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_61[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_393;\n assign io_core_exe_0_iresp_bits_uop_uses_stq = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_64[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_394;\n assign io_core_exe_0_iresp_bits_uop_dst_rtype = _GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_74[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_395;\n assign io_core_exe_0_iresp_bits_data = _GEN_400 ? io_dmem_resp_0_bits_data : {_ldq_bits_debug_wb_data_T_17 ? {56{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed_2[7]}} : {_ldq_bits_debug_wb_data_T_9 ? {48{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed_1[15]}} : {_ldq_bits_debug_wb_data_T_1 ? {32{_GEN_392 & io_core_exe_0_iresp_bits_data_zeroed[31]}} : _GEN_399[63:32], io_core_exe_0_iresp_bits_data_zeroed[31:16]}, io_core_exe_0_iresp_bits_data_zeroed_1[15:8]}, io_core_exe_0_iresp_bits_data_zeroed_2};\n assign io_core_exe_0_fresp_valid = io_core_exe_0_fresp_valid_0;\n assign io_core_exe_0_fresp_bits_uop_uopc = _GEN_400 ? _GEN_103[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_103[wb_forward_ldq_idx_0];\n assign io_core_exe_0_fresp_bits_uop_br_mask = _GEN_400 ? _GEN_97[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_389;\n assign io_core_exe_0_fresp_bits_uop_rob_idx = _GEN_400 ? _GEN_135[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_390;\n assign io_core_exe_0_fresp_bits_uop_stq_idx = _GEN_400 ? _GEN_98[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_98[wb_forward_ldq_idx_0];\n assign io_core_exe_0_fresp_bits_uop_pdst = _GEN_400 ? _GEN_138[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_391;\n assign io_core_exe_0_fresp_bits_uop_mem_size = _GEN_400 ? _GEN_99[io_dmem_resp_0_bits_uop_ldq_idx] : size_1;\n assign io_core_exe_0_fresp_bits_uop_is_amo = _GEN_400 ? _GEN_154[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_393;\n assign io_core_exe_0_fresp_bits_uop_uses_stq = _GEN_400 ? _GEN_156[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_394;\n assign io_core_exe_0_fresp_bits_uop_dst_rtype = _GEN_400 ? _GEN_166[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_395;\n assign io_core_exe_0_fresp_bits_uop_fp_val = _GEN_400 ? _GEN_170[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_170[wb_forward_ldq_idx_0];\n assign io_core_exe_0_fresp_bits_data = {1'h0, _GEN_400 ? io_dmem_resp_0_bits_data : {_ldq_bits_debug_wb_data_T_17 ? {56{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed_2[7]}} : {_ldq_bits_debug_wb_data_T_9 ? {48{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed_1[15]}} : {_ldq_bits_debug_wb_data_T_1 ? {32{_GEN_392 & io_core_exe_0_fresp_bits_data_zeroed[31]}} : _GEN_399[63:32], io_core_exe_0_fresp_bits_data_zeroed[31:16]}, io_core_exe_0_fresp_bits_data_zeroed_1[15:8]}, io_core_exe_0_fresp_bits_data_zeroed_2}};\n assign io_core_dis_ldq_idx_0 = ldq_tail;\n assign io_core_dis_stq_idx_0 = stq_tail;\n assign io_core_ldq_full_0 = _GEN_94 == ldq_head;\n assign io_core_stq_full_0 = _GEN_95 == stq_head;\n assign io_core_fp_stdata_ready = io_core_fp_stdata_ready_0;\n assign io_core_clr_bsy_0_valid = clr_bsy_valid_0 & (io_core_brupdate_b1_mispredict_mask & clr_bsy_brmask_0) == 8'h0 & ~io_core_exception & ~io_core_clr_bsy_0_valid_REG & ~io_core_clr_bsy_0_valid_REG_2;\n assign io_core_clr_bsy_0_bits = clr_bsy_rob_idx_0;\n assign io_core_clr_bsy_1_valid = stdf_clr_bsy_valid & (io_core_brupdate_b1_mispredict_mask & stdf_clr_bsy_brmask) == 8'h0 & ~io_core_exception & ~io_core_clr_bsy_1_valid_REG & ~io_core_clr_bsy_1_valid_REG_2;\n assign io_core_clr_bsy_1_bits = stdf_clr_bsy_rob_idx;\n assign io_core_spec_ld_wakeup_0_valid = io_core_spec_ld_wakeup_0_valid_0;\n assign io_core_spec_ld_wakeup_0_bits = mem_incoming_uop_0_pdst;\n assign io_core_ld_miss = ~(~spec_ld_succeed_REG | io_core_exe_0_iresp_valid_0 & (_GEN_400 ? (io_dmem_resp_0_bits_uop_uses_ldq ? _GEN_136[io_dmem_resp_0_bits_uop_ldq_idx] : _GEN_38[io_dmem_resp_0_bits_uop_stq_idx]) : _GEN_136[wb_forward_ldq_idx_0]) == spec_ld_succeed_REG_1) & io_core_ld_miss_REG;\n assign io_core_fencei_rdy = ~(stq_0_valid | stq_1_valid | stq_2_valid | stq_3_valid | stq_4_valid | stq_5_valid | stq_6_valid | stq_7_valid) & io_dmem_ordered;\n assign io_core_lxcpt_valid = r_xcpt_valid & ~io_core_exception & (io_core_brupdate_b1_mispredict_mask & r_xcpt_uop_br_mask) == 8'h0;\n assign io_core_lxcpt_bits_uop_br_mask = r_xcpt_uop_br_mask;\n assign io_core_lxcpt_bits_uop_rob_idx = r_xcpt_uop_rob_idx;\n assign io_core_lxcpt_bits_cause = r_xcpt_cause;\n assign io_core_lxcpt_bits_badvaddr = r_xcpt_badvaddr;\n assign io_core_perf_acquire = io_dmem_perf_acquire;\n assign io_core_perf_release = io_dmem_perf_release;\n assign io_core_perf_tlbMiss = io_ptw_req_ready & _dtlb_io_ptw_req_valid;\n assign io_dmem_req_valid = dmem_req_0_valid;\n assign io_dmem_req_bits_0_valid = dmem_req_0_valid;\n assign io_dmem_req_bits_0_bits_uop_uopc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_uopc : will_fire_load_retry_0_will_fire ? _GEN_103[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_5[stq_retry_idx] : 7'h0) : will_fire_store_commit_0_will_fire ? _GEN_5[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_103[ldq_wakeup_idx] : 7'h0;\n assign io_dmem_req_bits_0_bits_uop_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_inst : will_fire_load_retry_0_will_fire ? _GEN_104[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_6[stq_retry_idx] : 32'h0) : will_fire_store_commit_0_will_fire ? _GEN_6[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_104[ldq_wakeup_idx] : 32'h0;\n assign io_dmem_req_bits_0_bits_uop_debug_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_inst : will_fire_load_retry_0_will_fire ? _GEN_105[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_7[stq_retry_idx] : 32'h0) : will_fire_store_commit_0_will_fire ? _GEN_7[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_105[ldq_wakeup_idx] : 32'h0;\n assign io_dmem_req_bits_0_bits_uop_is_rvc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_rvc : will_fire_load_retry_0_will_fire ? _GEN_106[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_8[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_8[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_106[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_debug_pc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_pc : will_fire_load_retry_0_will_fire ? _GEN_107[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_9[stq_retry_idx] : 40'h0) : will_fire_store_commit_0_will_fire ? _GEN_9[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_107[ldq_wakeup_idx] : 40'h0;\n assign io_dmem_req_bits_0_bits_uop_iq_type = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_iq_type : will_fire_load_retry_0_will_fire ? _GEN_108[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_10[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_10[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_108[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_fu_code = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fu_code : will_fire_load_retry_0_will_fire ? _GEN_109[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_11[stq_retry_idx] : 10'h0) : will_fire_store_commit_0_will_fire ? _GEN_11[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_109[ldq_wakeup_idx] : 10'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_br_type = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_br_type : will_fire_load_retry_0_will_fire ? _GEN_110[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_12[stq_retry_idx] : 4'h0) : will_fire_store_commit_0_will_fire ? _GEN_12[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_110[ldq_wakeup_idx] : 4'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_op1_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op1_sel : will_fire_load_retry_0_will_fire ? _GEN_111[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_13[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_13[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_111[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_op2_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op2_sel : will_fire_load_retry_0_will_fire ? _GEN_112[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_14[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_14[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_112[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_imm_sel = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_imm_sel : will_fire_load_retry_0_will_fire ? _GEN_113[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_15[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_15[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_113[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_op_fcn = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_op_fcn : will_fire_load_retry_0_will_fire ? _GEN_114[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_16[stq_retry_idx] : 5'h0) : will_fire_store_commit_0_will_fire ? _GEN_16[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_114[ldq_wakeup_idx] : 5'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_fcn_dw : will_fire_load_retry_0_will_fire ? _GEN_115[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_17[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_17[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_115[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_csr_cmd : will_fire_load_retry_0_will_fire ? _GEN_116[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_18[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_18[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_116[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_ctrl_is_load = _GEN_219 ? exe_tlb_uop_0_ctrl_is_load : will_fire_store_commit_0_will_fire ? _GEN_19[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_117[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ctrl_is_sta = _GEN_219 ? exe_tlb_uop_0_ctrl_is_sta : will_fire_store_commit_0_will_fire ? _GEN_20[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_118[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ctrl_is_std = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ctrl_is_std : will_fire_load_retry_0_will_fire ? _GEN_119[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_21[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_21[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_119[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_iw_state = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_iw_state : will_fire_load_retry_0_will_fire ? _GEN_120[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_22[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_22[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_120[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_iw_p1_poisoned = _GEN_219 ? ~_exe_tlb_uop_T_2 & (will_fire_load_retry_0_will_fire ? _GEN_121[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_23[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_23[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_121[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_iw_p2_poisoned = _GEN_219 ? ~_exe_tlb_uop_T_2 & (will_fire_load_retry_0_will_fire ? _GEN_122[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_24[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_24[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_122[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_br = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_br : will_fire_load_retry_0_will_fire ? _GEN_123[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_25[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_25[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_123[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_jalr = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_jalr : will_fire_load_retry_0_will_fire ? _GEN_124[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_26[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_26[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_124[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_jal = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_jal : will_fire_load_retry_0_will_fire ? _GEN_125[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_27[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_27[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_125[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_sfb = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_sfb : will_fire_load_retry_0_will_fire ? _GEN_126[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_28[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_28[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_126[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_br_mask = _GEN_219 ? exe_tlb_uop_0_br_mask : will_fire_store_commit_0_will_fire ? _GEN_29[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_189 : 8'h0;\n assign io_dmem_req_bits_0_bits_uop_br_tag = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_br_tag : will_fire_load_retry_0_will_fire ? _GEN_128[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_30[stq_retry_idx] : 3'h0) : will_fire_store_commit_0_will_fire ? _GEN_30[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_128[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_ftq_idx = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ftq_idx : will_fire_load_retry_0_will_fire ? _GEN_129[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_31[stq_retry_idx] : 4'h0) : will_fire_store_commit_0_will_fire ? _GEN_31[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_129[ldq_wakeup_idx] : 4'h0;\n assign io_dmem_req_bits_0_bits_uop_edge_inst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_edge_inst : will_fire_load_retry_0_will_fire ? _GEN_130[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_32[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_32[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_130[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_pc_lob = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_pc_lob : will_fire_load_retry_0_will_fire ? _GEN_131[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_33[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_33[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_131[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_taken = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_taken : will_fire_load_retry_0_will_fire ? _GEN_132[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_34[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_34[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_132[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_imm_packed = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_imm_packed : will_fire_load_retry_0_will_fire ? _GEN_133[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_35[stq_retry_idx] : 20'h0) : will_fire_store_commit_0_will_fire ? _GEN_35[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_133[ldq_wakeup_idx] : 20'h0;\n assign io_dmem_req_bits_0_bits_uop_csr_addr = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_csr_addr : will_fire_load_retry_0_will_fire ? _GEN_134[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_36[stq_retry_idx] : 12'h0) : will_fire_store_commit_0_will_fire ? _GEN_36[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_134[ldq_wakeup_idx] : 12'h0;\n assign io_dmem_req_bits_0_bits_uop_rob_idx = _GEN_219 ? exe_tlb_uop_0_rob_idx : will_fire_store_commit_0_will_fire ? _GEN_37[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_135[ldq_wakeup_idx] : 5'h0;\n assign io_dmem_req_bits_0_bits_uop_ldq_idx = _GEN_219 ? exe_tlb_uop_0_ldq_idx : will_fire_store_commit_0_will_fire ? _GEN_38[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_136[ldq_wakeup_idx] : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_stq_idx = _GEN_219 ? exe_tlb_uop_0_stq_idx : will_fire_store_commit_0_will_fire ? _GEN_39[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? mem_ldq_wakeup_e_out_bits_uop_stq_idx : 3'h0;\n assign io_dmem_req_bits_0_bits_uop_rxq_idx = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_rxq_idx : will_fire_load_retry_0_will_fire ? _GEN_137[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_40[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_40[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_137[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_pdst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_pdst : will_fire_load_retry_0_will_fire ? _GEN_139 : _exe_tlb_uop_T_4_pdst) : will_fire_store_commit_0_will_fire ? _GEN_41[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_138[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_prs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs1 : will_fire_load_retry_0_will_fire ? _GEN_140[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_42[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_42[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_140[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_prs2 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs2 : will_fire_load_retry_0_will_fire ? _GEN_141[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_43[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_43[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_141[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_prs3 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs3 : will_fire_load_retry_0_will_fire ? _GEN_142[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_44[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_44[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_142[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_ppred = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ppred : will_fire_load_retry_0_will_fire | ~will_fire_sta_retry_0_will_fire ? 4'h0 : _GEN_45[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_45[stq_execute_head] : 4'h0;\n assign io_dmem_req_bits_0_bits_uop_prs1_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs1_busy : will_fire_load_retry_0_will_fire ? _GEN_143[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_46[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_46[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_143[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_prs2_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs2_busy : will_fire_load_retry_0_will_fire ? _GEN_144[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_47[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_47[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_144[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_prs3_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_prs3_busy : will_fire_load_retry_0_will_fire ? _GEN_145[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_48[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_48[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_145[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ppred_busy = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ppred_busy : ~will_fire_load_retry_0_will_fire & will_fire_sta_retry_0_will_fire & _GEN_49[stq_retry_idx]) : will_fire_store_commit_0_will_fire & _GEN_49[stq_execute_head];\n assign io_dmem_req_bits_0_bits_uop_stale_pdst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_stale_pdst : will_fire_load_retry_0_will_fire ? _GEN_146[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_50[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_50[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_146[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_exception = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_exception : will_fire_load_retry_0_will_fire ? _GEN_147[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_51[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_52 : will_fire_load_wakeup_0_will_fire & _GEN_147[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_exc_cause = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_exc_cause : will_fire_load_retry_0_will_fire ? _GEN_148[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_53[stq_retry_idx] : 64'h0) : will_fire_store_commit_0_will_fire ? _GEN_53[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_148[ldq_wakeup_idx] : 64'h0;\n assign io_dmem_req_bits_0_bits_uop_bypassable = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bypassable : will_fire_load_retry_0_will_fire ? _GEN_149[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_54[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_54[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_149[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_mem_cmd = _GEN_219 ? exe_tlb_uop_0_mem_cmd : will_fire_store_commit_0_will_fire ? _GEN_55[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_150[ldq_wakeup_idx] : 5'h0;\n assign io_dmem_req_bits_0_bits_uop_mem_size = _GEN_219 ? exe_tlb_uop_0_mem_size : will_fire_store_commit_0_will_fire ? dmem_req_0_bits_data_size : will_fire_load_wakeup_0_will_fire ? mem_ldq_wakeup_e_out_bits_uop_mem_size : {2{will_fire_hella_incoming_0_will_fire | will_fire_hella_wakeup_0_will_fire}};\n assign io_dmem_req_bits_0_bits_uop_mem_signed = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_mem_signed : will_fire_load_retry_0_will_fire ? _GEN_151[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_57[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_57[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_151[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_fence = _GEN_219 ? exe_tlb_uop_0_is_fence : will_fire_store_commit_0_will_fire ? _GEN_59 : will_fire_load_wakeup_0_will_fire & _GEN_152[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_fencei = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_fencei : will_fire_load_retry_0_will_fire ? _GEN_153[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_60[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_60[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_153[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_amo = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_amo : will_fire_load_retry_0_will_fire ? _GEN_154[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & mem_stq_retry_e_out_bits_uop_is_amo) : will_fire_store_commit_0_will_fire ? _GEN_62 : will_fire_load_wakeup_0_will_fire & _GEN_154[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_uses_ldq = _GEN_219 ? exe_tlb_uop_0_uses_ldq : will_fire_store_commit_0_will_fire ? _GEN_63[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_155[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_uses_stq = _GEN_219 ? exe_tlb_uop_0_uses_stq : will_fire_store_commit_0_will_fire ? _GEN_64[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_156[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_sys_pc2epc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_sys_pc2epc : will_fire_load_retry_0_will_fire ? _GEN_157[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_65[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_65[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_157[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_is_unique = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_is_unique : will_fire_load_retry_0_will_fire ? _GEN_158[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_66[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_66[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_158[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_flush_on_commit = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_flush_on_commit : will_fire_load_retry_0_will_fire ? _GEN_159[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_67[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_67[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_159[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ldst_is_rs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst_is_rs1 : will_fire_load_retry_0_will_fire ? _GEN_160[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_68[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_68[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_160[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_ldst = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst : will_fire_load_retry_0_will_fire ? _GEN_161[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_69[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_69[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_161[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_lrs1 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs1 : will_fire_load_retry_0_will_fire ? _GEN_162[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_70[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_70[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_162[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_lrs2 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs2 : will_fire_load_retry_0_will_fire ? _GEN_163[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_71[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_71[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_163[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_lrs3 = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs3 : will_fire_load_retry_0_will_fire ? _GEN_164[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_72[stq_retry_idx] : 6'h0) : will_fire_store_commit_0_will_fire ? _GEN_72[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_164[ldq_wakeup_idx] : 6'h0;\n assign io_dmem_req_bits_0_bits_uop_ldst_val = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_ldst_val : will_fire_load_retry_0_will_fire ? _GEN_165[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_73[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_73[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_165[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_dst_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_dst_rtype : will_fire_load_retry_0_will_fire ? _GEN_166[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_74[stq_retry_idx] : 2'h2) : will_fire_store_commit_0_will_fire ? _GEN_74[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_166[ldq_wakeup_idx] : 2'h2;\n assign io_dmem_req_bits_0_bits_uop_lrs1_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs1_rtype : will_fire_load_retry_0_will_fire ? _GEN_167[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_75[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_75[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_167[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_lrs2_rtype = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_lrs2_rtype : will_fire_load_retry_0_will_fire ? _GEN_168[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_76[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_76[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_168[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_frs3_en = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_frs3_en : will_fire_load_retry_0_will_fire ? _GEN_169[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_77[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_77[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_169[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_fp_val = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fp_val : will_fire_load_retry_0_will_fire ? _GEN_170[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_78[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_78[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_170[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_fp_single = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_fp_single : will_fire_load_retry_0_will_fire ? _GEN_171[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_79[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_79[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_171[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_xcpt_pf_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_pf_if : will_fire_load_retry_0_will_fire ? _GEN_172[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_80[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_80[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_172[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_xcpt_ae_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_ae_if : will_fire_load_retry_0_will_fire ? _GEN_173[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_81[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_81[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_173[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_xcpt_ma_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_xcpt_ma_if : will_fire_load_retry_0_will_fire ? _GEN_174[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_82[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_82[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_174[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_bp_debug_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bp_debug_if : will_fire_load_retry_0_will_fire ? _GEN_175[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_83[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_83[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_175[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_bp_xcpt_if = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_bp_xcpt_if : will_fire_load_retry_0_will_fire ? _GEN_176[ldq_retry_idx] : will_fire_sta_retry_0_will_fire & _GEN_84[stq_retry_idx]) : will_fire_store_commit_0_will_fire ? _GEN_84[stq_execute_head] : will_fire_load_wakeup_0_will_fire & _GEN_176[ldq_wakeup_idx];\n assign io_dmem_req_bits_0_bits_uop_debug_fsrc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_fsrc : will_fire_load_retry_0_will_fire ? _GEN_177[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_85[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_85[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_177[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_uop_debug_tsrc = _GEN_219 ? (_exe_tlb_uop_T_2 ? io_core_exe_0_req_bits_uop_debug_tsrc : will_fire_load_retry_0_will_fire ? _GEN_178[ldq_retry_idx] : will_fire_sta_retry_0_will_fire ? _GEN_86[stq_retry_idx] : 2'h0) : will_fire_store_commit_0_will_fire ? _GEN_86[stq_execute_head] : will_fire_load_wakeup_0_will_fire ? _GEN_178[ldq_wakeup_idx] : 2'h0;\n assign io_dmem_req_bits_0_bits_addr = dmem_req_0_bits_addr;\n assign io_dmem_req_bits_0_bits_data = _GEN_219 ? 64'h0 : will_fire_store_commit_0_will_fire ? _GEN_218[dmem_req_0_bits_data_size] : will_fire_load_wakeup_0_will_fire | will_fire_hella_incoming_0_will_fire | ~will_fire_hella_wakeup_0_will_fire ? 64'h0 : hella_data_data;\n assign io_dmem_req_bits_0_bits_is_hella = ~(_GEN_219 | will_fire_store_commit_0_will_fire | will_fire_load_wakeup_0_will_fire) & (will_fire_hella_incoming_0_will_fire | will_fire_hella_wakeup_0_will_fire);\n assign io_dmem_s1_kill_0 = _GEN_368 ? (_GEN_370 ? io_dmem_s1_kill_0_REG_29 : _GEN_371 ? io_dmem_s1_kill_0_REG_30 : _GEN_372 ? io_dmem_s1_kill_0_REG_31 : _GEN_366) : _GEN_366;\n assign io_dmem_brupdate_b1_resolve_mask = io_core_brupdate_b1_resolve_mask;\n assign io_dmem_brupdate_b1_mispredict_mask = io_core_brupdate_b1_mispredict_mask;\n assign io_dmem_exception = io_core_exception;\n assign io_dmem_release_ready = will_fire_release_0_will_fire;\n assign io_dmem_force_order = _GEN_427 & _GEN_428 | io_core_fence_dmem;\n assign io_hellacache_req_ready = io_hellacache_req_ready_0;\n assign io_hellacache_s2_nack = ~_GEN_430 & _GEN_429;\n assign io_hellacache_resp_valid = ~(_GEN_430 | _GEN_429 | _GEN_431) & _GEN_374 & _GEN_432;\n assign io_hellacache_resp_bits_data = io_dmem_resp_0_bits_data;\n assign io_hellacache_s2_xcpt_ae_ld = ~(io_hellacache_req_ready_0 | _GEN_2 | _GEN_429) & _GEN_431 & hella_xcpt_ae_ld;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// If regfile bypassing is disabled, then the functional unit must do its own\n// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)\n//\n// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}\n\nimport boom.v3.common._\nimport boom.v3.ifu._\nimport boom.v3.util._\n\n/**t\n * Functional unit constants\n */\nobject FUConstants\n{\n // bit mask, since a given execution pipeline may support multiple functional units\n val FUC_SZ = 10\n val FU_X = BitPat.dontCare(FUC_SZ)\n val FU_ALU = 1.U(FUC_SZ.W)\n val FU_JMP = 2.U(FUC_SZ.W)\n val FU_MEM = 4.U(FUC_SZ.W)\n val FU_MUL = 8.U(FUC_SZ.W)\n val FU_DIV = 16.U(FUC_SZ.W)\n val FU_CSR = 32.U(FUC_SZ.W)\n val FU_FPU = 64.U(FUC_SZ.W)\n val FU_FDV = 128.U(FUC_SZ.W)\n val FU_I2F = 256.U(FUC_SZ.W)\n val FU_F2I = 512.U(FUC_SZ.W)\n\n // FP stores generate data through FP F2I, and generate address through MemAddrCalc\n val FU_F2IMEM = 516.U(FUC_SZ.W)\n}\nimport FUConstants._\n\n/**\n * Class to tell the FUDecoders what units it needs to support\n *\n * @param alu support alu unit?\n * @param bru support br unit?\n * @param mem support mem unit?\n * @param muld support multiple div unit?\n * @param fpu support FP unit?\n * @param csr support csr writing unit?\n * @param fdiv support FP div unit?\n * @param ifpu support int to FP unit?\n */\nclass SupportedFuncUnits(\n val alu: Boolean = false,\n val jmp: Boolean = false,\n val mem: Boolean = false,\n val muld: Boolean = false,\n val fpu: Boolean = false,\n val csr: Boolean = false,\n val fdiv: Boolean = false,\n val ifpu: Boolean = false)\n{\n}\n\n\n/**\n * Bundle for signals sent to the functional unit\n *\n * @param dataWidth width of the data sent to the functional unit\n */\nclass FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val numOperands = 3\n\n val rs1_data = UInt(dataWidth.W)\n val rs2_data = UInt(dataWidth.W)\n val rs3_data = UInt(dataWidth.W) // only used for FMA units\n val pred_data = Bool()\n\n val kill = Bool() // kill everything\n}\n\n/**\n * Bundle for the signals sent out of the function unit\n *\n * @param dataWidth data sent from the functional unit\n */\nclass FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val predicated = Bool() // Was this response from a predicated-off instruction\n val data = UInt(dataWidth.W)\n val fflags = new ValidIO(new FFlagsResp)\n val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU\n val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU\n val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc\n}\n\n/**\n * Branch resolution information given from the branch unit\n */\nclass BrResolutionInfo(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp\n val valid = Bool()\n val mispredict = Bool()\n val taken = Bool() // which direction did the branch go?\n val cfi_type = UInt(CFI_SZ.W)\n\n // Info for recalculating the pc for this branch\n val pc_sel = UInt(2.W)\n\n val jalr_target = UInt(vaddrBitsExtended.W)\n val target_offset = SInt()\n}\n\nclass BrUpdateInfo(implicit p: Parameters) extends BoomBundle\n{\n // On the first cycle we get masks to kill registers\n val b1 = new BrUpdateMasks\n // On the second cycle we get indices to reset pointers\n val b2 = new BrResolutionInfo\n}\n\nclass BrUpdateMasks(implicit p: Parameters) extends BoomBundle\n{\n val resolve_mask = UInt(maxBrCount.W)\n val mispredict_mask = UInt(maxBrCount.W)\n}\n\n\n/**\n * Abstract top level functional unit class that wraps a lower level hand made functional unit\n *\n * @param isPipelined is the functional unit pipelined?\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class FunctionalUnit(\n val isPipelined: Boolean,\n val numStages: Int,\n val numBypassStages: Int,\n val dataWidth: Int,\n val isJmpUnit: Boolean = false,\n val isAluUnit: Boolean = false,\n val isMemAddrCalcUnit: Boolean = false,\n val needsFcsr: Boolean = false)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))\n\n val brupdate = Input(new BrUpdateInfo())\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n\n // only used by the fpu unit\n val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by branch unit\n val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null\n\n // only used by memaddr calc unit\n val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null\n\n })\n\n io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }\n\n io.resp.valid := false.B\n io.resp.bits := DontCare\n\n if (isJmpUnit) {\n io.get_ftq_pc.ftq_idx := DontCare\n }\n}\n\n/**\n * Abstract top level pipelined functional unit\n *\n * Note: this helps track which uops get killed while in intermediate stages,\n * but it is the job of the consumer to check for kills on the same cycle as consumption!!!\n *\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param earliestBypassStage first stage that you can start bypassing from\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class PipelinedFunctionalUnit(\n numStages: Int,\n numBypassStages: Int,\n earliestBypassStage: Int,\n dataWidth: Int,\n isJmpUnit: Boolean = false,\n isAluUnit: Boolean = false,\n isMemAddrCalcUnit: Boolean = false,\n needsFcsr: Boolean = false\n )(implicit p: Parameters) extends FunctionalUnit(\n isPipelined = true,\n numStages = numStages,\n numBypassStages = numBypassStages,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit,\n isAluUnit = isAluUnit,\n isMemAddrCalcUnit = isMemAddrCalcUnit,\n needsFcsr = needsFcsr)\n{\n // Pipelined functional unit is always ready.\n io.req.ready := true.B\n\n if (numStages > 0) {\n val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_uops = Reg(Vec(numStages, new MicroOp()))\n\n // handle incoming request\n r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill\n r_uops(0) := io.req.bits.uop\n r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n\n // handle middle of the pipeline\n for (i <- 1 until numStages) {\n r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill\n r_uops(i) := r_uops(i-1)\n r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))\n\n if (numBypassStages > 0) {\n io.bypass(i-1).bits.uop := r_uops(i-1)\n }\n }\n\n // handle outgoing (branch could still kill it)\n // consumer must also check for pipeline flushes (kills)\n io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := r_uops(numStages-1)\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))\n\n // bypassing (TODO allow bypass vector to have a different size from numStages)\n if (numBypassStages > 0 && earliestBypassStage == 0) {\n io.bypass(0).bits.uop := io.req.bits.uop\n\n for (i <- 1 until numBypassStages) {\n io.bypass(i).bits.uop := r_uops(i-1)\n }\n }\n } else {\n require (numStages == 0)\n // pass req straight through to response\n\n // valid doesn't check kill signals, let consumer deal with it.\n // The LSU already handles it and this hurts critical path.\n io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := io.req.bits.uop\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n }\n}\n\n/**\n * Functional unit that wraps RocketChips ALU\n *\n * @param isBranchUnit is this a branch unit?\n * @param numStages how many pipeline stages does the functional unit have\n * @param dataWidth width of the data being operated on in the functional unit\n */\nclass ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = numStages,\n isAluUnit = true,\n earliestBypassStage = 0,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit)\n with boom.v3.ifu.HasBoomFrontendParameters\n{\n val uop = io.req.bits.uop\n\n // immediate generation\n val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)\n\n // operand 1 select\n var op1_data: UInt = null\n if (isJmpUnit) {\n // Get the uop PC for jumps\n val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)\n val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)\n\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),\n 0.U))\n } else {\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n 0.U)\n }\n\n // operand 2 select\n val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),\n Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),\n Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,\n Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),\n 0.U))))\n\n val alu = Module(new freechips.rocketchip.rocket.ALU())\n\n alu.io.in1 := op1_data.asUInt\n alu.io.in2 := op2_data.asUInt\n alu.io.fn := uop.ctrl.op_fcn\n alu.io.dw := uop.ctrl.fcn_dw\n\n\n // Did I just get killed by the previous cycle's branch,\n // or by a flush pipeline?\n val killed = WireInit(false.B)\n when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {\n killed := true.B\n }\n\n val rs1 = io.req.bits.rs1_data\n val rs2 = io.req.bits.rs2_data\n val br_eq = (rs1 === rs2)\n val br_ltu = (rs1.asUInt < rs2.asUInt)\n val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |\n rs1(xLen-1) & ~rs2(xLen-1)).asBool\n\n val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(\n Seq( BR_N -> PC_PLUS4,\n BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),\n BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),\n BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),\n BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),\n BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),\n BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),\n BR_J -> PC_BRJMP,\n BR_JR -> PC_JALR\n ))\n\n val is_taken = io.req.valid &&\n !killed &&\n (uop.is_br || uop.is_jalr || uop.is_jal) &&\n (pc_sel =/= PC_PLUS4)\n\n // \"mispredict\" means that a branch has been resolved and it must be killed\n val mispredict = WireInit(false.B)\n\n val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb\n val is_jal = io.req.valid && !killed && uop.is_jal\n val is_jalr = io.req.valid && !killed && uop.is_jalr\n\n when (is_br || is_jalr) {\n if (!isJmpUnit) {\n assert (pc_sel =/= PC_JALR)\n }\n when (pc_sel === PC_PLUS4) {\n mispredict := uop.taken\n }\n when (pc_sel === PC_BRJMP) {\n mispredict := !uop.taken\n }\n }\n\n val brinfo = Wire(new BrResolutionInfo)\n\n // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit\n brinfo.valid := is_br || is_jalr\n brinfo.mispredict := mispredict\n brinfo.uop := uop\n brinfo.cfi_type := Mux(is_jalr, CFI_JALR,\n Mux(is_br , CFI_BR, CFI_X))\n brinfo.taken := is_taken\n brinfo.pc_sel := pc_sel\n\n brinfo.jalr_target := DontCare\n\n\n // Branch/Jump Target Calculation\n // For jumps we read the FTQ, and can calculate the target\n // For branches we emit the offset for the core to redirect if necessary\n val target_offset = imm_xprlen(20,0).asSInt\n brinfo.jalr_target := DontCare\n if (isJmpUnit) {\n def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {\n ea\n } else {\n // Efficient means to compress 64-bit VA into vaddrBits+1 bits.\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).\n val a = a0.asSInt >> vaddrBits\n val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))\n Cat(msb, ea(vaddrBits-1,0))\n }\n\n\n val jalr_target_base = io.req.bits.rs1_data.asSInt\n val jalr_target_xlen = Wire(UInt(xLen.W))\n jalr_target_xlen := (jalr_target_base + target_offset).asUInt\n val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt\n\n brinfo.jalr_target := jalr_target\n val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)\n\n when (pc_sel === PC_JALR) {\n mispredict := !io.get_ftq_pc.next_val ||\n (io.get_ftq_pc.next_pc =/= jalr_target) ||\n !io.get_ftq_pc.entry.cfi_idx.valid ||\n (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)\n }\n }\n\n brinfo.target_offset := target_offset\n\n\n io.brinfo := brinfo\n\n\n\n// Response\n// TODO add clock gate on resp bits from functional units\n// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)\n// val reg_data = Reg(outType = Bits(width = xLen))\n// reg_data := alu.io.out\n// io.resp.bits.data := reg_data\n\n val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_data = Reg(Vec(numStages, UInt(xLen.W)))\n val r_pred = Reg(Vec(numStages, Bool()))\n val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,\n Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),\n Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))\n r_val (0) := io.req.valid\n r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data\n for (i <- 1 until numStages) {\n r_val(i) := r_val(i-1)\n r_data(i) := r_data(i-1)\n r_pred(i) := r_pred(i-1)\n }\n io.resp.bits.data := r_data(numStages-1)\n io.resp.bits.predicated := r_pred(numStages-1)\n // Bypass\n // for the ALU, we can bypass same cycle as compute\n require (numStages >= 1)\n require (numBypassStages >= 1)\n io.bypass(0).valid := io.req.valid\n io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n for (i <- 1 until numStages) {\n io.bypass(i).valid := r_val(i-1)\n io.bypass(i).bits.data := r_data(i-1)\n }\n\n // Exceptions\n io.resp.bits.fflags.valid := false.B\n}\n\n/**\n * Functional unit that passes in base+imm to calculate addresses, and passes store data\n * to the LSU.\n * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form\n */\nclass MemAddrCalcUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = 0,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65, // TODO enable this only if FP is enabled?\n isMemAddrCalcUnit = true)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n with freechips.rocketchip.rocket.constants.ScalarOpConstants\n{\n // perform address calculation\n val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt\n val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,\n sum(63,vaddrBits) =/= 0.U)\n val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt\n\n val store_data = io.req.bits.rs2_data\n\n io.resp.bits.addr := effective_address\n io.resp.bits.data := store_data\n\n if (dataWidth > 63) {\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&\n io.resp.bits.data(64).asBool === true.B), \"65th bit set in MemAddrCalcUnit.\")\n\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),\n \"FP store-data should now be going through a different unit.\")\n }\n\n assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=\n uopLD && io.req.bits.uop.uopc =/= uopSTA),\n \"[maddrcalc] assert we never get store data in here.\")\n\n // Handle misaligned exceptions\n val size = io.req.bits.uop.mem_size\n val misaligned =\n (size === 1.U && (effective_address(0) =/= 0.U)) ||\n (size === 2.U && (effective_address(1,0) =/= 0.U)) ||\n (size === 3.U && (effective_address(2,0) =/= 0.U))\n\n val bkptu = Module(new BreakpointUnit(nBreakpoints))\n bkptu.io.status := io.status\n bkptu.io.bp := io.bp\n bkptu.io.pc := DontCare\n bkptu.io.ea := effective_address\n bkptu.io.mcontext := io.mcontext\n bkptu.io.scontext := io.scontext\n\n val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned\n val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned\n val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))\n val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n val (xcpt_val, xcpt_cause) = checkExceptions(List(\n (ma_ld, (Causes.misaligned_load).U),\n (ma_st, (Causes.misaligned_store).U),\n (dbg_bp, (CSR.debugTriggerCause).U),\n (bp, (Causes.breakpoint).U)))\n\n io.resp.bits.mxcpt.valid := xcpt_val\n io.resp.bits.mxcpt.bits := xcpt_cause\n assert (!(ma_ld && ma_st), \"Mutually-exclusive exceptions are firing.\")\n\n io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE\n io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)\n io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)\n io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data\n io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data\n}\n\n\n/**\n * Functional unit to wrap lower level FPU\n *\n * Currently, bypassing is unsupported!\n * All FP instructions are padded out to the max latency unit for easy\n * write-port scheduling.\n */\nclass FPUUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n{\n val fpu = Module(new FPU())\n fpu.io.req.valid := io.req.valid\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.fcsr_rm := io.fcsr_rm\n\n io.resp.bits.data := fpu.io.resp.bits.data\n io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now\n}\n\n/**\n * Int to FP conversion functional unit\n *\n * @param latency the amount of stages to delay by\n */\nclass IntToFPUnit(latency: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = latency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n with tile.HasFPUParameters\n{\n val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder\n val io_req = io.req.bits\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, None)\n req.in2 := unbox(io_req.rs2_data, tag, None)\n req.in3 := DontCare\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := DontCare // FIXME: this may not be the right thing to do here\n req.fmaCmd := DontCare\n\n assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n \"[func] IntToFP integer input has 65th high-order bit set!\")\n\n assert (!(io.req.valid && !fp_ctrl.fromint),\n \"[func] Only support fromInt micro-ops.\")\n\n val ifpu = Module(new tile.IntToFP(intToFpLatency))\n ifpu.io.in.valid := io.req.valid\n ifpu.io.in.bits := req\n ifpu.io.in.bits.in1 := io_req.rs1_data\n val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits\n\n//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)\n io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)\n io.resp.bits.fflags.valid := ifpu.io.out.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc\n}\n\n/**\n * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time\n * assumes at least one register between request and response\n *\n * TODO allow up to N micro-ops simultaneously.\n *\n * @param dataWidth width of the data to be passed into the functional unit\n */\nabstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)\n extends FunctionalUnit(\n isPipelined = false,\n numStages = 1,\n numBypassStages = 0,\n dataWidth = dataWidth)\n{\n val r_uop = Reg(new MicroOp())\n\n val do_kill = Wire(Bool())\n do_kill := io.req.bits.kill // irrelevant default\n\n when (io.req.fire) {\n // update incoming uop\n do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill\n r_uop := io.req.bits.uop\n r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n } .otherwise {\n do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill\n r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)\n }\n\n // assumes at least one pipeline register between request and response\n io.resp.bits.uop := r_uop\n}\n\n/**\n * Divide functional unit.\n *\n * @param dataWidth data to be passed into the functional unit\n */\nclass DivUnit(dataWidth: Int)(implicit p: Parameters)\n extends IterativeFunctionalUnit(dataWidth)\n{\n\n // We don't use the iterative multiply functionality here.\n // Instead we use the PipelinedMultiplier\n val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))\n\n // request\n div.io.req.valid := io.req.valid && !this.do_kill\n div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n div.io.req.bits.in1 := io.req.bits.rs1_data\n div.io.req.bits.in2 := io.req.bits.rs2_data\n div.io.req.bits.tag := DontCare\n io.req.ready := div.io.req.ready\n\n // handle pipeline kills and branch misspeculations\n div.io.kill := this.do_kill\n\n // response\n io.resp.valid := div.io.resp.valid && !this.do_kill\n div.io.resp.ready := io.resp.ready\n io.resp.bits.data := div.io.resp.bits.data\n}\n\n/**\n * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier\n *\n * @param numStages number of pipeline stages\n * @param dataWidth size of the data being passed into the functional unit\n */\nclass PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = dataWidth)\n{\n val imul = Module(new PipelinedMultiplier(xLen, numStages))\n // request\n imul.io.req.valid := io.req.valid\n imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n imul.io.req.bits.in1 := io.req.bits.rs1_data\n imul.io.req.bits.in2 := io.req.bits.rs2_data\n imul.io.req.bits.tag := DontCare\n // response\n io.resp.bits.data := imul.io.resp.bits.data\n}", + "response": "module FPUUnit(\n input clock,\n input reset,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_iw_p1_poisoned,\n input io_req_bits_uop_iw_p2_poisoned,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [64:0] io_req_bits_rs1_data,\n input [64:0] io_req_bits_rs2_data,\n input [64:0] io_req_bits_rs3_data,\n input io_req_bits_kill,\n output io_resp_valid,\n output [6:0] io_resp_bits_uop_uopc,\n output [31:0] io_resp_bits_uop_inst,\n output [31:0] io_resp_bits_uop_debug_inst,\n output io_resp_bits_uop_is_rvc,\n output [39:0] io_resp_bits_uop_debug_pc,\n output [2:0] io_resp_bits_uop_iq_type,\n output [9:0] io_resp_bits_uop_fu_code,\n output [3:0] io_resp_bits_uop_ctrl_br_type,\n output [1:0] io_resp_bits_uop_ctrl_op1_sel,\n output [2:0] io_resp_bits_uop_ctrl_op2_sel,\n output [2:0] io_resp_bits_uop_ctrl_imm_sel,\n output [4:0] io_resp_bits_uop_ctrl_op_fcn,\n output io_resp_bits_uop_ctrl_fcn_dw,\n output [2:0] io_resp_bits_uop_ctrl_csr_cmd,\n output io_resp_bits_uop_ctrl_is_load,\n output io_resp_bits_uop_ctrl_is_sta,\n output io_resp_bits_uop_ctrl_is_std,\n output [1:0] io_resp_bits_uop_iw_state,\n output io_resp_bits_uop_iw_p1_poisoned,\n output io_resp_bits_uop_iw_p2_poisoned,\n output io_resp_bits_uop_is_br,\n output io_resp_bits_uop_is_jalr,\n output io_resp_bits_uop_is_jal,\n output io_resp_bits_uop_is_sfb,\n output [7:0] io_resp_bits_uop_br_mask,\n output [2:0] io_resp_bits_uop_br_tag,\n output [3:0] io_resp_bits_uop_ftq_idx,\n output io_resp_bits_uop_edge_inst,\n output [5:0] io_resp_bits_uop_pc_lob,\n output io_resp_bits_uop_taken,\n output [19:0] io_resp_bits_uop_imm_packed,\n output [11:0] io_resp_bits_uop_csr_addr,\n output [4:0] io_resp_bits_uop_rob_idx,\n output [2:0] io_resp_bits_uop_ldq_idx,\n output [2:0] io_resp_bits_uop_stq_idx,\n output [1:0] io_resp_bits_uop_rxq_idx,\n output [5:0] io_resp_bits_uop_pdst,\n output [5:0] io_resp_bits_uop_prs1,\n output [5:0] io_resp_bits_uop_prs2,\n output [5:0] io_resp_bits_uop_prs3,\n output [3:0] io_resp_bits_uop_ppred,\n output io_resp_bits_uop_prs1_busy,\n output io_resp_bits_uop_prs2_busy,\n output io_resp_bits_uop_prs3_busy,\n output io_resp_bits_uop_ppred_busy,\n output [5:0] io_resp_bits_uop_stale_pdst,\n output io_resp_bits_uop_exception,\n output [63:0] io_resp_bits_uop_exc_cause,\n output io_resp_bits_uop_bypassable,\n output [4:0] io_resp_bits_uop_mem_cmd,\n output [1:0] io_resp_bits_uop_mem_size,\n output io_resp_bits_uop_mem_signed,\n output io_resp_bits_uop_is_fence,\n output io_resp_bits_uop_is_fencei,\n output io_resp_bits_uop_is_amo,\n output io_resp_bits_uop_uses_ldq,\n output io_resp_bits_uop_uses_stq,\n output io_resp_bits_uop_is_sys_pc2epc,\n output io_resp_bits_uop_is_unique,\n output io_resp_bits_uop_flush_on_commit,\n output io_resp_bits_uop_ldst_is_rs1,\n output [5:0] io_resp_bits_uop_ldst,\n output [5:0] io_resp_bits_uop_lrs1,\n output [5:0] io_resp_bits_uop_lrs2,\n output [5:0] io_resp_bits_uop_lrs3,\n output io_resp_bits_uop_ldst_val,\n output [1:0] io_resp_bits_uop_dst_rtype,\n output [1:0] io_resp_bits_uop_lrs1_rtype,\n output [1:0] io_resp_bits_uop_lrs2_rtype,\n output io_resp_bits_uop_frs3_en,\n output io_resp_bits_uop_fp_val,\n output io_resp_bits_uop_fp_single,\n output io_resp_bits_uop_xcpt_pf_if,\n output io_resp_bits_uop_xcpt_ae_if,\n output io_resp_bits_uop_xcpt_ma_if,\n output io_resp_bits_uop_bp_debug_if,\n output io_resp_bits_uop_bp_xcpt_if,\n output [1:0] io_resp_bits_uop_debug_fsrc,\n output [1:0] io_resp_bits_uop_debug_tsrc,\n output [64:0] io_resp_bits_data,\n output io_resp_bits_fflags_valid,\n output [6:0] io_resp_bits_fflags_bits_uop_uopc,\n output [31:0] io_resp_bits_fflags_bits_uop_inst,\n output [31:0] io_resp_bits_fflags_bits_uop_debug_inst,\n output io_resp_bits_fflags_bits_uop_is_rvc,\n output [39:0] io_resp_bits_fflags_bits_uop_debug_pc,\n output [2:0] io_resp_bits_fflags_bits_uop_iq_type,\n output [9:0] io_resp_bits_fflags_bits_uop_fu_code,\n output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type,\n output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel,\n output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel,\n output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel,\n output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn,\n output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw,\n output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd,\n output io_resp_bits_fflags_bits_uop_ctrl_is_load,\n output io_resp_bits_fflags_bits_uop_ctrl_is_sta,\n output io_resp_bits_fflags_bits_uop_ctrl_is_std,\n output [1:0] io_resp_bits_fflags_bits_uop_iw_state,\n output io_resp_bits_fflags_bits_uop_iw_p1_poisoned,\n output io_resp_bits_fflags_bits_uop_iw_p2_poisoned,\n output io_resp_bits_fflags_bits_uop_is_br,\n output io_resp_bits_fflags_bits_uop_is_jalr,\n output io_resp_bits_fflags_bits_uop_is_jal,\n output io_resp_bits_fflags_bits_uop_is_sfb,\n output [7:0] io_resp_bits_fflags_bits_uop_br_mask,\n output [2:0] io_resp_bits_fflags_bits_uop_br_tag,\n output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx,\n output io_resp_bits_fflags_bits_uop_edge_inst,\n output [5:0] io_resp_bits_fflags_bits_uop_pc_lob,\n output io_resp_bits_fflags_bits_uop_taken,\n output [19:0] io_resp_bits_fflags_bits_uop_imm_packed,\n output [11:0] io_resp_bits_fflags_bits_uop_csr_addr,\n output [4:0] io_resp_bits_fflags_bits_uop_rob_idx,\n output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx,\n output [2:0] io_resp_bits_fflags_bits_uop_stq_idx,\n output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx,\n output [5:0] io_resp_bits_fflags_bits_uop_pdst,\n output [5:0] io_resp_bits_fflags_bits_uop_prs1,\n output [5:0] io_resp_bits_fflags_bits_uop_prs2,\n output [5:0] io_resp_bits_fflags_bits_uop_prs3,\n output [3:0] io_resp_bits_fflags_bits_uop_ppred,\n output io_resp_bits_fflags_bits_uop_prs1_busy,\n output io_resp_bits_fflags_bits_uop_prs2_busy,\n output io_resp_bits_fflags_bits_uop_prs3_busy,\n output io_resp_bits_fflags_bits_uop_ppred_busy,\n output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst,\n output io_resp_bits_fflags_bits_uop_exception,\n output [63:0] io_resp_bits_fflags_bits_uop_exc_cause,\n output io_resp_bits_fflags_bits_uop_bypassable,\n output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd,\n output [1:0] io_resp_bits_fflags_bits_uop_mem_size,\n output io_resp_bits_fflags_bits_uop_mem_signed,\n output io_resp_bits_fflags_bits_uop_is_fence,\n output io_resp_bits_fflags_bits_uop_is_fencei,\n output io_resp_bits_fflags_bits_uop_is_amo,\n output io_resp_bits_fflags_bits_uop_uses_ldq,\n output io_resp_bits_fflags_bits_uop_uses_stq,\n output io_resp_bits_fflags_bits_uop_is_sys_pc2epc,\n output io_resp_bits_fflags_bits_uop_is_unique,\n output io_resp_bits_fflags_bits_uop_flush_on_commit,\n output io_resp_bits_fflags_bits_uop_ldst_is_rs1,\n output [5:0] io_resp_bits_fflags_bits_uop_ldst,\n output [5:0] io_resp_bits_fflags_bits_uop_lrs1,\n output [5:0] io_resp_bits_fflags_bits_uop_lrs2,\n output [5:0] io_resp_bits_fflags_bits_uop_lrs3,\n output io_resp_bits_fflags_bits_uop_ldst_val,\n output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype,\n output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype,\n output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype,\n output io_resp_bits_fflags_bits_uop_frs3_en,\n output io_resp_bits_fflags_bits_uop_fp_val,\n output io_resp_bits_fflags_bits_uop_fp_single,\n output io_resp_bits_fflags_bits_uop_xcpt_pf_if,\n output io_resp_bits_fflags_bits_uop_xcpt_ae_if,\n output io_resp_bits_fflags_bits_uop_xcpt_ma_if,\n output io_resp_bits_fflags_bits_uop_bp_debug_if,\n output io_resp_bits_fflags_bits_uop_bp_xcpt_if,\n output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc,\n output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc,\n output [4:0] io_resp_bits_fflags_bits_flags,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input [2:0] io_fcsr_rm\n);\n\n reg r_valids_0;\n reg r_valids_1;\n reg r_valids_2;\n reg r_valids_3;\n reg [6:0] r_uops_0_uopc;\n reg [31:0] r_uops_0_inst;\n reg [31:0] r_uops_0_debug_inst;\n reg r_uops_0_is_rvc;\n reg [39:0] r_uops_0_debug_pc;\n reg [2:0] r_uops_0_iq_type;\n reg [9:0] r_uops_0_fu_code;\n reg [3:0] r_uops_0_ctrl_br_type;\n reg [1:0] r_uops_0_ctrl_op1_sel;\n reg [2:0] r_uops_0_ctrl_op2_sel;\n reg [2:0] r_uops_0_ctrl_imm_sel;\n reg [4:0] r_uops_0_ctrl_op_fcn;\n reg r_uops_0_ctrl_fcn_dw;\n reg [2:0] r_uops_0_ctrl_csr_cmd;\n reg r_uops_0_ctrl_is_load;\n reg r_uops_0_ctrl_is_sta;\n reg r_uops_0_ctrl_is_std;\n reg [1:0] r_uops_0_iw_state;\n reg r_uops_0_iw_p1_poisoned;\n reg r_uops_0_iw_p2_poisoned;\n reg r_uops_0_is_br;\n reg r_uops_0_is_jalr;\n reg r_uops_0_is_jal;\n reg r_uops_0_is_sfb;\n reg [7:0] r_uops_0_br_mask;\n reg [2:0] r_uops_0_br_tag;\n reg [3:0] r_uops_0_ftq_idx;\n reg r_uops_0_edge_inst;\n reg [5:0] r_uops_0_pc_lob;\n reg r_uops_0_taken;\n reg [19:0] r_uops_0_imm_packed;\n reg [11:0] r_uops_0_csr_addr;\n reg [4:0] r_uops_0_rob_idx;\n reg [2:0] r_uops_0_ldq_idx;\n reg [2:0] r_uops_0_stq_idx;\n reg [1:0] r_uops_0_rxq_idx;\n reg [5:0] r_uops_0_pdst;\n reg [5:0] r_uops_0_prs1;\n reg [5:0] r_uops_0_prs2;\n reg [5:0] r_uops_0_prs3;\n reg [3:0] r_uops_0_ppred;\n reg r_uops_0_prs1_busy;\n reg r_uops_0_prs2_busy;\n reg r_uops_0_prs3_busy;\n reg r_uops_0_ppred_busy;\n reg [5:0] r_uops_0_stale_pdst;\n reg r_uops_0_exception;\n reg [63:0] r_uops_0_exc_cause;\n reg r_uops_0_bypassable;\n reg [4:0] r_uops_0_mem_cmd;\n reg [1:0] r_uops_0_mem_size;\n reg r_uops_0_mem_signed;\n reg r_uops_0_is_fence;\n reg r_uops_0_is_fencei;\n reg r_uops_0_is_amo;\n reg r_uops_0_uses_ldq;\n reg r_uops_0_uses_stq;\n reg r_uops_0_is_sys_pc2epc;\n reg r_uops_0_is_unique;\n reg r_uops_0_flush_on_commit;\n reg r_uops_0_ldst_is_rs1;\n reg [5:0] r_uops_0_ldst;\n reg [5:0] r_uops_0_lrs1;\n reg [5:0] r_uops_0_lrs2;\n reg [5:0] r_uops_0_lrs3;\n reg r_uops_0_ldst_val;\n reg [1:0] r_uops_0_dst_rtype;\n reg [1:0] r_uops_0_lrs1_rtype;\n reg [1:0] r_uops_0_lrs2_rtype;\n reg r_uops_0_frs3_en;\n reg r_uops_0_fp_val;\n reg r_uops_0_fp_single;\n reg r_uops_0_xcpt_pf_if;\n reg r_uops_0_xcpt_ae_if;\n reg r_uops_0_xcpt_ma_if;\n reg r_uops_0_bp_debug_if;\n reg r_uops_0_bp_xcpt_if;\n reg [1:0] r_uops_0_debug_fsrc;\n reg [1:0] r_uops_0_debug_tsrc;\n reg [6:0] r_uops_1_uopc;\n reg [31:0] r_uops_1_inst;\n reg [31:0] r_uops_1_debug_inst;\n reg r_uops_1_is_rvc;\n reg [39:0] r_uops_1_debug_pc;\n reg [2:0] r_uops_1_iq_type;\n reg [9:0] r_uops_1_fu_code;\n reg [3:0] r_uops_1_ctrl_br_type;\n reg [1:0] r_uops_1_ctrl_op1_sel;\n reg [2:0] r_uops_1_ctrl_op2_sel;\n reg [2:0] r_uops_1_ctrl_imm_sel;\n reg [4:0] r_uops_1_ctrl_op_fcn;\n reg r_uops_1_ctrl_fcn_dw;\n reg [2:0] r_uops_1_ctrl_csr_cmd;\n reg r_uops_1_ctrl_is_load;\n reg r_uops_1_ctrl_is_sta;\n reg r_uops_1_ctrl_is_std;\n reg [1:0] r_uops_1_iw_state;\n reg r_uops_1_iw_p1_poisoned;\n reg r_uops_1_iw_p2_poisoned;\n reg r_uops_1_is_br;\n reg r_uops_1_is_jalr;\n reg r_uops_1_is_jal;\n reg r_uops_1_is_sfb;\n reg [7:0] r_uops_1_br_mask;\n reg [2:0] r_uops_1_br_tag;\n reg [3:0] r_uops_1_ftq_idx;\n reg r_uops_1_edge_inst;\n reg [5:0] r_uops_1_pc_lob;\n reg r_uops_1_taken;\n reg [19:0] r_uops_1_imm_packed;\n reg [11:0] r_uops_1_csr_addr;\n reg [4:0] r_uops_1_rob_idx;\n reg [2:0] r_uops_1_ldq_idx;\n reg [2:0] r_uops_1_stq_idx;\n reg [1:0] r_uops_1_rxq_idx;\n reg [5:0] r_uops_1_pdst;\n reg [5:0] r_uops_1_prs1;\n reg [5:0] r_uops_1_prs2;\n reg [5:0] r_uops_1_prs3;\n reg [3:0] r_uops_1_ppred;\n reg r_uops_1_prs1_busy;\n reg r_uops_1_prs2_busy;\n reg r_uops_1_prs3_busy;\n reg r_uops_1_ppred_busy;\n reg [5:0] r_uops_1_stale_pdst;\n reg r_uops_1_exception;\n reg [63:0] r_uops_1_exc_cause;\n reg r_uops_1_bypassable;\n reg [4:0] r_uops_1_mem_cmd;\n reg [1:0] r_uops_1_mem_size;\n reg r_uops_1_mem_signed;\n reg r_uops_1_is_fence;\n reg r_uops_1_is_fencei;\n reg r_uops_1_is_amo;\n reg r_uops_1_uses_ldq;\n reg r_uops_1_uses_stq;\n reg r_uops_1_is_sys_pc2epc;\n reg r_uops_1_is_unique;\n reg r_uops_1_flush_on_commit;\n reg r_uops_1_ldst_is_rs1;\n reg [5:0] r_uops_1_ldst;\n reg [5:0] r_uops_1_lrs1;\n reg [5:0] r_uops_1_lrs2;\n reg [5:0] r_uops_1_lrs3;\n reg r_uops_1_ldst_val;\n reg [1:0] r_uops_1_dst_rtype;\n reg [1:0] r_uops_1_lrs1_rtype;\n reg [1:0] r_uops_1_lrs2_rtype;\n reg r_uops_1_frs3_en;\n reg r_uops_1_fp_val;\n reg r_uops_1_fp_single;\n reg r_uops_1_xcpt_pf_if;\n reg r_uops_1_xcpt_ae_if;\n reg r_uops_1_xcpt_ma_if;\n reg r_uops_1_bp_debug_if;\n reg r_uops_1_bp_xcpt_if;\n reg [1:0] r_uops_1_debug_fsrc;\n reg [1:0] r_uops_1_debug_tsrc;\n reg [6:0] r_uops_2_uopc;\n reg [31:0] r_uops_2_inst;\n reg [31:0] r_uops_2_debug_inst;\n reg r_uops_2_is_rvc;\n reg [39:0] r_uops_2_debug_pc;\n reg [2:0] r_uops_2_iq_type;\n reg [9:0] r_uops_2_fu_code;\n reg [3:0] r_uops_2_ctrl_br_type;\n reg [1:0] r_uops_2_ctrl_op1_sel;\n reg [2:0] r_uops_2_ctrl_op2_sel;\n reg [2:0] r_uops_2_ctrl_imm_sel;\n reg [4:0] r_uops_2_ctrl_op_fcn;\n reg r_uops_2_ctrl_fcn_dw;\n reg [2:0] r_uops_2_ctrl_csr_cmd;\n reg r_uops_2_ctrl_is_load;\n reg r_uops_2_ctrl_is_sta;\n reg r_uops_2_ctrl_is_std;\n reg [1:0] r_uops_2_iw_state;\n reg r_uops_2_iw_p1_poisoned;\n reg r_uops_2_iw_p2_poisoned;\n reg r_uops_2_is_br;\n reg r_uops_2_is_jalr;\n reg r_uops_2_is_jal;\n reg r_uops_2_is_sfb;\n reg [7:0] r_uops_2_br_mask;\n reg [2:0] r_uops_2_br_tag;\n reg [3:0] r_uops_2_ftq_idx;\n reg r_uops_2_edge_inst;\n reg [5:0] r_uops_2_pc_lob;\n reg r_uops_2_taken;\n reg [19:0] r_uops_2_imm_packed;\n reg [11:0] r_uops_2_csr_addr;\n reg [4:0] r_uops_2_rob_idx;\n reg [2:0] r_uops_2_ldq_idx;\n reg [2:0] r_uops_2_stq_idx;\n reg [1:0] r_uops_2_rxq_idx;\n reg [5:0] r_uops_2_pdst;\n reg [5:0] r_uops_2_prs1;\n reg [5:0] r_uops_2_prs2;\n reg [5:0] r_uops_2_prs3;\n reg [3:0] r_uops_2_ppred;\n reg r_uops_2_prs1_busy;\n reg r_uops_2_prs2_busy;\n reg r_uops_2_prs3_busy;\n reg r_uops_2_ppred_busy;\n reg [5:0] r_uops_2_stale_pdst;\n reg r_uops_2_exception;\n reg [63:0] r_uops_2_exc_cause;\n reg r_uops_2_bypassable;\n reg [4:0] r_uops_2_mem_cmd;\n reg [1:0] r_uops_2_mem_size;\n reg r_uops_2_mem_signed;\n reg r_uops_2_is_fence;\n reg r_uops_2_is_fencei;\n reg r_uops_2_is_amo;\n reg r_uops_2_uses_ldq;\n reg r_uops_2_uses_stq;\n reg r_uops_2_is_sys_pc2epc;\n reg r_uops_2_is_unique;\n reg r_uops_2_flush_on_commit;\n reg r_uops_2_ldst_is_rs1;\n reg [5:0] r_uops_2_ldst;\n reg [5:0] r_uops_2_lrs1;\n reg [5:0] r_uops_2_lrs2;\n reg [5:0] r_uops_2_lrs3;\n reg r_uops_2_ldst_val;\n reg [1:0] r_uops_2_dst_rtype;\n reg [1:0] r_uops_2_lrs1_rtype;\n reg [1:0] r_uops_2_lrs2_rtype;\n reg r_uops_2_frs3_en;\n reg r_uops_2_fp_val;\n reg r_uops_2_fp_single;\n reg r_uops_2_xcpt_pf_if;\n reg r_uops_2_xcpt_ae_if;\n reg r_uops_2_xcpt_ma_if;\n reg r_uops_2_bp_debug_if;\n reg r_uops_2_bp_xcpt_if;\n reg [1:0] r_uops_2_debug_fsrc;\n reg [1:0] r_uops_2_debug_tsrc;\n reg [6:0] r_uops_3_uopc;\n reg [31:0] r_uops_3_inst;\n reg [31:0] r_uops_3_debug_inst;\n reg r_uops_3_is_rvc;\n reg [39:0] r_uops_3_debug_pc;\n reg [2:0] r_uops_3_iq_type;\n reg [9:0] r_uops_3_fu_code;\n reg [3:0] r_uops_3_ctrl_br_type;\n reg [1:0] r_uops_3_ctrl_op1_sel;\n reg [2:0] r_uops_3_ctrl_op2_sel;\n reg [2:0] r_uops_3_ctrl_imm_sel;\n reg [4:0] r_uops_3_ctrl_op_fcn;\n reg r_uops_3_ctrl_fcn_dw;\n reg [2:0] r_uops_3_ctrl_csr_cmd;\n reg r_uops_3_ctrl_is_load;\n reg r_uops_3_ctrl_is_sta;\n reg r_uops_3_ctrl_is_std;\n reg [1:0] r_uops_3_iw_state;\n reg r_uops_3_iw_p1_poisoned;\n reg r_uops_3_iw_p2_poisoned;\n reg r_uops_3_is_br;\n reg r_uops_3_is_jalr;\n reg r_uops_3_is_jal;\n reg r_uops_3_is_sfb;\n reg [7:0] r_uops_3_br_mask;\n reg [2:0] r_uops_3_br_tag;\n reg [3:0] r_uops_3_ftq_idx;\n reg r_uops_3_edge_inst;\n reg [5:0] r_uops_3_pc_lob;\n reg r_uops_3_taken;\n reg [19:0] r_uops_3_imm_packed;\n reg [11:0] r_uops_3_csr_addr;\n reg [4:0] r_uops_3_rob_idx;\n reg [2:0] r_uops_3_ldq_idx;\n reg [2:0] r_uops_3_stq_idx;\n reg [1:0] r_uops_3_rxq_idx;\n reg [5:0] r_uops_3_pdst;\n reg [5:0] r_uops_3_prs1;\n reg [5:0] r_uops_3_prs2;\n reg [5:0] r_uops_3_prs3;\n reg [3:0] r_uops_3_ppred;\n reg r_uops_3_prs1_busy;\n reg r_uops_3_prs2_busy;\n reg r_uops_3_prs3_busy;\n reg r_uops_3_ppred_busy;\n reg [5:0] r_uops_3_stale_pdst;\n reg r_uops_3_exception;\n reg [63:0] r_uops_3_exc_cause;\n reg r_uops_3_bypassable;\n reg [4:0] r_uops_3_mem_cmd;\n reg [1:0] r_uops_3_mem_size;\n reg r_uops_3_mem_signed;\n reg r_uops_3_is_fence;\n reg r_uops_3_is_fencei;\n reg r_uops_3_is_amo;\n reg r_uops_3_uses_ldq;\n reg r_uops_3_uses_stq;\n reg r_uops_3_is_sys_pc2epc;\n reg r_uops_3_is_unique;\n reg r_uops_3_flush_on_commit;\n reg r_uops_3_ldst_is_rs1;\n reg [5:0] r_uops_3_ldst;\n reg [5:0] r_uops_3_lrs1;\n reg [5:0] r_uops_3_lrs2;\n reg [5:0] r_uops_3_lrs3;\n reg r_uops_3_ldst_val;\n reg [1:0] r_uops_3_dst_rtype;\n reg [1:0] r_uops_3_lrs1_rtype;\n reg [1:0] r_uops_3_lrs2_rtype;\n reg r_uops_3_frs3_en;\n reg r_uops_3_fp_val;\n reg r_uops_3_fp_single;\n reg r_uops_3_xcpt_pf_if;\n reg r_uops_3_xcpt_ae_if;\n reg r_uops_3_xcpt_ma_if;\n reg r_uops_3_bp_debug_if;\n reg r_uops_3_bp_xcpt_if;\n reg [1:0] r_uops_3_debug_fsrc;\n reg [1:0] r_uops_3_debug_tsrc;\n wire [7:0] io_resp_bits_uop_br_mask_0 = r_uops_3_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n r_valids_0 <= 1'h0;\n r_valids_1 <= 1'h0;\n r_valids_2 <= 1'h0;\n r_valids_3 <= 1'h0;\n end\n else begin\n r_valids_0 <= io_req_valid & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0 & ~io_req_bits_kill;\n r_valids_1 <= r_valids_0 & (io_brupdate_b1_mispredict_mask & r_uops_0_br_mask) == 8'h0 & ~io_req_bits_kill;\n r_valids_2 <= r_valids_1 & (io_brupdate_b1_mispredict_mask & r_uops_1_br_mask) == 8'h0 & ~io_req_bits_kill;\n r_valids_3 <= r_valids_2 & (io_brupdate_b1_mispredict_mask & r_uops_2_br_mask) == 8'h0 & ~io_req_bits_kill;\n end\n r_uops_0_uopc <= io_req_bits_uop_uopc;\n r_uops_0_inst <= io_req_bits_uop_inst;\n r_uops_0_debug_inst <= io_req_bits_uop_debug_inst;\n r_uops_0_is_rvc <= io_req_bits_uop_is_rvc;\n r_uops_0_debug_pc <= io_req_bits_uop_debug_pc;\n r_uops_0_iq_type <= io_req_bits_uop_iq_type;\n r_uops_0_fu_code <= io_req_bits_uop_fu_code;\n r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type;\n r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel;\n r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel;\n r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel;\n r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn;\n r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw;\n r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd;\n r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load;\n r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta;\n r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std;\n r_uops_0_iw_state <= io_req_bits_uop_iw_state;\n r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned;\n r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned;\n r_uops_0_is_br <= io_req_bits_uop_is_br;\n r_uops_0_is_jalr <= io_req_bits_uop_is_jalr;\n r_uops_0_is_jal <= io_req_bits_uop_is_jal;\n r_uops_0_is_sfb <= io_req_bits_uop_is_sfb;\n r_uops_0_br_mask <= io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_0_br_tag <= io_req_bits_uop_br_tag;\n r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx;\n r_uops_0_edge_inst <= io_req_bits_uop_edge_inst;\n r_uops_0_pc_lob <= io_req_bits_uop_pc_lob;\n r_uops_0_taken <= io_req_bits_uop_taken;\n r_uops_0_imm_packed <= io_req_bits_uop_imm_packed;\n r_uops_0_csr_addr <= io_req_bits_uop_csr_addr;\n r_uops_0_rob_idx <= io_req_bits_uop_rob_idx;\n r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx;\n r_uops_0_stq_idx <= io_req_bits_uop_stq_idx;\n r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx;\n r_uops_0_pdst <= io_req_bits_uop_pdst;\n r_uops_0_prs1 <= io_req_bits_uop_prs1;\n r_uops_0_prs2 <= io_req_bits_uop_prs2;\n r_uops_0_prs3 <= io_req_bits_uop_prs3;\n r_uops_0_ppred <= io_req_bits_uop_ppred;\n r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy;\n r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy;\n r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy;\n r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy;\n r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst;\n r_uops_0_exception <= io_req_bits_uop_exception;\n r_uops_0_exc_cause <= io_req_bits_uop_exc_cause;\n r_uops_0_bypassable <= io_req_bits_uop_bypassable;\n r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd;\n r_uops_0_mem_size <= io_req_bits_uop_mem_size;\n r_uops_0_mem_signed <= io_req_bits_uop_mem_signed;\n r_uops_0_is_fence <= io_req_bits_uop_is_fence;\n r_uops_0_is_fencei <= io_req_bits_uop_is_fencei;\n r_uops_0_is_amo <= io_req_bits_uop_is_amo;\n r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq;\n r_uops_0_uses_stq <= io_req_bits_uop_uses_stq;\n r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc;\n r_uops_0_is_unique <= io_req_bits_uop_is_unique;\n r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit;\n r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1;\n r_uops_0_ldst <= io_req_bits_uop_ldst;\n r_uops_0_lrs1 <= io_req_bits_uop_lrs1;\n r_uops_0_lrs2 <= io_req_bits_uop_lrs2;\n r_uops_0_lrs3 <= io_req_bits_uop_lrs3;\n r_uops_0_ldst_val <= io_req_bits_uop_ldst_val;\n r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype;\n r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype;\n r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype;\n r_uops_0_frs3_en <= io_req_bits_uop_frs3_en;\n r_uops_0_fp_val <= io_req_bits_uop_fp_val;\n r_uops_0_fp_single <= io_req_bits_uop_fp_single;\n r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if;\n r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if;\n r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if;\n r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if;\n r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if;\n r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc;\n r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc;\n r_uops_1_uopc <= r_uops_0_uopc;\n r_uops_1_inst <= r_uops_0_inst;\n r_uops_1_debug_inst <= r_uops_0_debug_inst;\n r_uops_1_is_rvc <= r_uops_0_is_rvc;\n r_uops_1_debug_pc <= r_uops_0_debug_pc;\n r_uops_1_iq_type <= r_uops_0_iq_type;\n r_uops_1_fu_code <= r_uops_0_fu_code;\n r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type;\n r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel;\n r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel;\n r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel;\n r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn;\n r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw;\n r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd;\n r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load;\n r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta;\n r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std;\n r_uops_1_iw_state <= r_uops_0_iw_state;\n r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned;\n r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned;\n r_uops_1_is_br <= r_uops_0_is_br;\n r_uops_1_is_jalr <= r_uops_0_is_jalr;\n r_uops_1_is_jal <= r_uops_0_is_jal;\n r_uops_1_is_sfb <= r_uops_0_is_sfb;\n r_uops_1_br_mask <= r_uops_0_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_1_br_tag <= r_uops_0_br_tag;\n r_uops_1_ftq_idx <= r_uops_0_ftq_idx;\n r_uops_1_edge_inst <= r_uops_0_edge_inst;\n r_uops_1_pc_lob <= r_uops_0_pc_lob;\n r_uops_1_taken <= r_uops_0_taken;\n r_uops_1_imm_packed <= r_uops_0_imm_packed;\n r_uops_1_csr_addr <= r_uops_0_csr_addr;\n r_uops_1_rob_idx <= r_uops_0_rob_idx;\n r_uops_1_ldq_idx <= r_uops_0_ldq_idx;\n r_uops_1_stq_idx <= r_uops_0_stq_idx;\n r_uops_1_rxq_idx <= r_uops_0_rxq_idx;\n r_uops_1_pdst <= r_uops_0_pdst;\n r_uops_1_prs1 <= r_uops_0_prs1;\n r_uops_1_prs2 <= r_uops_0_prs2;\n r_uops_1_prs3 <= r_uops_0_prs3;\n r_uops_1_ppred <= r_uops_0_ppred;\n r_uops_1_prs1_busy <= r_uops_0_prs1_busy;\n r_uops_1_prs2_busy <= r_uops_0_prs2_busy;\n r_uops_1_prs3_busy <= r_uops_0_prs3_busy;\n r_uops_1_ppred_busy <= r_uops_0_ppred_busy;\n r_uops_1_stale_pdst <= r_uops_0_stale_pdst;\n r_uops_1_exception <= r_uops_0_exception;\n r_uops_1_exc_cause <= r_uops_0_exc_cause;\n r_uops_1_bypassable <= r_uops_0_bypassable;\n r_uops_1_mem_cmd <= r_uops_0_mem_cmd;\n r_uops_1_mem_size <= r_uops_0_mem_size;\n r_uops_1_mem_signed <= r_uops_0_mem_signed;\n r_uops_1_is_fence <= r_uops_0_is_fence;\n r_uops_1_is_fencei <= r_uops_0_is_fencei;\n r_uops_1_is_amo <= r_uops_0_is_amo;\n r_uops_1_uses_ldq <= r_uops_0_uses_ldq;\n r_uops_1_uses_stq <= r_uops_0_uses_stq;\n r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc;\n r_uops_1_is_unique <= r_uops_0_is_unique;\n r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit;\n r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1;\n r_uops_1_ldst <= r_uops_0_ldst;\n r_uops_1_lrs1 <= r_uops_0_lrs1;\n r_uops_1_lrs2 <= r_uops_0_lrs2;\n r_uops_1_lrs3 <= r_uops_0_lrs3;\n r_uops_1_ldst_val <= r_uops_0_ldst_val;\n r_uops_1_dst_rtype <= r_uops_0_dst_rtype;\n r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype;\n r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype;\n r_uops_1_frs3_en <= r_uops_0_frs3_en;\n r_uops_1_fp_val <= r_uops_0_fp_val;\n r_uops_1_fp_single <= r_uops_0_fp_single;\n r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if;\n r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if;\n r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if;\n r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if;\n r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if;\n r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc;\n r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc;\n r_uops_2_uopc <= r_uops_1_uopc;\n r_uops_2_inst <= r_uops_1_inst;\n r_uops_2_debug_inst <= r_uops_1_debug_inst;\n r_uops_2_is_rvc <= r_uops_1_is_rvc;\n r_uops_2_debug_pc <= r_uops_1_debug_pc;\n r_uops_2_iq_type <= r_uops_1_iq_type;\n r_uops_2_fu_code <= r_uops_1_fu_code;\n r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type;\n r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel;\n r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel;\n r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel;\n r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn;\n r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw;\n r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd;\n r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load;\n r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta;\n r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std;\n r_uops_2_iw_state <= r_uops_1_iw_state;\n r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned;\n r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned;\n r_uops_2_is_br <= r_uops_1_is_br;\n r_uops_2_is_jalr <= r_uops_1_is_jalr;\n r_uops_2_is_jal <= r_uops_1_is_jal;\n r_uops_2_is_sfb <= r_uops_1_is_sfb;\n r_uops_2_br_mask <= r_uops_1_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_2_br_tag <= r_uops_1_br_tag;\n r_uops_2_ftq_idx <= r_uops_1_ftq_idx;\n r_uops_2_edge_inst <= r_uops_1_edge_inst;\n r_uops_2_pc_lob <= r_uops_1_pc_lob;\n r_uops_2_taken <= r_uops_1_taken;\n r_uops_2_imm_packed <= r_uops_1_imm_packed;\n r_uops_2_csr_addr <= r_uops_1_csr_addr;\n r_uops_2_rob_idx <= r_uops_1_rob_idx;\n r_uops_2_ldq_idx <= r_uops_1_ldq_idx;\n r_uops_2_stq_idx <= r_uops_1_stq_idx;\n r_uops_2_rxq_idx <= r_uops_1_rxq_idx;\n r_uops_2_pdst <= r_uops_1_pdst;\n r_uops_2_prs1 <= r_uops_1_prs1;\n r_uops_2_prs2 <= r_uops_1_prs2;\n r_uops_2_prs3 <= r_uops_1_prs3;\n r_uops_2_ppred <= r_uops_1_ppred;\n r_uops_2_prs1_busy <= r_uops_1_prs1_busy;\n r_uops_2_prs2_busy <= r_uops_1_prs2_busy;\n r_uops_2_prs3_busy <= r_uops_1_prs3_busy;\n r_uops_2_ppred_busy <= r_uops_1_ppred_busy;\n r_uops_2_stale_pdst <= r_uops_1_stale_pdst;\n r_uops_2_exception <= r_uops_1_exception;\n r_uops_2_exc_cause <= r_uops_1_exc_cause;\n r_uops_2_bypassable <= r_uops_1_bypassable;\n r_uops_2_mem_cmd <= r_uops_1_mem_cmd;\n r_uops_2_mem_size <= r_uops_1_mem_size;\n r_uops_2_mem_signed <= r_uops_1_mem_signed;\n r_uops_2_is_fence <= r_uops_1_is_fence;\n r_uops_2_is_fencei <= r_uops_1_is_fencei;\n r_uops_2_is_amo <= r_uops_1_is_amo;\n r_uops_2_uses_ldq <= r_uops_1_uses_ldq;\n r_uops_2_uses_stq <= r_uops_1_uses_stq;\n r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc;\n r_uops_2_is_unique <= r_uops_1_is_unique;\n r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit;\n r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1;\n r_uops_2_ldst <= r_uops_1_ldst;\n r_uops_2_lrs1 <= r_uops_1_lrs1;\n r_uops_2_lrs2 <= r_uops_1_lrs2;\n r_uops_2_lrs3 <= r_uops_1_lrs3;\n r_uops_2_ldst_val <= r_uops_1_ldst_val;\n r_uops_2_dst_rtype <= r_uops_1_dst_rtype;\n r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype;\n r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype;\n r_uops_2_frs3_en <= r_uops_1_frs3_en;\n r_uops_2_fp_val <= r_uops_1_fp_val;\n r_uops_2_fp_single <= r_uops_1_fp_single;\n r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if;\n r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if;\n r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if;\n r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if;\n r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if;\n r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc;\n r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc;\n r_uops_3_uopc <= r_uops_2_uopc;\n r_uops_3_inst <= r_uops_2_inst;\n r_uops_3_debug_inst <= r_uops_2_debug_inst;\n r_uops_3_is_rvc <= r_uops_2_is_rvc;\n r_uops_3_debug_pc <= r_uops_2_debug_pc;\n r_uops_3_iq_type <= r_uops_2_iq_type;\n r_uops_3_fu_code <= r_uops_2_fu_code;\n r_uops_3_ctrl_br_type <= r_uops_2_ctrl_br_type;\n r_uops_3_ctrl_op1_sel <= r_uops_2_ctrl_op1_sel;\n r_uops_3_ctrl_op2_sel <= r_uops_2_ctrl_op2_sel;\n r_uops_3_ctrl_imm_sel <= r_uops_2_ctrl_imm_sel;\n r_uops_3_ctrl_op_fcn <= r_uops_2_ctrl_op_fcn;\n r_uops_3_ctrl_fcn_dw <= r_uops_2_ctrl_fcn_dw;\n r_uops_3_ctrl_csr_cmd <= r_uops_2_ctrl_csr_cmd;\n r_uops_3_ctrl_is_load <= r_uops_2_ctrl_is_load;\n r_uops_3_ctrl_is_sta <= r_uops_2_ctrl_is_sta;\n r_uops_3_ctrl_is_std <= r_uops_2_ctrl_is_std;\n r_uops_3_iw_state <= r_uops_2_iw_state;\n r_uops_3_iw_p1_poisoned <= r_uops_2_iw_p1_poisoned;\n r_uops_3_iw_p2_poisoned <= r_uops_2_iw_p2_poisoned;\n r_uops_3_is_br <= r_uops_2_is_br;\n r_uops_3_is_jalr <= r_uops_2_is_jalr;\n r_uops_3_is_jal <= r_uops_2_is_jal;\n r_uops_3_is_sfb <= r_uops_2_is_sfb;\n r_uops_3_br_mask <= r_uops_2_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_3_br_tag <= r_uops_2_br_tag;\n r_uops_3_ftq_idx <= r_uops_2_ftq_idx;\n r_uops_3_edge_inst <= r_uops_2_edge_inst;\n r_uops_3_pc_lob <= r_uops_2_pc_lob;\n r_uops_3_taken <= r_uops_2_taken;\n r_uops_3_imm_packed <= r_uops_2_imm_packed;\n r_uops_3_csr_addr <= r_uops_2_csr_addr;\n r_uops_3_rob_idx <= r_uops_2_rob_idx;\n r_uops_3_ldq_idx <= r_uops_2_ldq_idx;\n r_uops_3_stq_idx <= r_uops_2_stq_idx;\n r_uops_3_rxq_idx <= r_uops_2_rxq_idx;\n r_uops_3_pdst <= r_uops_2_pdst;\n r_uops_3_prs1 <= r_uops_2_prs1;\n r_uops_3_prs2 <= r_uops_2_prs2;\n r_uops_3_prs3 <= r_uops_2_prs3;\n r_uops_3_ppred <= r_uops_2_ppred;\n r_uops_3_prs1_busy <= r_uops_2_prs1_busy;\n r_uops_3_prs2_busy <= r_uops_2_prs2_busy;\n r_uops_3_prs3_busy <= r_uops_2_prs3_busy;\n r_uops_3_ppred_busy <= r_uops_2_ppred_busy;\n r_uops_3_stale_pdst <= r_uops_2_stale_pdst;\n r_uops_3_exception <= r_uops_2_exception;\n r_uops_3_exc_cause <= r_uops_2_exc_cause;\n r_uops_3_bypassable <= r_uops_2_bypassable;\n r_uops_3_mem_cmd <= r_uops_2_mem_cmd;\n r_uops_3_mem_size <= r_uops_2_mem_size;\n r_uops_3_mem_signed <= r_uops_2_mem_signed;\n r_uops_3_is_fence <= r_uops_2_is_fence;\n r_uops_3_is_fencei <= r_uops_2_is_fencei;\n r_uops_3_is_amo <= r_uops_2_is_amo;\n r_uops_3_uses_ldq <= r_uops_2_uses_ldq;\n r_uops_3_uses_stq <= r_uops_2_uses_stq;\n r_uops_3_is_sys_pc2epc <= r_uops_2_is_sys_pc2epc;\n r_uops_3_is_unique <= r_uops_2_is_unique;\n r_uops_3_flush_on_commit <= r_uops_2_flush_on_commit;\n r_uops_3_ldst_is_rs1 <= r_uops_2_ldst_is_rs1;\n r_uops_3_ldst <= r_uops_2_ldst;\n r_uops_3_lrs1 <= r_uops_2_lrs1;\n r_uops_3_lrs2 <= r_uops_2_lrs2;\n r_uops_3_lrs3 <= r_uops_2_lrs3;\n r_uops_3_ldst_val <= r_uops_2_ldst_val;\n r_uops_3_dst_rtype <= r_uops_2_dst_rtype;\n r_uops_3_lrs1_rtype <= r_uops_2_lrs1_rtype;\n r_uops_3_lrs2_rtype <= r_uops_2_lrs2_rtype;\n r_uops_3_frs3_en <= r_uops_2_frs3_en;\n r_uops_3_fp_val <= r_uops_2_fp_val;\n r_uops_3_fp_single <= r_uops_2_fp_single;\n r_uops_3_xcpt_pf_if <= r_uops_2_xcpt_pf_if;\n r_uops_3_xcpt_ae_if <= r_uops_2_xcpt_ae_if;\n r_uops_3_xcpt_ma_if <= r_uops_2_xcpt_ma_if;\n r_uops_3_bp_debug_if <= r_uops_2_bp_debug_if;\n r_uops_3_bp_xcpt_if <= r_uops_2_bp_xcpt_if;\n r_uops_3_debug_fsrc <= r_uops_2_debug_fsrc;\n r_uops_3_debug_tsrc <= r_uops_2_debug_tsrc;\n end\n FPU fpu (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_rs1_data (io_req_bits_rs1_data),\n .io_req_bits_rs2_data (io_req_bits_rs2_data),\n .io_req_bits_rs3_data (io_req_bits_rs3_data),\n .io_req_bits_fcsr_rm (io_fcsr_rm),\n .io_resp_bits_data (io_resp_bits_data),\n .io_resp_bits_fflags_valid (io_resp_bits_fflags_valid),\n .io_resp_bits_fflags_bits_flags (io_resp_bits_fflags_bits_flags)\n );\n assign io_resp_valid = r_valids_3 & (io_brupdate_b1_mispredict_mask & r_uops_3_br_mask) == 8'h0;\n assign io_resp_bits_uop_uopc = r_uops_3_uopc;\n assign io_resp_bits_uop_inst = r_uops_3_inst;\n assign io_resp_bits_uop_debug_inst = r_uops_3_debug_inst;\n assign io_resp_bits_uop_is_rvc = r_uops_3_is_rvc;\n assign io_resp_bits_uop_debug_pc = r_uops_3_debug_pc;\n assign io_resp_bits_uop_iq_type = r_uops_3_iq_type;\n assign io_resp_bits_uop_fu_code = r_uops_3_fu_code;\n assign io_resp_bits_uop_ctrl_br_type = r_uops_3_ctrl_br_type;\n assign io_resp_bits_uop_ctrl_op1_sel = r_uops_3_ctrl_op1_sel;\n assign io_resp_bits_uop_ctrl_op2_sel = r_uops_3_ctrl_op2_sel;\n assign io_resp_bits_uop_ctrl_imm_sel = r_uops_3_ctrl_imm_sel;\n assign io_resp_bits_uop_ctrl_op_fcn = r_uops_3_ctrl_op_fcn;\n assign io_resp_bits_uop_ctrl_fcn_dw = r_uops_3_ctrl_fcn_dw;\n assign io_resp_bits_uop_ctrl_csr_cmd = r_uops_3_ctrl_csr_cmd;\n assign io_resp_bits_uop_ctrl_is_load = r_uops_3_ctrl_is_load;\n assign io_resp_bits_uop_ctrl_is_sta = r_uops_3_ctrl_is_sta;\n assign io_resp_bits_uop_ctrl_is_std = r_uops_3_ctrl_is_std;\n assign io_resp_bits_uop_iw_state = r_uops_3_iw_state;\n assign io_resp_bits_uop_iw_p1_poisoned = r_uops_3_iw_p1_poisoned;\n assign io_resp_bits_uop_iw_p2_poisoned = r_uops_3_iw_p2_poisoned;\n assign io_resp_bits_uop_is_br = r_uops_3_is_br;\n assign io_resp_bits_uop_is_jalr = r_uops_3_is_jalr;\n assign io_resp_bits_uop_is_jal = r_uops_3_is_jal;\n assign io_resp_bits_uop_is_sfb = r_uops_3_is_sfb;\n assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0;\n assign io_resp_bits_uop_br_tag = r_uops_3_br_tag;\n assign io_resp_bits_uop_ftq_idx = r_uops_3_ftq_idx;\n assign io_resp_bits_uop_edge_inst = r_uops_3_edge_inst;\n assign io_resp_bits_uop_pc_lob = r_uops_3_pc_lob;\n assign io_resp_bits_uop_taken = r_uops_3_taken;\n assign io_resp_bits_uop_imm_packed = r_uops_3_imm_packed;\n assign io_resp_bits_uop_csr_addr = r_uops_3_csr_addr;\n assign io_resp_bits_uop_rob_idx = r_uops_3_rob_idx;\n assign io_resp_bits_uop_ldq_idx = r_uops_3_ldq_idx;\n assign io_resp_bits_uop_stq_idx = r_uops_3_stq_idx;\n assign io_resp_bits_uop_rxq_idx = r_uops_3_rxq_idx;\n assign io_resp_bits_uop_pdst = r_uops_3_pdst;\n assign io_resp_bits_uop_prs1 = r_uops_3_prs1;\n assign io_resp_bits_uop_prs2 = r_uops_3_prs2;\n assign io_resp_bits_uop_prs3 = r_uops_3_prs3;\n assign io_resp_bits_uop_ppred = r_uops_3_ppred;\n assign io_resp_bits_uop_prs1_busy = r_uops_3_prs1_busy;\n assign io_resp_bits_uop_prs2_busy = r_uops_3_prs2_busy;\n assign io_resp_bits_uop_prs3_busy = r_uops_3_prs3_busy;\n assign io_resp_bits_uop_ppred_busy = r_uops_3_ppred_busy;\n assign io_resp_bits_uop_stale_pdst = r_uops_3_stale_pdst;\n assign io_resp_bits_uop_exception = r_uops_3_exception;\n assign io_resp_bits_uop_exc_cause = r_uops_3_exc_cause;\n assign io_resp_bits_uop_bypassable = r_uops_3_bypassable;\n assign io_resp_bits_uop_mem_cmd = r_uops_3_mem_cmd;\n assign io_resp_bits_uop_mem_size = r_uops_3_mem_size;\n assign io_resp_bits_uop_mem_signed = r_uops_3_mem_signed;\n assign io_resp_bits_uop_is_fence = r_uops_3_is_fence;\n assign io_resp_bits_uop_is_fencei = r_uops_3_is_fencei;\n assign io_resp_bits_uop_is_amo = r_uops_3_is_amo;\n assign io_resp_bits_uop_uses_ldq = r_uops_3_uses_ldq;\n assign io_resp_bits_uop_uses_stq = r_uops_3_uses_stq;\n assign io_resp_bits_uop_is_sys_pc2epc = r_uops_3_is_sys_pc2epc;\n assign io_resp_bits_uop_is_unique = r_uops_3_is_unique;\n assign io_resp_bits_uop_flush_on_commit = r_uops_3_flush_on_commit;\n assign io_resp_bits_uop_ldst_is_rs1 = r_uops_3_ldst_is_rs1;\n assign io_resp_bits_uop_ldst = r_uops_3_ldst;\n assign io_resp_bits_uop_lrs1 = r_uops_3_lrs1;\n assign io_resp_bits_uop_lrs2 = r_uops_3_lrs2;\n assign io_resp_bits_uop_lrs3 = r_uops_3_lrs3;\n assign io_resp_bits_uop_ldst_val = r_uops_3_ldst_val;\n assign io_resp_bits_uop_dst_rtype = r_uops_3_dst_rtype;\n assign io_resp_bits_uop_lrs1_rtype = r_uops_3_lrs1_rtype;\n assign io_resp_bits_uop_lrs2_rtype = r_uops_3_lrs2_rtype;\n assign io_resp_bits_uop_frs3_en = r_uops_3_frs3_en;\n assign io_resp_bits_uop_fp_val = r_uops_3_fp_val;\n assign io_resp_bits_uop_fp_single = r_uops_3_fp_single;\n assign io_resp_bits_uop_xcpt_pf_if = r_uops_3_xcpt_pf_if;\n assign io_resp_bits_uop_xcpt_ae_if = r_uops_3_xcpt_ae_if;\n assign io_resp_bits_uop_xcpt_ma_if = r_uops_3_xcpt_ma_if;\n assign io_resp_bits_uop_bp_debug_if = r_uops_3_bp_debug_if;\n assign io_resp_bits_uop_bp_xcpt_if = r_uops_3_bp_xcpt_if;\n assign io_resp_bits_uop_debug_fsrc = r_uops_3_debug_fsrc;\n assign io_resp_bits_uop_debug_tsrc = r_uops_3_debug_tsrc;\n assign io_resp_bits_fflags_bits_uop_uopc = r_uops_3_uopc;\n assign io_resp_bits_fflags_bits_uop_inst = r_uops_3_inst;\n assign io_resp_bits_fflags_bits_uop_debug_inst = r_uops_3_debug_inst;\n assign io_resp_bits_fflags_bits_uop_is_rvc = r_uops_3_is_rvc;\n assign io_resp_bits_fflags_bits_uop_debug_pc = r_uops_3_debug_pc;\n assign io_resp_bits_fflags_bits_uop_iq_type = r_uops_3_iq_type;\n assign io_resp_bits_fflags_bits_uop_fu_code = r_uops_3_fu_code;\n assign io_resp_bits_fflags_bits_uop_ctrl_br_type = r_uops_3_ctrl_br_type;\n assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel = r_uops_3_ctrl_op1_sel;\n assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel = r_uops_3_ctrl_op2_sel;\n assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel = r_uops_3_ctrl_imm_sel;\n assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn = r_uops_3_ctrl_op_fcn;\n assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = r_uops_3_ctrl_fcn_dw;\n assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = r_uops_3_ctrl_csr_cmd;\n assign io_resp_bits_fflags_bits_uop_ctrl_is_load = r_uops_3_ctrl_is_load;\n assign io_resp_bits_fflags_bits_uop_ctrl_is_sta = r_uops_3_ctrl_is_sta;\n assign io_resp_bits_fflags_bits_uop_ctrl_is_std = r_uops_3_ctrl_is_std;\n assign io_resp_bits_fflags_bits_uop_iw_state = r_uops_3_iw_state;\n assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned = r_uops_3_iw_p1_poisoned;\n assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned = r_uops_3_iw_p2_poisoned;\n assign io_resp_bits_fflags_bits_uop_is_br = r_uops_3_is_br;\n assign io_resp_bits_fflags_bits_uop_is_jalr = r_uops_3_is_jalr;\n assign io_resp_bits_fflags_bits_uop_is_jal = r_uops_3_is_jal;\n assign io_resp_bits_fflags_bits_uop_is_sfb = r_uops_3_is_sfb;\n assign io_resp_bits_fflags_bits_uop_br_mask = io_resp_bits_uop_br_mask_0;\n assign io_resp_bits_fflags_bits_uop_br_tag = r_uops_3_br_tag;\n assign io_resp_bits_fflags_bits_uop_ftq_idx = r_uops_3_ftq_idx;\n assign io_resp_bits_fflags_bits_uop_edge_inst = r_uops_3_edge_inst;\n assign io_resp_bits_fflags_bits_uop_pc_lob = r_uops_3_pc_lob;\n assign io_resp_bits_fflags_bits_uop_taken = r_uops_3_taken;\n assign io_resp_bits_fflags_bits_uop_imm_packed = r_uops_3_imm_packed;\n assign io_resp_bits_fflags_bits_uop_csr_addr = r_uops_3_csr_addr;\n assign io_resp_bits_fflags_bits_uop_rob_idx = r_uops_3_rob_idx;\n assign io_resp_bits_fflags_bits_uop_ldq_idx = r_uops_3_ldq_idx;\n assign io_resp_bits_fflags_bits_uop_stq_idx = r_uops_3_stq_idx;\n assign io_resp_bits_fflags_bits_uop_rxq_idx = r_uops_3_rxq_idx;\n assign io_resp_bits_fflags_bits_uop_pdst = r_uops_3_pdst;\n assign io_resp_bits_fflags_bits_uop_prs1 = r_uops_3_prs1;\n assign io_resp_bits_fflags_bits_uop_prs2 = r_uops_3_prs2;\n assign io_resp_bits_fflags_bits_uop_prs3 = r_uops_3_prs3;\n assign io_resp_bits_fflags_bits_uop_ppred = r_uops_3_ppred;\n assign io_resp_bits_fflags_bits_uop_prs1_busy = r_uops_3_prs1_busy;\n assign io_resp_bits_fflags_bits_uop_prs2_busy = r_uops_3_prs2_busy;\n assign io_resp_bits_fflags_bits_uop_prs3_busy = r_uops_3_prs3_busy;\n assign io_resp_bits_fflags_bits_uop_ppred_busy = r_uops_3_ppred_busy;\n assign io_resp_bits_fflags_bits_uop_stale_pdst = r_uops_3_stale_pdst;\n assign io_resp_bits_fflags_bits_uop_exception = r_uops_3_exception;\n assign io_resp_bits_fflags_bits_uop_exc_cause = r_uops_3_exc_cause;\n assign io_resp_bits_fflags_bits_uop_bypassable = r_uops_3_bypassable;\n assign io_resp_bits_fflags_bits_uop_mem_cmd = r_uops_3_mem_cmd;\n assign io_resp_bits_fflags_bits_uop_mem_size = r_uops_3_mem_size;\n assign io_resp_bits_fflags_bits_uop_mem_signed = r_uops_3_mem_signed;\n assign io_resp_bits_fflags_bits_uop_is_fence = r_uops_3_is_fence;\n assign io_resp_bits_fflags_bits_uop_is_fencei = r_uops_3_is_fencei;\n assign io_resp_bits_fflags_bits_uop_is_amo = r_uops_3_is_amo;\n assign io_resp_bits_fflags_bits_uop_uses_ldq = r_uops_3_uses_ldq;\n assign io_resp_bits_fflags_bits_uop_uses_stq = r_uops_3_uses_stq;\n assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc = r_uops_3_is_sys_pc2epc;\n assign io_resp_bits_fflags_bits_uop_is_unique = r_uops_3_is_unique;\n assign io_resp_bits_fflags_bits_uop_flush_on_commit = r_uops_3_flush_on_commit;\n assign io_resp_bits_fflags_bits_uop_ldst_is_rs1 = r_uops_3_ldst_is_rs1;\n assign io_resp_bits_fflags_bits_uop_ldst = r_uops_3_ldst;\n assign io_resp_bits_fflags_bits_uop_lrs1 = r_uops_3_lrs1;\n assign io_resp_bits_fflags_bits_uop_lrs2 = r_uops_3_lrs2;\n assign io_resp_bits_fflags_bits_uop_lrs3 = r_uops_3_lrs3;\n assign io_resp_bits_fflags_bits_uop_ldst_val = r_uops_3_ldst_val;\n assign io_resp_bits_fflags_bits_uop_dst_rtype = r_uops_3_dst_rtype;\n assign io_resp_bits_fflags_bits_uop_lrs1_rtype = r_uops_3_lrs1_rtype;\n assign io_resp_bits_fflags_bits_uop_lrs2_rtype = r_uops_3_lrs2_rtype;\n assign io_resp_bits_fflags_bits_uop_frs3_en = r_uops_3_frs3_en;\n assign io_resp_bits_fflags_bits_uop_fp_val = r_uops_3_fp_val;\n assign io_resp_bits_fflags_bits_uop_fp_single = r_uops_3_fp_single;\n assign io_resp_bits_fflags_bits_uop_xcpt_pf_if = r_uops_3_xcpt_pf_if;\n assign io_resp_bits_fflags_bits_uop_xcpt_ae_if = r_uops_3_xcpt_ae_if;\n assign io_resp_bits_fflags_bits_uop_xcpt_ma_if = r_uops_3_xcpt_ma_if;\n assign io_resp_bits_fflags_bits_uop_bp_debug_if = r_uops_3_bp_debug_if;\n assign io_resp_bits_fflags_bits_uop_bp_xcpt_if = r_uops_3_bp_xcpt_if;\n assign io_resp_bits_fflags_bits_uop_debug_fsrc = r_uops_3_debug_fsrc;\n assign io_resp_bits_fflags_bits_uop_debug_tsrc = r_uops_3_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.regmapper\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\nimport chisel3.util._\n\nimport freechips.rocketchip.diplomacy.AddressDecoder\n\nimport freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}\n\n// A bus agnostic register interface to a register-based device\ncase class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil)\n\nclass RegMapperInput(val params: RegMapperParams) extends Bundle\n{\n val read = Bool()\n val index = UInt((params.indexBits).W)\n val data = UInt((params.maskBits*8).W)\n val mask = UInt((params.maskBits).W)\n val extra = BundleMap(params.extraFields)\n}\n\nclass RegMapperOutput(val params: RegMapperParams) extends Bundle\n{\n val read = Bool()\n val data = UInt((params.maskBits*8).W)\n val extra = BundleMap(params.extraFields)\n}\n\nobject RegMapper\n{\n // Create a generic register-based device\n def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {\n // Filter out zero-width fields\n val bytemap = mapping.toList.map { case (offset, fields) => (offset, fields.filter(_.width != 0)) }\n\n // Negative addresses are bad\n bytemap.foreach { byte => require (byte._1 >= 0) }\n\n // Transform all fields into bit offsets Seq[(bit, field)]\n val bitmap = bytemap.map { case (byte, fields) =>\n val bits = fields.scanLeft(byte * 8)(_ + _.width).init\n bits zip fields\n }.flatten.sortBy(_._1)\n\n // Detect overlaps\n (bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>\n require (lbit + lfield.width <= rbit, s\"Register map overlaps at bit ${rbit}.\")\n }\n\n // Group those fields into bus words Map[word, List[(bit, field)]]\n val wordmap = bitmap.groupBy(_._1 / (8*bytes))\n\n // Make sure registers fit\n val inParams = in.bits.params\n val inBits = inParams.indexBits\n assert (wordmap.keySet.max < (1 << inBits), \"Register map does not fit in device\")\n\n val out = Wire(Decoupled(new RegMapperOutput(inParams)))\n val front = Wire(Decoupled(new RegMapperInput(inParams)))\n front.bits := in.bits\n\n // Must this device pipeline the control channel?\n val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)\n val depth = concurrency\n require (depth >= 0)\n require (!pipelined || depth > 0, \"Register-based device with request/response handshaking needs concurrency > 0\")\n val back = if (depth > 0) {\n val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {\n override def desiredName = s\"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}\"\n })\n front_q.io.enq <> front\n front_q.io.deq\n } else front\n\n // Convert to and from Bits\n def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =\n if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)\n def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }\n\n // Find the minimal mask that can decide the register map\n val mask = AddressDecoder(wordmap.keySet.toList)\n val maskMatch = ~mask.U(inBits.W)\n val maskFilter = toBits(mask)\n val maskBits = maskFilter.filter(x => x).size\n\n // Calculate size and indexes into the register map\n val regSize = 1 << maskBits\n def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))\n def regIndexU(x: UInt) = if (maskBits == 0) 0.U else\n Cat((maskFilter zip x.asBools).filter(_._1).map(_._2).reverse)\n\n val findex = front.bits.index & maskMatch\n val bindex = back .bits.index & maskMatch\n\n // Protection flag for undefined registers\n val iRightReg = Array.fill(regSize) { true.B }\n val oRightReg = Array.fill(regSize) { true.B }\n\n // Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]\n val flat = wordmap.toList.map { case (word, fields) =>\n val index = regIndexI(word)\n if (undefZero) {\n val uint = (word & ~mask).U(inBits.W)\n iRightReg(index) = findex === uint\n oRightReg(index) = bindex === uint\n }\n // Confirm that no field spans a word boundary\n fields foreach { case (bit, field) =>\n val off = bit - 8*bytes*word\n // println(s\"Reg ${word}: [${off}, ${off+field.width})\")\n require (off + field.width <= bytes * 8, s\"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.\")\n }\n // println(\"mapping 0x%x -> 0x%x for 0x%x/%d\".format(word, index, mask, maskBits))\n fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }\n }.flatten\n\n // Forward declaration of all flow control signals\n val rivalid = Wire(Vec(flat.size, Bool()))\n val wivalid = Wire(Vec(flat.size, Bool()))\n val roready = Wire(Vec(flat.size, Bool()))\n val woready = Wire(Vec(flat.size, Bool()))\n\n // Per-register list of all control signals needed for data to flow\n val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n\n // The output values for each register\n val dataOut = Array.fill(regSize) { 0.U }\n\n // Which bits are touched?\n val frontMask = FillInterleaved(8, front.bits.mask)\n val backMask = FillInterleaved(8, back .bits.mask)\n\n // Connect the fields\n for (i <- 0 until flat.size) {\n val (reg, low, field) = flat(i)\n val high = low + field.width - 1\n // Confirm that no register is too big\n require (high < 8*bytes)\n val rimask = frontMask(high, low).orR\n val wimask = frontMask(high, low).andR\n val romask = backMask(high, low).orR\n val womask = backMask(high, low).andR\n val data = if (field.write.combinational) back.bits.data else front.bits.data\n val f_rivalid = rivalid(i) && rimask\n val f_roready = roready(i) && romask\n val f_wivalid = wivalid(i) && wimask\n val f_woready = woready(i) && womask\n val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)\n val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))\n\n // cover reads and writes to register\n val fname = field.desc.map{_.name}.getOrElse(\"\")\n val fdesc = field.desc.map{_.desc + \":\"}.getOrElse(\"\")\n\n val facct = field.desc.map{_.access}.getOrElse(\"\")\n if((facct == RegFieldAccessType.R) || (facct == RegFieldAccessType.RW)) {\n property.cover(f_rivalid && f_riready, fname + \"_Reg_read_start\", fdesc + \" RegField Read Request Initiate\")\n property.cover(f_rovalid && f_roready, fname + \"_Reg_read_out\", fdesc + \" RegField Read Request Complete\")\n }\n if((facct == RegFieldAccessType.W) || (facct == RegFieldAccessType.RW)) {\n property.cover(f_wivalid && f_wiready, fname + \"_Reg_write_start\", fdesc + \" RegField Write Request Initiate\")\n property.cover(f_wovalid && f_woready, fname + \"_Reg_write_out\", fdesc + \" RegField Write Request Complete\")\n }\n\n def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) true.B else x || y\n // Add this field to the ready-valid signals for the register\n rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)\n wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)\n rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)\n wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)\n\n // ... this loop iterates from smallest to largest bit offset\n val prepend = if (low == 0) { f_data } else { Cat(f_data, dataOut(reg) | 0.U(low.W)) }\n dataOut(reg) = (prepend | 0.U((high+1).W))(high, 0)\n }\n\n // Which register is touched?\n val iindex = regIndexU(front.bits.index)\n val oindex = regIndexU(back .bits.index)\n val frontSel = UIntToOH(iindex).asBools\n val backSel = UIntToOH(oindex).asBools\n\n // Compute: is the selected register ready? ... and cross-connect all ready-valids\n def mux(index: UInt, valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Bool =\n MuxSeq(index, true.B, ((select zip guard) zip flow).map { case ((s, g), f) =>\n val out = Wire(Bool())\n ReduceOthers((out, valid && s && g) +: f)\n out || !g\n })\n\n // Include the per-register one-hot selected criteria\n val rifireMux = mux(iindex, in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)\n val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)\n val rofireMux = mux(oindex, back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)\n val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)\n\n val iready = Mux(front.bits.read, rifireMux, wifireMux)\n val oready = Mux(back .bits.read, rofireMux, wofireMux)\n\n // Connect the pipeline\n in.ready := front.ready && iready\n front.valid := in.valid && iready\n back.ready := out.ready && oready\n out.valid := back.valid && oready\n\n out.bits.read := back.bits.read\n out.bits.data := Mux(MuxSeq(oindex, true.B, oRightReg),\n MuxSeq(oindex, 0.U, dataOut),\n 0.U)\n out.bits.extra := back.bits.extra\n\n out\n }\n}", + "response": "module Queue1_RegMapperInput_i23_m8(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input io_enq_bits_read,\n input [22:0] io_enq_bits_index,\n input [63:0] io_enq_bits_data,\n input [7:0] io_enq_bits_mask,\n input [10:0] io_enq_bits_extra_tlrr_extra_source,\n input [1:0] io_enq_bits_extra_tlrr_extra_size,\n input io_deq_ready,\n output io_deq_valid,\n output io_deq_bits_read,\n output [22:0] io_deq_bits_index,\n output [63:0] io_deq_bits_data,\n output [7:0] io_deq_bits_mask,\n output [10:0] io_deq_bits_extra_tlrr_extra_source,\n output [1:0] io_deq_bits_extra_tlrr_extra_size\n);\n\n reg [108:0] ram;\n reg full;\n wire do_enq = ~full & io_enq_valid;\n always @(posedge clock) begin\n if (do_enq)\n ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read};\n if (reset)\n full <= 1'h0;\n else if (~(do_enq == (io_deq_ready & full)))\n full <= do_enq;\n end\n assign io_enq_ready = ~full;\n assign io_deq_valid = full;\n assign io_deq_bits_read = ram[0];\n assign io_deq_bits_index = ram[23:1];\n assign io_deq_bits_data = ram[87:24];\n assign io_deq_bits_mask = ram[95:88];\n assign io_deq_bits_extra_tlrr_extra_source = ram[106:96];\n assign io_deq_bits_extra_tlrr_extra_size = ram[108:107];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a13d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [12:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [12:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [12:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw87_f32_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// If regfile bypassing is disabled, then the functional unit must do its own\n// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)\n//\n// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}\n\nimport boom.v3.common._\nimport boom.v3.ifu._\nimport boom.v3.util._\n\n/**t\n * Functional unit constants\n */\nobject FUConstants\n{\n // bit mask, since a given execution pipeline may support multiple functional units\n val FUC_SZ = 10\n val FU_X = BitPat.dontCare(FUC_SZ)\n val FU_ALU = 1.U(FUC_SZ.W)\n val FU_JMP = 2.U(FUC_SZ.W)\n val FU_MEM = 4.U(FUC_SZ.W)\n val FU_MUL = 8.U(FUC_SZ.W)\n val FU_DIV = 16.U(FUC_SZ.W)\n val FU_CSR = 32.U(FUC_SZ.W)\n val FU_FPU = 64.U(FUC_SZ.W)\n val FU_FDV = 128.U(FUC_SZ.W)\n val FU_I2F = 256.U(FUC_SZ.W)\n val FU_F2I = 512.U(FUC_SZ.W)\n\n // FP stores generate data through FP F2I, and generate address through MemAddrCalc\n val FU_F2IMEM = 516.U(FUC_SZ.W)\n}\nimport FUConstants._\n\n/**\n * Class to tell the FUDecoders what units it needs to support\n *\n * @param alu support alu unit?\n * @param bru support br unit?\n * @param mem support mem unit?\n * @param muld support multiple div unit?\n * @param fpu support FP unit?\n * @param csr support csr writing unit?\n * @param fdiv support FP div unit?\n * @param ifpu support int to FP unit?\n */\nclass SupportedFuncUnits(\n val alu: Boolean = false,\n val jmp: Boolean = false,\n val mem: Boolean = false,\n val muld: Boolean = false,\n val fpu: Boolean = false,\n val csr: Boolean = false,\n val fdiv: Boolean = false,\n val ifpu: Boolean = false)\n{\n}\n\n\n/**\n * Bundle for signals sent to the functional unit\n *\n * @param dataWidth width of the data sent to the functional unit\n */\nclass FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val numOperands = 3\n\n val rs1_data = UInt(dataWidth.W)\n val rs2_data = UInt(dataWidth.W)\n val rs3_data = UInt(dataWidth.W) // only used for FMA units\n val pred_data = Bool()\n\n val kill = Bool() // kill everything\n}\n\n/**\n * Bundle for the signals sent out of the function unit\n *\n * @param dataWidth data sent from the functional unit\n */\nclass FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val predicated = Bool() // Was this response from a predicated-off instruction\n val data = UInt(dataWidth.W)\n val fflags = new ValidIO(new FFlagsResp)\n val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU\n val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU\n val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc\n}\n\n/**\n * Branch resolution information given from the branch unit\n */\nclass BrResolutionInfo(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp\n val valid = Bool()\n val mispredict = Bool()\n val taken = Bool() // which direction did the branch go?\n val cfi_type = UInt(CFI_SZ.W)\n\n // Info for recalculating the pc for this branch\n val pc_sel = UInt(2.W)\n\n val jalr_target = UInt(vaddrBitsExtended.W)\n val target_offset = SInt()\n}\n\nclass BrUpdateInfo(implicit p: Parameters) extends BoomBundle\n{\n // On the first cycle we get masks to kill registers\n val b1 = new BrUpdateMasks\n // On the second cycle we get indices to reset pointers\n val b2 = new BrResolutionInfo\n}\n\nclass BrUpdateMasks(implicit p: Parameters) extends BoomBundle\n{\n val resolve_mask = UInt(maxBrCount.W)\n val mispredict_mask = UInt(maxBrCount.W)\n}\n\n\n/**\n * Abstract top level functional unit class that wraps a lower level hand made functional unit\n *\n * @param isPipelined is the functional unit pipelined?\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class FunctionalUnit(\n val isPipelined: Boolean,\n val numStages: Int,\n val numBypassStages: Int,\n val dataWidth: Int,\n val isJmpUnit: Boolean = false,\n val isAluUnit: Boolean = false,\n val isMemAddrCalcUnit: Boolean = false,\n val needsFcsr: Boolean = false)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))\n\n val brupdate = Input(new BrUpdateInfo())\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n\n // only used by the fpu unit\n val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by branch unit\n val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null\n\n // only used by memaddr calc unit\n val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null\n\n })\n\n io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }\n\n io.resp.valid := false.B\n io.resp.bits := DontCare\n\n if (isJmpUnit) {\n io.get_ftq_pc.ftq_idx := DontCare\n }\n}\n\n/**\n * Abstract top level pipelined functional unit\n *\n * Note: this helps track which uops get killed while in intermediate stages,\n * but it is the job of the consumer to check for kills on the same cycle as consumption!!!\n *\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param earliestBypassStage first stage that you can start bypassing from\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class PipelinedFunctionalUnit(\n numStages: Int,\n numBypassStages: Int,\n earliestBypassStage: Int,\n dataWidth: Int,\n isJmpUnit: Boolean = false,\n isAluUnit: Boolean = false,\n isMemAddrCalcUnit: Boolean = false,\n needsFcsr: Boolean = false\n )(implicit p: Parameters) extends FunctionalUnit(\n isPipelined = true,\n numStages = numStages,\n numBypassStages = numBypassStages,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit,\n isAluUnit = isAluUnit,\n isMemAddrCalcUnit = isMemAddrCalcUnit,\n needsFcsr = needsFcsr)\n{\n // Pipelined functional unit is always ready.\n io.req.ready := true.B\n\n if (numStages > 0) {\n val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_uops = Reg(Vec(numStages, new MicroOp()))\n\n // handle incoming request\n r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill\n r_uops(0) := io.req.bits.uop\n r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n\n // handle middle of the pipeline\n for (i <- 1 until numStages) {\n r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill\n r_uops(i) := r_uops(i-1)\n r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))\n\n if (numBypassStages > 0) {\n io.bypass(i-1).bits.uop := r_uops(i-1)\n }\n }\n\n // handle outgoing (branch could still kill it)\n // consumer must also check for pipeline flushes (kills)\n io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := r_uops(numStages-1)\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))\n\n // bypassing (TODO allow bypass vector to have a different size from numStages)\n if (numBypassStages > 0 && earliestBypassStage == 0) {\n io.bypass(0).bits.uop := io.req.bits.uop\n\n for (i <- 1 until numBypassStages) {\n io.bypass(i).bits.uop := r_uops(i-1)\n }\n }\n } else {\n require (numStages == 0)\n // pass req straight through to response\n\n // valid doesn't check kill signals, let consumer deal with it.\n // The LSU already handles it and this hurts critical path.\n io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := io.req.bits.uop\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n }\n}\n\n/**\n * Functional unit that wraps RocketChips ALU\n *\n * @param isBranchUnit is this a branch unit?\n * @param numStages how many pipeline stages does the functional unit have\n * @param dataWidth width of the data being operated on in the functional unit\n */\nclass ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = numStages,\n isAluUnit = true,\n earliestBypassStage = 0,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit)\n with boom.v3.ifu.HasBoomFrontendParameters\n{\n val uop = io.req.bits.uop\n\n // immediate generation\n val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)\n\n // operand 1 select\n var op1_data: UInt = null\n if (isJmpUnit) {\n // Get the uop PC for jumps\n val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)\n val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)\n\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),\n 0.U))\n } else {\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n 0.U)\n }\n\n // operand 2 select\n val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),\n Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),\n Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,\n Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),\n 0.U))))\n\n val alu = Module(new freechips.rocketchip.rocket.ALU())\n\n alu.io.in1 := op1_data.asUInt\n alu.io.in2 := op2_data.asUInt\n alu.io.fn := uop.ctrl.op_fcn\n alu.io.dw := uop.ctrl.fcn_dw\n\n\n // Did I just get killed by the previous cycle's branch,\n // or by a flush pipeline?\n val killed = WireInit(false.B)\n when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {\n killed := true.B\n }\n\n val rs1 = io.req.bits.rs1_data\n val rs2 = io.req.bits.rs2_data\n val br_eq = (rs1 === rs2)\n val br_ltu = (rs1.asUInt < rs2.asUInt)\n val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |\n rs1(xLen-1) & ~rs2(xLen-1)).asBool\n\n val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(\n Seq( BR_N -> PC_PLUS4,\n BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),\n BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),\n BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),\n BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),\n BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),\n BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),\n BR_J -> PC_BRJMP,\n BR_JR -> PC_JALR\n ))\n\n val is_taken = io.req.valid &&\n !killed &&\n (uop.is_br || uop.is_jalr || uop.is_jal) &&\n (pc_sel =/= PC_PLUS4)\n\n // \"mispredict\" means that a branch has been resolved and it must be killed\n val mispredict = WireInit(false.B)\n\n val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb\n val is_jal = io.req.valid && !killed && uop.is_jal\n val is_jalr = io.req.valid && !killed && uop.is_jalr\n\n when (is_br || is_jalr) {\n if (!isJmpUnit) {\n assert (pc_sel =/= PC_JALR)\n }\n when (pc_sel === PC_PLUS4) {\n mispredict := uop.taken\n }\n when (pc_sel === PC_BRJMP) {\n mispredict := !uop.taken\n }\n }\n\n val brinfo = Wire(new BrResolutionInfo)\n\n // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit\n brinfo.valid := is_br || is_jalr\n brinfo.mispredict := mispredict\n brinfo.uop := uop\n brinfo.cfi_type := Mux(is_jalr, CFI_JALR,\n Mux(is_br , CFI_BR, CFI_X))\n brinfo.taken := is_taken\n brinfo.pc_sel := pc_sel\n\n brinfo.jalr_target := DontCare\n\n\n // Branch/Jump Target Calculation\n // For jumps we read the FTQ, and can calculate the target\n // For branches we emit the offset for the core to redirect if necessary\n val target_offset = imm_xprlen(20,0).asSInt\n brinfo.jalr_target := DontCare\n if (isJmpUnit) {\n def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {\n ea\n } else {\n // Efficient means to compress 64-bit VA into vaddrBits+1 bits.\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).\n val a = a0.asSInt >> vaddrBits\n val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))\n Cat(msb, ea(vaddrBits-1,0))\n }\n\n\n val jalr_target_base = io.req.bits.rs1_data.asSInt\n val jalr_target_xlen = Wire(UInt(xLen.W))\n jalr_target_xlen := (jalr_target_base + target_offset).asUInt\n val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt\n\n brinfo.jalr_target := jalr_target\n val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)\n\n when (pc_sel === PC_JALR) {\n mispredict := !io.get_ftq_pc.next_val ||\n (io.get_ftq_pc.next_pc =/= jalr_target) ||\n !io.get_ftq_pc.entry.cfi_idx.valid ||\n (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)\n }\n }\n\n brinfo.target_offset := target_offset\n\n\n io.brinfo := brinfo\n\n\n\n// Response\n// TODO add clock gate on resp bits from functional units\n// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)\n// val reg_data = Reg(outType = Bits(width = xLen))\n// reg_data := alu.io.out\n// io.resp.bits.data := reg_data\n\n val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_data = Reg(Vec(numStages, UInt(xLen.W)))\n val r_pred = Reg(Vec(numStages, Bool()))\n val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,\n Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),\n Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))\n r_val (0) := io.req.valid\n r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data\n for (i <- 1 until numStages) {\n r_val(i) := r_val(i-1)\n r_data(i) := r_data(i-1)\n r_pred(i) := r_pred(i-1)\n }\n io.resp.bits.data := r_data(numStages-1)\n io.resp.bits.predicated := r_pred(numStages-1)\n // Bypass\n // for the ALU, we can bypass same cycle as compute\n require (numStages >= 1)\n require (numBypassStages >= 1)\n io.bypass(0).valid := io.req.valid\n io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n for (i <- 1 until numStages) {\n io.bypass(i).valid := r_val(i-1)\n io.bypass(i).bits.data := r_data(i-1)\n }\n\n // Exceptions\n io.resp.bits.fflags.valid := false.B\n}\n\n/**\n * Functional unit that passes in base+imm to calculate addresses, and passes store data\n * to the LSU.\n * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form\n */\nclass MemAddrCalcUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = 0,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65, // TODO enable this only if FP is enabled?\n isMemAddrCalcUnit = true)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n with freechips.rocketchip.rocket.constants.ScalarOpConstants\n{\n // perform address calculation\n val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt\n val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,\n sum(63,vaddrBits) =/= 0.U)\n val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt\n\n val store_data = io.req.bits.rs2_data\n\n io.resp.bits.addr := effective_address\n io.resp.bits.data := store_data\n\n if (dataWidth > 63) {\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&\n io.resp.bits.data(64).asBool === true.B), \"65th bit set in MemAddrCalcUnit.\")\n\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),\n \"FP store-data should now be going through a different unit.\")\n }\n\n assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=\n uopLD && io.req.bits.uop.uopc =/= uopSTA),\n \"[maddrcalc] assert we never get store data in here.\")\n\n // Handle misaligned exceptions\n val size = io.req.bits.uop.mem_size\n val misaligned =\n (size === 1.U && (effective_address(0) =/= 0.U)) ||\n (size === 2.U && (effective_address(1,0) =/= 0.U)) ||\n (size === 3.U && (effective_address(2,0) =/= 0.U))\n\n val bkptu = Module(new BreakpointUnit(nBreakpoints))\n bkptu.io.status := io.status\n bkptu.io.bp := io.bp\n bkptu.io.pc := DontCare\n bkptu.io.ea := effective_address\n bkptu.io.mcontext := io.mcontext\n bkptu.io.scontext := io.scontext\n\n val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned\n val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned\n val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))\n val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n val (xcpt_val, xcpt_cause) = checkExceptions(List(\n (ma_ld, (Causes.misaligned_load).U),\n (ma_st, (Causes.misaligned_store).U),\n (dbg_bp, (CSR.debugTriggerCause).U),\n (bp, (Causes.breakpoint).U)))\n\n io.resp.bits.mxcpt.valid := xcpt_val\n io.resp.bits.mxcpt.bits := xcpt_cause\n assert (!(ma_ld && ma_st), \"Mutually-exclusive exceptions are firing.\")\n\n io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE\n io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)\n io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)\n io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data\n io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data\n}\n\n\n/**\n * Functional unit to wrap lower level FPU\n *\n * Currently, bypassing is unsupported!\n * All FP instructions are padded out to the max latency unit for easy\n * write-port scheduling.\n */\nclass FPUUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n{\n val fpu = Module(new FPU())\n fpu.io.req.valid := io.req.valid\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.fcsr_rm := io.fcsr_rm\n\n io.resp.bits.data := fpu.io.resp.bits.data\n io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now\n}\n\n/**\n * Int to FP conversion functional unit\n *\n * @param latency the amount of stages to delay by\n */\nclass IntToFPUnit(latency: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = latency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n with tile.HasFPUParameters\n{\n val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder\n val io_req = io.req.bits\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, None)\n req.in2 := unbox(io_req.rs2_data, tag, None)\n req.in3 := DontCare\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := DontCare // FIXME: this may not be the right thing to do here\n req.fmaCmd := DontCare\n\n assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n \"[func] IntToFP integer input has 65th high-order bit set!\")\n\n assert (!(io.req.valid && !fp_ctrl.fromint),\n \"[func] Only support fromInt micro-ops.\")\n\n val ifpu = Module(new tile.IntToFP(intToFpLatency))\n ifpu.io.in.valid := io.req.valid\n ifpu.io.in.bits := req\n ifpu.io.in.bits.in1 := io_req.rs1_data\n val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits\n\n//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)\n io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)\n io.resp.bits.fflags.valid := ifpu.io.out.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc\n}\n\n/**\n * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time\n * assumes at least one register between request and response\n *\n * TODO allow up to N micro-ops simultaneously.\n *\n * @param dataWidth width of the data to be passed into the functional unit\n */\nabstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)\n extends FunctionalUnit(\n isPipelined = false,\n numStages = 1,\n numBypassStages = 0,\n dataWidth = dataWidth)\n{\n val r_uop = Reg(new MicroOp())\n\n val do_kill = Wire(Bool())\n do_kill := io.req.bits.kill // irrelevant default\n\n when (io.req.fire) {\n // update incoming uop\n do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill\n r_uop := io.req.bits.uop\n r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n } .otherwise {\n do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill\n r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)\n }\n\n // assumes at least one pipeline register between request and response\n io.resp.bits.uop := r_uop\n}\n\n/**\n * Divide functional unit.\n *\n * @param dataWidth data to be passed into the functional unit\n */\nclass DivUnit(dataWidth: Int)(implicit p: Parameters)\n extends IterativeFunctionalUnit(dataWidth)\n{\n\n // We don't use the iterative multiply functionality here.\n // Instead we use the PipelinedMultiplier\n val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))\n\n // request\n div.io.req.valid := io.req.valid && !this.do_kill\n div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n div.io.req.bits.in1 := io.req.bits.rs1_data\n div.io.req.bits.in2 := io.req.bits.rs2_data\n div.io.req.bits.tag := DontCare\n io.req.ready := div.io.req.ready\n\n // handle pipeline kills and branch misspeculations\n div.io.kill := this.do_kill\n\n // response\n io.resp.valid := div.io.resp.valid && !this.do_kill\n div.io.resp.ready := io.resp.ready\n io.resp.bits.data := div.io.resp.bits.data\n}\n\n/**\n * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier\n *\n * @param numStages number of pipeline stages\n * @param dataWidth size of the data being passed into the functional unit\n */\nclass PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = dataWidth)\n{\n val imul = Module(new PipelinedMultiplier(xLen, numStages))\n // request\n imul.io.req.valid := io.req.valid\n imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n imul.io.req.bits.in1 := io.req.bits.rs1_data\n imul.io.req.bits.in2 := io.req.bits.rs2_data\n imul.io.req.bits.tag := DontCare\n // response\n io.resp.bits.data := imul.io.resp.bits.data\n}", + "response": "module MemAddrCalcUnit(\n input clock,\n input reset,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [64:0] io_req_bits_rs1_data,\n input [64:0] io_req_bits_rs2_data,\n output io_resp_valid,\n output [6:0] io_resp_bits_uop_uopc,\n output [31:0] io_resp_bits_uop_inst,\n output [31:0] io_resp_bits_uop_debug_inst,\n output io_resp_bits_uop_is_rvc,\n output [39:0] io_resp_bits_uop_debug_pc,\n output [2:0] io_resp_bits_uop_iq_type,\n output [9:0] io_resp_bits_uop_fu_code,\n output [3:0] io_resp_bits_uop_ctrl_br_type,\n output [1:0] io_resp_bits_uop_ctrl_op1_sel,\n output [2:0] io_resp_bits_uop_ctrl_op2_sel,\n output [2:0] io_resp_bits_uop_ctrl_imm_sel,\n output [4:0] io_resp_bits_uop_ctrl_op_fcn,\n output io_resp_bits_uop_ctrl_fcn_dw,\n output [2:0] io_resp_bits_uop_ctrl_csr_cmd,\n output io_resp_bits_uop_ctrl_is_load,\n output io_resp_bits_uop_ctrl_is_sta,\n output io_resp_bits_uop_ctrl_is_std,\n output [1:0] io_resp_bits_uop_iw_state,\n output io_resp_bits_uop_is_br,\n output io_resp_bits_uop_is_jalr,\n output io_resp_bits_uop_is_jal,\n output io_resp_bits_uop_is_sfb,\n output [7:0] io_resp_bits_uop_br_mask,\n output [2:0] io_resp_bits_uop_br_tag,\n output [3:0] io_resp_bits_uop_ftq_idx,\n output io_resp_bits_uop_edge_inst,\n output [5:0] io_resp_bits_uop_pc_lob,\n output io_resp_bits_uop_taken,\n output [19:0] io_resp_bits_uop_imm_packed,\n output [11:0] io_resp_bits_uop_csr_addr,\n output [4:0] io_resp_bits_uop_rob_idx,\n output [2:0] io_resp_bits_uop_ldq_idx,\n output [2:0] io_resp_bits_uop_stq_idx,\n output [1:0] io_resp_bits_uop_rxq_idx,\n output [5:0] io_resp_bits_uop_pdst,\n output [5:0] io_resp_bits_uop_prs1,\n output [5:0] io_resp_bits_uop_prs2,\n output [5:0] io_resp_bits_uop_prs3,\n output [3:0] io_resp_bits_uop_ppred,\n output io_resp_bits_uop_prs1_busy,\n output io_resp_bits_uop_prs2_busy,\n output io_resp_bits_uop_prs3_busy,\n output io_resp_bits_uop_ppred_busy,\n output [5:0] io_resp_bits_uop_stale_pdst,\n output io_resp_bits_uop_exception,\n output [63:0] io_resp_bits_uop_exc_cause,\n output io_resp_bits_uop_bypassable,\n output [4:0] io_resp_bits_uop_mem_cmd,\n output [1:0] io_resp_bits_uop_mem_size,\n output io_resp_bits_uop_mem_signed,\n output io_resp_bits_uop_is_fence,\n output io_resp_bits_uop_is_fencei,\n output io_resp_bits_uop_is_amo,\n output io_resp_bits_uop_uses_ldq,\n output io_resp_bits_uop_uses_stq,\n output io_resp_bits_uop_is_sys_pc2epc,\n output io_resp_bits_uop_is_unique,\n output io_resp_bits_uop_flush_on_commit,\n output io_resp_bits_uop_ldst_is_rs1,\n output [5:0] io_resp_bits_uop_ldst,\n output [5:0] io_resp_bits_uop_lrs1,\n output [5:0] io_resp_bits_uop_lrs2,\n output [5:0] io_resp_bits_uop_lrs3,\n output io_resp_bits_uop_ldst_val,\n output [1:0] io_resp_bits_uop_dst_rtype,\n output [1:0] io_resp_bits_uop_lrs1_rtype,\n output [1:0] io_resp_bits_uop_lrs2_rtype,\n output io_resp_bits_uop_frs3_en,\n output io_resp_bits_uop_fp_val,\n output io_resp_bits_uop_fp_single,\n output io_resp_bits_uop_xcpt_pf_if,\n output io_resp_bits_uop_xcpt_ae_if,\n output io_resp_bits_uop_xcpt_ma_if,\n output io_resp_bits_uop_bp_debug_if,\n output io_resp_bits_uop_bp_xcpt_if,\n output [1:0] io_resp_bits_uop_debug_fsrc,\n output [1:0] io_resp_bits_uop_debug_tsrc,\n output [64:0] io_resp_bits_data,\n output [39:0] io_resp_bits_addr,\n output io_resp_bits_mxcpt_valid,\n output io_resp_bits_sfence_valid,\n output io_resp_bits_sfence_bits_rs1,\n output io_resp_bits_sfence_bits_rs2,\n output [38:0] io_resp_bits_sfence_bits_addr,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask\n);\n\n wire [63:0] _sum_T_3 = io_req_bits_rs1_data[63:0] + {{52{io_req_bits_uop_imm_packed[19]}}, io_req_bits_uop_imm_packed[19:8]};\n wire misaligned = io_req_bits_uop_mem_size == 2'h1 & _sum_T_3[0] | io_req_bits_uop_mem_size == 2'h2 & (|(_sum_T_3[1:0])) | (&io_req_bits_uop_mem_size) & (|(_sum_T_3[2:0]));\n wire ma_ld = io_req_valid & io_req_bits_uop_uopc == 7'h1 & misaligned;\n wire ma_st = io_req_valid & (io_req_bits_uop_uopc == 7'h2 | io_req_bits_uop_uopc == 7'h43) & misaligned;\n assign io_resp_valid = io_req_valid & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0;\n assign io_resp_bits_uop_uopc = io_req_bits_uop_uopc;\n assign io_resp_bits_uop_inst = io_req_bits_uop_inst;\n assign io_resp_bits_uop_debug_inst = io_req_bits_uop_debug_inst;\n assign io_resp_bits_uop_is_rvc = io_req_bits_uop_is_rvc;\n assign io_resp_bits_uop_debug_pc = io_req_bits_uop_debug_pc;\n assign io_resp_bits_uop_iq_type = io_req_bits_uop_iq_type;\n assign io_resp_bits_uop_fu_code = io_req_bits_uop_fu_code;\n assign io_resp_bits_uop_ctrl_br_type = io_req_bits_uop_ctrl_br_type;\n assign io_resp_bits_uop_ctrl_op1_sel = io_req_bits_uop_ctrl_op1_sel;\n assign io_resp_bits_uop_ctrl_op2_sel = io_req_bits_uop_ctrl_op2_sel;\n assign io_resp_bits_uop_ctrl_imm_sel = io_req_bits_uop_ctrl_imm_sel;\n assign io_resp_bits_uop_ctrl_op_fcn = io_req_bits_uop_ctrl_op_fcn;\n assign io_resp_bits_uop_ctrl_fcn_dw = io_req_bits_uop_ctrl_fcn_dw;\n assign io_resp_bits_uop_ctrl_csr_cmd = io_req_bits_uop_ctrl_csr_cmd;\n assign io_resp_bits_uop_ctrl_is_load = io_req_bits_uop_ctrl_is_load;\n assign io_resp_bits_uop_ctrl_is_sta = io_req_bits_uop_ctrl_is_sta;\n assign io_resp_bits_uop_ctrl_is_std = io_req_bits_uop_ctrl_is_std;\n assign io_resp_bits_uop_iw_state = io_req_bits_uop_iw_state;\n assign io_resp_bits_uop_is_br = io_req_bits_uop_is_br;\n assign io_resp_bits_uop_is_jalr = io_req_bits_uop_is_jalr;\n assign io_resp_bits_uop_is_jal = io_req_bits_uop_is_jal;\n assign io_resp_bits_uop_is_sfb = io_req_bits_uop_is_sfb;\n assign io_resp_bits_uop_br_mask = io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_resp_bits_uop_br_tag = io_req_bits_uop_br_tag;\n assign io_resp_bits_uop_ftq_idx = io_req_bits_uop_ftq_idx;\n assign io_resp_bits_uop_edge_inst = io_req_bits_uop_edge_inst;\n assign io_resp_bits_uop_pc_lob = io_req_bits_uop_pc_lob;\n assign io_resp_bits_uop_taken = io_req_bits_uop_taken;\n assign io_resp_bits_uop_imm_packed = io_req_bits_uop_imm_packed;\n assign io_resp_bits_uop_csr_addr = io_req_bits_uop_csr_addr;\n assign io_resp_bits_uop_rob_idx = io_req_bits_uop_rob_idx;\n assign io_resp_bits_uop_ldq_idx = io_req_bits_uop_ldq_idx;\n assign io_resp_bits_uop_stq_idx = io_req_bits_uop_stq_idx;\n assign io_resp_bits_uop_rxq_idx = io_req_bits_uop_rxq_idx;\n assign io_resp_bits_uop_pdst = io_req_bits_uop_pdst;\n assign io_resp_bits_uop_prs1 = io_req_bits_uop_prs1;\n assign io_resp_bits_uop_prs2 = io_req_bits_uop_prs2;\n assign io_resp_bits_uop_prs3 = io_req_bits_uop_prs3;\n assign io_resp_bits_uop_ppred = io_req_bits_uop_ppred;\n assign io_resp_bits_uop_prs1_busy = io_req_bits_uop_prs1_busy;\n assign io_resp_bits_uop_prs2_busy = io_req_bits_uop_prs2_busy;\n assign io_resp_bits_uop_prs3_busy = io_req_bits_uop_prs3_busy;\n assign io_resp_bits_uop_ppred_busy = io_req_bits_uop_ppred_busy;\n assign io_resp_bits_uop_stale_pdst = io_req_bits_uop_stale_pdst;\n assign io_resp_bits_uop_exception = io_req_bits_uop_exception;\n assign io_resp_bits_uop_exc_cause = io_req_bits_uop_exc_cause;\n assign io_resp_bits_uop_bypassable = io_req_bits_uop_bypassable;\n assign io_resp_bits_uop_mem_cmd = io_req_bits_uop_mem_cmd;\n assign io_resp_bits_uop_mem_size = io_req_bits_uop_mem_size;\n assign io_resp_bits_uop_mem_signed = io_req_bits_uop_mem_signed;\n assign io_resp_bits_uop_is_fence = io_req_bits_uop_is_fence;\n assign io_resp_bits_uop_is_fencei = io_req_bits_uop_is_fencei;\n assign io_resp_bits_uop_is_amo = io_req_bits_uop_is_amo;\n assign io_resp_bits_uop_uses_ldq = io_req_bits_uop_uses_ldq;\n assign io_resp_bits_uop_uses_stq = io_req_bits_uop_uses_stq;\n assign io_resp_bits_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc;\n assign io_resp_bits_uop_is_unique = io_req_bits_uop_is_unique;\n assign io_resp_bits_uop_flush_on_commit = io_req_bits_uop_flush_on_commit;\n assign io_resp_bits_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1;\n assign io_resp_bits_uop_ldst = io_req_bits_uop_ldst;\n assign io_resp_bits_uop_lrs1 = io_req_bits_uop_lrs1;\n assign io_resp_bits_uop_lrs2 = io_req_bits_uop_lrs2;\n assign io_resp_bits_uop_lrs3 = io_req_bits_uop_lrs3;\n assign io_resp_bits_uop_ldst_val = io_req_bits_uop_ldst_val;\n assign io_resp_bits_uop_dst_rtype = io_req_bits_uop_dst_rtype;\n assign io_resp_bits_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype;\n assign io_resp_bits_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype;\n assign io_resp_bits_uop_frs3_en = io_req_bits_uop_frs3_en;\n assign io_resp_bits_uop_fp_val = io_req_bits_uop_fp_val;\n assign io_resp_bits_uop_fp_single = io_req_bits_uop_fp_single;\n assign io_resp_bits_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if;\n assign io_resp_bits_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if;\n assign io_resp_bits_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if;\n assign io_resp_bits_uop_bp_debug_if = io_req_bits_uop_bp_debug_if;\n assign io_resp_bits_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if;\n assign io_resp_bits_uop_debug_fsrc = io_req_bits_uop_debug_fsrc;\n assign io_resp_bits_uop_debug_tsrc = io_req_bits_uop_debug_tsrc;\n assign io_resp_bits_data = io_req_bits_rs2_data;\n assign io_resp_bits_addr = {_sum_T_3[38] ? (&(_sum_T_3[63:39])) : (|(_sum_T_3[63:39])), _sum_T_3[38:0]};\n assign io_resp_bits_mxcpt_valid = ma_ld | ma_st;\n assign io_resp_bits_sfence_valid = io_req_valid & io_req_bits_uop_mem_cmd == 5'h14;\n assign io_resp_bits_sfence_bits_rs1 = io_req_bits_uop_mem_size[0];\n assign io_resp_bits_sfence_bits_rs2 = io_req_bits_uop_mem_size[1];\n assign io_resp_bits_sfence_bits_addr = io_req_bits_rs1_data[38:0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.reflect.DataMirror\nimport chisel3.internal.firrtl.KnownWidth\nimport chisel3.util.{Cat, Valid}\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\n/** Base JTAG shifter IO, viewed from input to shift register chain.\n * Can be chained together.\n */\nclass ShifterIO extends Bundle {\n val shift = Bool() // advance the scan chain on clock high\n val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB\n val capture = Bool() // high in the CaptureIR/DR state when this chain is selected\n val update = Bool() // high in the UpdateIR/DR state when this chain is selected\n\n /** Sets a output shifter IO's control signals from a input shifter IO's control signals.\n */\n def chainControlFrom(in: ShifterIO): Unit = {\n shift := in.shift\n capture := in.capture\n update := in.update\n }\n}\n\ntrait ChainIO extends Bundle {\n val chainIn = Input(new ShifterIO)\n val chainOut = Output(new ShifterIO)\n}\n\nclass Capture[+T <: Data](gen: T) extends Bundle {\n val bits = Input(gen) // data to capture, should be always valid\n val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge\n}\n\nobject Capture {\n def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)\n}\n\n/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain\n * IO.\n */\ntrait Chain extends Module {\n val io: ChainIO\n}\n\n/** One-element shift register, data register for bypass mode.\n *\n * Implements Clause 10.\n */\nclass JtagBypassChain(implicit val p: Parameters) extends Chain {\n class ModIO extends ChainIO\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val reg = Reg(Bool()) // 10.1.1a single shift register stage\n\n io.chainOut.data := reg\n\n property.cover(io.chainIn.capture, \"bypass_chain_capture\", \"JTAG; bypass_chain_capture; This Bypass Chain captured data\")\n\n when (io.chainIn.capture) {\n reg := false.B // 10.1.1b capture logic 0 on TCK rising\n } .elsewhen (io.chainIn.shift) {\n reg := io.chainIn.data\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject JtagBypassChain {\n def apply()(implicit p: Parameters) = new JtagBypassChain\n}\n\n/** Simple shift register with parallel capture only, for read-only data registers.\n *\n * Number of stages is the number of bits in gen, which must have a known width.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureChain_${gen.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(gen)\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val n = DataMirror.widthOf(gen) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $gen\"); -1 // TODO: remove -1 type hack\n }\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG; chain_capture; This Chain captured data\")\n \n when (io.chainIn.capture) {\n (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))\n io.capture.capture := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n } .otherwise {\n io.capture.capture := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureChain {\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)\n}\n\n/** Simple shift register with parallel capture and update. Useful for general instruction and data\n * scan registers.\n *\n * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have\n * known widths. If there is a width mismatch, the unused most significant bits will be zero.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(genCapture)\n val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val captureWidth = DataMirror.widthOf(genCapture) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genCapture\"); -1 // TODO: remove -1 type hack\n }\n val updateWidth = DataMirror.widthOf(genUpdate) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genUpdate\"); -1 // TODO: remove -1 type hack\n }\n val n = math.max(captureWidth, updateWidth)\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n val updateBits = Cat(regs.reverse)(updateWidth-1, 0)\n io.update.bits := updateBits.asTypeOf(io.update.bits)\n\n val captureBits = io.capture.bits.asUInt\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG;chain_capture; This Chain captured data\")\n property.cover(io.chainIn.capture, \"chain_update\", \"JTAG;chain_update; This Chain updated data\")\n\n when (io.chainIn.capture) {\n (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))\n (captureWidth until n) map (x => regs(x) := 0.U)\n io.capture.capture := true.B\n io.update.valid := false.B\n } .elsewhen (io.chainIn.update) {\n io.capture.capture := false.B\n io.update.valid := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n io.update.valid := false.B\n } .otherwise {\n io.capture.capture := false.B\n io.update.valid := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureUpdateChain {\n /** Capture-update chain with matching capture and update types.\n */\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)\n def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =\n new CaptureUpdateChain(genCapture, genUpdate)\n}", + "response": "module JtagBypassChain(\n input clock,\n input reset,\n input io_chainIn_shift,\n input io_chainIn_data,\n input io_chainIn_capture,\n input io_chainIn_update,\n output io_chainOut_data\n);\n\n reg reg_0;\n always @(posedge clock) begin\n if (io_chainIn_capture)\n reg_0 <= 1'h0;\n else if (io_chainIn_shift)\n reg_0 <= io_chainIn_data;\n end\n assign io_chainOut_data = reg_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_0_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [43:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [43:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_ext table_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Fetch Target Queue (FTQ)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Each entry in the FTQ holds the fetch address and branch prediction snapshot state.\n//\n// TODO:\n// * reduce port counts.\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.util.{Str}\n\nimport boom.v3.common._\nimport boom.v3.exu._\nimport boom.v3.util._\n\n/**\n * FTQ Parameters used in configurations\n *\n * @param nEntries # of entries in the FTQ\n */\ncase class FtqParameters(\n nEntries: Int = 16\n)\n\n/**\n * Bundle to add to the FTQ RAM and to be used as the pass in IO\n */\nclass FTQBundle(implicit p: Parameters) extends BoomBundle\n with HasBoomFrontendParameters\n{\n // // TODO compress out high-order bits\n // val fetch_pc = UInt(vaddrBitsExtended.W)\n // IDX of instruction that was predicted taken, if any\n val cfi_idx = Valid(UInt(log2Ceil(fetchWidth).W))\n // Was the CFI in this bundle found to be taken? or not\n val cfi_taken = Bool()\n // Was this CFI mispredicted by the branch prediction pipeline?\n val cfi_mispredicted = Bool()\n // What type of CFI was taken out of this bundle\n val cfi_type = UInt(CFI_SZ.W)\n // mask of branches which were visible in this fetch bundle\n val br_mask = UInt(fetchWidth.W)\n // This CFI is likely a CALL\n val cfi_is_call = Bool()\n // This CFI is likely a RET\n val cfi_is_ret = Bool()\n // Is the NPC after the CFI +4 or +2\n val cfi_npc_plus4 = Bool()\n // What was the top of the RAS that this bundle saw?\n val ras_top = UInt(vaddrBitsExtended.W)\n val ras_idx = UInt(log2Ceil(nRasEntries).W)\n\n // Which bank did this start from?\n val start_bank = UInt(1.W)\n\n // // Metadata for the branch predictor\n // val bpd_meta = Vec(nBanks, UInt(bpdMaxMetaLength.W))\n}\n\n/**\n * IO to provide a port for a FunctionalUnit to get the PC of an instruction.\n * And for JALRs, the PC of the next instruction.\n */\nclass GetPCFromFtqIO(implicit p: Parameters) extends BoomBundle\n{\n val ftq_idx = Input(UInt(log2Ceil(ftqSz).W))\n\n val entry = Output(new FTQBundle)\n val ghist = Output(new GlobalHistory)\n\n val pc = Output(UInt(vaddrBitsExtended.W))\n val com_pc = Output(UInt(vaddrBitsExtended.W))\n\n // the next_pc may not be valid (stalled or still being fetched)\n val next_val = Output(Bool())\n val next_pc = Output(UInt(vaddrBitsExtended.W))\n}\n\n/**\n * Queue to store the fetch PC and other relevant branch predictor signals that are inflight in the\n * processor.\n *\n * @param num_entries # of entries in the FTQ\n */\nclass FetchTargetQueue(implicit p: Parameters) extends BoomModule\n with HasBoomCoreParameters\n with HasBoomFrontendParameters\n{\n val num_entries = ftqSz\n private val idx_sz = log2Ceil(num_entries)\n\n val io = IO(new BoomBundle {\n // Enqueue one entry for every fetch cycle.\n val enq = Flipped(Decoupled(new FetchBundle()))\n // Pass to FetchBuffer (newly fetched instructions).\n val enq_idx = Output(UInt(idx_sz.W))\n // ROB tells us the youngest committed ftq_idx to remove from FTQ.\n val deq = Flipped(Valid(UInt(idx_sz.W)))\n\n // Give PC info to BranchUnit.\n val get_ftq_pc = Vec(2, new GetPCFromFtqIO())\n\n\n // Used to regenerate PC for trace port stuff in FireSim\n // Don't tape this out, this blows up the FTQ\n val debug_ftq_idx = Input(Vec(coreWidth, UInt(log2Ceil(ftqSz).W)))\n val debug_fetch_pc = Output(Vec(coreWidth, UInt(vaddrBitsExtended.W)))\n\n val redirect = Input(Valid(UInt(idx_sz.W)))\n\n val brupdate = Input(new BrUpdateInfo)\n\n val bpdupdate = Output(Valid(new BranchPredictionUpdate))\n\n val ras_update = Output(Bool())\n val ras_update_idx = Output(UInt(log2Ceil(nRasEntries).W))\n val ras_update_pc = Output(UInt(vaddrBitsExtended.W))\n\n })\n val bpd_ptr = RegInit(0.U(idx_sz.W))\n val deq_ptr = RegInit(0.U(idx_sz.W))\n val enq_ptr = RegInit(1.U(idx_sz.W))\n\n val full = ((WrapInc(WrapInc(enq_ptr, num_entries), num_entries) === bpd_ptr) ||\n (WrapInc(enq_ptr, num_entries) === bpd_ptr))\n\n\n val pcs = Reg(Vec(num_entries, UInt(vaddrBitsExtended.W)))\n val meta = SyncReadMem(num_entries, Vec(nBanks, UInt(bpdMaxMetaLength.W)))\n val ram = Reg(Vec(num_entries, new FTQBundle))\n val ghist = Seq.fill(2) { SyncReadMem(num_entries, new GlobalHistory) }\n val lhist = if (useLHist) {\n Some(SyncReadMem(num_entries, Vec(nBanks, UInt(localHistoryLength.W))))\n } else {\n None\n }\n\n val do_enq = io.enq.fire\n\n\n // This register lets us initialize the ghist to 0\n val prev_ghist = RegInit((0.U).asTypeOf(new GlobalHistory))\n val prev_entry = RegInit((0.U).asTypeOf(new FTQBundle))\n val prev_pc = RegInit(0.U(vaddrBitsExtended.W))\n when (do_enq) {\n\n pcs(enq_ptr) := io.enq.bits.pc\n\n val new_entry = Wire(new FTQBundle)\n\n new_entry.cfi_idx := io.enq.bits.cfi_idx\n // Initially, if we see a CFI, it is assumed to be taken.\n // Branch resolutions may change this\n new_entry.cfi_taken := io.enq.bits.cfi_idx.valid\n new_entry.cfi_mispredicted := false.B\n new_entry.cfi_type := io.enq.bits.cfi_type\n new_entry.cfi_is_call := io.enq.bits.cfi_is_call\n new_entry.cfi_is_ret := io.enq.bits.cfi_is_ret\n new_entry.cfi_npc_plus4 := io.enq.bits.cfi_npc_plus4\n new_entry.ras_top := io.enq.bits.ras_top\n new_entry.ras_idx := io.enq.bits.ghist.ras_idx\n new_entry.br_mask := io.enq.bits.br_mask & io.enq.bits.mask\n new_entry.start_bank := bank(io.enq.bits.pc)\n\n val new_ghist = Mux(io.enq.bits.ghist.current_saw_branch_not_taken,\n io.enq.bits.ghist,\n prev_ghist.update(\n prev_entry.br_mask,\n prev_entry.cfi_taken,\n prev_entry.br_mask(prev_entry.cfi_idx.bits),\n prev_entry.cfi_idx.bits,\n prev_entry.cfi_idx.valid,\n prev_pc,\n prev_entry.cfi_is_call,\n prev_entry.cfi_is_ret\n )\n )\n\n lhist.map( l => l.write(enq_ptr, io.enq.bits.lhist))\n ghist.map( g => g.write(enq_ptr, new_ghist))\n meta.write(enq_ptr, io.enq.bits.bpd_meta)\n ram(enq_ptr) := new_entry\n\n prev_pc := io.enq.bits.pc\n prev_entry := new_entry\n prev_ghist := new_ghist\n\n enq_ptr := WrapInc(enq_ptr, num_entries)\n }\n\n io.enq_idx := enq_ptr\n\n io.bpdupdate.valid := false.B\n io.bpdupdate.bits := DontCare\n\n when (io.deq.valid) {\n deq_ptr := io.deq.bits\n }\n\n // This register avoids a spurious bpd update on the first fetch packet\n val first_empty = RegInit(true.B)\n\n // We can update the branch predictors when we know the target of the\n // CFI in this fetch bundle\n\n val ras_update = WireInit(false.B)\n val ras_update_pc = WireInit(0.U(vaddrBitsExtended.W))\n val ras_update_idx = WireInit(0.U(log2Ceil(nRasEntries).W))\n io.ras_update := RegNext(ras_update)\n io.ras_update_pc := RegNext(ras_update_pc)\n io.ras_update_idx := RegNext(ras_update_idx)\n\n val bpd_update_mispredict = RegInit(false.B)\n val bpd_update_repair = RegInit(false.B)\n val bpd_repair_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_end_idx = Reg(UInt(log2Ceil(ftqSz).W))\n val bpd_repair_pc = Reg(UInt(vaddrBitsExtended.W))\n\n val bpd_idx = Mux(io.redirect.valid, io.redirect.bits,\n Mux(bpd_update_repair || bpd_update_mispredict, bpd_repair_idx, bpd_ptr))\n val bpd_entry = RegNext(ram(bpd_idx))\n val bpd_ghist = ghist(0).read(bpd_idx, true.B)\n val bpd_lhist = if (useLHist) {\n lhist.get.read(bpd_idx, true.B)\n } else {\n VecInit(Seq.fill(nBanks) { 0.U })\n }\n val bpd_meta = meta.read(bpd_idx, true.B) // TODO fix these SRAMs\n val bpd_pc = RegNext(pcs(bpd_idx))\n val bpd_target = RegNext(pcs(WrapInc(bpd_idx, num_entries)))\n\n when (io.redirect.valid) {\n bpd_update_mispredict := false.B\n bpd_update_repair := false.B\n } .elsewhen (RegNext(io.brupdate.b2.mispredict)) {\n bpd_update_mispredict := true.B\n bpd_repair_idx := RegNext(io.brupdate.b2.uop.ftq_idx)\n bpd_end_idx := RegNext(enq_ptr)\n } .elsewhen (bpd_update_mispredict) {\n bpd_update_mispredict := false.B\n bpd_update_repair := true.B\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair && RegNext(bpd_update_mispredict)) {\n bpd_repair_pc := bpd_pc\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n } .elsewhen (bpd_update_repair) {\n bpd_repair_idx := WrapInc(bpd_repair_idx, num_entries)\n when (WrapInc(bpd_repair_idx, num_entries) === bpd_end_idx ||\n bpd_pc === bpd_repair_pc) {\n bpd_update_repair := false.B\n }\n\n }\n\n\n val do_commit_update = (!bpd_update_mispredict &&\n !bpd_update_repair &&\n bpd_ptr =/= deq_ptr &&\n enq_ptr =/= WrapInc(bpd_ptr, num_entries) &&\n !io.brupdate.b2.mispredict &&\n !io.redirect.valid && !RegNext(io.redirect.valid))\n val do_mispredict_update = bpd_update_mispredict\n val do_repair_update = bpd_update_repair\n\n when (RegNext(do_commit_update || do_repair_update || do_mispredict_update)) {\n val cfi_idx = bpd_entry.cfi_idx.bits\n val valid_repair = bpd_pc =/= bpd_repair_pc\n\n io.bpdupdate.valid := (!first_empty &&\n (bpd_entry.cfi_idx.valid || bpd_entry.br_mask =/= 0.U) &&\n !(RegNext(do_repair_update) && !valid_repair))\n io.bpdupdate.bits.is_mispredict_update := RegNext(do_mispredict_update)\n io.bpdupdate.bits.is_repair_update := RegNext(do_repair_update)\n io.bpdupdate.bits.pc := bpd_pc\n io.bpdupdate.bits.btb_mispredicts := 0.U\n io.bpdupdate.bits.br_mask := Mux(bpd_entry.cfi_idx.valid,\n MaskLower(UIntToOH(cfi_idx)) & bpd_entry.br_mask, bpd_entry.br_mask)\n io.bpdupdate.bits.cfi_idx := bpd_entry.cfi_idx\n io.bpdupdate.bits.cfi_mispredicted := bpd_entry.cfi_mispredicted\n io.bpdupdate.bits.cfi_taken := bpd_entry.cfi_taken\n io.bpdupdate.bits.target := bpd_target\n io.bpdupdate.bits.cfi_is_br := bpd_entry.br_mask(cfi_idx)\n io.bpdupdate.bits.cfi_is_jal := bpd_entry.cfi_type === CFI_JAL || bpd_entry.cfi_type === CFI_JALR\n io.bpdupdate.bits.ghist := bpd_ghist\n io.bpdupdate.bits.lhist := bpd_lhist\n io.bpdupdate.bits.meta := bpd_meta\n\n first_empty := false.B\n }\n\n when (do_commit_update) {\n bpd_ptr := WrapInc(bpd_ptr, num_entries)\n }\n\n io.enq.ready := RegNext(!full || do_commit_update)\n\n val redirect_idx = io.redirect.bits\n val redirect_entry = ram(redirect_idx)\n val redirect_new_entry = WireInit(redirect_entry)\n\n when (io.redirect.valid) {\n enq_ptr := WrapInc(io.redirect.bits, num_entries)\n\n when (io.brupdate.b2.mispredict) {\n val new_cfi_idx = (io.brupdate.b2.uop.pc_lob ^\n Mux(redirect_entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U))(log2Ceil(fetchWidth), 1)\n redirect_new_entry.cfi_idx.valid := true.B\n redirect_new_entry.cfi_idx.bits := new_cfi_idx\n redirect_new_entry.cfi_mispredicted := true.B\n redirect_new_entry.cfi_taken := io.brupdate.b2.taken\n redirect_new_entry.cfi_is_call := redirect_entry.cfi_is_call && redirect_entry.cfi_idx.bits === new_cfi_idx\n redirect_new_entry.cfi_is_ret := redirect_entry.cfi_is_ret && redirect_entry.cfi_idx.bits === new_cfi_idx\n }\n\n ras_update := true.B\n ras_update_pc := redirect_entry.ras_top\n ras_update_idx := redirect_entry.ras_idx\n\n } .elsewhen (RegNext(io.redirect.valid)) {\n prev_entry := RegNext(redirect_new_entry)\n prev_ghist := bpd_ghist\n prev_pc := bpd_pc\n\n ram(RegNext(io.redirect.bits)) := RegNext(redirect_new_entry)\n }\n\n //-------------------------------------------------------------\n // **** Core Read PCs ****\n //-------------------------------------------------------------\n\n for (i <- 0 until 2) {\n val idx = io.get_ftq_pc(i).ftq_idx\n val next_idx = WrapInc(idx, num_entries)\n val next_is_enq = (next_idx === enq_ptr) && io.enq.fire\n val next_pc = Mux(next_is_enq, io.enq.bits.pc, pcs(next_idx))\n val get_entry = ram(idx)\n val next_entry = ram(next_idx)\n io.get_ftq_pc(i).entry := RegNext(get_entry)\n if (i == 1)\n io.get_ftq_pc(i).ghist := ghist(1).read(idx, true.B)\n else\n io.get_ftq_pc(i).ghist := DontCare\n io.get_ftq_pc(i).pc := RegNext(pcs(idx))\n io.get_ftq_pc(i).next_pc := RegNext(next_pc)\n io.get_ftq_pc(i).next_val := RegNext(next_idx =/= enq_ptr || next_is_enq)\n io.get_ftq_pc(i).com_pc := RegNext(pcs(Mux(io.deq.valid, io.deq.bits, deq_ptr)))\n }\n\n for (w <- 0 until coreWidth) {\n io.debug_fetch_pc(w) := RegNext(pcs(io.debug_ftq_idx(w)))\n }\n}", + "response": "module ghist_0(\n input [3:0] R0_addr,\n input R0_clk,\n output [71:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [71:0] W0_data\n);\n\n ghist_0_ext ghist_0_ext (\n .R0_addr (R0_addr),\n .R0_en (1'h1),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\nobject JtagState {\n sealed abstract class State(val id: Int) {\n def U: UInt = id.U(State.width.W)\n }\n\n object State {\n import scala.language.implicitConversions\n\n implicit def toInt(x: State) = x.id\n implicit def toBigInt(x: State):BigInt = x.id\n\n // TODO: this could be automatically generated with macros and stuff\n val all: Set[State] = Set(\n TestLogicReset,\n RunTestIdle,\n SelectDRScan,\n CaptureDR,\n ShiftDR,\n Exit1DR,\n PauseDR,\n Exit2DR,\n UpdateDR,\n SelectIRScan,\n CaptureIR,\n ShiftIR,\n Exit1IR,\n PauseIR,\n Exit2IR,\n UpdateIR\n )\n val width = log2Ceil(all.size)\n def chiselType() = UInt(width.W)\n }\n\n // States as described in 6.1.1.2, numeric assignments from example in Table 6-3\n case object TestLogicReset extends State(15) // no effect on system logic, entered when TMS high for 5 TCK rising edges\n case object RunTestIdle extends State(12) // runs active instruction (which can be idle)\n case object SelectDRScan extends State(7)\n case object CaptureDR extends State(6) // parallel-load DR shifter when exiting this state (if required)\n case object ShiftDR extends State(2) // shifts DR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state\n case object Exit1DR extends State(1)\n case object PauseDR extends State(3) // pause DR shifting\n case object Exit2DR extends State(0)\n case object UpdateDR extends State(5) // parallel-load output from DR shifter on TCK falling edge while in this state (not a rule?)\n case object SelectIRScan extends State(4)\n case object CaptureIR extends State(14) // parallel-load IR shifter with fixed logic values and design-specific when exiting this state (if required)\n case object ShiftIR extends State(10) // shifts IR shifter from TDI towards TDO, last shift occurs on rising edge transition out of this state\n case object Exit1IR extends State(9)\n case object PauseIR extends State(11) // pause IR shifting\n case object Exit2IR extends State(8)\n case object UpdateIR extends State(13) // latch IR shifter into IR (changes to IR may only occur while in this state, latch on TCK falling edge)\n}\n\n/** The JTAG state machine, implements spec 6.1.1.1a (Figure 6.1)\n *\n * Usage notes:\n * - 6.1.1.1b state transitions occur on TCK rising edge\n * - 6.1.1.1c actions can occur on the following TCK falling or rising edge\n *\n */\nclass JtagStateMachine(implicit val p: Parameters) extends Module() {\n class StateMachineIO extends Bundle {\n val tms = Input(Bool())\n val currState = Output(JtagState.State.chiselType())\n }\n val io = IO(new StateMachineIO)\n\n val nextState = WireInit(JtagState.TestLogicReset.U)\n val currState = RegNext(next=nextState, init=JtagState.TestLogicReset.U)\n\n switch (currState) {\n is (JtagState.TestLogicReset.U) {\n nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.RunTestIdle.U)\n }\n is (JtagState.RunTestIdle.U) {\n nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)\n }\n is (JtagState.SelectDRScan.U) {\n nextState := Mux(io.tms, JtagState.SelectIRScan.U, JtagState.CaptureDR.U)\n }\n is (JtagState.CaptureDR.U) {\n nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)\n }\n is (JtagState.ShiftDR.U) {\n nextState := Mux(io.tms, JtagState.Exit1DR.U, JtagState.ShiftDR.U)\n }\n is (JtagState.Exit1DR.U) {\n nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.PauseDR.U)\n }\n is (JtagState.PauseDR.U) {\n nextState := Mux(io.tms, JtagState.Exit2DR.U, JtagState.PauseDR.U)\n }\n is (JtagState.Exit2DR.U) {\n nextState := Mux(io.tms, JtagState.UpdateDR.U, JtagState.ShiftDR.U)\n }\n is (JtagState.UpdateDR.U) {\n nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)\n }\n is (JtagState.SelectIRScan.U) {\n nextState := Mux(io.tms, JtagState.TestLogicReset.U, JtagState.CaptureIR.U)\n }\n is (JtagState.CaptureIR.U) {\n nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)\n }\n is (JtagState.ShiftIR.U) {\n nextState := Mux(io.tms, JtagState.Exit1IR.U, JtagState.ShiftIR.U)\n }\n is (JtagState.Exit1IR.U) {\n nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.PauseIR.U)\n }\n is (JtagState.PauseIR.U) {\n nextState := Mux(io.tms, JtagState.Exit2IR.U, JtagState.PauseIR.U)\n }\n is (JtagState.Exit2IR.U) {\n nextState := Mux(io.tms, JtagState.UpdateIR.U, JtagState.ShiftIR.U)\n }\n is (JtagState.UpdateIR.U) {\n nextState := Mux(io.tms, JtagState.SelectDRScan.U, JtagState.RunTestIdle.U)\n }\n }\n\n io.currState := currState\n\n // Generate Coverate Points\n JtagState.State.all.foreach { s =>\n property.cover (currState === s.U && io.tms === true.B, s\"${s.toString}_tms_1\", s\"JTAG; ${s.toString} with TMS = 1; State Transition from ${s.toString} with TMS = 1\")\n property.cover (currState === s.U && io.tms === false.B, s\"${s.toString}_tms_0\", s\"JTAG; ${s.toString} with TMS = 0; State Transition from ${s.toString} with TMS = 0\")\n property.cover (currState === s.U && reset.asBool === true.B, s\"${s.toString}_reset\", s\"JTAG; ${s.toString} with reset; JTAG Reset asserted during ${s.toString}\")\n \n }\n\n}", + "response": "module JtagStateMachine(\n input clock,\n input reset,\n input io_tms,\n output [3:0] io_currState\n);\n\n reg [3:0] currState;\n wire [15:0][3:0] _GEN = {{io_tms ? 4'hF : 4'hC}, {io_tms ? 4'h9 : 4'hA}, {io_tms ? 4'h7 : 4'hC}, {io_tms ? 4'h7 : 4'hC}, {io_tms ? 4'h8 : 4'hB}, {io_tms ? 4'h9 : 4'hA}, {io_tms ? 4'hD : 4'hB}, {io_tms ? 4'hD : 4'hA}, {{2'h1, ~io_tms, 1'h0}}, {io_tms ? 4'h1 : 4'h2}, {io_tms ? 4'h7 : 4'hC}, {{3'h7, io_tms}}, {io_tms ? 4'h0 : 4'h3}, {io_tms ? 4'h1 : 4'h2}, {io_tms ? 4'h5 : 4'h3}, {io_tms ? 4'h5 : 4'h2}};\n always @(posedge clock or posedge reset) begin\n if (reset)\n currState <= 4'hF;\n else\n currState <= _GEN[currState];\n end\n assign io_currState = currState;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.regmapper\n\nimport chisel3._\nimport chisel3.experimental.SourceInfo\nimport chisel3.util._\n\nimport freechips.rocketchip.diplomacy.AddressDecoder\n\nimport freechips.rocketchip.util.{BundleFieldBase, BundleMap, MuxSeq, ReduceOthers, property}\n\n// A bus agnostic register interface to a register-based device\ncase class RegMapperParams(indexBits: Int, maskBits: Int, extraFields: Seq[BundleFieldBase] = Nil)\n\nclass RegMapperInput(val params: RegMapperParams) extends Bundle\n{\n val read = Bool()\n val index = UInt((params.indexBits).W)\n val data = UInt((params.maskBits*8).W)\n val mask = UInt((params.maskBits).W)\n val extra = BundleMap(params.extraFields)\n}\n\nclass RegMapperOutput(val params: RegMapperParams) extends Bundle\n{\n val read = Bool()\n val data = UInt((params.maskBits*8).W)\n val extra = BundleMap(params.extraFields)\n}\n\nobject RegMapper\n{\n // Create a generic register-based device\n def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*)(implicit sourceInfo: SourceInfo) = {\n // Filter out zero-width fields\n val bytemap = mapping.toList.map { case (offset, fields) => (offset, fields.filter(_.width != 0)) }\n\n // Negative addresses are bad\n bytemap.foreach { byte => require (byte._1 >= 0) }\n\n // Transform all fields into bit offsets Seq[(bit, field)]\n val bitmap = bytemap.map { case (byte, fields) =>\n val bits = fields.scanLeft(byte * 8)(_ + _.width).init\n bits zip fields\n }.flatten.sortBy(_._1)\n\n // Detect overlaps\n (bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>\n require (lbit + lfield.width <= rbit, s\"Register map overlaps at bit ${rbit}.\")\n }\n\n // Group those fields into bus words Map[word, List[(bit, field)]]\n val wordmap = bitmap.groupBy(_._1 / (8*bytes))\n\n // Make sure registers fit\n val inParams = in.bits.params\n val inBits = inParams.indexBits\n assert (wordmap.keySet.max < (1 << inBits), \"Register map does not fit in device\")\n\n val out = Wire(Decoupled(new RegMapperOutput(inParams)))\n val front = Wire(Decoupled(new RegMapperInput(inParams)))\n front.bits := in.bits\n\n // Must this device pipeline the control channel?\n val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)\n val depth = concurrency\n require (depth >= 0)\n require (!pipelined || depth > 0, \"Register-based device with request/response handshaking needs concurrency > 0\")\n val back = if (depth > 0) {\n val front_q = Module(new Queue(new RegMapperInput(inParams), depth) {\n override def desiredName = s\"Queue${depth}_${front.bits.typeName}_i${inParams.indexBits}_m${inParams.maskBits}\"\n })\n front_q.io.enq <> front\n front_q.io.deq\n } else front\n\n // Convert to and from Bits\n def toBits(x: Int, tail: List[Boolean] = List.empty): List[Boolean] =\n if (x == 0) tail.reverse else toBits(x >> 1, ((x & 1) == 1) :: tail)\n def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }\n\n // Find the minimal mask that can decide the register map\n val mask = AddressDecoder(wordmap.keySet.toList)\n val maskMatch = ~mask.U(inBits.W)\n val maskFilter = toBits(mask)\n val maskBits = maskFilter.filter(x => x).size\n\n // Calculate size and indexes into the register map\n val regSize = 1 << maskBits\n def regIndexI(x: Int) = ofBits((maskFilter zip toBits(x)).filter(_._1).map(_._2))\n def regIndexU(x: UInt) = if (maskBits == 0) 0.U else\n Cat((maskFilter zip x.asBools).filter(_._1).map(_._2).reverse)\n\n val findex = front.bits.index & maskMatch\n val bindex = back .bits.index & maskMatch\n\n // Protection flag for undefined registers\n val iRightReg = Array.fill(regSize) { true.B }\n val oRightReg = Array.fill(regSize) { true.B }\n\n // Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]\n val flat = wordmap.toList.map { case (word, fields) =>\n val index = regIndexI(word)\n if (undefZero) {\n val uint = (word & ~mask).U(inBits.W)\n iRightReg(index) = findex === uint\n oRightReg(index) = bindex === uint\n }\n // Confirm that no field spans a word boundary\n fields foreach { case (bit, field) =>\n val off = bit - 8*bytes*word\n // println(s\"Reg ${word}: [${off}, ${off+field.width})\")\n require (off + field.width <= bytes * 8, s\"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.\")\n }\n // println(\"mapping 0x%x -> 0x%x for 0x%x/%d\".format(word, index, mask, maskBits))\n fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }\n }.flatten\n\n // Forward declaration of all flow control signals\n val rivalid = Wire(Vec(flat.size, Bool()))\n val wivalid = Wire(Vec(flat.size, Bool()))\n val roready = Wire(Vec(flat.size, Bool()))\n val woready = Wire(Vec(flat.size, Bool()))\n\n // Per-register list of all control signals needed for data to flow\n val rifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val wifire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val rofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n val wofire = Array.fill(regSize) { Nil:List[(Bool, Bool)] }\n\n // The output values for each register\n val dataOut = Array.fill(regSize) { 0.U }\n\n // Which bits are touched?\n val frontMask = FillInterleaved(8, front.bits.mask)\n val backMask = FillInterleaved(8, back .bits.mask)\n\n // Connect the fields\n for (i <- 0 until flat.size) {\n val (reg, low, field) = flat(i)\n val high = low + field.width - 1\n // Confirm that no register is too big\n require (high < 8*bytes)\n val rimask = frontMask(high, low).orR\n val wimask = frontMask(high, low).andR\n val romask = backMask(high, low).orR\n val womask = backMask(high, low).andR\n val data = if (field.write.combinational) back.bits.data else front.bits.data\n val f_rivalid = rivalid(i) && rimask\n val f_roready = roready(i) && romask\n val f_wivalid = wivalid(i) && wimask\n val f_woready = woready(i) && womask\n val (f_riready, f_rovalid, f_data) = field.read.fn(f_rivalid, f_roready)\n val (f_wiready, f_wovalid) = field.write.fn(f_wivalid, f_woready, data(high, low))\n\n // cover reads and writes to register\n val fname = field.desc.map{_.name}.getOrElse(\"\")\n val fdesc = field.desc.map{_.desc + \":\"}.getOrElse(\"\")\n\n val facct = field.desc.map{_.access}.getOrElse(\"\")\n if((facct == RegFieldAccessType.R) || (facct == RegFieldAccessType.RW)) {\n property.cover(f_rivalid && f_riready, fname + \"_Reg_read_start\", fdesc + \" RegField Read Request Initiate\")\n property.cover(f_rovalid && f_roready, fname + \"_Reg_read_out\", fdesc + \" RegField Read Request Complete\")\n }\n if((facct == RegFieldAccessType.W) || (facct == RegFieldAccessType.RW)) {\n property.cover(f_wivalid && f_wiready, fname + \"_Reg_write_start\", fdesc + \" RegField Write Request Initiate\")\n property.cover(f_wovalid && f_woready, fname + \"_Reg_write_out\", fdesc + \" RegField Write Request Complete\")\n }\n\n def litOR(x: Bool, y: Bool) = if (x.isLit && x.litValue == 1) true.B else x || y\n // Add this field to the ready-valid signals for the register\n rifire(reg) = (rivalid(i), litOR(f_riready, !rimask)) +: rifire(reg)\n wifire(reg) = (wivalid(i), litOR(f_wiready, !wimask)) +: wifire(reg)\n rofire(reg) = (roready(i), litOR(f_rovalid, !romask)) +: rofire(reg)\n wofire(reg) = (woready(i), litOR(f_wovalid, !womask)) +: wofire(reg)\n\n // ... this loop iterates from smallest to largest bit offset\n val prepend = if (low == 0) { f_data } else { Cat(f_data, dataOut(reg) | 0.U(low.W)) }\n dataOut(reg) = (prepend | 0.U((high+1).W))(high, 0)\n }\n\n // Which register is touched?\n val iindex = regIndexU(front.bits.index)\n val oindex = regIndexU(back .bits.index)\n val frontSel = UIntToOH(iindex).asBools\n val backSel = UIntToOH(oindex).asBools\n\n // Compute: is the selected register ready? ... and cross-connect all ready-valids\n def mux(index: UInt, valid: Bool, select: Seq[Bool], guard: Seq[Bool], flow: Seq[Seq[(Bool, Bool)]]): Bool =\n MuxSeq(index, true.B, ((select zip guard) zip flow).map { case ((s, g), f) =>\n val out = Wire(Bool())\n ReduceOthers((out, valid && s && g) +: f)\n out || !g\n })\n\n // Include the per-register one-hot selected criteria\n val rifireMux = mux(iindex, in.valid && front.ready && front.bits.read, frontSel, iRightReg, rifire)\n val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)\n val rofireMux = mux(oindex, back.valid && out.ready && back .bits.read, backSel, oRightReg, rofire)\n val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel, oRightReg, wofire)\n\n val iready = Mux(front.bits.read, rifireMux, wifireMux)\n val oready = Mux(back .bits.read, rofireMux, wofireMux)\n\n // Connect the pipeline\n in.ready := front.ready && iready\n front.valid := in.valid && iready\n back.ready := out.ready && oready\n out.valid := back.valid && oready\n\n out.bits.read := back.bits.read\n out.bits.data := Mux(MuxSeq(oindex, true.B, oRightReg),\n MuxSeq(oindex, 0.U, dataOut),\n 0.U)\n out.bits.extra := back.bits.extra\n\n out\n }\n}", + "response": "module Queue1_RegMapperInput_i9_m8(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input io_enq_bits_read,\n input [8:0] io_enq_bits_index,\n input [63:0] io_enq_bits_data,\n input [7:0] io_enq_bits_mask,\n input [10:0] io_enq_bits_extra_tlrr_extra_source,\n input [1:0] io_enq_bits_extra_tlrr_extra_size,\n input io_deq_ready,\n output io_deq_valid,\n output io_deq_bits_read,\n output [8:0] io_deq_bits_index,\n output [7:0] io_deq_bits_mask,\n output [10:0] io_deq_bits_extra_tlrr_extra_source,\n output [1:0] io_deq_bits_extra_tlrr_extra_size\n);\n\n reg [94:0] ram;\n reg full;\n wire do_enq = ~full & io_enq_valid;\n always @(posedge clock) begin\n if (do_enq)\n ram <= {io_enq_bits_extra_tlrr_extra_size, io_enq_bits_extra_tlrr_extra_source, io_enq_bits_mask, io_enq_bits_data, io_enq_bits_index, io_enq_bits_read};\n if (reset)\n full <= 1'h0;\n else if (~(do_enq == (io_deq_ready & full)))\n full <= do_enq;\n end\n assign io_enq_ready = ~full;\n assign io_deq_valid = full;\n assign io_deq_bits_read = ram[0];\n assign io_deq_bits_index = ram[9:1];\n assign io_deq_bits_mask = ram[81:74];\n assign io_deq_bits_extra_tlrr_extra_source = ram[92:82];\n assign io_deq_bits_extra_tlrr_extra_size = ram[94:93];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2017 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.subsystem._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property._\n\n\nimport boom.v3.common._\nimport boom.v3.exu.{CommitExceptionSignals, BranchDecode, BrUpdateInfo}\nimport boom.v3.util._\n\nclass BoomRAS(implicit p: Parameters) extends BoomModule()(p)\n{\n val io = IO(new Bundle {\n val read_idx = Input(UInt(log2Ceil(nRasEntries).W))\n val read_addr = Output(UInt(vaddrBitsExtended.W))\n\n val write_valid = Input(Bool())\n val write_idx = Input(UInt(log2Ceil(nRasEntries).W))\n val write_addr = Input(UInt(vaddrBitsExtended.W))\n })\n val ras = Reg(Vec(nRasEntries, UInt(vaddrBitsExtended.W)))\n\n io.read_addr := Mux(RegNext(io.write_valid && io.write_idx === io.read_idx),\n RegNext(io.write_addr),\n RegNext(ras(io.read_idx)))\n\n when (io.write_valid) {\n ras(io.write_idx) := io.write_addr\n }\n\n\n}", + "response": "module BoomRAS(\n input clock,\n input [4:0] io_read_idx,\n output [39:0] io_read_addr,\n input io_write_valid,\n input [4:0] io_write_idx,\n input [39:0] io_write_addr\n);\n\n reg [39:0] ras_0;\n reg [39:0] ras_1;\n reg [39:0] ras_2;\n reg [39:0] ras_3;\n reg [39:0] ras_4;\n reg [39:0] ras_5;\n reg [39:0] ras_6;\n reg [39:0] ras_7;\n reg [39:0] ras_8;\n reg [39:0] ras_9;\n reg [39:0] ras_10;\n reg [39:0] ras_11;\n reg [39:0] ras_12;\n reg [39:0] ras_13;\n reg [39:0] ras_14;\n reg [39:0] ras_15;\n reg [39:0] ras_16;\n reg [39:0] ras_17;\n reg [39:0] ras_18;\n reg [39:0] ras_19;\n reg [39:0] ras_20;\n reg [39:0] ras_21;\n reg [39:0] ras_22;\n reg [39:0] ras_23;\n reg [39:0] ras_24;\n reg [39:0] ras_25;\n reg [39:0] ras_26;\n reg [39:0] ras_27;\n reg [39:0] ras_28;\n reg [39:0] ras_29;\n reg [39:0] ras_30;\n reg [39:0] ras_31;\n reg io_read_addr_REG;\n reg [39:0] io_read_addr_REG_1;\n reg [39:0] io_read_addr_REG_2;\n wire [31:0][39:0] _GEN = {{ras_31}, {ras_30}, {ras_29}, {ras_28}, {ras_27}, {ras_26}, {ras_25}, {ras_24}, {ras_23}, {ras_22}, {ras_21}, {ras_20}, {ras_19}, {ras_18}, {ras_17}, {ras_16}, {ras_15}, {ras_14}, {ras_13}, {ras_12}, {ras_11}, {ras_10}, {ras_9}, {ras_8}, {ras_7}, {ras_6}, {ras_5}, {ras_4}, {ras_3}, {ras_2}, {ras_1}, {ras_0}};\n always @(posedge clock) begin\n if (io_write_valid & io_write_idx == 5'h0)\n ras_0 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1)\n ras_1 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h2)\n ras_2 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h3)\n ras_3 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h4)\n ras_4 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h5)\n ras_5 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h6)\n ras_6 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h7)\n ras_7 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h8)\n ras_8 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h9)\n ras_9 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hA)\n ras_10 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hB)\n ras_11 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hC)\n ras_12 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hD)\n ras_13 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hE)\n ras_14 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'hF)\n ras_15 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h10)\n ras_16 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h11)\n ras_17 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h12)\n ras_18 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h13)\n ras_19 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h14)\n ras_20 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h15)\n ras_21 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h16)\n ras_22 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h17)\n ras_23 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h18)\n ras_24 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h19)\n ras_25 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1A)\n ras_26 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1B)\n ras_27 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1C)\n ras_28 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1D)\n ras_29 <= io_write_addr;\n if (io_write_valid & io_write_idx == 5'h1E)\n ras_30 <= io_write_addr;\n if (io_write_valid & (&io_write_idx))\n ras_31 <= io_write_addr;\n io_read_addr_REG <= io_write_valid & io_write_idx == io_read_idx;\n io_read_addr_REG_1 <= io_write_addr;\n io_read_addr_REG_2 <= _GEN[io_read_idx];\n end\n assign io_read_addr = io_read_addr_REG ? io_read_addr_REG_1 : io_read_addr_REG_2;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitDemux_p32_f32_n5_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_phit,\n input io_out_0_ready,\n output io_out_0_valid,\n output [31:0] io_out_0_bits_phit,\n input io_out_1_ready,\n output io_out_1_valid,\n output [31:0] io_out_1_bits_phit,\n input io_out_2_ready,\n output io_out_2_valid,\n output [31:0] io_out_2_bits_phit,\n input io_out_3_ready,\n output io_out_3_valid,\n output [31:0] io_out_3_bits_phit,\n input io_out_4_ready,\n output io_out_4_valid,\n output [31:0] io_out_4_bits_phit\n);\n\n reg beat;\n reg [31:0] channel_vec_0;\n wire [7:0] _GEN = {{io_out_0_ready}, {io_out_0_ready}, {io_out_0_ready}, {io_out_4_ready}, {io_out_3_ready}, {io_out_2_ready}, {io_out_1_ready}, {io_out_0_ready}};\n wire io_in_ready_0 = ~beat | _GEN[channel_vec_0[2:0]];\n wire _GEN_0 = io_in_ready_0 & io_in_valid;\n always @(posedge clock) begin\n if (reset)\n beat <= 1'h0;\n else if (_GEN_0)\n beat <= ~beat & beat - 1'h1;\n if (_GEN_0 & ~beat)\n channel_vec_0 <= io_in_bits_phit;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_0_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h0;\n assign io_out_0_bits_phit = io_in_bits_phit;\n assign io_out_1_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h1;\n assign io_out_1_bits_phit = io_in_bits_phit;\n assign io_out_2_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h2;\n assign io_out_2_bits_phit = io_in_bits_phit;\n assign io_out_3_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h3;\n assign io_out_3_bits_phit = io_in_bits_phit;\n assign io_out_4_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h4;\n assign io_out_4_bits_phit = io_in_bits_phit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module FlitToPhit_f32_p32(\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_phit\n);\n\n assign io_in_ready = io_out_ready;\n assign io_out_valid = io_in_valid;\n assign io_out_bits_phit = io_in_bits_flit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module MulAddRecFNPipe_l2_e8_s24(\n input clock,\n input reset,\n input io_validin,\n input [1:0] io_op,\n input [32:0] io_a,\n input [32:0] io_b,\n input [32:0] io_c,\n input [2:0] io_roundingMode,\n output [32:0] io_out,\n output [4:0] io_exceptionFlags,\n output io_validout\n);\n\n wire _mulAddRecFNToRaw_postMul_io_invalidExc;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA;\n wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB;\n wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;\n reg [9:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;\n reg [4:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;\n reg [25:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;\n reg [48:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;\n reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;\n reg [2:0] roundingMode_stage0_pipe_b;\n reg valid_stage0_pipe_v;\n reg roundRawFNToRecFN_io_invalidExc_pipe_b;\n reg roundRawFNToRecFN_io_in_pipe_b_isNaN;\n reg roundRawFNToRecFN_io_in_pipe_b_isInf;\n reg roundRawFNToRecFN_io_in_pipe_b_isZero;\n reg roundRawFNToRecFN_io_in_pipe_b_sign;\n reg [9:0] roundRawFNToRecFN_io_in_pipe_b_sExp;\n reg [26:0] roundRawFNToRecFN_io_in_pipe_b_sig;\n reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;\n reg io_validout_pipe_v;\n always @(posedge clock) begin\n if (io_validin) begin\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= {1'h0, {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;\n roundingMode_stage0_pipe_b <= io_roundingMode;\n end\n if (valid_stage0_pipe_v) begin\n roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;\n roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;\n end\n if (reset) begin\n valid_stage0_pipe_v <= 1'h0;\n io_validout_pipe_v <= 1'h0;\n end\n else begin\n valid_stage0_pipe_v <= io_validin;\n io_validout_pipe_v <= valid_stage0_pipe_v;\n end\n end\n MulAddRecFNToRaw_preMul_e8_s24 mulAddRecFNToRaw_preMul (\n .io_op (io_op),\n .io_a (io_a),\n .io_b (io_b),\n .io_c (io_c),\n .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),\n .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),\n .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),\n .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),\n .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),\n .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),\n .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),\n .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),\n .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),\n .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),\n .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),\n .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),\n .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),\n .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),\n .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),\n .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),\n .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),\n .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),\n .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)\n );\n MulAddRecFNToRaw_postMul_e8_s24 mulAddRecFNToRaw_postMul (\n .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),\n .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),\n .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),\n .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),\n .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),\n .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),\n .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),\n .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),\n .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),\n .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),\n .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),\n .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),\n .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),\n .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),\n .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),\n .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),\n .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),\n .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),\n .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),\n .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),\n .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),\n .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),\n .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),\n .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),\n .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN (\n .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),\n .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),\n .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),\n .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),\n .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),\n .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),\n .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),\n .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\n assign io_validout = io_validout_pipe_v;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.{Cat, Fill}\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for standard 64-bit floating-point in\n| recoded form, using a separate integer multiplier-adder. Multiple clock\n| cycles are needed for each division or square-root operation. See\n| \"docs/DivSqrtRecF64_mulAddZ31.txt\" for more details.\n*----------------------------------------------------------------------------*/\n\nclass DivSqrtRecF64ToRaw_mulAddZ31 extends Module\n{\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(UInt(3.W))\n//*** OPTIONALLY PROPAGATE:\n// val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val usingMulAdd = Output(Bits(4.W))\n val latchMulAddA_0 = Output(Bool())\n val mulAddA_0 = Output(UInt(54.W))\n val latchMulAddB_0 = Output(Bool())\n val mulAddB_0 = Output(UInt(54.W))\n val mulAddC_2 = Output(UInt(105.W))\n val mulAddResult_3 = Input(UInt(105.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(11, 55))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum_A = RegInit(0.U(3.W))\n val cycleNum_B = RegInit(0.U(4.W))\n val cycleNum_C = RegInit(0.U(3.W))\n val cycleNum_E = RegInit(0.U(3.W))\n\n val valid_PA = RegInit(false.B)\n val sqrtOp_PA = Reg(Bool())\n val majorExc_PA = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PA = Reg(Bool())\n val isInf_PA = Reg(Bool())\n val isZero_PA = Reg(Bool())\n val sign_PA = Reg(Bool())\n val sExp_PA = Reg(SInt(13.W))\n val fractB_PA = Reg(UInt(52.W))\n val fractA_PA = Reg(UInt(52.W))\n val roundingMode_PA = Reg(UInt(3.W))\n\n val valid_PB = RegInit(false.B)\n val sqrtOp_PB = Reg(Bool())\n val majorExc_PB = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PB = Reg(Bool())\n val isInf_PB = Reg(Bool())\n val isZero_PB = Reg(Bool())\n val sign_PB = Reg(Bool())\n val sExp_PB = Reg(SInt(13.W))\n val bit0FractA_PB = Reg(UInt(1.W))\n val fractB_PB = Reg(UInt(52.W))\n val roundingMode_PB = Reg(UInt(3.W))\n\n val valid_PC = RegInit(false.B)\n val sqrtOp_PC = Reg(Bool())\n val majorExc_PC = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_PC = Reg(Bool())\n val isInf_PC = Reg(Bool())\n val isZero_PC = Reg(Bool())\n val sign_PC = Reg(Bool())\n val sExp_PC = Reg(SInt(13.W))\n val bit0FractA_PC = Reg(UInt(1.W))\n val fractB_PC = Reg(UInt(52.W))\n val roundingMode_PC = Reg(UInt(3.W))\n\n val fractR0_A = Reg(UInt(9.W))\n//*** COMBINE 'hiSqrR0_A_sqrt' AND 'partNegSigma0_A'?\n val hiSqrR0_A_sqrt = Reg(UInt(10.W))\n val partNegSigma0_A = Reg(UInt(21.W))\n val nextMulAdd9A_A = Reg(UInt(9.W))\n val nextMulAdd9B_A = Reg(UInt(9.W))\n val ER1_B_sqrt = Reg(UInt(17.W))\n\n val ESqrR1_B_sqrt = Reg(UInt(32.W))\n val sigX1_B = Reg(UInt(58.W))\n val sqrSigma1_C = Reg(UInt(33.W))\n val sigXN_C = Reg(UInt(58.W))\n val u_C_sqrt = Reg(UInt(31.W))\n val E_E_div = Reg(Bool())\n val sigT_E = Reg(UInt(54.W))\n val isNegRemT_E = Reg(Bool())\n val isZeroRemT_E = Reg(Bool())\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val ready_PA = Wire(Bool())\n val ready_PB = Wire(Bool())\n val ready_PC = Wire(Bool())\n val leaving_PA = Wire(Bool())\n val leaving_PB = Wire(Bool())\n val leaving_PC = Wire(Bool())\n\n val zSigma1_B4 = Wire(UInt())\n val sigXNU_B3_CX = Wire(UInt())\n val zComplSigT_C1_sqrt = Wire(UInt())\n val zComplSigT_C1 = Wire(UInt())\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cyc_S_div = io.inReady_div && io.inValid && ! io.sqrtOp\n val cyc_S_sqrt = io.inReady_sqrt && io.inValid && io.sqrtOp\n val cyc_S = cyc_S_div || cyc_S_sqrt\n\n val rawA_S = rawFloatFromRecFN(11, 53, io.a)\n val rawB_S = rawFloatFromRecFN(11, 53, io.b)\n\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawB_S.isNaN && ! rawB_S.isZero && rawB_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawB_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawB_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawB_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawB_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = (! io.sqrtOp && rawA_S.sign) ^ rawB_S.sign\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseB_S && ! rawB_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +& (rawB_S.sExp(11) ## ~rawB_S.sExp(10, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n (Mux(((7<<9).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(12, 9)\n ) ##\n sExpQuot_S_div(8, 0)\n ).asSInt\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PA_normalCase_div = cyc_S_div && normalCase_S_div\n val entering_PA_normalCase_sqrt = cyc_S_sqrt && normalCase_S_sqrt\n val entering_PA_normalCase =\n entering_PA_normalCase_div || entering_PA_normalCase_sqrt\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering_PA_normalCase || (cycleNum_A =/= 0.U)) {\n cycleNum_A :=\n Mux(entering_PA_normalCase_div, 3.U, 0.U) |\n Mux(entering_PA_normalCase_sqrt, 6.U, 0.U) |\n Mux(! entering_PA_normalCase, cycleNum_A - 1.U, 0.U)\n }\n\n val cyc_A7_sqrt = entering_PA_normalCase_sqrt\n val cyc_A6_sqrt = (cycleNum_A === 6.U)\n val cyc_A5_sqrt = (cycleNum_A === 5.U)\n val cyc_A4_sqrt = (cycleNum_A === 4.U)\n\n val cyc_A4_div = entering_PA_normalCase_div\n\n val cyc_A4 = cyc_A4_sqrt || cyc_A4_div\n val cyc_A3 = (cycleNum_A === 3.U)\n val cyc_A2 = (cycleNum_A === 2.U)\n val cyc_A1 = (cycleNum_A === 1.U)\n\n val cyc_A3_div = cyc_A3 && ! sqrtOp_PA\n val cyc_A2_div = cyc_A2 && ! sqrtOp_PA\n val cyc_A1_div = cyc_A1 && ! sqrtOp_PA\n\n val cyc_A3_sqrt = cyc_A3 && sqrtOp_PA\n val cyc_A2_sqrt = cyc_A2 && sqrtOp_PA\n val cyc_A1_sqrt = cyc_A1 && sqrtOp_PA\n\n when (cyc_A1 || (cycleNum_B =/= 0.U)) {\n cycleNum_B :=\n Mux(cyc_A1,\n Mux(sqrtOp_PA, 10.U, 6.U),\n cycleNum_B - 1.U\n )\n }\n\n val cyc_B10_sqrt = (cycleNum_B === 10.U)\n val cyc_B9_sqrt = (cycleNum_B === 9.U)\n val cyc_B8_sqrt = (cycleNum_B === 8.U)\n val cyc_B7_sqrt = (cycleNum_B === 7.U)\n\n val cyc_B6 = (cycleNum_B === 6.U)\n val cyc_B5 = (cycleNum_B === 5.U)\n val cyc_B4 = (cycleNum_B === 4.U)\n val cyc_B3 = (cycleNum_B === 3.U)\n val cyc_B2 = (cycleNum_B === 2.U)\n val cyc_B1 = (cycleNum_B === 1.U)\n\n val cyc_B6_div = cyc_B6 && valid_PA && ! sqrtOp_PA\n val cyc_B5_div = cyc_B5 && valid_PA && ! sqrtOp_PA\n val cyc_B4_div = cyc_B4 && valid_PA && ! sqrtOp_PA\n val cyc_B3_div = cyc_B3 && ! sqrtOp_PB\n val cyc_B2_div = cyc_B2 && ! sqrtOp_PB\n val cyc_B1_div = cyc_B1 && ! sqrtOp_PB\n\n val cyc_B6_sqrt = cyc_B6 && valid_PB && sqrtOp_PB\n val cyc_B5_sqrt = cyc_B5 && valid_PB && sqrtOp_PB\n val cyc_B4_sqrt = cyc_B4 && valid_PB && sqrtOp_PB\n val cyc_B3_sqrt = cyc_B3 && sqrtOp_PB\n val cyc_B2_sqrt = cyc_B2 && sqrtOp_PB\n val cyc_B1_sqrt = cyc_B1 && sqrtOp_PB\n\n when (cyc_B1 || (cycleNum_C =/= 0.U)) {\n cycleNum_C :=\n Mux(cyc_B1, Mux(sqrtOp_PB, 6.U, 5.U), cycleNum_C - 1.U)\n }\n\n val cyc_C6_sqrt = (cycleNum_C === 6.U)\n\n val cyc_C5 = (cycleNum_C === 5.U)\n val cyc_C4 = (cycleNum_C === 4.U)\n val cyc_C3 = (cycleNum_C === 3.U)\n val cyc_C2 = (cycleNum_C === 2.U)\n val cyc_C1 = (cycleNum_C === 1.U)\n\n val cyc_C5_div = cyc_C5 && ! sqrtOp_PB\n val cyc_C4_div = cyc_C4 && ! sqrtOp_PB\n val cyc_C3_div = cyc_C3 && ! sqrtOp_PB\n val cyc_C2_div = cyc_C2 && ! sqrtOp_PC\n val cyc_C1_div = cyc_C1 && ! sqrtOp_PC\n\n val cyc_C5_sqrt = cyc_C5 && sqrtOp_PB\n val cyc_C4_sqrt = cyc_C4 && sqrtOp_PB\n val cyc_C3_sqrt = cyc_C3 && sqrtOp_PB\n val cyc_C2_sqrt = cyc_C2 && sqrtOp_PC\n val cyc_C1_sqrt = cyc_C1 && sqrtOp_PC\n\n when (cyc_C1 || (cycleNum_E =/= 0.U)) {\n cycleNum_E := Mux(cyc_C1, 4.U, cycleNum_E - 1.U)\n }\n\n val cyc_E4 = (cycleNum_E === 4.U)\n val cyc_E3 = (cycleNum_E === 3.U)\n val cyc_E2 = (cycleNum_E === 2.U)\n val cyc_E1 = (cycleNum_E === 1.U)\n\n val cyc_E4_div = cyc_E4 && ! sqrtOp_PC\n val cyc_E3_div = cyc_E3 && ! sqrtOp_PC\n val cyc_E2_div = cyc_E2 && ! sqrtOp_PC\n val cyc_E1_div = cyc_E1 && ! sqrtOp_PC\n\n val cyc_E4_sqrt = cyc_E4 && sqrtOp_PC\n val cyc_E3_sqrt = cyc_E3 && sqrtOp_PC\n val cyc_E2_sqrt = cyc_E2 && sqrtOp_PC\n val cyc_E1_sqrt = cyc_E1 && sqrtOp_PC\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PA =\n entering_PA_normalCase || (cyc_S && (valid_PA || ! ready_PB))\n\n when (entering_PA || leaving_PA) {\n valid_PA := entering_PA\n }\n when (entering_PA) {\n sqrtOp_PA := io.sqrtOp\n majorExc_PA := majorExc_S\n isNaN_PA := isNaN_S\n isInf_PA := isInf_S\n isZero_PA := isZero_S\n sign_PA := sign_S\n }\n when (entering_PA_normalCase) {\n sExp_PA := Mux(io.sqrtOp, rawB_S.sExp, sSatExpQuot_S_div)\n fractB_PA := rawB_S.sig(51, 0)\n roundingMode_PA := io.roundingMode\n }\n when (entering_PA_normalCase_div) {\n fractA_PA := rawA_S.sig(51, 0)\n }\n\n val normalCase_PA = ! isNaN_PA && ! isInf_PA && ! isZero_PA\n val sigA_PA = 1.U(1.W) ## fractA_PA\n val sigB_PA = 1.U(1.W) ## fractB_PA\n\n val valid_normalCase_leaving_PA = cyc_B4_div || cyc_B7_sqrt\n val valid_leaving_PA =\n Mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB)\n leaving_PA := valid_PA && valid_leaving_PA\n ready_PA := ! valid_PA || valid_leaving_PA\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PB_S =\n cyc_S && ! normalCase_S && ! valid_PA &&\n (leaving_PB || (! valid_PB && ! ready_PC))\n val entering_PB_normalCase =\n valid_PA && normalCase_PA && valid_normalCase_leaving_PA\n val entering_PB = entering_PB_S || leaving_PA\n\n when (entering_PB || leaving_PB) {\n valid_PB := entering_PB\n }\n when (entering_PB) {\n sqrtOp_PB := Mux(valid_PA, sqrtOp_PA, io.sqrtOp )\n majorExc_PB := Mux(valid_PA, majorExc_PA, majorExc_S)\n isNaN_PB := Mux(valid_PA, isNaN_PA, isNaN_S )\n isInf_PB := Mux(valid_PA, isInf_PA, isInf_S )\n isZero_PB := Mux(valid_PA, isZero_PA, isZero_S )\n sign_PB := Mux(valid_PA, sign_PA, sign_S )\n }\n when (entering_PB_normalCase) {\n sExp_PB := sExp_PA\n bit0FractA_PB := fractA_PA(0)\n fractB_PB := fractB_PA\n roundingMode_PB := Mux(valid_PA, roundingMode_PA, io.roundingMode)\n }\n\n val normalCase_PB = ! isNaN_PB && ! isInf_PB && ! isZero_PB\n\n val valid_normalCase_leaving_PB = cyc_C3\n val valid_leaving_PB =\n Mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC)\n leaving_PB := valid_PB && valid_leaving_PB\n ready_PB := ! valid_PB || valid_leaving_PB\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val entering_PC_S =\n cyc_S && ! normalCase_S && ! valid_PA && ! valid_PB && ready_PC\n val entering_PC_normalCase =\n valid_PB && normalCase_PB && valid_normalCase_leaving_PB\n val entering_PC = entering_PC_S || leaving_PB\n\n when (entering_PC || leaving_PC) {\n valid_PC := entering_PC\n }\n when (entering_PC) {\n sqrtOp_PC := Mux(valid_PB, sqrtOp_PB, io.sqrtOp )\n majorExc_PC := Mux(valid_PB, majorExc_PB, majorExc_S)\n isNaN_PC := Mux(valid_PB, isNaN_PB, isNaN_S )\n isInf_PC := Mux(valid_PB, isInf_PB, isInf_S )\n isZero_PC := Mux(valid_PB, isZero_PB, isZero_S )\n sign_PC := Mux(valid_PB, sign_PB, sign_S )\n }\n when (entering_PC_normalCase) {\n sExp_PC := sExp_PB\n bit0FractA_PC := bit0FractA_PB\n fractB_PC := fractB_PB\n roundingMode_PC := Mux(valid_PB, roundingMode_PB, io.roundingMode)\n }\n\n val normalCase_PC = ! isNaN_PC && ! isInf_PC && ! isZero_PC\n val sigB_PC = 1.U(1.W) ## fractB_PC\n\n val valid_leaving_PC = ! normalCase_PC || cyc_E1\n leaving_PC := valid_PC && valid_leaving_PC\n ready_PC := ! valid_PC || valid_leaving_PC\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n//*** NEED TO COMPUTE AS MUCH AS POSSIBLE IN PREVIOUS CYCLE?:\n io.inReady_div :=\n//*** REPLACE ALL OF '! cyc_B*_sqrt' BY '! (valid_PB && sqrtOp_PB)'?:\n ready_PA && ! cyc_B7_sqrt && ! cyc_B6_sqrt && ! cyc_B5_sqrt &&\n ! cyc_B4_sqrt && ! cyc_B3 && ! cyc_B2 && ! cyc_B1_sqrt &&\n ! cyc_C5 && ! cyc_C4\n io.inReady_sqrt :=\n ready_PA && ! cyc_B6_sqrt && ! cyc_B5_sqrt && ! cyc_B4_sqrt &&\n ! cyc_B2_div && ! cyc_B1_sqrt\n\n /*------------------------------------------------------------------------\n | Macrostage A, built around a 9x9-bit multiplier-adder.\n *------------------------------------------------------------------------*/\n val zFractB_A4_div = Mux(cyc_A4_div, rawB_S.sig(51, 0), 0.U)\n\n val zLinPiece_0_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 0.U)\n val zLinPiece_1_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 1.U)\n val zLinPiece_2_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 2.U)\n val zLinPiece_3_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 3.U)\n val zLinPiece_4_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 4.U)\n val zLinPiece_5_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 5.U)\n val zLinPiece_6_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 6.U)\n val zLinPiece_7_A4_div = cyc_A4_div && (rawB_S.sig(51, 49) === 7.U)\n val zK1_A4_div =\n Mux(zLinPiece_0_A4_div, \"h1C7\".U, 0.U) |\n Mux(zLinPiece_1_A4_div, \"h16C\".U, 0.U) |\n Mux(zLinPiece_2_A4_div, \"h12A\".U, 0.U) |\n Mux(zLinPiece_3_A4_div, \"h0F8\".U, 0.U) |\n Mux(zLinPiece_4_A4_div, \"h0D2\".U, 0.U) |\n Mux(zLinPiece_5_A4_div, \"h0B4\".U, 0.U) |\n Mux(zLinPiece_6_A4_div, \"h09C\".U, 0.U) |\n Mux(zLinPiece_7_A4_div, \"h089\".U, 0.U)\n val zComplFractK0_A4_div =\n Mux(zLinPiece_0_A4_div, ~\"hFE3\".U(12.W), 0.U) |\n Mux(zLinPiece_1_A4_div, ~\"hC5D\".U(12.W), 0.U) |\n Mux(zLinPiece_2_A4_div, ~\"h98A\".U(12.W), 0.U) |\n Mux(zLinPiece_3_A4_div, ~\"h739\".U(12.W), 0.U) |\n Mux(zLinPiece_4_A4_div, ~\"h54B\".U(12.W), 0.U) |\n Mux(zLinPiece_5_A4_div, ~\"h3A9\".U(12.W), 0.U) |\n Mux(zLinPiece_6_A4_div, ~\"h242\".U(12.W), 0.U) |\n Mux(zLinPiece_7_A4_div, ~\"h10B\".U(12.W), 0.U)\n\n val zFractB_A7_sqrt = Mux(cyc_A7_sqrt, rawB_S.sig(51, 0), 0.U)\n\n val zQuadPiece_0_A7_sqrt =\n cyc_A7_sqrt && ! rawB_S.sExp(0) && ! rawB_S.sig(51)\n val zQuadPiece_1_A7_sqrt =\n cyc_A7_sqrt && ! rawB_S.sExp(0) && rawB_S.sig(51)\n val zQuadPiece_2_A7_sqrt =\n cyc_A7_sqrt && rawB_S.sExp(0) && ! rawB_S.sig(51)\n val zQuadPiece_3_A7_sqrt = cyc_A7_sqrt && rawB_S.sExp(0) && rawB_S.sig(51)\n val zK2_A7_sqrt =\n Mux(zQuadPiece_0_A7_sqrt, \"h1C8\".U, 0.U) |\n Mux(zQuadPiece_1_A7_sqrt, \"h0C1\".U, 0.U) |\n Mux(zQuadPiece_2_A7_sqrt, \"h143\".U, 0.U) |\n Mux(zQuadPiece_3_A7_sqrt, \"h089\".U, 0.U)\n val zComplK1_A7_sqrt =\n Mux(zQuadPiece_0_A7_sqrt, ~\"h3D0\".U(10.W), 0.U) |\n Mux(zQuadPiece_1_A7_sqrt, ~\"h220\".U(10.W), 0.U) |\n Mux(zQuadPiece_2_A7_sqrt, ~\"h2B2\".U(10.W), 0.U) |\n Mux(zQuadPiece_3_A7_sqrt, ~\"h181\".U(10.W), 0.U)\n\n val zQuadPiece_0_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && ! sigB_PA(51)\n val zQuadPiece_1_A6_sqrt = cyc_A6_sqrt && ! sExp_PA(0) && sigB_PA(51)\n val zQuadPiece_2_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && ! sigB_PA(51)\n val zQuadPiece_3_A6_sqrt = cyc_A6_sqrt && sExp_PA(0) && sigB_PA(51)\n val zComplFractK0_A6_sqrt =\n Mux(zQuadPiece_0_A6_sqrt, ~\"h1FE5\".U(13.W), 0.U) |\n Mux(zQuadPiece_1_A6_sqrt, ~\"h1435\".U(13.W), 0.U) |\n Mux(zQuadPiece_2_A6_sqrt, ~\"h0D2C\".U(13.W), 0.U) |\n Mux(zQuadPiece_3_A6_sqrt, ~\"h04E8\".U(13.W), 0.U)\n\n val mulAdd9A_A =\n zFractB_A4_div(48, 40) | zK2_A7_sqrt |\n Mux(! cyc_S, nextMulAdd9A_A, 0.U)\n val mulAdd9B_A =\n zK1_A4_div | zFractB_A7_sqrt(50, 42) |\n Mux(! cyc_S, nextMulAdd9B_A, 0.U)\n val mulAdd9C_A =\n//*** ADJUST CONSTANTS SO 'Fill'S AREN'T NEEDED:\n zComplK1_A7_sqrt ## Fill(10, cyc_A7_sqrt) |\n Cat(cyc_A6_sqrt, zComplFractK0_A6_sqrt, Fill(6, cyc_A6_sqrt)) |\n Cat(cyc_A4_div, zComplFractK0_A4_div, Fill(8, cyc_A4_div )) |\n Mux(cyc_A5_sqrt, (1<<18).U +& (fractR0_A<<10), 0.U) |\n Mux(cyc_A4_sqrt && ! hiSqrR0_A_sqrt(9), (1<<10).U, 0.U) |\n Mux((cyc_A4_sqrt && hiSqrR0_A_sqrt(9)) || cyc_A3_div,\n sigB_PA(46, 26) + (1<<10).U,\n 0.U\n ) |\n Mux(cyc_A3_sqrt || cyc_A2, partNegSigma0_A, 0.U) |\n Mux(cyc_A1_sqrt, fractR0_A<<16, 0.U) |\n Mux(cyc_A1_div, fractR0_A<<15, 0.U)\n val loMulAdd9Out_A = mulAdd9A_A * mulAdd9B_A +& mulAdd9C_A(17, 0)\n val mulAdd9Out_A =\n Cat(Mux(loMulAdd9Out_A(18),\n mulAdd9C_A(24, 18) + 1.U,\n mulAdd9C_A(24, 18)\n ),\n loMulAdd9Out_A(17, 0)\n )\n\n val zFractR0_A6_sqrt =\n Mux(cyc_A6_sqrt && mulAdd9Out_A(19), ~(mulAdd9Out_A>>10), 0.U)\n /*------------------------------------------------------------------------\n | ('sqrR0_A5_sqrt' is usually >= 1, but not always.)\n *------------------------------------------------------------------------*/\n val sqrR0_A5_sqrt = Mux(sExp_PA(0), mulAdd9Out_A<<1, mulAdd9Out_A)\n val zFractR0_A4_div =\n Mux(cyc_A4_div && mulAdd9Out_A(20), ~(mulAdd9Out_A>>11), 0.U)\n val zSigma0_A2 =\n Mux(cyc_A2 && mulAdd9Out_A(11), ~(mulAdd9Out_A>>2), 0.U)\n val r1_A1 = (1<<15).U | Mux(sqrtOp_PA, mulAdd9Out_A>>10, mulAdd9Out_A>>9)\n val ER1_A1_sqrt = Mux(sExp_PA(0), r1_A1<<1, r1_A1)\n\n when (cyc_A6_sqrt || cyc_A4_div) {\n fractR0_A := zFractR0_A6_sqrt | zFractR0_A4_div\n }\n when (cyc_A5_sqrt) {\n hiSqrR0_A_sqrt := sqrR0_A5_sqrt>>10\n }\n when (cyc_A4_sqrt || cyc_A3) {\n partNegSigma0_A := Mux(cyc_A4_sqrt, mulAdd9Out_A, mulAdd9Out_A>>9)\n }\n when (\n cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A3 || cyc_A2\n ) {\n nextMulAdd9A_A :=\n Mux(cyc_A7_sqrt, ~mulAdd9Out_A>>11, 0.U) |\n zFractR0_A6_sqrt |\n Mux(cyc_A4_sqrt, sigB_PA(43, 35), 0.U) |\n zFractB_A4_div(43, 35) |\n Mux(cyc_A5_sqrt || cyc_A3, sigB_PA(52, 44), 0.U) |\n zSigma0_A2\n }\n when (cyc_A7_sqrt || cyc_A6_sqrt || cyc_A5_sqrt || cyc_A4 || cyc_A2) {\n nextMulAdd9B_A :=\n zFractB_A7_sqrt(50, 42) |\n zFractR0_A6_sqrt |\n Mux(cyc_A5_sqrt, sqrR0_A5_sqrt(9, 1), 0.U) |\n zFractR0_A4_div |\n Mux(cyc_A4_sqrt, hiSqrR0_A_sqrt(8, 0), 0.U) |\n Mux(cyc_A2, Cat(1.U(1.W), fractR0_A(8, 1)), 0.U)\n }\n when (cyc_A1_sqrt) {\n ER1_B_sqrt := ER1_A1_sqrt\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.latchMulAddA_0 :=\n cyc_A1 || cyc_B7_sqrt || cyc_B6_div || cyc_B4 || cyc_B3 ||\n cyc_C6_sqrt || cyc_C4 || cyc_C1\n io.mulAddA_0 :=\n Mux(cyc_A1_sqrt, ER1_A1_sqrt<<36, 0.U) | // 52:36\n Mux(cyc_B7_sqrt || cyc_A1_div, sigB_PA, 0.U) | // 52:0\n Mux(cyc_B6_div, sigA_PA, 0.U) | // 52:0\n zSigma1_B4(45, 12) | // 33:0\n//*** ONLY 30 BITS NEEDED IN CYCLE C6:\n Mux(cyc_B3 || cyc_C6_sqrt, sigXNU_B3_CX(57, 12), 0.U) | // 45:0\n Mux(cyc_C4_div, sigXN_C(57, 25)<<13, 0.U) | // 45:13\n Mux(cyc_C4_sqrt, u_C_sqrt<<15, 0.U) | // 45:15\n Mux(cyc_C1_div, sigB_PC, 0.U) | // 52:0\n zComplSigT_C1_sqrt // 53:0\n io.latchMulAddB_0 :=\n cyc_A1 || cyc_B7_sqrt || cyc_B6_sqrt || cyc_B4 ||\n cyc_C6_sqrt || cyc_C4 || cyc_C1\n io.mulAddB_0 :=\n Mux(cyc_A1, r1_A1<<36, 0.U) | // 51:36\n Mux(cyc_B7_sqrt, ESqrR1_B_sqrt<<19, 0.U) | // 50:19\n Mux(cyc_B6_sqrt, ER1_B_sqrt<<36, 0.U) | // 52:36\n zSigma1_B4 | // 45:0\n Mux(cyc_C6_sqrt, sqrSigma1_C(30, 1), 0.U) | // 29:0\n Mux(cyc_C4, sqrSigma1_C, 0.U) | // 32:0\n zComplSigT_C1 // 53:0\n\n io.usingMulAdd :=\n Cat(cyc_A4 || cyc_A3_div || cyc_A1_div ||\n cyc_B10_sqrt || cyc_B9_sqrt || cyc_B7_sqrt || cyc_B6 ||\n cyc_B5_sqrt || cyc_B3_sqrt || cyc_B2_div || cyc_B1_sqrt ||\n cyc_C4,\n cyc_A3 || cyc_A2_div ||\n cyc_B9_sqrt || cyc_B8_sqrt || cyc_B6 || cyc_B5 ||\n cyc_B4_sqrt || cyc_B2_sqrt || cyc_B1_div || cyc_C6_sqrt ||\n cyc_C3,\n cyc_A2 || cyc_A1_div ||\n cyc_B8_sqrt || cyc_B7_sqrt || cyc_B5 || cyc_B4 ||\n cyc_B3_sqrt || cyc_B1_sqrt || cyc_C5 ||\n cyc_C2,\n io.latchMulAddA_0 || cyc_B6 || cyc_B2_sqrt\n )\n\n io.mulAddC_2 :=\n Mux(cyc_B1, sigX1_B<<47, 0.U) |\n Mux(cyc_C6_sqrt, sigX1_B<<46, 0.U) |\n Mux(cyc_C4_sqrt || cyc_C2, sigXN_C<<47, 0.U) |\n Mux(cyc_E3_div && ! E_E_div, bit0FractA_PC<<53, 0.U) |\n Mux(cyc_E3_sqrt,\n (Mux(sExp_PC(0),\n sigB_PC(0)<<1,\n (sigB_PC(1) ^ sigB_PC(0)) ## sigB_PC(0)\n ) ^ ((~ sigT_E(0))<<1)\n )<<54,\n 0.U\n )\n\n val ESqrR1_B8_sqrt = io.mulAddResult_3(103, 72)\n zSigma1_B4 := Mux(cyc_B4, ~io.mulAddResult_3(90, 45), 0.U)\n val sqrSigma1_B1 = io.mulAddResult_3(79, 47)\n sigXNU_B3_CX := io.mulAddResult_3(104, 47) // x1, x2, u (sqrt), xT'\n val E_C1_div = ! io.mulAddResult_3(104)\n zComplSigT_C1 :=\n Mux((cyc_C1_div && ! E_C1_div) || cyc_C1_sqrt,\n ~io.mulAddResult_3(104, 51),\n 0.U\n ) |\n Mux(cyc_C1_div && E_C1_div, ~io.mulAddResult_3(102, 50), 0.U)\n zComplSigT_C1_sqrt :=\n Mux(cyc_C1_sqrt, ~io.mulAddResult_3(104, 51), 0.U)\n /*------------------------------------------------------------------------\n | (For square root, 'sigT_C1' will usually be >= 1, but not always.)\n *------------------------------------------------------------------------*/\n val sigT_C1 = ~zComplSigT_C1\n val remT_E2 = io.mulAddResult_3(55, 0)\n\n when (cyc_B8_sqrt) {\n ESqrR1_B_sqrt := ESqrR1_B8_sqrt\n }\n when (cyc_B3) {\n sigX1_B := sigXNU_B3_CX\n }\n when (cyc_B1) {\n sqrSigma1_C := sqrSigma1_B1\n }\n\n when (cyc_C6_sqrt || cyc_C5_div || cyc_C3_sqrt) {\n sigXN_C := sigXNU_B3_CX\n }\n when (cyc_C5_sqrt) {\n u_C_sqrt := sigXNU_B3_CX(56, 26)\n }\n when (cyc_C1) {\n E_E_div := E_C1_div\n sigT_E := sigT_C1\n }\n\n when (cyc_E2) {\n isNegRemT_E := Mux(sqrtOp_PC, remT_E2(55), remT_E2(53))\n isZeroRemT_E :=\n (remT_E2(53, 0) === 0.U) &&\n (! sqrtOp_PC || (remT_E2(55, 54) === 0.U))\n }\n\n /*------------------------------------------------------------------------\n | T is the lower-bound \"trial\" result value, with 54 bits of precision.\n | It is known that the true unrounded result is within the range of\n | (T, T + (2 ulps of 54 bits)). X is defined as the best estimate,\n | = T + (1 ulp), which is exactly in the middle of the possible range.\n *------------------------------------------------------------------------*/\n val trueLtX_E1 =\n Mux(sqrtOp_PC, ! isNegRemT_E && ! isZeroRemT_E, isNegRemT_E)\n val trueEqX_E1 = isZeroRemT_E\n\n /*------------------------------------------------------------------------\n | The inputs to these two values are stable for several clock cycles in\n | advance, so the circuitry can be minimized at the expense of speed.\n*** ANY WAY TO TELL THIS TO THE TOOLS?\n *------------------------------------------------------------------------*/\n val sExpP1_PC = sExp_PC + 1.S\n val sigTP1_E = sigT_E +& 1.U\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := leaving_PC && ! sqrtOp_PC\n io.rawOutValid_sqrt := leaving_PC && sqrtOp_PC\n io.roundingModeOut := roundingMode_PC\n io.invalidExc := majorExc_PC && isNaN_PC\n io.infiniteExc := majorExc_PC && ! isNaN_PC\n io.rawOut.isNaN := isNaN_PC\n io.rawOut.isInf := isInf_PC\n io.rawOut.isZero := isZero_PC\n io.rawOut.sign := sign_PC\n io.rawOut.sExp :=\n Mux(! sqrtOp_PC && E_E_div, sExp_PC, 0.S) |\n Mux(! sqrtOp_PC && ! E_E_div, sExpP1_PC, 0.S) |\n Mux( sqrtOp_PC, (sExp_PC>>1) +& 1024.S, 0.S)\n io.rawOut.sig := Mux(trueLtX_E1, sigT_E, sigTP1_E) ## ! trueEqX_E1\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass DivSqrtRecF64_mulAddZ31(options: Int) extends Module\n{\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady_div = Output(Bool())\n val inReady_sqrt = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(Bits(65.W))\n val b = Input(Bits(65.W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val usingMulAdd = Output(Bits(4.W))\n val latchMulAddA_0 = Output(Bool())\n val mulAddA_0 = Output(UInt(54.W))\n val latchMulAddB_0 = Output(Bool())\n val mulAddB_0 = Output(UInt(54.W))\n val mulAddC_2 = Output(UInt(105.W))\n val mulAddResult_3 = Input(UInt(105.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(Bits(65.W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecF64ToRaw = Module(new DivSqrtRecF64ToRaw_mulAddZ31)\n\n io.inReady_div := divSqrtRecF64ToRaw.io.inReady_div\n io.inReady_sqrt := divSqrtRecF64ToRaw.io.inReady_sqrt\n divSqrtRecF64ToRaw.io.inValid := io.inValid\n divSqrtRecF64ToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecF64ToRaw.io.a := io.a\n divSqrtRecF64ToRaw.io.b := io.b\n divSqrtRecF64ToRaw.io.roundingMode := io.roundingMode\n\n io.usingMulAdd := divSqrtRecF64ToRaw.io.usingMulAdd\n io.latchMulAddA_0 := divSqrtRecF64ToRaw.io.latchMulAddA_0\n io.mulAddA_0 := divSqrtRecF64ToRaw.io.mulAddA_0\n io.latchMulAddB_0 := divSqrtRecF64ToRaw.io.latchMulAddB_0\n io.mulAddB_0 := divSqrtRecF64ToRaw.io.mulAddB_0\n io.mulAddC_2 := divSqrtRecF64ToRaw.io.mulAddC_2\n divSqrtRecF64ToRaw.io.mulAddResult_3 := io.mulAddResult_3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecF64ToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecF64ToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(11, 53, flRoundOpt_sigMSBitAlwaysZero))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecF64ToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecF64ToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecF64ToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecF64ToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRecF64ToRaw_mulAddZ31(\n input clock,\n input reset,\n output io_inReady_div,\n output io_inReady_sqrt,\n input io_inValid,\n input io_sqrtOp,\n input [64:0] io_a,\n input [64:0] io_b,\n input [2:0] io_roundingMode,\n output [3:0] io_usingMulAdd,\n output io_latchMulAddA_0,\n output [53:0] io_mulAddA_0,\n output io_latchMulAddB_0,\n output [53:0] io_mulAddB_0,\n output [104:0] io_mulAddC_2,\n input [104:0] io_mulAddResult_3,\n output io_rawOutValid_div,\n output io_rawOutValid_sqrt,\n output [2:0] io_roundingModeOut,\n output io_invalidExc,\n output io_infiniteExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [12:0] io_rawOut_sExp,\n output [55:0] io_rawOut_sig\n);\n\n wire [53:0] zComplSigT_C1_sqrt;\n wire [52:0] _GEN;\n wire _zComplSigT_C1_T_5_53;\n wire [45:0] zSigma1_B4;\n wire io_inReady_sqrt_0;\n wire io_inReady_div_0;\n wire ready_PC;\n wire ready_PB;\n reg [2:0] cycleNum_A;\n reg [3:0] cycleNum_B;\n reg [2:0] cycleNum_C;\n reg [2:0] cycleNum_E;\n reg valid_PA;\n reg sqrtOp_PA;\n reg majorExc_PA;\n reg isNaN_PA;\n reg isInf_PA;\n reg isZero_PA;\n reg sign_PA;\n reg [12:0] sExp_PA;\n reg [51:0] fractB_PA;\n reg [51:0] fractA_PA;\n reg [2:0] roundingMode_PA;\n reg valid_PB;\n reg sqrtOp_PB;\n reg majorExc_PB;\n reg isNaN_PB;\n reg isInf_PB;\n reg isZero_PB;\n reg sign_PB;\n reg [12:0] sExp_PB;\n reg bit0FractA_PB;\n reg [51:0] fractB_PB;\n reg [2:0] roundingMode_PB;\n reg valid_PC;\n reg sqrtOp_PC;\n reg majorExc_PC;\n reg isNaN_PC;\n reg isInf_PC;\n reg isZero_PC;\n reg sign_PC;\n reg [12:0] sExp_PC;\n reg bit0FractA_PC;\n reg [51:0] fractB_PC;\n reg [2:0] roundingMode_PC;\n reg [8:0] fractR0_A;\n reg [9:0] hiSqrR0_A_sqrt;\n reg [20:0] partNegSigma0_A;\n reg [8:0] nextMulAdd9A_A;\n reg [8:0] nextMulAdd9B_A;\n reg [16:0] ER1_B_sqrt;\n reg [31:0] ESqrR1_B_sqrt;\n reg [57:0] sigX1_B;\n reg [32:0] sqrSigma1_C;\n reg [57:0] sigXN_C;\n reg [30:0] u_C_sqrt;\n reg E_E_div;\n reg [53:0] sigT_E;\n reg isNegRemT_E;\n reg isZeroRemT_E;\n wire cyc_S_div = io_inReady_div_0 & io_inValid & ~io_sqrtOp;\n wire cyc_S_sqrt = io_inReady_sqrt_0 & io_inValid & io_sqrtOp;\n wire cyc_S = cyc_S_div | cyc_S_sqrt;\n wire rawA_S_isZero = io_a[63:61] == 3'h0;\n wire rawA_S_isNaN = (&(io_a[63:62])) & io_a[61];\n wire rawA_S_isInf = (&(io_a[63:62])) & ~(io_a[61]);\n wire rawB_S_isNaN = (&(io_b[63:62])) & io_b[61];\n wire rawB_S_isInf = (&(io_b[63:62])) & ~(io_b[61]);\n wire specialCaseB_S = rawB_S_isNaN | rawB_S_isInf | ~(|(io_b[63:61]));\n wire normalCase_S_div = ~(rawA_S_isNaN | rawA_S_isInf | rawA_S_isZero) & ~specialCaseB_S;\n wire normalCase_S_sqrt = ~specialCaseB_S & ~(io_b[64]);\n wire entering_PA_normalCase_div = cyc_S_div & normalCase_S_div;\n wire entering_PA_normalCase_sqrt = cyc_S_sqrt & normalCase_S_sqrt;\n wire cyc_A6_sqrt = cycleNum_A == 3'h6;\n wire cyc_A5_sqrt = cycleNum_A == 3'h5;\n wire cyc_A4_sqrt = cycleNum_A == 3'h4;\n wire cyc_A4 = cyc_A4_sqrt | entering_PA_normalCase_div;\n wire cyc_A3 = cycleNum_A == 3'h3;\n wire cyc_A2 = cycleNum_A == 3'h2;\n wire cyc_A1 = cycleNum_A == 3'h1;\n wire cyc_A3_div = cyc_A3 & ~sqrtOp_PA;\n wire cyc_A1_div = cyc_A1 & ~sqrtOp_PA;\n wire cyc_A1_sqrt = cyc_A1 & sqrtOp_PA;\n wire cyc_B9_sqrt = cycleNum_B == 4'h9;\n wire cyc_B8_sqrt = cycleNum_B == 4'h8;\n wire cyc_B7_sqrt = cycleNum_B == 4'h7;\n wire cyc_B6 = cycleNum_B == 4'h6;\n wire cyc_B5 = cycleNum_B == 4'h5;\n wire cyc_B4 = cycleNum_B == 4'h4;\n wire cyc_B3 = cycleNum_B == 4'h3;\n wire cyc_B2 = cycleNum_B == 4'h2;\n wire cyc_B1 = cycleNum_B == 4'h1;\n wire cyc_B6_div = cyc_B6 & valid_PA & ~sqrtOp_PA;\n wire cyc_B2_div = cyc_B2 & ~sqrtOp_PB;\n wire cyc_B6_sqrt = cyc_B6 & valid_PB & sqrtOp_PB;\n wire cyc_B5_sqrt = cyc_B5 & valid_PB & sqrtOp_PB;\n wire cyc_B4_sqrt = cyc_B4 & valid_PB & sqrtOp_PB;\n wire cyc_B3_sqrt = cyc_B3 & sqrtOp_PB;\n wire cyc_B2_sqrt = cyc_B2 & sqrtOp_PB;\n wire cyc_B1_sqrt = cyc_B1 & sqrtOp_PB;\n wire cyc_C6_sqrt = cycleNum_C == 3'h6;\n wire cyc_C5 = cycleNum_C == 3'h5;\n wire cyc_C4 = cycleNum_C == 3'h4;\n wire cyc_C3 = cycleNum_C == 3'h3;\n wire cyc_C2 = cycleNum_C == 3'h2;\n wire cyc_C1 = cycleNum_C == 3'h1;\n wire cyc_C1_div = cyc_C1 & ~sqrtOp_PC;\n wire cyc_C4_sqrt = cyc_C4 & sqrtOp_PB;\n wire cyc_C1_sqrt = cyc_C1 & sqrtOp_PC;\n wire cyc_E3 = cycleNum_E == 3'h3;\n wire normalCase_PA = ~isNaN_PA & ~isInf_PA & ~isZero_PA;\n wire valid_normalCase_leaving_PA = cyc_B4 & valid_PA & ~sqrtOp_PA | cyc_B7_sqrt;\n wire valid_leaving_PA = normalCase_PA ? valid_normalCase_leaving_PA : ready_PB;\n wire leaving_PA = valid_PA & valid_leaving_PA;\n wire ready_PA = ~valid_PA | valid_leaving_PA;\n wire normalCase_PB = ~isNaN_PB & ~isInf_PB & ~isZero_PB;\n wire valid_leaving_PB = normalCase_PB ? cyc_C3 : ready_PC;\n wire leaving_PB = valid_PB & valid_leaving_PB;\n assign ready_PB = ~valid_PB | valid_leaving_PB;\n wire valid_leaving_PC = ~(~isNaN_PC & ~isInf_PC & ~isZero_PC) | cycleNum_E == 3'h1;\n wire leaving_PC = valid_PC & valid_leaving_PC;\n assign ready_PC = ~valid_PC | valid_leaving_PC;\n assign io_inReady_div_0 = ready_PA & cycleNum_B != 4'h7 & ~cyc_B6_sqrt & ~cyc_B5_sqrt & ~cyc_B4_sqrt & cycleNum_B != 4'h3 & cycleNum_B != 4'h2 & ~cyc_B1_sqrt & cycleNum_C != 3'h5 & cycleNum_C != 3'h4;\n assign io_inReady_sqrt_0 = ready_PA & ~cyc_B6_sqrt & ~cyc_B5_sqrt & ~cyc_B4_sqrt & ~cyc_B2_div & ~cyc_B1_sqrt;\n wire [13:0] zFractB_A4_div = entering_PA_normalCase_div ? io_b[48:35] : 14'h0;\n wire zLinPiece_0_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h0;\n wire zLinPiece_1_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h1;\n wire zLinPiece_2_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h2;\n wire zLinPiece_3_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h3;\n wire zLinPiece_4_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h4;\n wire zLinPiece_5_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h5;\n wire zLinPiece_6_A4_div = entering_PA_normalCase_div & io_b[51:49] == 3'h6;\n wire zLinPiece_7_A4_div = entering_PA_normalCase_div & (&(io_b[51:49]));\n wire [8:0] _zK1_A4_div_T_4 = (zLinPiece_0_A4_div ? 9'h1C7 : 9'h0) | (zLinPiece_1_A4_div ? 9'h16C : 9'h0) | (zLinPiece_2_A4_div ? 9'h12A : 9'h0);\n wire [8:0] zFractB_A7_sqrt = entering_PA_normalCase_sqrt ? io_b[50:42] : 9'h0;\n wire zQuadPiece_0_A7_sqrt = entering_PA_normalCase_sqrt & ~(io_b[52]) & ~(io_b[51]);\n wire zQuadPiece_1_A7_sqrt = entering_PA_normalCase_sqrt & ~(io_b[52]) & io_b[51];\n wire zQuadPiece_2_A7_sqrt = entering_PA_normalCase_sqrt & io_b[52] & ~(io_b[51]);\n wire zQuadPiece_3_A7_sqrt = entering_PA_normalCase_sqrt & io_b[52] & io_b[51];\n wire [8:0] _zK2_A7_sqrt_T_4 = {zQuadPiece_0_A7_sqrt, (zQuadPiece_0_A7_sqrt ? 8'hC8 : 8'h0) | (zQuadPiece_1_A7_sqrt ? 8'hC1 : 8'h0)} | (zQuadPiece_2_A7_sqrt ? 9'h143 : 9'h0);\n wire [19:0] _mulAdd9C_A_T_4 = {(zQuadPiece_0_A7_sqrt ? 10'h2F : 10'h0) | (zQuadPiece_1_A7_sqrt ? 10'h1DF : 10'h0) | (zQuadPiece_2_A7_sqrt ? 10'h14D : 10'h0) | (zQuadPiece_3_A7_sqrt ? 10'h27E : 10'h0), {10{entering_PA_normalCase_sqrt}}} | {cyc_A6_sqrt, (cyc_A6_sqrt & ~(sExp_PA[0]) & ~(fractB_PA[51]) ? 13'h1A : 13'h0) | (cyc_A6_sqrt & ~(sExp_PA[0]) & fractB_PA[51] ? 13'hBCA : 13'h0) | (cyc_A6_sqrt & sExp_PA[0] & ~(fractB_PA[51]) ? 13'h12D3 : 13'h0) | (cyc_A6_sqrt & sExp_PA[0] & fractB_PA[51] ? 13'h1B17 : 13'h0), {6{cyc_A6_sqrt}}};\n wire [19:0] _GEN_0 = {_mulAdd9C_A_T_4[19:8] | (zLinPiece_0_A4_div ? 12'h1C : 12'h0) | (zLinPiece_1_A4_div ? 12'h3A2 : 12'h0) | (zLinPiece_2_A4_div ? 12'h675 : 12'h0) | (zLinPiece_3_A4_div ? 12'h8C6 : 12'h0) | (zLinPiece_4_A4_div ? 12'hAB4 : 12'h0) | (zLinPiece_5_A4_div ? 12'hC56 : 12'h0) | (zLinPiece_6_A4_div ? 12'hDBD : 12'h0) | (zLinPiece_7_A4_div ? 12'hEF4 : 12'h0), _mulAdd9C_A_T_4[7:0] | {8{entering_PA_normalCase_div}}} | (cyc_A5_sqrt ? {1'h0, fractR0_A, 10'h0} + 20'h40000 : 20'h0);\n wire [24:0] _mulAdd9C_A_T_30 = {4'h0, {entering_PA_normalCase_div, _GEN_0[19:11], _GEN_0[10:0] | {cyc_A4_sqrt & ~(hiSqrR0_A_sqrt[9]), 10'h0}} | (cyc_A4_sqrt & hiSqrR0_A_sqrt[9] | cyc_A3_div ? fractB_PA[46:26] + 21'h400 : 21'h0) | (cyc_A3 & sqrtOp_PA | cyc_A2 ? partNegSigma0_A : 21'h0)} | (cyc_A1_sqrt ? {fractR0_A, 16'h0} : 25'h0);\n wire [23:0] _GEN_1 = _mulAdd9C_A_T_30[23:0] | (cyc_A1_div ? {fractR0_A, 15'h0} : 24'h0);\n wire [18:0] loMulAdd9Out_A = {1'h0, {9'h0, zFractB_A4_div[13:5] | {_zK2_A7_sqrt_T_4[8], _zK2_A7_sqrt_T_4[7:0] | (zQuadPiece_3_A7_sqrt ? 8'h89 : 8'h0)} | (cyc_S ? 9'h0 : nextMulAdd9A_A)} * {9'h0, {_zK1_A4_div_T_4[8], _zK1_A4_div_T_4[7:0] | (zLinPiece_3_A4_div ? 8'hF8 : 8'h0) | (zLinPiece_4_A4_div ? 8'hD2 : 8'h0) | (zLinPiece_5_A4_div ? 8'hB4 : 8'h0) | (zLinPiece_6_A4_div ? 8'h9C : 8'h0) | (zLinPiece_7_A4_div ? 8'h89 : 8'h0)} | zFractB_A7_sqrt | (cyc_S ? 9'h0 : nextMulAdd9B_A)}} + {1'h0, _GEN_1[17:0]};\n wire [6:0] _mulAdd9Out_A_T_5 = loMulAdd9Out_A[18] ? {_mulAdd9C_A_T_30[24], _GEN_1[23:18]} + 7'h1 : {_mulAdd9C_A_T_30[24], _GEN_1[23:18]};\n wire [15:0] r1_A1 = (sqrtOp_PA ? {1'h0, _mulAdd9Out_A_T_5, loMulAdd9Out_A[17:10]} : {_mulAdd9Out_A_T_5, loMulAdd9Out_A[17:9]}) | 16'h8000;\n wire [16:0] ER1_A1_sqrt = sExp_PA[0] ? {r1_A1, 1'h0} : {1'h0, r1_A1};\n wire _io_latchMulAddB_0_T = cyc_A1 | cyc_B7_sqrt;\n wire io_latchMulAddA_0_0 = _io_latchMulAddB_0_T | cyc_B6_div | cyc_B4 | cyc_B3 | cyc_C6_sqrt | cyc_C4 | cyc_C1;\n wire [52:0] _io_mulAddA_0_T_6 = (cyc_A1_sqrt ? {ER1_A1_sqrt, 36'h0} : 53'h0) | (cyc_B7_sqrt | cyc_A1_div ? {1'h1, fractB_PA} : 53'h0) | (cyc_B6_div ? {1'h1, fractA_PA} : 53'h0);\n wire [51:0] _io_mulAddB_0_T_1 = cyc_A1 ? {r1_A1, 36'h0} : 52'h0;\n wire [52:0] _io_mulAddB_0_T_7 = {1'h0, _io_mulAddB_0_T_1[51], _io_mulAddB_0_T_1[50:0] | (cyc_B7_sqrt ? {ESqrR1_B_sqrt, 19'h0} : 51'h0)} | (cyc_B6_sqrt ? {ER1_B_sqrt, 36'h0} : 53'h0);\n wire [45:0] _GEN_2 = _io_mulAddB_0_T_7[45:0] | zSigma1_B4;\n wire [104:0] _io_mulAddC_2_T_1 = cyc_B1 ? {sigX1_B, 47'h0} : 105'h0;\n wire [104:0] _io_mulAddC_2_T_8 = {_io_mulAddC_2_T_1[104], _io_mulAddC_2_T_1[103:0] | (cyc_C6_sqrt ? {sigX1_B, 46'h0} : 104'h0)} | (cyc_C4_sqrt | cyc_C2 ? {sigXN_C, 47'h0} : 105'h0);\n assign zSigma1_B4 = cyc_B4 ? ~(io_mulAddResult_3[90:45]) : 46'h0;\n wire [53:0] _zComplSigT_C1_T_5 = cyc_C1_div & io_mulAddResult_3[104] | cyc_C1_sqrt ? ~(io_mulAddResult_3[104:51]) : 54'h0;\n assign _zComplSigT_C1_T_5_53 = _zComplSigT_C1_T_5[53];\n assign _GEN = _zComplSigT_C1_T_5[52:0] | (cyc_C1_div & ~(io_mulAddResult_3[104]) ? ~(io_mulAddResult_3[102:50]) : 53'h0);\n assign zComplSigT_C1_sqrt = cyc_C1_sqrt ? ~(io_mulAddResult_3[104:51]) : 54'h0;\n wire [54:0] _GEN_3 = {1'h0, sigT_E};\n wire [13:0] sExpQuot_S_div = {2'h0, io_a[63:52]} + {{3{io_b[63]}}, ~(io_b[62:52])};\n wire notSigNaNIn_invalidExc_S_div = rawA_S_isZero & ~(|(io_b[63:61])) | rawA_S_isInf & rawB_S_isInf;\n wire notSigNaNIn_invalidExc_S_sqrt = ~rawB_S_isNaN & (|(io_b[63:61])) & io_b[64];\n wire majorExc_S = io_sqrtOp ? rawB_S_isNaN & ~(io_b[51]) | notSigNaNIn_invalidExc_S_sqrt : rawA_S_isNaN & ~(io_a[51]) | rawB_S_isNaN & ~(io_b[51]) | notSigNaNIn_invalidExc_S_div | ~rawA_S_isNaN & ~rawA_S_isInf & ~(|(io_b[63:61]));\n wire isNaN_S = io_sqrtOp ? rawB_S_isNaN | notSigNaNIn_invalidExc_S_sqrt : rawA_S_isNaN | rawB_S_isNaN | notSigNaNIn_invalidExc_S_div;\n wire isInf_S = io_sqrtOp ? rawB_S_isInf : rawA_S_isInf | ~(|(io_b[63:61]));\n wire isZero_S = io_sqrtOp ? ~(|(io_b[63:61])) : rawA_S_isZero | rawB_S_isInf;\n wire sign_S = ~io_sqrtOp & io_a[64] ^ io_b[64];\n wire normalCase_S = io_sqrtOp ? normalCase_S_sqrt : normalCase_S_div;\n wire entering_PA_normalCase = entering_PA_normalCase_div | entering_PA_normalCase_sqrt;\n wire entering_PA = entering_PA_normalCase | cyc_S & (valid_PA | ~ready_PB);\n wire entering_PB = cyc_S & ~normalCase_S & ~valid_PA & (leaving_PB | ~valid_PB & ~ready_PC) | leaving_PA;\n wire entering_PC = cyc_S & ~normalCase_S & ~valid_PA & ~valid_PB & ready_PC | leaving_PB;\n wire [8:0] zFractR0_A6_sqrt = cyc_A6_sqrt & _mulAdd9Out_A_T_5[1] ? ~{_mulAdd9Out_A_T_5[0], loMulAdd9Out_A[17:10]} : 9'h0;\n wire [18:0] sqrR0_A5_sqrt = sExp_PA[0] ? {_mulAdd9Out_A_T_5[0], loMulAdd9Out_A[17:0]} : {_mulAdd9Out_A_T_5[1:0], loMulAdd9Out_A[17:1]};\n wire [8:0] _GEN_4 = {_mulAdd9Out_A_T_5[1:0], loMulAdd9Out_A[17:11]};\n wire [8:0] zFractR0_A4_div = entering_PA_normalCase_div & _mulAdd9Out_A_T_5[2] ? ~_GEN_4 : 9'h0;\n wire _GEN_5 = entering_PA_normalCase_sqrt | cyc_A6_sqrt | cyc_A5_sqrt | cyc_A4;\n always @(posedge clock) begin\n if (reset) begin\n cycleNum_A <= 3'h0;\n cycleNum_B <= 4'h0;\n cycleNum_C <= 3'h0;\n cycleNum_E <= 3'h0;\n valid_PA <= 1'h0;\n valid_PB <= 1'h0;\n valid_PC <= 1'h0;\n end\n else begin\n if (|{entering_PA_normalCase, cycleNum_A})\n cycleNum_A <= {1'h0, {2{entering_PA_normalCase_div}}} | (entering_PA_normalCase_sqrt ? 3'h6 : 3'h0) | (entering_PA_normalCase ? 3'h0 : cycleNum_A - 3'h1);\n if (|{cyc_A1, cycleNum_B})\n cycleNum_B <= cyc_A1 ? (sqrtOp_PA ? 4'hA : 4'h6) : cycleNum_B - 4'h1;\n if (|{cyc_B1, cycleNum_C})\n cycleNum_C <= cyc_B1 ? (sqrtOp_PB ? 3'h6 : 3'h5) : cycleNum_C - 3'h1;\n if (|{cyc_C1, cycleNum_E})\n cycleNum_E <= cyc_C1 ? 3'h4 : cycleNum_E - 3'h1;\n if (entering_PA | leaving_PA)\n valid_PA <= entering_PA;\n if (entering_PB | leaving_PB)\n valid_PB <= entering_PB;\n if (entering_PC | leaving_PC)\n valid_PC <= entering_PC;\n end\n if (entering_PA) begin\n sqrtOp_PA <= io_sqrtOp;\n majorExc_PA <= majorExc_S;\n isNaN_PA <= isNaN_S;\n isInf_PA <= isInf_S;\n isZero_PA <= isZero_S;\n sign_PA <= sign_S;\n end\n if (entering_PA_normalCase) begin\n sExp_PA <= io_sqrtOp ? {1'h0, io_b[63:52]} : {$signed(sExpQuot_S_div) > 14'shDFF ? 4'h6 : sExpQuot_S_div[12:9], sExpQuot_S_div[8:0]};\n fractB_PA <= io_b[51:0];\n roundingMode_PA <= io_roundingMode;\n end\n if (entering_PA_normalCase_div)\n fractA_PA <= io_a[51:0];\n if (entering_PB) begin\n sqrtOp_PB <= valid_PA ? sqrtOp_PA : io_sqrtOp;\n majorExc_PB <= valid_PA ? majorExc_PA : majorExc_S;\n isNaN_PB <= valid_PA ? isNaN_PA : isNaN_S;\n isInf_PB <= valid_PA ? isInf_PA : isInf_S;\n isZero_PB <= valid_PA ? isZero_PA : isZero_S;\n sign_PB <= valid_PA ? sign_PA : sign_S;\n end\n if (valid_PA & normalCase_PA & valid_normalCase_leaving_PA) begin\n sExp_PB <= sExp_PA;\n bit0FractA_PB <= fractA_PA[0];\n fractB_PB <= fractB_PA;\n roundingMode_PB <= valid_PA ? roundingMode_PA : io_roundingMode;\n end\n if (entering_PC) begin\n sqrtOp_PC <= valid_PB ? sqrtOp_PB : io_sqrtOp;\n majorExc_PC <= valid_PB ? majorExc_PB : majorExc_S;\n isNaN_PC <= valid_PB ? isNaN_PB : isNaN_S;\n isInf_PC <= valid_PB ? isInf_PB : isInf_S;\n isZero_PC <= valid_PB ? isZero_PB : isZero_S;\n sign_PC <= valid_PB ? sign_PB : sign_S;\n end\n if (valid_PB & normalCase_PB & cyc_C3) begin\n sExp_PC <= sExp_PB;\n bit0FractA_PC <= bit0FractA_PB;\n fractB_PC <= fractB_PB;\n roundingMode_PC <= valid_PB ? roundingMode_PB : io_roundingMode;\n end\n if (cyc_A6_sqrt | entering_PA_normalCase_div)\n fractR0_A <= zFractR0_A6_sqrt | zFractR0_A4_div;\n if (cyc_A5_sqrt)\n hiSqrR0_A_sqrt <= sqrR0_A5_sqrt[18:9];\n if (cyc_A4_sqrt | cyc_A3)\n partNegSigma0_A <= cyc_A4_sqrt ? {_mulAdd9Out_A_T_5[2:0], loMulAdd9Out_A[17:0]} : {5'h0, _mulAdd9Out_A_T_5, loMulAdd9Out_A[17:9]};\n if (_GEN_5 | cyc_A3 | cyc_A2)\n nextMulAdd9A_A <= (entering_PA_normalCase_sqrt ? ~_GEN_4 : 9'h0) | zFractR0_A6_sqrt | (cyc_A4_sqrt ? fractB_PA[43:35] : 9'h0) | zFractB_A4_div[8:0] | (cyc_A5_sqrt | cyc_A3 ? {1'h1, fractB_PA[51:44]} : 9'h0) | (cyc_A2 & loMulAdd9Out_A[11] ? ~(loMulAdd9Out_A[10:2]) : 9'h0);\n if (_GEN_5 | cyc_A2)\n nextMulAdd9B_A <= zFractB_A7_sqrt | zFractR0_A6_sqrt | (cyc_A5_sqrt ? sqrR0_A5_sqrt[8:0] : 9'h0) | zFractR0_A4_div | (cyc_A4_sqrt ? hiSqrR0_A_sqrt[8:0] : 9'h0) | (cyc_A2 ? {1'h1, fractR0_A[8:1]} : 9'h0);\n if (cyc_A1_sqrt)\n ER1_B_sqrt <= ER1_A1_sqrt;\n if (cyc_B8_sqrt)\n ESqrR1_B_sqrt <= io_mulAddResult_3[103:72];\n if (cyc_B3)\n sigX1_B <= io_mulAddResult_3[104:47];\n if (cyc_B1)\n sqrSigma1_C <= io_mulAddResult_3[79:47];\n if (cyc_C6_sqrt | cyc_C5 & ~sqrtOp_PB | cyc_C3 & sqrtOp_PB)\n sigXN_C <= io_mulAddResult_3[104:47];\n if (cyc_C5 & sqrtOp_PB)\n u_C_sqrt <= io_mulAddResult_3[103:73];\n if (cyc_C1) begin\n E_E_div <= ~(io_mulAddResult_3[104]);\n sigT_E <= ~{_zComplSigT_C1_T_5_53, _GEN};\n end\n if (cycleNum_E == 3'h2) begin\n isNegRemT_E <= sqrtOp_PC ? io_mulAddResult_3[55] : io_mulAddResult_3[53];\n isZeroRemT_E <= io_mulAddResult_3[53:0] == 54'h0 & (~sqrtOp_PC | io_mulAddResult_3[55:54] == 2'h0);\n end\n end\n assign io_inReady_div = io_inReady_div_0;\n assign io_inReady_sqrt = io_inReady_sqrt_0;\n assign io_usingMulAdd = {cyc_A4 | cyc_A3_div | cyc_A1_div | cycleNum_B == 4'hA | cyc_B9_sqrt | cyc_B7_sqrt | cyc_B6 | cyc_B5_sqrt | cyc_B3_sqrt | cyc_B2_div | cyc_B1_sqrt | cyc_C4, cyc_A3 | cyc_A2 & ~sqrtOp_PA | cyc_B9_sqrt | cyc_B8_sqrt | cyc_B6 | cyc_B5 | cyc_B4_sqrt | cyc_B2_sqrt | cyc_B1 & ~sqrtOp_PB | cyc_C6_sqrt | cyc_C3, cyc_A2 | cyc_A1_div | cyc_B8_sqrt | cyc_B7_sqrt | cyc_B5 | cyc_B4 | cyc_B3_sqrt | cyc_B1_sqrt | cyc_C5 | cyc_C2, io_latchMulAddA_0_0 | cyc_B6 | cyc_B2_sqrt};\n assign io_latchMulAddA_0 = io_latchMulAddA_0_0;\n assign io_mulAddA_0 = {1'h0, {_io_mulAddA_0_T_6[52:46], {_io_mulAddA_0_T_6[45:34], _io_mulAddA_0_T_6[33:0] | zSigma1_B4[45:12]} | (cyc_B3 | cyc_C6_sqrt ? io_mulAddResult_3[104:59] : 46'h0) | (cyc_C4 & ~sqrtOp_PB ? {sigXN_C[57:25], 13'h0} : 46'h0) | (cyc_C4_sqrt ? {u_C_sqrt, 15'h0} : 46'h0)} | (cyc_C1_div ? {1'h1, fractB_PC} : 53'h0)} | zComplSigT_C1_sqrt;\n assign io_latchMulAddB_0 = _io_latchMulAddB_0_T | cyc_B6_sqrt | cyc_B4 | cyc_C6_sqrt | cyc_C4 | cyc_C1;\n assign io_mulAddB_0 = {_zComplSigT_C1_T_5_53, _io_mulAddB_0_T_7[52:46] | _GEN[52:46], _GEN_2[45:33] | _GEN[45:33], {_GEN_2[32:30], _GEN_2[29:0] | (cyc_C6_sqrt ? sqrSigma1_C[30:1] : 30'h0)} | (cyc_C4 ? sqrSigma1_C : 33'h0) | _GEN[32:0]};\n assign io_mulAddC_2 = {_io_mulAddC_2_T_8[104:56], {_io_mulAddC_2_T_8[55:54], _io_mulAddC_2_T_8[53:0] | (cyc_E3 & ~sqrtOp_PC & ~E_E_div ? {bit0FractA_PC, 53'h0} : 54'h0)} | (cyc_E3 & sqrtOp_PC ? {(sExp_PC[0] ? {fractB_PC[0], 1'h0} : {fractB_PC[1] ^ fractB_PC[0], fractB_PC[0]}) ^ {~(sigT_E[0]), 1'h0}, 54'h0} : 56'h0)};\n assign io_rawOutValid_div = leaving_PC & ~sqrtOp_PC;\n assign io_rawOutValid_sqrt = leaving_PC & sqrtOp_PC;\n assign io_roundingModeOut = roundingMode_PC;\n assign io_invalidExc = majorExc_PC & isNaN_PC;\n assign io_infiniteExc = majorExc_PC & ~isNaN_PC;\n assign io_rawOut_isNaN = isNaN_PC;\n assign io_rawOut_isInf = isInf_PC;\n assign io_rawOut_isZero = isZero_PC;\n assign io_rawOut_sign = sign_PC;\n assign io_rawOut_sExp = (~sqrtOp_PC & E_E_div ? sExp_PC : 13'h0) | (sqrtOp_PC | E_E_div ? 13'h0 : sExp_PC + 13'h1) | (sqrtOp_PC ? {sExp_PC[12], sExp_PC[12:1]} + 13'h400 : 13'h0);\n assign io_rawOut_sig = {(sqrtOp_PC ? ~isNegRemT_E & ~isZeroRemT_E : isNegRemT_E) ? _GEN_3 : _GEN_3 + 55'h1, ~isZeroRemT_E};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.devices.tilelink\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.diplomacy.{AddressSet}\nimport freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}\nimport freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}\nimport freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}\nimport freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}\nimport freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}\nimport freechips.rocketchip.util.{Annotated, MuxT, property}\n\nimport scala.math.min\n\nimport freechips.rocketchip.util.UIntToAugmentedUInt\nimport freechips.rocketchip.util.SeqToAugmentedSeq\n\nclass GatewayPLICIO extends Bundle {\n val valid = Output(Bool())\n val ready = Input(Bool())\n val complete = Input(Bool())\n}\n\nclass LevelGateway extends Module {\n val io = IO(new Bundle {\n val interrupt = Input(Bool())\n val plic = new GatewayPLICIO\n })\n\n val inFlight = RegInit(false.B)\n when (io.interrupt && io.plic.ready) { inFlight := true.B }\n when (io.plic.complete) { inFlight := false.B }\n io.plic.valid := io.interrupt && !inFlight\n}\n\nobject PLICConsts\n{\n def maxDevices = 1023\n def maxMaxHarts = 15872\n def priorityBase = 0x0\n def pendingBase = 0x1000\n def enableBase = 0x2000\n def hartBase = 0x200000\n\n def claimOffset = 4\n def priorityBytes = 4\n\n def enableOffset(i: Int) = i * ((maxDevices+7)/8)\n def hartOffset(i: Int) = i * 0x1000\n def enableBase(i: Int):Int = enableOffset(i) + enableBase\n def hartBase(i: Int):Int = hartOffset(i) + hartBase\n\n def size(maxHarts: Int): Int = {\n require(maxHarts > 0 && maxHarts <= maxMaxHarts, s\"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}\")\n 1 << log2Ceil(hartBase(maxHarts))\n }\n\n require(hartBase >= enableBase(maxMaxHarts))\n}\n\ncase class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)\n{\n require (maxPriorities >= 0)\n def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)\n}\n\ncase object PLICKey extends Field[Option[PLICParams]](None)\n\ncase class PLICAttachParams(\n slaveWhere: TLBusWrapperLocation = CBUS\n)\n\ncase object PLICAttachKey extends Field(PLICAttachParams())\n\n/** Platform-Level Interrupt Controller */\nclass TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule\n{\n // plic0 => max devices 1023\n val device: SimpleDevice = new SimpleDevice(\"interrupt-controller\", Seq(\"riscv,plic0\")) {\n override val alwaysExtended = true\n override def describe(resources: ResourceBindings): Description = {\n val Description(name, mapping) = super.describe(resources)\n val extra = Map(\n \"interrupt-controller\" -> Nil,\n \"riscv,ndev\" -> Seq(ResourceInt(nDevices)),\n \"riscv,max-priority\" -> Seq(ResourceInt(nPriorities)),\n \"#interrupt-cells\" -> Seq(ResourceInt(1)))\n Description(name, mapping ++ extra)\n }\n }\n\n val node : TLRegisterNode = TLRegisterNode(\n address = Seq(params.address),\n device = device,\n beatBytes = beatBytes,\n undefZero = true,\n concurrency = 1) // limiting concurrency handles RAW hazards on claim registers\n\n val intnode: IntNexusNode = IntNexusNode(\n sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, \"int\"))))) },\n sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },\n outputRequiresInput = false,\n inputRequiresOutput = false)\n\n /* Negotiated sizes */\n def nDevices: Int = intnode.edges.in.map(_.source.num).sum\n def minPriorities = min(params.maxPriorities, nDevices)\n def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1\n def nHarts = intnode.edges.out.map(_.source.num).sum\n\n // Assign all the devices unique ranges\n lazy val sources = intnode.edges.in.map(_.source)\n lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {\n case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))\n }.flatten\n\n ResourceBinding {\n flatSources.foreach { s => s.resources.foreach { r =>\n // +1 because interrupt 0 is reserved\n (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }\n } }\n }\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n Annotated.params(this, params)\n\n val (io_devices, edgesIn) = intnode.in.unzip\n val (io_harts, _) = intnode.out.unzip\n\n // Compact the interrupt vector the same way\n val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten\n // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence\n val harts = io_harts.flatten\n\n def getNInterrupts = interrupts.size\n\n println(s\"Interrupt map (${nHarts} harts ${nDevices} interrupts):\")\n flatSources.foreach { s =>\n // +1 because 0 is reserved, +1-1 because the range is half-open\n println(s\" [${s.range.start+1}, ${s.range.end}] => ${s.name}\")\n }\n println(\"\")\n\n require (nDevices == interrupts.size, s\"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}\")\n require (nHarts == harts.size, s\"Must be: nHarts=$nHarts == harts.size=${harts.size}\")\n\n require(nDevices <= PLICConsts.maxDevices, s\"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}\")\n require(nHarts > 0 && nHarts <= params.maxHarts, s\"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}\")\n\n // For now, use LevelGateways for all TL2 interrupts\n val gateways = interrupts.map { case i =>\n val gateway = Module(new LevelGateway)\n gateway.io.interrupt := i\n gateway.io.plic\n }\n\n val prioBits = log2Ceil(nPriorities+1)\n val priority =\n if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))\n else WireDefault(VecInit.fill(nDevices max 1)(1.U))\n val threshold =\n if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))\n else WireDefault(VecInit.fill(nHarts)(0.U))\n val pending = RegInit(VecInit.fill(nDevices max 1){false.B})\n\n /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */\n val firstEnable = nDevices min 7\n val fullEnables = (nDevices - firstEnable) / 8\n val tailEnable = nDevices - firstEnable - 8*fullEnables\n def enableRegs = (Reg(UInt(firstEnable.W)) +:\n Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++\n (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)\n val enables = Seq.fill(nHarts) { enableRegs }\n val enableVec = VecInit(enables.map(x => Cat(x.reverse)))\n val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))\n \n val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))\n val pendingUInt = Cat(pending.reverse)\n if(nDevices > 0) {\n for (hart <- 0 until nHarts) {\n val fanin = Module(new PLICFanIn(nDevices, prioBits))\n fanin.io.prio := priority\n fanin.io.ip := enableVec(hart) & pendingUInt\n maxDevs(hart) := fanin.io.dev\n harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)\n }\n }\n\n // Priority registers are 32-bit aligned so treat each as its own group.\n // Otherwise, the off-by-one nature of the priority registers gets confusing.\n require(PLICConsts.priorityBytes == 4,\n s\"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}\")\n\n def priorityRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"priority_$i\",\n desc = s\"Acting priority of interrupt source $i\",\n group = Some(s\"priority_${i}\"),\n groupDesc = Some(s\"Acting priority of interrupt source ${i}\"),\n reset = if (nPriorities > 0) None else Some(1))\n\n def pendingRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"pending_$i\",\n desc = s\"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.\",\n group = Some(\"pending\"),\n groupDesc = Some(\"Pending Bit Array. 1 Bit for each interrupt source.\"),\n volatile = true)\n\n def enableRegDesc(i: Int, j: Int, wide: Int) = {\n val low = if (j == 0) 1 else j*8\n val high = low + wide - 1\n RegFieldDesc(\n name = s\"enables_${j}\",\n desc = s\"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.\",\n group = Some(s\"enables_${i}\"),\n groupDesc = Some(s\"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.\"))\n }\n\n def priorityRegField(x: UInt, i: Int) =\n if (nPriorities > 0) {\n RegField(prioBits, x, priorityRegDesc(i))\n } else {\n RegField.r(prioBits, x, priorityRegDesc(i))\n }\n\n val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>\n PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->\n Seq(priorityRegField(p, i+1)) }\n val pendingRegFields = Seq(PLICConsts.pendingBase ->\n (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))\n val enableRegFields = enables.zipWithIndex.map { case (e, i) =>\n PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>\n RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }\n\n // When a hart reads a claim/complete register, then the\n // device which is currently its highest priority is no longer pending.\n // This code exploits the fact that, practically, only one claim/complete\n // register can be read at a time. We check for this because if the address map\n // were to change, it may no longer be true.\n // Note: PLIC doesn't care which hart reads the register.\n val claimer = Wire(Vec(nHarts, Bool()))\n assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)\n val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)\n\n ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>\n g.ready := !p\n when (c || g.valid) { p := !c }\n }\n\n // When a hart writes a claim/complete register, then\n // the written device (as long as it is actually enabled for that\n // hart) is marked complete.\n // This code exploits the fact that, practically, only one claim/complete register\n // can be written at a time. We check for this because if the address map\n // were to change, it may no longer be true.\n // Note -- PLIC doesn't care which hart writes the register.\n val completer = Wire(Vec(nHarts, Bool()))\n assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n val completerDev = Wire(UInt(log2Up(nDevices + 1).W))\n val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)\n (gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>\n g.complete := c\n }\n\n def thresholdRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"threshold_$i\",\n desc = s\"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.\",\n reset = if (nPriorities > 0) None else Some(1))\n\n def thresholdRegField(x: UInt, i: Int) =\n if (nPriorities > 0) {\n RegField(prioBits, x, thresholdRegDesc(i))\n } else {\n RegField.r(prioBits, x, thresholdRegDesc(i))\n }\n\n val hartRegFields = Seq.tabulate(nHarts) { i =>\n PLICConsts.hartBase(i) -> Seq(\n thresholdRegField(threshold(i), i),\n RegField(32-prioBits),\n RegField(32,\n RegReadFn { valid =>\n claimer(i) := valid\n (true.B, maxDevs(i))\n },\n RegWriteFn { (valid, data) =>\n assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), \n \"completerDev should be consistent for all harts\")\n completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)\n completer(i) := valid && enableVec0(i)(completerDev)\n true.B\n },\n Some(RegFieldDesc(s\"claim_complete_$i\",\n s\"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending.\" +\n s\"Writing the interrupt number back completes the interrupt.\",\n reset = None,\n wrType = Some(RegFieldWrType.MODIFY),\n rdAction = Some(RegFieldRdAction.MODIFY),\n volatile = true))\n )\n )\n }\n\n node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)\n\n if (nDevices >= 2) {\n val claimed = claimer(0) && maxDevs(0) > 0.U\n val completed = completer(0)\n property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), \"TWO_CLAIMS\", \"two claims with no intervening complete\")\n property.cover(completed && RegEnable(completed, false.B, claimed || completed), \"TWO_COMPLETES\", \"two completes with no intervening claim\")\n\n val ep = enables(0).asUInt & pending.asUInt\n val ep2 = RegNext(ep)\n val diff = ep & ~ep2\n property.cover((diff & (diff - 1.U)) =/= 0.U, \"TWO_INTS_PENDING\", \"two enabled interrupts became pending on same cycle\")\n\n if (nPriorities > 0)\n ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),\n \"THRESHOLD\", \"interrupt pending but less than threshold\")\n }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"PLIC_$label\", \"Interrupts;;\" + desc)\n }\n}\n\nclass PLICFanIn(nDevices: Int, prioBits: Int) extends Module {\n val io = IO(new Bundle {\n val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))\n val ip = Flipped(UInt(nDevices.W))\n val dev = UInt(log2Ceil(nDevices+1).W)\n val max = UInt(prioBits.W)\n })\n\n def findMax(x: Seq[UInt]): (UInt, UInt) = {\n if (x.length > 1) {\n val half = 1 << (log2Ceil(x.length) - 1)\n val left = findMax(x take half)\n val right = findMax(x drop half)\n MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))\n } else (x.head, 0.U)\n }\n\n val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }\n val (maxPri, maxDev) = findMax(effectivePriority)\n io.max := maxPri // strips the always-constant high '1' bit\n io.dev := maxDev\n}\n\n/** Trait that will connect a PLIC to a subsystem */\ntrait CanHavePeripheryPLIC { this: BaseSubsystem =>\n val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>\n val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)\n val plicDomainWrapper = tlbus.generateSynchronousDomain(\"PLIC\").suggestName(\"plic_domain\")\n\n val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }\n plicDomainWrapper { plic.node := tlbus.coupleTo(\"plic\") { TLFragmenter(tlbus, Some(\"PLIC\")) := _ } }\n plicDomainWrapper { plic.intnode :=* ibus.toPLIC }\n\n (plic, plicDomainWrapper)\n }.unzip\n}", + "response": "module PLICFanIn(\n input io_prio_0,\n input io_ip,\n output io_dev,\n output io_max\n);\n\n wire [1:0] effectivePriority_1 = {io_ip, io_prio_0};\n assign io_dev = &effectivePriority_1;\n assign io_max = (&effectivePriority_1) & io_prio_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLEToBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_bits_head\n);\n\n assign io_beat_bits_head = 1'h1;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module next_35x6(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:34];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.devices.tilelink\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport org.chipsalliance.diplomacy.lazymodule._\n\nimport freechips.rocketchip.diplomacy.{AddressSet}\nimport freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}\nimport freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}\nimport freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}\nimport freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}\nimport freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}\nimport freechips.rocketchip.util.{Annotated, MuxT, property}\n\nimport scala.math.min\n\nimport freechips.rocketchip.util.UIntToAugmentedUInt\nimport freechips.rocketchip.util.SeqToAugmentedSeq\n\nclass GatewayPLICIO extends Bundle {\n val valid = Output(Bool())\n val ready = Input(Bool())\n val complete = Input(Bool())\n}\n\nclass LevelGateway extends Module {\n val io = IO(new Bundle {\n val interrupt = Input(Bool())\n val plic = new GatewayPLICIO\n })\n\n val inFlight = RegInit(false.B)\n when (io.interrupt && io.plic.ready) { inFlight := true.B }\n when (io.plic.complete) { inFlight := false.B }\n io.plic.valid := io.interrupt && !inFlight\n}\n\nobject PLICConsts\n{\n def maxDevices = 1023\n def maxMaxHarts = 15872\n def priorityBase = 0x0\n def pendingBase = 0x1000\n def enableBase = 0x2000\n def hartBase = 0x200000\n\n def claimOffset = 4\n def priorityBytes = 4\n\n def enableOffset(i: Int) = i * ((maxDevices+7)/8)\n def hartOffset(i: Int) = i * 0x1000\n def enableBase(i: Int):Int = enableOffset(i) + enableBase\n def hartBase(i: Int):Int = hartOffset(i) + hartBase\n\n def size(maxHarts: Int): Int = {\n require(maxHarts > 0 && maxHarts <= maxMaxHarts, s\"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}\")\n 1 << log2Ceil(hartBase(maxHarts))\n }\n\n require(hartBase >= enableBase(maxMaxHarts))\n}\n\ncase class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)\n{\n require (maxPriorities >= 0)\n def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)\n}\n\ncase object PLICKey extends Field[Option[PLICParams]](None)\n\ncase class PLICAttachParams(\n slaveWhere: TLBusWrapperLocation = CBUS\n)\n\ncase object PLICAttachKey extends Field(PLICAttachParams())\n\n/** Platform-Level Interrupt Controller */\nclass TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule\n{\n // plic0 => max devices 1023\n val device: SimpleDevice = new SimpleDevice(\"interrupt-controller\", Seq(\"riscv,plic0\")) {\n override val alwaysExtended = true\n override def describe(resources: ResourceBindings): Description = {\n val Description(name, mapping) = super.describe(resources)\n val extra = Map(\n \"interrupt-controller\" -> Nil,\n \"riscv,ndev\" -> Seq(ResourceInt(nDevices)),\n \"riscv,max-priority\" -> Seq(ResourceInt(nPriorities)),\n \"#interrupt-cells\" -> Seq(ResourceInt(1)))\n Description(name, mapping ++ extra)\n }\n }\n\n val node : TLRegisterNode = TLRegisterNode(\n address = Seq(params.address),\n device = device,\n beatBytes = beatBytes,\n undefZero = true,\n concurrency = 1) // limiting concurrency handles RAW hazards on claim registers\n\n val intnode: IntNexusNode = IntNexusNode(\n sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, \"int\"))))) },\n sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },\n outputRequiresInput = false,\n inputRequiresOutput = false)\n\n /* Negotiated sizes */\n def nDevices: Int = intnode.edges.in.map(_.source.num).sum\n def minPriorities = min(params.maxPriorities, nDevices)\n def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1\n def nHarts = intnode.edges.out.map(_.source.num).sum\n\n // Assign all the devices unique ranges\n lazy val sources = intnode.edges.in.map(_.source)\n lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {\n case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))\n }.flatten\n\n ResourceBinding {\n flatSources.foreach { s => s.resources.foreach { r =>\n // +1 because interrupt 0 is reserved\n (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }\n } }\n }\n\n lazy val module = new Impl\n class Impl extends LazyModuleImp(this) {\n Annotated.params(this, params)\n\n val (io_devices, edgesIn) = intnode.in.unzip\n val (io_harts, _) = intnode.out.unzip\n\n // Compact the interrupt vector the same way\n val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten\n // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence\n val harts = io_harts.flatten\n\n def getNInterrupts = interrupts.size\n\n println(s\"Interrupt map (${nHarts} harts ${nDevices} interrupts):\")\n flatSources.foreach { s =>\n // +1 because 0 is reserved, +1-1 because the range is half-open\n println(s\" [${s.range.start+1}, ${s.range.end}] => ${s.name}\")\n }\n println(\"\")\n\n require (nDevices == interrupts.size, s\"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}\")\n require (nHarts == harts.size, s\"Must be: nHarts=$nHarts == harts.size=${harts.size}\")\n\n require(nDevices <= PLICConsts.maxDevices, s\"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}\")\n require(nHarts > 0 && nHarts <= params.maxHarts, s\"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}\")\n\n // For now, use LevelGateways for all TL2 interrupts\n val gateways = interrupts.map { case i =>\n val gateway = Module(new LevelGateway)\n gateway.io.interrupt := i\n gateway.io.plic\n }\n\n val prioBits = log2Ceil(nPriorities+1)\n val priority =\n if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))\n else WireDefault(VecInit.fill(nDevices max 1)(1.U))\n val threshold =\n if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))\n else WireDefault(VecInit.fill(nHarts)(0.U))\n val pending = RegInit(VecInit.fill(nDevices max 1){false.B})\n\n /* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */\n val firstEnable = nDevices min 7\n val fullEnables = (nDevices - firstEnable) / 8\n val tailEnable = nDevices - firstEnable - 8*fullEnables\n def enableRegs = (Reg(UInt(firstEnable.W)) +:\n Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++\n (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)\n val enables = Seq.fill(nHarts) { enableRegs }\n val enableVec = VecInit(enables.map(x => Cat(x.reverse)))\n val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))\n \n val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))\n val pendingUInt = Cat(pending.reverse)\n if(nDevices > 0) {\n for (hart <- 0 until nHarts) {\n val fanin = Module(new PLICFanIn(nDevices, prioBits))\n fanin.io.prio := priority\n fanin.io.ip := enableVec(hart) & pendingUInt\n maxDevs(hart) := fanin.io.dev\n harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)\n }\n }\n\n // Priority registers are 32-bit aligned so treat each as its own group.\n // Otherwise, the off-by-one nature of the priority registers gets confusing.\n require(PLICConsts.priorityBytes == 4,\n s\"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}\")\n\n def priorityRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"priority_$i\",\n desc = s\"Acting priority of interrupt source $i\",\n group = Some(s\"priority_${i}\"),\n groupDesc = Some(s\"Acting priority of interrupt source ${i}\"),\n reset = if (nPriorities > 0) None else Some(1))\n\n def pendingRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"pending_$i\",\n desc = s\"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.\",\n group = Some(\"pending\"),\n groupDesc = Some(\"Pending Bit Array. 1 Bit for each interrupt source.\"),\n volatile = true)\n\n def enableRegDesc(i: Int, j: Int, wide: Int) = {\n val low = if (j == 0) 1 else j*8\n val high = low + wide - 1\n RegFieldDesc(\n name = s\"enables_${j}\",\n desc = s\"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.\",\n group = Some(s\"enables_${i}\"),\n groupDesc = Some(s\"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.\"))\n }\n\n def priorityRegField(x: UInt, i: Int) =\n if (nPriorities > 0) {\n RegField(prioBits, x, priorityRegDesc(i))\n } else {\n RegField.r(prioBits, x, priorityRegDesc(i))\n }\n\n val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>\n PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->\n Seq(priorityRegField(p, i+1)) }\n val pendingRegFields = Seq(PLICConsts.pendingBase ->\n (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))\n val enableRegFields = enables.zipWithIndex.map { case (e, i) =>\n PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>\n RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }\n\n // When a hart reads a claim/complete register, then the\n // device which is currently its highest priority is no longer pending.\n // This code exploits the fact that, practically, only one claim/complete\n // register can be read at a time. We check for this because if the address map\n // were to change, it may no longer be true.\n // Note: PLIC doesn't care which hart reads the register.\n val claimer = Wire(Vec(nHarts, Bool()))\n assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot\n val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)\n val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)\n\n ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>\n g.ready := !p\n when (c || g.valid) { p := !c }\n }\n\n // When a hart writes a claim/complete register, then\n // the written device (as long as it is actually enabled for that\n // hart) is marked complete.\n // This code exploits the fact that, practically, only one claim/complete register\n // can be written at a time. We check for this because if the address map\n // were to change, it may no longer be true.\n // Note -- PLIC doesn't care which hart writes the register.\n val completer = Wire(Vec(nHarts, Bool()))\n assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot\n val completerDev = Wire(UInt(log2Up(nDevices + 1).W))\n val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)\n (gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>\n g.complete := c\n }\n\n def thresholdRegDesc(i: Int) =\n RegFieldDesc(\n name = s\"threshold_$i\",\n desc = s\"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.\",\n reset = if (nPriorities > 0) None else Some(1))\n\n def thresholdRegField(x: UInt, i: Int) =\n if (nPriorities > 0) {\n RegField(prioBits, x, thresholdRegDesc(i))\n } else {\n RegField.r(prioBits, x, thresholdRegDesc(i))\n }\n\n val hartRegFields = Seq.tabulate(nHarts) { i =>\n PLICConsts.hartBase(i) -> Seq(\n thresholdRegField(threshold(i), i),\n RegField(32-prioBits),\n RegField(32,\n RegReadFn { valid =>\n claimer(i) := valid\n (true.B, maxDevs(i))\n },\n RegWriteFn { (valid, data) =>\n assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), \n \"completerDev should be consistent for all harts\")\n completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)\n completer(i) := valid && enableVec0(i)(completerDev)\n true.B\n },\n Some(RegFieldDesc(s\"claim_complete_$i\",\n s\"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending.\" +\n s\"Writing the interrupt number back completes the interrupt.\",\n reset = None,\n wrType = Some(RegFieldWrType.MODIFY),\n rdAction = Some(RegFieldRdAction.MODIFY),\n volatile = true))\n )\n )\n }\n\n node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)\n\n if (nDevices >= 2) {\n val claimed = claimer(0) && maxDevs(0) > 0.U\n val completed = completer(0)\n property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), \"TWO_CLAIMS\", \"two claims with no intervening complete\")\n property.cover(completed && RegEnable(completed, false.B, claimed || completed), \"TWO_COMPLETES\", \"two completes with no intervening claim\")\n\n val ep = enables(0).asUInt & pending.asUInt\n val ep2 = RegNext(ep)\n val diff = ep & ~ep2\n property.cover((diff & (diff - 1.U)) =/= 0.U, \"TWO_INTS_PENDING\", \"two enabled interrupts became pending on same cycle\")\n\n if (nPriorities > 0)\n ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),\n \"THRESHOLD\", \"interrupt pending but less than threshold\")\n }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"PLIC_$label\", \"Interrupts;;\" + desc)\n }\n}\n\nclass PLICFanIn(nDevices: Int, prioBits: Int) extends Module {\n val io = IO(new Bundle {\n val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))\n val ip = Flipped(UInt(nDevices.W))\n val dev = UInt(log2Ceil(nDevices+1).W)\n val max = UInt(prioBits.W)\n })\n\n def findMax(x: Seq[UInt]): (UInt, UInt) = {\n if (x.length > 1) {\n val half = 1 << (log2Ceil(x.length) - 1)\n val left = findMax(x take half)\n val right = findMax(x drop half)\n MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))\n } else (x.head, 0.U)\n }\n\n val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }\n val (maxPri, maxDev) = findMax(effectivePriority)\n io.max := maxPri // strips the always-constant high '1' bit\n io.dev := maxDev\n}\n\n/** Trait that will connect a PLIC to a subsystem */\ntrait CanHavePeripheryPLIC { this: BaseSubsystem =>\n val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>\n val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)\n val plicDomainWrapper = tlbus.generateSynchronousDomain(\"PLIC\").suggestName(\"plic_domain\")\n\n val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }\n plicDomainWrapper { plic.node := tlbus.coupleTo(\"plic\") { TLFragmenter(tlbus, Some(\"PLIC\")) := _ } }\n plicDomainWrapper { plic.intnode :=* ibus.toPLIC }\n\n (plic, plicDomainWrapper)\n }.unzip\n}", + "response": "module LevelGateway(\n input clock,\n input reset,\n input io_interrupt,\n output io_plic_valid,\n input io_plic_ready,\n input io_plic_complete\n);\n\n reg inFlight;\n always @(posedge clock) begin\n if (reset)\n inFlight <= 1'h0;\n else\n inFlight <= ~io_plic_complete & (io_interrupt & io_plic_ready | inFlight);\n end\n assign io_plic_valid = io_interrupt & ~inFlight;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n// See LICENSE.Berkeley for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {\n val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))\n size := typ\n val dat_padded = dat.pad(maxSize*8)\n def misaligned: Bool =\n (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR\n\n def mask = {\n var res = 1.U\n for (i <- 0 until log2Up(maxSize)) {\n val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)\n val lower = Mux(addr(i), 0.U, res)\n res = Cat(upper, lower)\n }\n res\n }\n\n protected def genData(i: Int): UInt =\n if (i >= log2Up(maxSize)) dat_padded\n else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))\n\n def data = genData(0)\n def wordData = genData(2)\n}\n\nclass LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {\n private val size = new StoreGen(typ, addr, dat, maxSize).size\n\n private def genData(logMinSize: Int): UInt = {\n var res = dat\n for (i <- log2Up(maxSize)-1 to logMinSize by -1) {\n val pos = 8 << i\n val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))\n val doZero = (i == 0).B && zero\n val zeroed = Mux(doZero, 0.U, shifted)\n res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)\n }\n res\n }\n\n def wordData = genData(2)\n def data = genData(0)\n}\n\nclass AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {\n val minXLen = 32\n val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)\n\n val io = IO(new Bundle {\n val mask = Input(UInt((operandBits / 8).W))\n val cmd = Input(UInt(M_SZ.W))\n val lhs = Input(UInt(operandBits.W))\n val rhs = Input(UInt(operandBits.W))\n val out = Output(UInt(operandBits.W))\n val out_unmasked = Output(UInt(operandBits.W))\n })\n\n val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU\n val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU\n val add = io.cmd === M_XA_ADD\n val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND\n val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR\n\n val adder_out = {\n // partition the carry chain to support sub-xLen addition\n val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)\n (io.lhs & mask) + (io.rhs & mask)\n }\n\n val less = {\n // break up the comparator so the lower parts will be CSE'd\n def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {\n if (n == minXLen) x(n-1, 0) < y(n-1, 0)\n else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)\n }\n\n def isLess(x: UInt, y: UInt, n: Int): Bool = {\n val signed = {\n val mask = M_XA_MIN ^ M_XA_MINU\n (io.cmd & mask) === (M_XA_MIN & mask)\n }\n Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))\n }\n\n PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))\n }\n\n val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)\n val logic =\n Mux(logic_and, io.lhs & io.rhs, 0.U) |\n Mux(logic_xor, io.lhs ^ io.rhs, 0.U)\n val out =\n Mux(add, adder_out,\n Mux(logic_and || logic_xor, logic,\n minmax))\n\n val wmask = FillInterleaved(8, io.mask)\n io.out := wmask & out | ~wmask & io.lhs\n io.out_unmasked := out\n}", + "response": "module AMOALU(\n input [7:0] io_mask,\n input [4:0] io_cmd,\n input [63:0] io_lhs,\n input [63:0] io_rhs,\n output [63:0] io_out\n);\n\n wire _logic_xor_T_1 = io_cmd == 5'hA;\n wire logic_and = _logic_xor_T_1 | io_cmd == 5'hB;\n wire logic_xor = io_cmd == 5'h9 | _logic_xor_T_1;\n wire [63:0] adder_out_mask = {32'hFFFFFFFF, io_mask[3], 31'h7FFFFFFF};\n wire [63:0] wmask = {{8{io_mask[7]}}, {8{io_mask[6]}}, {8{io_mask[5]}}, {8{io_mask[4]}}, {8{io_mask[3]}}, {8{io_mask[2]}}, {8{io_mask[1]}}, {8{io_mask[0]}}};\n assign io_out = wmask & (io_cmd == 5'h8 ? (io_lhs & adder_out_mask) + (io_rhs & adder_out_mask) : logic_and | logic_xor ? (logic_and ? io_lhs & io_rhs : 64'h0) | (logic_xor ? io_lhs ^ io_rhs : 64'h0) : ((io_mask[4] ? (io_lhs[63] == io_rhs[63] ? io_lhs[63:32] < io_rhs[63:32] | io_lhs[63:32] == io_rhs[63:32] & io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[63] : io_lhs[63]) : io_lhs[31] == io_rhs[31] ? io_lhs[31:0] < io_rhs[31:0] : io_cmd[1] ? io_rhs[31] : io_lhs[31]) ? io_cmd == 5'hC | io_cmd == 5'hE : io_cmd == 5'hD | io_cmd == 5'hF) ? io_lhs : io_rhs) | ~wmask & io_lhs;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.experimental._\nimport chisel3.util.HasBlackBoxResource\n\n@deprecated(\"This will be removed in Rocket Chip 2020.08\", \"Rocket Chip 2020.05\")\ncase class PlusArgInfo(default: BigInt, docstring: String)\n\n/** Case class for PlusArg information\n *\n * @tparam A scala type of the PlusArg value\n * @param default optional default value\n * @param docstring text to include in the help\n * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)\n */\nprivate case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)\n\n/** Typeclass for converting a type to a doctype string\n * @tparam A some type\n */\ntrait Doctypeable[A] {\n\n /** Return the doctype string for some option */\n def toDoctype(a: Option[A]): String\n\n}\n\n/** Object containing implementations of the Doctypeable typeclass */\nobject Doctypes {\n\n /** Converts an Int => \"INT\" */\n implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = \"INT\" }\n\n /** Converts a BigInt => \"INT\" */\n implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = \"INT\" }\n\n /** Converts a String => \"STRING\" */\n implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = \"STRING\" }\n\n}\n\nclass plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(\n \"FORMAT\" -> StringParam(format),\n \"DEFAULT\" -> IntParam(default),\n \"WIDTH\" -> IntParam(width)\n )) with HasBlackBoxResource {\n val io = IO(new Bundle {\n val out = Output(UInt(width.W))\n })\n\n addResource(\"/vsrc/plusarg_reader.v\")\n}\n\n/* This wrapper class has no outputs, making it clear it is a simulation-only construct */\nclass PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {\n val io = IO(new Bundle {\n val count = Input(UInt(width.W))\n })\n val max = Module(new plusarg_reader(format, default, docstring, width)).io.out\n when (max > 0.U) {\n assert (io.count < max, s\"Timeout exceeded: $docstring\")\n }\n}\n\nimport Doctypes._\n\nobject PlusArg\n{\n /** PlusArg(\"foo\") will return 42.U if the simulation is run with +foo=42\n * Do not use this as an initial register value. The value is set in an\n * initial block and thus accessing it from another initial is racey.\n * Add a docstring to document the arg, which can be dumped in an elaboration\n * pass.\n */\n def apply(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32): UInt = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new plusarg_reader(name + \"=%d\", default, docstring, width)).io.out\n }\n\n /** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert\n * to kill the simulation when count exceeds the specified integer argument.\n * Default 0 will never assert.\n */\n def timeout(name: String, default: BigInt = 0, docstring: String = \"\", width: Int = 32)(count: UInt): Unit = {\n PlusArgArtefacts.append(name, Some(default), docstring)\n Module(new PlusArgTimeout(name + \"=%d\", default, docstring, width)).io.count := count\n }\n}\n\nobject PlusArgArtefacts {\n private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty\n\n /* Add a new PlusArg */\n @deprecated(\n \"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08\",\n \"Rocket Chip 2020.05\"\n )\n def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)\n\n /** Add a new PlusArg\n *\n * @tparam A scala type of the PlusArg value\n * @param name name for the PlusArg\n * @param default optional default value\n * @param docstring text to include in the help\n */\n def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =\n artefacts = artefacts ++\n Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))\n\n /* From plus args, generate help text */\n private def serializeHelp_cHeader(tab: String = \"\"): String = artefacts\n .map{ case(arg, info) =>\n s\"\"\"|$tab+$arg=${info.doctype}\\\\n\\\\\n |$tab${\" \"*20}${info.docstring}\\\\n\\\\\n |\"\"\".stripMargin ++ info.default.map{ case default =>\n s\"$tab${\" \"*22}(default=${default})\\\\n\\\\\\n\"}.getOrElse(\"\")\n }.toSeq.mkString(\"\\\\n\\\\\\n\") ++ \"\\\"\"\n\n /* From plus args, generate a char array of their names */\n private def serializeArray_cHeader(tab: String = \"\"): String = {\n val prettyTab = tab + \" \" * 44 // Length of 'static const ...'\n s\"${tab}static const char * verilog_plusargs [] = {\\\\\\n\" ++\n artefacts\n .map{ case(arg, _) => s\"\"\"$prettyTab\"$arg\",\\\\\\n\"\"\" }\n .mkString(\"\")++\n s\"${prettyTab}0};\"\n }\n\n /* Generate C code to be included in emulator.cc that helps with\n * argument parsing based on available Verilog PlusArgs */\n def serialize_cHeader(): String =\n s\"\"\"|#define PLUSARG_USAGE_OPTIONS \\\"EMULATOR VERILOG PLUSARGS\\\\n\\\\\n |${serializeHelp_cHeader(\" \"*7)}\n |${serializeArray_cHeader()}\n |\"\"\".stripMargin\n}", + "response": "module PlusArgTimeout(\n input clock,\n input reset,\n input [31:0] io_count\n);\n\n wire [31:0] _plusarg_reader_out;\n plusarg_reader #(\n .DEFAULT(0),\n .FORMAT(\"max_core_cycles=%d\"),\n .WIDTH(32)\n ) plusarg_reader (\n .out (_plusarg_reader_out)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRawFN_small_e5_s11(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input io_a_isNaN,\n input io_a_isInf,\n input io_a_isZero,\n input io_a_sign,\n input [6:0] io_a_sExp,\n input [11:0] io_a_sig,\n input io_b_isNaN,\n input io_b_isInf,\n input io_b_isZero,\n input io_b_sign,\n input [6:0] io_b_sExp,\n input [11:0] io_b_sig,\n input [2:0] io_roundingMode,\n output io_rawOutValid_div,\n output io_rawOutValid_sqrt,\n output [2:0] io_roundingModeOut,\n output io_invalidExc,\n output io_infiniteExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [6:0] io_rawOut_sExp,\n output [13:0] io_rawOut_sig\n);\n\n reg [3:0] cycleNum;\n reg inReady;\n reg rawOutValid;\n reg sqrtOp_Z;\n reg majorExc_Z;\n reg isNaN_Z;\n reg isInf_Z;\n reg isZero_Z;\n reg sign_Z;\n reg [6:0] sExp_Z;\n reg [10:0] fractB_Z;\n reg [2:0] roundingMode_Z;\n reg [12:0] rem_Z;\n reg notZeroRem_Z;\n reg [12:0] sigX_Z;\n wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;\n wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);\n wire skipCycle2 = cycleNum == 4'h3 & sigX_Z[12];\n wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;\n wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign;\n wire [7:0] sExpQuot_S_div = {io_a_sExp[6], io_a_sExp} + {{3{io_b_sExp[5]}}, ~(io_b_sExp[4:0])};\n wire [10:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[9:0], 1'h0} : 11'h0;\n wire _fractB_Z_T_10 = inReady & io_sqrtOp;\n wire [15:0] _bitMask_T = 16'h1 << cycleNum;\n wire oddSqrt_S = io_sqrtOp & io_a_sExp[0];\n wire entering = inReady & io_inValid;\n wire _sigX_Z_T_7 = inReady & oddSqrt_S;\n wire [13:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 13'h0} | (_sigX_Z_T_7 ? {io_a_sig[10:9] - 2'h1, io_a_sig[8:0], 3'h0} : 14'h0) | (inReady ? 14'h0 : {rem_Z, 1'h0});\n wire [12:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 13'h0;\n wire [12:0] _trialTerm_T_9 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 11'h0}} | (_sigX_Z_T_7 ? 13'h1400 : 13'h0);\n wire [15:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[12], _trialTerm_T_9[11] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[10:0] | (inReady ? 11'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 14'h0)};\n wire newBit = $signed(trialRem) > -16'sh1;\n wire _GEN = entering | ~inReady;\n wire [3:0] _cycleNum_T_15 = {3'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? (io_a_sExp[0] ? 4'hB : 4'hC) : 4'hD) : 4'h0) | (entering | skipCycle2 ? 4'h0 : cycleNum - 4'h1);\n wire [12:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 12'h0} : 13'h0;\n wire [11:0] _GEN_0 = _sigX_Z_T_3[11:0] | {inReady & io_sqrtOp, 11'h0};\n always @(posedge clock) begin\n if (reset) begin\n cycleNum <= 4'h0;\n inReady <= 1'h1;\n rawOutValid <= 1'h0;\n end\n else if ((|cycleNum) | entering) begin\n cycleNum <= {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | skipCycle2};\n inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 < 4'h2 | skipCycle2;\n rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 4'h1 == 4'h1 | skipCycle2;\n end\n if (entering) begin\n sqrtOp_Z <= io_sqrtOp;\n majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[9]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[9]) | io_b_isNaN & ~(io_b_sig[9]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;\n isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;\n isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;\n isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;\n sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;\n sExp_Z <= io_sqrtOp ? {io_a_sExp[6], io_a_sExp[6:1]} + 7'h10 : {$signed(sExpQuot_S_div) > 8'sh37 ? 4'h6 : sExpQuot_S_div[6:3], sExpQuot_S_div[2:0]};\n roundingMode_Z <= io_roundingMode;\n end\n if (entering | ~inReady & sqrtOp_Z)\n fractB_Z <= {_fractB_Z_T_4[10] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[9:0] | {_fractB_Z_T_10 & io_a_sExp[0], 9'h0} | (inReady ? 10'h0 : fractB_Z[10:1])};\n if (_GEN) begin\n rem_Z <= newBit ? trialRem[12:0] : rem[12:0];\n sigX_Z <= {_sigX_Z_T_3[12], _GEN_0[11], _GEN_0[10:0] | (_sigX_Z_T_7 ? {newBit, 10'h0} : 11'h0)} | (inReady ? 13'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[14:2] : 13'h0);\n end\n if (_GEN & (inReady | newBit))\n notZeroRem_Z <= |trialRem;\n end\n assign io_inReady = inReady;\n assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;\n assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;\n assign io_roundingModeOut = roundingMode_Z;\n assign io_invalidExc = majorExc_Z & isNaN_Z;\n assign io_infiniteExc = majorExc_Z & ~isNaN_Z;\n assign io_rawOut_isNaN = isNaN_Z;\n assign io_rawOut_isInf = isInf_Z;\n assign io_rawOut_isZero = isZero_Z;\n assign io_rawOut_sign = sign_Z;\n assign io_rawOut_sExp = sExp_Z;\n assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundRawFNToRecFN_e11_s53(\n input io_invalidExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [12:0] io_in_sExp,\n input [55:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 roundAnyRawFNToRecFN (\n .io_invalidExc (io_invalidExc),\n .io_in_isNaN (io_in_isNaN),\n .io_in_isInf (io_in_isInf),\n .io_in_isZero (io_in_isZero),\n .io_in_sign (io_in_sign),\n .io_in_sExp (io_in_sExp),\n .io_in_sig (io_in_sig),\n .io_roundingMode (io_roundingMode),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_0(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.tilelink._\n\nclass SourceCRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val opcode = UInt(3.W)\n val param = UInt(3.W)\n val source = UInt(params.outer.bundle.sourceBits.W)\n val tag = UInt(params.tagBits.W)\n val set = UInt(params.setBits.W)\n val way = UInt(params.wayBits.W)\n val dirty = Bool()\n}\n\nclass SourceC(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new SourceCRequest(params)))\n val c = Decoupled(new TLBundleC(params.outer.bundle))\n // BankedStore port\n val bs_adr = Decoupled(new BankedStoreOuterAddress(params))\n val bs_dat = Flipped(new BankedStoreOuterDecoded(params))\n // RaW hazard\n val evict_req = new SourceDHazard(params)\n val evict_safe = Flipped(Bool())\n })\n\n // We ignore the depth and pipe is useless here (we have to provision for worst-case=stall)\n require (!params.micro.outerBuf.c.pipe)\n\n val beatBytes = params.outer.manager.beatBytes\n val beats = params.cache.blockBytes / beatBytes\n val flow = params.micro.outerBuf.c.flow\n val queue = Module(new Queue(chiselTypeOf(io.c.bits), beats + 3 + (if (flow) 0 else 1), flow = flow))\n\n // queue.io.count is far too slow\n val fillBits = log2Up(beats + 4)\n val fill = RegInit(0.U(fillBits.W))\n val room = RegInit(true.B)\n when (queue.io.enq.fire =/= queue.io.deq.fire) {\n fill := fill + Mux(queue.io.enq.fire, 1.U, ~0.U(fillBits.W))\n room := fill === 0.U || ((fill === 1.U || fill === 2.U) && !queue.io.enq.fire)\n }\n assert (room === queue.io.count <= 1.U)\n\n val busy = RegInit(false.B)\n val beat = RegInit(0.U(params.outerBeatBits.W))\n val last = if (params.cache.blockBytes == params.outer.manager.beatBytes) true.B else (beat === ~(0.U(params.outerBeatBits.W)))\n val req = Mux(!busy, io.req.bits, RegEnable(io.req.bits, !busy && io.req.valid))\n val want_data = busy || (io.req.valid && room && io.req.bits.dirty)\n\n io.req.ready := !busy && room\n\n io.evict_req.set := req.set\n io.evict_req.way := req.way\n\n io.bs_adr.valid := (beat.orR || io.evict_safe) && want_data\n io.bs_adr.bits.noop := false.B\n io.bs_adr.bits.way := req.way\n io.bs_adr.bits.set := req.set\n io.bs_adr.bits.beat := beat\n io.bs_adr.bits.mask := ~0.U(params.outerMaskBits.W)\n\n params.ccover(io.req.valid && io.req.bits.dirty && room && !io.evict_safe, \"SOURCEC_HAZARD\", \"Prevented Eviction data hazard with backpressure\")\n params.ccover(io.bs_adr.valid && !io.bs_adr.ready, \"SOURCEC_SRAM_STALL\", \"Data SRAM busy\")\n\n when (io.req.valid && room && io.req.bits.dirty) { busy := true.B }\n when (io.bs_adr.fire) {\n beat := beat + 1.U\n when (last) {\n busy := false.B\n beat := 0.U\n }\n }\n\n val s2_latch = Mux(want_data, io.bs_adr.fire, io.req.fire)\n val s2_valid = RegNext(s2_latch)\n val s2_req = RegEnable(req, s2_latch)\n val s2_beat = RegEnable(beat, s2_latch)\n val s2_last = RegEnable(last, s2_latch)\n\n val s3_latch = s2_valid\n val s3_valid = RegNext(s3_latch)\n val s3_req = RegEnable(s2_req, s3_latch)\n val s3_beat = RegEnable(s2_beat, s3_latch)\n val s3_last = RegEnable(s2_last, s3_latch)\n\n val c = Wire(chiselTypeOf(io.c))\n c.valid := s3_valid\n c.bits.opcode := s3_req.opcode\n c.bits.param := s3_req.param\n c.bits.size := params.offsetBits.U\n c.bits.source := s3_req.source\n c.bits.address := params.expandAddress(s3_req.tag, s3_req.set, 0.U)\n c.bits.data := io.bs_dat.data\n c.bits.corrupt := false.B\n\n // We never accept at the front-end unless we're sure things will fit\n assert(!c.valid || c.ready)\n params.ccover(!c.ready, \"SOURCEC_QUEUE_FULL\", \"Eviction queue fully utilized\")\n\n queue.io.enq <> c\n io.c <> queue.io.deq\n}", + "response": "module SourceC(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [2:0] io_req_bits_opcode,\n input [2:0] io_req_bits_param,\n input [1:0] io_req_bits_source,\n input [12:0] io_req_bits_tag,\n input [9:0] io_req_bits_set,\n input [2:0] io_req_bits_way,\n input io_req_bits_dirty,\n input io_c_ready,\n output io_c_valid,\n output [2:0] io_c_bits_opcode,\n output [2:0] io_c_bits_param,\n output [2:0] io_c_bits_size,\n output [1:0] io_c_bits_source,\n output [31:0] io_c_bits_address,\n output [63:0] io_c_bits_data,\n output io_c_bits_corrupt,\n input io_bs_adr_ready,\n output io_bs_adr_valid,\n output [2:0] io_bs_adr_bits_way,\n output [9:0] io_bs_adr_bits_set,\n output [2:0] io_bs_adr_bits_beat,\n input [63:0] io_bs_dat_data,\n output [9:0] io_evict_req_set,\n output [2:0] io_evict_req_way,\n input io_evict_safe\n);\n\n wire _queue_io_enq_ready;\n wire _queue_io_deq_valid;\n wire [3:0] _queue_io_count;\n reg [3:0] fill;\n reg room;\n reg busy;\n reg [2:0] beat;\n reg [2:0] req_r_opcode;\n reg [2:0] req_r_param;\n reg [1:0] req_r_source;\n reg [12:0] req_r_tag;\n reg [9:0] req_r_set;\n reg [2:0] req_r_way;\n wire [9:0] req_set = busy ? req_r_set : io_req_bits_set;\n wire [2:0] req_way = busy ? req_r_way : io_req_bits_way;\n wire _want_data_T = io_req_valid & room;\n wire want_data = busy | _want_data_T & io_req_bits_dirty;\n wire io_req_ready_0 = ~busy & room;\n wire io_bs_adr_valid_0 = ((|beat) | io_evict_safe) & want_data;\n reg s2_valid;\n reg [2:0] s2_req_opcode;\n reg [2:0] s2_req_param;\n reg [1:0] s2_req_source;\n reg [12:0] s2_req_tag;\n reg [9:0] s2_req_set;\n reg s3_valid;\n reg [2:0] s3_req_opcode;\n reg [2:0] s3_req_param;\n reg [1:0] s3_req_source;\n reg [12:0] s3_req_tag;\n reg [9:0] s3_req_set;\n wire _room_T_4 = _queue_io_enq_ready & s3_valid;\n wire _s2_latch_T = io_bs_adr_ready & io_bs_adr_valid_0;\n wire s2_latch = want_data ? _s2_latch_T : io_req_ready_0 & io_req_valid;\n always @(posedge clock) begin\n if (reset) begin\n fill <= 4'h0;\n room <= 1'h1;\n busy <= 1'h0;\n beat <= 3'h0;\n end\n else begin\n if (~(_room_T_4 == (io_c_ready & _queue_io_deq_valid))) begin\n fill <= fill + (_room_T_4 ? 4'h1 : 4'hF);\n room <= fill == 4'h0 | (fill == 4'h1 | fill == 4'h2) & ~_room_T_4;\n end\n busy <= ~(_s2_latch_T & (&beat)) & (_want_data_T & io_req_bits_dirty | busy);\n if (_s2_latch_T)\n beat <= (&beat) ? 3'h0 : beat + 3'h1;\n end\n if (~busy & io_req_valid) begin\n req_r_opcode <= io_req_bits_opcode;\n req_r_param <= io_req_bits_param;\n req_r_source <= io_req_bits_source;\n req_r_tag <= io_req_bits_tag;\n req_r_set <= io_req_bits_set;\n req_r_way <= io_req_bits_way;\n end\n s2_valid <= s2_latch;\n if (s2_latch) begin\n s2_req_opcode <= busy ? req_r_opcode : io_req_bits_opcode;\n s2_req_param <= busy ? req_r_param : io_req_bits_param;\n s2_req_source <= busy ? req_r_source : io_req_bits_source;\n s2_req_tag <= busy ? req_r_tag : io_req_bits_tag;\n s2_req_set <= req_set;\n end\n s3_valid <= s2_valid;\n if (s2_valid) begin\n s3_req_opcode <= s2_req_opcode;\n s3_req_param <= s2_req_param;\n s3_req_source <= s2_req_source;\n s3_req_tag <= s2_req_tag;\n s3_req_set <= s2_req_set;\n end\n end\n Queue12_TLBundleC_a32d64s2k3z3c queue (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_queue_io_enq_ready),\n .io_enq_valid (s3_valid),\n .io_enq_bits_opcode (s3_req_opcode),\n .io_enq_bits_param (s3_req_param),\n .io_enq_bits_source (s3_req_source),\n .io_enq_bits_address ({s3_req_tag[12], 3'h0, s3_req_tag[11:0], s3_req_set, 6'h0}),\n .io_enq_bits_data (io_bs_dat_data),\n .io_deq_ready (io_c_ready),\n .io_deq_valid (_queue_io_deq_valid),\n .io_deq_bits_opcode (io_c_bits_opcode),\n .io_deq_bits_param (io_c_bits_param),\n .io_deq_bits_size (io_c_bits_size),\n .io_deq_bits_source (io_c_bits_source),\n .io_deq_bits_address (io_c_bits_address),\n .io_deq_bits_data (io_c_bits_data),\n .io_deq_bits_corrupt (io_c_bits_corrupt),\n .io_count (_queue_io_count)\n );\n assign io_req_ready = io_req_ready_0;\n assign io_c_valid = _queue_io_deq_valid;\n assign io_bs_adr_valid = io_bs_adr_valid_0;\n assign io_bs_adr_bits_way = req_way;\n assign io_bs_adr_bits_set = req_set;\n assign io_bs_adr_bits_beat = beat;\n assign io_evict_req_set = req_set;\n assign io_evict_req_way = req_way;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.tilelink._\n\nclass SourceARequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val tag = UInt(params.tagBits.W)\n val set = UInt(params.setBits.W)\n val param = UInt(3.W)\n val source = UInt(params.outer.bundle.sourceBits.W)\n val block = Bool()\n}\n\nclass SourceA(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new SourceARequest(params)))\n val a = Decoupled(new TLBundleA(params.outer.bundle))\n })\n\n // ready must be a register, because we derive valid from ready\n require (!params.micro.outerBuf.a.pipe && params.micro.outerBuf.a.isDefined)\n\n val a = Wire(chiselTypeOf(io.a))\n io.a <> params.micro.outerBuf.a(a)\n\n io.req.ready := a.ready\n a.valid := io.req.valid\n params.ccover(a.valid && !a.ready, \"SOURCEA_STALL\", \"Backpressured when issuing an Acquire\")\n\n a.bits.opcode := Mux(io.req.bits.block, TLMessages.AcquireBlock, TLMessages.AcquirePerm)\n a.bits.param := io.req.bits.param\n a.bits.size := params.offsetBits.U\n a.bits.source := io.req.bits.source\n a.bits.address := params.expandAddress(io.req.bits.tag, io.req.bits.set, 0.U)\n a.bits.mask := ~0.U(params.outer.manager.beatBytes.W)\n a.bits.data := 0.U\n a.bits.corrupt := false.B\n}", + "response": "module SourceA(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [12:0] io_req_bits_tag,\n input [9:0] io_req_bits_set,\n input [2:0] io_req_bits_param,\n input [1:0] io_req_bits_source,\n input io_req_bits_block,\n input io_a_ready,\n output io_a_valid,\n output [2:0] io_a_bits_opcode,\n output [2:0] io_a_bits_param,\n output [2:0] io_a_bits_size,\n output [1:0] io_a_bits_source,\n output [31:0] io_a_bits_address,\n output [7:0] io_a_bits_mask,\n output [63:0] io_a_bits_data,\n output io_a_bits_corrupt\n);\n\n Queue2_TLBundleA_a32d64s2k3z3c io_a_q (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (io_req_ready),\n .io_enq_valid (io_req_valid),\n .io_enq_bits_opcode ({2'h3, ~io_req_bits_block}),\n .io_enq_bits_param (io_req_bits_param),\n .io_enq_bits_source (io_req_bits_source),\n .io_enq_bits_address ({io_req_bits_tag[12], 3'h0, io_req_bits_tag[11:0], io_req_bits_set, 6'h0}),\n .io_deq_ready (io_a_ready),\n .io_deq_valid (io_a_valid),\n .io_deq_bits_opcode (io_a_bits_opcode),\n .io_deq_bits_param (io_a_bits_param),\n .io_deq_bits_size (io_a_bits_size),\n .io_deq_bits_source (io_a_bits_source),\n .io_deq_bits_address (io_a_bits_address),\n .io_deq_bits_mask (io_a_bits_mask),\n .io_deq_bits_data (io_a_bits_data),\n .io_deq_bits_corrupt (io_a_bits_corrupt)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a32d64s5k3z4u(\n input clock,\n input reset,\n input io_repeat,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [3:0] io_enq_bits_size,\n input [4:0] io_enq_bits_source,\n input [31:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input [63:0] io_enq_bits_data,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [3:0] io_deq_bits_size,\n output [4:0] io_deq_bits_source,\n output [31:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output [63:0] io_deq_bits_data,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [3:0] saved_size;\n reg [4:0] saved_source;\n reg [31:0] saved_address;\n reg [7:0] saved_mask;\n reg [63:0] saved_data;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_data <= io_enq_bits_data;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_data = full ? saved_data : io_enq_bits_data;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module BranchKillableQueue(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [6:0] io_enq_bits_uop_uopc,\n input [31:0] io_enq_bits_uop_inst,\n input [31:0] io_enq_bits_uop_debug_inst,\n input io_enq_bits_uop_is_rvc,\n input [39:0] io_enq_bits_uop_debug_pc,\n input [2:0] io_enq_bits_uop_iq_type,\n input [9:0] io_enq_bits_uop_fu_code,\n input [3:0] io_enq_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_uop_ctrl_op_fcn,\n input io_enq_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_uop_ctrl_is_load,\n input io_enq_bits_uop_ctrl_is_sta,\n input io_enq_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_uop_iw_state,\n input io_enq_bits_uop_iw_p1_poisoned,\n input io_enq_bits_uop_iw_p2_poisoned,\n input io_enq_bits_uop_is_br,\n input io_enq_bits_uop_is_jalr,\n input io_enq_bits_uop_is_jal,\n input io_enq_bits_uop_is_sfb,\n input [7:0] io_enq_bits_uop_br_mask,\n input [2:0] io_enq_bits_uop_br_tag,\n input [3:0] io_enq_bits_uop_ftq_idx,\n input io_enq_bits_uop_edge_inst,\n input [5:0] io_enq_bits_uop_pc_lob,\n input io_enq_bits_uop_taken,\n input [19:0] io_enq_bits_uop_imm_packed,\n input [11:0] io_enq_bits_uop_csr_addr,\n input [4:0] io_enq_bits_uop_rob_idx,\n input [2:0] io_enq_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_uop_stq_idx,\n input [1:0] io_enq_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_uop_pdst,\n input [5:0] io_enq_bits_uop_prs1,\n input [5:0] io_enq_bits_uop_prs2,\n input [5:0] io_enq_bits_uop_prs3,\n input [3:0] io_enq_bits_uop_ppred,\n input io_enq_bits_uop_prs1_busy,\n input io_enq_bits_uop_prs2_busy,\n input io_enq_bits_uop_prs3_busy,\n input io_enq_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_uop_stale_pdst,\n input io_enq_bits_uop_exception,\n input [63:0] io_enq_bits_uop_exc_cause,\n input io_enq_bits_uop_bypassable,\n input [4:0] io_enq_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_uop_mem_size,\n input io_enq_bits_uop_mem_signed,\n input io_enq_bits_uop_is_fence,\n input io_enq_bits_uop_is_fencei,\n input io_enq_bits_uop_is_amo,\n input io_enq_bits_uop_uses_ldq,\n input io_enq_bits_uop_uses_stq,\n input io_enq_bits_uop_is_sys_pc2epc,\n input io_enq_bits_uop_is_unique,\n input io_enq_bits_uop_flush_on_commit,\n input io_enq_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_uop_ldst,\n input [5:0] io_enq_bits_uop_lrs1,\n input [5:0] io_enq_bits_uop_lrs2,\n input [5:0] io_enq_bits_uop_lrs3,\n input io_enq_bits_uop_ldst_val,\n input [1:0] io_enq_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_uop_lrs2_rtype,\n input io_enq_bits_uop_frs3_en,\n input io_enq_bits_uop_fp_val,\n input io_enq_bits_uop_fp_single,\n input io_enq_bits_uop_xcpt_pf_if,\n input io_enq_bits_uop_xcpt_ae_if,\n input io_enq_bits_uop_xcpt_ma_if,\n input io_enq_bits_uop_bp_debug_if,\n input io_enq_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_uop_debug_tsrc,\n input [39:0] io_enq_bits_addr,\n input [63:0] io_enq_bits_data,\n input io_enq_bits_is_hella,\n input io_enq_bits_tag_match,\n input [1:0] io_enq_bits_old_meta_coh_state,\n input [19:0] io_enq_bits_old_meta_tag,\n input [3:0] io_enq_bits_way_en,\n input [4:0] io_enq_bits_sdq_id,\n input io_deq_ready,\n output io_deq_valid,\n output [6:0] io_deq_bits_uop_uopc,\n output [31:0] io_deq_bits_uop_inst,\n output [31:0] io_deq_bits_uop_debug_inst,\n output io_deq_bits_uop_is_rvc,\n output [39:0] io_deq_bits_uop_debug_pc,\n output [2:0] io_deq_bits_uop_iq_type,\n output [9:0] io_deq_bits_uop_fu_code,\n output [3:0] io_deq_bits_uop_ctrl_br_type,\n output [1:0] io_deq_bits_uop_ctrl_op1_sel,\n output [2:0] io_deq_bits_uop_ctrl_op2_sel,\n output [2:0] io_deq_bits_uop_ctrl_imm_sel,\n output [4:0] io_deq_bits_uop_ctrl_op_fcn,\n output io_deq_bits_uop_ctrl_fcn_dw,\n output [2:0] io_deq_bits_uop_ctrl_csr_cmd,\n output io_deq_bits_uop_ctrl_is_load,\n output io_deq_bits_uop_ctrl_is_sta,\n output io_deq_bits_uop_ctrl_is_std,\n output [1:0] io_deq_bits_uop_iw_state,\n output io_deq_bits_uop_iw_p1_poisoned,\n output io_deq_bits_uop_iw_p2_poisoned,\n output io_deq_bits_uop_is_br,\n output io_deq_bits_uop_is_jalr,\n output io_deq_bits_uop_is_jal,\n output io_deq_bits_uop_is_sfb,\n output [7:0] io_deq_bits_uop_br_mask,\n output [2:0] io_deq_bits_uop_br_tag,\n output [3:0] io_deq_bits_uop_ftq_idx,\n output io_deq_bits_uop_edge_inst,\n output [5:0] io_deq_bits_uop_pc_lob,\n output io_deq_bits_uop_taken,\n output [19:0] io_deq_bits_uop_imm_packed,\n output [11:0] io_deq_bits_uop_csr_addr,\n output [4:0] io_deq_bits_uop_rob_idx,\n output [2:0] io_deq_bits_uop_ldq_idx,\n output [2:0] io_deq_bits_uop_stq_idx,\n output [1:0] io_deq_bits_uop_rxq_idx,\n output [5:0] io_deq_bits_uop_pdst,\n output [5:0] io_deq_bits_uop_prs1,\n output [5:0] io_deq_bits_uop_prs2,\n output [5:0] io_deq_bits_uop_prs3,\n output [3:0] io_deq_bits_uop_ppred,\n output io_deq_bits_uop_prs1_busy,\n output io_deq_bits_uop_prs2_busy,\n output io_deq_bits_uop_prs3_busy,\n output io_deq_bits_uop_ppred_busy,\n output [5:0] io_deq_bits_uop_stale_pdst,\n output io_deq_bits_uop_exception,\n output [63:0] io_deq_bits_uop_exc_cause,\n output io_deq_bits_uop_bypassable,\n output [4:0] io_deq_bits_uop_mem_cmd,\n output [1:0] io_deq_bits_uop_mem_size,\n output io_deq_bits_uop_mem_signed,\n output io_deq_bits_uop_is_fence,\n output io_deq_bits_uop_is_fencei,\n output io_deq_bits_uop_is_amo,\n output io_deq_bits_uop_uses_ldq,\n output io_deq_bits_uop_uses_stq,\n output io_deq_bits_uop_is_sys_pc2epc,\n output io_deq_bits_uop_is_unique,\n output io_deq_bits_uop_flush_on_commit,\n output io_deq_bits_uop_ldst_is_rs1,\n output [5:0] io_deq_bits_uop_ldst,\n output [5:0] io_deq_bits_uop_lrs1,\n output [5:0] io_deq_bits_uop_lrs2,\n output [5:0] io_deq_bits_uop_lrs3,\n output io_deq_bits_uop_ldst_val,\n output [1:0] io_deq_bits_uop_dst_rtype,\n output [1:0] io_deq_bits_uop_lrs1_rtype,\n output [1:0] io_deq_bits_uop_lrs2_rtype,\n output io_deq_bits_uop_frs3_en,\n output io_deq_bits_uop_fp_val,\n output io_deq_bits_uop_fp_single,\n output io_deq_bits_uop_xcpt_pf_if,\n output io_deq_bits_uop_xcpt_ae_if,\n output io_deq_bits_uop_xcpt_ma_if,\n output io_deq_bits_uop_bp_debug_if,\n output io_deq_bits_uop_bp_xcpt_if,\n output [1:0] io_deq_bits_uop_debug_fsrc,\n output [1:0] io_deq_bits_uop_debug_tsrc,\n output [39:0] io_deq_bits_addr,\n output io_deq_bits_is_hella,\n output [4:0] io_deq_bits_sdq_id,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_flush,\n output io_empty\n);\n\n wire [45:0] _ram_ext_R0_data;\n reg valids_0;\n reg valids_1;\n reg valids_2;\n reg valids_3;\n reg valids_4;\n reg valids_5;\n reg valids_6;\n reg valids_7;\n reg valids_8;\n reg valids_9;\n reg valids_10;\n reg valids_11;\n reg valids_12;\n reg valids_13;\n reg valids_14;\n reg valids_15;\n reg [6:0] uops_0_uopc;\n reg [31:0] uops_0_inst;\n reg [31:0] uops_0_debug_inst;\n reg uops_0_is_rvc;\n reg [39:0] uops_0_debug_pc;\n reg [2:0] uops_0_iq_type;\n reg [9:0] uops_0_fu_code;\n reg [3:0] uops_0_ctrl_br_type;\n reg [1:0] uops_0_ctrl_op1_sel;\n reg [2:0] uops_0_ctrl_op2_sel;\n reg [2:0] uops_0_ctrl_imm_sel;\n reg [4:0] uops_0_ctrl_op_fcn;\n reg uops_0_ctrl_fcn_dw;\n reg [2:0] uops_0_ctrl_csr_cmd;\n reg uops_0_ctrl_is_load;\n reg uops_0_ctrl_is_sta;\n reg uops_0_ctrl_is_std;\n reg [1:0] uops_0_iw_state;\n reg uops_0_iw_p1_poisoned;\n reg uops_0_iw_p2_poisoned;\n reg uops_0_is_br;\n reg uops_0_is_jalr;\n reg uops_0_is_jal;\n reg uops_0_is_sfb;\n reg [7:0] uops_0_br_mask;\n reg [2:0] uops_0_br_tag;\n reg [3:0] uops_0_ftq_idx;\n reg uops_0_edge_inst;\n reg [5:0] uops_0_pc_lob;\n reg uops_0_taken;\n reg [19:0] uops_0_imm_packed;\n reg [11:0] uops_0_csr_addr;\n reg [4:0] uops_0_rob_idx;\n reg [2:0] uops_0_ldq_idx;\n reg [2:0] uops_0_stq_idx;\n reg [1:0] uops_0_rxq_idx;\n reg [5:0] uops_0_pdst;\n reg [5:0] uops_0_prs1;\n reg [5:0] uops_0_prs2;\n reg [5:0] uops_0_prs3;\n reg [3:0] uops_0_ppred;\n reg uops_0_prs1_busy;\n reg uops_0_prs2_busy;\n reg uops_0_prs3_busy;\n reg uops_0_ppred_busy;\n reg [5:0] uops_0_stale_pdst;\n reg uops_0_exception;\n reg [63:0] uops_0_exc_cause;\n reg uops_0_bypassable;\n reg [4:0] uops_0_mem_cmd;\n reg [1:0] uops_0_mem_size;\n reg uops_0_mem_signed;\n reg uops_0_is_fence;\n reg uops_0_is_fencei;\n reg uops_0_is_amo;\n reg uops_0_uses_ldq;\n reg uops_0_uses_stq;\n reg uops_0_is_sys_pc2epc;\n reg uops_0_is_unique;\n reg uops_0_flush_on_commit;\n reg uops_0_ldst_is_rs1;\n reg [5:0] uops_0_ldst;\n reg [5:0] uops_0_lrs1;\n reg [5:0] uops_0_lrs2;\n reg [5:0] uops_0_lrs3;\n reg uops_0_ldst_val;\n reg [1:0] uops_0_dst_rtype;\n reg [1:0] uops_0_lrs1_rtype;\n reg [1:0] uops_0_lrs2_rtype;\n reg uops_0_frs3_en;\n reg uops_0_fp_val;\n reg uops_0_fp_single;\n reg uops_0_xcpt_pf_if;\n reg uops_0_xcpt_ae_if;\n reg uops_0_xcpt_ma_if;\n reg uops_0_bp_debug_if;\n reg uops_0_bp_xcpt_if;\n reg [1:0] uops_0_debug_fsrc;\n reg [1:0] uops_0_debug_tsrc;\n reg [6:0] uops_1_uopc;\n reg [31:0] uops_1_inst;\n reg [31:0] uops_1_debug_inst;\n reg uops_1_is_rvc;\n reg [39:0] uops_1_debug_pc;\n reg [2:0] uops_1_iq_type;\n reg [9:0] uops_1_fu_code;\n reg [3:0] uops_1_ctrl_br_type;\n reg [1:0] uops_1_ctrl_op1_sel;\n reg [2:0] uops_1_ctrl_op2_sel;\n reg [2:0] uops_1_ctrl_imm_sel;\n reg [4:0] uops_1_ctrl_op_fcn;\n reg uops_1_ctrl_fcn_dw;\n reg [2:0] uops_1_ctrl_csr_cmd;\n reg uops_1_ctrl_is_load;\n reg uops_1_ctrl_is_sta;\n reg uops_1_ctrl_is_std;\n reg [1:0] uops_1_iw_state;\n reg uops_1_iw_p1_poisoned;\n reg uops_1_iw_p2_poisoned;\n reg uops_1_is_br;\n reg uops_1_is_jalr;\n reg uops_1_is_jal;\n reg uops_1_is_sfb;\n reg [7:0] uops_1_br_mask;\n reg [2:0] uops_1_br_tag;\n reg [3:0] uops_1_ftq_idx;\n reg uops_1_edge_inst;\n reg [5:0] uops_1_pc_lob;\n reg uops_1_taken;\n reg [19:0] uops_1_imm_packed;\n reg [11:0] uops_1_csr_addr;\n reg [4:0] uops_1_rob_idx;\n reg [2:0] uops_1_ldq_idx;\n reg [2:0] uops_1_stq_idx;\n reg [1:0] uops_1_rxq_idx;\n reg [5:0] uops_1_pdst;\n reg [5:0] uops_1_prs1;\n reg [5:0] uops_1_prs2;\n reg [5:0] uops_1_prs3;\n reg [3:0] uops_1_ppred;\n reg uops_1_prs1_busy;\n reg uops_1_prs2_busy;\n reg uops_1_prs3_busy;\n reg uops_1_ppred_busy;\n reg [5:0] uops_1_stale_pdst;\n reg uops_1_exception;\n reg [63:0] uops_1_exc_cause;\n reg uops_1_bypassable;\n reg [4:0] uops_1_mem_cmd;\n reg [1:0] uops_1_mem_size;\n reg uops_1_mem_signed;\n reg uops_1_is_fence;\n reg uops_1_is_fencei;\n reg uops_1_is_amo;\n reg uops_1_uses_ldq;\n reg uops_1_uses_stq;\n reg uops_1_is_sys_pc2epc;\n reg uops_1_is_unique;\n reg uops_1_flush_on_commit;\n reg uops_1_ldst_is_rs1;\n reg [5:0] uops_1_ldst;\n reg [5:0] uops_1_lrs1;\n reg [5:0] uops_1_lrs2;\n reg [5:0] uops_1_lrs3;\n reg uops_1_ldst_val;\n reg [1:0] uops_1_dst_rtype;\n reg [1:0] uops_1_lrs1_rtype;\n reg [1:0] uops_1_lrs2_rtype;\n reg uops_1_frs3_en;\n reg uops_1_fp_val;\n reg uops_1_fp_single;\n reg uops_1_xcpt_pf_if;\n reg uops_1_xcpt_ae_if;\n reg uops_1_xcpt_ma_if;\n reg uops_1_bp_debug_if;\n reg uops_1_bp_xcpt_if;\n reg [1:0] uops_1_debug_fsrc;\n reg [1:0] uops_1_debug_tsrc;\n reg [6:0] uops_2_uopc;\n reg [31:0] uops_2_inst;\n reg [31:0] uops_2_debug_inst;\n reg uops_2_is_rvc;\n reg [39:0] uops_2_debug_pc;\n reg [2:0] uops_2_iq_type;\n reg [9:0] uops_2_fu_code;\n reg [3:0] uops_2_ctrl_br_type;\n reg [1:0] uops_2_ctrl_op1_sel;\n reg [2:0] uops_2_ctrl_op2_sel;\n reg [2:0] uops_2_ctrl_imm_sel;\n reg [4:0] uops_2_ctrl_op_fcn;\n reg uops_2_ctrl_fcn_dw;\n reg [2:0] uops_2_ctrl_csr_cmd;\n reg uops_2_ctrl_is_load;\n reg uops_2_ctrl_is_sta;\n reg uops_2_ctrl_is_std;\n reg [1:0] uops_2_iw_state;\n reg uops_2_iw_p1_poisoned;\n reg uops_2_iw_p2_poisoned;\n reg uops_2_is_br;\n reg uops_2_is_jalr;\n reg uops_2_is_jal;\n reg uops_2_is_sfb;\n reg [7:0] uops_2_br_mask;\n reg [2:0] uops_2_br_tag;\n reg [3:0] uops_2_ftq_idx;\n reg uops_2_edge_inst;\n reg [5:0] uops_2_pc_lob;\n reg uops_2_taken;\n reg [19:0] uops_2_imm_packed;\n reg [11:0] uops_2_csr_addr;\n reg [4:0] uops_2_rob_idx;\n reg [2:0] uops_2_ldq_idx;\n reg [2:0] uops_2_stq_idx;\n reg [1:0] uops_2_rxq_idx;\n reg [5:0] uops_2_pdst;\n reg [5:0] uops_2_prs1;\n reg [5:0] uops_2_prs2;\n reg [5:0] uops_2_prs3;\n reg [3:0] uops_2_ppred;\n reg uops_2_prs1_busy;\n reg uops_2_prs2_busy;\n reg uops_2_prs3_busy;\n reg uops_2_ppred_busy;\n reg [5:0] uops_2_stale_pdst;\n reg uops_2_exception;\n reg [63:0] uops_2_exc_cause;\n reg uops_2_bypassable;\n reg [4:0] uops_2_mem_cmd;\n reg [1:0] uops_2_mem_size;\n reg uops_2_mem_signed;\n reg uops_2_is_fence;\n reg uops_2_is_fencei;\n reg uops_2_is_amo;\n reg uops_2_uses_ldq;\n reg uops_2_uses_stq;\n reg uops_2_is_sys_pc2epc;\n reg uops_2_is_unique;\n reg uops_2_flush_on_commit;\n reg uops_2_ldst_is_rs1;\n reg [5:0] uops_2_ldst;\n reg [5:0] uops_2_lrs1;\n reg [5:0] uops_2_lrs2;\n reg [5:0] uops_2_lrs3;\n reg uops_2_ldst_val;\n reg [1:0] uops_2_dst_rtype;\n reg [1:0] uops_2_lrs1_rtype;\n reg [1:0] uops_2_lrs2_rtype;\n reg uops_2_frs3_en;\n reg uops_2_fp_val;\n reg uops_2_fp_single;\n reg uops_2_xcpt_pf_if;\n reg uops_2_xcpt_ae_if;\n reg uops_2_xcpt_ma_if;\n reg uops_2_bp_debug_if;\n reg uops_2_bp_xcpt_if;\n reg [1:0] uops_2_debug_fsrc;\n reg [1:0] uops_2_debug_tsrc;\n reg [6:0] uops_3_uopc;\n reg [31:0] uops_3_inst;\n reg [31:0] uops_3_debug_inst;\n reg uops_3_is_rvc;\n reg [39:0] uops_3_debug_pc;\n reg [2:0] uops_3_iq_type;\n reg [9:0] uops_3_fu_code;\n reg [3:0] uops_3_ctrl_br_type;\n reg [1:0] uops_3_ctrl_op1_sel;\n reg [2:0] uops_3_ctrl_op2_sel;\n reg [2:0] uops_3_ctrl_imm_sel;\n reg [4:0] uops_3_ctrl_op_fcn;\n reg uops_3_ctrl_fcn_dw;\n reg [2:0] uops_3_ctrl_csr_cmd;\n reg uops_3_ctrl_is_load;\n reg uops_3_ctrl_is_sta;\n reg uops_3_ctrl_is_std;\n reg [1:0] uops_3_iw_state;\n reg uops_3_iw_p1_poisoned;\n reg uops_3_iw_p2_poisoned;\n reg uops_3_is_br;\n reg uops_3_is_jalr;\n reg uops_3_is_jal;\n reg uops_3_is_sfb;\n reg [7:0] uops_3_br_mask;\n reg [2:0] uops_3_br_tag;\n reg [3:0] uops_3_ftq_idx;\n reg uops_3_edge_inst;\n reg [5:0] uops_3_pc_lob;\n reg uops_3_taken;\n reg [19:0] uops_3_imm_packed;\n reg [11:0] uops_3_csr_addr;\n reg [4:0] uops_3_rob_idx;\n reg [2:0] uops_3_ldq_idx;\n reg [2:0] uops_3_stq_idx;\n reg [1:0] uops_3_rxq_idx;\n reg [5:0] uops_3_pdst;\n reg [5:0] uops_3_prs1;\n reg [5:0] uops_3_prs2;\n reg [5:0] uops_3_prs3;\n reg [3:0] uops_3_ppred;\n reg uops_3_prs1_busy;\n reg uops_3_prs2_busy;\n reg uops_3_prs3_busy;\n reg uops_3_ppred_busy;\n reg [5:0] uops_3_stale_pdst;\n reg uops_3_exception;\n reg [63:0] uops_3_exc_cause;\n reg uops_3_bypassable;\n reg [4:0] uops_3_mem_cmd;\n reg [1:0] uops_3_mem_size;\n reg uops_3_mem_signed;\n reg uops_3_is_fence;\n reg uops_3_is_fencei;\n reg uops_3_is_amo;\n reg uops_3_uses_ldq;\n reg uops_3_uses_stq;\n reg uops_3_is_sys_pc2epc;\n reg uops_3_is_unique;\n reg uops_3_flush_on_commit;\n reg uops_3_ldst_is_rs1;\n reg [5:0] uops_3_ldst;\n reg [5:0] uops_3_lrs1;\n reg [5:0] uops_3_lrs2;\n reg [5:0] uops_3_lrs3;\n reg uops_3_ldst_val;\n reg [1:0] uops_3_dst_rtype;\n reg [1:0] uops_3_lrs1_rtype;\n reg [1:0] uops_3_lrs2_rtype;\n reg uops_3_frs3_en;\n reg uops_3_fp_val;\n reg uops_3_fp_single;\n reg uops_3_xcpt_pf_if;\n reg uops_3_xcpt_ae_if;\n reg uops_3_xcpt_ma_if;\n reg uops_3_bp_debug_if;\n reg uops_3_bp_xcpt_if;\n reg [1:0] uops_3_debug_fsrc;\n reg [1:0] uops_3_debug_tsrc;\n reg [6:0] uops_4_uopc;\n reg [31:0] uops_4_inst;\n reg [31:0] uops_4_debug_inst;\n reg uops_4_is_rvc;\n reg [39:0] uops_4_debug_pc;\n reg [2:0] uops_4_iq_type;\n reg [9:0] uops_4_fu_code;\n reg [3:0] uops_4_ctrl_br_type;\n reg [1:0] uops_4_ctrl_op1_sel;\n reg [2:0] uops_4_ctrl_op2_sel;\n reg [2:0] uops_4_ctrl_imm_sel;\n reg [4:0] uops_4_ctrl_op_fcn;\n reg uops_4_ctrl_fcn_dw;\n reg [2:0] uops_4_ctrl_csr_cmd;\n reg uops_4_ctrl_is_load;\n reg uops_4_ctrl_is_sta;\n reg uops_4_ctrl_is_std;\n reg [1:0] uops_4_iw_state;\n reg uops_4_iw_p1_poisoned;\n reg uops_4_iw_p2_poisoned;\n reg uops_4_is_br;\n reg uops_4_is_jalr;\n reg uops_4_is_jal;\n reg uops_4_is_sfb;\n reg [7:0] uops_4_br_mask;\n reg [2:0] uops_4_br_tag;\n reg [3:0] uops_4_ftq_idx;\n reg uops_4_edge_inst;\n reg [5:0] uops_4_pc_lob;\n reg uops_4_taken;\n reg [19:0] uops_4_imm_packed;\n reg [11:0] uops_4_csr_addr;\n reg [4:0] uops_4_rob_idx;\n reg [2:0] uops_4_ldq_idx;\n reg [2:0] uops_4_stq_idx;\n reg [1:0] uops_4_rxq_idx;\n reg [5:0] uops_4_pdst;\n reg [5:0] uops_4_prs1;\n reg [5:0] uops_4_prs2;\n reg [5:0] uops_4_prs3;\n reg [3:0] uops_4_ppred;\n reg uops_4_prs1_busy;\n reg uops_4_prs2_busy;\n reg uops_4_prs3_busy;\n reg uops_4_ppred_busy;\n reg [5:0] uops_4_stale_pdst;\n reg uops_4_exception;\n reg [63:0] uops_4_exc_cause;\n reg uops_4_bypassable;\n reg [4:0] uops_4_mem_cmd;\n reg [1:0] uops_4_mem_size;\n reg uops_4_mem_signed;\n reg uops_4_is_fence;\n reg uops_4_is_fencei;\n reg uops_4_is_amo;\n reg uops_4_uses_ldq;\n reg uops_4_uses_stq;\n reg uops_4_is_sys_pc2epc;\n reg uops_4_is_unique;\n reg uops_4_flush_on_commit;\n reg uops_4_ldst_is_rs1;\n reg [5:0] uops_4_ldst;\n reg [5:0] uops_4_lrs1;\n reg [5:0] uops_4_lrs2;\n reg [5:0] uops_4_lrs3;\n reg uops_4_ldst_val;\n reg [1:0] uops_4_dst_rtype;\n reg [1:0] uops_4_lrs1_rtype;\n reg [1:0] uops_4_lrs2_rtype;\n reg uops_4_frs3_en;\n reg uops_4_fp_val;\n reg uops_4_fp_single;\n reg uops_4_xcpt_pf_if;\n reg uops_4_xcpt_ae_if;\n reg uops_4_xcpt_ma_if;\n reg uops_4_bp_debug_if;\n reg uops_4_bp_xcpt_if;\n reg [1:0] uops_4_debug_fsrc;\n reg [1:0] uops_4_debug_tsrc;\n reg [6:0] uops_5_uopc;\n reg [31:0] uops_5_inst;\n reg [31:0] uops_5_debug_inst;\n reg uops_5_is_rvc;\n reg [39:0] uops_5_debug_pc;\n reg [2:0] uops_5_iq_type;\n reg [9:0] uops_5_fu_code;\n reg [3:0] uops_5_ctrl_br_type;\n reg [1:0] uops_5_ctrl_op1_sel;\n reg [2:0] uops_5_ctrl_op2_sel;\n reg [2:0] uops_5_ctrl_imm_sel;\n reg [4:0] uops_5_ctrl_op_fcn;\n reg uops_5_ctrl_fcn_dw;\n reg [2:0] uops_5_ctrl_csr_cmd;\n reg uops_5_ctrl_is_load;\n reg uops_5_ctrl_is_sta;\n reg uops_5_ctrl_is_std;\n reg [1:0] uops_5_iw_state;\n reg uops_5_iw_p1_poisoned;\n reg uops_5_iw_p2_poisoned;\n reg uops_5_is_br;\n reg uops_5_is_jalr;\n reg uops_5_is_jal;\n reg uops_5_is_sfb;\n reg [7:0] uops_5_br_mask;\n reg [2:0] uops_5_br_tag;\n reg [3:0] uops_5_ftq_idx;\n reg uops_5_edge_inst;\n reg [5:0] uops_5_pc_lob;\n reg uops_5_taken;\n reg [19:0] uops_5_imm_packed;\n reg [11:0] uops_5_csr_addr;\n reg [4:0] uops_5_rob_idx;\n reg [2:0] uops_5_ldq_idx;\n reg [2:0] uops_5_stq_idx;\n reg [1:0] uops_5_rxq_idx;\n reg [5:0] uops_5_pdst;\n reg [5:0] uops_5_prs1;\n reg [5:0] uops_5_prs2;\n reg [5:0] uops_5_prs3;\n reg [3:0] uops_5_ppred;\n reg uops_5_prs1_busy;\n reg uops_5_prs2_busy;\n reg uops_5_prs3_busy;\n reg uops_5_ppred_busy;\n reg [5:0] uops_5_stale_pdst;\n reg uops_5_exception;\n reg [63:0] uops_5_exc_cause;\n reg uops_5_bypassable;\n reg [4:0] uops_5_mem_cmd;\n reg [1:0] uops_5_mem_size;\n reg uops_5_mem_signed;\n reg uops_5_is_fence;\n reg uops_5_is_fencei;\n reg uops_5_is_amo;\n reg uops_5_uses_ldq;\n reg uops_5_uses_stq;\n reg uops_5_is_sys_pc2epc;\n reg uops_5_is_unique;\n reg uops_5_flush_on_commit;\n reg uops_5_ldst_is_rs1;\n reg [5:0] uops_5_ldst;\n reg [5:0] uops_5_lrs1;\n reg [5:0] uops_5_lrs2;\n reg [5:0] uops_5_lrs3;\n reg uops_5_ldst_val;\n reg [1:0] uops_5_dst_rtype;\n reg [1:0] uops_5_lrs1_rtype;\n reg [1:0] uops_5_lrs2_rtype;\n reg uops_5_frs3_en;\n reg uops_5_fp_val;\n reg uops_5_fp_single;\n reg uops_5_xcpt_pf_if;\n reg uops_5_xcpt_ae_if;\n reg uops_5_xcpt_ma_if;\n reg uops_5_bp_debug_if;\n reg uops_5_bp_xcpt_if;\n reg [1:0] uops_5_debug_fsrc;\n reg [1:0] uops_5_debug_tsrc;\n reg [6:0] uops_6_uopc;\n reg [31:0] uops_6_inst;\n reg [31:0] uops_6_debug_inst;\n reg uops_6_is_rvc;\n reg [39:0] uops_6_debug_pc;\n reg [2:0] uops_6_iq_type;\n reg [9:0] uops_6_fu_code;\n reg [3:0] uops_6_ctrl_br_type;\n reg [1:0] uops_6_ctrl_op1_sel;\n reg [2:0] uops_6_ctrl_op2_sel;\n reg [2:0] uops_6_ctrl_imm_sel;\n reg [4:0] uops_6_ctrl_op_fcn;\n reg uops_6_ctrl_fcn_dw;\n reg [2:0] uops_6_ctrl_csr_cmd;\n reg uops_6_ctrl_is_load;\n reg uops_6_ctrl_is_sta;\n reg uops_6_ctrl_is_std;\n reg [1:0] uops_6_iw_state;\n reg uops_6_iw_p1_poisoned;\n reg uops_6_iw_p2_poisoned;\n reg uops_6_is_br;\n reg uops_6_is_jalr;\n reg uops_6_is_jal;\n reg uops_6_is_sfb;\n reg [7:0] uops_6_br_mask;\n reg [2:0] uops_6_br_tag;\n reg [3:0] uops_6_ftq_idx;\n reg uops_6_edge_inst;\n reg [5:0] uops_6_pc_lob;\n reg uops_6_taken;\n reg [19:0] uops_6_imm_packed;\n reg [11:0] uops_6_csr_addr;\n reg [4:0] uops_6_rob_idx;\n reg [2:0] uops_6_ldq_idx;\n reg [2:0] uops_6_stq_idx;\n reg [1:0] uops_6_rxq_idx;\n reg [5:0] uops_6_pdst;\n reg [5:0] uops_6_prs1;\n reg [5:0] uops_6_prs2;\n reg [5:0] uops_6_prs3;\n reg [3:0] uops_6_ppred;\n reg uops_6_prs1_busy;\n reg uops_6_prs2_busy;\n reg uops_6_prs3_busy;\n reg uops_6_ppred_busy;\n reg [5:0] uops_6_stale_pdst;\n reg uops_6_exception;\n reg [63:0] uops_6_exc_cause;\n reg uops_6_bypassable;\n reg [4:0] uops_6_mem_cmd;\n reg [1:0] uops_6_mem_size;\n reg uops_6_mem_signed;\n reg uops_6_is_fence;\n reg uops_6_is_fencei;\n reg uops_6_is_amo;\n reg uops_6_uses_ldq;\n reg uops_6_uses_stq;\n reg uops_6_is_sys_pc2epc;\n reg uops_6_is_unique;\n reg uops_6_flush_on_commit;\n reg uops_6_ldst_is_rs1;\n reg [5:0] uops_6_ldst;\n reg [5:0] uops_6_lrs1;\n reg [5:0] uops_6_lrs2;\n reg [5:0] uops_6_lrs3;\n reg uops_6_ldst_val;\n reg [1:0] uops_6_dst_rtype;\n reg [1:0] uops_6_lrs1_rtype;\n reg [1:0] uops_6_lrs2_rtype;\n reg uops_6_frs3_en;\n reg uops_6_fp_val;\n reg uops_6_fp_single;\n reg uops_6_xcpt_pf_if;\n reg uops_6_xcpt_ae_if;\n reg uops_6_xcpt_ma_if;\n reg uops_6_bp_debug_if;\n reg uops_6_bp_xcpt_if;\n reg [1:0] uops_6_debug_fsrc;\n reg [1:0] uops_6_debug_tsrc;\n reg [6:0] uops_7_uopc;\n reg [31:0] uops_7_inst;\n reg [31:0] uops_7_debug_inst;\n reg uops_7_is_rvc;\n reg [39:0] uops_7_debug_pc;\n reg [2:0] uops_7_iq_type;\n reg [9:0] uops_7_fu_code;\n reg [3:0] uops_7_ctrl_br_type;\n reg [1:0] uops_7_ctrl_op1_sel;\n reg [2:0] uops_7_ctrl_op2_sel;\n reg [2:0] uops_7_ctrl_imm_sel;\n reg [4:0] uops_7_ctrl_op_fcn;\n reg uops_7_ctrl_fcn_dw;\n reg [2:0] uops_7_ctrl_csr_cmd;\n reg uops_7_ctrl_is_load;\n reg uops_7_ctrl_is_sta;\n reg uops_7_ctrl_is_std;\n reg [1:0] uops_7_iw_state;\n reg uops_7_iw_p1_poisoned;\n reg uops_7_iw_p2_poisoned;\n reg uops_7_is_br;\n reg uops_7_is_jalr;\n reg uops_7_is_jal;\n reg uops_7_is_sfb;\n reg [7:0] uops_7_br_mask;\n reg [2:0] uops_7_br_tag;\n reg [3:0] uops_7_ftq_idx;\n reg uops_7_edge_inst;\n reg [5:0] uops_7_pc_lob;\n reg uops_7_taken;\n reg [19:0] uops_7_imm_packed;\n reg [11:0] uops_7_csr_addr;\n reg [4:0] uops_7_rob_idx;\n reg [2:0] uops_7_ldq_idx;\n reg [2:0] uops_7_stq_idx;\n reg [1:0] uops_7_rxq_idx;\n reg [5:0] uops_7_pdst;\n reg [5:0] uops_7_prs1;\n reg [5:0] uops_7_prs2;\n reg [5:0] uops_7_prs3;\n reg [3:0] uops_7_ppred;\n reg uops_7_prs1_busy;\n reg uops_7_prs2_busy;\n reg uops_7_prs3_busy;\n reg uops_7_ppred_busy;\n reg [5:0] uops_7_stale_pdst;\n reg uops_7_exception;\n reg [63:0] uops_7_exc_cause;\n reg uops_7_bypassable;\n reg [4:0] uops_7_mem_cmd;\n reg [1:0] uops_7_mem_size;\n reg uops_7_mem_signed;\n reg uops_7_is_fence;\n reg uops_7_is_fencei;\n reg uops_7_is_amo;\n reg uops_7_uses_ldq;\n reg uops_7_uses_stq;\n reg uops_7_is_sys_pc2epc;\n reg uops_7_is_unique;\n reg uops_7_flush_on_commit;\n reg uops_7_ldst_is_rs1;\n reg [5:0] uops_7_ldst;\n reg [5:0] uops_7_lrs1;\n reg [5:0] uops_7_lrs2;\n reg [5:0] uops_7_lrs3;\n reg uops_7_ldst_val;\n reg [1:0] uops_7_dst_rtype;\n reg [1:0] uops_7_lrs1_rtype;\n reg [1:0] uops_7_lrs2_rtype;\n reg uops_7_frs3_en;\n reg uops_7_fp_val;\n reg uops_7_fp_single;\n reg uops_7_xcpt_pf_if;\n reg uops_7_xcpt_ae_if;\n reg uops_7_xcpt_ma_if;\n reg uops_7_bp_debug_if;\n reg uops_7_bp_xcpt_if;\n reg [1:0] uops_7_debug_fsrc;\n reg [1:0] uops_7_debug_tsrc;\n reg [6:0] uops_8_uopc;\n reg [31:0] uops_8_inst;\n reg [31:0] uops_8_debug_inst;\n reg uops_8_is_rvc;\n reg [39:0] uops_8_debug_pc;\n reg [2:0] uops_8_iq_type;\n reg [9:0] uops_8_fu_code;\n reg [3:0] uops_8_ctrl_br_type;\n reg [1:0] uops_8_ctrl_op1_sel;\n reg [2:0] uops_8_ctrl_op2_sel;\n reg [2:0] uops_8_ctrl_imm_sel;\n reg [4:0] uops_8_ctrl_op_fcn;\n reg uops_8_ctrl_fcn_dw;\n reg [2:0] uops_8_ctrl_csr_cmd;\n reg uops_8_ctrl_is_load;\n reg uops_8_ctrl_is_sta;\n reg uops_8_ctrl_is_std;\n reg [1:0] uops_8_iw_state;\n reg uops_8_iw_p1_poisoned;\n reg uops_8_iw_p2_poisoned;\n reg uops_8_is_br;\n reg uops_8_is_jalr;\n reg uops_8_is_jal;\n reg uops_8_is_sfb;\n reg [7:0] uops_8_br_mask;\n reg [2:0] uops_8_br_tag;\n reg [3:0] uops_8_ftq_idx;\n reg uops_8_edge_inst;\n reg [5:0] uops_8_pc_lob;\n reg uops_8_taken;\n reg [19:0] uops_8_imm_packed;\n reg [11:0] uops_8_csr_addr;\n reg [4:0] uops_8_rob_idx;\n reg [2:0] uops_8_ldq_idx;\n reg [2:0] uops_8_stq_idx;\n reg [1:0] uops_8_rxq_idx;\n reg [5:0] uops_8_pdst;\n reg [5:0] uops_8_prs1;\n reg [5:0] uops_8_prs2;\n reg [5:0] uops_8_prs3;\n reg [3:0] uops_8_ppred;\n reg uops_8_prs1_busy;\n reg uops_8_prs2_busy;\n reg uops_8_prs3_busy;\n reg uops_8_ppred_busy;\n reg [5:0] uops_8_stale_pdst;\n reg uops_8_exception;\n reg [63:0] uops_8_exc_cause;\n reg uops_8_bypassable;\n reg [4:0] uops_8_mem_cmd;\n reg [1:0] uops_8_mem_size;\n reg uops_8_mem_signed;\n reg uops_8_is_fence;\n reg uops_8_is_fencei;\n reg uops_8_is_amo;\n reg uops_8_uses_ldq;\n reg uops_8_uses_stq;\n reg uops_8_is_sys_pc2epc;\n reg uops_8_is_unique;\n reg uops_8_flush_on_commit;\n reg uops_8_ldst_is_rs1;\n reg [5:0] uops_8_ldst;\n reg [5:0] uops_8_lrs1;\n reg [5:0] uops_8_lrs2;\n reg [5:0] uops_8_lrs3;\n reg uops_8_ldst_val;\n reg [1:0] uops_8_dst_rtype;\n reg [1:0] uops_8_lrs1_rtype;\n reg [1:0] uops_8_lrs2_rtype;\n reg uops_8_frs3_en;\n reg uops_8_fp_val;\n reg uops_8_fp_single;\n reg uops_8_xcpt_pf_if;\n reg uops_8_xcpt_ae_if;\n reg uops_8_xcpt_ma_if;\n reg uops_8_bp_debug_if;\n reg uops_8_bp_xcpt_if;\n reg [1:0] uops_8_debug_fsrc;\n reg [1:0] uops_8_debug_tsrc;\n reg [6:0] uops_9_uopc;\n reg [31:0] uops_9_inst;\n reg [31:0] uops_9_debug_inst;\n reg uops_9_is_rvc;\n reg [39:0] uops_9_debug_pc;\n reg [2:0] uops_9_iq_type;\n reg [9:0] uops_9_fu_code;\n reg [3:0] uops_9_ctrl_br_type;\n reg [1:0] uops_9_ctrl_op1_sel;\n reg [2:0] uops_9_ctrl_op2_sel;\n reg [2:0] uops_9_ctrl_imm_sel;\n reg [4:0] uops_9_ctrl_op_fcn;\n reg uops_9_ctrl_fcn_dw;\n reg [2:0] uops_9_ctrl_csr_cmd;\n reg uops_9_ctrl_is_load;\n reg uops_9_ctrl_is_sta;\n reg uops_9_ctrl_is_std;\n reg [1:0] uops_9_iw_state;\n reg uops_9_iw_p1_poisoned;\n reg uops_9_iw_p2_poisoned;\n reg uops_9_is_br;\n reg uops_9_is_jalr;\n reg uops_9_is_jal;\n reg uops_9_is_sfb;\n reg [7:0] uops_9_br_mask;\n reg [2:0] uops_9_br_tag;\n reg [3:0] uops_9_ftq_idx;\n reg uops_9_edge_inst;\n reg [5:0] uops_9_pc_lob;\n reg uops_9_taken;\n reg [19:0] uops_9_imm_packed;\n reg [11:0] uops_9_csr_addr;\n reg [4:0] uops_9_rob_idx;\n reg [2:0] uops_9_ldq_idx;\n reg [2:0] uops_9_stq_idx;\n reg [1:0] uops_9_rxq_idx;\n reg [5:0] uops_9_pdst;\n reg [5:0] uops_9_prs1;\n reg [5:0] uops_9_prs2;\n reg [5:0] uops_9_prs3;\n reg [3:0] uops_9_ppred;\n reg uops_9_prs1_busy;\n reg uops_9_prs2_busy;\n reg uops_9_prs3_busy;\n reg uops_9_ppred_busy;\n reg [5:0] uops_9_stale_pdst;\n reg uops_9_exception;\n reg [63:0] uops_9_exc_cause;\n reg uops_9_bypassable;\n reg [4:0] uops_9_mem_cmd;\n reg [1:0] uops_9_mem_size;\n reg uops_9_mem_signed;\n reg uops_9_is_fence;\n reg uops_9_is_fencei;\n reg uops_9_is_amo;\n reg uops_9_uses_ldq;\n reg uops_9_uses_stq;\n reg uops_9_is_sys_pc2epc;\n reg uops_9_is_unique;\n reg uops_9_flush_on_commit;\n reg uops_9_ldst_is_rs1;\n reg [5:0] uops_9_ldst;\n reg [5:0] uops_9_lrs1;\n reg [5:0] uops_9_lrs2;\n reg [5:0] uops_9_lrs3;\n reg uops_9_ldst_val;\n reg [1:0] uops_9_dst_rtype;\n reg [1:0] uops_9_lrs1_rtype;\n reg [1:0] uops_9_lrs2_rtype;\n reg uops_9_frs3_en;\n reg uops_9_fp_val;\n reg uops_9_fp_single;\n reg uops_9_xcpt_pf_if;\n reg uops_9_xcpt_ae_if;\n reg uops_9_xcpt_ma_if;\n reg uops_9_bp_debug_if;\n reg uops_9_bp_xcpt_if;\n reg [1:0] uops_9_debug_fsrc;\n reg [1:0] uops_9_debug_tsrc;\n reg [6:0] uops_10_uopc;\n reg [31:0] uops_10_inst;\n reg [31:0] uops_10_debug_inst;\n reg uops_10_is_rvc;\n reg [39:0] uops_10_debug_pc;\n reg [2:0] uops_10_iq_type;\n reg [9:0] uops_10_fu_code;\n reg [3:0] uops_10_ctrl_br_type;\n reg [1:0] uops_10_ctrl_op1_sel;\n reg [2:0] uops_10_ctrl_op2_sel;\n reg [2:0] uops_10_ctrl_imm_sel;\n reg [4:0] uops_10_ctrl_op_fcn;\n reg uops_10_ctrl_fcn_dw;\n reg [2:0] uops_10_ctrl_csr_cmd;\n reg uops_10_ctrl_is_load;\n reg uops_10_ctrl_is_sta;\n reg uops_10_ctrl_is_std;\n reg [1:0] uops_10_iw_state;\n reg uops_10_iw_p1_poisoned;\n reg uops_10_iw_p2_poisoned;\n reg uops_10_is_br;\n reg uops_10_is_jalr;\n reg uops_10_is_jal;\n reg uops_10_is_sfb;\n reg [7:0] uops_10_br_mask;\n reg [2:0] uops_10_br_tag;\n reg [3:0] uops_10_ftq_idx;\n reg uops_10_edge_inst;\n reg [5:0] uops_10_pc_lob;\n reg uops_10_taken;\n reg [19:0] uops_10_imm_packed;\n reg [11:0] uops_10_csr_addr;\n reg [4:0] uops_10_rob_idx;\n reg [2:0] uops_10_ldq_idx;\n reg [2:0] uops_10_stq_idx;\n reg [1:0] uops_10_rxq_idx;\n reg [5:0] uops_10_pdst;\n reg [5:0] uops_10_prs1;\n reg [5:0] uops_10_prs2;\n reg [5:0] uops_10_prs3;\n reg [3:0] uops_10_ppred;\n reg uops_10_prs1_busy;\n reg uops_10_prs2_busy;\n reg uops_10_prs3_busy;\n reg uops_10_ppred_busy;\n reg [5:0] uops_10_stale_pdst;\n reg uops_10_exception;\n reg [63:0] uops_10_exc_cause;\n reg uops_10_bypassable;\n reg [4:0] uops_10_mem_cmd;\n reg [1:0] uops_10_mem_size;\n reg uops_10_mem_signed;\n reg uops_10_is_fence;\n reg uops_10_is_fencei;\n reg uops_10_is_amo;\n reg uops_10_uses_ldq;\n reg uops_10_uses_stq;\n reg uops_10_is_sys_pc2epc;\n reg uops_10_is_unique;\n reg uops_10_flush_on_commit;\n reg uops_10_ldst_is_rs1;\n reg [5:0] uops_10_ldst;\n reg [5:0] uops_10_lrs1;\n reg [5:0] uops_10_lrs2;\n reg [5:0] uops_10_lrs3;\n reg uops_10_ldst_val;\n reg [1:0] uops_10_dst_rtype;\n reg [1:0] uops_10_lrs1_rtype;\n reg [1:0] uops_10_lrs2_rtype;\n reg uops_10_frs3_en;\n reg uops_10_fp_val;\n reg uops_10_fp_single;\n reg uops_10_xcpt_pf_if;\n reg uops_10_xcpt_ae_if;\n reg uops_10_xcpt_ma_if;\n reg uops_10_bp_debug_if;\n reg uops_10_bp_xcpt_if;\n reg [1:0] uops_10_debug_fsrc;\n reg [1:0] uops_10_debug_tsrc;\n reg [6:0] uops_11_uopc;\n reg [31:0] uops_11_inst;\n reg [31:0] uops_11_debug_inst;\n reg uops_11_is_rvc;\n reg [39:0] uops_11_debug_pc;\n reg [2:0] uops_11_iq_type;\n reg [9:0] uops_11_fu_code;\n reg [3:0] uops_11_ctrl_br_type;\n reg [1:0] uops_11_ctrl_op1_sel;\n reg [2:0] uops_11_ctrl_op2_sel;\n reg [2:0] uops_11_ctrl_imm_sel;\n reg [4:0] uops_11_ctrl_op_fcn;\n reg uops_11_ctrl_fcn_dw;\n reg [2:0] uops_11_ctrl_csr_cmd;\n reg uops_11_ctrl_is_load;\n reg uops_11_ctrl_is_sta;\n reg uops_11_ctrl_is_std;\n reg [1:0] uops_11_iw_state;\n reg uops_11_iw_p1_poisoned;\n reg uops_11_iw_p2_poisoned;\n reg uops_11_is_br;\n reg uops_11_is_jalr;\n reg uops_11_is_jal;\n reg uops_11_is_sfb;\n reg [7:0] uops_11_br_mask;\n reg [2:0] uops_11_br_tag;\n reg [3:0] uops_11_ftq_idx;\n reg uops_11_edge_inst;\n reg [5:0] uops_11_pc_lob;\n reg uops_11_taken;\n reg [19:0] uops_11_imm_packed;\n reg [11:0] uops_11_csr_addr;\n reg [4:0] uops_11_rob_idx;\n reg [2:0] uops_11_ldq_idx;\n reg [2:0] uops_11_stq_idx;\n reg [1:0] uops_11_rxq_idx;\n reg [5:0] uops_11_pdst;\n reg [5:0] uops_11_prs1;\n reg [5:0] uops_11_prs2;\n reg [5:0] uops_11_prs3;\n reg [3:0] uops_11_ppred;\n reg uops_11_prs1_busy;\n reg uops_11_prs2_busy;\n reg uops_11_prs3_busy;\n reg uops_11_ppred_busy;\n reg [5:0] uops_11_stale_pdst;\n reg uops_11_exception;\n reg [63:0] uops_11_exc_cause;\n reg uops_11_bypassable;\n reg [4:0] uops_11_mem_cmd;\n reg [1:0] uops_11_mem_size;\n reg uops_11_mem_signed;\n reg uops_11_is_fence;\n reg uops_11_is_fencei;\n reg uops_11_is_amo;\n reg uops_11_uses_ldq;\n reg uops_11_uses_stq;\n reg uops_11_is_sys_pc2epc;\n reg uops_11_is_unique;\n reg uops_11_flush_on_commit;\n reg uops_11_ldst_is_rs1;\n reg [5:0] uops_11_ldst;\n reg [5:0] uops_11_lrs1;\n reg [5:0] uops_11_lrs2;\n reg [5:0] uops_11_lrs3;\n reg uops_11_ldst_val;\n reg [1:0] uops_11_dst_rtype;\n reg [1:0] uops_11_lrs1_rtype;\n reg [1:0] uops_11_lrs2_rtype;\n reg uops_11_frs3_en;\n reg uops_11_fp_val;\n reg uops_11_fp_single;\n reg uops_11_xcpt_pf_if;\n reg uops_11_xcpt_ae_if;\n reg uops_11_xcpt_ma_if;\n reg uops_11_bp_debug_if;\n reg uops_11_bp_xcpt_if;\n reg [1:0] uops_11_debug_fsrc;\n reg [1:0] uops_11_debug_tsrc;\n reg [6:0] uops_12_uopc;\n reg [31:0] uops_12_inst;\n reg [31:0] uops_12_debug_inst;\n reg uops_12_is_rvc;\n reg [39:0] uops_12_debug_pc;\n reg [2:0] uops_12_iq_type;\n reg [9:0] uops_12_fu_code;\n reg [3:0] uops_12_ctrl_br_type;\n reg [1:0] uops_12_ctrl_op1_sel;\n reg [2:0] uops_12_ctrl_op2_sel;\n reg [2:0] uops_12_ctrl_imm_sel;\n reg [4:0] uops_12_ctrl_op_fcn;\n reg uops_12_ctrl_fcn_dw;\n reg [2:0] uops_12_ctrl_csr_cmd;\n reg uops_12_ctrl_is_load;\n reg uops_12_ctrl_is_sta;\n reg uops_12_ctrl_is_std;\n reg [1:0] uops_12_iw_state;\n reg uops_12_iw_p1_poisoned;\n reg uops_12_iw_p2_poisoned;\n reg uops_12_is_br;\n reg uops_12_is_jalr;\n reg uops_12_is_jal;\n reg uops_12_is_sfb;\n reg [7:0] uops_12_br_mask;\n reg [2:0] uops_12_br_tag;\n reg [3:0] uops_12_ftq_idx;\n reg uops_12_edge_inst;\n reg [5:0] uops_12_pc_lob;\n reg uops_12_taken;\n reg [19:0] uops_12_imm_packed;\n reg [11:0] uops_12_csr_addr;\n reg [4:0] uops_12_rob_idx;\n reg [2:0] uops_12_ldq_idx;\n reg [2:0] uops_12_stq_idx;\n reg [1:0] uops_12_rxq_idx;\n reg [5:0] uops_12_pdst;\n reg [5:0] uops_12_prs1;\n reg [5:0] uops_12_prs2;\n reg [5:0] uops_12_prs3;\n reg [3:0] uops_12_ppred;\n reg uops_12_prs1_busy;\n reg uops_12_prs2_busy;\n reg uops_12_prs3_busy;\n reg uops_12_ppred_busy;\n reg [5:0] uops_12_stale_pdst;\n reg uops_12_exception;\n reg [63:0] uops_12_exc_cause;\n reg uops_12_bypassable;\n reg [4:0] uops_12_mem_cmd;\n reg [1:0] uops_12_mem_size;\n reg uops_12_mem_signed;\n reg uops_12_is_fence;\n reg uops_12_is_fencei;\n reg uops_12_is_amo;\n reg uops_12_uses_ldq;\n reg uops_12_uses_stq;\n reg uops_12_is_sys_pc2epc;\n reg uops_12_is_unique;\n reg uops_12_flush_on_commit;\n reg uops_12_ldst_is_rs1;\n reg [5:0] uops_12_ldst;\n reg [5:0] uops_12_lrs1;\n reg [5:0] uops_12_lrs2;\n reg [5:0] uops_12_lrs3;\n reg uops_12_ldst_val;\n reg [1:0] uops_12_dst_rtype;\n reg [1:0] uops_12_lrs1_rtype;\n reg [1:0] uops_12_lrs2_rtype;\n reg uops_12_frs3_en;\n reg uops_12_fp_val;\n reg uops_12_fp_single;\n reg uops_12_xcpt_pf_if;\n reg uops_12_xcpt_ae_if;\n reg uops_12_xcpt_ma_if;\n reg uops_12_bp_debug_if;\n reg uops_12_bp_xcpt_if;\n reg [1:0] uops_12_debug_fsrc;\n reg [1:0] uops_12_debug_tsrc;\n reg [6:0] uops_13_uopc;\n reg [31:0] uops_13_inst;\n reg [31:0] uops_13_debug_inst;\n reg uops_13_is_rvc;\n reg [39:0] uops_13_debug_pc;\n reg [2:0] uops_13_iq_type;\n reg [9:0] uops_13_fu_code;\n reg [3:0] uops_13_ctrl_br_type;\n reg [1:0] uops_13_ctrl_op1_sel;\n reg [2:0] uops_13_ctrl_op2_sel;\n reg [2:0] uops_13_ctrl_imm_sel;\n reg [4:0] uops_13_ctrl_op_fcn;\n reg uops_13_ctrl_fcn_dw;\n reg [2:0] uops_13_ctrl_csr_cmd;\n reg uops_13_ctrl_is_load;\n reg uops_13_ctrl_is_sta;\n reg uops_13_ctrl_is_std;\n reg [1:0] uops_13_iw_state;\n reg uops_13_iw_p1_poisoned;\n reg uops_13_iw_p2_poisoned;\n reg uops_13_is_br;\n reg uops_13_is_jalr;\n reg uops_13_is_jal;\n reg uops_13_is_sfb;\n reg [7:0] uops_13_br_mask;\n reg [2:0] uops_13_br_tag;\n reg [3:0] uops_13_ftq_idx;\n reg uops_13_edge_inst;\n reg [5:0] uops_13_pc_lob;\n reg uops_13_taken;\n reg [19:0] uops_13_imm_packed;\n reg [11:0] uops_13_csr_addr;\n reg [4:0] uops_13_rob_idx;\n reg [2:0] uops_13_ldq_idx;\n reg [2:0] uops_13_stq_idx;\n reg [1:0] uops_13_rxq_idx;\n reg [5:0] uops_13_pdst;\n reg [5:0] uops_13_prs1;\n reg [5:0] uops_13_prs2;\n reg [5:0] uops_13_prs3;\n reg [3:0] uops_13_ppred;\n reg uops_13_prs1_busy;\n reg uops_13_prs2_busy;\n reg uops_13_prs3_busy;\n reg uops_13_ppred_busy;\n reg [5:0] uops_13_stale_pdst;\n reg uops_13_exception;\n reg [63:0] uops_13_exc_cause;\n reg uops_13_bypassable;\n reg [4:0] uops_13_mem_cmd;\n reg [1:0] uops_13_mem_size;\n reg uops_13_mem_signed;\n reg uops_13_is_fence;\n reg uops_13_is_fencei;\n reg uops_13_is_amo;\n reg uops_13_uses_ldq;\n reg uops_13_uses_stq;\n reg uops_13_is_sys_pc2epc;\n reg uops_13_is_unique;\n reg uops_13_flush_on_commit;\n reg uops_13_ldst_is_rs1;\n reg [5:0] uops_13_ldst;\n reg [5:0] uops_13_lrs1;\n reg [5:0] uops_13_lrs2;\n reg [5:0] uops_13_lrs3;\n reg uops_13_ldst_val;\n reg [1:0] uops_13_dst_rtype;\n reg [1:0] uops_13_lrs1_rtype;\n reg [1:0] uops_13_lrs2_rtype;\n reg uops_13_frs3_en;\n reg uops_13_fp_val;\n reg uops_13_fp_single;\n reg uops_13_xcpt_pf_if;\n reg uops_13_xcpt_ae_if;\n reg uops_13_xcpt_ma_if;\n reg uops_13_bp_debug_if;\n reg uops_13_bp_xcpt_if;\n reg [1:0] uops_13_debug_fsrc;\n reg [1:0] uops_13_debug_tsrc;\n reg [6:0] uops_14_uopc;\n reg [31:0] uops_14_inst;\n reg [31:0] uops_14_debug_inst;\n reg uops_14_is_rvc;\n reg [39:0] uops_14_debug_pc;\n reg [2:0] uops_14_iq_type;\n reg [9:0] uops_14_fu_code;\n reg [3:0] uops_14_ctrl_br_type;\n reg [1:0] uops_14_ctrl_op1_sel;\n reg [2:0] uops_14_ctrl_op2_sel;\n reg [2:0] uops_14_ctrl_imm_sel;\n reg [4:0] uops_14_ctrl_op_fcn;\n reg uops_14_ctrl_fcn_dw;\n reg [2:0] uops_14_ctrl_csr_cmd;\n reg uops_14_ctrl_is_load;\n reg uops_14_ctrl_is_sta;\n reg uops_14_ctrl_is_std;\n reg [1:0] uops_14_iw_state;\n reg uops_14_iw_p1_poisoned;\n reg uops_14_iw_p2_poisoned;\n reg uops_14_is_br;\n reg uops_14_is_jalr;\n reg uops_14_is_jal;\n reg uops_14_is_sfb;\n reg [7:0] uops_14_br_mask;\n reg [2:0] uops_14_br_tag;\n reg [3:0] uops_14_ftq_idx;\n reg uops_14_edge_inst;\n reg [5:0] uops_14_pc_lob;\n reg uops_14_taken;\n reg [19:0] uops_14_imm_packed;\n reg [11:0] uops_14_csr_addr;\n reg [4:0] uops_14_rob_idx;\n reg [2:0] uops_14_ldq_idx;\n reg [2:0] uops_14_stq_idx;\n reg [1:0] uops_14_rxq_idx;\n reg [5:0] uops_14_pdst;\n reg [5:0] uops_14_prs1;\n reg [5:0] uops_14_prs2;\n reg [5:0] uops_14_prs3;\n reg [3:0] uops_14_ppred;\n reg uops_14_prs1_busy;\n reg uops_14_prs2_busy;\n reg uops_14_prs3_busy;\n reg uops_14_ppred_busy;\n reg [5:0] uops_14_stale_pdst;\n reg uops_14_exception;\n reg [63:0] uops_14_exc_cause;\n reg uops_14_bypassable;\n reg [4:0] uops_14_mem_cmd;\n reg [1:0] uops_14_mem_size;\n reg uops_14_mem_signed;\n reg uops_14_is_fence;\n reg uops_14_is_fencei;\n reg uops_14_is_amo;\n reg uops_14_uses_ldq;\n reg uops_14_uses_stq;\n reg uops_14_is_sys_pc2epc;\n reg uops_14_is_unique;\n reg uops_14_flush_on_commit;\n reg uops_14_ldst_is_rs1;\n reg [5:0] uops_14_ldst;\n reg [5:0] uops_14_lrs1;\n reg [5:0] uops_14_lrs2;\n reg [5:0] uops_14_lrs3;\n reg uops_14_ldst_val;\n reg [1:0] uops_14_dst_rtype;\n reg [1:0] uops_14_lrs1_rtype;\n reg [1:0] uops_14_lrs2_rtype;\n reg uops_14_frs3_en;\n reg uops_14_fp_val;\n reg uops_14_fp_single;\n reg uops_14_xcpt_pf_if;\n reg uops_14_xcpt_ae_if;\n reg uops_14_xcpt_ma_if;\n reg uops_14_bp_debug_if;\n reg uops_14_bp_xcpt_if;\n reg [1:0] uops_14_debug_fsrc;\n reg [1:0] uops_14_debug_tsrc;\n reg [6:0] uops_15_uopc;\n reg [31:0] uops_15_inst;\n reg [31:0] uops_15_debug_inst;\n reg uops_15_is_rvc;\n reg [39:0] uops_15_debug_pc;\n reg [2:0] uops_15_iq_type;\n reg [9:0] uops_15_fu_code;\n reg [3:0] uops_15_ctrl_br_type;\n reg [1:0] uops_15_ctrl_op1_sel;\n reg [2:0] uops_15_ctrl_op2_sel;\n reg [2:0] uops_15_ctrl_imm_sel;\n reg [4:0] uops_15_ctrl_op_fcn;\n reg uops_15_ctrl_fcn_dw;\n reg [2:0] uops_15_ctrl_csr_cmd;\n reg uops_15_ctrl_is_load;\n reg uops_15_ctrl_is_sta;\n reg uops_15_ctrl_is_std;\n reg [1:0] uops_15_iw_state;\n reg uops_15_iw_p1_poisoned;\n reg uops_15_iw_p2_poisoned;\n reg uops_15_is_br;\n reg uops_15_is_jalr;\n reg uops_15_is_jal;\n reg uops_15_is_sfb;\n reg [7:0] uops_15_br_mask;\n reg [2:0] uops_15_br_tag;\n reg [3:0] uops_15_ftq_idx;\n reg uops_15_edge_inst;\n reg [5:0] uops_15_pc_lob;\n reg uops_15_taken;\n reg [19:0] uops_15_imm_packed;\n reg [11:0] uops_15_csr_addr;\n reg [4:0] uops_15_rob_idx;\n reg [2:0] uops_15_ldq_idx;\n reg [2:0] uops_15_stq_idx;\n reg [1:0] uops_15_rxq_idx;\n reg [5:0] uops_15_pdst;\n reg [5:0] uops_15_prs1;\n reg [5:0] uops_15_prs2;\n reg [5:0] uops_15_prs3;\n reg [3:0] uops_15_ppred;\n reg uops_15_prs1_busy;\n reg uops_15_prs2_busy;\n reg uops_15_prs3_busy;\n reg uops_15_ppred_busy;\n reg [5:0] uops_15_stale_pdst;\n reg uops_15_exception;\n reg [63:0] uops_15_exc_cause;\n reg uops_15_bypassable;\n reg [4:0] uops_15_mem_cmd;\n reg [1:0] uops_15_mem_size;\n reg uops_15_mem_signed;\n reg uops_15_is_fence;\n reg uops_15_is_fencei;\n reg uops_15_is_amo;\n reg uops_15_uses_ldq;\n reg uops_15_uses_stq;\n reg uops_15_is_sys_pc2epc;\n reg uops_15_is_unique;\n reg uops_15_flush_on_commit;\n reg uops_15_ldst_is_rs1;\n reg [5:0] uops_15_ldst;\n reg [5:0] uops_15_lrs1;\n reg [5:0] uops_15_lrs2;\n reg [5:0] uops_15_lrs3;\n reg uops_15_ldst_val;\n reg [1:0] uops_15_dst_rtype;\n reg [1:0] uops_15_lrs1_rtype;\n reg [1:0] uops_15_lrs2_rtype;\n reg uops_15_frs3_en;\n reg uops_15_fp_val;\n reg uops_15_fp_single;\n reg uops_15_xcpt_pf_if;\n reg uops_15_xcpt_ae_if;\n reg uops_15_xcpt_ma_if;\n reg uops_15_bp_debug_if;\n reg uops_15_bp_xcpt_if;\n reg [1:0] uops_15_debug_fsrc;\n reg [1:0] uops_15_debug_tsrc;\n reg [3:0] enq_ptr_value;\n reg [3:0] deq_ptr_value;\n reg maybe_full;\n wire ptr_match = enq_ptr_value == deq_ptr_value;\n wire io_empty_0 = ptr_match & ~maybe_full;\n wire full = ptr_match & maybe_full;\n wire do_enq = ~full & io_enq_valid;\n wire [15:0] _GEN = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}};\n wire _GEN_0 = _GEN[deq_ptr_value];\n wire [15:0][6:0] _GEN_1 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};\n wire [15:0][31:0] _GEN_2 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}};\n wire [15:0][31:0] _GEN_3 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}};\n wire [15:0] _GEN_4 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}};\n wire [15:0][39:0] _GEN_5 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}};\n wire [15:0][2:0] _GEN_6 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}};\n wire [15:0][9:0] _GEN_7 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}};\n wire [15:0][3:0] _GEN_8 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}};\n wire [15:0][1:0] _GEN_9 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}};\n wire [15:0][2:0] _GEN_10 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}};\n wire [15:0][2:0] _GEN_11 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}};\n wire [15:0][4:0] _GEN_12 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}};\n wire [15:0] _GEN_13 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}};\n wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}};\n wire [15:0] _GEN_15 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}};\n wire [15:0] _GEN_16 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}};\n wire [15:0] _GEN_17 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}};\n wire [15:0][1:0] _GEN_18 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}};\n wire [15:0] _GEN_19 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}};\n wire [15:0] _GEN_20 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}};\n wire [15:0] _GEN_21 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}};\n wire [15:0] _GEN_22 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}};\n wire [15:0] _GEN_23 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}};\n wire [15:0] _GEN_24 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}};\n wire [15:0][7:0] _GEN_25 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};\n wire [7:0] out_uop_br_mask = _GEN_25[deq_ptr_value];\n wire [15:0][2:0] _GEN_26 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}};\n wire [15:0][3:0] _GEN_27 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}};\n wire [15:0] _GEN_28 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}};\n wire [15:0][5:0] _GEN_29 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}};\n wire [15:0] _GEN_30 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}};\n wire [15:0][19:0] _GEN_31 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}};\n wire [15:0][11:0] _GEN_32 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}};\n wire [15:0][4:0] _GEN_33 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};\n wire [15:0][2:0] _GEN_34 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}};\n wire [15:0][2:0] _GEN_35 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};\n wire [15:0][1:0] _GEN_36 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}};\n wire [15:0][5:0] _GEN_37 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};\n wire [15:0][5:0] _GEN_38 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}};\n wire [15:0][5:0] _GEN_39 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}};\n wire [15:0][5:0] _GEN_40 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}};\n wire [15:0][3:0] _GEN_41 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}};\n wire [15:0] _GEN_42 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}};\n wire [15:0] _GEN_43 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}};\n wire [15:0] _GEN_44 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}};\n wire [15:0] _GEN_45 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}};\n wire [15:0][5:0] _GEN_46 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}};\n wire [15:0] _GEN_47 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}};\n wire [15:0][63:0] _GEN_48 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}};\n wire [15:0] _GEN_49 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}};\n wire [15:0][4:0] _GEN_50 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}};\n wire [15:0][1:0] _GEN_51 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}};\n wire [15:0] _GEN_52 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}};\n wire [15:0] _GEN_53 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}};\n wire [15:0] _GEN_54 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}};\n wire [15:0] _GEN_55 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};\n wire [15:0] _GEN_56 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}};\n wire out_uop_uses_ldq = _GEN_56[deq_ptr_value];\n wire [15:0] _GEN_57 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};\n wire [15:0] _GEN_58 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}};\n wire [15:0] _GEN_59 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}};\n wire [15:0] _GEN_60 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}};\n wire [15:0] _GEN_61 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}};\n wire [15:0][5:0] _GEN_62 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}};\n wire [15:0][5:0] _GEN_63 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}};\n wire [15:0][5:0] _GEN_64 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}};\n wire [15:0][5:0] _GEN_65 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}};\n wire [15:0] _GEN_66 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}};\n wire [15:0][1:0] _GEN_67 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};\n wire [15:0][1:0] _GEN_68 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}};\n wire [15:0][1:0] _GEN_69 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}};\n wire [15:0] _GEN_70 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}};\n wire [15:0] _GEN_71 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};\n wire [15:0] _GEN_72 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}};\n wire [15:0] _GEN_73 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}};\n wire [15:0] _GEN_74 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}};\n wire [15:0] _GEN_75 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}};\n wire [15:0] _GEN_76 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}};\n wire [15:0] _GEN_77 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}};\n wire [15:0][1:0] _GEN_78 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}};\n wire [15:0][1:0] _GEN_79 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}};\n wire do_deq = (io_deq_ready | ~_GEN_0) & ~io_empty_0;\n wire _GEN_80 = enq_ptr_value == 4'h0;\n wire _GEN_81 = do_enq & _GEN_80;\n wire _GEN_82 = enq_ptr_value == 4'h1;\n wire _GEN_83 = do_enq & _GEN_82;\n wire _GEN_84 = enq_ptr_value == 4'h2;\n wire _GEN_85 = do_enq & _GEN_84;\n wire _GEN_86 = enq_ptr_value == 4'h3;\n wire _GEN_87 = do_enq & _GEN_86;\n wire _GEN_88 = enq_ptr_value == 4'h4;\n wire _GEN_89 = do_enq & _GEN_88;\n wire _GEN_90 = enq_ptr_value == 4'h5;\n wire _GEN_91 = do_enq & _GEN_90;\n wire _GEN_92 = enq_ptr_value == 4'h6;\n wire _GEN_93 = do_enq & _GEN_92;\n wire _GEN_94 = enq_ptr_value == 4'h7;\n wire _GEN_95 = do_enq & _GEN_94;\n wire _GEN_96 = enq_ptr_value == 4'h8;\n wire _GEN_97 = do_enq & _GEN_96;\n wire _GEN_98 = enq_ptr_value == 4'h9;\n wire _GEN_99 = do_enq & _GEN_98;\n wire _GEN_100 = enq_ptr_value == 4'hA;\n wire _GEN_101 = do_enq & _GEN_100;\n wire _GEN_102 = enq_ptr_value == 4'hB;\n wire _GEN_103 = do_enq & _GEN_102;\n wire _GEN_104 = enq_ptr_value == 4'hC;\n wire _GEN_105 = do_enq & _GEN_104;\n wire _GEN_106 = enq_ptr_value == 4'hD;\n wire _GEN_107 = do_enq & _GEN_106;\n wire _GEN_108 = enq_ptr_value == 4'hE;\n wire _GEN_109 = do_enq & _GEN_108;\n wire _GEN_110 = do_enq & (&enq_ptr_value);\n wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n valids_0 <= 1'h0;\n valids_1 <= 1'h0;\n valids_2 <= 1'h0;\n valids_3 <= 1'h0;\n valids_4 <= 1'h0;\n valids_5 <= 1'h0;\n valids_6 <= 1'h0;\n valids_7 <= 1'h0;\n valids_8 <= 1'h0;\n valids_9 <= 1'h0;\n valids_10 <= 1'h0;\n valids_11 <= 1'h0;\n valids_12 <= 1'h0;\n valids_13 <= 1'h0;\n valids_14 <= 1'h0;\n valids_15 <= 1'h0;\n enq_ptr_value <= 4'h0;\n deq_ptr_value <= 4'h0;\n maybe_full <= 1'h0;\n end\n else begin\n valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_81 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~(io_flush & uops_0_uses_ldq));\n valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_83 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~(io_flush & uops_1_uses_ldq));\n valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_85 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~(io_flush & uops_2_uses_ldq));\n valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_87 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~(io_flush & uops_3_uses_ldq));\n valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_89 | valids_4 & (io_brupdate_b1_mispredict_mask & uops_4_br_mask) == 8'h0 & ~(io_flush & uops_4_uses_ldq));\n valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_91 | valids_5 & (io_brupdate_b1_mispredict_mask & uops_5_br_mask) == 8'h0 & ~(io_flush & uops_5_uses_ldq));\n valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_93 | valids_6 & (io_brupdate_b1_mispredict_mask & uops_6_br_mask) == 8'h0 & ~(io_flush & uops_6_uses_ldq));\n valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_95 | valids_7 & (io_brupdate_b1_mispredict_mask & uops_7_br_mask) == 8'h0 & ~(io_flush & uops_7_uses_ldq));\n valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_97 | valids_8 & (io_brupdate_b1_mispredict_mask & uops_8_br_mask) == 8'h0 & ~(io_flush & uops_8_uses_ldq));\n valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_99 | valids_9 & (io_brupdate_b1_mispredict_mask & uops_9_br_mask) == 8'h0 & ~(io_flush & uops_9_uses_ldq));\n valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_101 | valids_10 & (io_brupdate_b1_mispredict_mask & uops_10_br_mask) == 8'h0 & ~(io_flush & uops_10_uses_ldq));\n valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_103 | valids_11 & (io_brupdate_b1_mispredict_mask & uops_11_br_mask) == 8'h0 & ~(io_flush & uops_11_uses_ldq));\n valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_105 | valids_12 & (io_brupdate_b1_mispredict_mask & uops_12_br_mask) == 8'h0 & ~(io_flush & uops_12_uses_ldq));\n valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_107 | valids_13 & (io_brupdate_b1_mispredict_mask & uops_13_br_mask) == 8'h0 & ~(io_flush & uops_13_uses_ldq));\n valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_109 | valids_14 & (io_brupdate_b1_mispredict_mask & uops_14_br_mask) == 8'h0 & ~(io_flush & uops_14_uses_ldq));\n valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_110 | valids_15 & (io_brupdate_b1_mispredict_mask & uops_15_br_mask) == 8'h0 & ~(io_flush & uops_15_uses_ldq));\n if (do_enq)\n enq_ptr_value <= enq_ptr_value + 4'h1;\n if (do_deq)\n deq_ptr_value <= deq_ptr_value + 4'h1;\n if (~(do_enq == do_deq))\n maybe_full <= do_enq;\n end\n if (_GEN_81) begin\n uops_0_uopc <= io_enq_bits_uop_uopc;\n uops_0_inst <= io_enq_bits_uop_inst;\n uops_0_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_0_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_0_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_0_iq_type <= io_enq_bits_uop_iq_type;\n uops_0_fu_code <= io_enq_bits_uop_fu_code;\n uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_0_iw_state <= io_enq_bits_uop_iw_state;\n uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_0_is_br <= io_enq_bits_uop_is_br;\n uops_0_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_0_is_jal <= io_enq_bits_uop_is_jal;\n uops_0_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_0_br_tag <= io_enq_bits_uop_br_tag;\n uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_0_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_0_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_0_taken <= io_enq_bits_uop_taken;\n uops_0_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_0_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_0_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_0_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_0_pdst <= io_enq_bits_uop_pdst;\n uops_0_prs1 <= io_enq_bits_uop_prs1;\n uops_0_prs2 <= io_enq_bits_uop_prs2;\n uops_0_prs3 <= io_enq_bits_uop_prs3;\n uops_0_ppred <= io_enq_bits_uop_ppred;\n uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_0_exception <= io_enq_bits_uop_exception;\n uops_0_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_0_bypassable <= io_enq_bits_uop_bypassable;\n uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_0_mem_size <= io_enq_bits_uop_mem_size;\n uops_0_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_0_is_fence <= io_enq_bits_uop_is_fence;\n uops_0_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_0_is_amo <= io_enq_bits_uop_is_amo;\n uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_0_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_0_is_unique <= io_enq_bits_uop_is_unique;\n uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_0_ldst <= io_enq_bits_uop_ldst;\n uops_0_lrs1 <= io_enq_bits_uop_lrs1;\n uops_0_lrs2 <= io_enq_bits_uop_lrs2;\n uops_0_lrs3 <= io_enq_bits_uop_lrs3;\n uops_0_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_0_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_0_fp_val <= io_enq_bits_uop_fp_val;\n uops_0_fp_single <= io_enq_bits_uop_fp_single;\n uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_0_br_mask <= do_enq & _GEN_80 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;\n if (_GEN_83) begin\n uops_1_uopc <= io_enq_bits_uop_uopc;\n uops_1_inst <= io_enq_bits_uop_inst;\n uops_1_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_1_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_1_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_1_iq_type <= io_enq_bits_uop_iq_type;\n uops_1_fu_code <= io_enq_bits_uop_fu_code;\n uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_1_iw_state <= io_enq_bits_uop_iw_state;\n uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_1_is_br <= io_enq_bits_uop_is_br;\n uops_1_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_1_is_jal <= io_enq_bits_uop_is_jal;\n uops_1_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_1_br_tag <= io_enq_bits_uop_br_tag;\n uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_1_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_1_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_1_taken <= io_enq_bits_uop_taken;\n uops_1_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_1_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_1_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_1_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_1_pdst <= io_enq_bits_uop_pdst;\n uops_1_prs1 <= io_enq_bits_uop_prs1;\n uops_1_prs2 <= io_enq_bits_uop_prs2;\n uops_1_prs3 <= io_enq_bits_uop_prs3;\n uops_1_ppred <= io_enq_bits_uop_ppred;\n uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_1_exception <= io_enq_bits_uop_exception;\n uops_1_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_1_bypassable <= io_enq_bits_uop_bypassable;\n uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_1_mem_size <= io_enq_bits_uop_mem_size;\n uops_1_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_1_is_fence <= io_enq_bits_uop_is_fence;\n uops_1_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_1_is_amo <= io_enq_bits_uop_is_amo;\n uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_1_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_1_is_unique <= io_enq_bits_uop_is_unique;\n uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_1_ldst <= io_enq_bits_uop_ldst;\n uops_1_lrs1 <= io_enq_bits_uop_lrs1;\n uops_1_lrs2 <= io_enq_bits_uop_lrs2;\n uops_1_lrs3 <= io_enq_bits_uop_lrs3;\n uops_1_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_1_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_1_fp_val <= io_enq_bits_uop_fp_val;\n uops_1_fp_single <= io_enq_bits_uop_fp_single;\n uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_1_br_mask <= do_enq & _GEN_82 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;\n if (_GEN_85) begin\n uops_2_uopc <= io_enq_bits_uop_uopc;\n uops_2_inst <= io_enq_bits_uop_inst;\n uops_2_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_2_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_2_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_2_iq_type <= io_enq_bits_uop_iq_type;\n uops_2_fu_code <= io_enq_bits_uop_fu_code;\n uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_2_iw_state <= io_enq_bits_uop_iw_state;\n uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_2_is_br <= io_enq_bits_uop_is_br;\n uops_2_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_2_is_jal <= io_enq_bits_uop_is_jal;\n uops_2_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_2_br_tag <= io_enq_bits_uop_br_tag;\n uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_2_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_2_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_2_taken <= io_enq_bits_uop_taken;\n uops_2_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_2_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_2_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_2_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_2_pdst <= io_enq_bits_uop_pdst;\n uops_2_prs1 <= io_enq_bits_uop_prs1;\n uops_2_prs2 <= io_enq_bits_uop_prs2;\n uops_2_prs3 <= io_enq_bits_uop_prs3;\n uops_2_ppred <= io_enq_bits_uop_ppred;\n uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_2_exception <= io_enq_bits_uop_exception;\n uops_2_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_2_bypassable <= io_enq_bits_uop_bypassable;\n uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_2_mem_size <= io_enq_bits_uop_mem_size;\n uops_2_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_2_is_fence <= io_enq_bits_uop_is_fence;\n uops_2_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_2_is_amo <= io_enq_bits_uop_is_amo;\n uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_2_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_2_is_unique <= io_enq_bits_uop_is_unique;\n uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_2_ldst <= io_enq_bits_uop_ldst;\n uops_2_lrs1 <= io_enq_bits_uop_lrs1;\n uops_2_lrs2 <= io_enq_bits_uop_lrs2;\n uops_2_lrs3 <= io_enq_bits_uop_lrs3;\n uops_2_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_2_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_2_fp_val <= io_enq_bits_uop_fp_val;\n uops_2_fp_single <= io_enq_bits_uop_fp_single;\n uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_2_br_mask <= do_enq & _GEN_84 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;\n if (_GEN_87) begin\n uops_3_uopc <= io_enq_bits_uop_uopc;\n uops_3_inst <= io_enq_bits_uop_inst;\n uops_3_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_3_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_3_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_3_iq_type <= io_enq_bits_uop_iq_type;\n uops_3_fu_code <= io_enq_bits_uop_fu_code;\n uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_3_iw_state <= io_enq_bits_uop_iw_state;\n uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_3_is_br <= io_enq_bits_uop_is_br;\n uops_3_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_3_is_jal <= io_enq_bits_uop_is_jal;\n uops_3_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_3_br_tag <= io_enq_bits_uop_br_tag;\n uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_3_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_3_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_3_taken <= io_enq_bits_uop_taken;\n uops_3_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_3_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_3_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_3_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_3_pdst <= io_enq_bits_uop_pdst;\n uops_3_prs1 <= io_enq_bits_uop_prs1;\n uops_3_prs2 <= io_enq_bits_uop_prs2;\n uops_3_prs3 <= io_enq_bits_uop_prs3;\n uops_3_ppred <= io_enq_bits_uop_ppred;\n uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_3_exception <= io_enq_bits_uop_exception;\n uops_3_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_3_bypassable <= io_enq_bits_uop_bypassable;\n uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_3_mem_size <= io_enq_bits_uop_mem_size;\n uops_3_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_3_is_fence <= io_enq_bits_uop_is_fence;\n uops_3_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_3_is_amo <= io_enq_bits_uop_is_amo;\n uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_3_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_3_is_unique <= io_enq_bits_uop_is_unique;\n uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_3_ldst <= io_enq_bits_uop_ldst;\n uops_3_lrs1 <= io_enq_bits_uop_lrs1;\n uops_3_lrs2 <= io_enq_bits_uop_lrs2;\n uops_3_lrs3 <= io_enq_bits_uop_lrs3;\n uops_3_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_3_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_3_fp_val <= io_enq_bits_uop_fp_val;\n uops_3_fp_single <= io_enq_bits_uop_fp_single;\n uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_3_br_mask <= do_enq & _GEN_86 ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;\n if (_GEN_89) begin\n uops_4_uopc <= io_enq_bits_uop_uopc;\n uops_4_inst <= io_enq_bits_uop_inst;\n uops_4_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_4_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_4_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_4_iq_type <= io_enq_bits_uop_iq_type;\n uops_4_fu_code <= io_enq_bits_uop_fu_code;\n uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_4_iw_state <= io_enq_bits_uop_iw_state;\n uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_4_is_br <= io_enq_bits_uop_is_br;\n uops_4_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_4_is_jal <= io_enq_bits_uop_is_jal;\n uops_4_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_4_br_tag <= io_enq_bits_uop_br_tag;\n uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_4_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_4_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_4_taken <= io_enq_bits_uop_taken;\n uops_4_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_4_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_4_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_4_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_4_pdst <= io_enq_bits_uop_pdst;\n uops_4_prs1 <= io_enq_bits_uop_prs1;\n uops_4_prs2 <= io_enq_bits_uop_prs2;\n uops_4_prs3 <= io_enq_bits_uop_prs3;\n uops_4_ppred <= io_enq_bits_uop_ppred;\n uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_4_exception <= io_enq_bits_uop_exception;\n uops_4_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_4_bypassable <= io_enq_bits_uop_bypassable;\n uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_4_mem_size <= io_enq_bits_uop_mem_size;\n uops_4_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_4_is_fence <= io_enq_bits_uop_is_fence;\n uops_4_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_4_is_amo <= io_enq_bits_uop_is_amo;\n uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_4_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_4_is_unique <= io_enq_bits_uop_is_unique;\n uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_4_ldst <= io_enq_bits_uop_ldst;\n uops_4_lrs1 <= io_enq_bits_uop_lrs1;\n uops_4_lrs2 <= io_enq_bits_uop_lrs2;\n uops_4_lrs3 <= io_enq_bits_uop_lrs3;\n uops_4_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_4_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_4_fp_val <= io_enq_bits_uop_fp_val;\n uops_4_fp_single <= io_enq_bits_uop_fp_single;\n uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_4_br_mask <= do_enq & _GEN_88 ? _uops_br_mask_T_1 : ({8{~valids_4}} | ~io_brupdate_b1_resolve_mask) & uops_4_br_mask;\n if (_GEN_91) begin\n uops_5_uopc <= io_enq_bits_uop_uopc;\n uops_5_inst <= io_enq_bits_uop_inst;\n uops_5_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_5_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_5_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_5_iq_type <= io_enq_bits_uop_iq_type;\n uops_5_fu_code <= io_enq_bits_uop_fu_code;\n uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_5_iw_state <= io_enq_bits_uop_iw_state;\n uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_5_is_br <= io_enq_bits_uop_is_br;\n uops_5_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_5_is_jal <= io_enq_bits_uop_is_jal;\n uops_5_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_5_br_tag <= io_enq_bits_uop_br_tag;\n uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_5_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_5_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_5_taken <= io_enq_bits_uop_taken;\n uops_5_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_5_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_5_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_5_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_5_pdst <= io_enq_bits_uop_pdst;\n uops_5_prs1 <= io_enq_bits_uop_prs1;\n uops_5_prs2 <= io_enq_bits_uop_prs2;\n uops_5_prs3 <= io_enq_bits_uop_prs3;\n uops_5_ppred <= io_enq_bits_uop_ppred;\n uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_5_exception <= io_enq_bits_uop_exception;\n uops_5_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_5_bypassable <= io_enq_bits_uop_bypassable;\n uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_5_mem_size <= io_enq_bits_uop_mem_size;\n uops_5_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_5_is_fence <= io_enq_bits_uop_is_fence;\n uops_5_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_5_is_amo <= io_enq_bits_uop_is_amo;\n uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_5_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_5_is_unique <= io_enq_bits_uop_is_unique;\n uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_5_ldst <= io_enq_bits_uop_ldst;\n uops_5_lrs1 <= io_enq_bits_uop_lrs1;\n uops_5_lrs2 <= io_enq_bits_uop_lrs2;\n uops_5_lrs3 <= io_enq_bits_uop_lrs3;\n uops_5_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_5_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_5_fp_val <= io_enq_bits_uop_fp_val;\n uops_5_fp_single <= io_enq_bits_uop_fp_single;\n uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_5_br_mask <= do_enq & _GEN_90 ? _uops_br_mask_T_1 : ({8{~valids_5}} | ~io_brupdate_b1_resolve_mask) & uops_5_br_mask;\n if (_GEN_93) begin\n uops_6_uopc <= io_enq_bits_uop_uopc;\n uops_6_inst <= io_enq_bits_uop_inst;\n uops_6_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_6_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_6_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_6_iq_type <= io_enq_bits_uop_iq_type;\n uops_6_fu_code <= io_enq_bits_uop_fu_code;\n uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_6_iw_state <= io_enq_bits_uop_iw_state;\n uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_6_is_br <= io_enq_bits_uop_is_br;\n uops_6_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_6_is_jal <= io_enq_bits_uop_is_jal;\n uops_6_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_6_br_tag <= io_enq_bits_uop_br_tag;\n uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_6_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_6_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_6_taken <= io_enq_bits_uop_taken;\n uops_6_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_6_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_6_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_6_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_6_pdst <= io_enq_bits_uop_pdst;\n uops_6_prs1 <= io_enq_bits_uop_prs1;\n uops_6_prs2 <= io_enq_bits_uop_prs2;\n uops_6_prs3 <= io_enq_bits_uop_prs3;\n uops_6_ppred <= io_enq_bits_uop_ppred;\n uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_6_exception <= io_enq_bits_uop_exception;\n uops_6_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_6_bypassable <= io_enq_bits_uop_bypassable;\n uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_6_mem_size <= io_enq_bits_uop_mem_size;\n uops_6_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_6_is_fence <= io_enq_bits_uop_is_fence;\n uops_6_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_6_is_amo <= io_enq_bits_uop_is_amo;\n uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_6_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_6_is_unique <= io_enq_bits_uop_is_unique;\n uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_6_ldst <= io_enq_bits_uop_ldst;\n uops_6_lrs1 <= io_enq_bits_uop_lrs1;\n uops_6_lrs2 <= io_enq_bits_uop_lrs2;\n uops_6_lrs3 <= io_enq_bits_uop_lrs3;\n uops_6_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_6_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_6_fp_val <= io_enq_bits_uop_fp_val;\n uops_6_fp_single <= io_enq_bits_uop_fp_single;\n uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_6_br_mask <= do_enq & _GEN_92 ? _uops_br_mask_T_1 : ({8{~valids_6}} | ~io_brupdate_b1_resolve_mask) & uops_6_br_mask;\n if (_GEN_95) begin\n uops_7_uopc <= io_enq_bits_uop_uopc;\n uops_7_inst <= io_enq_bits_uop_inst;\n uops_7_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_7_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_7_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_7_iq_type <= io_enq_bits_uop_iq_type;\n uops_7_fu_code <= io_enq_bits_uop_fu_code;\n uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_7_iw_state <= io_enq_bits_uop_iw_state;\n uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_7_is_br <= io_enq_bits_uop_is_br;\n uops_7_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_7_is_jal <= io_enq_bits_uop_is_jal;\n uops_7_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_7_br_tag <= io_enq_bits_uop_br_tag;\n uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_7_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_7_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_7_taken <= io_enq_bits_uop_taken;\n uops_7_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_7_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_7_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_7_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_7_pdst <= io_enq_bits_uop_pdst;\n uops_7_prs1 <= io_enq_bits_uop_prs1;\n uops_7_prs2 <= io_enq_bits_uop_prs2;\n uops_7_prs3 <= io_enq_bits_uop_prs3;\n uops_7_ppred <= io_enq_bits_uop_ppred;\n uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_7_exception <= io_enq_bits_uop_exception;\n uops_7_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_7_bypassable <= io_enq_bits_uop_bypassable;\n uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_7_mem_size <= io_enq_bits_uop_mem_size;\n uops_7_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_7_is_fence <= io_enq_bits_uop_is_fence;\n uops_7_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_7_is_amo <= io_enq_bits_uop_is_amo;\n uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_7_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_7_is_unique <= io_enq_bits_uop_is_unique;\n uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_7_ldst <= io_enq_bits_uop_ldst;\n uops_7_lrs1 <= io_enq_bits_uop_lrs1;\n uops_7_lrs2 <= io_enq_bits_uop_lrs2;\n uops_7_lrs3 <= io_enq_bits_uop_lrs3;\n uops_7_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_7_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_7_fp_val <= io_enq_bits_uop_fp_val;\n uops_7_fp_single <= io_enq_bits_uop_fp_single;\n uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_7_br_mask <= do_enq & _GEN_94 ? _uops_br_mask_T_1 : ({8{~valids_7}} | ~io_brupdate_b1_resolve_mask) & uops_7_br_mask;\n if (_GEN_97) begin\n uops_8_uopc <= io_enq_bits_uop_uopc;\n uops_8_inst <= io_enq_bits_uop_inst;\n uops_8_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_8_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_8_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_8_iq_type <= io_enq_bits_uop_iq_type;\n uops_8_fu_code <= io_enq_bits_uop_fu_code;\n uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_8_iw_state <= io_enq_bits_uop_iw_state;\n uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_8_is_br <= io_enq_bits_uop_is_br;\n uops_8_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_8_is_jal <= io_enq_bits_uop_is_jal;\n uops_8_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_8_br_tag <= io_enq_bits_uop_br_tag;\n uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_8_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_8_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_8_taken <= io_enq_bits_uop_taken;\n uops_8_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_8_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_8_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_8_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_8_pdst <= io_enq_bits_uop_pdst;\n uops_8_prs1 <= io_enq_bits_uop_prs1;\n uops_8_prs2 <= io_enq_bits_uop_prs2;\n uops_8_prs3 <= io_enq_bits_uop_prs3;\n uops_8_ppred <= io_enq_bits_uop_ppred;\n uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_8_exception <= io_enq_bits_uop_exception;\n uops_8_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_8_bypassable <= io_enq_bits_uop_bypassable;\n uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_8_mem_size <= io_enq_bits_uop_mem_size;\n uops_8_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_8_is_fence <= io_enq_bits_uop_is_fence;\n uops_8_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_8_is_amo <= io_enq_bits_uop_is_amo;\n uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_8_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_8_is_unique <= io_enq_bits_uop_is_unique;\n uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_8_ldst <= io_enq_bits_uop_ldst;\n uops_8_lrs1 <= io_enq_bits_uop_lrs1;\n uops_8_lrs2 <= io_enq_bits_uop_lrs2;\n uops_8_lrs3 <= io_enq_bits_uop_lrs3;\n uops_8_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_8_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_8_fp_val <= io_enq_bits_uop_fp_val;\n uops_8_fp_single <= io_enq_bits_uop_fp_single;\n uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_8_br_mask <= do_enq & _GEN_96 ? _uops_br_mask_T_1 : ({8{~valids_8}} | ~io_brupdate_b1_resolve_mask) & uops_8_br_mask;\n if (_GEN_99) begin\n uops_9_uopc <= io_enq_bits_uop_uopc;\n uops_9_inst <= io_enq_bits_uop_inst;\n uops_9_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_9_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_9_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_9_iq_type <= io_enq_bits_uop_iq_type;\n uops_9_fu_code <= io_enq_bits_uop_fu_code;\n uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_9_iw_state <= io_enq_bits_uop_iw_state;\n uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_9_is_br <= io_enq_bits_uop_is_br;\n uops_9_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_9_is_jal <= io_enq_bits_uop_is_jal;\n uops_9_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_9_br_tag <= io_enq_bits_uop_br_tag;\n uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_9_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_9_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_9_taken <= io_enq_bits_uop_taken;\n uops_9_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_9_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_9_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_9_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_9_pdst <= io_enq_bits_uop_pdst;\n uops_9_prs1 <= io_enq_bits_uop_prs1;\n uops_9_prs2 <= io_enq_bits_uop_prs2;\n uops_9_prs3 <= io_enq_bits_uop_prs3;\n uops_9_ppred <= io_enq_bits_uop_ppred;\n uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_9_exception <= io_enq_bits_uop_exception;\n uops_9_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_9_bypassable <= io_enq_bits_uop_bypassable;\n uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_9_mem_size <= io_enq_bits_uop_mem_size;\n uops_9_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_9_is_fence <= io_enq_bits_uop_is_fence;\n uops_9_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_9_is_amo <= io_enq_bits_uop_is_amo;\n uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_9_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_9_is_unique <= io_enq_bits_uop_is_unique;\n uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_9_ldst <= io_enq_bits_uop_ldst;\n uops_9_lrs1 <= io_enq_bits_uop_lrs1;\n uops_9_lrs2 <= io_enq_bits_uop_lrs2;\n uops_9_lrs3 <= io_enq_bits_uop_lrs3;\n uops_9_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_9_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_9_fp_val <= io_enq_bits_uop_fp_val;\n uops_9_fp_single <= io_enq_bits_uop_fp_single;\n uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_9_br_mask <= do_enq & _GEN_98 ? _uops_br_mask_T_1 : ({8{~valids_9}} | ~io_brupdate_b1_resolve_mask) & uops_9_br_mask;\n if (_GEN_101) begin\n uops_10_uopc <= io_enq_bits_uop_uopc;\n uops_10_inst <= io_enq_bits_uop_inst;\n uops_10_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_10_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_10_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_10_iq_type <= io_enq_bits_uop_iq_type;\n uops_10_fu_code <= io_enq_bits_uop_fu_code;\n uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_10_iw_state <= io_enq_bits_uop_iw_state;\n uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_10_is_br <= io_enq_bits_uop_is_br;\n uops_10_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_10_is_jal <= io_enq_bits_uop_is_jal;\n uops_10_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_10_br_tag <= io_enq_bits_uop_br_tag;\n uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_10_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_10_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_10_taken <= io_enq_bits_uop_taken;\n uops_10_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_10_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_10_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_10_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_10_pdst <= io_enq_bits_uop_pdst;\n uops_10_prs1 <= io_enq_bits_uop_prs1;\n uops_10_prs2 <= io_enq_bits_uop_prs2;\n uops_10_prs3 <= io_enq_bits_uop_prs3;\n uops_10_ppred <= io_enq_bits_uop_ppred;\n uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_10_exception <= io_enq_bits_uop_exception;\n uops_10_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_10_bypassable <= io_enq_bits_uop_bypassable;\n uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_10_mem_size <= io_enq_bits_uop_mem_size;\n uops_10_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_10_is_fence <= io_enq_bits_uop_is_fence;\n uops_10_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_10_is_amo <= io_enq_bits_uop_is_amo;\n uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_10_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_10_is_unique <= io_enq_bits_uop_is_unique;\n uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_10_ldst <= io_enq_bits_uop_ldst;\n uops_10_lrs1 <= io_enq_bits_uop_lrs1;\n uops_10_lrs2 <= io_enq_bits_uop_lrs2;\n uops_10_lrs3 <= io_enq_bits_uop_lrs3;\n uops_10_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_10_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_10_fp_val <= io_enq_bits_uop_fp_val;\n uops_10_fp_single <= io_enq_bits_uop_fp_single;\n uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_10_br_mask <= do_enq & _GEN_100 ? _uops_br_mask_T_1 : ({8{~valids_10}} | ~io_brupdate_b1_resolve_mask) & uops_10_br_mask;\n if (_GEN_103) begin\n uops_11_uopc <= io_enq_bits_uop_uopc;\n uops_11_inst <= io_enq_bits_uop_inst;\n uops_11_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_11_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_11_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_11_iq_type <= io_enq_bits_uop_iq_type;\n uops_11_fu_code <= io_enq_bits_uop_fu_code;\n uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_11_iw_state <= io_enq_bits_uop_iw_state;\n uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_11_is_br <= io_enq_bits_uop_is_br;\n uops_11_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_11_is_jal <= io_enq_bits_uop_is_jal;\n uops_11_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_11_br_tag <= io_enq_bits_uop_br_tag;\n uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_11_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_11_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_11_taken <= io_enq_bits_uop_taken;\n uops_11_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_11_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_11_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_11_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_11_pdst <= io_enq_bits_uop_pdst;\n uops_11_prs1 <= io_enq_bits_uop_prs1;\n uops_11_prs2 <= io_enq_bits_uop_prs2;\n uops_11_prs3 <= io_enq_bits_uop_prs3;\n uops_11_ppred <= io_enq_bits_uop_ppred;\n uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_11_exception <= io_enq_bits_uop_exception;\n uops_11_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_11_bypassable <= io_enq_bits_uop_bypassable;\n uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_11_mem_size <= io_enq_bits_uop_mem_size;\n uops_11_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_11_is_fence <= io_enq_bits_uop_is_fence;\n uops_11_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_11_is_amo <= io_enq_bits_uop_is_amo;\n uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_11_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_11_is_unique <= io_enq_bits_uop_is_unique;\n uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_11_ldst <= io_enq_bits_uop_ldst;\n uops_11_lrs1 <= io_enq_bits_uop_lrs1;\n uops_11_lrs2 <= io_enq_bits_uop_lrs2;\n uops_11_lrs3 <= io_enq_bits_uop_lrs3;\n uops_11_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_11_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_11_fp_val <= io_enq_bits_uop_fp_val;\n uops_11_fp_single <= io_enq_bits_uop_fp_single;\n uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_11_br_mask <= do_enq & _GEN_102 ? _uops_br_mask_T_1 : ({8{~valids_11}} | ~io_brupdate_b1_resolve_mask) & uops_11_br_mask;\n if (_GEN_105) begin\n uops_12_uopc <= io_enq_bits_uop_uopc;\n uops_12_inst <= io_enq_bits_uop_inst;\n uops_12_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_12_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_12_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_12_iq_type <= io_enq_bits_uop_iq_type;\n uops_12_fu_code <= io_enq_bits_uop_fu_code;\n uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_12_iw_state <= io_enq_bits_uop_iw_state;\n uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_12_is_br <= io_enq_bits_uop_is_br;\n uops_12_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_12_is_jal <= io_enq_bits_uop_is_jal;\n uops_12_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_12_br_tag <= io_enq_bits_uop_br_tag;\n uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_12_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_12_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_12_taken <= io_enq_bits_uop_taken;\n uops_12_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_12_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_12_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_12_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_12_pdst <= io_enq_bits_uop_pdst;\n uops_12_prs1 <= io_enq_bits_uop_prs1;\n uops_12_prs2 <= io_enq_bits_uop_prs2;\n uops_12_prs3 <= io_enq_bits_uop_prs3;\n uops_12_ppred <= io_enq_bits_uop_ppred;\n uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_12_exception <= io_enq_bits_uop_exception;\n uops_12_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_12_bypassable <= io_enq_bits_uop_bypassable;\n uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_12_mem_size <= io_enq_bits_uop_mem_size;\n uops_12_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_12_is_fence <= io_enq_bits_uop_is_fence;\n uops_12_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_12_is_amo <= io_enq_bits_uop_is_amo;\n uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_12_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_12_is_unique <= io_enq_bits_uop_is_unique;\n uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_12_ldst <= io_enq_bits_uop_ldst;\n uops_12_lrs1 <= io_enq_bits_uop_lrs1;\n uops_12_lrs2 <= io_enq_bits_uop_lrs2;\n uops_12_lrs3 <= io_enq_bits_uop_lrs3;\n uops_12_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_12_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_12_fp_val <= io_enq_bits_uop_fp_val;\n uops_12_fp_single <= io_enq_bits_uop_fp_single;\n uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_12_br_mask <= do_enq & _GEN_104 ? _uops_br_mask_T_1 : ({8{~valids_12}} | ~io_brupdate_b1_resolve_mask) & uops_12_br_mask;\n if (_GEN_107) begin\n uops_13_uopc <= io_enq_bits_uop_uopc;\n uops_13_inst <= io_enq_bits_uop_inst;\n uops_13_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_13_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_13_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_13_iq_type <= io_enq_bits_uop_iq_type;\n uops_13_fu_code <= io_enq_bits_uop_fu_code;\n uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_13_iw_state <= io_enq_bits_uop_iw_state;\n uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_13_is_br <= io_enq_bits_uop_is_br;\n uops_13_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_13_is_jal <= io_enq_bits_uop_is_jal;\n uops_13_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_13_br_tag <= io_enq_bits_uop_br_tag;\n uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_13_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_13_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_13_taken <= io_enq_bits_uop_taken;\n uops_13_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_13_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_13_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_13_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_13_pdst <= io_enq_bits_uop_pdst;\n uops_13_prs1 <= io_enq_bits_uop_prs1;\n uops_13_prs2 <= io_enq_bits_uop_prs2;\n uops_13_prs3 <= io_enq_bits_uop_prs3;\n uops_13_ppred <= io_enq_bits_uop_ppred;\n uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_13_exception <= io_enq_bits_uop_exception;\n uops_13_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_13_bypassable <= io_enq_bits_uop_bypassable;\n uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_13_mem_size <= io_enq_bits_uop_mem_size;\n uops_13_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_13_is_fence <= io_enq_bits_uop_is_fence;\n uops_13_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_13_is_amo <= io_enq_bits_uop_is_amo;\n uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_13_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_13_is_unique <= io_enq_bits_uop_is_unique;\n uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_13_ldst <= io_enq_bits_uop_ldst;\n uops_13_lrs1 <= io_enq_bits_uop_lrs1;\n uops_13_lrs2 <= io_enq_bits_uop_lrs2;\n uops_13_lrs3 <= io_enq_bits_uop_lrs3;\n uops_13_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_13_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_13_fp_val <= io_enq_bits_uop_fp_val;\n uops_13_fp_single <= io_enq_bits_uop_fp_single;\n uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_13_br_mask <= do_enq & _GEN_106 ? _uops_br_mask_T_1 : ({8{~valids_13}} | ~io_brupdate_b1_resolve_mask) & uops_13_br_mask;\n if (_GEN_109) begin\n uops_14_uopc <= io_enq_bits_uop_uopc;\n uops_14_inst <= io_enq_bits_uop_inst;\n uops_14_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_14_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_14_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_14_iq_type <= io_enq_bits_uop_iq_type;\n uops_14_fu_code <= io_enq_bits_uop_fu_code;\n uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_14_iw_state <= io_enq_bits_uop_iw_state;\n uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_14_is_br <= io_enq_bits_uop_is_br;\n uops_14_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_14_is_jal <= io_enq_bits_uop_is_jal;\n uops_14_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_14_br_tag <= io_enq_bits_uop_br_tag;\n uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_14_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_14_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_14_taken <= io_enq_bits_uop_taken;\n uops_14_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_14_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_14_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_14_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_14_pdst <= io_enq_bits_uop_pdst;\n uops_14_prs1 <= io_enq_bits_uop_prs1;\n uops_14_prs2 <= io_enq_bits_uop_prs2;\n uops_14_prs3 <= io_enq_bits_uop_prs3;\n uops_14_ppred <= io_enq_bits_uop_ppred;\n uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_14_exception <= io_enq_bits_uop_exception;\n uops_14_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_14_bypassable <= io_enq_bits_uop_bypassable;\n uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_14_mem_size <= io_enq_bits_uop_mem_size;\n uops_14_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_14_is_fence <= io_enq_bits_uop_is_fence;\n uops_14_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_14_is_amo <= io_enq_bits_uop_is_amo;\n uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_14_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_14_is_unique <= io_enq_bits_uop_is_unique;\n uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_14_ldst <= io_enq_bits_uop_ldst;\n uops_14_lrs1 <= io_enq_bits_uop_lrs1;\n uops_14_lrs2 <= io_enq_bits_uop_lrs2;\n uops_14_lrs3 <= io_enq_bits_uop_lrs3;\n uops_14_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_14_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_14_fp_val <= io_enq_bits_uop_fp_val;\n uops_14_fp_single <= io_enq_bits_uop_fp_single;\n uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_14_br_mask <= do_enq & _GEN_108 ? _uops_br_mask_T_1 : ({8{~valids_14}} | ~io_brupdate_b1_resolve_mask) & uops_14_br_mask;\n if (_GEN_110) begin\n uops_15_uopc <= io_enq_bits_uop_uopc;\n uops_15_inst <= io_enq_bits_uop_inst;\n uops_15_debug_inst <= io_enq_bits_uop_debug_inst;\n uops_15_is_rvc <= io_enq_bits_uop_is_rvc;\n uops_15_debug_pc <= io_enq_bits_uop_debug_pc;\n uops_15_iq_type <= io_enq_bits_uop_iq_type;\n uops_15_fu_code <= io_enq_bits_uop_fu_code;\n uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type;\n uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel;\n uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel;\n uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel;\n uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn;\n uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw;\n uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd;\n uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load;\n uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta;\n uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std;\n uops_15_iw_state <= io_enq_bits_uop_iw_state;\n uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned;\n uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned;\n uops_15_is_br <= io_enq_bits_uop_is_br;\n uops_15_is_jalr <= io_enq_bits_uop_is_jalr;\n uops_15_is_jal <= io_enq_bits_uop_is_jal;\n uops_15_is_sfb <= io_enq_bits_uop_is_sfb;\n uops_15_br_tag <= io_enq_bits_uop_br_tag;\n uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx;\n uops_15_edge_inst <= io_enq_bits_uop_edge_inst;\n uops_15_pc_lob <= io_enq_bits_uop_pc_lob;\n uops_15_taken <= io_enq_bits_uop_taken;\n uops_15_imm_packed <= io_enq_bits_uop_imm_packed;\n uops_15_csr_addr <= io_enq_bits_uop_csr_addr;\n uops_15_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_15_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx;\n uops_15_pdst <= io_enq_bits_uop_pdst;\n uops_15_prs1 <= io_enq_bits_uop_prs1;\n uops_15_prs2 <= io_enq_bits_uop_prs2;\n uops_15_prs3 <= io_enq_bits_uop_prs3;\n uops_15_ppred <= io_enq_bits_uop_ppred;\n uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy;\n uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy;\n uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy;\n uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy;\n uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst;\n uops_15_exception <= io_enq_bits_uop_exception;\n uops_15_exc_cause <= io_enq_bits_uop_exc_cause;\n uops_15_bypassable <= io_enq_bits_uop_bypassable;\n uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd;\n uops_15_mem_size <= io_enq_bits_uop_mem_size;\n uops_15_mem_signed <= io_enq_bits_uop_mem_signed;\n uops_15_is_fence <= io_enq_bits_uop_is_fence;\n uops_15_is_fencei <= io_enq_bits_uop_is_fencei;\n uops_15_is_amo <= io_enq_bits_uop_is_amo;\n uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_15_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc;\n uops_15_is_unique <= io_enq_bits_uop_is_unique;\n uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit;\n uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1;\n uops_15_ldst <= io_enq_bits_uop_ldst;\n uops_15_lrs1 <= io_enq_bits_uop_lrs1;\n uops_15_lrs2 <= io_enq_bits_uop_lrs2;\n uops_15_lrs3 <= io_enq_bits_uop_lrs3;\n uops_15_ldst_val <= io_enq_bits_uop_ldst_val;\n uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype;\n uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype;\n uops_15_frs3_en <= io_enq_bits_uop_frs3_en;\n uops_15_fp_val <= io_enq_bits_uop_fp_val;\n uops_15_fp_single <= io_enq_bits_uop_fp_single;\n uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if;\n uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if;\n uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if;\n uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if;\n uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if;\n uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc;\n uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc;\n end\n uops_15_br_mask <= do_enq & (&enq_ptr_value) ? _uops_br_mask_T_1 : ({8{~valids_15}} | ~io_brupdate_b1_resolve_mask) & uops_15_br_mask;\n end\n ram_16x46 ram_ext (\n .R0_addr (deq_ptr_value),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_ram_ext_R0_data),\n .W0_addr (enq_ptr_value),\n .W0_en (do_enq),\n .W0_clk (clock),\n .W0_data ({io_enq_bits_sdq_id, io_enq_bits_is_hella, io_enq_bits_addr})\n );\n assign io_enq_ready = ~full;\n assign io_deq_valid = ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~(io_flush & out_uop_uses_ldq);\n assign io_deq_bits_uop_uopc = _GEN_1[deq_ptr_value];\n assign io_deq_bits_uop_inst = _GEN_2[deq_ptr_value];\n assign io_deq_bits_uop_debug_inst = _GEN_3[deq_ptr_value];\n assign io_deq_bits_uop_is_rvc = _GEN_4[deq_ptr_value];\n assign io_deq_bits_uop_debug_pc = _GEN_5[deq_ptr_value];\n assign io_deq_bits_uop_iq_type = _GEN_6[deq_ptr_value];\n assign io_deq_bits_uop_fu_code = _GEN_7[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_br_type = _GEN_8[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_op1_sel = _GEN_9[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_op2_sel = _GEN_10[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_imm_sel = _GEN_11[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_op_fcn = _GEN_12[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_fcn_dw = _GEN_13[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_csr_cmd = _GEN_14[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_is_load = _GEN_15[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_is_sta = _GEN_16[deq_ptr_value];\n assign io_deq_bits_uop_ctrl_is_std = _GEN_17[deq_ptr_value];\n assign io_deq_bits_uop_iw_state = _GEN_18[deq_ptr_value];\n assign io_deq_bits_uop_iw_p1_poisoned = _GEN_19[deq_ptr_value];\n assign io_deq_bits_uop_iw_p2_poisoned = _GEN_20[deq_ptr_value];\n assign io_deq_bits_uop_is_br = _GEN_21[deq_ptr_value];\n assign io_deq_bits_uop_is_jalr = _GEN_22[deq_ptr_value];\n assign io_deq_bits_uop_is_jal = _GEN_23[deq_ptr_value];\n assign io_deq_bits_uop_is_sfb = _GEN_24[deq_ptr_value];\n assign io_deq_bits_uop_br_mask = out_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_deq_bits_uop_br_tag = _GEN_26[deq_ptr_value];\n assign io_deq_bits_uop_ftq_idx = _GEN_27[deq_ptr_value];\n assign io_deq_bits_uop_edge_inst = _GEN_28[deq_ptr_value];\n assign io_deq_bits_uop_pc_lob = _GEN_29[deq_ptr_value];\n assign io_deq_bits_uop_taken = _GEN_30[deq_ptr_value];\n assign io_deq_bits_uop_imm_packed = _GEN_31[deq_ptr_value];\n assign io_deq_bits_uop_csr_addr = _GEN_32[deq_ptr_value];\n assign io_deq_bits_uop_rob_idx = _GEN_33[deq_ptr_value];\n assign io_deq_bits_uop_ldq_idx = _GEN_34[deq_ptr_value];\n assign io_deq_bits_uop_stq_idx = _GEN_35[deq_ptr_value];\n assign io_deq_bits_uop_rxq_idx = _GEN_36[deq_ptr_value];\n assign io_deq_bits_uop_pdst = _GEN_37[deq_ptr_value];\n assign io_deq_bits_uop_prs1 = _GEN_38[deq_ptr_value];\n assign io_deq_bits_uop_prs2 = _GEN_39[deq_ptr_value];\n assign io_deq_bits_uop_prs3 = _GEN_40[deq_ptr_value];\n assign io_deq_bits_uop_ppred = _GEN_41[deq_ptr_value];\n assign io_deq_bits_uop_prs1_busy = _GEN_42[deq_ptr_value];\n assign io_deq_bits_uop_prs2_busy = _GEN_43[deq_ptr_value];\n assign io_deq_bits_uop_prs3_busy = _GEN_44[deq_ptr_value];\n assign io_deq_bits_uop_ppred_busy = _GEN_45[deq_ptr_value];\n assign io_deq_bits_uop_stale_pdst = _GEN_46[deq_ptr_value];\n assign io_deq_bits_uop_exception = _GEN_47[deq_ptr_value];\n assign io_deq_bits_uop_exc_cause = _GEN_48[deq_ptr_value];\n assign io_deq_bits_uop_bypassable = _GEN_49[deq_ptr_value];\n assign io_deq_bits_uop_mem_cmd = _GEN_50[deq_ptr_value];\n assign io_deq_bits_uop_mem_size = _GEN_51[deq_ptr_value];\n assign io_deq_bits_uop_mem_signed = _GEN_52[deq_ptr_value];\n assign io_deq_bits_uop_is_fence = _GEN_53[deq_ptr_value];\n assign io_deq_bits_uop_is_fencei = _GEN_54[deq_ptr_value];\n assign io_deq_bits_uop_is_amo = _GEN_55[deq_ptr_value];\n assign io_deq_bits_uop_uses_ldq = out_uop_uses_ldq;\n assign io_deq_bits_uop_uses_stq = _GEN_57[deq_ptr_value];\n assign io_deq_bits_uop_is_sys_pc2epc = _GEN_58[deq_ptr_value];\n assign io_deq_bits_uop_is_unique = _GEN_59[deq_ptr_value];\n assign io_deq_bits_uop_flush_on_commit = _GEN_60[deq_ptr_value];\n assign io_deq_bits_uop_ldst_is_rs1 = _GEN_61[deq_ptr_value];\n assign io_deq_bits_uop_ldst = _GEN_62[deq_ptr_value];\n assign io_deq_bits_uop_lrs1 = _GEN_63[deq_ptr_value];\n assign io_deq_bits_uop_lrs2 = _GEN_64[deq_ptr_value];\n assign io_deq_bits_uop_lrs3 = _GEN_65[deq_ptr_value];\n assign io_deq_bits_uop_ldst_val = _GEN_66[deq_ptr_value];\n assign io_deq_bits_uop_dst_rtype = _GEN_67[deq_ptr_value];\n assign io_deq_bits_uop_lrs1_rtype = _GEN_68[deq_ptr_value];\n assign io_deq_bits_uop_lrs2_rtype = _GEN_69[deq_ptr_value];\n assign io_deq_bits_uop_frs3_en = _GEN_70[deq_ptr_value];\n assign io_deq_bits_uop_fp_val = _GEN_71[deq_ptr_value];\n assign io_deq_bits_uop_fp_single = _GEN_72[deq_ptr_value];\n assign io_deq_bits_uop_xcpt_pf_if = _GEN_73[deq_ptr_value];\n assign io_deq_bits_uop_xcpt_ae_if = _GEN_74[deq_ptr_value];\n assign io_deq_bits_uop_xcpt_ma_if = _GEN_75[deq_ptr_value];\n assign io_deq_bits_uop_bp_debug_if = _GEN_76[deq_ptr_value];\n assign io_deq_bits_uop_bp_xcpt_if = _GEN_77[deq_ptr_value];\n assign io_deq_bits_uop_debug_fsrc = _GEN_78[deq_ptr_value];\n assign io_deq_bits_uop_debug_tsrc = _GEN_79[deq_ptr_value];\n assign io_deq_bits_addr = _ram_ext_R0_data[39:0];\n assign io_deq_bits_is_hella = _ram_ext_R0_data[40];\n assign io_deq_bits_sdq_id = _ram_ext_R0_data[45:41];\n assign io_empty = io_empty_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_2(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.reflect.DataMirror\nimport chisel3.internal.firrtl.KnownWidth\nimport chisel3.util.{Cat, Valid}\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\n/** Base JTAG shifter IO, viewed from input to shift register chain.\n * Can be chained together.\n */\nclass ShifterIO extends Bundle {\n val shift = Bool() // advance the scan chain on clock high\n val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB\n val capture = Bool() // high in the CaptureIR/DR state when this chain is selected\n val update = Bool() // high in the UpdateIR/DR state when this chain is selected\n\n /** Sets a output shifter IO's control signals from a input shifter IO's control signals.\n */\n def chainControlFrom(in: ShifterIO): Unit = {\n shift := in.shift\n capture := in.capture\n update := in.update\n }\n}\n\ntrait ChainIO extends Bundle {\n val chainIn = Input(new ShifterIO)\n val chainOut = Output(new ShifterIO)\n}\n\nclass Capture[+T <: Data](gen: T) extends Bundle {\n val bits = Input(gen) // data to capture, should be always valid\n val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge\n}\n\nobject Capture {\n def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)\n}\n\n/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain\n * IO.\n */\ntrait Chain extends Module {\n val io: ChainIO\n}\n\n/** One-element shift register, data register for bypass mode.\n *\n * Implements Clause 10.\n */\nclass JtagBypassChain(implicit val p: Parameters) extends Chain {\n class ModIO extends ChainIO\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val reg = Reg(Bool()) // 10.1.1a single shift register stage\n\n io.chainOut.data := reg\n\n property.cover(io.chainIn.capture, \"bypass_chain_capture\", \"JTAG; bypass_chain_capture; This Bypass Chain captured data\")\n\n when (io.chainIn.capture) {\n reg := false.B // 10.1.1b capture logic 0 on TCK rising\n } .elsewhen (io.chainIn.shift) {\n reg := io.chainIn.data\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject JtagBypassChain {\n def apply()(implicit p: Parameters) = new JtagBypassChain\n}\n\n/** Simple shift register with parallel capture only, for read-only data registers.\n *\n * Number of stages is the number of bits in gen, which must have a known width.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureChain_${gen.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(gen)\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val n = DataMirror.widthOf(gen) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $gen\"); -1 // TODO: remove -1 type hack\n }\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG; chain_capture; This Chain captured data\")\n \n when (io.chainIn.capture) {\n (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))\n io.capture.capture := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n } .otherwise {\n io.capture.capture := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureChain {\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)\n}\n\n/** Simple shift register with parallel capture and update. Useful for general instruction and data\n * scan registers.\n *\n * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have\n * known widths. If there is a width mismatch, the unused most significant bits will be zero.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(genCapture)\n val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val captureWidth = DataMirror.widthOf(genCapture) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genCapture\"); -1 // TODO: remove -1 type hack\n }\n val updateWidth = DataMirror.widthOf(genUpdate) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genUpdate\"); -1 // TODO: remove -1 type hack\n }\n val n = math.max(captureWidth, updateWidth)\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n val updateBits = Cat(regs.reverse)(updateWidth-1, 0)\n io.update.bits := updateBits.asTypeOf(io.update.bits)\n\n val captureBits = io.capture.bits.asUInt\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG;chain_capture; This Chain captured data\")\n property.cover(io.chainIn.capture, \"chain_update\", \"JTAG;chain_update; This Chain updated data\")\n\n when (io.chainIn.capture) {\n (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))\n (captureWidth until n) map (x => regs(x) := 0.U)\n io.capture.capture := true.B\n io.update.valid := false.B\n } .elsewhen (io.chainIn.update) {\n io.capture.capture := false.B\n io.update.valid := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n io.update.valid := false.B\n } .otherwise {\n io.capture.capture := false.B\n io.update.valid := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureUpdateChain {\n /** Capture-update chain with matching capture and update types.\n */\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)\n def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =\n new CaptureUpdateChain(genCapture, genUpdate)\n}", + "response": "module CaptureUpdateChain_DMIAccessCapture_To_DMIAccessUpdate(\n input clock,\n input reset,\n input io_chainIn_shift,\n input io_chainIn_data,\n input io_chainIn_capture,\n input io_chainIn_update,\n output io_chainOut_data,\n input [6:0] io_capture_bits_addr,\n input [31:0] io_capture_bits_data,\n input [1:0] io_capture_bits_resp,\n output io_capture_capture,\n output io_update_valid,\n output [6:0] io_update_bits_addr,\n output [31:0] io_update_bits_data,\n output [1:0] io_update_bits_op\n);\n\n reg regs_0;\n reg regs_1;\n reg regs_2;\n reg regs_3;\n reg regs_4;\n reg regs_5;\n reg regs_6;\n reg regs_7;\n reg regs_8;\n reg regs_9;\n reg regs_10;\n reg regs_11;\n reg regs_12;\n reg regs_13;\n reg regs_14;\n reg regs_15;\n reg regs_16;\n reg regs_17;\n reg regs_18;\n reg regs_19;\n reg regs_20;\n reg regs_21;\n reg regs_22;\n reg regs_23;\n reg regs_24;\n reg regs_25;\n reg regs_26;\n reg regs_27;\n reg regs_28;\n reg regs_29;\n reg regs_30;\n reg regs_31;\n reg regs_32;\n reg regs_33;\n reg regs_34;\n reg regs_35;\n reg regs_36;\n reg regs_37;\n reg regs_38;\n reg regs_39;\n reg regs_40;\n always @(posedge clock) begin\n if (io_chainIn_capture) begin\n regs_0 <= io_capture_bits_resp[0];\n regs_1 <= io_capture_bits_resp[1];\n regs_2 <= io_capture_bits_data[0];\n regs_3 <= io_capture_bits_data[1];\n regs_4 <= io_capture_bits_data[2];\n regs_5 <= io_capture_bits_data[3];\n regs_6 <= io_capture_bits_data[4];\n regs_7 <= io_capture_bits_data[5];\n regs_8 <= io_capture_bits_data[6];\n regs_9 <= io_capture_bits_data[7];\n regs_10 <= io_capture_bits_data[8];\n regs_11 <= io_capture_bits_data[9];\n regs_12 <= io_capture_bits_data[10];\n regs_13 <= io_capture_bits_data[11];\n regs_14 <= io_capture_bits_data[12];\n regs_15 <= io_capture_bits_data[13];\n regs_16 <= io_capture_bits_data[14];\n regs_17 <= io_capture_bits_data[15];\n regs_18 <= io_capture_bits_data[16];\n regs_19 <= io_capture_bits_data[17];\n regs_20 <= io_capture_bits_data[18];\n regs_21 <= io_capture_bits_data[19];\n regs_22 <= io_capture_bits_data[20];\n regs_23 <= io_capture_bits_data[21];\n regs_24 <= io_capture_bits_data[22];\n regs_25 <= io_capture_bits_data[23];\n regs_26 <= io_capture_bits_data[24];\n regs_27 <= io_capture_bits_data[25];\n regs_28 <= io_capture_bits_data[26];\n regs_29 <= io_capture_bits_data[27];\n regs_30 <= io_capture_bits_data[28];\n regs_31 <= io_capture_bits_data[29];\n regs_32 <= io_capture_bits_data[30];\n regs_33 <= io_capture_bits_data[31];\n regs_34 <= io_capture_bits_addr[0];\n regs_35 <= io_capture_bits_addr[1];\n regs_36 <= io_capture_bits_addr[2];\n regs_37 <= io_capture_bits_addr[3];\n regs_38 <= io_capture_bits_addr[4];\n regs_39 <= io_capture_bits_addr[5];\n regs_40 <= io_capture_bits_addr[6];\n end\n else if (io_chainIn_update | ~io_chainIn_shift) begin\n end\n else begin\n regs_0 <= regs_1;\n regs_1 <= regs_2;\n regs_2 <= regs_3;\n regs_3 <= regs_4;\n regs_4 <= regs_5;\n regs_5 <= regs_6;\n regs_6 <= regs_7;\n regs_7 <= regs_8;\n regs_8 <= regs_9;\n regs_9 <= regs_10;\n regs_10 <= regs_11;\n regs_11 <= regs_12;\n regs_12 <= regs_13;\n regs_13 <= regs_14;\n regs_14 <= regs_15;\n regs_15 <= regs_16;\n regs_16 <= regs_17;\n regs_17 <= regs_18;\n regs_18 <= regs_19;\n regs_19 <= regs_20;\n regs_20 <= regs_21;\n regs_21 <= regs_22;\n regs_22 <= regs_23;\n regs_23 <= regs_24;\n regs_24 <= regs_25;\n regs_25 <= regs_26;\n regs_26 <= regs_27;\n regs_27 <= regs_28;\n regs_28 <= regs_29;\n regs_29 <= regs_30;\n regs_30 <= regs_31;\n regs_31 <= regs_32;\n regs_32 <= regs_33;\n regs_33 <= regs_34;\n regs_34 <= regs_35;\n regs_35 <= regs_36;\n regs_36 <= regs_37;\n regs_37 <= regs_38;\n regs_38 <= regs_39;\n regs_39 <= regs_40;\n regs_40 <= io_chainIn_data;\n end\n end\n assign io_chainOut_data = regs_0;\n assign io_capture_capture = io_chainIn_capture;\n assign io_update_valid = ~io_chainIn_capture & io_chainIn_update;\n assign io_update_bits_addr = {regs_40, regs_39, regs_38, regs_37, regs_36, regs_35, regs_34};\n assign io_update_bits_data = {regs_33, regs_32, regs_31, regs_30, regs_29, regs_28, regs_27, regs_26, regs_25, regs_24, regs_23, regs_22, regs_21, regs_20, regs_19, regs_18, regs_17, regs_16, regs_15, regs_14, regs_13, regs_12, regs_11, regs_10, regs_9, regs_8, regs_7, regs_6, regs_5, regs_4, regs_3, regs_2};\n assign io_update_bits_op = {regs_1, regs_0};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Unit Decode\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Generate the functional unit control signals from the micro-op opcodes.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.uintToBitPat\nimport freechips.rocketchip.rocket.CSR\nimport freechips.rocketchip.rocket.ALU._\n\nimport boom.v3.common._\n\n/**\n * Control signal bundle for register renaming\n */\nclass RRdCtrlSigs(implicit p: Parameters) extends BoomBundle\n{\n val br_type = UInt(BR_N.getWidth.W)\n val use_alupipe = Bool()\n val use_muldivpipe = Bool()\n val use_mempipe = Bool()\n val op_fcn = Bits(SZ_ALU_FN.W)\n val fcn_dw = Bool()\n val op1_sel = UInt(OP1_X.getWidth.W)\n val op2_sel = UInt(OP2_X.getWidth.W)\n val imm_sel = UInt(IS_X.getWidth.W)\n val rf_wen = Bool()\n val csr_cmd = Bits(CSR.SZ.W)\n\n def decode(uopc: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(uopc, AluRRdDecode.default, table)\n val sigs = Seq(br_type, use_alupipe, use_muldivpipe, use_mempipe, op_fcn,\n fcn_dw, op1_sel, op2_sel, imm_sel, rf_wen, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n this\n }\n}\n\n/**\n * Default register read constants\n */\nabstract trait RRdDecodeConstants\n{\n val default: List[BitPat] =\n List[BitPat](BR_N , Y, N, N, FN_ADD , DW_X , OP1_X , OP2_X , IS_X, REN_0, CSR.N)\n val table: Array[(BitPat, List[BitPat])]\n}\n\n/**\n * ALU register read constants\n */\nobject AluRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLUI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMM , IS_U, REN_1, CSR.N),\n\n BitPat(uopADDI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopANDI) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopORI) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopXORI) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTI) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLTIU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLI) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAI) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLI) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADDIW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSLLIW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRAIW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n BitPat(uopSRLIW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_IMM , IS_I, REN_1, CSR.N),\n\n BitPat(uopADD) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLL) -> List(BR_N , Y, N, N, FN_SL , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUB) -> List(BR_N , Y, N, N, FN_SUB , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLT) -> List(BR_N , Y, N, N, FN_SLT , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLTU) -> List(BR_N , Y, N, N, FN_SLTU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopAND) -> List(BR_N , Y, N, N, FN_AND , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopOR) -> List(BR_N , Y, N, N, FN_OR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopXOR) -> List(BR_N , Y, N, N, FN_XOR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRA) -> List(BR_N , Y, N, N, FN_SRA , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRL) -> List(BR_N , Y, N, N, FN_SR , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopADDW) -> List(BR_N , Y, N, N, FN_ADD , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSUBW) -> List(BR_N , Y, N, N, FN_SUB , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSLLW) -> List(BR_N , Y, N, N, FN_SL , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRAW) -> List(BR_N , Y, N, N, FN_SRA , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopSRLW) -> List(BR_N , Y, N, N, FN_SR , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n\n BitPat(uopBEQ) -> List(BR_EQ ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBNE) -> List(BR_NE ,Y, N, N, FN_SUB , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGE) -> List(BR_GE ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBGEU) -> List(BR_GEU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLT) -> List(BR_LT ,Y, N, N, FN_SLT , DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N),\n BitPat(uopBLTU) -> List(BR_LTU,Y, N, N, FN_SLTU, DW_XPR, OP1_X , OP2_X , IS_B, REN_0, CSR.N))\n}\n\nobject JmpRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopJAL) -> List(BR_J , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_J, REN_1, CSR.N),\n BitPat(uopJALR) -> List(BR_JR, Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_NEXT, IS_I, REN_1, CSR.N),\n BitPat(uopAUIPC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_PC , OP2_IMM , IS_U, REN_1, CSR.N))\n}\n\n/**\n * Multiply divider register read constants\n */\nobject MulDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopMUL) -> List(BR_N , N, Y, N, FN_MUL, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULH) -> List(BR_N , N, Y, N, FN_MULH, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHU) -> List(BR_N , N, Y, N, FN_MULHU, DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULHSU)-> List(BR_N , N, Y, N, FN_MULHSU,DW_XPR,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n BitPat(uopMULW) -> List(BR_N , N, Y, N, FN_MUL, DW_32 ,OP1_RS1 , OP2_RS2 , IS_X, REN_1,CSR.N),\n\n BitPat(uopDIV) -> List(BR_N , N, Y, N, FN_DIV , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVU) -> List(BR_N , N, Y, N, FN_DIVU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREM) -> List(BR_N , N, Y, N, FN_REM , DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMU) -> List(BR_N , N, Y, N, FN_REMU, DW_XPR, OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVW) -> List(BR_N , N, Y, N, FN_DIV , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopDIVUW) -> List(BR_N , N, Y, N, FN_DIVU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMW) -> List(BR_N , N, Y, N, FN_REM , DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N),\n BitPat(uopREMUW) -> List(BR_N , N, Y, N, FN_REMU, DW_32 , OP1_RS1 , OP2_RS2 , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Memory unit register read constants\n */\nobject MemRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopLD) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_I, REN_0, CSR.N),\n BitPat(uopSTA) -> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_IMM , IS_S, REN_0, CSR.N),\n BitPat(uopSTD) -> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n BitPat(uopSFENCE)-> List(BR_N , N, N, Y, FN_X , DW_X , OP1_RS1 , OP2_RS2 , IS_X, REN_0, CSR.N),\n\n BitPat(uopAMO_AG)-> List(BR_N , N, N, Y, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_X, REN_0, CSR.N))\n}\n\n/**\n * CSR register read constants\n */\nobject CsrRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopCSRRW) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRS) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRC) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_RS1 , OP2_ZERO, IS_I, REN_1, CSR.C),\n\n BitPat(uopCSRRWI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.W),\n BitPat(uopCSRRSI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.S),\n BitPat(uopCSRRCI)-> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_1, CSR.C),\n\n BitPat(uopWFI) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I),\n BitPat(uopERET) -> List(BR_N , Y, N, N, FN_ADD , DW_XPR, OP1_ZERO, OP2_IMMC, IS_I, REN_0, CSR.I))\n}\n\n/**\n * FPU register read constants\n */\nobject FpuRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFCLASS_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCLASS_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n// BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_W)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_X_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_S)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSGNJ_D)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n// TODO comment out I2F instructions.\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_X_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_X_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopCMPR_S) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopCMPR_D) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMINMAX_S)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMINMAX_D)->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMUL_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFMADD_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_S) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_S)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMADD_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMSUB_D) ->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMADD_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFNMSUB_D)->List(BR_N, Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Fused multiple add register read constants\n */\nobject IfmvRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFMV_W_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFMV_D_X)->List(BR_N , Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n\n BitPat(uopFCVT_S_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFCVT_D_X) ->List(BR_N,Y, N, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Floating point divide and square root register read constants\n */\nobject FDivRRdDecode extends RRdDecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] =\n Array[(BitPat, List[BitPat])](\n // br type\n // | use alu pipe op1 sel op2 sel\n // | | use muldiv pipe | | immsel csr_cmd\n // | | | use mem pipe | | | rf wen |\n // | | | | alu fcn wd/word?| | | | |\n // | | | | | | | | | | |\n BitPat(uopFDIV_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFDIV_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_S) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N),\n BitPat(uopFSQRT_D) ->List(BR_N, N, Y, N, FN_X , DW_X , OP1_X , OP2_X , IS_X, REN_1, CSR.N))\n}\n\n/**\n * Register read decoder\n *\n * @param supportedUnits indicate what functional units are being used\n */\nclass RegisterReadDecode(supportedUnits: SupportedFuncUnits)(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new BoomBundle {\n val iss_valid = Input(Bool())\n val iss_uop = Input(new MicroOp())\n\n val rrd_valid = Output(Bool())\n val rrd_uop = Output(new MicroOp())\n })\n\n // Issued Instruction\n val rrd_valid = io.iss_valid\n io.rrd_uop := io.iss_uop\n\n var dec_table = AluRRdDecode.table\n if (supportedUnits.jmp) dec_table ++= JmpRRdDecode.table\n if (supportedUnits.mem) dec_table ++= MemRRdDecode.table\n if (supportedUnits.muld) dec_table ++= MulDivRRdDecode.table\n if (supportedUnits.csr) dec_table ++= CsrRRdDecode.table\n if (supportedUnits.fpu) dec_table ++= FpuRRdDecode.table\n if (supportedUnits.fdiv) dec_table ++= FDivRRdDecode.table\n if (supportedUnits.ifpu) dec_table ++= IfmvRRdDecode.table\n val rrd_cs = Wire(new RRdCtrlSigs()).decode(io.rrd_uop.uopc, dec_table)\n\n // rrd_use_alupipe is unused\n io.rrd_uop.ctrl.br_type := rrd_cs.br_type\n io.rrd_uop.ctrl.op1_sel := rrd_cs.op1_sel\n io.rrd_uop.ctrl.op2_sel := rrd_cs.op2_sel\n io.rrd_uop.ctrl.imm_sel := rrd_cs.imm_sel\n io.rrd_uop.ctrl.op_fcn := rrd_cs.op_fcn.asUInt\n io.rrd_uop.ctrl.fcn_dw := rrd_cs.fcn_dw.asBool\n io.rrd_uop.ctrl.is_load := io.rrd_uop.uopc === uopLD\n io.rrd_uop.ctrl.is_sta := io.rrd_uop.uopc === uopSTA || io.rrd_uop.uopc === uopAMO_AG\n io.rrd_uop.ctrl.is_std := io.rrd_uop.uopc === uopSTD || (io.rrd_uop.ctrl.is_sta && io.rrd_uop.lrs2_rtype === RT_FIX)\n\n when (io.rrd_uop.uopc === uopAMO_AG || (io.rrd_uop.uopc === uopLD && io.rrd_uop.mem_cmd === M_XLR)) {\n io.rrd_uop.imm_packed := 0.U\n }\n\n val raddr1 = io.rrd_uop.prs1 // although renamed, it'll stay 0 if lrs1 = 0\n val csr_ren = (rrd_cs.csr_cmd === CSR.S || rrd_cs.csr_cmd === CSR.C) && raddr1 === 0.U\n io.rrd_uop.ctrl.csr_cmd := Mux(csr_ren, CSR.R, rrd_cs.csr_cmd)\n\n //-------------------------------------------------------------\n // set outputs\n\n io.rrd_valid := rrd_valid\n}", + "response": "module RegisterReadDecode_1(\n input io_iss_valid,\n input [6:0] io_iss_uop_uopc,\n input [31:0] io_iss_uop_inst,\n input [31:0] io_iss_uop_debug_inst,\n input io_iss_uop_is_rvc,\n input [39:0] io_iss_uop_debug_pc,\n input [2:0] io_iss_uop_iq_type,\n input [9:0] io_iss_uop_fu_code,\n input [1:0] io_iss_uop_iw_state,\n input io_iss_uop_is_br,\n input io_iss_uop_is_jalr,\n input io_iss_uop_is_jal,\n input io_iss_uop_is_sfb,\n input [7:0] io_iss_uop_br_mask,\n input [2:0] io_iss_uop_br_tag,\n input [3:0] io_iss_uop_ftq_idx,\n input io_iss_uop_edge_inst,\n input [5:0] io_iss_uop_pc_lob,\n input io_iss_uop_taken,\n input [19:0] io_iss_uop_imm_packed,\n input [11:0] io_iss_uop_csr_addr,\n input [4:0] io_iss_uop_rob_idx,\n input [2:0] io_iss_uop_ldq_idx,\n input [2:0] io_iss_uop_stq_idx,\n input [1:0] io_iss_uop_rxq_idx,\n input [5:0] io_iss_uop_pdst,\n input [5:0] io_iss_uop_prs1,\n input [5:0] io_iss_uop_prs2,\n input [5:0] io_iss_uop_prs3,\n input [3:0] io_iss_uop_ppred,\n input io_iss_uop_prs1_busy,\n input io_iss_uop_prs2_busy,\n input io_iss_uop_prs3_busy,\n input io_iss_uop_ppred_busy,\n input [5:0] io_iss_uop_stale_pdst,\n input io_iss_uop_exception,\n input [63:0] io_iss_uop_exc_cause,\n input io_iss_uop_bypassable,\n input [4:0] io_iss_uop_mem_cmd,\n input [1:0] io_iss_uop_mem_size,\n input io_iss_uop_mem_signed,\n input io_iss_uop_is_fence,\n input io_iss_uop_is_fencei,\n input io_iss_uop_is_amo,\n input io_iss_uop_uses_ldq,\n input io_iss_uop_uses_stq,\n input io_iss_uop_is_sys_pc2epc,\n input io_iss_uop_is_unique,\n input io_iss_uop_flush_on_commit,\n input io_iss_uop_ldst_is_rs1,\n input [5:0] io_iss_uop_ldst,\n input [5:0] io_iss_uop_lrs1,\n input [5:0] io_iss_uop_lrs2,\n input [5:0] io_iss_uop_lrs3,\n input io_iss_uop_ldst_val,\n input [1:0] io_iss_uop_dst_rtype,\n input [1:0] io_iss_uop_lrs1_rtype,\n input [1:0] io_iss_uop_lrs2_rtype,\n input io_iss_uop_frs3_en,\n input io_iss_uop_fp_val,\n input io_iss_uop_fp_single,\n input io_iss_uop_xcpt_pf_if,\n input io_iss_uop_xcpt_ae_if,\n input io_iss_uop_xcpt_ma_if,\n input io_iss_uop_bp_debug_if,\n input io_iss_uop_bp_xcpt_if,\n input [1:0] io_iss_uop_debug_fsrc,\n input [1:0] io_iss_uop_debug_tsrc,\n output io_rrd_valid,\n output [6:0] io_rrd_uop_uopc,\n output [31:0] io_rrd_uop_inst,\n output [31:0] io_rrd_uop_debug_inst,\n output io_rrd_uop_is_rvc,\n output [39:0] io_rrd_uop_debug_pc,\n output [2:0] io_rrd_uop_iq_type,\n output [9:0] io_rrd_uop_fu_code,\n output [3:0] io_rrd_uop_ctrl_br_type,\n output [1:0] io_rrd_uop_ctrl_op1_sel,\n output [2:0] io_rrd_uop_ctrl_op2_sel,\n output [2:0] io_rrd_uop_ctrl_imm_sel,\n output [4:0] io_rrd_uop_ctrl_op_fcn,\n output io_rrd_uop_ctrl_fcn_dw,\n output [2:0] io_rrd_uop_ctrl_csr_cmd,\n output io_rrd_uop_ctrl_is_load,\n output io_rrd_uop_ctrl_is_sta,\n output io_rrd_uop_ctrl_is_std,\n output [1:0] io_rrd_uop_iw_state,\n output io_rrd_uop_is_br,\n output io_rrd_uop_is_jalr,\n output io_rrd_uop_is_jal,\n output io_rrd_uop_is_sfb,\n output [7:0] io_rrd_uop_br_mask,\n output [2:0] io_rrd_uop_br_tag,\n output [3:0] io_rrd_uop_ftq_idx,\n output io_rrd_uop_edge_inst,\n output [5:0] io_rrd_uop_pc_lob,\n output io_rrd_uop_taken,\n output [19:0] io_rrd_uop_imm_packed,\n output [11:0] io_rrd_uop_csr_addr,\n output [4:0] io_rrd_uop_rob_idx,\n output [2:0] io_rrd_uop_ldq_idx,\n output [2:0] io_rrd_uop_stq_idx,\n output [1:0] io_rrd_uop_rxq_idx,\n output [5:0] io_rrd_uop_pdst,\n output [5:0] io_rrd_uop_prs1,\n output [5:0] io_rrd_uop_prs2,\n output [5:0] io_rrd_uop_prs3,\n output [3:0] io_rrd_uop_ppred,\n output io_rrd_uop_prs1_busy,\n output io_rrd_uop_prs2_busy,\n output io_rrd_uop_prs3_busy,\n output io_rrd_uop_ppred_busy,\n output [5:0] io_rrd_uop_stale_pdst,\n output io_rrd_uop_exception,\n output [63:0] io_rrd_uop_exc_cause,\n output io_rrd_uop_bypassable,\n output [4:0] io_rrd_uop_mem_cmd,\n output [1:0] io_rrd_uop_mem_size,\n output io_rrd_uop_mem_signed,\n output io_rrd_uop_is_fence,\n output io_rrd_uop_is_fencei,\n output io_rrd_uop_is_amo,\n output io_rrd_uop_uses_ldq,\n output io_rrd_uop_uses_stq,\n output io_rrd_uop_is_sys_pc2epc,\n output io_rrd_uop_is_unique,\n output io_rrd_uop_flush_on_commit,\n output io_rrd_uop_ldst_is_rs1,\n output [5:0] io_rrd_uop_ldst,\n output [5:0] io_rrd_uop_lrs1,\n output [5:0] io_rrd_uop_lrs2,\n output [5:0] io_rrd_uop_lrs3,\n output io_rrd_uop_ldst_val,\n output [1:0] io_rrd_uop_dst_rtype,\n output [1:0] io_rrd_uop_lrs1_rtype,\n output [1:0] io_rrd_uop_lrs2_rtype,\n output io_rrd_uop_frs3_en,\n output io_rrd_uop_fp_val,\n output io_rrd_uop_fp_single,\n output io_rrd_uop_xcpt_pf_if,\n output io_rrd_uop_xcpt_ae_if,\n output io_rrd_uop_xcpt_ma_if,\n output io_rrd_uop_bp_debug_if,\n output io_rrd_uop_bp_xcpt_if,\n output [1:0] io_rrd_uop_debug_fsrc,\n output [1:0] io_rrd_uop_debug_tsrc\n);\n\n wire [6:0] rrd_cs_decoder_decoded_invInputs = ~io_iss_uop_uopc;\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_9 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_12 = {rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [5:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_14 = {io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_51 = {io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [4:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_54 = {rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]};\n wire [6:0] _rrd_cs_decoder_decoded_andMatrixOutputs_T_58 = {io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], io_iss_uop_uopc[6]};\n wire io_rrd_uop_ctrl_is_load_0 = io_iss_uop_uopc == 7'h1;\n wire _io_rrd_uop_ctrl_is_sta_T_1 = io_iss_uop_uopc == 7'h43;\n wire io_rrd_uop_ctrl_is_sta_0 = io_iss_uop_uopc == 7'h2 | _io_rrd_uop_ctrl_is_sta_T_1;\n assign io_rrd_valid = io_iss_valid;\n assign io_rrd_uop_uopc = io_iss_uop_uopc;\n assign io_rrd_uop_inst = io_iss_uop_inst;\n assign io_rrd_uop_debug_inst = io_iss_uop_debug_inst;\n assign io_rrd_uop_is_rvc = io_iss_uop_is_rvc;\n assign io_rrd_uop_debug_pc = io_iss_uop_debug_pc;\n assign io_rrd_uop_iq_type = io_iss_uop_iq_type;\n assign io_rrd_uop_fu_code = io_iss_uop_fu_code;\n assign io_rrd_uop_ctrl_br_type = {1'h0, |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}};\n assign io_rrd_uop_ctrl_op1_sel = {1'h0, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12};\n assign io_rrd_uop_ctrl_op2_sel = {1'h0, &{rrd_cs_decoder_decoded_invInputs[5], io_iss_uop_uopc[6]}, |{&{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}}};\n assign io_rrd_uop_ctrl_imm_sel = {1'h0, |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_12, &{io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}}, |{&{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_12}};\n assign io_rrd_uop_ctrl_op_fcn =\n {|{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},\n |{&_rrd_cs_decoder_decoded_andMatrixOutputs_T_9, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},\n |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},\n |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_14, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_51, &{rrd_cs_decoder_decoded_invInputs[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58},\n |{&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[3], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[0], io_iss_uop_uopc[1], rrd_cs_decoder_decoded_invInputs[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[0], io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{rrd_cs_decoder_decoded_invInputs[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], rrd_cs_decoder_decoded_invInputs[3], io_iss_uop_uopc[4], rrd_cs_decoder_decoded_invInputs[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[1], io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_58}};\n assign io_rrd_uop_ctrl_fcn_dw = {&{io_iss_uop_uopc[0], io_iss_uop_uopc[1], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &{io_iss_uop_uopc[2], io_iss_uop_uopc[3], rrd_cs_decoder_decoded_invInputs[4], io_iss_uop_uopc[5], rrd_cs_decoder_decoded_invInputs[6]}, &_rrd_cs_decoder_decoded_andMatrixOutputs_T_54} == 3'h0;\n assign io_rrd_uop_ctrl_csr_cmd = 3'h0;\n assign io_rrd_uop_ctrl_is_load = io_rrd_uop_ctrl_is_load_0;\n assign io_rrd_uop_ctrl_is_sta = io_rrd_uop_ctrl_is_sta_0;\n assign io_rrd_uop_ctrl_is_std = io_iss_uop_uopc == 7'h3 | io_rrd_uop_ctrl_is_sta_0 & io_iss_uop_lrs2_rtype == 2'h0;\n assign io_rrd_uop_iw_state = io_iss_uop_iw_state;\n assign io_rrd_uop_is_br = io_iss_uop_is_br;\n assign io_rrd_uop_is_jalr = io_iss_uop_is_jalr;\n assign io_rrd_uop_is_jal = io_iss_uop_is_jal;\n assign io_rrd_uop_is_sfb = io_iss_uop_is_sfb;\n assign io_rrd_uop_br_mask = io_iss_uop_br_mask;\n assign io_rrd_uop_br_tag = io_iss_uop_br_tag;\n assign io_rrd_uop_ftq_idx = io_iss_uop_ftq_idx;\n assign io_rrd_uop_edge_inst = io_iss_uop_edge_inst;\n assign io_rrd_uop_pc_lob = io_iss_uop_pc_lob;\n assign io_rrd_uop_taken = io_iss_uop_taken;\n assign io_rrd_uop_imm_packed = _io_rrd_uop_ctrl_is_sta_T_1 | io_rrd_uop_ctrl_is_load_0 & io_iss_uop_mem_cmd == 5'h6 ? 20'h0 : io_iss_uop_imm_packed;\n assign io_rrd_uop_csr_addr = io_iss_uop_csr_addr;\n assign io_rrd_uop_rob_idx = io_iss_uop_rob_idx;\n assign io_rrd_uop_ldq_idx = io_iss_uop_ldq_idx;\n assign io_rrd_uop_stq_idx = io_iss_uop_stq_idx;\n assign io_rrd_uop_rxq_idx = io_iss_uop_rxq_idx;\n assign io_rrd_uop_pdst = io_iss_uop_pdst;\n assign io_rrd_uop_prs1 = io_iss_uop_prs1;\n assign io_rrd_uop_prs2 = io_iss_uop_prs2;\n assign io_rrd_uop_prs3 = io_iss_uop_prs3;\n assign io_rrd_uop_ppred = io_iss_uop_ppred;\n assign io_rrd_uop_prs1_busy = io_iss_uop_prs1_busy;\n assign io_rrd_uop_prs2_busy = io_iss_uop_prs2_busy;\n assign io_rrd_uop_prs3_busy = io_iss_uop_prs3_busy;\n assign io_rrd_uop_ppred_busy = io_iss_uop_ppred_busy;\n assign io_rrd_uop_stale_pdst = io_iss_uop_stale_pdst;\n assign io_rrd_uop_exception = io_iss_uop_exception;\n assign io_rrd_uop_exc_cause = io_iss_uop_exc_cause;\n assign io_rrd_uop_bypassable = io_iss_uop_bypassable;\n assign io_rrd_uop_mem_cmd = io_iss_uop_mem_cmd;\n assign io_rrd_uop_mem_size = io_iss_uop_mem_size;\n assign io_rrd_uop_mem_signed = io_iss_uop_mem_signed;\n assign io_rrd_uop_is_fence = io_iss_uop_is_fence;\n assign io_rrd_uop_is_fencei = io_iss_uop_is_fencei;\n assign io_rrd_uop_is_amo = io_iss_uop_is_amo;\n assign io_rrd_uop_uses_ldq = io_iss_uop_uses_ldq;\n assign io_rrd_uop_uses_stq = io_iss_uop_uses_stq;\n assign io_rrd_uop_is_sys_pc2epc = io_iss_uop_is_sys_pc2epc;\n assign io_rrd_uop_is_unique = io_iss_uop_is_unique;\n assign io_rrd_uop_flush_on_commit = io_iss_uop_flush_on_commit;\n assign io_rrd_uop_ldst_is_rs1 = io_iss_uop_ldst_is_rs1;\n assign io_rrd_uop_ldst = io_iss_uop_ldst;\n assign io_rrd_uop_lrs1 = io_iss_uop_lrs1;\n assign io_rrd_uop_lrs2 = io_iss_uop_lrs2;\n assign io_rrd_uop_lrs3 = io_iss_uop_lrs3;\n assign io_rrd_uop_ldst_val = io_iss_uop_ldst_val;\n assign io_rrd_uop_dst_rtype = io_iss_uop_dst_rtype;\n assign io_rrd_uop_lrs1_rtype = io_iss_uop_lrs1_rtype;\n assign io_rrd_uop_lrs2_rtype = io_iss_uop_lrs2_rtype;\n assign io_rrd_uop_frs3_en = io_iss_uop_frs3_en;\n assign io_rrd_uop_fp_val = io_iss_uop_fp_val;\n assign io_rrd_uop_fp_single = io_iss_uop_fp_single;\n assign io_rrd_uop_xcpt_pf_if = io_iss_uop_xcpt_pf_if;\n assign io_rrd_uop_xcpt_ae_if = io_iss_uop_xcpt_ae_if;\n assign io_rrd_uop_xcpt_ma_if = io_iss_uop_xcpt_ma_if;\n assign io_rrd_uop_bp_debug_if = io_iss_uop_bp_debug_if;\n assign io_rrd_uop_bp_xcpt_if = io_iss_uop_bp_xcpt_if;\n assign io_rrd_uop_debug_fsrc = io_iss_uop_debug_fsrc;\n assign io_rrd_uop_debug_tsrc = io_iss_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a28d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [27:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [27:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [27:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{RegEnable, Cat}\n\n/** These wrap behavioral\n * shift and next registers into specific modules to allow for\n * backend flows to replace or constrain\n * them properly when used for CDC synchronization,\n * rather than buffering.\n * \n * \n * These are built up of *ResetSynchronizerPrimitiveShiftReg,\n * intended to be replaced by the integrator's metastable flops chains or replaced\n * at this level if they have a multi-bit wide synchronizer primitive.\n * The different types vary in their reset behavior:\n * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin\n * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep\n * 1-bit-wide shift registers.\n * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg\n * \n * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.\n * \n * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross\n * Clock Domains.\n*/\n\nobject SynchronizerResetType extends Enumeration {\n val NonSync, Inferred, Sync, Async = Value\n}\n\n\n// Note: this should not be used directly.\n// Use the companion object to generate this with the correct reset type mixin.\nprivate class SynchronizerPrimitiveShiftReg(\n sync: Int,\n init: Boolean,\n resetType: SynchronizerResetType.Value)\n extends AbstractPipelineReg(1) {\n\n val initInt = if (init) 1 else 0\n val initPostfix = resetType match {\n case SynchronizerResetType.NonSync => \"\"\n case _ => s\"_i${initInt}\"\n }\n override def desiredName = s\"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}\"\n\n val chain = List.tabulate(sync) { i =>\n val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)\n reg.suggestName(s\"sync_$i\")\n }\n chain.last := io.d.asBool\n\n (chain.init zip chain.tail).foreach { case (sink, source) =>\n sink := source\n }\n io.q := chain.head.asUInt\n}\n\nprivate object SynchronizerPrimitiveShiftReg {\n def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {\n val gen: () => SynchronizerPrimitiveShiftReg = resetType match {\n case SynchronizerResetType.NonSync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n case SynchronizerResetType.Async =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset\n case SynchronizerResetType.Sync =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset\n case SynchronizerResetType.Inferred =>\n () => new SynchronizerPrimitiveShiftReg(sync, init, resetType)\n }\n AbstractPipelineReg(gen(), in)\n }\n}\n\n// Note: This module may end up with a non-AsyncReset type reset.\n// But the Primitives within will always have AsyncReset type.\nclass AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)\n extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asAsyncReset){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject AsyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\n// Note: This module may end up with a non-Bool type reset.\n// But the Primitives within will always have Bool reset type.\n@deprecated(\"SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.\", \"rocket-chip 1.2\")\nclass SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n withReset(reset.asBool){\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)\n }\n }\n io.q := Cat(output.reverse)\n}\n\nobject SyncResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}\"\n val output = Seq.tabulate(w) { i =>\n val initBit = ((init >> i) & 1) > 0\n SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)\n }\n io.q := Cat(output.reverse)\n}\n\nobject ResetSynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =\n AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)\n\n def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =\n apply (in, sync, 0, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, 0, None)\n\n def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =\n apply(in, sync, init.litValue.toInt, name)\n\n def apply [T <: Data](in: T, sync: Int, init: T): T =\n apply (in, sync, init.litValue.toInt, None)\n}\n\nclass SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {\n require(sync > 1, s\"Sync must be greater than 1, not ${sync}.\")\n override def desiredName = s\"SynchronizerShiftReg_w${w}_d${sync}\"\n val output = Seq.tabulate(w) { i =>\n SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)\n }\n io.q := Cat(output.reverse)\n}\n\nobject SynchronizerShiftReg {\n def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =\n if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)\n\n def apply [T <: Data](in: T, sync: Int): T =\n apply (in, sync, None)\n\n def apply [T <: Data](in: T): T =\n apply (in, 3, None)\n\n\n}\n\nclass ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {\n\n override def desiredName = s\"ClockCrossingReg_w${w}\"\n\n val io = IO(new Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n })\n\n val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)\n io.q := cdc_reg\n}\n\nobject ClockCrossingReg {\n def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {\n val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))\n name.foreach{ cdc_reg.suggestName(_) }\n cdc_reg.io.d := in.asUInt\n cdc_reg.io.en := en\n cdc_reg.io.q.asTypeOf(in)\n }\n}", + "response": "module ClockCrossingReg_w32_TestHarness_UNIQUIFIED(\n input clock,\n input [31:0] io_d,\n output [31:0] io_q,\n input io_en\n);\n\n reg [31:0] cdc_reg;\n always @(posedge clock) begin\n if (io_en)\n cdc_reg <= io_d;\n end\n assign io_q = cdc_reg;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPToInt(\n input clock,\n input io_in_valid,\n input io_in_bits_ren2,\n input [1:0] io_in_bits_typeTagOut,\n input io_in_bits_wflags,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_typ,\n input [1:0] io_in_bits_fmt,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n output io_out_bits_lt,\n output [63:0] io_out_bits_toint,\n output [4:0] io_out_bits_exc\n);\n\n wire [63:0] toint;\n wire _narrow_io_signedOut_T;\n wire intType;\n wire [2:0] _narrow_io_intExceptionFlags;\n wire [63:0] _conv_io_out;\n wire [2:0] _conv_io_intExceptionFlags;\n wire _dcmp_io_lt;\n wire _dcmp_io_eq;\n wire [4:0] _dcmp_io_exceptionFlags;\n reg in_ren2;\n reg [1:0] in_typeTagOut;\n reg in_wflags;\n reg [2:0] in_rm;\n reg [1:0] in_typ;\n reg [1:0] in_fmt;\n reg [64:0] in_in1;\n reg [64:0] in_in2;\n wire [12:0] toint_ieee_unrecoded_rawIn_sExp = {1'h0, in_in1[63:52]};\n wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];\n wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T = {in_in1[52], in_in1[30]};\n wire toint_ieee_prevUnrecoded_rawIn_isInf = (&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T) & ~(in_in1[29]);\n wire toint_ieee_prevUnrecoded_isSubnormal = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;\n wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];\n wire toint_ieee_unrecoded_rawIn_1_isInf = (&(in_in1[63:62])) & ~(in_in1[61]);\n wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402;\n wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52];\n wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? _toint_ieee_unrecoded_denormFract_T_3[51:0] : toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : in_in1[51:0];\n wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1 = {in_in1[52], in_in1[30]};\n wire toint_ieee_prevUnrecoded_rawIn_1_isInf = (&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1) & ~(in_in1[29]);\n wire toint_ieee_prevUnrecoded_isSubnormal_1 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82;\n wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23];\n wire [63:0] toint_ieee = in_typeTagOut[0] ? {in_in1[64], (toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : in_in1[62:52] + 11'h3FF) | {11{(&(in_in1[63:62])) & in_in1[61] | toint_ieee_unrecoded_rawIn_1_isInf}}, toint_ieee_unrecoded_fractOut_1[51:32], (&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1) & in_in1[29] | toint_ieee_prevUnrecoded_rawIn_1_isInf}}, toint_ieee_prevUnrecoded_isSubnormal_1 ? _toint_ieee_prevUnrecoded_denormFract_T_3[22:0] : toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]} : toint_ieee_unrecoded_fractOut_1[31:0]} : {2{(&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_rawIn_isSpecial_T) & in_in1[29] | toint_ieee_prevUnrecoded_rawIn_isInf}}, toint_ieee_prevUnrecoded_isSubnormal ? _toint_ieee_prevUnrecoded_denormFract_T_1[22:0] : toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : in_in1[22:0]} : $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402 ? _toint_ieee_unrecoded_denormFract_T_1[31:0] : (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}};\n wire [8:0] _classify_out_expOut_commonCase_T = in_in1[60:52] - 9'h100;\n wire [8:0] classify_out_expOut = in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5 ? {in_in1[63:61], _classify_out_expOut_commonCase_T[5:0]} : _classify_out_expOut_commonCase_T;\n wire _classify_out_isNormal_T = classify_out_expOut[8:7] == 2'h1;\n wire classify_out_isSubnormal = classify_out_expOut[8:6] == 3'h1 | _classify_out_isNormal_T & classify_out_expOut[6:0] < 7'h2;\n wire classify_out_isNormal = _classify_out_isNormal_T & (|(classify_out_expOut[6:1])) | classify_out_expOut[8:7] == 2'h2;\n wire classify_out_isZero = classify_out_expOut[8:6] == 3'h0;\n wire classify_out_isInf = (&(classify_out_expOut[8:7])) & ~(classify_out_expOut[6]);\n wire _classify_out_isNormal_T_4 = in_in1[63:62] == 2'h1;\n wire classify_out_isSubnormal_1 = in_in1[63:61] == 3'h1 | _classify_out_isNormal_T_4 & in_in1[61:52] < 10'h2;\n wire classify_out_isNormal_1 = _classify_out_isNormal_T_4 & (|(in_in1[61:53])) | in_in1[63:62] == 2'h2;\n wire classify_out_isZero_1 = in_in1[63:61] == 3'h0;\n wire classify_out_isInf_1 = (&(in_in1[63:62])) & ~(in_in1[61]);\n assign intType = in_wflags ? ~in_ren2 & in_typ[1] : ~(in_rm[0]) & in_fmt[0];\n assign _narrow_io_signedOut_T = in_typ[0];\n wire excSign = in_in1[64] & in_in1[63:61] != 3'h7;\n wire invalid = _conv_io_intExceptionFlags[2] | _narrow_io_intExceptionFlags[1];\n assign toint = in_wflags ? (in_ren2 ? {toint_ieee[63:32], 31'h0, |(~(in_rm[1:0]) & {_dcmp_io_lt, _dcmp_io_eq})} : ~(in_typ[1]) & invalid ? {_conv_io_out[63:32], ~_narrow_io_signedOut_T == excSign, {31{~excSign}}} : _conv_io_out) : in_rm[0] ? {toint_ieee[63:32], 22'h0, in_typeTagOut[0] ? {(&(in_in1[63:61])) & in_in1[51], (&(in_in1[63:61])) & ~(in_in1[51]), classify_out_isInf_1 & ~(in_in1[64]), classify_out_isNormal_1 & ~(in_in1[64]), classify_out_isSubnormal_1 & ~(in_in1[64]), classify_out_isZero_1 & ~(in_in1[64]), classify_out_isZero_1 & in_in1[64], classify_out_isSubnormal_1 & in_in1[64], classify_out_isNormal_1 & in_in1[64], classify_out_isInf_1 & in_in1[64]} : {(&(classify_out_expOut[8:6])) & in_in1[51], (&(classify_out_expOut[8:6])) & ~(in_in1[51]), classify_out_isInf & ~(in_in1[64]), classify_out_isNormal & ~(in_in1[64]), classify_out_isSubnormal & ~(in_in1[64]), classify_out_isZero & ~(in_in1[64]), classify_out_isZero & in_in1[64], classify_out_isSubnormal & in_in1[64], classify_out_isNormal & in_in1[64], classify_out_isInf & in_in1[64]}} : toint_ieee;\n always @(posedge clock) begin\n if (io_in_valid) begin\n in_ren2 <= io_in_bits_ren2;\n in_typeTagOut <= io_in_bits_typeTagOut;\n in_wflags <= io_in_bits_wflags;\n in_rm <= io_in_bits_rm;\n in_typ <= io_in_bits_typ;\n in_fmt <= io_in_bits_fmt;\n in_in1 <= io_in_bits_in1;\n in_in2 <= io_in_bits_in2;\n end\n end\n CompareRecFN dcmp (\n .io_a (in_in1),\n .io_b (in_in2),\n .io_signaling (~(in_rm[1])),\n .io_lt (_dcmp_io_lt),\n .io_eq (_dcmp_io_eq),\n .io_exceptionFlags (_dcmp_io_exceptionFlags)\n );\n RecFNToIN_e11_s53_i64 conv (\n .io_in (in_in1),\n .io_roundingMode (in_rm),\n .io_signedOut (~_narrow_io_signedOut_T),\n .io_out (_conv_io_out),\n .io_intExceptionFlags (_conv_io_intExceptionFlags)\n );\n RecFNToIN_e11_s53_i32 narrow (\n .io_in (in_in1),\n .io_roundingMode (in_rm),\n .io_signedOut (~_narrow_io_signedOut_T),\n .io_intExceptionFlags (_narrow_io_intExceptionFlags)\n );\n assign io_out_bits_lt = _dcmp_io_lt | $signed(in_in1) < 65'sh0 & $signed(in_in2) > -65'sh1;\n assign io_out_bits_toint = intType ? toint : {{32{toint[31]}}, toint[31:0]};\n assign io_out_bits_exc = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : in_typ[1] ? {|(_conv_io_intExceptionFlags[2:1]), 3'h0, _conv_io_intExceptionFlags[0]} : {invalid, 3'h0, ~invalid & _conv_io_intExceptionFlags[0]}) : 5'h0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\ncase class AsyncQueueParams(\n depth: Int = 8,\n sync: Int = 3,\n safe: Boolean = true,\n// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.\n// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.\n narrow: Boolean = false)\n// If narrow is true then the read mux is moved to the source side of the crossing.\n// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,\n// at the expense of a combinational path from the sink to the source and back to the sink.\n{\n require (depth > 0 && isPow2(depth))\n require (sync >= 2)\n\n val bits = log2Ceil(depth)\n val wires = if (narrow) 1 else depth\n}\n\nobject AsyncQueueParams {\n // When there is only one entry, we don't need narrow.\n def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)\n}\n\nclass AsyncBundleSafety extends Bundle {\n val ridx_valid = Input (Bool())\n val widx_valid = Output(Bool())\n val source_reset_n = Output(Bool())\n val sink_reset_n = Input (Bool())\n}\n\nclass AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {\n // Data-path synchronization\n val mem = Output(Vec(params.wires, gen))\n val ridx = Input (UInt((params.bits+1).W))\n val widx = Output(UInt((params.bits+1).W))\n val index = params.narrow.option(Input(UInt(params.bits.W)))\n\n // Signals used to self-stabilize a safe AsyncQueue\n val safe = params.safe.option(new AsyncBundleSafety)\n}\n\nobject GrayCounter {\n def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = \"binary\"): UInt = {\n val incremented = Wire(UInt(bits.W))\n val binary = RegNext(next=incremented, init=0.U).suggestName(name)\n incremented := Mux(clear, 0.U, binary + increment.asUInt)\n incremented ^ (incremented >> 1)\n }\n}\n\nclass AsyncValidSync(sync: Int, desc: String) extends RawModule {\n val io = IO(new Bundle {\n val in = Input(Bool())\n val out = Output(Bool())\n })\n val clock = IO(Input(Clock()))\n val reset = IO(Input(AsyncReset()))\n withClockAndReset(clock, reset){\n io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))\n }\n}\n\nclass AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSource_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the source domain\n val enq = Flipped(Decoupled(gen))\n // These cross to the sink clock domain\n val async = new AsyncBundle(gen, params)\n })\n\n val bits = params.bits\n val sink_ready = WireInit(true.B)\n val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.\n val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, \"widx_bin\"))\n val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some(\"ridx_gray\"))\n val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)\n\n val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))\n when (io.enq.fire) { mem(index) := io.enq.bits }\n\n val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName(\"ready_reg\"))\n io.enq.ready := ready_reg && sink_ready\n\n val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName(\"widx_gray\"))\n io.async.widx := widx_reg\n\n io.async.index match {\n case Some(index) => io.async.mem(0) := mem(index)\n case None => io.async.mem := mem\n }\n\n io.async.safe.foreach { sio =>\n val source_valid_0 = Module(new AsyncValidSync(params.sync, \"source_valid_0\"))\n val source_valid_1 = Module(new AsyncValidSync(params.sync, \"source_valid_1\"))\n\n val sink_extend = Module(new AsyncValidSync(params.sync, \"sink_extend\"))\n val sink_valid = Module(new AsyncValidSync(params.sync, \"sink_valid\"))\n source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset\n sink_valid .reset := reset.asAsyncReset\n\n source_valid_0.clock := clock\n source_valid_1.clock := clock\n sink_extend .clock := clock\n sink_valid .clock := clock\n\n source_valid_0.io.in := true.B\n source_valid_1.io.in := source_valid_0.io.out\n sio.widx_valid := source_valid_1.io.out\n sink_extend.io.in := sio.ridx_valid\n sink_valid.io.in := sink_extend.io.out\n sink_ready := sink_valid.io.out\n sio.source_reset_n := !reset.asBool\n\n // Assert that if there is stuff in the queue, then reset cannot happen\n // Impossible to write because dequeue can occur on the receiving side,\n // then reset allowed to happen, but write side cannot know that dequeue\n // occurred.\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, \"Enqueue while sink is reset and AsyncQueueSource is unprotected\")\n // assert (!reset_rise || prev_idx_match.asBool, \"Sink reset while AsyncQueueSource not empty\")\n }\n}\n\nclass AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {\n override def desiredName = s\"AsyncQueueSink_${gen.typeName}\"\n\n val io = IO(new Bundle {\n // These come from the sink domain\n val deq = Decoupled(gen)\n // These cross to the source clock domain\n val async = Flipped(new AsyncBundle(gen, params))\n })\n\n val bits = params.bits\n val source_ready = WireInit(true.B)\n val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, \"ridx_bin\"))\n val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some(\"widx_gray\"))\n val valid = source_ready && ridx =/= widx\n\n // The mux is safe because timing analysis ensures ridx has reached the register\n // On an ASIC, changes to the unread location cannot affect the selected value\n // On an FPGA, only one input changes at a time => mem updates don't cause glitches\n // The register only latches when the selected valued is not being written\n val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))\n io.async.index.foreach { _ := index }\n // This register does not NEED to be reset, as its contents will not\n // be considered unless the asynchronously reset deq valid register is set.\n // It is possible that bits latches when the source domain is reset / has power cut\n // This is safe, because isolation gates brought mem low before the zeroed widx reached us\n val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)\n io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some(\"deq_bits_reg\"))\n\n val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName(\"valid_reg\"))\n io.deq.valid := valid_reg && source_ready\n\n val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName(\"ridx_gray\"))\n io.async.ridx := ridx_reg\n\n io.async.safe.foreach { sio =>\n val sink_valid_0 = Module(new AsyncValidSync(params.sync, \"sink_valid_0\"))\n val sink_valid_1 = Module(new AsyncValidSync(params.sync, \"sink_valid_1\"))\n\n val source_extend = Module(new AsyncValidSync(params.sync, \"source_extend\"))\n val source_valid = Module(new AsyncValidSync(params.sync, \"source_valid\"))\n sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset\n source_valid .reset := reset.asAsyncReset\n\n sink_valid_0 .clock := clock\n sink_valid_1 .clock := clock\n source_extend.clock := clock\n source_valid .clock := clock\n\n sink_valid_0.io.in := true.B\n sink_valid_1.io.in := sink_valid_0.io.out\n sio.ridx_valid := sink_valid_1.io.out\n source_extend.io.in := sio.widx_valid\n source_valid.io.in := source_extend.io.out\n source_ready := source_valid.io.out\n sio.sink_reset_n := !reset.asBool\n\n // TODO: write some sort of sanity check assertion for users\n // that denote don't reset when there is activity\n // \n // val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool\n // val reset_and_extend_prev = RegNext(reset_and_extend, true.B)\n // val reset_rise = !reset_and_extend_prev && reset_and_extend\n // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)\n // assert (!reset_rise || prev_idx_match.asBool, \"Source reset while AsyncQueueSink not empty\")\n }\n}\n\nobject FromAsyncBundle\n{\n // Sometimes it makes sense for the sink to have different sync than the source\n def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)\n def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {\n val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))\n sink.io.async <> x\n sink.io.deq\n }\n}\n\nobject ToAsyncBundle\n{\n def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {\n val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))\n source.io.enq <> x\n source.io.async\n }\n}\n\nclass AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {\n val io = IO(new CrossingIO(gen))\n val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }\n val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }\n\n source.io.enq <> io.enq\n io.deq <> sink.io.deq\n sink.io.async <> source.io.async\n}", + "response": "module AsyncQueue(\n input io_enq_clock,\n input io_enq_reset,\n output io_enq_ready,\n input io_enq_valid,\n input [31:0] io_enq_bits_phit,\n input io_deq_clock,\n input io_deq_reset,\n input io_deq_ready,\n output io_deq_valid,\n output [31:0] io_deq_bits_phit\n);\n\n wire [3:0] _sink_io_async_ridx;\n wire _sink_io_async_safe_ridx_valid;\n wire _sink_io_async_safe_sink_reset_n;\n wire [31:0] _source_io_async_mem_0_phit;\n wire [31:0] _source_io_async_mem_1_phit;\n wire [31:0] _source_io_async_mem_2_phit;\n wire [31:0] _source_io_async_mem_3_phit;\n wire [31:0] _source_io_async_mem_4_phit;\n wire [31:0] _source_io_async_mem_5_phit;\n wire [31:0] _source_io_async_mem_6_phit;\n wire [31:0] _source_io_async_mem_7_phit;\n wire [3:0] _source_io_async_widx;\n wire _source_io_async_safe_widx_valid;\n wire _source_io_async_safe_source_reset_n;\n AsyncQueueSource_Phit source (\n .clock (io_enq_clock),\n .reset (io_enq_reset),\n .io_enq_ready (io_enq_ready),\n .io_enq_valid (io_enq_valid),\n .io_enq_bits_phit (io_enq_bits_phit),\n .io_async_mem_0_phit (_source_io_async_mem_0_phit),\n .io_async_mem_1_phit (_source_io_async_mem_1_phit),\n .io_async_mem_2_phit (_source_io_async_mem_2_phit),\n .io_async_mem_3_phit (_source_io_async_mem_3_phit),\n .io_async_mem_4_phit (_source_io_async_mem_4_phit),\n .io_async_mem_5_phit (_source_io_async_mem_5_phit),\n .io_async_mem_6_phit (_source_io_async_mem_6_phit),\n .io_async_mem_7_phit (_source_io_async_mem_7_phit),\n .io_async_ridx (_sink_io_async_ridx),\n .io_async_widx (_source_io_async_widx),\n .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),\n .io_async_safe_widx_valid (_source_io_async_safe_widx_valid),\n .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),\n .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)\n );\n AsyncQueueSink_Phit sink (\n .clock (io_deq_clock),\n .reset (io_deq_reset),\n .io_deq_ready (io_deq_ready),\n .io_deq_valid (io_deq_valid),\n .io_deq_bits_phit (io_deq_bits_phit),\n .io_async_mem_0_phit (_source_io_async_mem_0_phit),\n .io_async_mem_1_phit (_source_io_async_mem_1_phit),\n .io_async_mem_2_phit (_source_io_async_mem_2_phit),\n .io_async_mem_3_phit (_source_io_async_mem_3_phit),\n .io_async_mem_4_phit (_source_io_async_mem_4_phit),\n .io_async_mem_5_phit (_source_io_async_mem_5_phit),\n .io_async_mem_6_phit (_source_io_async_mem_6_phit),\n .io_async_mem_7_phit (_source_io_async_mem_7_phit),\n .io_async_ridx (_sink_io_async_ridx),\n .io_async_widx (_source_io_async_widx),\n .io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),\n .io_async_safe_widx_valid (_source_io_async_safe_widx_valid),\n .io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),\n .io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module tail_2x4(\n input R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input R1_addr,\n input R1_en,\n input R1_clk,\n output [3:0] R1_data,\n input W0_addr,\n input W0_en,\n input W0_clk,\n input [3:0] W0_data\n);\n\n reg [3:0] Memory[0:1];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 4'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module next_16x4(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [3:0] W0_data\n);\n\n reg [3:0] Memory[0:15];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename FreeList\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass RenameFreeList(\n val plWidth: Int,\n val numPregs: Int,\n val numLregs: Int)\n (implicit p: Parameters) extends BoomModule\n{\n private val pregSz = log2Ceil(numPregs)\n private val n = numPregs\n\n val io = IO(new BoomBundle()(p) {\n // Physical register requests.\n val reqs = Input(Vec(plWidth, Bool()))\n val alloc_pregs = Output(Vec(plWidth, Valid(UInt(pregSz.W))))\n\n // Pregs returned by the ROB.\n val dealloc_pregs = Input(Vec(plWidth, Valid(UInt(pregSz.W))))\n\n // Branch info for starting new allocation lists.\n val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Mispredict info for recovering speculatively allocated registers.\n val brupdate = Input(new BrUpdateInfo)\n\n val debug = new Bundle {\n val pipeline_empty = Input(Bool())\n val freelist = Output(Bits(numPregs.W))\n val isprlist = Output(Bits(numPregs.W))\n }\n })\n // The free list register array and its branch allocation lists.\n val free_list = RegInit(UInt(numPregs.W), ~(1.U(numPregs.W)))\n val br_alloc_lists = Reg(Vec(maxBrCount, UInt(numPregs.W)))\n\n // Select pregs from the free list.\n val sels = SelectFirstN(free_list, plWidth)\n val sel_fire = Wire(Vec(plWidth, Bool()))\n\n // Allocations seen by branches in each pipeline slot.\n val allocs = io.alloc_pregs map (a => UIntToOH(a.bits))\n val alloc_masks = (allocs zip io.reqs).scanRight(0.U(n.W)) { case ((a,r),m) => m | a & Fill(n,r) }\n\n // Masks that modify the freelist array.\n val sel_mask = (sels zip sel_fire) map { case (s,f) => s & Fill(n,f) } reduce(_|_)\n val br_deallocs = br_alloc_lists(io.brupdate.b2.uop.br_tag) & Fill(n, io.brupdate.b2.mispredict)\n val dealloc_mask = io.dealloc_pregs.map(d => UIntToOH(d.bits)(numPregs-1,0) & Fill(n,d.valid)).reduce(_|_) | br_deallocs\n\n val br_slots = VecInit(io.ren_br_tags.map(tag => tag.valid)).asUInt\n // Create branch allocation lists.\n for (i <- 0 until maxBrCount) {\n val list_req = VecInit(io.ren_br_tags.map(tag => UIntToOH(tag.bits)(i))).asUInt & br_slots\n val new_list = list_req.orR\n br_alloc_lists(i) := Mux(new_list, Mux1H(list_req, alloc_masks.slice(1, plWidth+1)),\n br_alloc_lists(i) & ~br_deallocs | alloc_masks(0))\n }\n\n // Update the free list.\n free_list := (free_list & ~sel_mask | dealloc_mask) & ~(1.U(numPregs.W))\n\n // Pipeline logic | hookup outputs.\n for (w <- 0 until plWidth) {\n val can_sel = sels(w).orR\n val r_valid = RegInit(false.B)\n val r_sel = RegEnable(OHToUInt(sels(w)), sel_fire(w))\n\n r_valid := r_valid && !io.reqs(w) || can_sel\n sel_fire(w) := (!r_valid || io.reqs(w)) && can_sel\n\n io.alloc_pregs(w).bits := r_sel\n io.alloc_pregs(w).valid := r_valid\n }\n\n io.debug.freelist := free_list | io.alloc_pregs.map(p => UIntToOH(p.bits) & Fill(n,p.valid)).reduce(_|_)\n io.debug.isprlist := 0.U // TODO track commit free list.\n\n assert (!(io.debug.freelist & dealloc_mask).orR, \"[freelist] Returning a free physical register.\")\n assert (!io.debug.pipeline_empty || PopCount(io.debug.freelist) >= (numPregs - numLregs - 1).U,\n \"[freelist] Leaking physical registers.\")\n}", + "response": "module RenameFreeList(\n input clock,\n input reset,\n input io_reqs_0,\n output io_alloc_pregs_0_valid,\n output [5:0] io_alloc_pregs_0_bits,\n input io_dealloc_pregs_0_valid,\n input [5:0] io_dealloc_pregs_0_bits,\n input io_ren_br_tags_0_valid,\n input [2:0] io_ren_br_tags_0_bits,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_debug_pipeline_empty\n);\n\n reg [5:0] r_sel;\n reg [51:0] free_list;\n reg [51:0] br_alloc_lists_0;\n reg [51:0] br_alloc_lists_1;\n reg [51:0] br_alloc_lists_2;\n reg [51:0] br_alloc_lists_3;\n reg [51:0] br_alloc_lists_4;\n reg [51:0] br_alloc_lists_5;\n reg [51:0] br_alloc_lists_6;\n reg [51:0] br_alloc_lists_7;\n wire [51:0] sels_0 = free_list[0] ? 52'h1 : free_list[1] ? 52'h2 : free_list[2] ? 52'h4 : free_list[3] ? 52'h8 : free_list[4] ? 52'h10 : free_list[5] ? 52'h20 : free_list[6] ? 52'h40 : free_list[7] ? 52'h80 : free_list[8] ? 52'h100 : free_list[9] ? 52'h200 : free_list[10] ? 52'h400 : free_list[11] ? 52'h800 : free_list[12] ? 52'h1000 : free_list[13] ? 52'h2000 : free_list[14] ? 52'h4000 : free_list[15] ? 52'h8000 : free_list[16] ? 52'h10000 : free_list[17] ? 52'h20000 : free_list[18] ? 52'h40000 : free_list[19] ? 52'h80000 : free_list[20] ? 52'h100000 : free_list[21] ? 52'h200000 : free_list[22] ? 52'h400000 : free_list[23] ? 52'h800000 : free_list[24] ? 52'h1000000 : free_list[25] ? 52'h2000000 : free_list[26] ? 52'h4000000 : free_list[27] ? 52'h8000000 : free_list[28] ? 52'h10000000 : free_list[29] ? 52'h20000000 : free_list[30] ? 52'h40000000 : free_list[31] ? 52'h80000000 : free_list[32] ? 52'h100000000 : free_list[33] ? 52'h200000000 : free_list[34] ? 52'h400000000 : free_list[35] ? 52'h800000000 : free_list[36] ? 52'h1000000000 : free_list[37] ? 52'h2000000000 : free_list[38] ? 52'h4000000000 : free_list[39] ? 52'h8000000000 : free_list[40] ? 52'h10000000000 : free_list[41] ? 52'h20000000000 : free_list[42] ? 52'h40000000000 : free_list[43] ? 52'h80000000000 : free_list[44] ? 52'h100000000000 : free_list[45] ? 52'h200000000000 : free_list[46] ? 52'h400000000000 : free_list[47] ? 52'h800000000000 : free_list[48] ? 52'h1000000000000 : free_list[49] ? 52'h2000000000000 : free_list[50] ? 52'h4000000000000 : {free_list[51], 51'h0};\n wire [63:0] allocs_0 = 64'h1 << r_sel;\n wire [7:0][51:0] _GEN = {{br_alloc_lists_7}, {br_alloc_lists_6}, {br_alloc_lists_5}, {br_alloc_lists_4}, {br_alloc_lists_3}, {br_alloc_lists_2}, {br_alloc_lists_1}, {br_alloc_lists_0}};\n wire [51:0] br_deallocs = _GEN[io_brupdate_b2_uop_br_tag] & {52{io_brupdate_b2_mispredict}};\n wire [63:0] _dealloc_mask_T = 64'h1 << io_dealloc_pregs_0_bits;\n wire [51:0] dealloc_mask = _dealloc_mask_T[51:0] & {52{io_dealloc_pregs_0_valid}} | br_deallocs;\n reg r_valid;\n wire sel_fire_0 = (~r_valid | io_reqs_0) & (|sels_0);\n wire [30:0] _r_sel_T_1 = {12'h0, sels_0[51:33]} | sels_0[31:1];\n wire [14:0] _r_sel_T_3 = _r_sel_T_1[30:16] | _r_sel_T_1[14:0];\n wire [6:0] _r_sel_T_5 = _r_sel_T_3[14:8] | _r_sel_T_3[6:0];\n wire [2:0] _r_sel_T_7 = _r_sel_T_5[6:4] | _r_sel_T_5[2:0];\n wire [51:0] _GEN_0 = allocs_0[51:0] & {52{io_reqs_0}};\n always @(posedge clock) begin\n if (reset) begin\n free_list <= 52'hFFFFFFFFFFFFE;\n r_valid <= 1'h0;\n end\n else begin\n free_list <= (free_list & ~(sels_0 & {52{sel_fire_0}}) | dealloc_mask) & 52'hFFFFFFFFFFFFE;\n r_valid <= |{r_valid & ~io_reqs_0, sels_0};\n end\n br_alloc_lists_0 <= io_ren_br_tags_0_bits == 3'h0 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_0 & ~br_deallocs | _GEN_0;\n br_alloc_lists_1 <= io_ren_br_tags_0_bits == 3'h1 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_1 & ~br_deallocs | _GEN_0;\n br_alloc_lists_2 <= io_ren_br_tags_0_bits == 3'h2 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_2 & ~br_deallocs | _GEN_0;\n br_alloc_lists_3 <= io_ren_br_tags_0_bits == 3'h3 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_3 & ~br_deallocs | _GEN_0;\n br_alloc_lists_4 <= io_ren_br_tags_0_bits == 3'h4 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_4 & ~br_deallocs | _GEN_0;\n br_alloc_lists_5 <= io_ren_br_tags_0_bits == 3'h5 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_5 & ~br_deallocs | _GEN_0;\n br_alloc_lists_6 <= io_ren_br_tags_0_bits == 3'h6 & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_6 & ~br_deallocs | _GEN_0;\n br_alloc_lists_7 <= (&io_ren_br_tags_0_bits) & io_ren_br_tags_0_valid ? 52'h0 : br_alloc_lists_7 & ~br_deallocs | _GEN_0;\n if (sel_fire_0)\n r_sel <= {|(sels_0[51:32]), |(_r_sel_T_1[30:15]), |(_r_sel_T_3[14:7]), |(_r_sel_T_5[6:3]), |(_r_sel_T_7[2:1]), _r_sel_T_7[2] | _r_sel_T_7[0]};\n end\n assign io_alloc_pregs_0_valid = r_valid;\n assign io_alloc_pregs_0_bits = r_sel;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1(\n input io_invalidExc,\n input io_infiniteExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [12:0] io_in_sExp,\n input [55:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire roundingMode_odd = io_roundingMode == 3'h6;\n wire roundMagUp = io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign;\n wire [11:0] _roundMask_T_1 = ~(io_in_sExp[11:0]);\n wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);\n wire [18:0] _GEN = {roundMask_shift[18:17], roundMask_shift[20:19], roundMask_shift[22:21], roundMask_shift[24:23], roundMask_shift[26:25], roundMask_shift[28:27], roundMask_shift[30:29], roundMask_shift[32:31], roundMask_shift[34:33], roundMask_shift[36]} & 19'h55555;\n wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> _roundMask_T_1[5:0]);\n wire [53:0] _roundMask_T_129 = _roundMask_T_1[11] ? (_roundMask_T_1[10] ? {~(_roundMask_T_1[9] | _roundMask_T_1[8] | _roundMask_T_1[7] | _roundMask_T_1[6] ? 51'h0 : ~{roundMask_shift[13], roundMask_shift[14], roundMask_shift[15], roundMask_shift[16], roundMask_shift[17], _GEN[18:15] | {roundMask_shift[20:19], roundMask_shift[22:21]} & 4'h5, roundMask_shift[22], _GEN[13] | roundMask_shift[23], roundMask_shift[24], roundMask_shift[25], _GEN[10:7] | {roundMask_shift[28:27], roundMask_shift[30:29]} & 4'h5, roundMask_shift[30], _GEN[5] | roundMask_shift[31], roundMask_shift[32], roundMask_shift[33], {_GEN[2:0], 1'h0} | {roundMask_shift[36:35], roundMask_shift[38:37]} & 4'h5, roundMask_shift[38], roundMask_shift[39], roundMask_shift[40], roundMask_shift[41], roundMask_shift[42], roundMask_shift[43], roundMask_shift[44], roundMask_shift[45], roundMask_shift[46], roundMask_shift[47], roundMask_shift[48], roundMask_shift[49], roundMask_shift[50], roundMask_shift[51], roundMask_shift[52], roundMask_shift[53], roundMask_shift[54], roundMask_shift[55], roundMask_shift[56], roundMask_shift[57], roundMask_shift[58], roundMask_shift[59], roundMask_shift[60], roundMask_shift[61], roundMask_shift[62], roundMask_shift[63]}), 3'h7} : {51'h0, _roundMask_T_1[9] & _roundMask_T_1[8] & _roundMask_T_1[7] & _roundMask_T_1[6] ? {roundMask_shift_1[0], roundMask_shift_1[1], roundMask_shift_1[2]} : 3'h0}) : 54'h0;\n wire [54:0] _GEN_0 = {1'h1, ~_roundMask_T_129};\n wire [54:0] _GEN_1 = {_roundMask_T_129, 1'h1};\n wire [54:0] _roundPosBit_T = io_in_sig[55:1] & _GEN_0 & _GEN_1;\n wire [54:0] _anyRoundExtra_T = io_in_sig[54:0] & _GEN_1;\n wire [109:0] _GEN_2 = {_roundPosBit_T, _anyRoundExtra_T};\n wire _overflow_roundMagUp_T = roundingMode_near_even | io_roundingMode == 3'h4;\n wire [54:0] roundedSig = _overflow_roundMagUp_T & (|_roundPosBit_T) | roundMagUp & (|_GEN_2) ? {1'h0, io_in_sig[55:2] | _roundMask_T_129} + 55'h1 & ~(roundingMode_near_even & (|_roundPosBit_T) & _anyRoundExtra_T == 55'h0 ? {_roundMask_T_129, 1'h1} : 55'h0) : {1'h0, io_in_sig[55:2] & ~_roundMask_T_129} | (roundingMode_odd & (|_GEN_2) ? _GEN_0 & _GEN_1 : 55'h0);\n wire [13:0] sRoundedExp = {io_in_sExp[12], io_in_sExp} + {12'h0, roundedSig[54:53]};\n wire common_totalUnderflow = $signed(sRoundedExp) < 14'sh3CE;\n wire isNaNOut = io_invalidExc | io_in_isNaN;\n wire notNaN_isSpecialInfOut = io_infiniteExc | io_in_isInf;\n wire commonCase = ~isNaNOut & ~notNaN_isSpecialInfOut & ~io_in_isZero;\n wire overflow = commonCase & $signed(sRoundedExp[13:10]) > 4'sh2;\n wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp;\n wire pegMinNonzeroMagOut = commonCase & common_totalUnderflow & (roundMagUp | roundingMode_odd);\n wire pegMaxFiniteMagOut = overflow & ~overflow_roundMagUp;\n wire notNaN_isInfOut = notNaN_isSpecialInfOut | overflow & overflow_roundMagUp;\n assign io_out = {~isNaNOut & io_in_sign, sRoundedExp[11:0] & ~(io_in_isZero | common_totalUnderflow ? 12'hE00 : 12'h0) & ~(pegMinNonzeroMagOut ? 12'hC31 : 12'h0) & {1'h1, ~pegMaxFiniteMagOut, 10'h3FF} & {2'h3, ~notNaN_isInfOut, 9'h1FF} | (pegMinNonzeroMagOut ? 12'h3CE : 12'h0) | (pegMaxFiniteMagOut ? 12'hBFF : 12'h0) | (notNaN_isInfOut ? 12'hC00 : 12'h0) | (isNaNOut ? 12'hE00 : 12'h0), (isNaNOut | io_in_isZero | common_totalUnderflow ? {isNaNOut, 51'h0} : roundedSig[51:0]) | {52{pegMaxFiniteMagOut}}};\n assign io_exceptionFlags = {io_invalidExc, io_infiniteExc, overflow, commonCase & (common_totalUnderflow | (|_GEN_2) & io_in_sExp[12:11] != 2'h1 & _roundMask_T_129[0]), overflow | commonCase & (|{common_totalUnderflow, _roundPosBit_T, _anyRoundExtra_T})};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module l2_tlb_ram_0(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [44:0] RW0_wdata,\n output [44:0] RW0_rdata\n);\n\n l2_tlb_ram_0_ext l2_tlb_ram_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomBTBParams(\n nSets: Int = 128,\n nWays: Int = 2,\n offsetSz: Int = 13,\n extendedNSets: Int = 128\n)\n\n\nclass BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n override val nWays = params.nWays\n val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1\n val offsetSz = params.offsetSz\n val extendedNSets = params.extendedNSets\n\n require(isPow2(nSets))\n require(isPow2(extendedNSets) || extendedNSets == 0)\n require(extendedNSets <= nSets)\n require(extendedNSets >= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }\n val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n\n val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })\n val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })\n val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n\n for (w <- 0 until bankWidth) {\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := Mux(\n entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n for (w <- 0 until nWays) {\n when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {\n btb(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wbtb_mask).asBools\n )\n meta(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wmeta_mask).asBools\n )\n\n\n }\n }\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n\n}", + "response": "module meta_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [123:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [123:0] W0_data,\n input [3:0] W0_mask\n);\n\n meta_0_ext meta_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module dataArrayWay_3(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [63:0] RW0_wdata,\n output [63:0] RW0_rdata\n);\n\n dataArrayWay_0_ext dataArrayWay_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module array_2_0_0(\n input [8:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [8:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n array_0_0_0_ext array_0_0_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomBTBParams(\n nSets: Int = 128,\n nWays: Int = 2,\n offsetSz: Int = 13,\n extendedNSets: Int = 128\n)\n\n\nclass BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n override val nWays = params.nWays\n val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1\n val offsetSz = params.offsetSz\n val extendedNSets = params.extendedNSets\n\n require(isPow2(nSets))\n require(isPow2(extendedNSets) || extendedNSets == 0)\n require(extendedNSets <= nSets)\n require(extendedNSets >= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }\n val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n\n val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })\n val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })\n val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n\n for (w <- 0 until bankWidth) {\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := Mux(\n entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n for (w <- 0 until nWays) {\n when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {\n btb(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wbtb_mask).asBools\n )\n meta(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wmeta_mask).asBools\n )\n\n\n }\n }\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n\n}", + "response": "module meta_1(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [123:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [123:0] W0_data,\n input [3:0] W0_mask\n);\n\n meta_0_ext meta_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleD_a29d64s6k1z4u(\n input clock,\n input reset,\n input io_repeat,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [1:0] io_enq_bits_param,\n input [3:0] io_enq_bits_size,\n input [5:0] io_enq_bits_source,\n input io_enq_bits_sink,\n input io_enq_bits_denied,\n input [63:0] io_enq_bits_data,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [1:0] io_deq_bits_param,\n output [3:0] io_deq_bits_size,\n output [5:0] io_deq_bits_source,\n output io_deq_bits_sink,\n output io_deq_bits_denied,\n output [63:0] io_deq_bits_data,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [1:0] saved_param;\n reg [3:0] saved_size;\n reg [5:0] saved_source;\n reg saved_sink;\n reg saved_denied;\n reg [63:0] saved_data;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_sink <= io_enq_bits_sink;\n saved_denied <= io_enq_bits_denied;\n saved_data <= io_enq_bits_data;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_sink = full ? saved_sink : io_enq_bits_sink;\n assign io_deq_bits_denied = full ? saved_denied : io_enq_bits_denied;\n assign io_deq_bits_data = full ? saved_data : io_enq_bits_data;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRawFN_small_e8_s24(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input io_a_isNaN,\n input io_a_isInf,\n input io_a_isZero,\n input io_a_sign,\n input [9:0] io_a_sExp,\n input [24:0] io_a_sig,\n input io_b_isNaN,\n input io_b_isInf,\n input io_b_isZero,\n input io_b_sign,\n input [9:0] io_b_sExp,\n input [24:0] io_b_sig,\n input [2:0] io_roundingMode,\n output io_rawOutValid_div,\n output io_rawOutValid_sqrt,\n output [2:0] io_roundingModeOut,\n output io_invalidExc,\n output io_infiniteExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [9:0] io_rawOut_sExp,\n output [26:0] io_rawOut_sig\n);\n\n reg [4:0] cycleNum;\n reg inReady;\n reg rawOutValid;\n reg sqrtOp_Z;\n reg majorExc_Z;\n reg isNaN_Z;\n reg isInf_Z;\n reg isZero_Z;\n reg sign_Z;\n reg [9:0] sExp_Z;\n reg [23:0] fractB_Z;\n reg [2:0] roundingMode_Z;\n reg [25:0] rem_Z;\n reg notZeroRem_Z;\n reg [25:0] sigX_Z;\n wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;\n wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);\n wire skipCycle2 = cycleNum == 5'h3 & sigX_Z[25];\n wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;\n wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign;\n wire [10:0] sExpQuot_S_div = {io_a_sExp[9], io_a_sExp} + {{3{io_b_sExp[8]}}, ~(io_b_sExp[7:0])};\n wire [23:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[22:0], 1'h0} : 24'h0;\n wire _fractB_Z_T_10 = inReady & io_sqrtOp;\n wire [31:0] _bitMask_T = 32'h1 << cycleNum;\n wire oddSqrt_S = io_sqrtOp & io_a_sExp[0];\n wire entering = inReady & io_inValid;\n wire _sigX_Z_T_7 = inReady & oddSqrt_S;\n wire [26:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 26'h0} | (_sigX_Z_T_7 ? {io_a_sig[23:22] - 2'h1, io_a_sig[21:0], 3'h0} : 27'h0) | (inReady ? 27'h0 : {rem_Z, 1'h0});\n wire [25:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 26'h0;\n wire [25:0] _trialTerm_T_9 = {_trialTerm_T_3[25], _trialTerm_T_3[24:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 24'h0}} | (_sigX_Z_T_7 ? 26'h2800000 : 26'h0);\n wire [28:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[25], _trialTerm_T_9[24] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[23:0] | (inReady ? 24'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 27'h0)};\n wire newBit = $signed(trialRem) > -29'sh1;\n wire _GEN = entering | ~inReady;\n wire [4:0] _cycleNum_T_15 = {4'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? {4'hC, ~(io_a_sExp[0])} : 5'h1A) : 5'h0) | (entering | skipCycle2 ? 5'h0 : cycleNum - 5'h1);\n wire [25:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 25'h0} : 26'h0;\n wire [24:0] _GEN_0 = _sigX_Z_T_3[24:0] | {inReady & io_sqrtOp, 24'h0};\n always @(posedge clock) begin\n if (reset) begin\n cycleNum <= 5'h0;\n inReady <= 1'h1;\n rawOutValid <= 1'h0;\n end\n else if ((|cycleNum) | entering) begin\n cycleNum <= {_cycleNum_T_15[4:1], _cycleNum_T_15[0] | skipCycle2};\n inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 < 5'h2 | skipCycle2;\n rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 5'h1 == 5'h1 | skipCycle2;\n end\n if (entering) begin\n sqrtOp_Z <= io_sqrtOp;\n majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[22]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[22]) | io_b_isNaN & ~(io_b_sig[22]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;\n isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;\n isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;\n isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;\n sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;\n sExp_Z <= io_sqrtOp ? {io_a_sExp[9], io_a_sExp[9:1]} + 10'h80 : {$signed(sExpQuot_S_div) > 11'sh1BF ? 4'h6 : sExpQuot_S_div[9:6], sExpQuot_S_div[5:0]};\n roundingMode_Z <= io_roundingMode;\n end\n if (entering | ~inReady & sqrtOp_Z)\n fractB_Z <= {_fractB_Z_T_4[23] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[22:0] | {_fractB_Z_T_10 & io_a_sExp[0], 22'h0} | (inReady ? 23'h0 : fractB_Z[23:1])};\n if (_GEN) begin\n rem_Z <= newBit ? trialRem[25:0] : rem[25:0];\n sigX_Z <= {_sigX_Z_T_3[25], _GEN_0[24], _GEN_0[23:0] | (_sigX_Z_T_7 ? {newBit, 23'h0} : 24'h0)} | (inReady ? 26'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[27:2] : 26'h0);\n end\n if (_GEN & (inReady | newBit))\n notZeroRem_Z <= |trialRem;\n end\n assign io_inReady = inReady;\n assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;\n assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;\n assign io_roundingModeOut = roundingMode_Z;\n assign io_invalidExc = majorExc_Z & isNaN_Z;\n assign io_infiniteExc = majorExc_Z & ~isNaN_Z;\n assign io_rawOut_isNaN = isNaN_Z;\n assign io_rawOut_isInf = isInf_Z;\n assign io_rawOut_isZero = isZero_Z;\n assign io_rawOut_sign = sign_Z;\n assign io_rawOut_sExp = sExp_Z;\n assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRecFM_small_e8_s24(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input [32:0] io_a,\n input [32:0] io_b,\n input [2:0] io_roundingMode,\n output io_outValid_div,\n output io_outValid_sqrt,\n output [32:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut;\n wire _divSqrtRecFNToRaw_io_invalidExc;\n wire _divSqrtRecFNToRaw_io_infiniteExc;\n wire _divSqrtRecFNToRaw_io_rawOut_isNaN;\n wire _divSqrtRecFNToRaw_io_rawOut_isInf;\n wire _divSqrtRecFNToRaw_io_rawOut_isZero;\n wire _divSqrtRecFNToRaw_io_rawOut_sign;\n wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp;\n wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig;\n DivSqrtRecFMToRaw_small_e8_s24 divSqrtRecFNToRaw (\n .clock (clock),\n .reset (reset),\n .io_inReady (io_inReady),\n .io_inValid (io_inValid),\n .io_sqrtOp (io_sqrtOp),\n .io_a (io_a),\n .io_b (io_b),\n .io_roundingMode (io_roundingMode),\n .io_rawOutValid_div (io_outValid_div),\n .io_rawOutValid_sqrt (io_outValid_sqrt),\n .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e8_s24 roundRawFNToRecFN (\n .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),\n .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),\n .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),\n .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),\n .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),\n .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign),\n .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),\n .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig),\n .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module array_0_0_0(\n input [8:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [8:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n array_0_0_0_ext array_0_0_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\n\n/** This black-boxes an Async Reset\n * (or Set)\n * Register.\n * \n * Because Chisel doesn't support\n * parameterized black boxes, \n * we unfortunately have to \n * instantiate a number of these.\n * \n * We also have to hard-code the set/\n * reset behavior.\n * \n * Do not confuse an asynchronous\n * reset signal with an asynchronously\n * reset reg. You should still \n * properly synchronize your reset \n * deassertion.\n * \n * @param d Data input\n * @param q Data Output\n * @param clk Clock Input\n * @param rst Reset Input\n * @param en Write Enable Input\n * \n */\n\nclass AsyncResetReg(resetValue: Int = 0) extends RawModule {\n val io = IO(new Bundle {\n val d = Input(Bool())\n val q = Output(Bool())\n val en = Input(Bool())\n\n val clk = Input(Clock())\n val rst = Input(Reset())\n })\n\n val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nclass SimpleRegIO(val w: Int) extends Bundle{\n val d = Input(UInt(w.W))\n val q = Output(UInt(w.W))\n val en = Input(Bool())\n}\n\nclass AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {\n override def desiredName = s\"AsyncResetRegVec_w${w}_i${init}\"\n\n val io = IO(new SimpleRegIO(w))\n\n val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))\n when (io.en) {\n reg := io.d\n }\n io.q := reg\n}\n\nobject AsyncResetReg {\n // Create Single Registers\n def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {\n val reg = Module(new AsyncResetReg(if (init) 1 else 0))\n reg.io.d := d\n reg.io.clk := clk\n reg.io.rst := rst\n reg.io.en := true.B\n name.foreach(reg.suggestName(_))\n reg.io.q\n }\n\n def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)\n def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))\n\n // Create Vectors of Registers\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {\n val w = updateData.getWidth max resetData.bitLength\n val reg = Module(new AsyncResetRegVec(w, resetData))\n name.foreach(reg.suggestName(_))\n reg.io.d := updateData\n reg.io.en := enable\n reg.io.q\n }\n def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,\n resetData, enable, Some(name))\n\n\n def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)\n def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))\n\n def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)\n def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))\n\n def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)\n def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))\n}", + "response": "module AsyncResetRegVec_w1_i1(\n input clock,\n input reset,\n input io_d,\n output io_q,\n input io_en\n);\n\n reg reg_0;\n always @(posedge clock or posedge reset) begin\n if (reset)\n reg_0 <= 1'h1;\n else if (io_en)\n reg_0 <= io_d;\n end\n assign io_q = reg_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module BranchKillableQueue_2(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [6:0] io_enq_bits_uop_uopc,\n input [31:0] io_enq_bits_uop_inst,\n input [31:0] io_enq_bits_uop_debug_inst,\n input io_enq_bits_uop_is_rvc,\n input [39:0] io_enq_bits_uop_debug_pc,\n input [2:0] io_enq_bits_uop_iq_type,\n input [9:0] io_enq_bits_uop_fu_code,\n input [3:0] io_enq_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_uop_ctrl_op_fcn,\n input io_enq_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_uop_ctrl_is_load,\n input io_enq_bits_uop_ctrl_is_sta,\n input io_enq_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_uop_iw_state,\n input io_enq_bits_uop_iw_p1_poisoned,\n input io_enq_bits_uop_iw_p2_poisoned,\n input io_enq_bits_uop_is_br,\n input io_enq_bits_uop_is_jalr,\n input io_enq_bits_uop_is_jal,\n input io_enq_bits_uop_is_sfb,\n input [7:0] io_enq_bits_uop_br_mask,\n input [2:0] io_enq_bits_uop_br_tag,\n input [3:0] io_enq_bits_uop_ftq_idx,\n input io_enq_bits_uop_edge_inst,\n input [5:0] io_enq_bits_uop_pc_lob,\n input io_enq_bits_uop_taken,\n input [19:0] io_enq_bits_uop_imm_packed,\n input [11:0] io_enq_bits_uop_csr_addr,\n input [4:0] io_enq_bits_uop_rob_idx,\n input [2:0] io_enq_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_uop_stq_idx,\n input [1:0] io_enq_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_uop_pdst,\n input [5:0] io_enq_bits_uop_prs1,\n input [5:0] io_enq_bits_uop_prs2,\n input [5:0] io_enq_bits_uop_prs3,\n input [3:0] io_enq_bits_uop_ppred,\n input io_enq_bits_uop_prs1_busy,\n input io_enq_bits_uop_prs2_busy,\n input io_enq_bits_uop_prs3_busy,\n input io_enq_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_uop_stale_pdst,\n input io_enq_bits_uop_exception,\n input [63:0] io_enq_bits_uop_exc_cause,\n input io_enq_bits_uop_bypassable,\n input [4:0] io_enq_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_uop_mem_size,\n input io_enq_bits_uop_mem_signed,\n input io_enq_bits_uop_is_fence,\n input io_enq_bits_uop_is_fencei,\n input io_enq_bits_uop_is_amo,\n input io_enq_bits_uop_uses_ldq,\n input io_enq_bits_uop_uses_stq,\n input io_enq_bits_uop_is_sys_pc2epc,\n input io_enq_bits_uop_is_unique,\n input io_enq_bits_uop_flush_on_commit,\n input io_enq_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_uop_ldst,\n input [5:0] io_enq_bits_uop_lrs1,\n input [5:0] io_enq_bits_uop_lrs2,\n input [5:0] io_enq_bits_uop_lrs3,\n input io_enq_bits_uop_ldst_val,\n input [1:0] io_enq_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_uop_lrs2_rtype,\n input io_enq_bits_uop_frs3_en,\n input io_enq_bits_uop_fp_val,\n input io_enq_bits_uop_fp_single,\n input io_enq_bits_uop_xcpt_pf_if,\n input io_enq_bits_uop_xcpt_ae_if,\n input io_enq_bits_uop_xcpt_ma_if,\n input io_enq_bits_uop_bp_debug_if,\n input io_enq_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_uop_debug_tsrc,\n input [63:0] io_enq_bits_data,\n input io_enq_bits_is_hella,\n input io_deq_ready,\n output io_deq_valid,\n output [7:0] io_deq_bits_uop_br_mask,\n output [2:0] io_deq_bits_uop_ldq_idx,\n output [2:0] io_deq_bits_uop_stq_idx,\n output io_deq_bits_uop_is_amo,\n output io_deq_bits_uop_uses_ldq,\n output io_deq_bits_uop_uses_stq,\n output [63:0] io_deq_bits_data,\n output io_deq_bits_is_hella,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_flush\n);\n\n wire [64:0] _ram_ext_R0_data;\n reg valids_0;\n reg valids_1;\n reg valids_2;\n reg valids_3;\n reg [7:0] uops_0_br_mask;\n reg [2:0] uops_0_ldq_idx;\n reg [2:0] uops_0_stq_idx;\n reg uops_0_is_amo;\n reg uops_0_uses_ldq;\n reg uops_0_uses_stq;\n reg [7:0] uops_1_br_mask;\n reg [2:0] uops_1_ldq_idx;\n reg [2:0] uops_1_stq_idx;\n reg uops_1_is_amo;\n reg uops_1_uses_ldq;\n reg uops_1_uses_stq;\n reg [7:0] uops_2_br_mask;\n reg [2:0] uops_2_ldq_idx;\n reg [2:0] uops_2_stq_idx;\n reg uops_2_is_amo;\n reg uops_2_uses_ldq;\n reg uops_2_uses_stq;\n reg [7:0] uops_3_br_mask;\n reg [2:0] uops_3_ldq_idx;\n reg [2:0] uops_3_stq_idx;\n reg uops_3_is_amo;\n reg uops_3_uses_ldq;\n reg uops_3_uses_stq;\n reg [1:0] enq_ptr_value;\n reg [1:0] deq_ptr_value;\n reg maybe_full;\n wire ptr_match = enq_ptr_value == deq_ptr_value;\n wire io_empty = ptr_match & ~maybe_full;\n wire full = ptr_match & maybe_full;\n wire do_enq = ~full & io_enq_valid;\n wire [3:0] _GEN = {{valids_3}, {valids_2}, {valids_1}, {valids_0}};\n wire _GEN_0 = _GEN[deq_ptr_value];\n wire [3:0][7:0] _GEN_1 = {{uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};\n wire [7:0] out_uop_br_mask = _GEN_1[deq_ptr_value];\n wire [3:0][2:0] _GEN_2 = {{uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}};\n wire [3:0][2:0] _GEN_3 = {{uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};\n wire [3:0] _GEN_4 = {{uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};\n wire [3:0] _GEN_5 = {{uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}};\n wire out_uop_uses_ldq = _GEN_5[deq_ptr_value];\n wire [3:0] _GEN_6 = {{uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};\n wire do_deq = (io_deq_ready | ~_GEN_0) & ~io_empty;\n wire _GEN_7 = enq_ptr_value == 2'h0;\n wire _GEN_8 = do_enq & _GEN_7;\n wire _GEN_9 = enq_ptr_value == 2'h1;\n wire _GEN_10 = do_enq & _GEN_9;\n wire _GEN_11 = enq_ptr_value == 2'h2;\n wire _GEN_12 = do_enq & _GEN_11;\n wire _GEN_13 = do_enq & (&enq_ptr_value);\n wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n valids_0 <= 1'h0;\n valids_1 <= 1'h0;\n valids_2 <= 1'h0;\n valids_3 <= 1'h0;\n enq_ptr_value <= 2'h0;\n deq_ptr_value <= 2'h0;\n maybe_full <= 1'h0;\n end\n else begin\n valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_8 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~(io_flush & uops_0_uses_ldq));\n valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_10 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~(io_flush & uops_1_uses_ldq));\n valids_2 <= ~(do_deq & deq_ptr_value == 2'h2) & (_GEN_12 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~(io_flush & uops_2_uses_ldq));\n valids_3 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_13 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~(io_flush & uops_3_uses_ldq));\n if (do_enq)\n enq_ptr_value <= enq_ptr_value + 2'h1;\n if (do_deq)\n deq_ptr_value <= deq_ptr_value + 2'h1;\n if (~(do_enq == do_deq))\n maybe_full <= do_enq;\n end\n uops_0_br_mask <= do_enq & _GEN_7 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;\n if (_GEN_8) begin\n uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_0_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_0_is_amo <= io_enq_bits_uop_is_amo;\n uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_0_uses_stq <= io_enq_bits_uop_uses_stq;\n end\n uops_1_br_mask <= do_enq & _GEN_9 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;\n if (_GEN_10) begin\n uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_1_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_1_is_amo <= io_enq_bits_uop_is_amo;\n uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_1_uses_stq <= io_enq_bits_uop_uses_stq;\n end\n uops_2_br_mask <= do_enq & _GEN_11 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;\n if (_GEN_12) begin\n uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_2_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_2_is_amo <= io_enq_bits_uop_is_amo;\n uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_2_uses_stq <= io_enq_bits_uop_uses_stq;\n end\n uops_3_br_mask <= do_enq & (&enq_ptr_value) ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;\n if (_GEN_13) begin\n uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx;\n uops_3_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_3_is_amo <= io_enq_bits_uop_is_amo;\n uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq;\n uops_3_uses_stq <= io_enq_bits_uop_uses_stq;\n end\n end\n ram_4x65 ram_ext (\n .R0_addr (deq_ptr_value),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_ram_ext_R0_data),\n .W0_addr (enq_ptr_value),\n .W0_en (do_enq),\n .W0_clk (clock),\n .W0_data ({io_enq_bits_is_hella, io_enq_bits_data})\n );\n assign io_enq_ready = ~full;\n assign io_deq_valid = ~io_empty & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~(io_flush & out_uop_uses_ldq);\n assign io_deq_bits_uop_br_mask = out_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_deq_bits_uop_ldq_idx = _GEN_2[deq_ptr_value];\n assign io_deq_bits_uop_stq_idx = _GEN_3[deq_ptr_value];\n assign io_deq_bits_uop_is_amo = _GEN_4[deq_ptr_value];\n assign io_deq_bits_uop_uses_ldq = out_uop_uses_ldq;\n assign io_deq_bits_uop_uses_stq = _GEN_6[deq_ptr_value];\n assign io_deq_bits_data = _ram_ext_R0_data[63:0];\n assign io_deq_bits_is_hella = _ram_ext_R0_data[64];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Register File (Abstract class and Synthesizable RegFile)\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.ArrayBuffer\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\n/**\n * IO bundle for a register read port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = Input(UInt(addrWidth.W))\n val data = Output(UInt(dataWidth.W))\n}\n\n/**\n * IO bundle for the register write port\n *\n * @param addrWidth size of register address in bits\n * @param dataWidth size of register in bits\n */\nclass RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n{\n val addr = UInt(addrWidth.W)\n val data = UInt(dataWidth.W)\n}\n\n/**\n * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os.\n */\nobject WritePort\n{\n def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt)\n (implicit p: Parameters): Valid[RegisterFileWritePort] = {\n val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth)))\n\n wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype\n wport.bits.addr := enq.bits.uop.pdst\n wport.bits.data := enq.bits.data\n enq.ready := true.B\n wport\n }\n}\n\n/**\n * Register file abstract class\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nabstract class RegisterFile(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports?\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new BoomBundle {\n val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth))\n val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth))))\n })\n\n private val rf_cost = (numReadPorts + numWritePorts) * (numReadPorts + 2*numWritePorts)\n private val type_str = if (registerWidth == fLen+1) \"Floating Point\" else \"Integer\"\n override def toString: String = BoomCoreStringPrefix(\n \"==\" + type_str + \" Regfile==\",\n \"Num RF Read Ports : \" + numReadPorts,\n \"Num RF Write Ports : \" + numWritePorts,\n \"RF Cost (R+W)*(R+2W) : \" + rf_cost,\n \"Bypassable Units : \" + bypassableArray)\n}\n\n/**\n * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts.\n *\n * @param numRegisters number of registers\n * @param numReadPorts number of read ports\n * @param numWritePorts number of write ports\n * @param registerWidth size of registers in bits\n * @param bypassableArray list of write ports from func units to the read port of the regfile\n */\nclass RegisterFileSynthesizable(\n numRegisters: Int,\n numReadPorts: Int,\n numWritePorts: Int,\n registerWidth: Int,\n bypassableArray: Seq[Boolean])\n (implicit p: Parameters)\n extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray)\n{\n // --------------------------------------------------------------\n\n val regfile = Mem(numRegisters, UInt(registerWidth.W))\n\n // --------------------------------------------------------------\n // Read ports.\n\n val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W)))\n\n // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired).\n val read_addrs = io.read_ports.map(p => RegNext(p.addr))\n\n for (i <- 0 until numReadPorts) {\n read_data(i) := regfile(read_addrs(i))\n }\n\n // --------------------------------------------------------------\n // Bypass out of the ALU's write ports.\n // We are assuming we cannot bypass a writer to a reader within the regfile memory\n // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1.\n // But since these bypasses are expensive, and not all write ports need to bypass their data,\n // only perform the w->r bypass on a select number of write ports.\n\n require (bypassableArray.length == io.write_ports.length)\n\n if (bypassableArray.reduce(_||_)) {\n val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]()\n io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} }\n\n for (i <- 0 until numReadPorts) {\n val bypass_ens = bypassable_wports.map(x => x.valid &&\n x.bits.addr === read_addrs(i))\n\n val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq))\n\n io.read_ports(i).data := Mux(bypass_ens.reduce(_|_), bypass_data, read_data(i))\n }\n } else {\n for (i <- 0 until numReadPorts) {\n io.read_ports(i).data := read_data(i)\n }\n }\n\n // --------------------------------------------------------------\n // Write ports.\n\n for (wport <- io.write_ports) {\n when (wport.valid) {\n regfile(wport.bits.addr) := wport.bits.data\n }\n }\n\n // ensure there is only 1 writer per register (unless to preg0)\n if (numWritePorts > 1) {\n for (i <- 0 until (numWritePorts - 1)) {\n for (j <- (i + 1) until numWritePorts) {\n assert(!io.write_ports(i).valid ||\n !io.write_ports(j).valid ||\n (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) ||\n (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here\n \"[regfile] too many writers a register\")\n }\n }\n }\n}", + "response": "module RegisterFileSynthesizable(\n input clock,\n input reset,\n input [5:0] io_read_ports_0_addr,\n output [64:0] io_read_ports_0_data,\n input [5:0] io_read_ports_1_addr,\n output [64:0] io_read_ports_1_data,\n input [5:0] io_read_ports_2_addr,\n output [64:0] io_read_ports_2_data,\n input io_write_ports_0_valid,\n input [5:0] io_write_ports_0_bits_addr,\n input [64:0] io_write_ports_0_bits_data,\n input io_write_ports_1_valid,\n input [5:0] io_write_ports_1_bits_addr,\n input [64:0] io_write_ports_1_bits_data\n);\n\n reg [5:0] read_addrs_0;\n reg [5:0] read_addrs_1;\n reg [5:0] read_addrs_2;\n always @(posedge clock) begin\n read_addrs_0 <= io_read_ports_0_addr;\n read_addrs_1 <= io_read_ports_1_addr;\n read_addrs_2 <= io_read_ports_2_addr;\n end\n regfile_48x65 regfile_ext (\n .R0_addr (read_addrs_2),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (io_read_ports_2_data),\n .R1_addr (read_addrs_1),\n .R1_en (1'h1),\n .R1_clk (clock),\n .R1_data (io_read_ports_1_data),\n .R2_addr (read_addrs_0),\n .R2_en (1'h1),\n .R2_clk (clock),\n .R2_data (io_read_ports_0_data),\n .W0_addr (io_write_ports_1_bits_addr),\n .W0_en (io_write_ports_1_valid),\n .W0_clk (clock),\n .W0_data (io_write_ports_1_bits_data),\n .W1_addr (io_write_ports_0_bits_addr),\n .W1_en (io_write_ports_0_valid),\n .W1_clk (clock),\n .W1_data (io_write_ports_0_bits_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module rockettile_dcache_data_arrays_0(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [511:0] RW0_wdata,\n output [511:0] RW0_rdata,\n input [63:0] RW0_wmask\n);\n\n rockettile_dcache_data_arrays_0_ext rockettile_dcache_data_arrays_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util._\n\n/** Implements the same interface as chisel3.util.Queue, but uses a shift\n * register internally. It is less energy efficient whenever the queue\n * has more than one entry populated, but is faster on the dequeue side.\n * It is efficient for usually-empty flow-through queues. */\nclass ShiftQueue[T <: Data](gen: T,\n val entries: Int,\n pipe: Boolean = false,\n flow: Boolean = false)\n extends Module {\n val io = IO(new QueueIO(gen, entries) {\n val mask = Output(UInt(entries.W))\n })\n\n private val valid = RegInit(VecInit(Seq.fill(entries) { false.B }))\n private val elts = Reg(Vec(entries, gen))\n\n for (i <- 0 until entries) {\n def paddedValid(i: Int) = if (i == -1) true.B else if (i == entries) false.B else valid(i)\n\n val wdata = if (i == entries-1) io.enq.bits else Mux(valid(i+1), elts(i+1), io.enq.bits)\n val wen =\n Mux(io.deq.ready,\n paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)),\n io.enq.fire && paddedValid(i-1) && !valid(i))\n when (wen) { elts(i) := wdata }\n\n valid(i) :=\n Mux(io.deq.ready,\n paddedValid(i+1) || io.enq.fire && ((i == 0 && !flow).B || valid(i)),\n io.enq.fire && paddedValid(i-1) || valid(i))\n }\n\n io.enq.ready := !valid(entries-1)\n io.deq.valid := valid(0)\n io.deq.bits := elts.head\n\n if (flow) {\n when (io.enq.valid) { io.deq.valid := true.B }\n when (!valid(0)) { io.deq.bits := io.enq.bits }\n }\n\n if (pipe) {\n when (io.deq.ready) { io.enq.ready := true.B }\n }\n\n io.mask := valid.asUInt\n io.count := PopCount(io.mask)\n}\n\nobject ShiftQueue\n{\n def apply[T <: Data](enq: DecoupledIO[T], entries: Int = 2, pipe: Boolean = false, flow: Boolean = false): DecoupledIO[T] = {\n val q = Module(new ShiftQueue(enq.bits.cloneType, entries, pipe, flow))\n q.io.enq <> enq\n q.io.deq\n }\n}", + "response": "module ShiftQueue(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input io_enq_bits_btb_taken,\n input io_enq_bits_btb_bridx,\n input [4:0] io_enq_bits_btb_entry,\n input [7:0] io_enq_bits_btb_bht_history,\n input [39:0] io_enq_bits_pc,\n input [31:0] io_enq_bits_data,\n input io_enq_bits_xcpt_pf_inst,\n input io_enq_bits_xcpt_ae_inst,\n input io_enq_bits_replay,\n input io_deq_ready,\n output io_deq_valid,\n output io_deq_bits_btb_taken,\n output io_deq_bits_btb_bridx,\n output [4:0] io_deq_bits_btb_entry,\n output [7:0] io_deq_bits_btb_bht_history,\n output [39:0] io_deq_bits_pc,\n output [31:0] io_deq_bits_data,\n output io_deq_bits_xcpt_pf_inst,\n output io_deq_bits_xcpt_gf_inst,\n output io_deq_bits_xcpt_ae_inst,\n output io_deq_bits_replay,\n output [4:0] io_mask\n);\n\n reg valid_0;\n reg valid_1;\n reg valid_2;\n reg valid_3;\n reg valid_4;\n reg elts_0_btb_taken;\n reg elts_0_btb_bridx;\n reg [4:0] elts_0_btb_entry;\n reg [7:0] elts_0_btb_bht_history;\n reg [39:0] elts_0_pc;\n reg [31:0] elts_0_data;\n reg elts_0_xcpt_pf_inst;\n reg elts_0_xcpt_gf_inst;\n reg elts_0_xcpt_ae_inst;\n reg elts_0_replay;\n reg elts_1_btb_taken;\n reg elts_1_btb_bridx;\n reg [4:0] elts_1_btb_entry;\n reg [7:0] elts_1_btb_bht_history;\n reg [39:0] elts_1_pc;\n reg [31:0] elts_1_data;\n reg elts_1_xcpt_pf_inst;\n reg elts_1_xcpt_gf_inst;\n reg elts_1_xcpt_ae_inst;\n reg elts_1_replay;\n reg elts_2_btb_taken;\n reg elts_2_btb_bridx;\n reg [4:0] elts_2_btb_entry;\n reg [7:0] elts_2_btb_bht_history;\n reg [39:0] elts_2_pc;\n reg [31:0] elts_2_data;\n reg elts_2_xcpt_pf_inst;\n reg elts_2_xcpt_gf_inst;\n reg elts_2_xcpt_ae_inst;\n reg elts_2_replay;\n reg elts_3_btb_taken;\n reg elts_3_btb_bridx;\n reg [4:0] elts_3_btb_entry;\n reg [7:0] elts_3_btb_bht_history;\n reg [39:0] elts_3_pc;\n reg [31:0] elts_3_data;\n reg elts_3_xcpt_pf_inst;\n reg elts_3_xcpt_gf_inst;\n reg elts_3_xcpt_ae_inst;\n reg elts_3_replay;\n reg elts_4_btb_taken;\n reg elts_4_btb_bridx;\n reg [4:0] elts_4_btb_entry;\n reg [7:0] elts_4_btb_bht_history;\n reg [39:0] elts_4_pc;\n reg [31:0] elts_4_data;\n reg elts_4_xcpt_pf_inst;\n reg elts_4_xcpt_gf_inst;\n reg elts_4_xcpt_ae_inst;\n reg elts_4_replay;\n wire _valid_4_T_4 = ~valid_4 & io_enq_valid;\n wire wen_4 = io_deq_ready ? _valid_4_T_4 & valid_4 : _valid_4_T_4 & valid_3;\n always @(posedge clock) begin\n if (reset) begin\n valid_0 <= 1'h0;\n valid_1 <= 1'h0;\n valid_2 <= 1'h0;\n valid_3 <= 1'h0;\n valid_4 <= 1'h0;\n end\n else begin\n valid_0 <= io_deq_ready ? valid_1 | _valid_4_T_4 & valid_0 : _valid_4_T_4 | valid_0;\n valid_1 <= io_deq_ready ? valid_2 | _valid_4_T_4 & valid_1 : _valid_4_T_4 & valid_0 | valid_1;\n valid_2 <= io_deq_ready ? valid_3 | _valid_4_T_4 & valid_2 : _valid_4_T_4 & valid_1 | valid_2;\n valid_3 <= io_deq_ready ? valid_4 | _valid_4_T_4 & valid_3 : _valid_4_T_4 & valid_2 | valid_3;\n valid_4 <= io_deq_ready ? _valid_4_T_4 & valid_4 : _valid_4_T_4 & valid_3 | valid_4;\n end\n if (io_deq_ready ? valid_1 | _valid_4_T_4 & valid_0 : _valid_4_T_4 & ~valid_0) begin\n elts_0_btb_taken <= valid_1 ? elts_1_btb_taken : io_enq_bits_btb_taken;\n elts_0_btb_bridx <= valid_1 ? elts_1_btb_bridx : io_enq_bits_btb_bridx;\n elts_0_btb_entry <= valid_1 ? elts_1_btb_entry : io_enq_bits_btb_entry;\n elts_0_btb_bht_history <= valid_1 ? elts_1_btb_bht_history : io_enq_bits_btb_bht_history;\n elts_0_pc <= valid_1 ? elts_1_pc : io_enq_bits_pc;\n elts_0_data <= valid_1 ? elts_1_data : io_enq_bits_data;\n elts_0_xcpt_pf_inst <= valid_1 ? elts_1_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;\n elts_0_xcpt_gf_inst <= valid_1 & elts_1_xcpt_gf_inst;\n elts_0_xcpt_ae_inst <= valid_1 ? elts_1_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;\n elts_0_replay <= valid_1 ? elts_1_replay : io_enq_bits_replay;\n end\n if (io_deq_ready ? valid_2 | _valid_4_T_4 & valid_1 : _valid_4_T_4 & valid_0 & ~valid_1) begin\n elts_1_btb_taken <= valid_2 ? elts_2_btb_taken : io_enq_bits_btb_taken;\n elts_1_btb_bridx <= valid_2 ? elts_2_btb_bridx : io_enq_bits_btb_bridx;\n elts_1_btb_entry <= valid_2 ? elts_2_btb_entry : io_enq_bits_btb_entry;\n elts_1_btb_bht_history <= valid_2 ? elts_2_btb_bht_history : io_enq_bits_btb_bht_history;\n elts_1_pc <= valid_2 ? elts_2_pc : io_enq_bits_pc;\n elts_1_data <= valid_2 ? elts_2_data : io_enq_bits_data;\n elts_1_xcpt_pf_inst <= valid_2 ? elts_2_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;\n elts_1_xcpt_gf_inst <= valid_2 & elts_2_xcpt_gf_inst;\n elts_1_xcpt_ae_inst <= valid_2 ? elts_2_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;\n elts_1_replay <= valid_2 ? elts_2_replay : io_enq_bits_replay;\n end\n if (io_deq_ready ? valid_3 | _valid_4_T_4 & valid_2 : _valid_4_T_4 & valid_1 & ~valid_2) begin\n elts_2_btb_taken <= valid_3 ? elts_3_btb_taken : io_enq_bits_btb_taken;\n elts_2_btb_bridx <= valid_3 ? elts_3_btb_bridx : io_enq_bits_btb_bridx;\n elts_2_btb_entry <= valid_3 ? elts_3_btb_entry : io_enq_bits_btb_entry;\n elts_2_btb_bht_history <= valid_3 ? elts_3_btb_bht_history : io_enq_bits_btb_bht_history;\n elts_2_pc <= valid_3 ? elts_3_pc : io_enq_bits_pc;\n elts_2_data <= valid_3 ? elts_3_data : io_enq_bits_data;\n elts_2_xcpt_pf_inst <= valid_3 ? elts_3_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;\n elts_2_xcpt_gf_inst <= valid_3 & elts_3_xcpt_gf_inst;\n elts_2_xcpt_ae_inst <= valid_3 ? elts_3_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;\n elts_2_replay <= valid_3 ? elts_3_replay : io_enq_bits_replay;\n end\n if (io_deq_ready ? valid_4 | _valid_4_T_4 & valid_3 : _valid_4_T_4 & valid_2 & ~valid_3) begin\n elts_3_btb_taken <= valid_4 ? elts_4_btb_taken : io_enq_bits_btb_taken;\n elts_3_btb_bridx <= valid_4 ? elts_4_btb_bridx : io_enq_bits_btb_bridx;\n elts_3_btb_entry <= valid_4 ? elts_4_btb_entry : io_enq_bits_btb_entry;\n elts_3_btb_bht_history <= valid_4 ? elts_4_btb_bht_history : io_enq_bits_btb_bht_history;\n elts_3_pc <= valid_4 ? elts_4_pc : io_enq_bits_pc;\n elts_3_data <= valid_4 ? elts_4_data : io_enq_bits_data;\n elts_3_xcpt_pf_inst <= valid_4 ? elts_4_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;\n elts_3_xcpt_gf_inst <= valid_4 & elts_4_xcpt_gf_inst;\n elts_3_xcpt_ae_inst <= valid_4 ? elts_4_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;\n elts_3_replay <= valid_4 ? elts_4_replay : io_enq_bits_replay;\n end\n if (wen_4) begin\n elts_4_btb_taken <= io_enq_bits_btb_taken;\n elts_4_btb_bridx <= io_enq_bits_btb_bridx;\n elts_4_btb_entry <= io_enq_bits_btb_entry;\n elts_4_btb_bht_history <= io_enq_bits_btb_bht_history;\n elts_4_pc <= io_enq_bits_pc;\n elts_4_data <= io_enq_bits_data;\n elts_4_xcpt_pf_inst <= io_enq_bits_xcpt_pf_inst;\n elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;\n elts_4_replay <= io_enq_bits_replay;\n end\n elts_4_xcpt_gf_inst <= ~wen_4 & elts_4_xcpt_gf_inst;\n end\n assign io_enq_ready = ~valid_4;\n assign io_deq_valid = io_enq_valid | valid_0;\n assign io_deq_bits_btb_taken = valid_0 ? elts_0_btb_taken : io_enq_bits_btb_taken;\n assign io_deq_bits_btb_bridx = valid_0 ? elts_0_btb_bridx : io_enq_bits_btb_bridx;\n assign io_deq_bits_btb_entry = valid_0 ? elts_0_btb_entry : io_enq_bits_btb_entry;\n assign io_deq_bits_btb_bht_history = valid_0 ? elts_0_btb_bht_history : io_enq_bits_btb_bht_history;\n assign io_deq_bits_pc = valid_0 ? elts_0_pc : io_enq_bits_pc;\n assign io_deq_bits_data = valid_0 ? elts_0_data : io_enq_bits_data;\n assign io_deq_bits_xcpt_pf_inst = valid_0 ? elts_0_xcpt_pf_inst : io_enq_bits_xcpt_pf_inst;\n assign io_deq_bits_xcpt_gf_inst = valid_0 & elts_0_xcpt_gf_inst;\n assign io_deq_bits_xcpt_ae_inst = valid_0 ? elts_0_xcpt_ae_inst : io_enq_bits_xcpt_ae_inst;\n assign io_deq_bits_replay = valid_0 ? elts_0_replay : io_enq_bits_replay;\n assign io_mask = {valid_4, valid_3, valid_2, valid_1, valid_0};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLCFromBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Functional Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// If regfile bypassing is disabled, then the functional unit must do its own\n// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)\n//\n// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tile\nimport freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}\n\nimport boom.v3.common._\nimport boom.v3.ifu._\nimport boom.v3.util._\n\n/**t\n * Functional unit constants\n */\nobject FUConstants\n{\n // bit mask, since a given execution pipeline may support multiple functional units\n val FUC_SZ = 10\n val FU_X = BitPat.dontCare(FUC_SZ)\n val FU_ALU = 1.U(FUC_SZ.W)\n val FU_JMP = 2.U(FUC_SZ.W)\n val FU_MEM = 4.U(FUC_SZ.W)\n val FU_MUL = 8.U(FUC_SZ.W)\n val FU_DIV = 16.U(FUC_SZ.W)\n val FU_CSR = 32.U(FUC_SZ.W)\n val FU_FPU = 64.U(FUC_SZ.W)\n val FU_FDV = 128.U(FUC_SZ.W)\n val FU_I2F = 256.U(FUC_SZ.W)\n val FU_F2I = 512.U(FUC_SZ.W)\n\n // FP stores generate data through FP F2I, and generate address through MemAddrCalc\n val FU_F2IMEM = 516.U(FUC_SZ.W)\n}\nimport FUConstants._\n\n/**\n * Class to tell the FUDecoders what units it needs to support\n *\n * @param alu support alu unit?\n * @param bru support br unit?\n * @param mem support mem unit?\n * @param muld support multiple div unit?\n * @param fpu support FP unit?\n * @param csr support csr writing unit?\n * @param fdiv support FP div unit?\n * @param ifpu support int to FP unit?\n */\nclass SupportedFuncUnits(\n val alu: Boolean = false,\n val jmp: Boolean = false,\n val mem: Boolean = false,\n val muld: Boolean = false,\n val fpu: Boolean = false,\n val csr: Boolean = false,\n val fdiv: Boolean = false,\n val ifpu: Boolean = false)\n{\n}\n\n\n/**\n * Bundle for signals sent to the functional unit\n *\n * @param dataWidth width of the data sent to the functional unit\n */\nclass FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val numOperands = 3\n\n val rs1_data = UInt(dataWidth.W)\n val rs2_data = UInt(dataWidth.W)\n val rs3_data = UInt(dataWidth.W) // only used for FMA units\n val pred_data = Bool()\n\n val kill = Bool() // kill everything\n}\n\n/**\n * Bundle for the signals sent out of the function unit\n *\n * @param dataWidth data sent from the functional unit\n */\nclass FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val predicated = Bool() // Was this response from a predicated-off instruction\n val data = UInt(dataWidth.W)\n val fflags = new ValidIO(new FFlagsResp)\n val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU\n val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU\n val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc\n}\n\n/**\n * Branch resolution information given from the branch unit\n */\nclass BrResolutionInfo(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp\n val valid = Bool()\n val mispredict = Bool()\n val taken = Bool() // which direction did the branch go?\n val cfi_type = UInt(CFI_SZ.W)\n\n // Info for recalculating the pc for this branch\n val pc_sel = UInt(2.W)\n\n val jalr_target = UInt(vaddrBitsExtended.W)\n val target_offset = SInt()\n}\n\nclass BrUpdateInfo(implicit p: Parameters) extends BoomBundle\n{\n // On the first cycle we get masks to kill registers\n val b1 = new BrUpdateMasks\n // On the second cycle we get indices to reset pointers\n val b2 = new BrResolutionInfo\n}\n\nclass BrUpdateMasks(implicit p: Parameters) extends BoomBundle\n{\n val resolve_mask = UInt(maxBrCount.W)\n val mispredict_mask = UInt(maxBrCount.W)\n}\n\n\n/**\n * Abstract top level functional unit class that wraps a lower level hand made functional unit\n *\n * @param isPipelined is the functional unit pipelined?\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class FunctionalUnit(\n val isPipelined: Boolean,\n val numStages: Int,\n val numBypassStages: Int,\n val dataWidth: Int,\n val isJmpUnit: Boolean = false,\n val isAluUnit: Boolean = false,\n val isMemAddrCalcUnit: Boolean = false,\n val needsFcsr: Boolean = false)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))\n\n val brupdate = Input(new BrUpdateInfo())\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n\n // only used by the fpu unit\n val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by branch unit\n val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null\n\n // only used by memaddr calc unit\n val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null\n\n })\n\n io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }\n\n io.resp.valid := false.B\n io.resp.bits := DontCare\n\n if (isJmpUnit) {\n io.get_ftq_pc.ftq_idx := DontCare\n }\n}\n\n/**\n * Abstract top level pipelined functional unit\n *\n * Note: this helps track which uops get killed while in intermediate stages,\n * but it is the job of the consumer to check for kills on the same cycle as consumption!!!\n *\n * @param numStages how many pipeline stages does the functional unit have\n * @param numBypassStages how many bypass stages does the function unit have\n * @param earliestBypassStage first stage that you can start bypassing from\n * @param dataWidth width of the data being operated on in the functional unit\n * @param hasBranchUnit does this functional unit have a branch unit?\n */\nabstract class PipelinedFunctionalUnit(\n numStages: Int,\n numBypassStages: Int,\n earliestBypassStage: Int,\n dataWidth: Int,\n isJmpUnit: Boolean = false,\n isAluUnit: Boolean = false,\n isMemAddrCalcUnit: Boolean = false,\n needsFcsr: Boolean = false\n )(implicit p: Parameters) extends FunctionalUnit(\n isPipelined = true,\n numStages = numStages,\n numBypassStages = numBypassStages,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit,\n isAluUnit = isAluUnit,\n isMemAddrCalcUnit = isMemAddrCalcUnit,\n needsFcsr = needsFcsr)\n{\n // Pipelined functional unit is always ready.\n io.req.ready := true.B\n\n if (numStages > 0) {\n val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_uops = Reg(Vec(numStages, new MicroOp()))\n\n // handle incoming request\n r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill\n r_uops(0) := io.req.bits.uop\n r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n\n // handle middle of the pipeline\n for (i <- 1 until numStages) {\n r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill\n r_uops(i) := r_uops(i-1)\n r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))\n\n if (numBypassStages > 0) {\n io.bypass(i-1).bits.uop := r_uops(i-1)\n }\n }\n\n // handle outgoing (branch could still kill it)\n // consumer must also check for pipeline flushes (kills)\n io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := r_uops(numStages-1)\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))\n\n // bypassing (TODO allow bypass vector to have a different size from numStages)\n if (numBypassStages > 0 && earliestBypassStage == 0) {\n io.bypass(0).bits.uop := io.req.bits.uop\n\n for (i <- 1 until numBypassStages) {\n io.bypass(i).bits.uop := r_uops(i-1)\n }\n }\n } else {\n require (numStages == 0)\n // pass req straight through to response\n\n // valid doesn't check kill signals, let consumer deal with it.\n // The LSU already handles it and this hurts critical path.\n io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n io.resp.bits.predicated := false.B\n io.resp.bits.uop := io.req.bits.uop\n io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n }\n}\n\n/**\n * Functional unit that wraps RocketChips ALU\n *\n * @param isBranchUnit is this a branch unit?\n * @param numStages how many pipeline stages does the functional unit have\n * @param dataWidth width of the data being operated on in the functional unit\n */\nclass ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = numStages,\n isAluUnit = true,\n earliestBypassStage = 0,\n dataWidth = dataWidth,\n isJmpUnit = isJmpUnit)\n with boom.v3.ifu.HasBoomFrontendParameters\n{\n val uop = io.req.bits.uop\n\n // immediate generation\n val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)\n\n // operand 1 select\n var op1_data: UInt = null\n if (isJmpUnit) {\n // Get the uop PC for jumps\n val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)\n val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)\n\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),\n 0.U))\n } else {\n op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,\n 0.U)\n }\n\n // operand 2 select\n val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),\n Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),\n Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,\n Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),\n 0.U))))\n\n val alu = Module(new freechips.rocketchip.rocket.ALU())\n\n alu.io.in1 := op1_data.asUInt\n alu.io.in2 := op2_data.asUInt\n alu.io.fn := uop.ctrl.op_fcn\n alu.io.dw := uop.ctrl.fcn_dw\n\n\n // Did I just get killed by the previous cycle's branch,\n // or by a flush pipeline?\n val killed = WireInit(false.B)\n when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {\n killed := true.B\n }\n\n val rs1 = io.req.bits.rs1_data\n val rs2 = io.req.bits.rs2_data\n val br_eq = (rs1 === rs2)\n val br_ltu = (rs1.asUInt < rs2.asUInt)\n val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |\n rs1(xLen-1) & ~rs2(xLen-1)).asBool\n\n val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(\n Seq( BR_N -> PC_PLUS4,\n BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),\n BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),\n BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),\n BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),\n BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),\n BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),\n BR_J -> PC_BRJMP,\n BR_JR -> PC_JALR\n ))\n\n val is_taken = io.req.valid &&\n !killed &&\n (uop.is_br || uop.is_jalr || uop.is_jal) &&\n (pc_sel =/= PC_PLUS4)\n\n // \"mispredict\" means that a branch has been resolved and it must be killed\n val mispredict = WireInit(false.B)\n\n val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb\n val is_jal = io.req.valid && !killed && uop.is_jal\n val is_jalr = io.req.valid && !killed && uop.is_jalr\n\n when (is_br || is_jalr) {\n if (!isJmpUnit) {\n assert (pc_sel =/= PC_JALR)\n }\n when (pc_sel === PC_PLUS4) {\n mispredict := uop.taken\n }\n when (pc_sel === PC_BRJMP) {\n mispredict := !uop.taken\n }\n }\n\n val brinfo = Wire(new BrResolutionInfo)\n\n // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit\n brinfo.valid := is_br || is_jalr\n brinfo.mispredict := mispredict\n brinfo.uop := uop\n brinfo.cfi_type := Mux(is_jalr, CFI_JALR,\n Mux(is_br , CFI_BR, CFI_X))\n brinfo.taken := is_taken\n brinfo.pc_sel := pc_sel\n\n brinfo.jalr_target := DontCare\n\n\n // Branch/Jump Target Calculation\n // For jumps we read the FTQ, and can calculate the target\n // For branches we emit the offset for the core to redirect if necessary\n val target_offset = imm_xprlen(20,0).asSInt\n brinfo.jalr_target := DontCare\n if (isJmpUnit) {\n def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {\n ea\n } else {\n // Efficient means to compress 64-bit VA into vaddrBits+1 bits.\n // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).\n val a = a0.asSInt >> vaddrBits\n val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))\n Cat(msb, ea(vaddrBits-1,0))\n }\n\n\n val jalr_target_base = io.req.bits.rs1_data.asSInt\n val jalr_target_xlen = Wire(UInt(xLen.W))\n jalr_target_xlen := (jalr_target_base + target_offset).asUInt\n val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt\n\n brinfo.jalr_target := jalr_target\n val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)\n\n when (pc_sel === PC_JALR) {\n mispredict := !io.get_ftq_pc.next_val ||\n (io.get_ftq_pc.next_pc =/= jalr_target) ||\n !io.get_ftq_pc.entry.cfi_idx.valid ||\n (io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)\n }\n }\n\n brinfo.target_offset := target_offset\n\n\n io.brinfo := brinfo\n\n\n\n// Response\n// TODO add clock gate on resp bits from functional units\n// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)\n// val reg_data = Reg(outType = Bits(width = xLen))\n// reg_data := alu.io.out\n// io.resp.bits.data := reg_data\n\n val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))\n val r_data = Reg(Vec(numStages, UInt(xLen.W)))\n val r_pred = Reg(Vec(numStages, Bool()))\n val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,\n Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),\n Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))\n r_val (0) := io.req.valid\n r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data\n for (i <- 1 until numStages) {\n r_val(i) := r_val(i-1)\n r_data(i) := r_data(i-1)\n r_pred(i) := r_pred(i-1)\n }\n io.resp.bits.data := r_data(numStages-1)\n io.resp.bits.predicated := r_pred(numStages-1)\n // Bypass\n // for the ALU, we can bypass same cycle as compute\n require (numStages >= 1)\n require (numBypassStages >= 1)\n io.bypass(0).valid := io.req.valid\n io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)\n for (i <- 1 until numStages) {\n io.bypass(i).valid := r_val(i-1)\n io.bypass(i).bits.data := r_data(i-1)\n }\n\n // Exceptions\n io.resp.bits.fflags.valid := false.B\n}\n\n/**\n * Functional unit that passes in base+imm to calculate addresses, and passes store data\n * to the LSU.\n * For floating point, 65bit FP store-data needs to be decoded into 64bit FP form\n */\nclass MemAddrCalcUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = 0,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65, // TODO enable this only if FP is enabled?\n isMemAddrCalcUnit = true)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n with freechips.rocketchip.rocket.constants.ScalarOpConstants\n{\n // perform address calculation\n val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt\n val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,\n sum(63,vaddrBits) =/= 0.U)\n val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt\n\n val store_data = io.req.bits.rs2_data\n\n io.resp.bits.addr := effective_address\n io.resp.bits.data := store_data\n\n if (dataWidth > 63) {\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&\n io.resp.bits.data(64).asBool === true.B), \"65th bit set in MemAddrCalcUnit.\")\n\n assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),\n \"FP store-data should now be going through a different unit.\")\n }\n\n assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=\n uopLD && io.req.bits.uop.uopc =/= uopSTA),\n \"[maddrcalc] assert we never get store data in here.\")\n\n // Handle misaligned exceptions\n val size = io.req.bits.uop.mem_size\n val misaligned =\n (size === 1.U && (effective_address(0) =/= 0.U)) ||\n (size === 2.U && (effective_address(1,0) =/= 0.U)) ||\n (size === 3.U && (effective_address(2,0) =/= 0.U))\n\n val bkptu = Module(new BreakpointUnit(nBreakpoints))\n bkptu.io.status := io.status\n bkptu.io.bp := io.bp\n bkptu.io.pc := DontCare\n bkptu.io.ea := effective_address\n bkptu.io.mcontext := io.mcontext\n bkptu.io.scontext := io.scontext\n\n val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned\n val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned\n val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))\n val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||\n (io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n val (xcpt_val, xcpt_cause) = checkExceptions(List(\n (ma_ld, (Causes.misaligned_load).U),\n (ma_st, (Causes.misaligned_store).U),\n (dbg_bp, (CSR.debugTriggerCause).U),\n (bp, (Causes.breakpoint).U)))\n\n io.resp.bits.mxcpt.valid := xcpt_val\n io.resp.bits.mxcpt.bits := xcpt_cause\n assert (!(ma_ld && ma_st), \"Mutually-exclusive exceptions are firing.\")\n\n io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE\n io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)\n io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)\n io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data\n io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data\n}\n\n\n/**\n * Functional unit to wrap lower level FPU\n *\n * Currently, bypassing is unsupported!\n * All FP instructions are padded out to the max latency unit for easy\n * write-port scheduling.\n */\nclass FPUUnit(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n{\n val fpu = Module(new FPU())\n fpu.io.req.valid := io.req.valid\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.fcsr_rm := io.fcsr_rm\n\n io.resp.bits.data := fpu.io.resp.bits.data\n io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now\n}\n\n/**\n * Int to FP conversion functional unit\n *\n * @param latency the amount of stages to delay by\n */\nclass IntToFPUnit(latency: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = latency,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = 65,\n needsFcsr = true)\n with tile.HasFPUParameters\n{\n val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder\n val io_req = io.req.bits\n fp_decoder.io.uopc := io_req.uop.uopc\n val fp_ctrl = fp_decoder.io.sigs\n val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))\n val req = Wire(new tile.FPInput)\n val tag = fp_ctrl.typeTagIn\n\n req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl\n\n req.rm := fp_rm\n req.in1 := unbox(io_req.rs1_data, tag, None)\n req.in2 := unbox(io_req.rs2_data, tag, None)\n req.in3 := DontCare\n req.typ := ImmGenTyp(io_req.uop.imm_packed)\n req.fmt := DontCare // FIXME: this may not be the right thing to do here\n req.fmaCmd := DontCare\n\n assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),\n \"[func] IntToFP integer input has 65th high-order bit set!\")\n\n assert (!(io.req.valid && !fp_ctrl.fromint),\n \"[func] Only support fromInt micro-ops.\")\n\n val ifpu = Module(new tile.IntToFP(intToFpLatency))\n ifpu.io.in.valid := io.req.valid\n ifpu.io.in.bits := req\n ifpu.io.in.bits.in1 := io_req.rs1_data\n val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits\n\n//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)\n io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)\n io.resp.bits.fflags.valid := ifpu.io.out.valid\n io.resp.bits.fflags.bits.uop := io.resp.bits.uop\n io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc\n}\n\n/**\n * Iterative/unpipelined functional unit, can only hold a single MicroOp at a time\n * assumes at least one register between request and response\n *\n * TODO allow up to N micro-ops simultaneously.\n *\n * @param dataWidth width of the data to be passed into the functional unit\n */\nabstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)\n extends FunctionalUnit(\n isPipelined = false,\n numStages = 1,\n numBypassStages = 0,\n dataWidth = dataWidth)\n{\n val r_uop = Reg(new MicroOp())\n\n val do_kill = Wire(Bool())\n do_kill := io.req.bits.kill // irrelevant default\n\n when (io.req.fire) {\n // update incoming uop\n do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill\n r_uop := io.req.bits.uop\n r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n } .otherwise {\n do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill\n r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)\n }\n\n // assumes at least one pipeline register between request and response\n io.resp.bits.uop := r_uop\n}\n\n/**\n * Divide functional unit.\n *\n * @param dataWidth data to be passed into the functional unit\n */\nclass DivUnit(dataWidth: Int)(implicit p: Parameters)\n extends IterativeFunctionalUnit(dataWidth)\n{\n\n // We don't use the iterative multiply functionality here.\n // Instead we use the PipelinedMultiplier\n val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))\n\n // request\n div.io.req.valid := io.req.valid && !this.do_kill\n div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n div.io.req.bits.in1 := io.req.bits.rs1_data\n div.io.req.bits.in2 := io.req.bits.rs2_data\n div.io.req.bits.tag := DontCare\n io.req.ready := div.io.req.ready\n\n // handle pipeline kills and branch misspeculations\n div.io.kill := this.do_kill\n\n // response\n io.resp.valid := div.io.resp.valid && !this.do_kill\n div.io.resp.ready := io.resp.ready\n io.resp.bits.data := div.io.resp.bits.data\n}\n\n/**\n * Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier\n *\n * @param numStages number of pipeline stages\n * @param dataWidth size of the data being passed into the functional unit\n */\nclass PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)\n extends PipelinedFunctionalUnit(\n numStages = numStages,\n numBypassStages = 0,\n earliestBypassStage = 0,\n dataWidth = dataWidth)\n{\n val imul = Module(new PipelinedMultiplier(xLen, numStages))\n // request\n imul.io.req.valid := io.req.valid\n imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn\n imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw\n imul.io.req.bits.in1 := io.req.bits.rs1_data\n imul.io.req.bits.in2 := io.req.bits.rs2_data\n imul.io.req.bits.tag := DontCare\n // response\n io.resp.bits.data := imul.io.resp.bits.data\n}", + "response": "module PipelinedMulUnit(\n input clock,\n input reset,\n input io_req_valid,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [7:0] io_req_bits_uop_br_mask,\n input [4:0] io_req_bits_uop_rob_idx,\n input [5:0] io_req_bits_uop_pdst,\n input io_req_bits_uop_bypassable,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_stq,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [63:0] io_req_bits_rs1_data,\n input [63:0] io_req_bits_rs2_data,\n input io_req_bits_kill,\n output io_resp_valid,\n output [4:0] io_resp_bits_uop_rob_idx,\n output [5:0] io_resp_bits_uop_pdst,\n output io_resp_bits_uop_bypassable,\n output io_resp_bits_uop_is_amo,\n output io_resp_bits_uop_uses_stq,\n output [1:0] io_resp_bits_uop_dst_rtype,\n output [63:0] io_resp_bits_data,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask\n);\n\n reg r_valids_0;\n reg r_valids_1;\n reg r_valids_2;\n reg [7:0] r_uops_0_br_mask;\n reg [4:0] r_uops_0_rob_idx;\n reg [5:0] r_uops_0_pdst;\n reg r_uops_0_bypassable;\n reg r_uops_0_is_amo;\n reg r_uops_0_uses_stq;\n reg [1:0] r_uops_0_dst_rtype;\n reg [7:0] r_uops_1_br_mask;\n reg [4:0] r_uops_1_rob_idx;\n reg [5:0] r_uops_1_pdst;\n reg r_uops_1_bypassable;\n reg r_uops_1_is_amo;\n reg r_uops_1_uses_stq;\n reg [1:0] r_uops_1_dst_rtype;\n reg [7:0] r_uops_2_br_mask;\n reg [4:0] r_uops_2_rob_idx;\n reg [5:0] r_uops_2_pdst;\n reg r_uops_2_bypassable;\n reg r_uops_2_is_amo;\n reg r_uops_2_uses_stq;\n reg [1:0] r_uops_2_dst_rtype;\n always @(posedge clock) begin\n if (reset) begin\n r_valids_0 <= 1'h0;\n r_valids_1 <= 1'h0;\n r_valids_2 <= 1'h0;\n end\n else begin\n r_valids_0 <= io_req_valid & (io_brupdate_b1_mispredict_mask & io_req_bits_uop_br_mask) == 8'h0 & ~io_req_bits_kill;\n r_valids_1 <= r_valids_0 & (io_brupdate_b1_mispredict_mask & r_uops_0_br_mask) == 8'h0 & ~io_req_bits_kill;\n r_valids_2 <= r_valids_1 & (io_brupdate_b1_mispredict_mask & r_uops_1_br_mask) == 8'h0 & ~io_req_bits_kill;\n end\n r_uops_0_br_mask <= io_req_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_0_rob_idx <= io_req_bits_uop_rob_idx;\n r_uops_0_pdst <= io_req_bits_uop_pdst;\n r_uops_0_bypassable <= io_req_bits_uop_bypassable;\n r_uops_0_is_amo <= io_req_bits_uop_is_amo;\n r_uops_0_uses_stq <= io_req_bits_uop_uses_stq;\n r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype;\n r_uops_1_br_mask <= r_uops_0_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_1_rob_idx <= r_uops_0_rob_idx;\n r_uops_1_pdst <= r_uops_0_pdst;\n r_uops_1_bypassable <= r_uops_0_bypassable;\n r_uops_1_is_amo <= r_uops_0_is_amo;\n r_uops_1_uses_stq <= r_uops_0_uses_stq;\n r_uops_1_dst_rtype <= r_uops_0_dst_rtype;\n r_uops_2_br_mask <= r_uops_1_br_mask & ~io_brupdate_b1_resolve_mask;\n r_uops_2_rob_idx <= r_uops_1_rob_idx;\n r_uops_2_pdst <= r_uops_1_pdst;\n r_uops_2_bypassable <= r_uops_1_bypassable;\n r_uops_2_is_amo <= r_uops_1_is_amo;\n r_uops_2_uses_stq <= r_uops_1_uses_stq;\n r_uops_2_dst_rtype <= r_uops_1_dst_rtype;\n end\n PipelinedMultiplier imul (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid),\n .io_req_bits_fn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_in1 (io_req_bits_rs1_data),\n .io_req_bits_in2 (io_req_bits_rs2_data),\n .io_resp_bits_data (io_resp_bits_data)\n );\n assign io_resp_valid = r_valids_2 & (io_brupdate_b1_mispredict_mask & r_uops_2_br_mask) == 8'h0;\n assign io_resp_bits_uop_rob_idx = r_uops_2_rob_idx;\n assign io_resp_bits_uop_pdst = r_uops_2_pdst;\n assign io_resp_bits_uop_bypassable = r_uops_2_bypassable;\n assign io_resp_bits_uop_is_amo = r_uops_2_is_amo;\n assign io_resp_bits_uop_uses_stq = r_uops_2_uses_stq;\n assign io_resp_bits_uop_dst_rtype = r_uops_2_dst_rtype;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module lo_us_1(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_0_ext hi_us_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module data_40x73(\n input [5:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [72:0] R0_data,\n input [5:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [72:0] W0_data\n);\n\n reg [72:0] Memory[0:39];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 73'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module rockettile_icache_data_arrays_0(\n input [8:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [255:0] RW0_wdata,\n output [255:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n rockettile_icache_data_arrays_0_ext rockettile_icache_data_arrays_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module rockettile_icache_tag_array(\n input [5:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [167:0] RW0_wdata,\n output [167:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n rockettile_icache_tag_array_ext rockettile_icache_tag_array_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// FDiv/FSqrt Unit\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile.FPConstants._\nimport freechips.rocketchip.tile\nimport boom.v3.common._\nimport boom.v3.util._\nimport freechips.rocketchip.tile.HasFPUParameters\nimport freechips.rocketchip.util.uintToBitPat\n\n/**\n * Decoder for FPU divide and square root signals\n */\nclass UOPCodeFDivDecoder(implicit p: Parameters) extends BoomModule\n with HasFPUParameters\n{\n val io = IO(new Bundle {\n val uopc = Input(Bits(UOPC_SZ.W))\n val sigs = Output(new tile.FPUCtrlSigs())\n })\n\n val N = BitPat(\"b0\")\n val Y = BitPat(\"b1\")\n val X = BitPat(\"b?\")\n\n val decoder = freechips.rocketchip.rocket.DecodeLogic(io.uopc,\n // Note: not all of these signals are used or necessary, but we're\n // constrained by the need to fit the rocket.FPU units' ctrl signals.\n // swap12 fma\n // | swap32 | div\n // | | typeTagIn | | sqrt\n // ldst | | | typeTagOut | | wflags\n // | wen | | | | from_int | | |\n // | | ren1 | | | | | to_int | | |\n // | | | ren2 | | | | | | fast | | |\n // | | | | ren3 | | | | | | | | | |\n // | | | | | | | | | | | | | | | |\n /* Default */ List(X,X,X,X,X, X,X,X,X,X,X,X, X,X,X,X),\n Array(\n BitPat(uopFDIV_S) -> List(X,X,Y,Y,X, X,X,S,S,X,X,X, X,Y,N,Y),\n BitPat(uopFDIV_D) -> List(X,X,Y,Y,X, X,X,D,D,X,X,X, X,Y,N,Y),\n BitPat(uopFSQRT_S) -> List(X,X,Y,N,X, X,X,S,S,X,X,X, X,N,Y,Y),\n BitPat(uopFSQRT_D) -> List(X,X,Y,N,X, X,X,D,D,X,X,X, X,N,Y,Y)\n ): Array[(BitPat, List[BitPat])])\n\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma,\n s.div, s.sqrt, s.wflags)\n s.vec := false.B\n sigs zip decoder map {case(s,d) => s := d}\n}\n\n/**\n * fdiv/fsqrt is douple-precision. Must upconvert inputs and downconvert outputs\n * as necessary. Must wait till killed uop finishes before we're ready again.\n * fdiv/fsqrt unit uses an unstable FIFO interface, and thus we must spend a\n * cycle buffering up an uop to provide slack between the issue queue and the\n * fdiv/fsqrt unit. FDivUnit inherents directly from FunctionalUnit, because\n * UnpipelinedFunctionalUnit can only handle 1 inflight uop, whereas FDivUnit\n * contains up to 2 inflight uops due to the need to buffer the input as the\n * fdiv unit uses an unstable FIFO interface.\n * TODO extend UnpipelinedFunctionalUnit to handle a >1 uops inflight.\n *\n * @param isPipelined is the functional unit pipelined\n * @param numStages number of stages for the functional unit\n * @param numBypassStages number of bypass stages\n * @param dataWidth width of the data out of the functional unit\n */\nclass FDivSqrtUnit(implicit p: Parameters)\n extends FunctionalUnit(\n isPipelined = false,\n numStages = 1,\n numBypassStages = 0,\n dataWidth = 65,\n needsFcsr = true)\n with tile.HasFPUParameters\n{\n //--------------------------------------\n // buffer inputs and upconvert as needed\n\n // provide a one-entry queue to store incoming uops while waiting for the fdiv/fsqrt unit to become available.\n val r_buffer_val = RegInit(false.B)\n val r_buffer_req = Reg(new FuncUnitReq(dataWidth=65))\n val r_buffer_fin = Reg(new tile.FPInput)\n\n val fdiv_decoder = Module(new UOPCodeFDivDecoder)\n fdiv_decoder.io.uopc := io.req.bits.uop.uopc\n\n // handle branch kill on queued entry\n r_buffer_val := !IsKilledByBranch(io.brupdate, r_buffer_req.uop) && !io.req.bits.kill && r_buffer_val\n r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)\n\n // handle incoming uop, including upconversion as needed, and push back if our input queue is already occupied\n io.req.ready := !r_buffer_val\n\n def upconvert(x: UInt) = {\n val s2d = Module(new hardfloat.RecFNToRecFN(inExpWidth = 8, inSigWidth = 24, outExpWidth = 11, outSigWidth = 53))\n s2d.io.in := x\n s2d.io.roundingMode := 0.U\n s2d.io.detectTininess := DontCare\n s2d.io.out\n }\n val in1_upconvert = upconvert(unbox(io.req.bits.rs1_data, false.B, Some(tile.FType.S)))\n val in2_upconvert = upconvert(unbox(io.req.bits.rs2_data, false.B, Some(tile.FType.S)))\n\n when (io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill) {\n r_buffer_val := true.B\n r_buffer_req := io.req.bits\n r_buffer_req.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)\n r_buffer_fin.viewAsSupertype(new tile.FPUCtrlSigs) := fdiv_decoder.io.sigs\n\n r_buffer_fin.rm := Mux(ImmGenRm(io.req.bits.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io.req.bits.uop.imm_packed))\n r_buffer_fin.typ := 0.U // unused for fdivsqrt\n val tag = fdiv_decoder.io.sigs.typeTagIn\n r_buffer_fin.in1 := unbox(io.req.bits.rs1_data, tag, Some(tile.FType.D))\n r_buffer_fin.in2 := unbox(io.req.bits.rs2_data, tag, Some(tile.FType.D))\n when (tag === S) {\n r_buffer_fin.in1 := in1_upconvert\n r_buffer_fin.in2 := in2_upconvert\n }\n }\n\n assert (!(r_buffer_val && io.req.valid), \"[fdiv] a request is incoming while the buffer is already full.\")\n\n //-----------\n // fdiv/fsqrt\n\n val divsqrt = Module(new hardfloat.DivSqrtRecF64)\n\n val r_divsqrt_val = RegInit(false.B) // inflight uop?\n val r_divsqrt_killed = Reg(Bool()) // has inflight uop been killed?\n val r_divsqrt_fin = Reg(new tile.FPInput)\n val r_divsqrt_uop = Reg(new MicroOp)\n\n // Need to buffer output until RF writeport is available.\n val output_buffer_available = Wire(Bool())\n\n val may_fire_input =\n r_buffer_val &&\n (r_buffer_fin.div || r_buffer_fin.sqrt) &&\n !r_divsqrt_val &&\n output_buffer_available\n\n val divsqrt_ready = Mux(divsqrt.io.sqrtOp, divsqrt.io.inReady_sqrt, divsqrt.io.inReady_div)\n divsqrt.io.inValid := may_fire_input // must be setup early\n divsqrt.io.sqrtOp := r_buffer_fin.sqrt\n divsqrt.io.a := r_buffer_fin.in1\n divsqrt.io.b := Mux(divsqrt.io.sqrtOp, r_buffer_fin.in1, r_buffer_fin.in2)\n divsqrt.io.roundingMode := r_buffer_fin.rm\n divsqrt.io.detectTininess := DontCare\n\n r_divsqrt_killed := r_divsqrt_killed || IsKilledByBranch(io.brupdate, r_divsqrt_uop) || io.req.bits.kill\n r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)\n\n when (may_fire_input && divsqrt_ready) {\n // Remove entry from the input buffer.\n // We don't have time to kill divsqrt request so must track if killed on entry.\n r_buffer_val := false.B\n r_divsqrt_val := true.B\n r_divsqrt_fin := r_buffer_fin\n r_divsqrt_uop := r_buffer_req.uop\n r_divsqrt_killed := IsKilledByBranch(io.brupdate, r_buffer_req.uop) || io.req.bits.kill\n r_divsqrt_uop.br_mask := GetNewBrMask(io.brupdate, r_buffer_req.uop)\n }\n\n //-----------------------------------------\n // buffer output and down-convert as needed\n\n val r_out_val = RegInit(false.B)\n val r_out_uop = Reg(new MicroOp)\n val r_out_flags_double = Reg(Bits())\n val r_out_wdata_double = Reg(Bits())\n\n output_buffer_available := !r_out_val\n\n r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)\n\n when (io.resp.ready || IsKilledByBranch(io.brupdate, r_out_uop) || io.req.bits.kill) {\n r_out_val := false.B\n }\n when (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt) {\n r_divsqrt_val := false.B\n\n r_out_val := !r_divsqrt_killed && !IsKilledByBranch(io.brupdate, r_divsqrt_uop) && !io.req.bits.kill\n r_out_uop := r_divsqrt_uop\n r_out_uop.br_mask := GetNewBrMask(io.brupdate, r_divsqrt_uop)\n r_out_wdata_double := sanitizeNaN(divsqrt.io.out, tile.FType.D)\n r_out_flags_double := divsqrt.io.exceptionFlags\n\n assert (r_divsqrt_val, \"[fdiv] a response is being generated for no request.\")\n }\n\n assert (!(r_out_val && (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt)),\n \"[fdiv] Buffered output being overwritten by another output from the fdiv/fsqrt unit.\")\n\n val downvert_d2s = Module(new hardfloat.RecFNToRecFN(\n inExpWidth = 11, inSigWidth = 53, outExpWidth = 8, outSigWidth = 24))\n downvert_d2s.io.in := r_out_wdata_double\n downvert_d2s.io.roundingMode := r_divsqrt_fin.rm\n downvert_d2s.io.detectTininess := DontCare\n val out_flags = r_out_flags_double | Mux(r_divsqrt_fin.typeTagIn === S, downvert_d2s.io.exceptionFlags, 0.U)\n\n io.resp.valid := r_out_val && !IsKilledByBranch(io.brupdate, r_out_uop)\n io.resp.bits.uop := r_out_uop\n io.resp.bits.data :=\n Mux(r_divsqrt_fin.typeTagIn === S,\n box(downvert_d2s.io.out, false.B),\n box(r_out_wdata_double, true.B))\n io.resp.bits.fflags.valid := io.resp.valid\n io.resp.bits.fflags.bits.uop := r_out_uop\n io.resp.bits.fflags.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_out_uop)\n io.resp.bits.fflags.bits.flags := out_flags\n}", + "response": "module UOPCodeFDivDecoder(\n input [6:0] io_uopc,\n output [1:0] io_sigs_typeTagIn,\n output io_sigs_div,\n output io_sigs_sqrt\n);\n\n wire [4:0] decoder_decoded_invInputs = ~(io_uopc[4:0]);\n wire [6:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_invInputs[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n wire [3:0] _decoder_decoded_andMatrixOutputs_T_3 = {io_uopc[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]};\n assign io_sigs_typeTagIn = {1'h0, |{&_decoder_decoded_andMatrixOutputs_T_1, &_decoder_decoded_andMatrixOutputs_T_3}};\n assign io_sigs_div = |{&{decoder_decoded_invInputs[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_1};\n assign io_sigs_sqrt = |{&{io_uopc[0], io_uopc[1], io_uopc[2], decoder_decoded_invInputs[3], decoder_decoded_invInputs[4], io_uopc[5], io_uopc[6]}, &_decoder_decoded_andMatrixOutputs_T_3};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.reflect.DataMirror\nimport chisel3.internal.firrtl.KnownWidth\nimport chisel3.util.{Cat, Valid}\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\n/** Base JTAG shifter IO, viewed from input to shift register chain.\n * Can be chained together.\n */\nclass ShifterIO extends Bundle {\n val shift = Bool() // advance the scan chain on clock high\n val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB\n val capture = Bool() // high in the CaptureIR/DR state when this chain is selected\n val update = Bool() // high in the UpdateIR/DR state when this chain is selected\n\n /** Sets a output shifter IO's control signals from a input shifter IO's control signals.\n */\n def chainControlFrom(in: ShifterIO): Unit = {\n shift := in.shift\n capture := in.capture\n update := in.update\n }\n}\n\ntrait ChainIO extends Bundle {\n val chainIn = Input(new ShifterIO)\n val chainOut = Output(new ShifterIO)\n}\n\nclass Capture[+T <: Data](gen: T) extends Bundle {\n val bits = Input(gen) // data to capture, should be always valid\n val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge\n}\n\nobject Capture {\n def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)\n}\n\n/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain\n * IO.\n */\ntrait Chain extends Module {\n val io: ChainIO\n}\n\n/** One-element shift register, data register for bypass mode.\n *\n * Implements Clause 10.\n */\nclass JtagBypassChain(implicit val p: Parameters) extends Chain {\n class ModIO extends ChainIO\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val reg = Reg(Bool()) // 10.1.1a single shift register stage\n\n io.chainOut.data := reg\n\n property.cover(io.chainIn.capture, \"bypass_chain_capture\", \"JTAG; bypass_chain_capture; This Bypass Chain captured data\")\n\n when (io.chainIn.capture) {\n reg := false.B // 10.1.1b capture logic 0 on TCK rising\n } .elsewhen (io.chainIn.shift) {\n reg := io.chainIn.data\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject JtagBypassChain {\n def apply()(implicit p: Parameters) = new JtagBypassChain\n}\n\n/** Simple shift register with parallel capture only, for read-only data registers.\n *\n * Number of stages is the number of bits in gen, which must have a known width.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureChain_${gen.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(gen)\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val n = DataMirror.widthOf(gen) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $gen\"); -1 // TODO: remove -1 type hack\n }\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG; chain_capture; This Chain captured data\")\n \n when (io.chainIn.capture) {\n (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))\n io.capture.capture := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n } .otherwise {\n io.capture.capture := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureChain {\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)\n}\n\n/** Simple shift register with parallel capture and update. Useful for general instruction and data\n * scan registers.\n *\n * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have\n * known widths. If there is a width mismatch, the unused most significant bits will be zero.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(genCapture)\n val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val captureWidth = DataMirror.widthOf(genCapture) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genCapture\"); -1 // TODO: remove -1 type hack\n }\n val updateWidth = DataMirror.widthOf(genUpdate) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genUpdate\"); -1 // TODO: remove -1 type hack\n }\n val n = math.max(captureWidth, updateWidth)\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n val updateBits = Cat(regs.reverse)(updateWidth-1, 0)\n io.update.bits := updateBits.asTypeOf(io.update.bits)\n\n val captureBits = io.capture.bits.asUInt\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG;chain_capture; This Chain captured data\")\n property.cover(io.chainIn.capture, \"chain_update\", \"JTAG;chain_update; This Chain updated data\")\n\n when (io.chainIn.capture) {\n (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))\n (captureWidth until n) map (x => regs(x) := 0.U)\n io.capture.capture := true.B\n io.update.valid := false.B\n } .elsewhen (io.chainIn.update) {\n io.capture.capture := false.B\n io.update.valid := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n io.update.valid := false.B\n } .otherwise {\n io.capture.capture := false.B\n io.update.valid := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureUpdateChain {\n /** Capture-update chain with matching capture and update types.\n */\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)\n def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =\n new CaptureUpdateChain(genCapture, genUpdate)\n}", + "response": "module CaptureUpdateChain_DTMInfo_To_DTMInfo(\n input clock,\n input reset,\n input io_chainIn_shift,\n input io_chainIn_data,\n input io_chainIn_capture,\n input io_chainIn_update,\n output io_chainOut_data,\n input [1:0] io_capture_bits_dmiStatus,\n output io_update_valid,\n output io_update_bits_dmireset\n);\n\n reg regs_0;\n reg regs_1;\n reg regs_2;\n reg regs_3;\n reg regs_4;\n reg regs_5;\n reg regs_6;\n reg regs_7;\n reg regs_8;\n reg regs_9;\n reg regs_10;\n reg regs_11;\n reg regs_12;\n reg regs_13;\n reg regs_14;\n reg regs_15;\n reg regs_16;\n reg regs_17;\n reg regs_18;\n reg regs_19;\n reg regs_20;\n reg regs_21;\n reg regs_22;\n reg regs_23;\n reg regs_24;\n reg regs_25;\n reg regs_26;\n reg regs_27;\n reg regs_28;\n reg regs_29;\n reg regs_30;\n reg regs_31;\n wire _GEN = io_chainIn_update | ~io_chainIn_shift;\n always @(posedge clock) begin\n regs_0 <= io_chainIn_capture | (_GEN ? regs_0 : regs_1);\n regs_1 <= ~io_chainIn_capture & (_GEN ? regs_1 : regs_2);\n regs_2 <= ~io_chainIn_capture & (_GEN ? regs_2 : regs_3);\n regs_3 <= ~io_chainIn_capture & (_GEN ? regs_3 : regs_4);\n regs_4 <= io_chainIn_capture | (_GEN ? regs_4 : regs_5);\n regs_5 <= io_chainIn_capture | (_GEN ? regs_5 : regs_6);\n regs_6 <= io_chainIn_capture | (_GEN ? regs_6 : regs_7);\n regs_7 <= ~io_chainIn_capture & (_GEN ? regs_7 : regs_8);\n regs_8 <= ~io_chainIn_capture & (_GEN ? regs_8 : regs_9);\n regs_9 <= ~io_chainIn_capture & (_GEN ? regs_9 : regs_10);\n if (io_chainIn_capture) begin\n regs_10 <= io_capture_bits_dmiStatus[0];\n regs_11 <= io_capture_bits_dmiStatus[1];\n end\n else if (_GEN) begin\n end\n else begin\n regs_10 <= regs_11;\n regs_11 <= regs_12;\n end\n regs_12 <= io_chainIn_capture | (_GEN ? regs_12 : regs_13);\n regs_13 <= ~io_chainIn_capture & (_GEN ? regs_13 : regs_14);\n regs_14 <= io_chainIn_capture | (_GEN ? regs_14 : regs_15);\n regs_15 <= ~io_chainIn_capture & (_GEN ? regs_15 : regs_16);\n regs_16 <= ~io_chainIn_capture & (_GEN ? regs_16 : regs_17);\n regs_17 <= ~io_chainIn_capture & (_GEN ? regs_17 : regs_18);\n regs_18 <= ~io_chainIn_capture & (_GEN ? regs_18 : regs_19);\n regs_19 <= ~io_chainIn_capture & (_GEN ? regs_19 : regs_20);\n regs_20 <= ~io_chainIn_capture & (_GEN ? regs_20 : regs_21);\n regs_21 <= ~io_chainIn_capture & (_GEN ? regs_21 : regs_22);\n regs_22 <= ~io_chainIn_capture & (_GEN ? regs_22 : regs_23);\n regs_23 <= ~io_chainIn_capture & (_GEN ? regs_23 : regs_24);\n regs_24 <= ~io_chainIn_capture & (_GEN ? regs_24 : regs_25);\n regs_25 <= ~io_chainIn_capture & (_GEN ? regs_25 : regs_26);\n regs_26 <= ~io_chainIn_capture & (_GEN ? regs_26 : regs_27);\n regs_27 <= ~io_chainIn_capture & (_GEN ? regs_27 : regs_28);\n regs_28 <= ~io_chainIn_capture & (_GEN ? regs_28 : regs_29);\n regs_29 <= ~io_chainIn_capture & (_GEN ? regs_29 : regs_30);\n regs_30 <= ~io_chainIn_capture & (_GEN ? regs_30 : regs_31);\n regs_31 <= ~io_chainIn_capture & (_GEN ? regs_31 : io_chainIn_data);\n end\n assign io_chainOut_data = regs_0;\n assign io_update_valid = ~io_chainIn_capture & io_chainIn_update;\n assign io_update_bits_dmireset = regs_16;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle\n{\n//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:\n val isSigNaNAny = Bool()\n val isNaNAOrB = Bool()\n val isInfA = Bool()\n val isZeroA = Bool()\n val isInfB = Bool()\n val isZeroB = Bool()\n val signProd = Bool()\n val isNaNC = Bool()\n val isInfC = Bool()\n val isZeroC = Bool()\n val sExpSum = SInt((expWidth + 2).W)\n val doSubMags = Bool()\n val CIsDominant = Bool()\n val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)\n val highAlignedSigC = UInt((sigWidth + 2).W)\n val bit0AlignedSigC = UInt(1.W)\n\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val mulAddA = Output(UInt(sigWidth.W))\n val mulAddB = Output(UInt(sigWidth.W))\n val mulAddC = Output(UInt((sigWidth * 2).W))\n val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN\n//*** UNSHIFTED C AND PRODUCT):\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)\n val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)\n val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)\n\n val signProd = rawA.sign ^ rawB.sign ^ io.op(1)\n//*** REVIEW THE BIAS FOR 'sExpAlignedProd':\n val sExpAlignedProd =\n rawA.sExp +& rawB.sExp + (-(BigInt(1)<>CAlignDist\n val reduced4CExtra =\n (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &\n lowMask(\n CAlignDist>>2,\n//*** NOT NEEDED?:\n// (sigSumWidth + 2)>>2,\n (sigSumWidth - 1)>>2,\n (sigSumWidth - sigWidth - 1)>>2\n )\n ).orR\n val alignedSigC =\n Cat(mainAlignedSigC>>3,\n Mux(doSubMags,\n mainAlignedSigC(2, 0).andR && ! reduced4CExtra,\n mainAlignedSigC(2, 0).orR || reduced4CExtra\n )\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.mulAddA := rawA.sig\n io.mulAddB := rawB.sig\n io.mulAddC := alignedSigC(sigWidth * 2, 1)\n\n io.toPostMul.isSigNaNAny :=\n isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||\n isSigNaNRawFloat(rawC)\n io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN\n io.toPostMul.isInfA := rawA.isInf\n io.toPostMul.isZeroA := rawA.isZero\n io.toPostMul.isInfB := rawB.isInf\n io.toPostMul.isZeroB := rawB.isZero\n io.toPostMul.signProd := signProd\n io.toPostMul.isNaNC := rawC.isNaN\n io.toPostMul.isInfC := rawC.isInf\n io.toPostMul.isZeroC := rawC.isZero\n io.toPostMul.sExpSum :=\n Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)\n io.toPostMul.doSubMags := doSubMags\n io.toPostMul.CIsDominant := CIsDominant\n io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)\n io.toPostMul.highAlignedSigC :=\n alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)\n io.toPostMul.bit0AlignedSigC := alignedSigC(0)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\nclass MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))\n val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))\n val roundingMode = Input(UInt(3.W))\n val invalidExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigSumWidth = sigWidth * 3 + 3\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_min = (io.roundingMode === round_min)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags\n val sigSum =\n Cat(Mux(io.mulAddResult(sigWidth * 2),\n io.fromPreMul.highAlignedSigC + 1.U,\n io.fromPreMul.highAlignedSigC\n ),\n io.mulAddResult(sigWidth * 2 - 1, 0),\n io.fromPreMul.bit0AlignedSigC\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val CDom_sign = opSignC\n val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext\n val CDom_absSigSum =\n Mux(io.fromPreMul.doSubMags,\n ~sigSum(sigSumWidth - 1, sigWidth + 1),\n 0.U(1.W) ##\n//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:\n io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##\n sigSum(sigSumWidth - 3, sigWidth + 2)\n\n )\n val CDom_absSigSumExtra =\n Mux(io.fromPreMul.doSubMags,\n (~sigSum(sigWidth, 1)).orR,\n sigSum(sigWidth + 1, 1).orR\n )\n val CDom_mainSig =\n (CDom_absSigSum<>2, 0, sigWidth>>2)).orR\n val CDom_sig =\n Cat(CDom_mainSig>>3,\n CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||\n CDom_absSigSumExtra\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)\n val notCDom_absSigSum =\n Mux(notCDom_signSigSum,\n ~sigSum(sigWidth * 2 + 2, 0),\n sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags\n )\n val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)\n val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)\n val notCDom_nearNormDist = notCDom_normDistReduced2<<1\n val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext\n val notCDom_mainSig =\n (notCDom_absSigSum<>1, 0)<<((sigWidth>>1) & 1)) &\n lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)\n ).orR\n val notCDom_sig =\n Cat(notCDom_mainSig>>3,\n notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra\n )\n val notCDom_completeCancellation =\n (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)\n val notCDom_sign =\n Mux(notCDom_completeCancellation,\n roundingMode_min,\n io.fromPreMul.signProd ^ notCDom_signSigSum\n )\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB\n val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC\n val notNaN_addZeros =\n (io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&\n io.fromPreMul.isZeroC\n\n io.invalidExc :=\n io.fromPreMul.isSigNaNAny ||\n (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||\n (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||\n (! io.fromPreMul.isNaNAOrB &&\n (io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&\n io.fromPreMul.isInfC &&\n io.fromPreMul.doSubMags)\n io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC\n io.rawOut.isInf := notNaN_isInfOut\n//*** IMPROVE?:\n io.rawOut.isZero :=\n notNaN_addZeros ||\n (! io.fromPreMul.CIsDominant && notCDom_completeCancellation)\n io.rawOut.sign :=\n (notNaN_isInfProd && io.fromPreMul.signProd) ||\n (io.fromPreMul.isInfC && opSignC) ||\n (notNaN_addZeros && ! roundingMode_min &&\n io.fromPreMul.signProd && opSignC) ||\n (notNaN_addZeros && roundingMode_min &&\n (io.fromPreMul.signProd || opSignC)) ||\n (! notNaN_isInfOut && ! notNaN_addZeros &&\n Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))\n io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)\n io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule\n{\n override def desiredName = s\"MulAddRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val mulAddRecFNToRaw_preMul =\n Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul =\n Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n mulAddRecFNToRaw_postMul.io.fromPreMul :=\n mulAddRecFNToRaw_preMul.io.toPostMul\n mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult\n mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := false.B\n roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut\n roundRawFNToRecFN.io.roundingMode := io.roundingMode\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}", + "response": "module MulAddRecFNToRaw_preMul_e8_s24(\n input [1:0] io_op,\n input [32:0] io_a,\n input [32:0] io_b,\n input [32:0] io_c,\n output [23:0] io_mulAddA,\n output [23:0] io_mulAddB,\n output [47:0] io_mulAddC,\n output io_toPostMul_isSigNaNAny,\n output io_toPostMul_isNaNAOrB,\n output io_toPostMul_isInfA,\n output io_toPostMul_isZeroA,\n output io_toPostMul_isInfB,\n output io_toPostMul_isZeroB,\n output io_toPostMul_signProd,\n output io_toPostMul_isNaNC,\n output io_toPostMul_isInfC,\n output io_toPostMul_isZeroC,\n output [9:0] io_toPostMul_sExpSum,\n output io_toPostMul_doSubMags,\n output io_toPostMul_CIsDominant,\n output [4:0] io_toPostMul_CDom_CAlignDist,\n output [25:0] io_toPostMul_highAlignedSigC,\n output io_toPostMul_bit0AlignedSigC\n);\n\n wire rawA_isNaN = (&(io_a[31:30])) & io_a[29];\n wire rawB_isNaN = (&(io_b[31:30])) & io_b[29];\n wire rawC_isNaN = (&(io_c[31:30])) & io_c[29];\n wire signProd = io_a[32] ^ io_b[32] ^ io_op[1];\n wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5;\n wire doSubMags = signProd ^ io_c[32] ^ io_op[0];\n wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]};\n wire isMinCAlign = ~(|(io_a[31:29])) | ~(|(io_b[31:29])) | $signed(_sNatCAlignDist_T) < 11'sh0;\n wire CIsDominant = (|(io_c[31:29])) & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19);\n wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A;\n wire [77:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[31:29])), ~(io_c[22:0])} : {1'h0, |(io_c[31:29]), io_c[22:0]}, {53{doSubMags}}}) >>> CAlignDist);\n wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> CAlignDist[6:2]);\n wire [5:0] _GEN = {|(io_c[21:18]), |(io_c[17:14]), |(io_c[13:10]), |(io_c[9:6]), |(io_c[5:2]), |(io_c[1:0])} & {reduced4CExtra_shift[14], reduced4CExtra_shift[15], reduced4CExtra_shift[16], reduced4CExtra_shift[17], reduced4CExtra_shift[18], reduced4CExtra_shift[19]};\n assign io_mulAddA = {|(io_a[31:29]), io_a[22:0]};\n assign io_mulAddB = {|(io_b[31:29]), io_b[22:0]};\n assign io_mulAddC = mainAlignedSigC[50:3];\n assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]);\n assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN;\n assign io_toPostMul_isInfA = (&(io_a[31:30])) & ~(io_a[29]);\n assign io_toPostMul_isZeroA = ~(|(io_a[31:29]));\n assign io_toPostMul_isInfB = (&(io_b[31:30])) & ~(io_b[29]);\n assign io_toPostMul_isZeroB = ~(|(io_b[31:29]));\n assign io_toPostMul_signProd = signProd;\n assign io_toPostMul_isNaNC = rawC_isNaN;\n assign io_toPostMul_isInfC = (&(io_c[31:30])) & ~(io_c[29]);\n assign io_toPostMul_isZeroC = ~(|(io_c[31:29]));\n assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18;\n assign io_toPostMul_doSubMags = doSubMags;\n assign io_toPostMul_CIsDominant = CIsDominant;\n assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0];\n assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51];\n assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 6'h0 : (|{mainAlignedSigC[2:0], _GEN});\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us_1(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_0_ext hi_us_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat, log2Ceil}\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\n\nclass PMPConfig extends Bundle {\n val l = Bool()\n val res = UInt(2.W)\n val a = UInt(2.W)\n val x = Bool()\n val w = Bool()\n val r = Bool()\n}\n\nobject PMP {\n def lgAlign = 2\n\n def apply(reg: PMPReg): PMP = {\n val pmp = Wire(new PMP()(reg.p))\n pmp.cfg := reg.cfg\n pmp.addr := reg.addr\n pmp.mask := pmp.computeMask\n pmp\n }\n}\n\nclass PMPReg(implicit p: Parameters) extends CoreBundle()(p) {\n val cfg = new PMPConfig\n val addr = UInt((paddrBits - PMP.lgAlign).W)\n\n def reset(): Unit = {\n cfg.a := 0.U\n cfg.l := 0.U\n }\n\n def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {\n val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U\n Mux(napot, addr | (mask >> 1), ~(~addr | mask))\n }\n def napot = cfg.a(1)\n def torNotNAPOT = cfg.a(0)\n def tor = !napot && torNotNAPOT\n def cfgLocked = cfg.l\n def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor\n}\n\nclass PMP(implicit p: Parameters) extends PMPReg {\n val mask = UInt(paddrBits.W)\n\n import PMP._\n def computeMask = {\n val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)\n Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)\n }\n private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)\n\n private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {\n def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U\n if (lgMaxSize <= pmpGranularity.log2) {\n eval(x, comparand, mask)\n } else {\n // break up the circuit; the MSB part will be CSE'd\n val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)\n val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)\n val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))\n msbMatch && lsbMatch\n }\n }\n\n private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {\n if (lgMaxSize <= pmpGranularity.log2) {\n x < comparand\n } else {\n // break up the circuit; the MSB part will be CSE'd\n val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)\n val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U\n val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)\n msbsLess || (msbsEqual && lsbsLess)\n }\n }\n\n private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =\n !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)\n\n private def upperBoundMatch(x: UInt, lgMaxSize: Int) =\n boundMatch(x, 0.U, lgMaxSize)\n\n private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =\n prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)\n\n private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {\n val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)\n maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))\n }\n\n private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>\n f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)\n }\n\n private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {\n val beginsAfterLower = !(x < prev.comparand)\n val beginsAfterUpper = !(x < comparand)\n\n val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)\n val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)\n val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)\n\n endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)\n }\n\n // returns whether this PMP completely contains, or contains none of, a page\n def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =\n Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))\n\n // returns whether this matching PMP fully contains the access\n def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {\n val lsbMask = UIntToOH1(lgSize, lgMaxSize)\n val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U\n val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U\n val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)\n val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U\n Mux(napot, pow2Aligned, rangeAligned)\n }\n\n // returns whether this PMP matches at least one byte of the access\n def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =\n Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))\n}\n\nclass PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {\n def apply(addr: UInt, pgLevel: UInt): Bool = {\n pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>\n (h && pmp.homogeneous(addr, pgLevel, prev), pmp)\n }._1\n }\n}\n\nclass PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module\n with HasCoreParameters {\n override def desiredName = s\"PMPChecker_s${lgMaxSize}\"\n val io = IO(new Bundle {\n val prv = Input(UInt(PRV.SZ.W))\n val pmp = Input(Vec(nPMPs, new PMP))\n val addr = Input(UInt(paddrBits.W))\n val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))\n val r = Output(Bool())\n val w = Output(Bool())\n val x = Output(Bool())\n })\n\n val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U\n val pmp0 = WireInit(0.U.asTypeOf(new PMP))\n pmp0.cfg.r := default\n pmp0.cfg.w := default\n pmp0.cfg.x := default\n\n val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>\n val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)\n val ignore = default && !pmp.cfg.l\n val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)\n\n for ((name, idx) <- Seq(\"no\", \"TOR\", if (pmpGranularity <= 4) \"NA4\" else \"\", \"NAPOT\").zipWithIndex; if name.nonEmpty)\n property.cover(pmp.cfg.a === idx.U, s\"The cfg access is set to ${name} access \", \"Cover PMP access mode setting\")\n\n property.cover(pmp.cfg.l === 0x1.U, s\"The cfg lock is set to high \", \"Cover PMP lock mode setting\")\n \n // Not including Write and no Read permission as the combination is reserved\n for ((name, idx) <- Seq(\"no\", \"RO\", \"\", \"RW\", \"X\", \"RX\", \"\", \"RWX\").zipWithIndex; if name.nonEmpty)\n property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s\"The permission is set to ${name} access \", \"Cover PMP access permission setting\")\n\n for ((name, idx) <- Seq(\"\", \"TOR\", if (pmpGranularity <= 4) \"NA4\" else \"\", \"NAPOT\").zipWithIndex; if name.nonEmpty) {\n property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s\"The access matches ${name} mode \", \"Cover PMP access\")\n property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s\"The access matches ${name} mode with lock bit high\", \"Cover PMP access with lock bit\")\n }\n\n val cur = WireInit(pmp)\n cur.cfg.r := aligned && (pmp.cfg.r || ignore)\n cur.cfg.w := aligned && (pmp.cfg.w || ignore)\n cur.cfg.x := aligned && (pmp.cfg.x || ignore)\n Mux(hit, cur, prev)\n }\n\n io.r := res.cfg.r\n io.w := res.cfg.w\n io.x := res.cfg.x\n}", + "response": "module PMPChecker_s2(\n input [1:0] io_prv,\n input io_pmp_0_cfg_l,\n input [1:0] io_pmp_0_cfg_a,\n input io_pmp_0_cfg_x,\n input io_pmp_0_cfg_w,\n input io_pmp_0_cfg_r,\n input [29:0] io_pmp_0_addr,\n input [31:0] io_pmp_0_mask,\n input io_pmp_1_cfg_l,\n input [1:0] io_pmp_1_cfg_a,\n input io_pmp_1_cfg_x,\n input io_pmp_1_cfg_w,\n input io_pmp_1_cfg_r,\n input [29:0] io_pmp_1_addr,\n input [31:0] io_pmp_1_mask,\n input io_pmp_2_cfg_l,\n input [1:0] io_pmp_2_cfg_a,\n input io_pmp_2_cfg_x,\n input io_pmp_2_cfg_w,\n input io_pmp_2_cfg_r,\n input [29:0] io_pmp_2_addr,\n input [31:0] io_pmp_2_mask,\n input io_pmp_3_cfg_l,\n input [1:0] io_pmp_3_cfg_a,\n input io_pmp_3_cfg_x,\n input io_pmp_3_cfg_w,\n input io_pmp_3_cfg_r,\n input [29:0] io_pmp_3_addr,\n input [31:0] io_pmp_3_mask,\n input io_pmp_4_cfg_l,\n input [1:0] io_pmp_4_cfg_a,\n input io_pmp_4_cfg_x,\n input io_pmp_4_cfg_w,\n input io_pmp_4_cfg_r,\n input [29:0] io_pmp_4_addr,\n input [31:0] io_pmp_4_mask,\n input io_pmp_5_cfg_l,\n input [1:0] io_pmp_5_cfg_a,\n input io_pmp_5_cfg_x,\n input io_pmp_5_cfg_w,\n input io_pmp_5_cfg_r,\n input [29:0] io_pmp_5_addr,\n input [31:0] io_pmp_5_mask,\n input io_pmp_6_cfg_l,\n input [1:0] io_pmp_6_cfg_a,\n input io_pmp_6_cfg_x,\n input io_pmp_6_cfg_w,\n input io_pmp_6_cfg_r,\n input [29:0] io_pmp_6_addr,\n input [31:0] io_pmp_6_mask,\n input io_pmp_7_cfg_l,\n input [1:0] io_pmp_7_cfg_a,\n input io_pmp_7_cfg_x,\n input io_pmp_7_cfg_w,\n input io_pmp_7_cfg_r,\n input [29:0] io_pmp_7_addr,\n input [31:0] io_pmp_7_mask,\n input [31:0] io_addr,\n output io_r,\n output io_w,\n output io_x\n);\n\n wire res_hit = io_pmp_7_cfg_a[1] ? ((io_addr ^ {io_pmp_7_addr, 2'h0}) & ~io_pmp_7_mask) == 32'h0 : io_pmp_7_cfg_a[0] & io_addr >= {io_pmp_6_addr, 2'h0} & io_addr < {io_pmp_7_addr, 2'h0};\n wire res_ignore = io_prv[1] & ~io_pmp_7_cfg_l;\n wire res_hit_1 = io_pmp_6_cfg_a[1] ? ((io_addr ^ {io_pmp_6_addr, 2'h0}) & ~io_pmp_6_mask) == 32'h0 : io_pmp_6_cfg_a[0] & io_addr >= {io_pmp_5_addr, 2'h0} & io_addr < {io_pmp_6_addr, 2'h0};\n wire res_ignore_1 = io_prv[1] & ~io_pmp_6_cfg_l;\n wire res_hit_2 = io_pmp_5_cfg_a[1] ? ((io_addr ^ {io_pmp_5_addr, 2'h0}) & ~io_pmp_5_mask) == 32'h0 : io_pmp_5_cfg_a[0] & io_addr >= {io_pmp_4_addr, 2'h0} & io_addr < {io_pmp_5_addr, 2'h0};\n wire res_ignore_2 = io_prv[1] & ~io_pmp_5_cfg_l;\n wire res_hit_3 = io_pmp_4_cfg_a[1] ? ((io_addr ^ {io_pmp_4_addr, 2'h0}) & ~io_pmp_4_mask) == 32'h0 : io_pmp_4_cfg_a[0] & io_addr >= {io_pmp_3_addr, 2'h0} & io_addr < {io_pmp_4_addr, 2'h0};\n wire res_ignore_3 = io_prv[1] & ~io_pmp_4_cfg_l;\n wire res_hit_4 = io_pmp_3_cfg_a[1] ? ((io_addr ^ {io_pmp_3_addr, 2'h0}) & ~io_pmp_3_mask) == 32'h0 : io_pmp_3_cfg_a[0] & io_addr >= {io_pmp_2_addr, 2'h0} & io_addr < {io_pmp_3_addr, 2'h0};\n wire res_ignore_4 = io_prv[1] & ~io_pmp_3_cfg_l;\n wire res_hit_5 = io_pmp_2_cfg_a[1] ? ((io_addr ^ {io_pmp_2_addr, 2'h0}) & ~io_pmp_2_mask) == 32'h0 : io_pmp_2_cfg_a[0] & io_addr >= {io_pmp_1_addr, 2'h0} & io_addr < {io_pmp_2_addr, 2'h0};\n wire res_ignore_5 = io_prv[1] & ~io_pmp_2_cfg_l;\n wire res_hit_6 = io_pmp_1_cfg_a[1] ? ((io_addr ^ {io_pmp_1_addr, 2'h0}) & ~io_pmp_1_mask) == 32'h0 : io_pmp_1_cfg_a[0] & io_addr >= {io_pmp_0_addr, 2'h0} & io_addr < {io_pmp_1_addr, 2'h0};\n wire res_ignore_6 = io_prv[1] & ~io_pmp_1_cfg_l;\n wire res_hit_7 = io_pmp_0_cfg_a[1] ? ((io_addr ^ {io_pmp_0_addr, 2'h0}) & ~io_pmp_0_mask) == 32'h0 : io_pmp_0_cfg_a[0] & io_addr < {io_pmp_0_addr, 2'h0};\n wire res_ignore_7 = io_prv[1] & ~io_pmp_0_cfg_l;\n assign io_r = res_hit_7 ? io_pmp_0_cfg_r | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_r | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_r | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_r | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_r | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_r | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_r | res_ignore_1 : res_hit ? io_pmp_7_cfg_r | res_ignore : io_prv[1];\n assign io_w = res_hit_7 ? io_pmp_0_cfg_w | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_w | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_w | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_w | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_w | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_w | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_w | res_ignore_1 : res_hit ? io_pmp_7_cfg_w | res_ignore : io_prv[1];\n assign io_x = res_hit_7 ? io_pmp_0_cfg_x | res_ignore_7 : res_hit_6 ? io_pmp_1_cfg_x | res_ignore_6 : res_hit_5 ? io_pmp_2_cfg_x | res_ignore_5 : res_hit_4 ? io_pmp_3_cfg_x | res_ignore_4 : res_hit_3 ? io_pmp_4_cfg_x | res_ignore_3 : res_hit_2 ? io_pmp_5_cfg_x | res_ignore_2 : res_hit_1 ? io_pmp_6_cfg_x | res_ignore_1 : res_hit ? io_pmp_7_cfg_x | res_ignore : io_prv[1];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module regfile_32x65(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [64:0] R0_data,\n input [4:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [64:0] R1_data,\n input [4:0] R2_addr,\n input R2_en,\n input R2_clk,\n output [64:0] R2_data,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [64:0] W0_data,\n input [4:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [64:0] W1_data\n);\n\n reg [64:0] Memory[0:31];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 65'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 65'bx;\n assign R2_data = R2_en ? Memory[R2_addr] : 65'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a29d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [28:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [28:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [28:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2017 SiFive, Inc. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of SiFive nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY SIFIVE AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL SIFIVE OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\n\n\n\n/*\n\ns = sigWidth\nc_i = newBit\n\nDivision:\nwidth of a is (s+2)\n\nNormal\n------\n\n(qi + ci * 2^(-i))*b <= a\nq0 = 0\nr0 = a\n\nq(i+1) = qi + ci*2^(-i)\nri = a - qi*b\nr(i+1) = a - q(i+1)*b\n = a - qi*b - ci*2^(-i)*b\nr(i+1) = ri - ci*2^(-i)*b\nci = ri >= 2^(-i)*b\nsummary_i = ri != 0\n\ni = 0 to s+1\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding\nIf (a < b), then we need to calculate (s+2)th bit and summary_(i+1)\nbecause we need s bits ignoring the leading zero. (This is skipCycle2\npart of Hauser's code.)\n\nHauser\n------\nsig_i = qi\nrem_i = 2^(i-2)*ri\ncycle_i = s+3-i\n\nsig_0 = 0\nrem_0 = a/4\ncycle_0 = s+3\nbit_0 = 2^0 (= 2^(s+1), since we represent a, b and q with (s+2) bits)\n\nsig(i+1) = sig(i) + ci*bit_i\nrem(i+1) = 2rem_i - ci*b/2\nci = 2rem_i >= b/2\nbit_i = 2^-i (=2^(cycle_i-2), since we represent a, b and q with (s+2) bits)\ncycle(i+1) = cycle_i-1\nsummary_1 = a <> b\nsummary(i+1) = if ci then 2rem_i-b/2 <> 0 else summary_i, i <> 0\n\nProof:\n2^i*r(i+1) = 2^i*ri - ci*b. Qed\n\nci = 2^i*ri >= b. Qed\n\nsummary(i+1) = if ci then rem(i+1) else summary_i, i <> 0\nNow, note that all of ck's cannot be 0, since that means\na is 0. So when you traverse through a chain of 0 ck's,\nfrom the end,\neventually, you reach a non-zero cj. That is exactly the\nvalue of ri as the reminder remains the same. When all ck's\nare 0 except c0 (which must be 1) then summary_1 is set\ncorrectly according\nto r1 = a-b != 0. So summary(i+1) is always set correctly\naccording to r(i+1)\n\n\n\nSquare root:\nwidth of a is (s+1)\n\nNormal\n------\n(xi + ci*2^(-i))^2 <= a\nxi^2 + ci*2^(-i)*(2xi+ci*2^(-i)) <= a\n\nx0 = 0\nx(i+1) = xi + ci*2^(-i)\nri = a - xi^2\nr(i+1) = a - x(i+1)^2\n = a - (xi^2 + ci*2^(-i)*(2xi+ci*2^(-i)))\n = ri - ci*2^(-i)*(2xi+ci*2^(-i))\n = ri - ci*2^(-i)*(2xi+2^(-i)) // ci is always 0 or 1\nci = ri >= 2^(-i)*(2xi + 2^(-i))\nsummary_i = ri != 0\n\n\ni = 0 to s+1\n\nFor odd expression, do 2 steps initially.\n\n(s+1)th bit plus summary_(i+1) gives enough information for rounding.\n\nHauser\n------\n\nsig_i = xi\nrem_i = ri*2^(i-1)\ncycle_i = s+2-i\nbit_i = 2^(-i) (= 2^(s-i) = 2^(cycle_i-2) in terms of bit representation)\n\nsig_0 = 0\nrem_0 = a/2\ncycle_0 = s+2\nbit_0 = 1 (= 2^s in terms of bit representation)\n\nsig(i+1) = sig_i + ci * bit_i\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nci = 2*sig_i + bit_i <= 2*rem_i\nbit_i = 2^(cycle_i-2) (in terms of bit representation)\ncycle(i+1) = cycle_i-1\nsummary_1 = a - (2^s) (in terms of bit representation) \nsummary(i+1) = if ci then rem(i+1) <> 0 else summary_i, i <> 0\n\n\nProof:\nci = 2*sig_i + bit_i <= 2*rem_i\nci = 2xi + 2^(-i) <= ri*2^i. Qed\n\nsig(i+1) = sig_i + ci * bit_i\nx(i+1) = xi + ci*2^(-i). Qed\n\nrem(i+1) = 2rem_i - ci*(2sig_i + bit_i)\nr(i+1)*2^i = ri*2^i - ci*(2xi + 2^(-i))\nr(i+1) = ri - ci*2^(-i)*(2xi + 2^(-i)). Qed\n\nSame argument as before for summary.\n\n\n------------------------------\nNote that all registers are updated normally until cycle == 2.\nAt cycle == 2, rem is not updated, but all other registers are updated normally.\nBut, cycle == 1 does not read rem to calculate anything (note that final summary\nis calculated using the values at cycle = 2).\n\n*/\n\n\n\n\n\n\n\n\n\n\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util._\nimport consts._\n\n/*----------------------------------------------------------------------------\n| Computes a division or square root for floating-point in recoded form.\n| Multiple clock cycles are needed for each division or square-root operation,\n| except possibly in special cases.\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRawFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRawFN_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(new RawFloat(expWidth, sigWidth))\n val b = Input(new RawFloat(expWidth, sigWidth))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val cycleNum = RegInit(0.U(log2Ceil(sigWidth + 3).W))\n val inReady = RegInit(true.B) // <-> (cycleNum <= 1)\n val rawOutValid = RegInit(false.B) // <-> (cycleNum === 1)\n\n val sqrtOp_Z = Reg(Bool())\n val majorExc_Z = Reg(Bool())\n//*** REDUCE 3 BITS TO 2-BIT CODE:\n val isNaN_Z = Reg(Bool())\n val isInf_Z = Reg(Bool())\n val isZero_Z = Reg(Bool())\n val sign_Z = Reg(Bool())\n val sExp_Z = Reg(SInt((expWidth + 2).W))\n val fractB_Z = Reg(UInt(sigWidth.W))\n val roundingMode_Z = Reg(UInt(3.W))\n\n /*------------------------------------------------------------------------\n | (The most-significant and least-significant bits of 'rem_Z' are needed\n | only for square roots.)\n *------------------------------------------------------------------------*/\n val rem_Z = Reg(UInt((sigWidth + 2).W))\n val notZeroRem_Z = Reg(Bool())\n val sigX_Z = Reg(UInt((sigWidth + 2).W))\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rawA_S = io.a\n val rawB_S = io.b\n\n//*** IMPROVE THESE:\n val notSigNaNIn_invalidExc_S_div =\n (rawA_S.isZero && rawB_S.isZero) || (rawA_S.isInf && rawB_S.isInf)\n val notSigNaNIn_invalidExc_S_sqrt =\n ! rawA_S.isNaN && ! rawA_S.isZero && rawA_S.sign\n val majorExc_S =\n Mux(io.sqrtOp,\n isSigNaNRawFloat(rawA_S) || notSigNaNIn_invalidExc_S_sqrt,\n isSigNaNRawFloat(rawA_S) || isSigNaNRawFloat(rawB_S) ||\n notSigNaNIn_invalidExc_S_div ||\n (! rawA_S.isNaN && ! rawA_S.isInf && rawB_S.isZero)\n )\n val isNaN_S =\n Mux(io.sqrtOp,\n rawA_S.isNaN || notSigNaNIn_invalidExc_S_sqrt,\n rawA_S.isNaN || rawB_S.isNaN || notSigNaNIn_invalidExc_S_div\n )\n val isInf_S = Mux(io.sqrtOp, rawA_S.isInf, rawA_S.isInf || rawB_S.isZero)\n val isZero_S = Mux(io.sqrtOp, rawA_S.isZero, rawA_S.isZero || rawB_S.isInf)\n val sign_S = rawA_S.sign ^ (! io.sqrtOp && rawB_S.sign)\n\n val specialCaseA_S = rawA_S.isNaN || rawA_S.isInf || rawA_S.isZero\n val specialCaseB_S = rawB_S.isNaN || rawB_S.isInf || rawB_S.isZero\n val normalCase_S_div = ! specialCaseA_S && ! specialCaseB_S\n val normalCase_S_sqrt = ! specialCaseA_S && ! rawA_S.sign\n val normalCase_S = Mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)\n\n val sExpQuot_S_div =\n rawA_S.sExp +&\n Cat(rawB_S.sExp(expWidth), ~rawB_S.sExp(expWidth - 1, 0)).asSInt\n//*** IS THIS OPTIMAL?:\n val sSatExpQuot_S_div =\n Cat(Mux(((BigInt(7)<<(expWidth - 2)).S <= sExpQuot_S_div),\n 6.U,\n sExpQuot_S_div(expWidth + 1, expWidth - 2)\n ),\n sExpQuot_S_div(expWidth - 3, 0)\n ).asSInt\n\n val evenSqrt_S = io.sqrtOp && ! rawA_S.sExp(0)\n val oddSqrt_S = io.sqrtOp && rawA_S.sExp(0)\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val idle = cycleNum === 0.U\n val entering = inReady && io.inValid\n val entering_normalCase = entering && normalCase_S\n\n val processTwoBits = cycleNum >= 3.U && ((options & divSqrtOpt_twoBitsPerCycle) != 0).B\n val skipCycle2 = cycleNum === 3.U && sigX_Z(sigWidth + 1) && ((options & divSqrtOpt_twoBitsPerCycle) == 0).B\n\n when (! idle || entering) {\n def computeCycleNum(f: UInt => UInt): UInt = {\n Mux(entering & ! normalCase_S, f(1.U), 0.U) |\n Mux(entering_normalCase,\n Mux(io.sqrtOp,\n Mux(rawA_S.sExp(0), f(sigWidth.U), f((sigWidth + 1).U)),\n f((sigWidth + 2).U)\n ),\n 0.U\n ) |\n Mux(! entering && ! skipCycle2, f(cycleNum - Mux(processTwoBits, 2.U, 1.U)), 0.U) |\n Mux(skipCycle2, f(1.U), 0.U)\n }\n\n inReady := computeCycleNum(_ <= 1.U).asBool\n rawOutValid := computeCycleNum(_ === 1.U).asBool\n cycleNum := computeCycleNum(x => x)\n }\n\n io.inReady := inReady\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n when (entering) {\n sqrtOp_Z := io.sqrtOp\n majorExc_Z := majorExc_S\n isNaN_Z := isNaN_S\n isInf_Z := isInf_S\n isZero_Z := isZero_S\n sign_Z := sign_S\n sExp_Z :=\n Mux(io.sqrtOp,\n (rawA_S.sExp>>1) +& (BigInt(1)<<(expWidth - 1)).S,\n sSatExpQuot_S_div\n )\n roundingMode_Z := io.roundingMode\n }\n when (entering || ! inReady && sqrtOp_Z) {\n fractB_Z :=\n Mux(inReady && ! io.sqrtOp, rawB_S.sig(sigWidth - 2, 0)<<1, 0.U) |\n Mux(inReady && io.sqrtOp && rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 2)).U, 0.U) |\n Mux(inReady && io.sqrtOp && ! rawA_S.sExp(0), (BigInt(1)<<(sigWidth - 1)).U, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && processTwoBits, fractB_Z>>2, 0.U) |\n Mux(! inReady /* sqrtOp_Z */ && ! processTwoBits, fractB_Z>>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n val rem =\n Mux(inReady && ! oddSqrt_S, rawA_S.sig<<1, 0.U) |\n Mux(inReady && oddSqrt_S,\n Cat(rawA_S.sig(sigWidth - 1, sigWidth - 2) - 1.U,\n rawA_S.sig(sigWidth - 3, 0)<<3\n ),\n 0.U\n ) |\n Mux(! inReady, rem_Z<<1, 0.U)\n val bitMask = (1.U<>2\n val trialTerm =\n Mux(inReady && ! io.sqrtOp, rawB_S.sig<<1, 0.U) |\n Mux(inReady && evenSqrt_S, (BigInt(1)<>1 | sigX_Z<<1, fractB_Z | (1.U << sigWidth))\n val trialTerm2_newBit1 = trialTerm2_newBit0 | Mux(sqrtOp_Z, fractB_Z<<1, 0.U)\n val trialRem2 =\n Mux(newBit,\n (trialRem<<1) - trialTerm2_newBit1.zext,\n (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext)\n val newBit2 = (0.S <= trialRem2)\n val nextNotZeroRem_Z = Mux(inReady || newBit, trialRem =/= 0.S, notZeroRem_Z)\n val nextNotZeroRem_Z_2 = // <-> Mux(newBit2, trialRem2 =/= 0.S, nextNotZeroRem_Z)\n processTwoBits && newBit && (0.S < (trialRem<<1) - trialTerm2_newBit1.zext) ||\n processTwoBits && !newBit && (0.S < (rem_Z<<2)(sigWidth+2, 0).zext - trialTerm2_newBit0.zext) ||\n !(processTwoBits && newBit2) && nextNotZeroRem_Z\n val nextRem_Z_2 =\n Mux(processTwoBits && newBit2, trialRem2.asUInt(sigWidth + 1, 0), 0.U) |\n Mux(processTwoBits && !newBit2, rem2(sigWidth + 1, 0), 0.U) |\n Mux(!processTwoBits, nextRem_Z, 0.U)\n\n when (entering || ! inReady) {\n notZeroRem_Z := nextNotZeroRem_Z_2\n rem_Z := nextRem_Z_2\n sigX_Z :=\n Mux(inReady && ! io.sqrtOp, newBit<<(sigWidth + 1), 0.U) |\n Mux(inReady && io.sqrtOp, (BigInt(1)<>1, 0.U)\n }\n\n /*------------------------------------------------------------------------\n *------------------------------------------------------------------------*/\n io.rawOutValid_div := rawOutValid && ! sqrtOp_Z\n io.rawOutValid_sqrt := rawOutValid && sqrtOp_Z\n io.roundingModeOut := roundingMode_Z\n io.invalidExc := majorExc_Z && isNaN_Z\n io.infiniteExc := majorExc_Z && ! isNaN_Z\n io.rawOut.isNaN := isNaN_Z\n io.rawOut.isInf := isInf_Z\n io.rawOut.isZero := isZero_Z\n io.rawOut.sign := sign_Z\n io.rawOut.sExp := sExp_Z\n io.rawOut.sig := sigX_Z<<1 | notZeroRem_Z\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFNToRaw_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFMToRaw_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val rawOutValid_div = Output(Bool())\n val rawOutValid_sqrt = Output(Bool())\n val roundingModeOut = Output(UInt(3.W))\n val invalidExc = Output(Bool())\n val infiniteExc = Output(Bool())\n val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))\n })\n\n val divSqrtRawFN =\n Module(new DivSqrtRawFN_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRawFN.io.inReady\n divSqrtRawFN.io.inValid := io.inValid\n divSqrtRawFN.io.sqrtOp := io.sqrtOp\n divSqrtRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)\n divSqrtRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)\n divSqrtRawFN.io.roundingMode := io.roundingMode\n\n io.rawOutValid_div := divSqrtRawFN.io.rawOutValid_div\n io.rawOutValid_sqrt := divSqrtRawFN.io.rawOutValid_sqrt\n io.roundingModeOut := divSqrtRawFN.io.roundingModeOut\n io.invalidExc := divSqrtRawFN.io.invalidExc\n io.infiniteExc := divSqrtRawFN.io.infiniteExc\n io.rawOut := divSqrtRawFN.io.rawOut\n\n}\n\n/*----------------------------------------------------------------------------\n*----------------------------------------------------------------------------*/\n\nclass\n DivSqrtRecFN_small(expWidth: Int, sigWidth: Int, options: Int)\n extends Module\n{\n override def desiredName = s\"DivSqrtRecFM_small_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val inReady = Output(Bool())\n val inValid = Input(Bool())\n val sqrtOp = Input(Bool())\n val a = Input(UInt((expWidth + sigWidth + 1).W))\n val b = Input(UInt((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n /*--------------------------------------------------------------------\n *--------------------------------------------------------------------*/\n val outValid_div = Output(Bool())\n val outValid_sqrt = Output(Bool())\n val out = Output(UInt((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(UInt(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val divSqrtRecFNToRaw =\n Module(new DivSqrtRecFNToRaw_small(expWidth, sigWidth, options))\n\n io.inReady := divSqrtRecFNToRaw.io.inReady\n divSqrtRecFNToRaw.io.inValid := io.inValid\n divSqrtRecFNToRaw.io.sqrtOp := io.sqrtOp\n divSqrtRecFNToRaw.io.a := io.a\n divSqrtRecFNToRaw.io.b := io.b\n divSqrtRecFNToRaw.io.roundingMode := io.roundingMode\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n io.outValid_div := divSqrtRecFNToRaw.io.rawOutValid_div\n io.outValid_sqrt := divSqrtRecFNToRaw.io.rawOutValid_sqrt\n\n val roundRawFNToRecFN =\n Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))\n roundRawFNToRecFN.io.invalidExc := divSqrtRecFNToRaw.io.invalidExc\n roundRawFNToRecFN.io.infiniteExc := divSqrtRecFNToRaw.io.infiniteExc\n roundRawFNToRecFN.io.in := divSqrtRecFNToRaw.io.rawOut\n roundRawFNToRecFN.io.roundingMode := divSqrtRecFNToRaw.io.roundingModeOut\n roundRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n\n}", + "response": "module DivSqrtRawFN_small_e11_s53(\n input clock,\n input reset,\n output io_inReady,\n input io_inValid,\n input io_sqrtOp,\n input io_a_isNaN,\n input io_a_isInf,\n input io_a_isZero,\n input io_a_sign,\n input [12:0] io_a_sExp,\n input [53:0] io_a_sig,\n input io_b_isNaN,\n input io_b_isInf,\n input io_b_isZero,\n input io_b_sign,\n input [12:0] io_b_sExp,\n input [53:0] io_b_sig,\n input [2:0] io_roundingMode,\n output io_rawOutValid_div,\n output io_rawOutValid_sqrt,\n output [2:0] io_roundingModeOut,\n output io_invalidExc,\n output io_infiniteExc,\n output io_rawOut_isNaN,\n output io_rawOut_isInf,\n output io_rawOut_isZero,\n output io_rawOut_sign,\n output [12:0] io_rawOut_sExp,\n output [55:0] io_rawOut_sig\n);\n\n reg [5:0] cycleNum;\n reg inReady;\n reg rawOutValid;\n reg sqrtOp_Z;\n reg majorExc_Z;\n reg isNaN_Z;\n reg isInf_Z;\n reg isZero_Z;\n reg sign_Z;\n reg [12:0] sExp_Z;\n reg [52:0] fractB_Z;\n reg [2:0] roundingMode_Z;\n reg [54:0] rem_Z;\n reg notZeroRem_Z;\n reg [54:0] sigX_Z;\n wire specialCaseA_S = io_a_isNaN | io_a_isInf | io_a_isZero;\n wire normalCase_S = io_sqrtOp ? ~specialCaseA_S & ~io_a_sign : ~specialCaseA_S & ~(io_b_isNaN | io_b_isInf | io_b_isZero);\n wire skipCycle2 = cycleNum == 6'h3 & sigX_Z[54];\n wire notSigNaNIn_invalidExc_S_div = io_a_isZero & io_b_isZero | io_a_isInf & io_b_isInf;\n wire notSigNaNIn_invalidExc_S_sqrt = ~io_a_isNaN & ~io_a_isZero & io_a_sign;\n wire [13:0] sExpQuot_S_div = {io_a_sExp[12], io_a_sExp} + {{3{io_b_sExp[11]}}, ~(io_b_sExp[10:0])};\n wire [52:0] _fractB_Z_T_4 = inReady & ~io_sqrtOp ? {io_b_sig[51:0], 1'h0} : 53'h0;\n wire _fractB_Z_T_10 = inReady & io_sqrtOp;\n wire [63:0] _bitMask_T = 64'h1 << cycleNum;\n wire oddSqrt_S = io_sqrtOp & io_a_sExp[0];\n wire entering = inReady & io_inValid;\n wire _sigX_Z_T_7 = inReady & oddSqrt_S;\n wire [55:0] rem = {1'h0, inReady & ~oddSqrt_S ? {io_a_sig, 1'h0} : 55'h0} | (_sigX_Z_T_7 ? {io_a_sig[52:51] - 2'h1, io_a_sig[50:0], 3'h0} : 56'h0) | (inReady ? 56'h0 : {rem_Z, 1'h0});\n wire [54:0] _trialTerm_T_3 = inReady & ~io_sqrtOp ? {io_b_sig, 1'h0} : 55'h0;\n wire [54:0] _trialTerm_T_9 = {_trialTerm_T_3[54], _trialTerm_T_3[53:0] | {inReady & io_sqrtOp & ~(io_a_sExp[0]), 53'h0}} | (_sigX_Z_T_7 ? 55'h50000000000000 : 55'h0);\n wire [57:0] trialRem = {2'h0, rem} - {2'h0, {1'h0, _trialTerm_T_9[54], _trialTerm_T_9[53] | ~inReady & ~sqrtOp_Z, _trialTerm_T_9[52:0] | (inReady ? 53'h0 : fractB_Z)} | (~inReady & sqrtOp_Z ? {sigX_Z, 1'h0} : 56'h0)};\n wire newBit = $signed(trialRem) > -58'sh1;\n wire _GEN = entering | ~inReady;\n wire [5:0] _cycleNum_T_15 = {5'h0, entering & ~normalCase_S} | (entering & normalCase_S ? (io_sqrtOp ? (io_a_sExp[0] ? 6'h35 : 6'h36) : 6'h37) : 6'h0) | (entering | skipCycle2 ? 6'h0 : cycleNum - 6'h1);\n wire [54:0] _sigX_Z_T_3 = inReady & ~io_sqrtOp ? {newBit, 54'h0} : 55'h0;\n wire [53:0] _GEN_0 = _sigX_Z_T_3[53:0] | {inReady & io_sqrtOp, 53'h0};\n always @(posedge clock) begin\n if (reset) begin\n cycleNum <= 6'h0;\n inReady <= 1'h1;\n rawOutValid <= 1'h0;\n end\n else if ((|cycleNum) | entering) begin\n cycleNum <= {_cycleNum_T_15[5:1], _cycleNum_T_15[0] | skipCycle2};\n inReady <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 < 6'h2 | skipCycle2;\n rawOutValid <= entering & ~normalCase_S | ~entering & ~skipCycle2 & cycleNum - 6'h1 == 6'h1 | skipCycle2;\n end\n if (entering) begin\n sqrtOp_Z <= io_sqrtOp;\n majorExc_Z <= io_sqrtOp ? io_a_isNaN & ~(io_a_sig[51]) | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN & ~(io_a_sig[51]) | io_b_isNaN & ~(io_b_sig[51]) | notSigNaNIn_invalidExc_S_div | ~io_a_isNaN & ~io_a_isInf & io_b_isZero;\n isNaN_Z <= io_sqrtOp ? io_a_isNaN | notSigNaNIn_invalidExc_S_sqrt : io_a_isNaN | io_b_isNaN | notSigNaNIn_invalidExc_S_div;\n isInf_Z <= ~io_sqrtOp & io_b_isZero | io_a_isInf;\n isZero_Z <= ~io_sqrtOp & io_b_isInf | io_a_isZero;\n sign_Z <= io_a_sign ^ ~io_sqrtOp & io_b_sign;\n sExp_Z <= io_sqrtOp ? {io_a_sExp[12], io_a_sExp[12:1]} + 13'h400 : {$signed(sExpQuot_S_div) > 14'shDFF ? 4'h6 : sExpQuot_S_div[12:9], sExpQuot_S_div[8:0]};\n roundingMode_Z <= io_roundingMode;\n end\n if (entering | ~inReady & sqrtOp_Z)\n fractB_Z <= {_fractB_Z_T_4[52] | _fractB_Z_T_10 & ~(io_a_sExp[0]), _fractB_Z_T_4[51:0] | {_fractB_Z_T_10 & io_a_sExp[0], 51'h0} | (inReady ? 52'h0 : fractB_Z[52:1])};\n if (_GEN) begin\n rem_Z <= newBit ? trialRem[54:0] : rem[54:0];\n sigX_Z <= {_sigX_Z_T_3[54], _GEN_0[53], _GEN_0[52:0] | (_sigX_Z_T_7 ? {newBit, 52'h0} : 53'h0)} | (inReady ? 55'h0 : sigX_Z) | (~inReady & newBit ? _bitMask_T[56:2] : 55'h0);\n end\n if (_GEN & (inReady | newBit))\n notZeroRem_Z <= |trialRem;\n end\n assign io_inReady = inReady;\n assign io_rawOutValid_div = rawOutValid & ~sqrtOp_Z;\n assign io_rawOutValid_sqrt = rawOutValid & sqrtOp_Z;\n assign io_roundingModeOut = roundingMode_Z;\n assign io_invalidExc = majorExc_Z & isNaN_Z;\n assign io_infiniteExc = majorExc_Z & ~isNaN_Z;\n assign io_rawOut_isNaN = isNaN_Z;\n assign io_rawOut_isInf = isInf_Z;\n assign io_rawOut_isZero = isZero_Z;\n assign io_rawOut_sign = sign_Z;\n assign io_rawOut_sExp = sExp_Z;\n assign io_rawOut_sig = {sigX_Z, notZeroRem_Z};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module array_3_0_0(\n input [8:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [8:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n array_0_0_0_ext array_0_0_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_6(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module TageTable(\n input clock,\n input reset,\n input io_f1_req_valid,\n input [39:0] io_f1_req_pc,\n input [63:0] io_f1_req_ghist,\n output io_f3_resp_0_valid,\n output [2:0] io_f3_resp_0_bits_ctr,\n output [1:0] io_f3_resp_0_bits_u,\n output io_f3_resp_1_valid,\n output [2:0] io_f3_resp_1_bits_ctr,\n output [1:0] io_f3_resp_1_bits_u,\n output io_f3_resp_2_valid,\n output [2:0] io_f3_resp_2_bits_ctr,\n output [1:0] io_f3_resp_2_bits_u,\n output io_f3_resp_3_valid,\n output [2:0] io_f3_resp_3_bits_ctr,\n output [1:0] io_f3_resp_3_bits_u,\n input io_update_mask_0,\n input io_update_mask_1,\n input io_update_mask_2,\n input io_update_mask_3,\n input io_update_taken_0,\n input io_update_taken_1,\n input io_update_taken_2,\n input io_update_taken_3,\n input io_update_alloc_0,\n input io_update_alloc_1,\n input io_update_alloc_2,\n input io_update_alloc_3,\n input [2:0] io_update_old_ctr_0,\n input [2:0] io_update_old_ctr_1,\n input [2:0] io_update_old_ctr_2,\n input [2:0] io_update_old_ctr_3,\n input [39:0] io_update_pc,\n input [63:0] io_update_hist,\n input io_update_u_mask_0,\n input io_update_u_mask_1,\n input io_update_u_mask_2,\n input io_update_u_mask_3,\n input [1:0] io_update_u_0,\n input [1:0] io_update_u_1,\n input [1:0] io_update_u_2,\n input [1:0] io_update_u_3\n);\n\n wire update_lo_wdata_3;\n wire update_hi_wdata_3;\n wire [2:0] update_wdata_3_ctr;\n wire update_lo_wdata_2;\n wire update_hi_wdata_2;\n wire [2:0] update_wdata_2_ctr;\n wire update_lo_wdata_1;\n wire update_hi_wdata_1;\n wire [2:0] update_wdata_1_ctr;\n wire update_lo_wdata_0;\n wire update_hi_wdata_0;\n wire [2:0] update_wdata_0_ctr;\n wire lo_us_MPORT_2_data_3;\n wire lo_us_MPORT_2_data_2;\n wire lo_us_MPORT_2_data_1;\n wire lo_us_MPORT_2_data_0;\n wire hi_us_MPORT_1_data_3;\n wire hi_us_MPORT_1_data_2;\n wire hi_us_MPORT_1_data_1;\n wire hi_us_MPORT_1_data_0;\n wire [10:0] table_MPORT_data_3;\n wire [10:0] table_MPORT_data_2;\n wire [10:0] table_MPORT_data_1;\n wire [10:0] table_MPORT_data_0;\n wire [43:0] _table_R0_data;\n wire [3:0] _lo_us_R0_data;\n wire [3:0] _hi_us_R0_data;\n reg doing_reset;\n reg [6:0] reset_idx;\n wire [6:0] s1_hashed_idx = {io_f1_req_pc[9:5], io_f1_req_pc[4:3] ^ io_f1_req_ghist[1:0]};\n reg [6:0] s2_tag;\n reg io_f3_resp_0_valid_REG;\n reg [1:0] io_f3_resp_0_bits_u_REG;\n reg [2:0] io_f3_resp_0_bits_ctr_REG;\n reg io_f3_resp_1_valid_REG;\n reg [1:0] io_f3_resp_1_bits_u_REG;\n reg [2:0] io_f3_resp_1_bits_ctr_REG;\n reg io_f3_resp_2_valid_REG;\n reg [1:0] io_f3_resp_2_bits_u_REG;\n reg [2:0] io_f3_resp_2_bits_ctr_REG;\n reg io_f3_resp_3_valid_REG;\n reg [1:0] io_f3_resp_3_bits_u_REG;\n reg [2:0] io_f3_resp_3_bits_ctr_REG;\n reg [18:0] clear_u_ctr;\n wire doing_clear_u = clear_u_ctr[10:0] == 11'h0;\n wire doing_clear_u_hi = doing_clear_u & clear_u_ctr[18];\n wire doing_clear_u_lo = doing_clear_u & ~(clear_u_ctr[18]);\n wire [1:0] _GEN = io_update_pc[4:3] ^ io_update_hist[1:0];\n wire [6:0] update_idx = {io_update_pc[9:5], _GEN};\n wire [1:0] _GEN_0 = io_update_pc[11:10] ^ io_update_hist[1:0];\n wire [6:0] update_tag = {io_update_pc[16:12], _GEN_0};\n assign table_MPORT_data_0 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:12], _GEN_0, update_wdata_0_ctr};\n assign table_MPORT_data_1 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:12], _GEN_0, update_wdata_1_ctr};\n assign table_MPORT_data_2 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:12], _GEN_0, update_wdata_2_ctr};\n assign table_MPORT_data_3 = doing_reset ? 11'h0 : {1'h1, io_update_pc[16:12], _GEN_0, update_wdata_3_ctr};\n wire [6:0] _GEN_1 = {io_update_pc[9:5], _GEN};\n wire _GEN_2 = doing_reset | doing_clear_u_hi;\n assign hi_us_MPORT_1_data_0 = ~_GEN_2 & update_hi_wdata_0;\n assign hi_us_MPORT_1_data_1 = ~_GEN_2 & update_hi_wdata_1;\n assign hi_us_MPORT_1_data_2 = ~_GEN_2 & update_hi_wdata_2;\n assign hi_us_MPORT_1_data_3 = ~_GEN_2 & update_hi_wdata_3;\n wire [3:0] _GEN_3 = {io_update_u_mask_3, io_update_u_mask_2, io_update_u_mask_1, io_update_u_mask_0};\n wire _GEN_4 = doing_reset | doing_clear_u_lo;\n assign lo_us_MPORT_2_data_0 = ~_GEN_4 & update_lo_wdata_0;\n assign lo_us_MPORT_2_data_1 = ~_GEN_4 & update_lo_wdata_1;\n assign lo_us_MPORT_2_data_2 = ~_GEN_4 & update_lo_wdata_2;\n assign lo_us_MPORT_2_data_3 = ~_GEN_4 & update_lo_wdata_3;\n reg [6:0] wrbypass_tags_0;\n reg [6:0] wrbypass_tags_1;\n reg [6:0] wrbypass_idxs_0;\n reg [6:0] wrbypass_idxs_1;\n reg [2:0] wrbypass_0_0;\n reg [2:0] wrbypass_0_1;\n reg [2:0] wrbypass_0_2;\n reg [2:0] wrbypass_0_3;\n reg [2:0] wrbypass_1_0;\n reg [2:0] wrbypass_1_1;\n reg [2:0] wrbypass_1_2;\n reg [2:0] wrbypass_1_3;\n reg wrbypass_enq_idx;\n wire wrbypass_hits_0 = ~doing_reset & wrbypass_tags_0 == update_tag & wrbypass_idxs_0 == update_idx;\n wire wrbypass_hit = wrbypass_hits_0 | ~doing_reset & wrbypass_tags_1 == update_tag & wrbypass_idxs_1 == update_idx;\n wire [2:0] _GEN_5 = wrbypass_hits_0 ? wrbypass_0_0 : wrbypass_1_0;\n wire [2:0] _GEN_6 = wrbypass_hits_0 ? wrbypass_0_1 : wrbypass_1_1;\n wire [2:0] _GEN_7 = wrbypass_hits_0 ? wrbypass_0_2 : wrbypass_1_2;\n wire [2:0] _GEN_8 = wrbypass_hits_0 ? wrbypass_0_3 : wrbypass_1_3;\n assign update_wdata_0_ctr = io_update_alloc_0 ? (io_update_taken_0 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_0 ? ((&_GEN_5) ? 3'h7 : _GEN_5 + 3'h1) : _GEN_5 == 3'h0 ? 3'h0 : _GEN_5 - 3'h1) : io_update_taken_0 ? ((&io_update_old_ctr_0) ? 3'h7 : io_update_old_ctr_0 + 3'h1) : io_update_old_ctr_0 == 3'h0 ? 3'h0 : io_update_old_ctr_0 - 3'h1;\n assign update_hi_wdata_0 = io_update_u_0[1];\n assign update_lo_wdata_0 = io_update_u_0[0];\n assign update_wdata_1_ctr = io_update_alloc_1 ? (io_update_taken_1 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_1 ? ((&_GEN_6) ? 3'h7 : _GEN_6 + 3'h1) : _GEN_6 == 3'h0 ? 3'h0 : _GEN_6 - 3'h1) : io_update_taken_1 ? ((&io_update_old_ctr_1) ? 3'h7 : io_update_old_ctr_1 + 3'h1) : io_update_old_ctr_1 == 3'h0 ? 3'h0 : io_update_old_ctr_1 - 3'h1;\n assign update_hi_wdata_1 = io_update_u_1[1];\n assign update_lo_wdata_1 = io_update_u_1[0];\n assign update_wdata_2_ctr = io_update_alloc_2 ? (io_update_taken_2 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_2 ? ((&_GEN_7) ? 3'h7 : _GEN_7 + 3'h1) : _GEN_7 == 3'h0 ? 3'h0 : _GEN_7 - 3'h1) : io_update_taken_2 ? ((&io_update_old_ctr_2) ? 3'h7 : io_update_old_ctr_2 + 3'h1) : io_update_old_ctr_2 == 3'h0 ? 3'h0 : io_update_old_ctr_2 - 3'h1;\n assign update_hi_wdata_2 = io_update_u_2[1];\n assign update_lo_wdata_2 = io_update_u_2[0];\n assign update_wdata_3_ctr = io_update_alloc_3 ? (io_update_taken_3 ? 3'h4 : 3'h3) : wrbypass_hit ? (io_update_taken_3 ? ((&_GEN_8) ? 3'h7 : _GEN_8 + 3'h1) : _GEN_8 == 3'h0 ? 3'h0 : _GEN_8 - 3'h1) : io_update_taken_3 ? ((&io_update_old_ctr_3) ? 3'h7 : io_update_old_ctr_3 + 3'h1) : io_update_old_ctr_3 == 3'h0 ? 3'h0 : io_update_old_ctr_3 - 3'h1;\n assign update_hi_wdata_3 = io_update_u_3[1];\n assign update_lo_wdata_3 = io_update_u_3[0];\n wire _GEN_9 = io_update_mask_0 | io_update_mask_1 | io_update_mask_2 | io_update_mask_3;\n wire _GEN_10 = ~_GEN_9 | wrbypass_hit | wrbypass_enq_idx;\n wire _GEN_11 = ~_GEN_9 | wrbypass_hit | ~wrbypass_enq_idx;\n always @(posedge clock) begin\n if (reset) begin\n doing_reset <= 1'h1;\n reset_idx <= 7'h0;\n clear_u_ctr <= 19'h0;\n wrbypass_enq_idx <= 1'h0;\n end\n else begin\n doing_reset <= reset_idx != 7'h7F & doing_reset;\n reset_idx <= reset_idx + {6'h0, doing_reset};\n clear_u_ctr <= doing_reset ? 19'h1 : clear_u_ctr + 19'h1;\n if (~_GEN_9 | wrbypass_hit) begin\n end\n else\n wrbypass_enq_idx <= wrbypass_enq_idx - 1'h1;\n end\n s2_tag <= {io_f1_req_pc[16:12], io_f1_req_pc[11:10] ^ io_f1_req_ghist[1:0]};\n io_f3_resp_0_valid_REG <= _table_R0_data[10] & _table_R0_data[9:3] == s2_tag & ~doing_reset;\n io_f3_resp_0_bits_u_REG <= {_hi_us_R0_data[0], _lo_us_R0_data[0]};\n io_f3_resp_0_bits_ctr_REG <= _table_R0_data[2:0];\n io_f3_resp_1_valid_REG <= _table_R0_data[21] & _table_R0_data[20:14] == s2_tag & ~doing_reset;\n io_f3_resp_1_bits_u_REG <= {_hi_us_R0_data[1], _lo_us_R0_data[1]};\n io_f3_resp_1_bits_ctr_REG <= _table_R0_data[13:11];\n io_f3_resp_2_valid_REG <= _table_R0_data[32] & _table_R0_data[31:25] == s2_tag & ~doing_reset;\n io_f3_resp_2_bits_u_REG <= {_hi_us_R0_data[2], _lo_us_R0_data[2]};\n io_f3_resp_2_bits_ctr_REG <= _table_R0_data[24:22];\n io_f3_resp_3_valid_REG <= _table_R0_data[43] & _table_R0_data[42:36] == s2_tag & ~doing_reset;\n io_f3_resp_3_bits_u_REG <= {_hi_us_R0_data[3], _lo_us_R0_data[3]};\n io_f3_resp_3_bits_ctr_REG <= _table_R0_data[35:33];\n if (_GEN_10) begin\n end\n else\n wrbypass_tags_0 <= update_tag;\n if (_GEN_11) begin\n end\n else\n wrbypass_tags_1 <= update_tag;\n if (_GEN_10) begin\n end\n else\n wrbypass_idxs_0 <= update_idx;\n if (_GEN_11) begin\n end\n else\n wrbypass_idxs_1 <= update_idx;\n if (_GEN_9) begin\n if (wrbypass_hit) begin\n if (wrbypass_hits_0) begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n end\n else if (wrbypass_enq_idx) begin\n wrbypass_1_0 <= update_wdata_0_ctr;\n wrbypass_1_1 <= update_wdata_1_ctr;\n wrbypass_1_2 <= update_wdata_2_ctr;\n wrbypass_1_3 <= update_wdata_3_ctr;\n end\n else begin\n wrbypass_0_0 <= update_wdata_0_ctr;\n wrbypass_0_1 <= update_wdata_1_ctr;\n wrbypass_0_2 <= update_wdata_2_ctr;\n wrbypass_0_3 <= update_wdata_3_ctr;\n end\n end\n end\n hi_us hi_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_hi_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_ctr[17:11] : _GEN_1),\n .W0_clk (clock),\n .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}),\n .W0_mask (_GEN_2 ? 4'hF : _GEN_3)\n );\n lo_us lo_us (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_lo_us_R0_data),\n .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_ctr[17:11] : _GEN_1),\n .W0_clk (clock),\n .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}),\n .W0_mask (_GEN_4 ? 4'hF : _GEN_3)\n );\n table_0 table_0 (\n .R0_addr (s1_hashed_idx),\n .R0_en (io_f1_req_valid),\n .R0_clk (clock),\n .R0_data (_table_R0_data),\n .W0_addr (doing_reset ? reset_idx : update_idx),\n .W0_clk (clock),\n .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}),\n .W0_mask (doing_reset ? 4'hF : {io_update_mask_3, io_update_mask_2, io_update_mask_1, io_update_mask_0})\n );\n assign io_f3_resp_0_valid = io_f3_resp_0_valid_REG;\n assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_REG;\n assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_REG;\n assign io_f3_resp_1_valid = io_f3_resp_1_valid_REG;\n assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_REG;\n assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_REG;\n assign io_f3_resp_2_valid = io_f3_resp_2_valid_REG;\n assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_REG;\n assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_REG;\n assign io_f3_resp_3_valid = io_f3_resp_3_valid_REG;\n assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_REG;\n assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_REG;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.experimental.SourceInfo\nimport freechips.rocketchip.tilelink._\nimport TLPermissions._\nimport TLMessages._\nimport MetaData._\nimport chisel3.PrintableHelper\nimport chisel3.experimental.dataview._\n\nclass ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val a = Valid(new SourceARequest(params))\n val b = Valid(new SourceBRequest(params))\n val c = Valid(new SourceCRequest(params))\n val d = Valid(new SourceDRequest(params))\n val e = Valid(new SourceERequest(params))\n val x = Valid(new SourceXRequest(params))\n val dir = Valid(new DirectoryWrite(params))\n val reload = Bool() // get next request via allocate (if any)\n}\n\nclass MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val tag = UInt(params.tagBits.W)\n val way = UInt(params.wayBits.W)\n val blockB = Bool()\n val nestB = Bool()\n val blockC = Bool()\n val nestC = Bool()\n}\n\nclass NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val set = UInt(params.setBits.W)\n val tag = UInt(params.tagBits.W)\n val b_toN = Bool() // nested Probes may unhit us\n val b_toB = Bool() // nested Probes may demote us\n val b_clr_dirty = Bool() // nested Probes clear dirty\n val c_set_dirty = Bool() // nested Releases MAY set dirty\n}\n\nsealed trait CacheState\n{\n val code = CacheState.index.U\n CacheState.index = CacheState.index + 1\n}\n\nobject CacheState\n{\n var index = 0\n}\n\ncase object S_INVALID extends CacheState\ncase object S_BRANCH extends CacheState\ncase object S_BRANCH_C extends CacheState\ncase object S_TIP extends CacheState\ncase object S_TIP_C extends CacheState\ncase object S_TIP_CD extends CacheState\ncase object S_TIP_D extends CacheState\ncase object S_TRUNK_C extends CacheState\ncase object S_TRUNK_CD extends CacheState\n\nclass MSHR(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle\n val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup\n val status = Valid(new MSHRStatus(params))\n val schedule = Decoupled(new ScheduleRequest(params))\n val sinkc = Flipped(Valid(new SinkCResponse(params)))\n val sinkd = Flipped(Valid(new SinkDResponse(params)))\n val sinke = Flipped(Valid(new SinkEResponse(params)))\n val nestedwb = Flipped(new NestedWriteback(params))\n })\n\n val request_valid = RegInit(false.B)\n val request = Reg(new FullRequest(params))\n val meta_valid = RegInit(false.B)\n val meta = Reg(new DirectoryResult(params))\n\n // Define which states are valid\n when (meta_valid) {\n when (meta.state === INVALID) {\n assert (!meta.clients.orR)\n assert (!meta.dirty)\n }\n when (meta.state === BRANCH) {\n assert (!meta.dirty)\n }\n when (meta.state === TRUNK) {\n assert (meta.clients.orR)\n assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n }\n when (meta.state === TIP) {\n // noop\n }\n }\n\n // Completed transitions (s_ = scheduled), (w_ = waiting)\n val s_rprobe = RegInit(true.B) // B\n val w_rprobeackfirst = RegInit(true.B)\n val w_rprobeacklast = RegInit(true.B)\n val s_release = RegInit(true.B) // CW w_rprobeackfirst\n val w_releaseack = RegInit(true.B)\n val s_pprobe = RegInit(true.B) // B\n val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]\n val s_flush = RegInit(true.B) // X w_releaseack\n val w_grantfirst = RegInit(true.B)\n val w_grantlast = RegInit(true.B)\n val w_grant = RegInit(true.B) // first | last depending on wormhole\n val w_pprobeackfirst = RegInit(true.B)\n val w_pprobeacklast = RegInit(true.B)\n val w_pprobeack = RegInit(true.B) // first | last depending on wormhole\n val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)\n val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD\n val s_execute = RegInit(true.B) // D w_pprobeack, w_grant\n val w_grantack = RegInit(true.B)\n val s_writeback = RegInit(true.B) // W w_*\n\n // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)\n // However, inB and outC are higher priority than outB, so s_release and s_pprobe\n // may be safely issued while blockB. Thus we must NOT try to schedule the\n // potentially stuck s_acquire with either of them (scheduler is all or none).\n\n // Meta-data that we discover underway\n val sink = Reg(UInt(params.outer.bundle.sinkBits.W))\n val gotT = Reg(Bool())\n val bad_grant = Reg(Bool())\n val probes_done = Reg(UInt(params.clientBits.W))\n val probes_toN = Reg(UInt(params.clientBits.W))\n val probes_noT = Reg(Bool())\n\n // When a nested transaction completes, update our meta data\n when (meta_valid && meta.state =/= INVALID &&\n io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {\n when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }\n when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }\n when (io.nestedwb.b_toB) { meta.state := BRANCH }\n when (io.nestedwb.b_toN) { meta.hit := false.B }\n }\n\n // Scheduler status\n io.status.valid := request_valid\n io.status.bits.set := request.set\n io.status.bits.tag := request.tag\n io.status.bits.way := meta.way\n io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)\n io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst\n // The above rules ensure we will block and not nest an outer probe while still doing our\n // own inner probes. Thus every probe wakes exactly one MSHR.\n io.status.bits.blockC := !meta_valid\n io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)\n // The w_grantfirst in nestC is necessary to deal with:\n // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock\n // ... this is possible because the release+probe can be for same set, but different tag\n\n // We can only demand: block, nest, or queue\n assert (!io.status.bits.nestB || !io.status.bits.blockB)\n assert (!io.status.bits.nestC || !io.status.bits.blockC)\n\n // Scheduler requests\n val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack\n io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe\n io.schedule.bits.b.valid := !s_rprobe || !s_pprobe\n io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)\n io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant\n io.schedule.bits.e.valid := !s_grantack && w_grantfirst\n io.schedule.bits.x.valid := !s_flush && w_releaseack\n io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)\n io.schedule.bits.reload := no_wait\n io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||\n io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||\n io.schedule.bits.dir.valid\n\n // Schedule completions\n when (io.schedule.ready) {\n s_rprobe := true.B\n when (w_rprobeackfirst) { s_release := true.B }\n s_pprobe := true.B\n when (s_release && s_pprobe) { s_acquire := true.B }\n when (w_releaseack) { s_flush := true.B }\n when (w_pprobeackfirst) { s_probeack := true.B }\n when (w_grantfirst) { s_grantack := true.B }\n when (w_pprobeack && w_grant) { s_execute := true.B }\n when (no_wait) { s_writeback := true.B }\n // Await the next operation\n when (no_wait) {\n request_valid := false.B\n meta_valid := false.B\n }\n }\n\n // Resulting meta-data\n val final_meta_writeback = WireInit(meta)\n\n val req_clientBit = params.clientBit(request.source)\n val req_needT = needT(request.opcode, request.param)\n val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm\n val meta_no_clients = !meta.clients.orR\n val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)\n\n when (request.prio(2) && (!params.firstLevel).B) { // always a hit\n final_meta_writeback.dirty := meta.dirty || request.opcode(0)\n final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)\n final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)\n final_meta_writeback.hit := true.B // chained requests are hits\n } .elsewhen (request.control && params.control.B) { // request.prio(0)\n when (meta.hit) {\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := INVALID\n final_meta_writeback.clients := meta.clients & ~probes_toN\n }\n final_meta_writeback.hit := false.B\n } .otherwise {\n final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)\n final_meta_writeback.state := Mux(req_needT,\n Mux(req_acquire, TRUNK, TIP),\n Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),\n MuxLookup(meta.state, 0.U(2.W))(Seq(\n INVALID -> BRANCH,\n BRANCH -> BRANCH,\n TRUNK -> TIP,\n TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))\n final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |\n Mux(req_acquire, req_clientBit, 0.U)\n final_meta_writeback.tag := request.tag\n final_meta_writeback.hit := true.B\n }\n\n when (bad_grant) {\n when (meta.hit) {\n // upgrade failed (B -> T)\n assert (!meta_valid || meta.state === BRANCH)\n final_meta_writeback.hit := true.B\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := BRANCH\n final_meta_writeback.clients := meta.clients & ~probes_toN\n } .otherwise {\n // failed N -> (T or B)\n final_meta_writeback.hit := false.B\n final_meta_writeback.dirty := false.B\n final_meta_writeback.state := INVALID\n final_meta_writeback.clients := 0.U\n }\n }\n\n val invalid = Wire(new DirectoryEntry(params))\n invalid.dirty := false.B\n invalid.state := INVALID\n invalid.clients := 0.U\n invalid.tag := 0.U\n\n // Just because a client says BtoT, by the time we process the request he may be N.\n // Therefore, we must consult our own meta-data state to confirm he owns the line still.\n val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR\n\n // The client asking us to act is proof they don't have permissions.\n val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)\n io.schedule.bits.a.bits.tag := request.tag\n io.schedule.bits.a.bits.set := request.set\n io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)\n io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||\n !(request.opcode === PutFullData || request.opcode === AcquirePerm)\n io.schedule.bits.a.bits.source := 0.U\n io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))\n io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)\n io.schedule.bits.b.bits.set := request.set\n io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client\n io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)\n io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)\n io.schedule.bits.c.bits.source := 0.U\n io.schedule.bits.c.bits.tag := meta.tag\n io.schedule.bits.c.bits.set := request.set\n io.schedule.bits.c.bits.way := meta.way\n io.schedule.bits.c.bits.dirty := meta.dirty\n io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request\n io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,\n MuxLookup(request.param, request.param)(Seq(\n NtoB -> Mux(req_promoteT, NtoT, NtoB),\n BtoT -> Mux(honour_BtoT, BtoT, NtoT),\n NtoT -> NtoT)))\n io.schedule.bits.d.bits.sink := 0.U\n io.schedule.bits.d.bits.way := meta.way\n io.schedule.bits.d.bits.bad := bad_grant\n io.schedule.bits.e.bits.sink := sink\n io.schedule.bits.x.bits.fail := false.B\n io.schedule.bits.dir.bits.set := request.set\n io.schedule.bits.dir.bits.way := meta.way\n io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))\n\n // Coverage of state transitions\n def cacheState(entry: DirectoryEntry, hit: Bool) = {\n val out = WireDefault(0.U)\n val c = entry.clients.orR\n val d = entry.dirty\n switch (entry.state) {\n is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }\n is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }\n is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }\n is (INVALID) { out := S_INVALID.code }\n }\n when (!hit) { out := S_INVALID.code }\n out\n }\n\n val p = !params.lastLevel // can be probed\n val c = !params.firstLevel // can be acquired\n val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)\n val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist\n val f = params.control // flush control register exists\n val cfg = (p, c, m, r, f)\n val b = r || p // can reach branch state (via probe downgrade or read-only device)\n\n // The cache must be used for something or we would not be here\n require(c || m)\n\n val evict = cacheState(meta, !meta.hit)\n val before = cacheState(meta, meta.hit)\n val after = cacheState(final_meta_writeback, true.B)\n\n def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(evict === from.code, s\"MSHR_${from}_EVICT\", s\"State transition from ${from} to evicted ${cfg}\")\n } else {\n assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n }\n if (cover && f) {\n params.ccover(before === from.code, s\"MSHR_${from}_FLUSH\", s\"State transition from ${from} to flushed ${cfg}\")\n } else {\n assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n }\n }\n\n def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(before === from.code && after === to.code, s\"MSHR_${from}_${to}\", s\"State transition from ${from} to ${to} ${cfg}\")\n } else {\n assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n }\n }\n\n when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {\n eviction(S_BRANCH, b) // MMIO read to read-only device\n eviction(S_BRANCH_C, b && c) // you need children to become C\n eviction(S_TIP, true) // MMIO read || clean release can lead to this state\n eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client\n eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client\n eviction(S_TIP_D, true) // MMIO write || dirty release lead here\n eviction(S_TRUNK_C, c) // acquire for write\n eviction(S_TRUNK_CD, c) // dirty release then reacquire\n }\n\n when ((!s_writeback && no_wait) && io.schedule.ready) {\n transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state\n transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches\n transition(S_INVALID, S_TIP, m) // MMIO read\n transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately\n transition(S_INVALID, S_TIP_D, m) // MMIO write\n transition(S_INVALID, S_TRUNK_C, c) // acquire\n transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)\n transition(S_BRANCH, S_BRANCH_C, b && c) // acquire\n transition(S_BRANCH, S_TIP, b && m) // prefetch write\n transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately\n transition(S_BRANCH, S_TIP_D, b && m) // MMIO write\n transition(S_BRANCH, S_TRUNK_C, b && c) // acquire\n transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_BRANCH_C, S_INVALID, b && c && p)\n transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)\n transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write\n transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write\n transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients\n transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire\n transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately\n\n transition(S_TIP, S_INVALID, p)\n transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe\n transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write\n transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately\n transition(S_TIP, S_TRUNK_C, c) // acquire\n transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately\n\n transition(S_TIP_C, S_INVALID, c && p)\n transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe\n transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe\n transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)\n transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write\n transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients\n transition(S_TIP_C, S_TRUNK_C, c) // acquire\n transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty\n\n transition(S_TIP_D, S_INVALID, p)\n transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe\n transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared\n transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead\n transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired\n transition(S_TIP_D, S_TRUNK_CD, c) // acquire\n\n transition(S_TIP_CD, S_INVALID, c && p)\n transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe\n transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe\n transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)\n transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire\n transition(S_TIP_CD, S_TRUNK_CD, c) // acquire\n\n transition(S_TRUNK_C, S_INVALID, c && p)\n transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe\n transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe\n transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)\n transition(S_TRUNK_C, S_TIP_C, c) // bounce shared\n transition(S_TRUNK_C, S_TIP_D, c) // dirty release\n transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared\n transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce\n\n transition(S_TRUNK_CD, S_INVALID, c && p)\n transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe\n transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe\n transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)\n transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead\n transition(S_TRUNK_CD, S_TIP_D, c) // dirty release\n transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared\n transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire\n }\n\n // Handle response messages\n val probe_bit = params.clientBit(io.sinkc.bits.source)\n val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)\n val probe_toN = isToN(io.sinkc.bits.param)\n if (!params.firstLevel) when (io.sinkc.valid) {\n params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, \"MSHR_PROBE_FULL\", \"Client downgraded to N when asked only to do B\")\n params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, \"MSHR_PROBE_HALF\", \"Client downgraded to B when asked only to do B\")\n // Caution: the probe matches us only in set.\n // We would never allow an outer probe to nest until both w_[rp]probeack complete, so\n // it is safe to just unguardedly update the probe FSM.\n probes_done := probes_done | probe_bit\n probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)\n probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT\n w_rprobeackfirst := w_rprobeackfirst || last_probe\n w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)\n w_pprobeackfirst := w_pprobeackfirst || last_probe\n w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)\n // Allow wormhole routing from sinkC if the first request beat has offset 0\n val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)\n w_pprobeack := w_pprobeack || set_pprobeack\n params.ccover(!set_pprobeack && w_rprobeackfirst, \"MSHR_PROBE_SERIAL\", \"Sequential routing of probe response data\")\n params.ccover( set_pprobeack && w_rprobeackfirst, \"MSHR_PROBE_WORMHOLE\", \"Wormhole routing of probe response data\")\n // However, meta-data updates need to be done more cautiously\n when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!\n }\n when (io.sinkd.valid) {\n when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {\n sink := io.sinkd.bits.sink\n w_grantfirst := true.B\n w_grantlast := io.sinkd.bits.last\n // Record if we need to prevent taking ownership\n bad_grant := io.sinkd.bits.denied\n // Allow wormhole routing for requests whose first beat has offset 0\n w_grant := request.offset === 0.U || io.sinkd.bits.last\n params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, \"MSHR_GRANT_WORMHOLE\", \"Wormhole routing of grant response data\")\n params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, \"MSHR_GRANT_SERIAL\", \"Sequential routing of grant response data\")\n gotT := io.sinkd.bits.param === toT\n }\n .elsewhen (io.sinkd.bits.opcode === ReleaseAck) {\n w_releaseack := true.B\n }\n }\n when (io.sinke.valid) {\n w_grantack := true.B\n }\n\n // Bootstrap new requests\n val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)\n val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)\n val new_request = Mux(io.allocate.valid, allocate_as_full, request)\n val new_needT = needT(new_request.opcode, new_request.param)\n val new_clientBit = params.clientBit(new_request.source)\n val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)\n\n val prior = cacheState(final_meta_writeback, true.B)\n def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {\n if (cover) {\n params.ccover(prior === from.code, s\"MSHR_${from}_BYPASS\", s\"State bypass transition from ${from} ${cfg}\")\n } else {\n assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n }\n }\n\n when (io.allocate.valid && io.allocate.bits.repeat) {\n bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)\n bypass(S_BRANCH, b) // MMIO read to read-only device\n bypass(S_BRANCH_C, b && c) // you need children to become C\n bypass(S_TIP, true) // MMIO read || clean release can lead to this state\n bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client\n bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client\n bypass(S_TIP_D, true) // MMIO write || dirty release lead here\n bypass(S_TRUNK_C, c) // acquire for write\n bypass(S_TRUNK_CD, c) // dirty release then reacquire\n }\n\n when (io.allocate.valid) {\n assert (!request_valid || (no_wait && io.schedule.fire))\n request_valid := true.B\n request := io.allocate.bits\n }\n\n // Create execution plan\n when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {\n meta_valid := true.B\n meta := new_meta\n probes_done := 0.U\n probes_toN := 0.U\n probes_noT := false.B\n gotT := false.B\n bad_grant := false.B\n\n // These should already be either true or turning true\n // We clear them here explicitly to simplify the mux tree\n s_rprobe := true.B\n w_rprobeackfirst := true.B\n w_rprobeacklast := true.B\n s_release := true.B\n w_releaseack := true.B\n s_pprobe := true.B\n s_acquire := true.B\n s_flush := true.B\n w_grantfirst := true.B\n w_grantlast := true.B\n w_grant := true.B\n w_pprobeackfirst := true.B\n w_pprobeacklast := true.B\n w_pprobeack := true.B\n s_probeack := true.B\n s_grantack := true.B\n s_execute := true.B\n w_grantack := true.B\n s_writeback := true.B\n\n // For C channel requests (ie: Release[Data])\n when (new_request.prio(2) && (!params.firstLevel).B) {\n s_execute := false.B\n // Do we need to go dirty?\n when (new_request.opcode(0) && !new_meta.dirty) {\n s_writeback := false.B\n }\n // Does our state change?\n when (isToB(new_request.param) && new_meta.state === TRUNK) {\n s_writeback := false.B\n }\n // Do our clients change?\n when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {\n s_writeback := false.B\n }\n assert (new_meta.hit)\n }\n // For X channel requests (ie: flush)\n .elsewhen (new_request.control && params.control.B) { // new_request.prio(0)\n s_flush := false.B\n // Do we need to actually do something?\n when (new_meta.hit) {\n s_release := false.B\n w_releaseack := false.B\n // Do we need to shoot-down inner caches?\n when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {\n s_rprobe := false.B\n w_rprobeackfirst := false.B\n w_rprobeacklast := false.B\n }\n }\n }\n // For A channel requests\n .otherwise { // new_request.prio(0) && !new_request.control\n s_execute := false.B\n // Do we need an eviction?\n when (!new_meta.hit && new_meta.state =/= INVALID) {\n s_release := false.B\n w_releaseack := false.B\n // Do we need to shoot-down inner caches?\n when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {\n s_rprobe := false.B\n w_rprobeackfirst := false.B\n w_rprobeacklast := false.B\n }\n }\n // Do we need an acquire?\n when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {\n s_acquire := false.B\n w_grantfirst := false.B\n w_grantlast := false.B\n w_grant := false.B\n s_grantack := false.B\n s_writeback := false.B\n }\n // Do we need a probe?\n when ((!params.firstLevel).B && (new_meta.hit &&\n (new_needT || new_meta.state === TRUNK) &&\n (new_meta.clients & ~new_skipProbe) =/= 0.U)) {\n s_pprobe := false.B\n w_pprobeackfirst := false.B\n w_pprobeacklast := false.B\n w_pprobeack := false.B\n s_writeback := false.B\n }\n // Do we need a grantack?\n when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {\n w_grantack := false.B\n s_writeback := false.B\n }\n // Becomes dirty?\n when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {\n s_writeback := false.B\n }\n }\n }\n}", + "response": "module MSHR(\n input clock,\n input reset,\n input io_allocate_valid,\n input io_allocate_bits_prio_0,\n input io_allocate_bits_prio_2,\n input io_allocate_bits_control,\n input [2:0] io_allocate_bits_opcode,\n input [2:0] io_allocate_bits_param,\n input [2:0] io_allocate_bits_size,\n input [5:0] io_allocate_bits_source,\n input [12:0] io_allocate_bits_tag,\n input [5:0] io_allocate_bits_offset,\n input [5:0] io_allocate_bits_put,\n input [9:0] io_allocate_bits_set,\n input io_allocate_bits_repeat,\n input io_directory_valid,\n input io_directory_bits_dirty,\n input [1:0] io_directory_bits_state,\n input io_directory_bits_clients,\n input [12:0] io_directory_bits_tag,\n input io_directory_bits_hit,\n input [2:0] io_directory_bits_way,\n output io_status_valid,\n output [9:0] io_status_bits_set,\n output [12:0] io_status_bits_tag,\n output [2:0] io_status_bits_way,\n input io_schedule_ready,\n output io_schedule_valid,\n output io_schedule_bits_a_valid,\n output [12:0] io_schedule_bits_a_bits_tag,\n output [9:0] io_schedule_bits_a_bits_set,\n output [2:0] io_schedule_bits_a_bits_param,\n output io_schedule_bits_a_bits_block,\n output io_schedule_bits_c_valid,\n output [2:0] io_schedule_bits_c_bits_opcode,\n output [2:0] io_schedule_bits_c_bits_param,\n output [12:0] io_schedule_bits_c_bits_tag,\n output [9:0] io_schedule_bits_c_bits_set,\n output [2:0] io_schedule_bits_c_bits_way,\n output io_schedule_bits_c_bits_dirty,\n output io_schedule_bits_d_valid,\n output io_schedule_bits_d_bits_prio_0,\n output io_schedule_bits_d_bits_prio_2,\n output [2:0] io_schedule_bits_d_bits_opcode,\n output [2:0] io_schedule_bits_d_bits_param,\n output [2:0] io_schedule_bits_d_bits_size,\n output [5:0] io_schedule_bits_d_bits_source,\n output [5:0] io_schedule_bits_d_bits_offset,\n output [5:0] io_schedule_bits_d_bits_put,\n output [9:0] io_schedule_bits_d_bits_set,\n output [2:0] io_schedule_bits_d_bits_way,\n output io_schedule_bits_d_bits_bad,\n output io_schedule_bits_e_valid,\n output [2:0] io_schedule_bits_e_bits_sink,\n output io_schedule_bits_x_valid,\n output io_schedule_bits_dir_valid,\n output [9:0] io_schedule_bits_dir_bits_set,\n output [2:0] io_schedule_bits_dir_bits_way,\n output io_schedule_bits_dir_bits_data_dirty,\n output [1:0] io_schedule_bits_dir_bits_data_state,\n output io_schedule_bits_dir_bits_data_clients,\n output [12:0] io_schedule_bits_dir_bits_data_tag,\n output io_schedule_bits_reload,\n input io_sinkd_valid,\n input io_sinkd_bits_last,\n input [2:0] io_sinkd_bits_opcode,\n input [2:0] io_sinkd_bits_param,\n input [2:0] io_sinkd_bits_sink,\n input io_sinkd_bits_denied,\n input [9:0] io_nestedwb_set,\n input [12:0] io_nestedwb_tag,\n input io_nestedwb_b_toN,\n input io_nestedwb_b_toB,\n input io_nestedwb_b_clr_dirty,\n input io_nestedwb_c_set_dirty\n);\n\n reg request_valid;\n reg request_prio_0;\n reg request_prio_2;\n reg request_control;\n reg [2:0] request_opcode;\n reg [2:0] request_param;\n reg [2:0] request_size;\n reg [5:0] request_source;\n reg [12:0] request_tag;\n reg [5:0] request_offset;\n reg [5:0] request_put;\n reg [9:0] request_set;\n reg meta_valid;\n reg meta_dirty;\n reg [1:0] meta_state;\n reg evict_c;\n reg [12:0] meta_tag;\n reg meta_hit;\n reg [2:0] meta_way;\n reg s_release;\n reg w_releaseack;\n reg s_acquire;\n reg s_flush;\n reg w_grantfirst;\n reg w_grantlast;\n reg w_grant;\n reg s_grantack;\n reg s_execute;\n reg w_grantack;\n reg s_writeback;\n reg [2:0] sink;\n reg gotT;\n reg bad_grant;\n wire no_wait = w_releaseack & w_grantlast & w_grantack;\n wire io_schedule_bits_a_valid_0 = ~s_acquire & s_release;\n wire io_schedule_bits_d_valid_0 = ~s_execute & w_grant;\n wire io_schedule_bits_e_valid_0 = ~s_grantack & w_grantfirst;\n wire io_schedule_bits_x_valid_0 = ~s_flush & w_releaseack;\n wire io_schedule_bits_dir_valid_0 = ~s_release | ~s_writeback & no_wait;\n wire io_schedule_valid_0 = io_schedule_bits_a_valid_0 | io_schedule_bits_d_valid_0 | io_schedule_bits_e_valid_0 | io_schedule_bits_x_valid_0 | io_schedule_bits_dir_valid_0;\n wire _excluded_client_T_1 = request_opcode == 3'h6;\n wire req_needT = ~(request_opcode[2]) | request_opcode == 3'h5 & request_param == 3'h1 | (_excluded_client_T_1 | (&request_opcode)) & (|request_param);\n wire req_acquire = _excluded_client_T_1 | (&request_opcode);\n wire [1:0] _final_meta_writeback_state_T_6 = {1'h1, ~req_acquire};\n wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_6 : meta_hit ? ((&meta_state) ? {1'h1, ~(~evict_c & req_acquire)} : {meta_state == 2'h2, 1'h1}) : gotT ? _final_meta_writeback_state_T_6 : 2'h1;\n wire final_meta_writeback_dirty = ~bad_grant & (request_control ? ~meta_hit & meta_dirty : meta_hit & meta_dirty | ~(request_opcode[2]));\n wire [1:0] _GEN = {1'h0, meta_hit};\n wire [1:0] final_meta_writeback_state = bad_grant ? _GEN : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17;\n wire after_c = bad_grant ? meta_hit & evict_c : (request_control | meta_hit) & evict_c;\n wire _new_meta_T = io_allocate_valid & io_allocate_bits_repeat;\n wire _GEN_32 = io_schedule_ready & no_wait;\n wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state;\n wire new_meta_hit = _new_meta_T ? (bad_grant ? meta_hit : ~request_control) : io_directory_bits_hit;\n wire new_request_control = io_allocate_valid ? io_allocate_bits_control : request_control;\n wire [2:0] new_request_opcode = io_allocate_valid ? io_allocate_bits_opcode : request_opcode;\n wire [2:0] new_request_param = io_allocate_valid ? io_allocate_bits_param : request_param;\n wire _new_skipProbe_T = new_request_opcode == 3'h6;\n wire _GEN_33 = new_request_control ? ~new_meta_hit : ~(~new_meta_hit & (|new_meta_state));\n wire _GEN_34 = ~new_meta_hit | new_meta_state == 2'h1 & (~(new_request_opcode[2]) | new_request_opcode == 3'h5 & new_request_param == 3'h1 | (_new_skipProbe_T | (&new_request_opcode)) & (|new_request_param));\n wire _GEN_35 = new_request_control | ~_GEN_34;\n wire _GEN_36 = _new_skipProbe_T | (&new_request_opcode);\n wire _GEN_37 = meta_valid & (|meta_state) & io_nestedwb_set == request_set & io_nestedwb_tag == meta_tag;\n wire _GEN_38 = io_sinkd_bits_opcode == 3'h4 | io_sinkd_bits_opcode == 3'h5;\n wire _GEN_39 = io_sinkd_valid & _GEN_38;\n wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty;\n wire _GEN_40 = io_directory_valid | _new_meta_T;\n always @(posedge clock) begin\n if (reset) begin\n request_valid <= 1'h0;\n meta_valid <= 1'h0;\n s_release <= 1'h1;\n w_releaseack <= 1'h1;\n s_acquire <= 1'h1;\n s_flush <= 1'h1;\n w_grantfirst <= 1'h1;\n w_grantlast <= 1'h1;\n w_grant <= 1'h1;\n s_grantack <= 1'h1;\n s_execute <= 1'h1;\n w_grantack <= 1'h1;\n s_writeback <= 1'h1;\n end\n else begin\n request_valid <= io_allocate_valid | ~_GEN_32 & request_valid;\n meta_valid <= _GEN_40 | ~_GEN_32 & meta_valid;\n s_release <= _GEN_40 ? _GEN_33 : io_schedule_ready | s_release;\n w_releaseack <= _GEN_40 ? _GEN_33 : io_sinkd_valid & ~_GEN_38 & io_sinkd_bits_opcode == 3'h6 | w_releaseack;\n s_acquire <= _GEN_40 ? _GEN_35 : io_schedule_ready & s_release | s_acquire;\n s_flush <= _GEN_40 ? ~new_request_control : io_schedule_ready & w_releaseack | s_flush;\n w_grantfirst <= _GEN_40 ? _GEN_35 : _GEN_39 | w_grantfirst;\n if (_GEN_40) begin\n w_grantlast <= _GEN_35;\n w_grant <= _GEN_35;\n w_grantack <= new_request_control | ~_GEN_36;\n end\n else if (_GEN_39) begin\n w_grantlast <= io_sinkd_bits_last;\n w_grant <= request_offset == 6'h0 | io_sinkd_bits_last;\n end\n s_grantack <= _GEN_40 ? _GEN_35 : io_schedule_ready & w_grantfirst | s_grantack;\n s_execute <= _GEN_40 ? new_request_control : io_schedule_ready & w_grant | s_execute;\n s_writeback <= _GEN_40 ? new_request_control | ~(~(new_request_opcode[2]) & new_meta_hit & ~new_meta_dirty | _GEN_36) & ~_GEN_34 : _GEN_32 | s_writeback;\n end\n if (io_allocate_valid) begin\n request_prio_0 <= io_allocate_bits_prio_0;\n request_prio_2 <= io_allocate_bits_prio_2;\n request_control <= io_allocate_bits_control;\n request_opcode <= io_allocate_bits_opcode;\n request_param <= io_allocate_bits_param;\n request_size <= io_allocate_bits_size;\n request_source <= io_allocate_bits_source;\n request_tag <= io_allocate_bits_tag;\n request_offset <= io_allocate_bits_offset;\n request_put <= io_allocate_bits_put;\n request_set <= io_allocate_bits_set;\n end\n if (_GEN_40) begin\n meta_dirty <= new_meta_dirty;\n if (_new_meta_T) begin\n if (bad_grant)\n meta_state <= _GEN;\n else begin\n if (request_control) begin\n if (meta_hit)\n meta_state <= 2'h0;\n end\n else\n meta_state <= _final_meta_writeback_state_T_17;\n meta_hit <= ~request_control;\n end\n if (request_control) begin\n end\n else\n meta_tag <= request_tag;\n end\n else begin\n meta_state <= io_directory_bits_state;\n meta_tag <= io_directory_bits_tag;\n meta_hit <= io_directory_bits_hit;\n end\n evict_c <= _new_meta_T ? after_c : io_directory_bits_clients;\n end\n else begin\n if (_GEN_37)\n meta_dirty <= io_nestedwb_c_set_dirty | ~io_nestedwb_b_clr_dirty & meta_dirty;\n if (_GEN_37 & io_nestedwb_b_toB)\n meta_state <= 2'h1;\n meta_hit <= ~(_GEN_37 & io_nestedwb_b_toN) & meta_hit;\n end\n if (~_GEN_40 | _new_meta_T) begin\n end\n else\n meta_way <= io_directory_bits_way;\n if (_GEN_39)\n sink <= io_sinkd_bits_sink;\n gotT <= ~_GEN_40 & (_GEN_39 ? io_sinkd_bits_param == 3'h0 : gotT);\n bad_grant <= ~_GEN_40 & (_GEN_39 ? io_sinkd_bits_denied : bad_grant);\n end\n assign io_status_valid = request_valid;\n assign io_status_bits_set = request_set;\n assign io_status_bits_tag = request_tag;\n assign io_status_bits_way = meta_way;\n assign io_schedule_valid = io_schedule_valid_0;\n assign io_schedule_bits_a_valid = io_schedule_bits_a_valid_0;\n assign io_schedule_bits_a_bits_tag = request_tag;\n assign io_schedule_bits_a_bits_set = request_set;\n assign io_schedule_bits_a_bits_param = {1'h0, req_needT ? (meta_hit ? 2'h2 : 2'h1) : 2'h0};\n assign io_schedule_bits_a_bits_block = request_size != 3'h6 | ~(request_opcode == 3'h0 | (&request_opcode));\n assign io_schedule_bits_c_valid = ~s_release;\n assign io_schedule_bits_c_bits_opcode = {2'h3, meta_dirty};\n assign io_schedule_bits_c_bits_param = meta_state == 2'h1 ? 3'h2 : 3'h1;\n assign io_schedule_bits_c_bits_tag = meta_tag;\n assign io_schedule_bits_c_bits_set = request_set;\n assign io_schedule_bits_c_bits_way = meta_way;\n assign io_schedule_bits_c_bits_dirty = meta_dirty;\n assign io_schedule_bits_d_valid = io_schedule_bits_d_valid_0;\n assign io_schedule_bits_d_bits_prio_0 = request_prio_0;\n assign io_schedule_bits_d_bits_prio_2 = request_prio_2;\n assign io_schedule_bits_d_bits_opcode = request_opcode;\n assign io_schedule_bits_d_bits_param = req_acquire ? (request_param == 3'h1 | request_param == 3'h2 ? 3'h1 : request_param == 3'h0 ? {2'h0, req_acquire & (meta_hit ? ~evict_c & (&meta_state) : gotT)} : request_param) : request_param;\n assign io_schedule_bits_d_bits_size = request_size;\n assign io_schedule_bits_d_bits_source = request_source;\n assign io_schedule_bits_d_bits_offset = request_offset;\n assign io_schedule_bits_d_bits_put = request_put;\n assign io_schedule_bits_d_bits_set = request_set;\n assign io_schedule_bits_d_bits_way = meta_way;\n assign io_schedule_bits_d_bits_bad = bad_grant;\n assign io_schedule_bits_e_valid = io_schedule_bits_e_valid_0;\n assign io_schedule_bits_e_bits_sink = sink;\n assign io_schedule_bits_x_valid = io_schedule_bits_x_valid_0;\n assign io_schedule_bits_dir_valid = io_schedule_bits_dir_valid_0;\n assign io_schedule_bits_dir_bits_set = request_set;\n assign io_schedule_bits_dir_bits_way = meta_way;\n assign io_schedule_bits_dir_bits_data_dirty = s_release & final_meta_writeback_dirty;\n assign io_schedule_bits_dir_bits_data_state = s_release ? final_meta_writeback_state : 2'h0;\n assign io_schedule_bits_dir_bits_data_clients = s_release & after_c;\n assign io_schedule_bits_dir_bits_data_tag = s_release ? (request_control ? meta_tag : request_tag) : 13'h0;\n assign io_schedule_bits_reload = no_wait;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a28d64s4k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [3:0] io_enq_bits_source,\n input [27:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [3:0] io_deq_bits_source,\n output [27:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [3:0] saved_source;\n reg [27:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module BranchKillableQueue_4(\n input clock,\n input reset,\n output io_enq_ready,\n input io_enq_valid,\n input [6:0] io_enq_bits_uop_uopc,\n input [31:0] io_enq_bits_uop_inst,\n input [31:0] io_enq_bits_uop_debug_inst,\n input io_enq_bits_uop_is_rvc,\n input [39:0] io_enq_bits_uop_debug_pc,\n input [2:0] io_enq_bits_uop_iq_type,\n input [9:0] io_enq_bits_uop_fu_code,\n input [3:0] io_enq_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_uop_ctrl_op_fcn,\n input io_enq_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_uop_ctrl_is_load,\n input io_enq_bits_uop_ctrl_is_sta,\n input io_enq_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_uop_iw_state,\n input io_enq_bits_uop_iw_p1_poisoned,\n input io_enq_bits_uop_iw_p2_poisoned,\n input io_enq_bits_uop_is_br,\n input io_enq_bits_uop_is_jalr,\n input io_enq_bits_uop_is_jal,\n input io_enq_bits_uop_is_sfb,\n input [7:0] io_enq_bits_uop_br_mask,\n input [2:0] io_enq_bits_uop_br_tag,\n input [3:0] io_enq_bits_uop_ftq_idx,\n input io_enq_bits_uop_edge_inst,\n input [5:0] io_enq_bits_uop_pc_lob,\n input io_enq_bits_uop_taken,\n input [19:0] io_enq_bits_uop_imm_packed,\n input [11:0] io_enq_bits_uop_csr_addr,\n input [4:0] io_enq_bits_uop_rob_idx,\n input [2:0] io_enq_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_uop_stq_idx,\n input [1:0] io_enq_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_uop_pdst,\n input [5:0] io_enq_bits_uop_prs1,\n input [5:0] io_enq_bits_uop_prs2,\n input [5:0] io_enq_bits_uop_prs3,\n input [3:0] io_enq_bits_uop_ppred,\n input io_enq_bits_uop_prs1_busy,\n input io_enq_bits_uop_prs2_busy,\n input io_enq_bits_uop_prs3_busy,\n input io_enq_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_uop_stale_pdst,\n input io_enq_bits_uop_exception,\n input [63:0] io_enq_bits_uop_exc_cause,\n input io_enq_bits_uop_bypassable,\n input [4:0] io_enq_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_uop_mem_size,\n input io_enq_bits_uop_mem_signed,\n input io_enq_bits_uop_is_fence,\n input io_enq_bits_uop_is_fencei,\n input io_enq_bits_uop_is_amo,\n input io_enq_bits_uop_uses_ldq,\n input io_enq_bits_uop_uses_stq,\n input io_enq_bits_uop_is_sys_pc2epc,\n input io_enq_bits_uop_is_unique,\n input io_enq_bits_uop_flush_on_commit,\n input io_enq_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_uop_ldst,\n input [5:0] io_enq_bits_uop_lrs1,\n input [5:0] io_enq_bits_uop_lrs2,\n input [5:0] io_enq_bits_uop_lrs3,\n input io_enq_bits_uop_ldst_val,\n input [1:0] io_enq_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_uop_lrs2_rtype,\n input io_enq_bits_uop_frs3_en,\n input io_enq_bits_uop_fp_val,\n input io_enq_bits_uop_fp_single,\n input io_enq_bits_uop_xcpt_pf_if,\n input io_enq_bits_uop_xcpt_ae_if,\n input io_enq_bits_uop_xcpt_ma_if,\n input io_enq_bits_uop_bp_debug_if,\n input io_enq_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_uop_debug_tsrc,\n input [64:0] io_enq_bits_data,\n input io_enq_bits_fflags_valid,\n input [6:0] io_enq_bits_fflags_bits_uop_uopc,\n input [31:0] io_enq_bits_fflags_bits_uop_inst,\n input [31:0] io_enq_bits_fflags_bits_uop_debug_inst,\n input io_enq_bits_fflags_bits_uop_is_rvc,\n input [39:0] io_enq_bits_fflags_bits_uop_debug_pc,\n input [2:0] io_enq_bits_fflags_bits_uop_iq_type,\n input [9:0] io_enq_bits_fflags_bits_uop_fu_code,\n input [3:0] io_enq_bits_fflags_bits_uop_ctrl_br_type,\n input [1:0] io_enq_bits_fflags_bits_uop_ctrl_op1_sel,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_op2_sel,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_imm_sel,\n input [4:0] io_enq_bits_fflags_bits_uop_ctrl_op_fcn,\n input io_enq_bits_fflags_bits_uop_ctrl_fcn_dw,\n input [2:0] io_enq_bits_fflags_bits_uop_ctrl_csr_cmd,\n input io_enq_bits_fflags_bits_uop_ctrl_is_load,\n input io_enq_bits_fflags_bits_uop_ctrl_is_sta,\n input io_enq_bits_fflags_bits_uop_ctrl_is_std,\n input [1:0] io_enq_bits_fflags_bits_uop_iw_state,\n input io_enq_bits_fflags_bits_uop_iw_p1_poisoned,\n input io_enq_bits_fflags_bits_uop_iw_p2_poisoned,\n input io_enq_bits_fflags_bits_uop_is_br,\n input io_enq_bits_fflags_bits_uop_is_jalr,\n input io_enq_bits_fflags_bits_uop_is_jal,\n input io_enq_bits_fflags_bits_uop_is_sfb,\n input [7:0] io_enq_bits_fflags_bits_uop_br_mask,\n input [2:0] io_enq_bits_fflags_bits_uop_br_tag,\n input [3:0] io_enq_bits_fflags_bits_uop_ftq_idx,\n input io_enq_bits_fflags_bits_uop_edge_inst,\n input [5:0] io_enq_bits_fflags_bits_uop_pc_lob,\n input io_enq_bits_fflags_bits_uop_taken,\n input [19:0] io_enq_bits_fflags_bits_uop_imm_packed,\n input [11:0] io_enq_bits_fflags_bits_uop_csr_addr,\n input [4:0] io_enq_bits_fflags_bits_uop_rob_idx,\n input [2:0] io_enq_bits_fflags_bits_uop_ldq_idx,\n input [2:0] io_enq_bits_fflags_bits_uop_stq_idx,\n input [1:0] io_enq_bits_fflags_bits_uop_rxq_idx,\n input [5:0] io_enq_bits_fflags_bits_uop_pdst,\n input [5:0] io_enq_bits_fflags_bits_uop_prs1,\n input [5:0] io_enq_bits_fflags_bits_uop_prs2,\n input [5:0] io_enq_bits_fflags_bits_uop_prs3,\n input [3:0] io_enq_bits_fflags_bits_uop_ppred,\n input io_enq_bits_fflags_bits_uop_prs1_busy,\n input io_enq_bits_fflags_bits_uop_prs2_busy,\n input io_enq_bits_fflags_bits_uop_prs3_busy,\n input io_enq_bits_fflags_bits_uop_ppred_busy,\n input [5:0] io_enq_bits_fflags_bits_uop_stale_pdst,\n input io_enq_bits_fflags_bits_uop_exception,\n input [63:0] io_enq_bits_fflags_bits_uop_exc_cause,\n input io_enq_bits_fflags_bits_uop_bypassable,\n input [4:0] io_enq_bits_fflags_bits_uop_mem_cmd,\n input [1:0] io_enq_bits_fflags_bits_uop_mem_size,\n input io_enq_bits_fflags_bits_uop_mem_signed,\n input io_enq_bits_fflags_bits_uop_is_fence,\n input io_enq_bits_fflags_bits_uop_is_fencei,\n input io_enq_bits_fflags_bits_uop_is_amo,\n input io_enq_bits_fflags_bits_uop_uses_ldq,\n input io_enq_bits_fflags_bits_uop_uses_stq,\n input io_enq_bits_fflags_bits_uop_is_sys_pc2epc,\n input io_enq_bits_fflags_bits_uop_is_unique,\n input io_enq_bits_fflags_bits_uop_flush_on_commit,\n input io_enq_bits_fflags_bits_uop_ldst_is_rs1,\n input [5:0] io_enq_bits_fflags_bits_uop_ldst,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs1,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs2,\n input [5:0] io_enq_bits_fflags_bits_uop_lrs3,\n input io_enq_bits_fflags_bits_uop_ldst_val,\n input [1:0] io_enq_bits_fflags_bits_uop_dst_rtype,\n input [1:0] io_enq_bits_fflags_bits_uop_lrs1_rtype,\n input [1:0] io_enq_bits_fflags_bits_uop_lrs2_rtype,\n input io_enq_bits_fflags_bits_uop_frs3_en,\n input io_enq_bits_fflags_bits_uop_fp_val,\n input io_enq_bits_fflags_bits_uop_fp_single,\n input io_enq_bits_fflags_bits_uop_xcpt_pf_if,\n input io_enq_bits_fflags_bits_uop_xcpt_ae_if,\n input io_enq_bits_fflags_bits_uop_xcpt_ma_if,\n input io_enq_bits_fflags_bits_uop_bp_debug_if,\n input io_enq_bits_fflags_bits_uop_bp_xcpt_if,\n input [1:0] io_enq_bits_fflags_bits_uop_debug_fsrc,\n input [1:0] io_enq_bits_fflags_bits_uop_debug_tsrc,\n input [4:0] io_enq_bits_fflags_bits_flags,\n input io_deq_ready,\n output io_deq_valid,\n output [6:0] io_deq_bits_uop_uopc,\n output [7:0] io_deq_bits_uop_br_mask,\n output [4:0] io_deq_bits_uop_rob_idx,\n output [2:0] io_deq_bits_uop_stq_idx,\n output [5:0] io_deq_bits_uop_pdst,\n output io_deq_bits_uop_is_amo,\n output io_deq_bits_uop_uses_stq,\n output [1:0] io_deq_bits_uop_dst_rtype,\n output io_deq_bits_uop_fp_val,\n output [64:0] io_deq_bits_data,\n output io_deq_bits_predicated,\n output io_deq_bits_fflags_valid,\n output [4:0] io_deq_bits_fflags_bits_uop_rob_idx,\n output [4:0] io_deq_bits_fflags_bits_flags,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_flush,\n output io_empty\n);\n\n wire [76:0] _ram_ext_R0_data;\n reg valids_0;\n reg valids_1;\n reg valids_2;\n reg valids_3;\n reg valids_4;\n reg valids_5;\n reg valids_6;\n reg [6:0] uops_0_uopc;\n reg [7:0] uops_0_br_mask;\n reg [4:0] uops_0_rob_idx;\n reg [2:0] uops_0_stq_idx;\n reg [5:0] uops_0_pdst;\n reg uops_0_is_amo;\n reg uops_0_uses_stq;\n reg [1:0] uops_0_dst_rtype;\n reg uops_0_fp_val;\n reg [6:0] uops_1_uopc;\n reg [7:0] uops_1_br_mask;\n reg [4:0] uops_1_rob_idx;\n reg [2:0] uops_1_stq_idx;\n reg [5:0] uops_1_pdst;\n reg uops_1_is_amo;\n reg uops_1_uses_stq;\n reg [1:0] uops_1_dst_rtype;\n reg uops_1_fp_val;\n reg [6:0] uops_2_uopc;\n reg [7:0] uops_2_br_mask;\n reg [4:0] uops_2_rob_idx;\n reg [2:0] uops_2_stq_idx;\n reg [5:0] uops_2_pdst;\n reg uops_2_is_amo;\n reg uops_2_uses_stq;\n reg [1:0] uops_2_dst_rtype;\n reg uops_2_fp_val;\n reg [6:0] uops_3_uopc;\n reg [7:0] uops_3_br_mask;\n reg [4:0] uops_3_rob_idx;\n reg [2:0] uops_3_stq_idx;\n reg [5:0] uops_3_pdst;\n reg uops_3_is_amo;\n reg uops_3_uses_stq;\n reg [1:0] uops_3_dst_rtype;\n reg uops_3_fp_val;\n reg [6:0] uops_4_uopc;\n reg [7:0] uops_4_br_mask;\n reg [4:0] uops_4_rob_idx;\n reg [2:0] uops_4_stq_idx;\n reg [5:0] uops_4_pdst;\n reg uops_4_is_amo;\n reg uops_4_uses_stq;\n reg [1:0] uops_4_dst_rtype;\n reg uops_4_fp_val;\n reg [6:0] uops_5_uopc;\n reg [7:0] uops_5_br_mask;\n reg [4:0] uops_5_rob_idx;\n reg [2:0] uops_5_stq_idx;\n reg [5:0] uops_5_pdst;\n reg uops_5_is_amo;\n reg uops_5_uses_stq;\n reg [1:0] uops_5_dst_rtype;\n reg uops_5_fp_val;\n reg [6:0] uops_6_uopc;\n reg [7:0] uops_6_br_mask;\n reg [4:0] uops_6_rob_idx;\n reg [2:0] uops_6_stq_idx;\n reg [5:0] uops_6_pdst;\n reg uops_6_is_amo;\n reg uops_6_uses_stq;\n reg [1:0] uops_6_dst_rtype;\n reg uops_6_fp_val;\n reg [2:0] enq_ptr_value;\n reg [2:0] deq_ptr_value;\n reg maybe_full;\n wire ptr_match = enq_ptr_value == deq_ptr_value;\n wire io_empty_0 = ptr_match & ~maybe_full;\n wire full = ptr_match & maybe_full;\n wire [7:0] _GEN = {{valids_0}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}};\n wire _GEN_0 = _GEN[deq_ptr_value];\n wire [7:0][6:0] _GEN_1 = {{uops_0_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}};\n wire [7:0][7:0] _GEN_2 = {{uops_0_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}};\n wire [7:0] out_uop_br_mask = _GEN_2[deq_ptr_value];\n wire [7:0][4:0] _GEN_3 = {{uops_0_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}};\n wire [7:0][2:0] _GEN_4 = {{uops_0_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}};\n wire [7:0][5:0] _GEN_5 = {{uops_0_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}};\n wire [7:0] _GEN_6 = {{uops_0_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}};\n wire [7:0] _GEN_7 = {{uops_0_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}};\n wire [7:0][1:0] _GEN_8 = {{uops_0_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}};\n wire [7:0] _GEN_9 = {{uops_0_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}};\n wire do_deq = ~io_empty_0 & (io_deq_ready | ~_GEN_0) & ~io_empty_0;\n wire do_enq = ~(io_empty_0 & io_deq_ready) & ~full & io_enq_valid;\n wire _GEN_10 = enq_ptr_value == 3'h0;\n wire _GEN_11 = do_enq & _GEN_10;\n wire _GEN_12 = enq_ptr_value == 3'h1;\n wire _GEN_13 = do_enq & _GEN_12;\n wire _GEN_14 = enq_ptr_value == 3'h2;\n wire _GEN_15 = do_enq & _GEN_14;\n wire _GEN_16 = enq_ptr_value == 3'h3;\n wire _GEN_17 = do_enq & _GEN_16;\n wire _GEN_18 = enq_ptr_value == 3'h4;\n wire _GEN_19 = do_enq & _GEN_18;\n wire _GEN_20 = enq_ptr_value == 3'h5;\n wire _GEN_21 = do_enq & _GEN_20;\n wire _GEN_22 = enq_ptr_value == 3'h6;\n wire _GEN_23 = do_enq & _GEN_22;\n wire [7:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n always @(posedge clock) begin\n if (reset) begin\n valids_0 <= 1'h0;\n valids_1 <= 1'h0;\n valids_2 <= 1'h0;\n valids_3 <= 1'h0;\n valids_4 <= 1'h0;\n valids_5 <= 1'h0;\n valids_6 <= 1'h0;\n enq_ptr_value <= 3'h0;\n deq_ptr_value <= 3'h0;\n maybe_full <= 1'h0;\n end\n else begin\n valids_0 <= ~(do_deq & deq_ptr_value == 3'h0) & (_GEN_11 | valids_0 & (io_brupdate_b1_mispredict_mask & uops_0_br_mask) == 8'h0 & ~io_flush);\n valids_1 <= ~(do_deq & deq_ptr_value == 3'h1) & (_GEN_13 | valids_1 & (io_brupdate_b1_mispredict_mask & uops_1_br_mask) == 8'h0 & ~io_flush);\n valids_2 <= ~(do_deq & deq_ptr_value == 3'h2) & (_GEN_15 | valids_2 & (io_brupdate_b1_mispredict_mask & uops_2_br_mask) == 8'h0 & ~io_flush);\n valids_3 <= ~(do_deq & deq_ptr_value == 3'h3) & (_GEN_17 | valids_3 & (io_brupdate_b1_mispredict_mask & uops_3_br_mask) == 8'h0 & ~io_flush);\n valids_4 <= ~(do_deq & deq_ptr_value == 3'h4) & (_GEN_19 | valids_4 & (io_brupdate_b1_mispredict_mask & uops_4_br_mask) == 8'h0 & ~io_flush);\n valids_5 <= ~(do_deq & deq_ptr_value == 3'h5) & (_GEN_21 | valids_5 & (io_brupdate_b1_mispredict_mask & uops_5_br_mask) == 8'h0 & ~io_flush);\n valids_6 <= ~(do_deq & deq_ptr_value == 3'h6) & (_GEN_23 | valids_6 & (io_brupdate_b1_mispredict_mask & uops_6_br_mask) == 8'h0 & ~io_flush);\n if (do_enq)\n enq_ptr_value <= enq_ptr_value == 3'h6 ? 3'h0 : enq_ptr_value + 3'h1;\n if (do_deq)\n deq_ptr_value <= deq_ptr_value == 3'h6 ? 3'h0 : deq_ptr_value + 3'h1;\n if (~(do_enq == do_deq))\n maybe_full <= do_enq;\n end\n if (_GEN_11) begin\n uops_0_uopc <= io_enq_bits_uop_uopc;\n uops_0_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_0_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_0_pdst <= io_enq_bits_uop_pdst;\n uops_0_is_amo <= io_enq_bits_uop_is_amo;\n uops_0_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_0_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_0_br_mask <= do_enq & _GEN_10 ? _uops_br_mask_T_1 : ({8{~valids_0}} | ~io_brupdate_b1_resolve_mask) & uops_0_br_mask;\n if (_GEN_13) begin\n uops_1_uopc <= io_enq_bits_uop_uopc;\n uops_1_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_1_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_1_pdst <= io_enq_bits_uop_pdst;\n uops_1_is_amo <= io_enq_bits_uop_is_amo;\n uops_1_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_1_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_1_br_mask <= do_enq & _GEN_12 ? _uops_br_mask_T_1 : ({8{~valids_1}} | ~io_brupdate_b1_resolve_mask) & uops_1_br_mask;\n if (_GEN_15) begin\n uops_2_uopc <= io_enq_bits_uop_uopc;\n uops_2_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_2_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_2_pdst <= io_enq_bits_uop_pdst;\n uops_2_is_amo <= io_enq_bits_uop_is_amo;\n uops_2_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_2_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_2_br_mask <= do_enq & _GEN_14 ? _uops_br_mask_T_1 : ({8{~valids_2}} | ~io_brupdate_b1_resolve_mask) & uops_2_br_mask;\n if (_GEN_17) begin\n uops_3_uopc <= io_enq_bits_uop_uopc;\n uops_3_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_3_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_3_pdst <= io_enq_bits_uop_pdst;\n uops_3_is_amo <= io_enq_bits_uop_is_amo;\n uops_3_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_3_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_3_br_mask <= do_enq & _GEN_16 ? _uops_br_mask_T_1 : ({8{~valids_3}} | ~io_brupdate_b1_resolve_mask) & uops_3_br_mask;\n if (_GEN_19) begin\n uops_4_uopc <= io_enq_bits_uop_uopc;\n uops_4_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_4_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_4_pdst <= io_enq_bits_uop_pdst;\n uops_4_is_amo <= io_enq_bits_uop_is_amo;\n uops_4_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_4_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_4_br_mask <= do_enq & _GEN_18 ? _uops_br_mask_T_1 : ({8{~valids_4}} | ~io_brupdate_b1_resolve_mask) & uops_4_br_mask;\n if (_GEN_21) begin\n uops_5_uopc <= io_enq_bits_uop_uopc;\n uops_5_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_5_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_5_pdst <= io_enq_bits_uop_pdst;\n uops_5_is_amo <= io_enq_bits_uop_is_amo;\n uops_5_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_5_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_5_br_mask <= do_enq & _GEN_20 ? _uops_br_mask_T_1 : ({8{~valids_5}} | ~io_brupdate_b1_resolve_mask) & uops_5_br_mask;\n if (_GEN_23) begin\n uops_6_uopc <= io_enq_bits_uop_uopc;\n uops_6_rob_idx <= io_enq_bits_uop_rob_idx;\n uops_6_stq_idx <= io_enq_bits_uop_stq_idx;\n uops_6_pdst <= io_enq_bits_uop_pdst;\n uops_6_is_amo <= io_enq_bits_uop_is_amo;\n uops_6_uses_stq <= io_enq_bits_uop_uses_stq;\n uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype;\n uops_6_fp_val <= io_enq_bits_uop_fp_val;\n end\n uops_6_br_mask <= do_enq & _GEN_22 ? _uops_br_mask_T_1 : ({8{~valids_6}} | ~io_brupdate_b1_resolve_mask) & uops_6_br_mask;\n end\n ram_7x77 ram_ext (\n .R0_addr (deq_ptr_value),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_ram_ext_R0_data),\n .W0_addr (enq_ptr_value),\n .W0_en (do_enq),\n .W0_clk (clock),\n .W0_data ({io_enq_bits_fflags_bits_flags, io_enq_bits_fflags_bits_uop_rob_idx, io_enq_bits_fflags_valid, 1'h0, io_enq_bits_data})\n );\n assign io_enq_ready = ~full;\n assign io_deq_valid = io_empty_0 ? io_enq_valid : ~io_empty_0 & _GEN_0 & (io_brupdate_b1_mispredict_mask & out_uop_br_mask) == 8'h0 & ~io_flush;\n assign io_deq_bits_uop_uopc = io_empty_0 ? io_enq_bits_uop_uopc : _GEN_1[deq_ptr_value];\n assign io_deq_bits_uop_br_mask = io_empty_0 ? io_enq_bits_uop_br_mask & ~io_brupdate_b1_resolve_mask : out_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_deq_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_uop_rob_idx : _GEN_3[deq_ptr_value];\n assign io_deq_bits_uop_stq_idx = io_empty_0 ? io_enq_bits_uop_stq_idx : _GEN_4[deq_ptr_value];\n assign io_deq_bits_uop_pdst = io_empty_0 ? io_enq_bits_uop_pdst : _GEN_5[deq_ptr_value];\n assign io_deq_bits_uop_is_amo = io_empty_0 ? io_enq_bits_uop_is_amo : _GEN_6[deq_ptr_value];\n assign io_deq_bits_uop_uses_stq = io_empty_0 ? io_enq_bits_uop_uses_stq : _GEN_7[deq_ptr_value];\n assign io_deq_bits_uop_dst_rtype = io_empty_0 ? io_enq_bits_uop_dst_rtype : _GEN_8[deq_ptr_value];\n assign io_deq_bits_uop_fp_val = io_empty_0 ? io_enq_bits_uop_fp_val : _GEN_9[deq_ptr_value];\n assign io_deq_bits_data = io_empty_0 ? io_enq_bits_data : _ram_ext_R0_data[64:0];\n assign io_deq_bits_predicated = ~io_empty_0 & _ram_ext_R0_data[65];\n assign io_deq_bits_fflags_valid = io_empty_0 ? io_enq_bits_fflags_valid : _ram_ext_R0_data[66];\n assign io_deq_bits_fflags_bits_uop_rob_idx = io_empty_0 ? io_enq_bits_fflags_bits_uop_rob_idx : _ram_ext_R0_data[71:67];\n assign io_deq_bits_fflags_bits_flags = io_empty_0 ? io_enq_bits_fflags_bits_flags : _ram_ext_R0_data[76:72];\n assign io_empty = io_empty_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module tail_15x6(\n input [3:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [3:0] R1_addr,\n input R1_en,\n input R1_clk,\n output [5:0] R1_data,\n input [3:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data\n);\n\n reg [5:0] Memory[0:14];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\n assign R1_data = R1_en ? Memory[R1_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.tilelink._\n\nclass SourceERequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val sink = UInt(params.outer.bundle.sinkBits.W)\n}\n\nclass SourceE(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new SourceERequest(params)))\n val e = Decoupled(new TLBundleE(params.outer.bundle))\n })\n\n // ready must be a register, because we derive valid from ready\n require (!params.micro.outerBuf.e.pipe && params.micro.outerBuf.e.isDefined)\n\n val e = Wire(chiselTypeOf(io.e))\n io.e <> params.micro.outerBuf.e(e)\n\n io.req.ready := e.ready\n e.valid := io.req.valid\n\n e.bits.sink := io.req.bits.sink\n\n // we can't cover valid+!ready, because no backpressure on E is common\n}", + "response": "module SourceE(\n input clock,\n input reset,\n output io_req_ready,\n input io_req_valid,\n input [2:0] io_req_bits_sink,\n output io_e_valid,\n output [2:0] io_e_bits_sink\n);\n\n Queue2_TLBundleE_a32d64s2k3z3c io_e_q (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (io_req_ready),\n .io_enq_valid (io_req_valid),\n .io_enq_bits_sink (io_req_bits_sink),\n .io_deq_valid (io_e_valid),\n .io_deq_bits_sink (io_e_bits_sink)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a26d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [25:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [25:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [25:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitArbiter_p32_f32_n5(\n input clock,\n input reset,\n output io_in_0_ready,\n input io_in_0_valid,\n input [31:0] io_in_0_bits_phit,\n output io_in_1_ready,\n input io_in_1_valid,\n input [31:0] io_in_1_bits_phit,\n output io_in_2_ready,\n input io_in_2_valid,\n input [31:0] io_in_2_bits_phit,\n output io_in_3_ready,\n input io_in_3_valid,\n input [31:0] io_in_3_bits_phit,\n output io_in_4_ready,\n input io_in_4_valid,\n input [31:0] io_in_4_bits_phit,\n input io_out_ready,\n output io_out_valid,\n output [31:0] io_out_bits_phit\n);\n\n reg beat;\n reg [2:0] chosen_reg;\n wire [2:0] chosen_prio = io_in_0_valid ? 3'h0 : io_in_1_valid ? 3'h1 : io_in_2_valid ? 3'h2 : io_in_3_valid ? 3'h3 : 3'h4;\n wire [2:0] chosen = beat ? chosen_reg : chosen_prio;\n wire [7:0] _GEN = {{io_in_0_valid}, {io_in_0_valid}, {io_in_0_valid}, {io_in_4_valid}, {io_in_3_valid}, {io_in_2_valid}, {io_in_1_valid}, {io_in_0_valid}};\n wire [7:0][31:0] _GEN_0 = {{io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_0_bits_phit}, {io_in_4_bits_phit}, {io_in_3_bits_phit}, {io_in_2_bits_phit}, {io_in_1_bits_phit}, {io_in_0_bits_phit}};\n wire _GEN_1 = io_out_ready & _GEN[chosen];\n always @(posedge clock) begin\n if (reset)\n beat <= 1'h0;\n else if (_GEN_1)\n beat <= ~beat & beat - 1'h1;\n if (_GEN_1 & ~beat)\n chosen_reg <= chosen_prio;\n end\n assign io_in_0_ready = io_out_ready & beat & chosen_reg == 3'h0;\n assign io_in_1_ready = io_out_ready & beat & chosen_reg == 3'h1;\n assign io_in_2_ready = io_out_ready & beat & chosen_reg == 3'h2;\n assign io_in_3_ready = io_out_ready & beat & chosen_reg == 3'h3;\n assign io_in_4_ready = io_out_ready & beat & chosen_reg == 3'h4;\n assign io_out_valid = _GEN[chosen];\n assign io_out_bits_phit = beat ? _GEN_0[chosen] : {29'h0, chosen};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.rocket\n\nimport chisel3._\nimport chisel3.util.{Cat}\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}\nimport freechips.rocketchip.util._\n\nclass BPControl(implicit p: Parameters) extends CoreBundle()(p) {\n val ttype = UInt(4.W)\n val dmode = Bool()\n val maskmax = UInt(6.W)\n val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)\n val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)\n val chain = Bool()\n val zero = UInt(2.W)\n val tmatch = UInt(2.W)\n val m = Bool()\n val h = Bool()\n val s = Bool()\n val u = Bool()\n val x = Bool()\n val w = Bool()\n val r = Bool()\n\n def tType = 2\n def maskMax = 4\n def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)\n}\n\nclass TExtra(implicit p: Parameters) extends CoreBundle()(p) {\n def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13\n def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34\n def mselectPos: Int = if (xLen == 32) 25 else 50\n def mvaluePos : Int = mselectPos + 1\n def sselectPos: Int = 0\n def svaluePos : Int = 2\n\n val mvalue = UInt(mvalueBits.W)\n val mselect = Bool()\n val pad2 = UInt((mselectPos - svalueBits - 2).W)\n val svalue = UInt(svalueBits.W)\n val pad1 = UInt(1.W)\n val sselect = Bool()\n}\n\nclass BP(implicit p: Parameters) extends CoreBundle()(p) {\n val control = new BPControl\n val address = UInt(vaddrBits.W)\n val textra = new TExtra\n\n def contextMatch(mcontext: UInt, scontext: UInt) =\n (if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&\n (if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)\n\n def mask(dummy: Int = 0) =\n (0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt\n\n def pow2AddressMatch(x: UInt) =\n (~x | mask()) === (~address | mask())\n\n def rangeAddressMatch(x: UInt) =\n (x >= address) ^ control.tmatch(0)\n\n def addressMatch(x: UInt) =\n Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))\n}\n\nclass BPWatch (val n: Int) extends Bundle() {\n val valid = Vec(n, Bool())\n val rvalid = Vec(n, Bool())\n val wvalid = Vec(n, Bool())\n val ivalid = Vec(n, Bool())\n val action = UInt(3.W)\n}\n\nclass BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {\n val io = IO(new Bundle {\n val status = Input(new MStatus())\n val bp = Input(Vec(n, new BP))\n val pc = Input(UInt(vaddrBits.W))\n val ea = Input(UInt(vaddrBits.W))\n val mcontext = Input(UInt(coreParams.mcontextWidth.W))\n val scontext = Input(UInt(coreParams.scontextWidth.W))\n val xcpt_if = Output(Bool())\n val xcpt_ld = Output(Bool())\n val xcpt_st = Output(Bool())\n val debug_if = Output(Bool())\n val debug_ld = Output(Bool())\n val debug_st = Output(Bool())\n val bpwatch = Output(Vec(n, new BPWatch(1)))\n })\n\n io.xcpt_if := false.B\n io.xcpt_ld := false.B\n io.xcpt_st := false.B\n io.debug_if := false.B\n io.debug_ld := false.B\n io.debug_st := false.B\n\n (io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>\n val en = bp.control.enabled(io.status)\n val cx = bp.contextMatch(io.mcontext, io.scontext)\n val r = en && bp.control.r && bp.addressMatch(io.ea) && cx\n val w = en && bp.control.w && bp.addressMatch(io.ea) && cx\n val x = en && bp.control.x && bp.addressMatch(io.pc) && cx\n val end = !bp.control.chain\n val action = bp.control.action\n\n bpw.action := action\n bpw.valid(0) := false.B\n bpw.rvalid(0) := false.B\n bpw.wvalid(0) := false.B\n bpw.ivalid(0) := false.B\n\n when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }\n when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }\n when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }\n\n (end || r, end || w, end || x)\n }\n}", + "response": "module BreakpointUnit(\n input io_status_debug,\n input [1:0] io_status_prv,\n input io_bp_0_control_action,\n input [1:0] io_bp_0_control_tmatch,\n input io_bp_0_control_m,\n input io_bp_0_control_s,\n input io_bp_0_control_u,\n input io_bp_0_control_x,\n input io_bp_0_control_w,\n input io_bp_0_control_r,\n input [38:0] io_bp_0_address,\n input [38:0] io_pc,\n input [38:0] io_ea,\n output io_xcpt_if,\n output io_xcpt_ld,\n output io_xcpt_st,\n output io_debug_if,\n output io_debug_ld,\n output io_debug_st\n);\n\n wire [3:0] _en_T_2 = {io_bp_0_control_m, 1'h0, io_bp_0_control_s, io_bp_0_control_u} >> io_status_prv;\n wire en = ~io_status_debug & _en_T_2[0];\n wire _w_T_2 = io_ea >= io_bp_0_address;\n wire [38:0] _w_T_5 = ~io_ea;\n wire _r_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _r_T_10 = _r_T_8 & io_bp_0_address[1];\n wire [38:0] _x_T_15 = ~io_bp_0_address;\n wire _r_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _r_T_20 = _r_T_18 & io_bp_0_address[1];\n wire r = en & io_bp_0_control_r & (io_bp_0_control_tmatch[1] ? _w_T_2 ^ io_bp_0_control_tmatch[0] : {_w_T_5[38:4], _w_T_5[3:0] | {_r_T_10 & io_bp_0_address[2], _r_T_10, _r_T_8, io_bp_0_control_tmatch[0]}} == {_x_T_15[38:4], _x_T_15[3:0] | {_r_T_20 & io_bp_0_address[2], _r_T_20, _r_T_18, io_bp_0_control_tmatch[0]}});\n wire _w_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _w_T_10 = _w_T_8 & io_bp_0_address[1];\n wire _w_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _w_T_20 = _w_T_18 & io_bp_0_address[1];\n wire w = en & io_bp_0_control_w & (io_bp_0_control_tmatch[1] ? _w_T_2 ^ io_bp_0_control_tmatch[0] : {_w_T_5[38:4], _w_T_5[3:0] | {_w_T_10 & io_bp_0_address[2], _w_T_10, _w_T_8, io_bp_0_control_tmatch[0]}} == {_x_T_15[38:4], _x_T_15[3:0] | {_w_T_20 & io_bp_0_address[2], _w_T_20, _w_T_18, io_bp_0_control_tmatch[0]}});\n wire [38:0] _x_T_5 = ~io_pc;\n wire _x_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _x_T_10 = _x_T_8 & io_bp_0_address[1];\n wire _x_T_18 = io_bp_0_control_tmatch[0] & io_bp_0_address[0];\n wire _x_T_20 = _x_T_18 & io_bp_0_address[1];\n wire x = en & io_bp_0_control_x & (io_bp_0_control_tmatch[1] ? io_pc >= io_bp_0_address ^ io_bp_0_control_tmatch[0] : {_x_T_5[38:4], _x_T_5[3:0] | {_x_T_10 & io_bp_0_address[2], _x_T_10, _x_T_8, io_bp_0_control_tmatch[0]}} == {_x_T_15[38:4], _x_T_15[3:0] | {_x_T_20 & io_bp_0_address[2], _x_T_20, _x_T_18, io_bp_0_control_tmatch[0]}});\n assign io_xcpt_if = x & ~io_bp_0_control_action;\n assign io_xcpt_ld = r & ~io_bp_0_control_action;\n assign io_xcpt_st = w & ~io_bp_0_control_action;\n assign io_debug_if = x & io_bp_0_control_action;\n assign io_debug_ld = r & io_bp_0_control_action;\n assign io_debug_st = w & io_bp_0_control_action;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a21d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [20:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [20:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [20:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleD_a32d64s1k3z4u(\n input clock,\n input reset,\n input io_repeat,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [1:0] io_enq_bits_param,\n input [3:0] io_enq_bits_size,\n input [2:0] io_enq_bits_sink,\n input io_enq_bits_denied,\n input [63:0] io_enq_bits_data,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [1:0] io_deq_bits_param,\n output [3:0] io_deq_bits_size,\n output [2:0] io_deq_bits_sink,\n output io_deq_bits_denied,\n output [63:0] io_deq_bits_data,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [1:0] saved_param;\n reg [3:0] saved_size;\n reg [2:0] saved_sink;\n reg saved_denied;\n reg [63:0] saved_data;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_sink <= io_enq_bits_sink;\n saved_denied <= io_enq_bits_denied;\n saved_data <= io_enq_bits_data;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_sink = full ? saved_sink : io_enq_bits_sink;\n assign io_deq_bits_denied = full ? saved_denied : io_enq_bits_denied;\n assign io_deq_bits_data = full ? saved_data : io_enq_bits_data;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package sifive.blocks.devices.uart\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.util._\n\n/** UARTRx module recivies serial input from Rx port and transmits them to Rx fifo in parallel\n *\n * ==Datapass==\n * Port(Rx) -> sample -> shifter -> Rx fifo -> TL bus\n *\n * ==Structure==\n * - baud rate divisor counter:\n * generate pulse, the enable signal for sample and data shift\n * - sample counter:\n * sample happens in middle\n * - data counter\n * control signals for data shift process\n * - sample and data shift logic\n *\n * ==State Machine==\n * s_idle: detect start bit, init data_count and sample count, start pulse counter\n * s_data: data reciving\n *\n * @note Rx fifo transmits Rx data to TL bus\n */\nclass UARTRx(c: UARTParams) extends Module {\n val io = IO(new Bundle {\n /** enable signal from top */\n val en = Input(Bool())\n /** input data from rx port */\n val in = Input(UInt(1.W))\n /** output data to Rx fifo */\n val out = Valid(UInt(c.dataBits.W))\n /** divisor bits */\n val div = Input(UInt(c.divisorBits.W))\n /** parity enable */\n val enparity = c.includeParity.option(Input(Bool()))\n /** parity select\n *\n * 0 -> even parity\n * 1 -> odd parity\n */\n val parity = c.includeParity.option(Input(Bool()))\n /** parity error bit */\n val errorparity = c.includeParity.option(Output(Bool()))\n /** databit select\n *\n * ture -> 8\n * false -> 9\n */\n val data8or9 = (c.dataBits == 9).option(Input(Bool()))\n })\n\n if (c.includeParity)\n io.errorparity.get := false.B\n\n val debounce = RegInit(0.U(2.W))\n val debounce_max = (debounce === 3.U)\n val debounce_min = (debounce === 0.U)\n\n val prescaler = Reg(UInt((c.divisorBits - c.oversample + 1).W))\n val start = WireDefault(false.B)\n /** enable signal for sampling and data shifting */\n val pulse = (prescaler === 0.U)\n\n private val dataCountBits = log2Floor(c.dataBits+c.includeParity.toInt) + 1\n /** init = data bits(8 or 9) + parity bit(0 or 1) + start bit(1) */\n val data_count = Reg(UInt(dataCountBits.W))\n val data_last = (data_count === 0.U)\n val parity_bit = (data_count === 1.U) && io.enparity.getOrElse(false.B)\n val sample_count = Reg(UInt(c.oversample.W))\n val sample_mid = (sample_count === ((c.oversampleFactor - c.nSamples + 1) >> 1).U)\n // todo unused\n val sample_last = (sample_count === 0.U)\n /** counter for data and sample\n *\n * {{{\n * | data_count | sample_count |\n * }}}\n */\n val countdown = Cat(data_count, sample_count) - 1.U\n\n // Compensate for the divisor not being a multiple of the oversampling period.\n // Let remainder k = (io.div % c.oversampleFactor).\n // For the last k samples, extend the sampling delay by 1 cycle.\n val remainder = io.div(c.oversample-1, 0)\n val extend = (sample_count < remainder) // Pad head: (sample_count > ~remainder)\n /** prescaler reset signal\n *\n * conditions:\n * {{{\n * start : transmisson starts\n * pulse : returns ture every pluse counter period\n * }}}\n */\n val restore = start || pulse\n val prescaler_in = Mux(restore, io.div >> c.oversample, prescaler)\n val prescaler_next = prescaler_in - Mux(restore && extend, 0.U, 1.U)\n /** buffer for sample results */\n val sample = Reg(UInt(c.nSamples.W))\n // take the majority bit of sample buffer\n val voter = Majority(sample.asBools.toSet)\n // data buffer\n val shifter = Reg(UInt(c.dataBits.W))\n\n val valid = RegInit(false.B)\n valid := false.B\n io.out.valid := valid\n io.out.bits := (if (c.dataBits == 8) shifter else Mux(io.data8or9.get, Cat(0.U, shifter(8,1)), shifter))\n\n val (s_idle :: s_data :: Nil) = Enum(2)\n val state = RegInit(s_idle)\n\n switch (state) {\n is (s_idle) {\n // todo !(!io.in)?\n when (!(!io.in) && !debounce_min) {\n debounce := debounce - 1.U\n }\n when (!io.in) {\n debounce := debounce + 1.U\n when (debounce_max) {\n state := s_data\n start := true.B\n prescaler := prescaler_next\n // init data_count\n data_count := (c.dataBits+1).U + (if (c.includeParity) io.enparity.get else 0.U) - io.data8or9.getOrElse(false.B).asUInt\n // init sample_count = 15\n sample_count := (c.oversampleFactor - 1).U\n }\n }\n }\n\n is (s_data) {\n prescaler := prescaler_next\n when (pulse) {\n // sample scan in\n sample := Cat(sample, io.in)\n data_count := countdown >> c.oversample\n sample_count := countdown(c.oversample-1, 0)\n\n when (sample_mid) {\n if (c.includeParity) {\n // act according to frame bit stage at its respective sampling point\n // check parity bit for error\n when (parity_bit) {\n io.errorparity.get := (shifter.asBools.reduce(_ ^ _) ^ voter ^ io.parity.get)\n }\n when (data_last) {\n state := s_idle\n valid := true.B\n } .elsewhen (!parity_bit) {\n // do not add parity bit to final rx data\n shifter := Cat(voter, shifter >> 1)\n }\n } else {\n when (data_last) {\n state := s_idle\n valid := true.B\n } .otherwise {\n shifter := Cat(voter, shifter >> 1)\n }\n }\n }\n }\n }\n }\n\n when (!io.en) {\n debounce := 0.U\n }\n}\n\n/*\n Copyright 2016 SiFive, Inc.\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License.\n*/", + "response": "module UARTRx(\n input clock,\n input reset,\n input io_en,\n input io_in,\n output io_out_valid,\n output [7:0] io_out_bits,\n input [15:0] io_div\n);\n\n reg [1:0] debounce;\n reg [12:0] prescaler;\n reg [3:0] data_count;\n reg [3:0] sample_count;\n reg [2:0] sample;\n reg [7:0] shifter;\n reg valid;\n reg state;\n wire [7:0] _countdown_T_1 = {data_count, sample_count} - 8'h1;\n wire pulse = prescaler == 13'h0;\n wire data_last = data_count == 4'h0;\n wire sample_mid = sample_count == 4'h7;\n wire _GEN = ~io_in & (&debounce);\n wire _GEN_0 = _GEN | state;\n wire _GEN_1 = state & pulse;\n wire _GEN_2 = state & pulse & sample_mid;\n wire restore = ~state & ~io_in & (&debounce) | pulse;\n always @(posedge clock) begin\n if (reset) begin\n debounce <= 2'h0;\n valid <= 1'h0;\n state <= 1'h0;\n end\n else begin\n if (io_en) begin\n if (state) begin\n end\n else if (io_in) begin\n if (io_in & (|debounce))\n debounce <= debounce - 2'h1;\n end\n else\n debounce <= debounce + 2'h1;\n end\n else\n debounce <= 2'h0;\n valid <= _GEN_2 & data_last;\n if (state)\n state <= ~(state & pulse & sample_mid & data_last) & state;\n else\n state <= _GEN_0;\n end\n if (_GEN_0)\n prescaler <= (restore ? {1'h0, io_div[15:4]} : prescaler) - {12'h0, ~(restore & sample_count < io_div[3:0])};\n if (state) begin\n if (_GEN_1) begin\n data_count <= _countdown_T_1[7:4];\n sample_count <= _countdown_T_1[3:0];\n end\n end\n else if (_GEN) begin\n data_count <= 4'h9;\n sample_count <= 4'hF;\n end\n if (_GEN_1)\n sample <= {sample[1:0], io_in};\n if (~state | ~_GEN_2 | data_last) begin\n end\n else\n shifter <= {sample[0] & sample[1] | sample[0] & sample[2] | sample[1] & sample[2], shifter[7:1]};\n end\n assign io_out_valid = valid;\n assign io_out_bits = shifter;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module array_1_0_0(\n input [8:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [8:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n array_0_0_0_ext array_0_0_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}", + "response": "module OptimizationBarrier_TLBEntryData(\n input [19:0] io_x_ppn,\n input io_x_u,\n input io_x_ae_ptw,\n input io_x_ae_final,\n input io_x_pf,\n input io_x_gf,\n input io_x_sx,\n input io_x_px,\n output [19:0] io_y_ppn,\n output io_y_u,\n output io_y_ae_ptw,\n output io_y_ae_final,\n output io_y_pf,\n output io_y_gf,\n output io_y_sx,\n output io_y_px\n);\n\n assign io_y_ppn = io_x_ppn;\n assign io_y_u = io_x_u;\n assign io_y_ae_ptw = io_x_ae_ptw;\n assign io_y_ae_final = io_x_ae_final;\n assign io_y_pf = io_x_pf;\n assign io_y_gf = io_x_gf;\n assign io_y_sx = io_x_sx;\n assign io_y_px = io_x_px;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket.Instructions32\nimport freechips.rocketchip.rocket.CustomInstructions._\nimport freechips.rocketchip.rocket.RVCExpander\nimport freechips.rocketchip.rocket.{CSR,Causes}\nimport freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.util._\n\n// scalastyle:off\n/**\n * Abstract trait giving defaults and other relevant values to different Decode constants/\n */\nabstract trait DecodeConstants\n extends freechips.rocketchip.rocket.constants.ScalarOpConstants\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val xpr64 = Y // TODO inform this from xLen\n val DC2 = BitPat.dontCare(2) // Makes the listing below more readable\n def decode_default: List[BitPat] =\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)\n\n val table: Array[(BitPat, List[BitPat])]\n}\n// scalastyle:on\n\n/**\n * Decoded control signals\n */\nclass CtrlSigs extends Bundle\n{\n val legal = Bool()\n val fp_val = Bool()\n val fp_single = Bool()\n val uopc = UInt(UOPC_SZ.W)\n val iq_type = UInt(IQT_SZ.W)\n val fu_code = UInt(FUC_SZ.W)\n val dst_type = UInt(2.W)\n val rs1_type = UInt(2.W)\n val rs2_type = UInt(2.W)\n val frs3_en = Bool()\n val imm_sel = UInt(IS_X.getWidth.W)\n val uses_ldq = Bool()\n val uses_stq = Bool()\n val is_amo = Bool()\n val is_fence = Bool()\n val is_fencei = Bool()\n val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)\n val wakeup_delay = UInt(2.W)\n val bypassable = Bool()\n val is_br = Bool()\n val is_sys_pc2epc = Bool()\n val inst_unique = Bool()\n val flush_on_commit = Bool()\n val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)\n val rocc = Bool()\n\n def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)\n val sigs =\n Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,\n rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,\n is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,\n is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n rocc := false.B\n this\n }\n}\n\n// scalastyle:off\n/**\n * Decode constants for RV32\n */\nobject X32Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n Instructions32.SLLI ->\n List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRLI ->\n List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRAI ->\n List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Decode constants for RV64\n */\nobject X64Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Overall Decode constants\n */\nobject XDecode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n\n SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read\n JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n\n // I-type, the immediate12 holds the CSR register.\n CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),\n ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),\n FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance\n // currently serializes pipeline\n\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // A-type | | | | | | | | | | | | | | | | | | | | | | | |\n AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance\n AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),\n AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),\n SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)\n )\n}\n\n/**\n * FP Decode constants\n */\nobject FDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops\n FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to FP\n FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // Int to FP\n FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to Int\n FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // \"fp_single\" is used for wb_data formatting (and debugging)\n FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * FP Divide SquareRoot Constants\n */\nobject FDivSqrtDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n//scalastyle:on\n\n/**\n * RoCC initial decode\n */\nobject RoCCDecode extends DecodeConstants\n{\n // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec rs1 regtype | | | uses_stq | | |\n // | | | | rs2 type| | | | is_amo | | |\n // | | | micro-code func unit | | | | | | | is_fence | | |\n // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |\n CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n\n\n\n\n/**\n * IO bundle for the Decode unit\n */\nclass DecodeUnitIo(implicit p: Parameters) extends BoomBundle\n{\n val enq = new Bundle { val uop = Input(new MicroOp()) }\n val deq = new Bundle { val uop = Output(new MicroOp()) }\n\n // from CSRFile\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)\n val interrupt = Input(Bool())\n val interrupt_cause = Input(UInt(xLen.W))\n}\n\n/**\n * Decode unit that takes in a single instruction and generates a MicroOp.\n */\nclass DecodeUnit(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new DecodeUnitIo)\n\n val uop = Wire(new MicroOp())\n uop := io.enq.uop\n\n var decode_table = XDecode.table\n if (usingFPU) decode_table ++= FDecode.table\n if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table\n if (usingRoCC) decode_table ++= RoCCDecode.table\n decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)\n\n val inst = uop.inst\n\n val cs = Wire(new CtrlSigs()).decode(inst, decode_table)\n\n // Exception Handling\n io.csr_decode.inst := inst\n val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)\n val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U\n val system_insn = cs.csr_cmd === CSR.I\n val sfence = cs.uopc === uopSFENCE\n\n val cs_legal = cs.legal\n// dontTouch(cs_legal)\n\n val id_illegal_insn = !cs_legal ||\n cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)\n cs.rocc && io.csr_decode.rocc_illegal ||\n cs.is_amo && !io.status.isa('a'-'a') ||\n (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||\n csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||\n ((sfence || system_insn) && io.csr_decode.system_illegal)\n\n// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n\n val (xcpt_valid, xcpt_cause) = checkExceptions(List(\n (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB\n (uop.bp_debug_if, (CSR.debugTriggerCause).U),\n (uop.bp_xcpt_if, (Causes.breakpoint).U),\n (uop.xcpt_pf_if, (Causes.fetch_page_fault).U),\n (uop.xcpt_ae_if, (Causes.fetch_access).U),\n (id_illegal_insn, (Causes.illegal_instruction).U)))\n\n uop.exception := xcpt_valid\n uop.exc_cause := xcpt_cause\n\n //-------------------------------------------------------------\n\n uop.uopc := cs.uopc\n uop.iq_type := cs.iq_type\n uop.fu_code := cs.fu_code\n\n // x-registers placed in 0-31, f-registers placed in 32-63.\n // This allows us to straight-up compare register specifiers and not need to\n // verify the rtypes (e.g., bypassing in rename).\n uop.ldst := inst(RD_MSB,RD_LSB)\n uop.lrs1 := inst(RS1_MSB,RS1_LSB)\n uop.lrs2 := inst(RS2_MSB,RS2_LSB)\n uop.lrs3 := inst(RS3_MSB,RS3_LSB)\n\n uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)\n uop.dst_rtype := cs.dst_type\n uop.lrs1_rtype := cs.rs1_type\n uop.lrs2_rtype := cs.rs2_type\n uop.frs3_en := cs.frs3_en\n\n uop.ldst_is_rs1 := uop.is_sfb_shadow\n // SFB optimization\n when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {\n uop.lrs2_rtype := RT_FIX\n uop.lrs2 := inst(RD_MSB,RD_LSB)\n uop.ldst_is_rs1 := false.B\n } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {\n uop.uopc := uopMOV\n uop.lrs1 := inst(RD_MSB, RD_LSB)\n uop.ldst_is_rs1 := true.B\n }\n when (uop.is_sfb_br) {\n uop.fu_code := FU_JMP\n }\n\n\n uop.fp_val := cs.fp_val\n uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?\n\n uop.mem_cmd := cs.mem_cmd\n uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))\n uop.mem_signed := !inst(14)\n uop.uses_ldq := cs.uses_ldq\n uop.uses_stq := cs.uses_stq\n uop.is_amo := cs.is_amo\n uop.is_fence := cs.is_fence\n uop.is_fencei := cs.is_fencei\n uop.is_sys_pc2epc := cs.is_sys_pc2epc\n uop.is_unique := cs.inst_unique\n uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)\n\n uop.bypassable := cs.bypassable\n\n //-------------------------------------------------------------\n // immediates\n\n // repackage the immediate, and then pass the fewest number of bits around\n val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))\n uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))\n\n //-------------------------------------------------------------\n\n uop.is_br := cs.is_br\n uop.is_jal := (uop.uopc === uopJAL)\n uop.is_jalr := (uop.uopc === uopJALR)\n // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)\n // uop.is_ret := (uop.uopc === uopJALR) &&\n // (uop.ldst === X0) &&\n // (uop.lrs1 === RA)\n // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&\n // (uop.ldst === RA)\n\n //-------------------------------------------------------------\n\n io.deq.uop := uop\n}\n\n/**\n * Smaller Decode unit for the Frontend to decode different\n * branches.\n * Accepts EXPANDED RVC instructions\n */\n\nclass BranchDecodeSignals(implicit p: Parameters) extends BoomBundle\n{\n val is_ret = Bool()\n val is_call = Bool()\n val target = UInt(vaddrBitsExtended.W)\n val cfi_type = UInt(CFI_SZ.W)\n\n\n // Is this branch a short forwards jump?\n val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))\n // Is this instruction allowed to be inside a sfb?\n val shadowable = Bool()\n}\n\nclass BranchDecode(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val inst = Input(UInt(32.W))\n val pc = Input(UInt(vaddrBitsExtended.W))\n\n val out = Output(new BranchDecodeSignals)\n })\n\n val bpd_csignals =\n freechips.rocketchip.rocket.DecodeLogic(io.inst,\n List[BitPat](N, N, N, N, X),\n//// is br?\n//// | is jal?\n//// | | is jalr?\n//// | | |\n//// | | | shadowable\n//// | | | | has_rs2\n//// | | | | |\n Array[(BitPat, List[BitPat])](\n JAL -> List(N, Y, N, N, X),\n JALR -> List(N, N, Y, N, X),\n BEQ -> List(Y, N, N, N, X),\n BNE -> List(Y, N, N, N, X),\n BGE -> List(Y, N, N, N, X),\n BGEU -> List(Y, N, N, N, X),\n BLT -> List(Y, N, N, N, X),\n BLTU -> List(Y, N, N, N, X),\n\n SLLI -> List(N, N, N, Y, N),\n SRLI -> List(N, N, N, Y, N),\n SRAI -> List(N, N, N, Y, N),\n\n ADDIW -> List(N, N, N, Y, N),\n SLLIW -> List(N, N, N, Y, N),\n SRAIW -> List(N, N, N, Y, N),\n SRLIW -> List(N, N, N, Y, N),\n\n ADDW -> List(N, N, N, Y, Y),\n SUBW -> List(N, N, N, Y, Y),\n SLLW -> List(N, N, N, Y, Y),\n SRAW -> List(N, N, N, Y, Y),\n SRLW -> List(N, N, N, Y, Y),\n\n LUI -> List(N, N, N, Y, N),\n\n ADDI -> List(N, N, N, Y, N),\n ANDI -> List(N, N, N, Y, N),\n ORI -> List(N, N, N, Y, N),\n XORI -> List(N, N, N, Y, N),\n SLTI -> List(N, N, N, Y, N),\n SLTIU -> List(N, N, N, Y, N),\n\n SLL -> List(N, N, N, Y, Y),\n ADD -> List(N, N, N, Y, Y),\n SUB -> List(N, N, N, Y, Y),\n SLT -> List(N, N, N, Y, Y),\n SLTU -> List(N, N, N, Y, Y),\n AND -> List(N, N, N, Y, Y),\n OR -> List(N, N, N, Y, Y),\n XOR -> List(N, N, N, Y, Y),\n SRA -> List(N, N, N, Y, Y),\n SRL -> List(N, N, N, Y, Y)\n ))\n\n val cs_is_br = bpd_csignals(0)(0)\n val cs_is_jal = bpd_csignals(1)(0)\n val cs_is_jalr = bpd_csignals(2)(0)\n val cs_is_shadowable = bpd_csignals(3)(0)\n val cs_has_rs2 = bpd_csignals(4)(0)\n\n io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA\n io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat(\"b00?01\") && GetRd(io.inst) === X0\n\n io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),\n ComputeJALTarget(io.pc, io.inst, xLen))\n io.out.cfi_type :=\n Mux(cs_is_jalr,\n CFI_JALR,\n Mux(cs_is_jal,\n CFI_JAL,\n Mux(cs_is_br,\n CFI_BR,\n CFI_X)))\n\n val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))\n // Is a sfb if it points forwards (offset is positive)\n io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U\n io.out.sfb_offset.bits := br_offset\n io.out.shadowable := cs_is_shadowable && (\n !cs_has_rs2 ||\n (GetRs1(io.inst) === GetRd(io.inst)) ||\n (io.inst === ADD && GetRs1(io.inst) === X0)\n )\n}\n\n/**\n * Track the current \"branch mask\", and give out the branch mask to each micro-op in Decode\n * (each micro-op in the machine has a branch mask which says which branches it\n * is being speculated under).\n *\n * @param pl_width pipeline width for the processor\n */\nclass BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n // guess if the uop is a branch (we'll catch this later)\n val is_branch = Input(Vec(pl_width, Bool()))\n // lock in that it's actually a branch and will fire, so we update\n // the branch_masks.\n val will_fire = Input(Vec(pl_width, Bool()))\n\n // give out tag immediately (needed in rename)\n // mask can come later in the cycle\n val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))\n val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))\n\n // tell decoders the branch mask has filled up, but on the granularity\n // of an individual micro-op (so some micro-ops can go through)\n val is_full = Output(Vec(pl_width, Bool()))\n\n val brupdate = Input(new BrUpdateInfo())\n val flush_pipeline = Input(Bool())\n\n val debug_branch_mask = Output(UInt(maxBrCount.W))\n })\n\n val branch_mask = RegInit(0.U(maxBrCount.W))\n\n //-------------------------------------------------------------\n // Give out the branch tag to each branch micro-op\n\n var allocate_mask = branch_mask\n val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))\n\n for (w <- 0 until pl_width) {\n // TODO this is a loss of performance as we're blocking branches based on potentially fake branches\n io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)\n\n // find br_tag and compute next br_mask\n val new_br_tag = Wire(UInt(brTagSz.W))\n new_br_tag := 0.U\n tag_masks(w) := 0.U\n\n for (i <- maxBrCount-1 to 0 by -1) {\n when (~allocate_mask(i)) {\n new_br_tag := i.U\n tag_masks(w) := (1.U << i.U)\n }\n }\n\n io.br_tag(w) := new_br_tag\n allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)\n }\n\n //-------------------------------------------------------------\n // Give out the branch mask to each micro-op\n // (kill off the bits that corresponded to branches that aren't going to fire)\n\n var curr_mask = branch_mask\n for (w <- 0 until pl_width) {\n io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)\n curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)\n }\n\n //-------------------------------------------------------------\n // Update the current branch_mask\n\n when (io.flush_pipeline) {\n branch_mask := 0.U\n } .otherwise {\n val mask = Mux(io.brupdate.b2.mispredict,\n io.brupdate.b2.uop.br_mask,\n ~(0.U(maxBrCount.W)))\n branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask\n }\n\n io.debug_branch_mask := branch_mask\n}", + "response": "module DecodeUnit(\n input [31:0] io_enq_uop_inst,\n input [31:0] io_enq_uop_debug_inst,\n input io_enq_uop_is_rvc,\n input [39:0] io_enq_uop_debug_pc,\n input io_enq_uop_is_sfb,\n input [3:0] io_enq_uop_ftq_idx,\n input io_enq_uop_edge_inst,\n input [5:0] io_enq_uop_pc_lob,\n input io_enq_uop_taken,\n input io_enq_uop_xcpt_pf_if,\n input io_enq_uop_xcpt_ae_if,\n input io_enq_uop_bp_debug_if,\n input io_enq_uop_bp_xcpt_if,\n input [1:0] io_enq_uop_debug_fsrc,\n output [6:0] io_deq_uop_uopc,\n output [31:0] io_deq_uop_inst,\n output [31:0] io_deq_uop_debug_inst,\n output io_deq_uop_is_rvc,\n output [39:0] io_deq_uop_debug_pc,\n output [2:0] io_deq_uop_iq_type,\n output [9:0] io_deq_uop_fu_code,\n output io_deq_uop_is_br,\n output io_deq_uop_is_jalr,\n output io_deq_uop_is_jal,\n output io_deq_uop_is_sfb,\n output [3:0] io_deq_uop_ftq_idx,\n output io_deq_uop_edge_inst,\n output [5:0] io_deq_uop_pc_lob,\n output io_deq_uop_taken,\n output [19:0] io_deq_uop_imm_packed,\n output io_deq_uop_exception,\n output [63:0] io_deq_uop_exc_cause,\n output io_deq_uop_bypassable,\n output [4:0] io_deq_uop_mem_cmd,\n output [1:0] io_deq_uop_mem_size,\n output io_deq_uop_mem_signed,\n output io_deq_uop_is_fence,\n output io_deq_uop_is_fencei,\n output io_deq_uop_is_amo,\n output io_deq_uop_uses_ldq,\n output io_deq_uop_uses_stq,\n output io_deq_uop_is_sys_pc2epc,\n output io_deq_uop_is_unique,\n output io_deq_uop_flush_on_commit,\n output [5:0] io_deq_uop_ldst,\n output [5:0] io_deq_uop_lrs1,\n output [5:0] io_deq_uop_lrs2,\n output [5:0] io_deq_uop_lrs3,\n output io_deq_uop_ldst_val,\n output [1:0] io_deq_uop_dst_rtype,\n output [1:0] io_deq_uop_lrs1_rtype,\n output [1:0] io_deq_uop_lrs2_rtype,\n output io_deq_uop_frs3_en,\n output io_deq_uop_fp_val,\n output io_deq_uop_fp_single,\n output io_deq_uop_xcpt_pf_if,\n output io_deq_uop_xcpt_ae_if,\n output io_deq_uop_bp_debug_if,\n output io_deq_uop_bp_xcpt_if,\n output [1:0] io_deq_uop_debug_fsrc,\n output [31:0] io_csr_decode_inst,\n input io_csr_decode_fp_illegal,\n input io_csr_decode_read_illegal,\n input io_csr_decode_write_illegal,\n input io_csr_decode_write_flush,\n input io_csr_decode_system_illegal,\n input io_interrupt,\n input [63:0] io_interrupt_cause\n);\n\n wire [4:0] _uop_lrs1_T;\n wire [29:0] cs_decoder_decoded_invInputs = ~(io_enq_uop_inst[31:2]);\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11]};\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[12]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[4]};\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4]};\n wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[12]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6]};\n wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24]};\n wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11]};\n wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6]};\n wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {io_enq_uop_inst[0], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12]};\n wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]};\n wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[13]};\n wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]};\n wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[14]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], io_enq_uop_inst[14]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], io_enq_uop_inst[14]};\n wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[13], io_enq_uop_inst[14]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[27], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {io_enq_uop_inst[0], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[18], io_enq_uop_inst[21], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[18], io_enq_uop_inst[21], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], io_enq_uop_inst[20], cs_decoder_decoded_invInputs[19], io_enq_uop_inst[22], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], io_enq_uop_inst[20], cs_decoder_decoded_invInputs[19], io_enq_uop_inst[22], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[27], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]};\n wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]};\n wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[20], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30]};\n wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[20], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30]};\n wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[18], io_enq_uop_inst[21], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], io_enq_uop_inst[24], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], io_enq_uop_inst[29], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[5], cs_decoder_decoded_invInputs[6], cs_decoder_decoded_invInputs[7], cs_decoder_decoded_invInputs[8], cs_decoder_decoded_invInputs[9], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[13], cs_decoder_decoded_invInputs[14], cs_decoder_decoded_invInputs[15], cs_decoder_decoded_invInputs[16], cs_decoder_decoded_invInputs[17], cs_decoder_decoded_invInputs[18], io_enq_uop_inst[21], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], io_enq_uop_inst[24], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], io_enq_uop_inst[29], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], io_enq_uop_inst[31]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], io_enq_uop_inst[31]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_169 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_174 = {io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]};\n wire [36:0] _cs_decoder_decoded_orMatrixOutputs_T_76 =\n {&_cs_decoder_decoded_andMatrixOutputs_T_2,\n &_cs_decoder_decoded_andMatrixOutputs_T_8,\n &_cs_decoder_decoded_andMatrixOutputs_T_11,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_43,\n &_cs_decoder_decoded_andMatrixOutputs_T_48,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13]},\n &_cs_decoder_decoded_andMatrixOutputs_T_62,\n &_cs_decoder_decoded_andMatrixOutputs_T_70,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_75,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_92,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[13], io_enq_uop_inst[14]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_108,\n &_cs_decoder_decoded_andMatrixOutputs_T_115,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_118,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_124,\n &_cs_decoder_decoded_andMatrixOutputs_T_129,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_151,\n &_cs_decoder_decoded_andMatrixOutputs_T_154,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], io_enq_uop_inst[31]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]}};\n wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_92 = {&_cs_decoder_decoded_andMatrixOutputs_T_25, &_cs_decoder_decoded_andMatrixOutputs_T_33, &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]}, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_162, &_cs_decoder_decoded_andMatrixOutputs_T_167, &_cs_decoder_decoded_andMatrixOutputs_T_169};\n wire [6:0] cs_uopc =\n {|{&_cs_decoder_decoded_andMatrixOutputs_T_24, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_70, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], io_enq_uop_inst[13], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]}, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_129, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_156, &_cs_decoder_decoded_andMatrixOutputs_T_161, &_cs_decoder_decoded_andMatrixOutputs_T_162},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_6, &_cs_decoder_decoded_andMatrixOutputs_T_11, &_cs_decoder_decoded_andMatrixOutputs_T_12, &_cs_decoder_decoded_andMatrixOutputs_T_22, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24]}, &_cs_decoder_decoded_andMatrixOutputs_T_42, &_cs_decoder_decoded_andMatrixOutputs_T_43, &_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_50, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], io_enq_uop_inst[13]}, &_cs_decoder_decoded_andMatrixOutputs_T_84, &_cs_decoder_decoded_andMatrixOutputs_T_92, &_cs_decoder_decoded_andMatrixOutputs_T_95, &_cs_decoder_decoded_andMatrixOutputs_T_96, &_cs_decoder_decoded_andMatrixOutputs_T_97, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24]}, &_cs_decoder_decoded_andMatrixOutputs_T_108, &_cs_decoder_decoded_andMatrixOutputs_T_109, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_129, &_cs_decoder_decoded_andMatrixOutputs_T_131, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_156},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_28,\n &_cs_decoder_decoded_andMatrixOutputs_T_30,\n &_cs_decoder_decoded_andMatrixOutputs_T_35,\n &_cs_decoder_decoded_andMatrixOutputs_T_37,\n &_cs_decoder_decoded_andMatrixOutputs_T_40,\n &_cs_decoder_decoded_andMatrixOutputs_T_56,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_75,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_81,\n &_cs_decoder_decoded_andMatrixOutputs_T_84,\n &_cs_decoder_decoded_andMatrixOutputs_T_86,\n &_cs_decoder_decoded_andMatrixOutputs_T_88,\n &_cs_decoder_decoded_andMatrixOutputs_T_96,\n &_cs_decoder_decoded_andMatrixOutputs_T_97,\n &_cs_decoder_decoded_andMatrixOutputs_T_108,\n &_cs_decoder_decoded_andMatrixOutputs_T_145,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_159,\n &_cs_decoder_decoded_andMatrixOutputs_T_160,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]}},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_6,\n &_cs_decoder_decoded_andMatrixOutputs_T_12,\n &_cs_decoder_decoded_andMatrixOutputs_T_19,\n &_cs_decoder_decoded_andMatrixOutputs_T_22,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_28,\n &_cs_decoder_decoded_andMatrixOutputs_T_30,\n &_cs_decoder_decoded_andMatrixOutputs_T_40,\n &_cs_decoder_decoded_andMatrixOutputs_T_44,\n &_cs_decoder_decoded_andMatrixOutputs_T_48,\n &_cs_decoder_decoded_andMatrixOutputs_T_52,\n &_cs_decoder_decoded_andMatrixOutputs_T_56,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]},\n &_cs_decoder_decoded_andMatrixOutputs_T_75,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14]},\n &_cs_decoder_decoded_andMatrixOutputs_T_81,\n &_cs_decoder_decoded_andMatrixOutputs_T_83,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_108,\n &_cs_decoder_decoded_andMatrixOutputs_T_109,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_122,\n &_cs_decoder_decoded_andMatrixOutputs_T_124,\n &_cs_decoder_decoded_andMatrixOutputs_T_128,\n &_cs_decoder_decoded_andMatrixOutputs_T_139,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_149,\n &_cs_decoder_decoded_andMatrixOutputs_T_151,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_156,\n &_cs_decoder_decoded_andMatrixOutputs_T_162},\n |{&{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]},\n &_cs_decoder_decoded_andMatrixOutputs_T_10,\n &_cs_decoder_decoded_andMatrixOutputs_T_19,\n &_cs_decoder_decoded_andMatrixOutputs_T_22,\n &_cs_decoder_decoded_andMatrixOutputs_T_28,\n &_cs_decoder_decoded_andMatrixOutputs_T_30,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_42,\n &_cs_decoder_decoded_andMatrixOutputs_T_43,\n &_cs_decoder_decoded_andMatrixOutputs_T_52,\n &_cs_decoder_decoded_andMatrixOutputs_T_59,\n &_cs_decoder_decoded_andMatrixOutputs_T_75,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[14]},\n &_cs_decoder_decoded_andMatrixOutputs_T_83,\n &_cs_decoder_decoded_andMatrixOutputs_T_87,\n &_cs_decoder_decoded_andMatrixOutputs_T_93,\n &_cs_decoder_decoded_andMatrixOutputs_T_98,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], io_enq_uop_inst[13], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[28], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_131,\n &_cs_decoder_decoded_andMatrixOutputs_T_145,\n &_cs_decoder_decoded_andMatrixOutputs_T_154,\n &_cs_decoder_decoded_andMatrixOutputs_T_162,\n &_cs_decoder_decoded_andMatrixOutputs_T_167},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_6,\n &_cs_decoder_decoded_andMatrixOutputs_T_11,\n &_cs_decoder_decoded_andMatrixOutputs_T_12,\n &_cs_decoder_decoded_andMatrixOutputs_T_13,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_42,\n &_cs_decoder_decoded_andMatrixOutputs_T_44,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_50,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_59,\n &_cs_decoder_decoded_andMatrixOutputs_T_68,\n &_cs_decoder_decoded_andMatrixOutputs_T_70,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], io_enq_uop_inst[13]},\n &_cs_decoder_decoded_andMatrixOutputs_T_87,\n &_cs_decoder_decoded_andMatrixOutputs_T_88,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], io_enq_uop_inst[14]},\n &_cs_decoder_decoded_andMatrixOutputs_T_93,\n &_cs_decoder_decoded_andMatrixOutputs_T_95,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13], io_enq_uop_inst[14], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_115,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], io_enq_uop_inst[27], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_122,\n &_cs_decoder_decoded_andMatrixOutputs_T_128,\n &_cs_decoder_decoded_andMatrixOutputs_T_149,\n &_cs_decoder_decoded_andMatrixOutputs_T_151,\n &_cs_decoder_decoded_andMatrixOutputs_T_154,\n &_cs_decoder_decoded_andMatrixOutputs_T_156,\n &_cs_decoder_decoded_andMatrixOutputs_T_164,\n &_cs_decoder_decoded_andMatrixOutputs_T_169},\n |_cs_decoder_decoded_orMatrixOutputs_T_76};\n wire [1:0] cs_dst_type =\n {{&_cs_decoder_decoded_andMatrixOutputs_T, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_8, &_cs_decoder_decoded_andMatrixOutputs_T_10, &_cs_decoder_decoded_andMatrixOutputs_T_14, &_cs_decoder_decoded_andMatrixOutputs_T_15, &_cs_decoder_decoded_andMatrixOutputs_T_16, &_cs_decoder_decoded_andMatrixOutputs_T_25, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_42, &_cs_decoder_decoded_andMatrixOutputs_T_43, &_cs_decoder_decoded_andMatrixOutputs_T_47, &_cs_decoder_decoded_andMatrixOutputs_T_50, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_62, &_cs_decoder_decoded_andMatrixOutputs_T_66, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_83, &_cs_decoder_decoded_andMatrixOutputs_T_84, &_cs_decoder_decoded_andMatrixOutputs_T_86, &_cs_decoder_decoded_andMatrixOutputs_T_106, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_121, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_162, &_cs_decoder_decoded_andMatrixOutputs_T_167, &_cs_decoder_decoded_andMatrixOutputs_T_169} == 33'h0,\n |{&_cs_decoder_decoded_andMatrixOutputs_T_25, &_cs_decoder_decoded_andMatrixOutputs_T_33, &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]}, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_139, &_cs_decoder_decoded_andMatrixOutputs_T_150, &_cs_decoder_decoded_andMatrixOutputs_T_152, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_166, &_cs_decoder_decoded_andMatrixOutputs_T_174}};\n wire [2:0] cs_imm_sel = {&_cs_decoder_decoded_andMatrixOutputs_T_43, |{&_cs_decoder_decoded_andMatrixOutputs_T_10, &_cs_decoder_decoded_andMatrixOutputs_T_40, &_cs_decoder_decoded_andMatrixOutputs_T_81}, |{&_cs_decoder_decoded_andMatrixOutputs_T_10, &_cs_decoder_decoded_andMatrixOutputs_T_13, &_cs_decoder_decoded_andMatrixOutputs_T_68}};\n wire [4:0] cs_mem_cmd = {&_cs_decoder_decoded_andMatrixOutputs_T_127, &_cs_decoder_decoded_andMatrixOutputs_T_70, |{&_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_118, &_cs_decoder_decoded_andMatrixOutputs_T_127, &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[31]}}, |{&_cs_decoder_decoded_andMatrixOutputs_T_118, &_cs_decoder_decoded_andMatrixOutputs_T_132, &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[30]}}, |{&_cs_decoder_decoded_andMatrixOutputs_T_13, &_cs_decoder_decoded_andMatrixOutputs_T_68, &_cs_decoder_decoded_andMatrixOutputs_T_132, &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29]}}};\n wire [2:0] cs_csr_cmd = {|{&_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_156}, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_58};\n wire _csr_ren_T = cs_csr_cmd == 3'h6;\n wire csr_en = _csr_ren_T | (&cs_csr_cmd) | cs_csr_cmd == 3'h5;\n wire csr_ren = (_csr_ren_T | (&cs_csr_cmd)) & _uop_lrs1_T == 5'h0;\n wire _GEN = io_interrupt & ~io_enq_uop_is_sfb;\n assign _uop_lrs1_T = io_enq_uop_inst[19:15];\n assign io_deq_uop_uopc = cs_uopc;\n assign io_deq_uop_inst = io_enq_uop_inst;\n assign io_deq_uop_debug_inst = io_enq_uop_debug_inst;\n assign io_deq_uop_is_rvc = io_enq_uop_is_rvc;\n assign io_deq_uop_debug_pc = io_enq_uop_debug_pc;\n assign io_deq_uop_iq_type = {|{&_cs_decoder_decoded_andMatrixOutputs_T_25, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_69, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_164, &_cs_decoder_decoded_andMatrixOutputs_T_169}, |{&_cs_decoder_decoded_andMatrixOutputs_T_1, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_3, &_cs_decoder_decoded_andMatrixOutputs_T_61, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_121, &_cs_decoder_decoded_andMatrixOutputs_T_130}, {&_cs_decoder_decoded_andMatrixOutputs_T_1, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_3, &_cs_decoder_decoded_andMatrixOutputs_T_25, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_61, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_121, &_cs_decoder_decoded_andMatrixOutputs_T_130, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_164, &_cs_decoder_decoded_andMatrixOutputs_T_169} == 18'h0};\n assign io_deq_uop_fu_code =\n {|{&_cs_decoder_decoded_andMatrixOutputs_T_69, &_cs_decoder_decoded_andMatrixOutputs_T_159, &_cs_decoder_decoded_andMatrixOutputs_T_160, &_cs_decoder_decoded_andMatrixOutputs_T_164, &_cs_decoder_decoded_andMatrixOutputs_T_169},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_166, &_cs_decoder_decoded_andMatrixOutputs_T_174},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_131, &_cs_decoder_decoded_andMatrixOutputs_T_153},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_24, &_cs_decoder_decoded_andMatrixOutputs_T_35, &_cs_decoder_decoded_andMatrixOutputs_T_37, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_139, &_cs_decoder_decoded_andMatrixOutputs_T_150, &_cs_decoder_decoded_andMatrixOutputs_T_152},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_156},\n &_cs_decoder_decoded_andMatrixOutputs_T_106,\n |{&_cs_decoder_decoded_andMatrixOutputs_T_98, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[4], io_enq_uop_inst[5], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], io_enq_uop_inst[25], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]}},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_1, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_3, &_cs_decoder_decoded_andMatrixOutputs_T_6, &_cs_decoder_decoded_andMatrixOutputs_T_61, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_118, &_cs_decoder_decoded_andMatrixOutputs_T_129},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_11, &_cs_decoder_decoded_andMatrixOutputs_T_42, &_cs_decoder_decoded_andMatrixOutputs_T_43},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_7, &_cs_decoder_decoded_andMatrixOutputs_T_8, &_cs_decoder_decoded_andMatrixOutputs_T_14, &_cs_decoder_decoded_andMatrixOutputs_T_17, &_cs_decoder_decoded_andMatrixOutputs_T_21, &_cs_decoder_decoded_andMatrixOutputs_T_40, &_cs_decoder_decoded_andMatrixOutputs_T_48, &_cs_decoder_decoded_andMatrixOutputs_T_50, &_cs_decoder_decoded_andMatrixOutputs_T_66, &_cs_decoder_decoded_andMatrixOutputs_T_81, &_cs_decoder_decoded_andMatrixOutputs_T_83, &_cs_decoder_decoded_andMatrixOutputs_T_84, &_cs_decoder_decoded_andMatrixOutputs_T_86}};\n assign io_deq_uop_is_br = |{&_cs_decoder_decoded_andMatrixOutputs_T_40, &_cs_decoder_decoded_andMatrixOutputs_T_81};\n assign io_deq_uop_is_jalr = cs_uopc == 7'h26;\n assign io_deq_uop_is_jal = cs_uopc == 7'h25;\n assign io_deq_uop_is_sfb = io_enq_uop_is_sfb;\n assign io_deq_uop_ftq_idx = io_enq_uop_ftq_idx;\n assign io_deq_uop_edge_inst = io_enq_uop_edge_inst;\n assign io_deq_uop_pc_lob = io_enq_uop_pc_lob;\n assign io_deq_uop_taken = io_enq_uop_taken;\n assign io_deq_uop_imm_packed = {io_enq_uop_inst[31:25], cs_imm_sel == 3'h2 | cs_imm_sel == 3'h1 ? io_enq_uop_inst[11:7] : io_enq_uop_inst[24:20], io_enq_uop_inst[19:12]};\n assign io_deq_uop_exception =\n _GEN | io_enq_uop_bp_debug_if | io_enq_uop_bp_xcpt_if | io_enq_uop_xcpt_pf_if | io_enq_uop_xcpt_ae_if\n | {&_cs_decoder_decoded_andMatrixOutputs_T,\n &_cs_decoder_decoded_andMatrixOutputs_T_2,\n &_cs_decoder_decoded_andMatrixOutputs_T_3,\n &_cs_decoder_decoded_andMatrixOutputs_T_5,\n &_cs_decoder_decoded_andMatrixOutputs_T_8,\n &_cs_decoder_decoded_andMatrixOutputs_T_10,\n &_cs_decoder_decoded_andMatrixOutputs_T_14,\n &_cs_decoder_decoded_andMatrixOutputs_T_15,\n &_cs_decoder_decoded_andMatrixOutputs_T_16,\n &_cs_decoder_decoded_andMatrixOutputs_T_25,\n &_cs_decoder_decoded_andMatrixOutputs_T_33,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], io_enq_uop_inst[5], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]},\n &_cs_decoder_decoded_andMatrixOutputs_T_43,\n &_cs_decoder_decoded_andMatrixOutputs_T_45,\n &_cs_decoder_decoded_andMatrixOutputs_T_47,\n &_cs_decoder_decoded_andMatrixOutputs_T_50,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[5], io_enq_uop_inst[6], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11]},\n &_cs_decoder_decoded_andMatrixOutputs_T_61,\n &_cs_decoder_decoded_andMatrixOutputs_T_66,\n &_cs_decoder_decoded_andMatrixOutputs_T_70,\n &_cs_decoder_decoded_andMatrixOutputs_T_73,\n &_cs_decoder_decoded_andMatrixOutputs_T_81,\n &_cs_decoder_decoded_andMatrixOutputs_T_83,\n &_cs_decoder_decoded_andMatrixOutputs_T_84,\n &_cs_decoder_decoded_andMatrixOutputs_T_86,\n &_cs_decoder_decoded_andMatrixOutputs_T_106,\n &_cs_decoder_decoded_andMatrixOutputs_T_115,\n &_cs_decoder_decoded_andMatrixOutputs_T_121,\n &_cs_decoder_decoded_andMatrixOutputs_T_123,\n &_cs_decoder_decoded_andMatrixOutputs_T_125,\n &_cs_decoder_decoded_andMatrixOutputs_T_130,\n &_cs_decoder_decoded_andMatrixOutputs_T_133,\n &_cs_decoder_decoded_andMatrixOutputs_T_134,\n &_cs_decoder_decoded_andMatrixOutputs_T_137,\n &_cs_decoder_decoded_andMatrixOutputs_T_149,\n &_cs_decoder_decoded_andMatrixOutputs_T_151,\n &_cs_decoder_decoded_andMatrixOutputs_T_153,\n &_cs_decoder_decoded_andMatrixOutputs_T_157,\n &_cs_decoder_decoded_andMatrixOutputs_T_162,\n &_cs_decoder_decoded_andMatrixOutputs_T_167,\n &_cs_decoder_decoded_andMatrixOutputs_T_169} == 41'h0 | (|_cs_decoder_decoded_orMatrixOutputs_T_92) & io_csr_decode_fp_illegal | csr_en & (io_csr_decode_read_illegal | ~csr_ren & io_csr_decode_write_illegal) | (cs_uopc == 7'h6B | cs_csr_cmd == 3'h4) & io_csr_decode_system_illegal;\n assign io_deq_uop_exc_cause = _GEN ? io_interrupt_cause : {60'h0, io_enq_uop_bp_debug_if ? 4'hE : io_enq_uop_bp_xcpt_if ? 4'h3 : io_enq_uop_xcpt_pf_if ? 4'hC : {2'h0, io_enq_uop_xcpt_ae_if ? 2'h1 : 2'h2}};\n assign io_deq_uop_bypassable = |{&_cs_decoder_decoded_andMatrixOutputs_T_7, &_cs_decoder_decoded_andMatrixOutputs_T_8, &_cs_decoder_decoded_andMatrixOutputs_T_14, &_cs_decoder_decoded_andMatrixOutputs_T_17, &_cs_decoder_decoded_andMatrixOutputs_T_21, &_cs_decoder_decoded_andMatrixOutputs_T_48, &_cs_decoder_decoded_andMatrixOutputs_T_50, &_cs_decoder_decoded_andMatrixOutputs_T_66, &_cs_decoder_decoded_andMatrixOutputs_T_83, &_cs_decoder_decoded_andMatrixOutputs_T_84, &_cs_decoder_decoded_andMatrixOutputs_T_86};\n assign io_deq_uop_mem_cmd = cs_mem_cmd;\n assign io_deq_uop_mem_size = cs_mem_cmd == 5'h14 | cs_mem_cmd == 5'h5 ? {|(io_enq_uop_inst[24:20]), |_uop_lrs1_T} : io_enq_uop_inst[13:12];\n assign io_deq_uop_mem_signed = ~(io_enq_uop_inst[14]);\n assign io_deq_uop_is_fence = &_cs_decoder_decoded_andMatrixOutputs_T_6;\n assign io_deq_uop_is_fencei = &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], io_enq_uop_inst[3], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12]};\n assign io_deq_uop_is_amo = |{&_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_115};\n assign io_deq_uop_uses_ldq = |{&_cs_decoder_decoded_andMatrixOutputs_T_1, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_62, &_cs_decoder_decoded_andMatrixOutputs_T_118};\n assign io_deq_uop_uses_stq = |{&_cs_decoder_decoded_andMatrixOutputs_T_6, &_cs_decoder_decoded_andMatrixOutputs_T_13, &_cs_decoder_decoded_andMatrixOutputs_T_68, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_115};\n assign io_deq_uop_is_sys_pc2epc = &_cs_decoder_decoded_andMatrixOutputs_T_45;\n assign io_deq_uop_is_unique = |{&_cs_decoder_decoded_andMatrixOutputs_T_5, &_cs_decoder_decoded_andMatrixOutputs_T_45, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_121, &_cs_decoder_decoded_andMatrixOutputs_T_123, &_cs_decoder_decoded_andMatrixOutputs_T_125, &_cs_decoder_decoded_andMatrixOutputs_T_130, &_cs_decoder_decoded_andMatrixOutputs_T_157};\n assign io_deq_uop_flush_on_commit = (|{&_cs_decoder_decoded_andMatrixOutputs_T_5, &_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_70, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_115, &_cs_decoder_decoded_andMatrixOutputs_T_118, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_127, &_cs_decoder_decoded_andMatrixOutputs_T_156}) | csr_en & ~csr_ren & io_csr_decode_write_flush;\n assign io_deq_uop_ldst = {1'h0, io_enq_uop_inst[11:7]};\n assign io_deq_uop_lrs1 = {1'h0, _uop_lrs1_T};\n assign io_deq_uop_lrs2 = {1'h0, io_enq_uop_inst[24:20]};\n assign io_deq_uop_lrs3 = {1'h0, io_enq_uop_inst[31:27]};\n assign io_deq_uop_ldst_val = cs_dst_type != 2'h2 & ~(io_enq_uop_inst[11:7] == 5'h0 & cs_dst_type == 2'h0);\n assign io_deq_uop_dst_rtype = cs_dst_type;\n assign io_deq_uop_lrs1_rtype = {|{&_cs_decoder_decoded_andMatrixOutputs_T_5, &_cs_decoder_decoded_andMatrixOutputs_T_10, &_cs_decoder_decoded_andMatrixOutputs_T_43, &_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_92, &_cs_decoder_decoded_andMatrixOutputs_T_95, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_156}, |{&_cs_decoder_decoded_andMatrixOutputs_T_24, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_92, &_cs_decoder_decoded_andMatrixOutputs_T_95, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_164, &_cs_decoder_decoded_andMatrixOutputs_T_169}};\n assign io_deq_uop_lrs2_rtype =\n {|{&_cs_decoder_decoded_andMatrixOutputs_T, &_cs_decoder_decoded_andMatrixOutputs_T_2, &_cs_decoder_decoded_andMatrixOutputs_T_5, &_cs_decoder_decoded_andMatrixOutputs_T_8, &_cs_decoder_decoded_andMatrixOutputs_T_10, &_cs_decoder_decoded_andMatrixOutputs_T_42, &_cs_decoder_decoded_andMatrixOutputs_T_43, &_cs_decoder_decoded_andMatrixOutputs_T_44, &_cs_decoder_decoded_andMatrixOutputs_T_48, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]}, &_cs_decoder_decoded_andMatrixOutputs_T_58, &_cs_decoder_decoded_andMatrixOutputs_T_62, &_cs_decoder_decoded_andMatrixOutputs_T_66, &_cs_decoder_decoded_andMatrixOutputs_T_73, &_cs_decoder_decoded_andMatrixOutputs_T_83, &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], io_enq_uop_inst[3], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], cs_decoder_decoded_invInputs[4], io_enq_uop_inst[12], cs_decoder_decoded_invInputs[11], io_enq_uop_inst[14], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[29]}, &_cs_decoder_decoded_andMatrixOutputs_T_118, &_cs_decoder_decoded_andMatrixOutputs_T_122, &_cs_decoder_decoded_andMatrixOutputs_T_124, &_cs_decoder_decoded_andMatrixOutputs_T_149, &_cs_decoder_decoded_andMatrixOutputs_T_151, &_cs_decoder_decoded_andMatrixOutputs_T_153, &_cs_decoder_decoded_andMatrixOutputs_T_156, &_cs_decoder_decoded_andMatrixOutputs_T_161, &_cs_decoder_decoded_andMatrixOutputs_T_162},\n |{&_cs_decoder_decoded_andMatrixOutputs_T_24, &_cs_decoder_decoded_andMatrixOutputs_T_33, &_cs_decoder_decoded_andMatrixOutputs_T_69, &_cs_decoder_decoded_andMatrixOutputs_T_133, &_cs_decoder_decoded_andMatrixOutputs_T_134, &_cs_decoder_decoded_andMatrixOutputs_T_137}};\n assign io_deq_uop_frs3_en = &_cs_decoder_decoded_andMatrixOutputs_T_24;\n assign io_deq_uop_fp_val = |_cs_decoder_decoded_orMatrixOutputs_T_92;\n assign io_deq_uop_fp_single =\n |{&{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[27], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], io_enq_uop_inst[2], cs_decoder_decoded_invInputs[1], cs_decoder_decoded_invInputs[2], cs_decoder_decoded_invInputs[4], cs_decoder_decoded_invInputs[10], io_enq_uop_inst[13], cs_decoder_decoded_invInputs[12]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], cs_decoder_decoded_invInputs[28], cs_decoder_decoded_invInputs[29]},\n &_cs_decoder_decoded_andMatrixOutputs_T_149,\n &_cs_decoder_decoded_andMatrixOutputs_T_154,\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[27], io_enq_uop_inst[30], io_enq_uop_inst[31]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[10], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]},\n &{io_enq_uop_inst[0], io_enq_uop_inst[1], cs_decoder_decoded_invInputs[0], cs_decoder_decoded_invInputs[1], io_enq_uop_inst[4], cs_decoder_decoded_invInputs[3], io_enq_uop_inst[6], cs_decoder_decoded_invInputs[11], cs_decoder_decoded_invInputs[12], cs_decoder_decoded_invInputs[18], cs_decoder_decoded_invInputs[19], cs_decoder_decoded_invInputs[20], cs_decoder_decoded_invInputs[21], cs_decoder_decoded_invInputs[22], cs_decoder_decoded_invInputs[23], cs_decoder_decoded_invInputs[24], cs_decoder_decoded_invInputs[25], cs_decoder_decoded_invInputs[26], io_enq_uop_inst[29], io_enq_uop_inst[30], io_enq_uop_inst[31]}};\n assign io_deq_uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if;\n assign io_deq_uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if;\n assign io_deq_uop_bp_debug_if = io_enq_uop_bp_debug_if;\n assign io_deq_uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if;\n assign io_deq_uop_debug_fsrc = io_enq_uop_debug_fsrc;\n assign io_csr_decode_inst = io_enq_uop_inst;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us_2(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_0_ext hi_us_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLCFromBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_1(\n input [7:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [47:0] R0_data,\n input [7:0] W0_addr,\n input W0_clk,\n input [47:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_0_ext table_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module head_21x6(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [5:0] R0_data,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [5:0] W0_data,\n input [4:0] W1_addr,\n input W1_en,\n input W1_clk,\n input [5:0] W1_data\n);\n\n reg [5:0] Memory[0:20];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 6'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module IntToFP(\n input clock,\n input reset,\n input io_in_valid,\n input [1:0] io_in_bits_typeTagIn,\n input io_in_bits_wflags,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_typ,\n input [63:0] io_in_bits_in1,\n output io_out_valid,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc\n);\n\n wire [64:0] _i2fResults_i2f_1_io_out;\n wire [4:0] _i2fResults_i2f_1_io_exceptionFlags;\n wire [32:0] _i2fResults_i2f_io_out;\n wire [4:0] _i2fResults_i2f_io_exceptionFlags;\n reg in_pipe_v;\n reg [1:0] in_pipe_b_typeTagIn;\n reg in_pipe_b_wflags;\n reg [2:0] in_pipe_b_rm;\n reg [1:0] in_pipe_b_typ;\n reg [63:0] in_pipe_b_in1;\n wire [63:0] intValue_res = in_pipe_b_typ[1] ? in_pipe_b_in1 : {{32{~(in_pipe_b_typ[0]) & in_pipe_b_in1[31]}}, in_pipe_b_in1[31:0]};\n reg io_out_pipe_v;\n reg [64:0] io_out_pipe_b_data;\n reg [4:0] io_out_pipe_b_exc;\n wire [63:0] _mux_data_T_2 = (in_pipe_b_typeTagIn[0] ? 64'h0 : 64'hFFFFFFFF00000000) | in_pipe_b_in1;\n wire mux_data_rawIn_isZeroExpIn = _mux_data_T_2[62:52] == 11'h0;\n wire [5:0] mux_data_rawIn_normDist = _mux_data_T_2[51] ? 6'h0 : _mux_data_T_2[50] ? 6'h1 : _mux_data_T_2[49] ? 6'h2 : _mux_data_T_2[48] ? 6'h3 : _mux_data_T_2[47] ? 6'h4 : _mux_data_T_2[46] ? 6'h5 : _mux_data_T_2[45] ? 6'h6 : _mux_data_T_2[44] ? 6'h7 : _mux_data_T_2[43] ? 6'h8 : _mux_data_T_2[42] ? 6'h9 : _mux_data_T_2[41] ? 6'hA : _mux_data_T_2[40] ? 6'hB : _mux_data_T_2[39] ? 6'hC : _mux_data_T_2[38] ? 6'hD : _mux_data_T_2[37] ? 6'hE : _mux_data_T_2[36] ? 6'hF : _mux_data_T_2[35] ? 6'h10 : _mux_data_T_2[34] ? 6'h11 : _mux_data_T_2[33] ? 6'h12 : _mux_data_T_2[32] ? 6'h13 : _mux_data_T_2[31] ? 6'h14 : _mux_data_T_2[30] ? 6'h15 : _mux_data_T_2[29] ? 6'h16 : _mux_data_T_2[28] ? 6'h17 : _mux_data_T_2[27] ? 6'h18 : _mux_data_T_2[26] ? 6'h19 : _mux_data_T_2[25] ? 6'h1A : _mux_data_T_2[24] ? 6'h1B : _mux_data_T_2[23] ? 6'h1C : _mux_data_T_2[22] ? 6'h1D : _mux_data_T_2[21] ? 6'h1E : _mux_data_T_2[20] ? 6'h1F : _mux_data_T_2[19] ? 6'h20 : _mux_data_T_2[18] ? 6'h21 : _mux_data_T_2[17] ? 6'h22 : _mux_data_T_2[16] ? 6'h23 : _mux_data_T_2[15] ? 6'h24 : _mux_data_T_2[14] ? 6'h25 : _mux_data_T_2[13] ? 6'h26 : _mux_data_T_2[12] ? 6'h27 : _mux_data_T_2[11] ? 6'h28 : _mux_data_T_2[10] ? 6'h29 : _mux_data_T_2[9] ? 6'h2A : _mux_data_T_2[8] ? 6'h2B : _mux_data_T_2[7] ? 6'h2C : _mux_data_T_2[6] ? 6'h2D : _mux_data_T_2[5] ? 6'h2E : _mux_data_T_2[4] ? 6'h2F : _mux_data_T_2[3] ? 6'h30 : _mux_data_T_2[2] ? 6'h31 : {5'h19, ~(_mux_data_T_2[1])};\n wire [11:0] _mux_data_rawIn_adjustedExp_T_4 = (mux_data_rawIn_isZeroExpIn ? {6'h3F, ~mux_data_rawIn_normDist} : {1'h0, _mux_data_T_2[62:52]}) + {10'h100, mux_data_rawIn_isZeroExpIn ? 2'h2 : 2'h1};\n wire [114:0] _mux_data_rawIn_subnormFract_T = {63'h0, _mux_data_T_2[51:0]} << mux_data_rawIn_normDist;\n wire [51:0] _mux_data_rawIn_out_sig_T_2 = mux_data_rawIn_isZeroExpIn ? {_mux_data_rawIn_subnormFract_T[50:0], 1'h0} : _mux_data_T_2[51:0];\n wire [2:0] _mux_data_T_4 = mux_data_rawIn_isZeroExpIn & ~(|(_mux_data_T_2[51:0])) ? 3'h0 : _mux_data_rawIn_adjustedExp_T_4[11:9];\n wire _GEN = _mux_data_T_4[0] | (&(_mux_data_rawIn_adjustedExp_T_4[11:10])) & (|(_mux_data_T_2[51:0]));\n wire mux_data_rawIn_isZeroExpIn_1 = _mux_data_T_2[30:23] == 8'h0;\n wire [4:0] mux_data_rawIn_normDist_1 = _mux_data_T_2[22] ? 5'h0 : _mux_data_T_2[21] ? 5'h1 : _mux_data_T_2[20] ? 5'h2 : _mux_data_T_2[19] ? 5'h3 : _mux_data_T_2[18] ? 5'h4 : _mux_data_T_2[17] ? 5'h5 : _mux_data_T_2[16] ? 5'h6 : _mux_data_T_2[15] ? 5'h7 : _mux_data_T_2[14] ? 5'h8 : _mux_data_T_2[13] ? 5'h9 : _mux_data_T_2[12] ? 5'hA : _mux_data_T_2[11] ? 5'hB : _mux_data_T_2[10] ? 5'hC : _mux_data_T_2[9] ? 5'hD : _mux_data_T_2[8] ? 5'hE : _mux_data_T_2[7] ? 5'hF : _mux_data_T_2[6] ? 5'h10 : _mux_data_T_2[5] ? 5'h11 : _mux_data_T_2[4] ? 5'h12 : _mux_data_T_2[3] ? 5'h13 : _mux_data_T_2[2] ? 5'h14 : _mux_data_T_2[1] ? 5'h15 : 5'h16;\n wire [8:0] _mux_data_rawIn_adjustedExp_T_9 = (mux_data_rawIn_isZeroExpIn_1 ? {4'hF, ~mux_data_rawIn_normDist_1} : {1'h0, _mux_data_T_2[30:23]}) + {7'h20, mux_data_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1};\n wire [2:0] _mux_data_T_13 = mux_data_rawIn_isZeroExpIn_1 & ~(|(_mux_data_T_2[22:0])) ? 3'h0 : _mux_data_rawIn_adjustedExp_T_9[8:6];\n wire [64:0] i2fResults_1_1 = ({65{_i2fResults_i2f_1_io_out[63:61] != 3'h7}} | 65'h1EFEFFFFFFFFFFFFF) & _i2fResults_i2f_1_io_out;\n wire [53:0] _mux_data_rawIn_subnormFract_T_2 = {31'h0, _mux_data_T_2[22:0]} << mux_data_rawIn_normDist_1;\n always @(posedge clock) begin\n if (reset) begin\n in_pipe_v <= 1'h0;\n io_out_pipe_v <= 1'h0;\n end\n else begin\n in_pipe_v <= io_in_valid;\n io_out_pipe_v <= in_pipe_v;\n end\n if (io_in_valid) begin\n in_pipe_b_typeTagIn <= io_in_bits_typeTagIn;\n in_pipe_b_wflags <= io_in_bits_wflags;\n in_pipe_b_rm <= io_in_bits_rm;\n in_pipe_b_typ <= io_in_bits_typ;\n in_pipe_b_in1 <= io_in_bits_in1;\n end\n if (in_pipe_v) begin\n io_out_pipe_b_data <= in_pipe_b_wflags ? (in_pipe_b_typeTagIn[0] ? i2fResults_1_1 : {i2fResults_1_1[64:33], _i2fResults_i2f_io_out}) : {_mux_data_T_2[63], _mux_data_T_4[2:1], _GEN, (&{_mux_data_T_4[2:1], _GEN}) ? {&(_mux_data_rawIn_out_sig_T_2[51:32]), _mux_data_rawIn_adjustedExp_T_4[7:1], _mux_data_T_13[2], _mux_data_rawIn_out_sig_T_2[51:32], _mux_data_T_2[31], _mux_data_T_13[1], _mux_data_T_13[0] | (&(_mux_data_rawIn_adjustedExp_T_9[8:7])) & (|(_mux_data_T_2[22:0])), _mux_data_rawIn_adjustedExp_T_9[5:0], mux_data_rawIn_isZeroExpIn_1 ? {_mux_data_rawIn_subnormFract_T_2[21:0], 1'h0} : _mux_data_T_2[22:0]} : {_mux_data_rawIn_adjustedExp_T_4[8:0], _mux_data_rawIn_out_sig_T_2}};\n io_out_pipe_b_exc <= in_pipe_b_wflags ? (in_pipe_b_typeTagIn[0] ? _i2fResults_i2f_1_io_exceptionFlags : _i2fResults_i2f_io_exceptionFlags) : 5'h0;\n end\n end\n INToRecFN_i64_e8_s24 i2fResults_i2f (\n .io_signedIn (~(in_pipe_b_typ[0])),\n .io_in (intValue_res),\n .io_roundingMode (in_pipe_b_rm),\n .io_out (_i2fResults_i2f_io_out),\n .io_exceptionFlags (_i2fResults_i2f_io_exceptionFlags)\n );\n INToRecFN_i64_e11_s53 i2fResults_i2f_1 (\n .io_signedIn (~(in_pipe_b_typ[0])),\n .io_in (intValue_res),\n .io_roundingMode (in_pipe_b_rm),\n .io_out (_i2fResults_i2f_1_io_out),\n .io_exceptionFlags (_i2fResults_i2f_1_io_exceptionFlags)\n );\n assign io_out_valid = io_out_pipe_v;\n assign io_out_bits_data = io_out_pipe_b_data;\n assign io_out_bits_exc = io_out_pipe_b_exc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module rockettile_dcache_tag_array(\n input [5:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [175:0] RW0_wdata,\n output [175:0] RW0_rdata,\n input [7:0] RW0_wmask\n);\n\n rockettile_dcache_tag_array_ext rockettile_dcache_tag_array_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata),\n .RW0_wmask (RW0_wmask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53(\n input io_in_isZero,\n input io_in_sign,\n input [8:0] io_in_sExp,\n input [64:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [64:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire roundingMode_near_even = io_roundingMode == 3'h0;\n wire [1:0] _GEN = {io_in_sig[10], |(io_in_sig[9:0])};\n wire [54:0] roundedSig = (roundingMode_near_even | io_roundingMode == 3'h4) & io_in_sig[10] | (io_roundingMode == 3'h2 & io_in_sign | io_roundingMode == 3'h3 & ~io_in_sign) & (|_GEN) ? {1'h0, io_in_sig[64:11]} + 55'h1 & {54'h3FFFFFFFFFFFFF, ~(roundingMode_near_even & io_in_sig[10] & ~(|(io_in_sig[9:0])))} : {1'h0, io_in_sig[64:12], io_in_sig[11] | io_roundingMode == 3'h6 & (|_GEN)};\n assign io_out = {io_in_sign, {{3{io_in_sExp[8]}}, io_in_sExp} + {10'h0, roundedSig[54:53]} + 12'h780 & ~(io_in_isZero ? 12'hE00 : 12'h0), io_in_isZero ? 52'h0 : roundedSig[51:0]};\n assign io_exceptionFlags = {4'h0, ~io_in_isZero & (|_GEN)};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module table_3(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [51:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [51:0] W0_data,\n input [3:0] W0_mask\n);\n\n table_1_ext table_1_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.jtag for license details.\n\npackage freechips.rocketchip.jtag\n\nimport chisel3._\nimport chisel3.reflect.DataMirror\nimport chisel3.internal.firrtl.KnownWidth\nimport chisel3.util.{Cat, Valid}\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.util.property\n\n/** Base JTAG shifter IO, viewed from input to shift register chain.\n * Can be chained together.\n */\nclass ShifterIO extends Bundle {\n val shift = Bool() // advance the scan chain on clock high\n val data = Bool() // as input: bit to be captured into shifter MSB on next rising edge; as output: value of shifter LSB\n val capture = Bool() // high in the CaptureIR/DR state when this chain is selected\n val update = Bool() // high in the UpdateIR/DR state when this chain is selected\n\n /** Sets a output shifter IO's control signals from a input shifter IO's control signals.\n */\n def chainControlFrom(in: ShifterIO): Unit = {\n shift := in.shift\n capture := in.capture\n update := in.update\n }\n}\n\ntrait ChainIO extends Bundle {\n val chainIn = Input(new ShifterIO)\n val chainOut = Output(new ShifterIO)\n}\n\nclass Capture[+T <: Data](gen: T) extends Bundle {\n val bits = Input(gen) // data to capture, should be always valid\n val capture = Output(Bool()) // will be high in capture state (single cycle), captured on following rising edge\n}\n\nobject Capture {\n def apply[T <: Data](gen: T): Capture[T] = new Capture(gen)\n}\n\n/** Trait that all JTAG chains (data and instruction registers) must extend, providing basic chain\n * IO.\n */\ntrait Chain extends Module {\n val io: ChainIO\n}\n\n/** One-element shift register, data register for bypass mode.\n *\n * Implements Clause 10.\n */\nclass JtagBypassChain(implicit val p: Parameters) extends Chain {\n class ModIO extends ChainIO\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val reg = Reg(Bool()) // 10.1.1a single shift register stage\n\n io.chainOut.data := reg\n\n property.cover(io.chainIn.capture, \"bypass_chain_capture\", \"JTAG; bypass_chain_capture; This Bypass Chain captured data\")\n\n when (io.chainIn.capture) {\n reg := false.B // 10.1.1b capture logic 0 on TCK rising\n } .elsewhen (io.chainIn.shift) {\n reg := io.chainIn.data\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject JtagBypassChain {\n def apply()(implicit p: Parameters) = new JtagBypassChain\n}\n\n/** Simple shift register with parallel capture only, for read-only data registers.\n *\n * Number of stages is the number of bits in gen, which must have a known width.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureChain[+T <: Data](gen: T)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureChain_${gen.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(gen)\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val n = DataMirror.widthOf(gen) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $gen\"); -1 // TODO: remove -1 type hack\n }\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG; chain_capture; This Chain captured data\")\n \n when (io.chainIn.capture) {\n (0 until n) map (x => regs(x) := io.capture.bits.asUInt(x))\n io.capture.capture := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n } .otherwise {\n io.capture.capture := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureChain {\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureChain(gen)\n}\n\n/** Simple shift register with parallel capture and update. Useful for general instruction and data\n * scan registers.\n *\n * Number of stages is the max number of bits in genCapture and genUpdate, both of which must have\n * known widths. If there is a width mismatch, the unused most significant bits will be zero.\n *\n * Useful notes:\n * 7.2.1c shifter shifts on TCK rising edge\n * 4.3.2a TDI captured on TCK rising edge, 6.1.2.1b assumed changes on TCK falling edge\n */\nclass CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V)(implicit val p: Parameters) extends Chain {\n override def desiredName = s\"CaptureUpdateChain_${genCapture.typeName}_To_${genUpdate.typeName}\"\n class ModIO extends ChainIO {\n val capture = Capture(genCapture)\n val update = Valid(genUpdate) // valid high when in update state (single cycle), contents may change any time after\n }\n val io = IO(new ModIO)\n io.chainOut chainControlFrom io.chainIn\n\n val captureWidth = DataMirror.widthOf(genCapture) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genCapture\"); -1 // TODO: remove -1 type hack\n }\n val updateWidth = DataMirror.widthOf(genUpdate) match {\n case KnownWidth(x) => x\n case _ => require(false, s\"can't generate chain for unknown width data type $genUpdate\"); -1 // TODO: remove -1 type hack\n }\n val n = math.max(captureWidth, updateWidth)\n\n val regs = (0 until n) map (x => Reg(Bool()))\n\n io.chainOut.data := regs(0)\n\n val updateBits = Cat(regs.reverse)(updateWidth-1, 0)\n io.update.bits := updateBits.asTypeOf(io.update.bits)\n\n val captureBits = io.capture.bits.asUInt\n\n property.cover(io.chainIn.capture, \"chain_capture\", \"JTAG;chain_capture; This Chain captured data\")\n property.cover(io.chainIn.capture, \"chain_update\", \"JTAG;chain_update; This Chain updated data\")\n\n when (io.chainIn.capture) {\n (0 until math.min(n, captureWidth)) map (x => regs(x) := captureBits(x))\n (captureWidth until n) map (x => regs(x) := 0.U)\n io.capture.capture := true.B\n io.update.valid := false.B\n } .elsewhen (io.chainIn.update) {\n io.capture.capture := false.B\n io.update.valid := true.B\n } .elsewhen (io.chainIn.shift) {\n regs(n-1) := io.chainIn.data\n (0 until n-1) map (x => regs(x) := regs(x+1))\n io.capture.capture := false.B\n io.update.valid := false.B\n } .otherwise {\n io.capture.capture := false.B\n io.update.valid := false.B\n }\n assert(!(io.chainIn.capture && io.chainIn.update)\n && !(io.chainIn.capture && io.chainIn.shift)\n && !(io.chainIn.update && io.chainIn.shift))\n}\n\nobject CaptureUpdateChain {\n /** Capture-update chain with matching capture and update types.\n */\n def apply[T <: Data](gen: T)(implicit p: Parameters) = new CaptureUpdateChain(gen, gen)\n def apply[T <: Data, V <: Data](genCapture: T, genUpdate: V)(implicit p: Parameters) =\n new CaptureUpdateChain(genCapture, genUpdate)\n}", + "response": "module CaptureUpdateChain_UInt5_To_UInt5(\n input clock,\n input reset,\n input io_chainIn_shift,\n input io_chainIn_data,\n input io_chainIn_capture,\n input io_chainIn_update,\n output io_chainOut_data,\n output [4:0] io_update_bits\n);\n\n reg regs_0;\n reg regs_1;\n reg regs_2;\n reg regs_3;\n reg regs_4;\n always @(posedge clock) begin\n if (io_chainIn_capture) begin\n regs_0 <= 1'h1;\n regs_1 <= 1'h0;\n regs_2 <= 1'h0;\n regs_3 <= 1'h0;\n regs_4 <= 1'h0;\n end\n else if (io_chainIn_update | ~io_chainIn_shift) begin\n end\n else begin\n regs_0 <= regs_1;\n regs_1 <= regs_2;\n regs_2 <= regs_3;\n regs_3 <= regs_4;\n regs_4 <= io_chainIn_data;\n end\n end\n assign io_chainOut_data = regs_0;\n assign io_update_bits = {regs_4, regs_3, regs_2, regs_1, regs_0};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3.{Data, SyncReadMem, Vec}\nimport chisel3.util.log2Ceil\n\nobject DescribedSRAM {\n def apply[T <: Data](\n name: String,\n desc: String,\n size: BigInt, // depth\n data: T\n ): SyncReadMem[T] = {\n\n val mem = SyncReadMem(size, data)\n\n mem.suggestName(name)\n\n val granWidth = data match {\n case v: Vec[_] => v.head.getWidth\n case d => d.getWidth\n }\n\n val uid = 0\n\n Annotated.srams(\n component = mem,\n name = name,\n address_width = log2Ceil(size),\n data_width = data.getWidth,\n depth = size,\n description = desc,\n write_mask_granularity = granWidth\n )\n\n mem\n }\n}", + "response": "module cc_banks_3(\n input [13:0] RW0_addr,\n input RW0_en,\n input RW0_clk,\n input RW0_wmode,\n input [31:0] RW0_wdata,\n output [31:0] RW0_rdata\n);\n\n cc_banks_0_ext cc_banks_0_ext (\n .RW0_addr (RW0_addr),\n .RW0_en (RW0_en),\n .RW0_clk (RW0_clk),\n .RW0_wmode (RW0_wmode),\n .RW0_wdata (RW0_wdata),\n .RW0_rdata (RW0_rdata)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw67_f32(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [64:0] io_out_bits_payload,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_payload = {io_in_bits_flit[2:0], data_1, data_0[31:2]};\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Issue Slot Logic\n//--------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Note: stores (and AMOs) are \"broken down\" into 2 uops, but stored within a single issue-slot.\n// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.\n// TODO Disable ldspec for FP queue.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\nimport FUConstants._\n\n/**\n * IO bundle to interact with Issue slot\n *\n * @param numWakeupPorts number of wakeup ports for the slot\n */\nclass IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle\n{\n val valid = Output(Bool())\n val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?\n val request = Output(Bool())\n val request_hp = Output(Bool())\n val grant = Input(Bool())\n\n val brupdate = Input(new BrUpdateInfo())\n val kill = Input(Bool()) // pipeline flush\n val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)\n val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.\n\n val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))\n val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))\n val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))\n val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!\n val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.\n val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.\n\n val debug = {\n val result = new Bundle {\n val p1 = Bool()\n val p2 = Bool()\n val p3 = Bool()\n val ppred = Bool()\n val state = UInt(width=2.W)\n }\n Output(result)\n }\n}\n\n/**\n * Single issue slot. Holds a uop within the issue queue\n *\n * @param numWakeupPorts number of wakeup ports\n */\nclass IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)\n extends BoomModule\n with IssueUnitConstants\n{\n val io = IO(new IssueSlotIO(numWakeupPorts))\n\n // slot invalid?\n // slot is valid, holding 1 uop\n // slot is valid, holds 2 uops (like a store)\n def is_invalid = state === s_invalid\n def is_valid = state =/= s_invalid\n\n val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)\n val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)\n val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n\n val state = RegInit(s_invalid)\n val p1 = RegInit(false.B)\n val p2 = RegInit(false.B)\n val p3 = RegInit(false.B)\n val ppred = RegInit(false.B)\n\n // Poison if woken up by speculative load.\n // Poison lasts 1 cycle (as ldMiss will come on the next cycle).\n // SO if poisoned is true, set it to false!\n val p1_poisoned = RegInit(false.B)\n val p2_poisoned = RegInit(false.B)\n p1_poisoned := false.B\n p2_poisoned := false.B\n val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)\n val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)\n\n val slot_uop = RegInit(NullMicroOp)\n val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)\n\n //-----------------------------------------------------------------------------\n // next slot state computation\n // compute the next state for THIS entry slot (in a collasping queue, the\n // current uop may get moved elsewhere, and a new uop can enter\n\n when (io.kill) {\n state := s_invalid\n } .elsewhen (io.in_uop.valid) {\n state := io.in_uop.bits.iw_state\n } .elsewhen (io.clear) {\n state := s_invalid\n } .otherwise {\n state := next_state\n }\n\n //-----------------------------------------------------------------------------\n // \"update\" state\n // compute the next state for the micro-op in this slot. This micro-op may\n // be moved elsewhere, so the \"next_state\" travels with it.\n\n // defaults\n next_state := state\n next_uopc := slot_uop.uopc\n next_lrs1_rtype := slot_uop.lrs1_rtype\n next_lrs2_rtype := slot_uop.lrs2_rtype\n\n when (io.kill) {\n next_state := s_invalid\n } .elsewhen ((io.grant && (state === s_valid_1)) ||\n (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {\n // try to issue this uop.\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_invalid\n }\n } .elsewhen (io.grant && (state === s_valid_2)) {\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_valid_1\n when (p1) {\n slot_uop.uopc := uopSTD\n next_uopc := uopSTD\n slot_uop.lrs1_rtype := RT_X\n next_lrs1_rtype := RT_X\n } .otherwise {\n slot_uop.lrs2_rtype := RT_X\n next_lrs2_rtype := RT_X\n }\n }\n }\n\n when (io.in_uop.valid) {\n slot_uop := io.in_uop.bits\n assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n }\n\n // Wakeup Compare Logic\n\n // these signals are the \"next_p*\" for the current slot's micro-op.\n // they are important for shifting the current slot_uop up to an other entry.\n val next_p1 = WireInit(p1)\n val next_p2 = WireInit(p2)\n val next_p3 = WireInit(p3)\n val next_ppred = WireInit(ppred)\n\n when (io.in_uop.valid) {\n p1 := !(io.in_uop.bits.prs1_busy)\n p2 := !(io.in_uop.bits.prs2_busy)\n p3 := !(io.in_uop.bits.prs3_busy)\n ppred := !(io.in_uop.bits.ppred_busy)\n }\n\n when (io.ldspec_miss && next_p1_poisoned) {\n assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n p1 := false.B\n }\n when (io.ldspec_miss && next_p2_poisoned) {\n assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n p2 := false.B\n }\n\n for (i <- 0 until numWakeupPorts) {\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {\n p1 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {\n p2 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {\n p3 := true.B\n }\n }\n when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {\n ppred := true.B\n }\n\n for (w <- 0 until memWidth) {\n assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n \"Loads to x0 should never speculatively wakeup other instructions\")\n }\n\n // TODO disable if FP IQ.\n for (w <- 0 until memWidth) {\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs1 &&\n next_uop.lrs1_rtype === RT_FIX) {\n p1 := true.B\n p1_poisoned := true.B\n assert (!next_p1_poisoned)\n }\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs2 &&\n next_uop.lrs2_rtype === RT_FIX) {\n p2 := true.B\n p2_poisoned := true.B\n assert (!next_p2_poisoned)\n }\n }\n\n\n // Handle branch misspeculations\n val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)\n\n // was this micro-op killed by a branch? if yes, we can't let it be valid if\n // we compact it into an other entry\n when (IsKilledByBranch(io.brupdate, slot_uop)) {\n next_state := s_invalid\n }\n\n when (!io.in_uop.valid) {\n slot_uop.br_mask := next_br_mask\n }\n\n //-------------------------------------------------------------\n // Request Logic\n io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill\n val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr\n io.request_hp := io.request && high_priority\n\n when (state === s_valid_1) {\n io.request := p1 && p2 && p3 && ppred && !io.kill\n } .elsewhen (state === s_valid_2) {\n io.request := (p1 || p2) && ppred && !io.kill\n } .otherwise {\n io.request := false.B\n }\n\n //assign outputs\n io.valid := is_valid\n io.uop := slot_uop\n io.uop.iw_p1_poisoned := p1_poisoned\n io.uop.iw_p2_poisoned := p2_poisoned\n\n // micro-op will vacate due to grant.\n val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)\n val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)\n io.will_be_valid := is_valid && !(may_vacate && !squash_grant)\n\n io.out_uop := slot_uop\n io.out_uop.iw_state := next_state\n io.out_uop.uopc := next_uopc\n io.out_uop.lrs1_rtype := next_lrs1_rtype\n io.out_uop.lrs2_rtype := next_lrs2_rtype\n io.out_uop.br_mask := next_br_mask\n io.out_uop.prs1_busy := !p1\n io.out_uop.prs2_busy := !p2\n io.out_uop.prs3_busy := !p3\n io.out_uop.ppred_busy := !ppred\n io.out_uop.iw_p1_poisoned := p1_poisoned\n io.out_uop.iw_p2_poisoned := p2_poisoned\n\n when (state === s_valid_2) {\n when (p1 && p2 && ppred) {\n ; // send out the entire instruction as one uop\n } .elsewhen (p1 && ppred) {\n io.uop.uopc := slot_uop.uopc\n io.uop.lrs2_rtype := RT_X\n } .elsewhen (p2 && ppred) {\n io.uop.uopc := uopSTD\n io.uop.lrs1_rtype := RT_X\n }\n }\n\n // debug outputs\n io.debug.p1 := p1\n io.debug.p2 := p2\n io.debug.p3 := p3\n io.debug.ppred := ppred\n io.debug.state := state\n}", + "response": "module IssueSlot_8(\n input clock,\n input reset,\n output io_valid,\n output io_will_be_valid,\n output io_request,\n input io_grant,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_kill,\n input io_clear,\n input io_ldspec_miss,\n input io_wakeup_ports_0_valid,\n input [5:0] io_wakeup_ports_0_bits_pdst,\n input io_wakeup_ports_1_valid,\n input [5:0] io_wakeup_ports_1_bits_pdst,\n input io_wakeup_ports_2_valid,\n input [5:0] io_wakeup_ports_2_bits_pdst,\n input io_spec_ld_wakeup_0_valid,\n input [5:0] io_spec_ld_wakeup_0_bits,\n input io_in_uop_valid,\n input [6:0] io_in_uop_bits_uopc,\n input [31:0] io_in_uop_bits_inst,\n input [31:0] io_in_uop_bits_debug_inst,\n input io_in_uop_bits_is_rvc,\n input [39:0] io_in_uop_bits_debug_pc,\n input [2:0] io_in_uop_bits_iq_type,\n input [9:0] io_in_uop_bits_fu_code,\n input [1:0] io_in_uop_bits_iw_state,\n input io_in_uop_bits_iw_p1_poisoned,\n input io_in_uop_bits_iw_p2_poisoned,\n input io_in_uop_bits_is_br,\n input io_in_uop_bits_is_jalr,\n input io_in_uop_bits_is_jal,\n input io_in_uop_bits_is_sfb,\n input [7:0] io_in_uop_bits_br_mask,\n input [2:0] io_in_uop_bits_br_tag,\n input [3:0] io_in_uop_bits_ftq_idx,\n input io_in_uop_bits_edge_inst,\n input [5:0] io_in_uop_bits_pc_lob,\n input io_in_uop_bits_taken,\n input [19:0] io_in_uop_bits_imm_packed,\n input [11:0] io_in_uop_bits_csr_addr,\n input [4:0] io_in_uop_bits_rob_idx,\n input [2:0] io_in_uop_bits_ldq_idx,\n input [2:0] io_in_uop_bits_stq_idx,\n input [1:0] io_in_uop_bits_rxq_idx,\n input [5:0] io_in_uop_bits_pdst,\n input [5:0] io_in_uop_bits_prs1,\n input [5:0] io_in_uop_bits_prs2,\n input [5:0] io_in_uop_bits_prs3,\n input [3:0] io_in_uop_bits_ppred,\n input io_in_uop_bits_prs1_busy,\n input io_in_uop_bits_prs2_busy,\n input io_in_uop_bits_prs3_busy,\n input io_in_uop_bits_ppred_busy,\n input [5:0] io_in_uop_bits_stale_pdst,\n input io_in_uop_bits_exception,\n input [63:0] io_in_uop_bits_exc_cause,\n input io_in_uop_bits_bypassable,\n input [4:0] io_in_uop_bits_mem_cmd,\n input [1:0] io_in_uop_bits_mem_size,\n input io_in_uop_bits_mem_signed,\n input io_in_uop_bits_is_fence,\n input io_in_uop_bits_is_fencei,\n input io_in_uop_bits_is_amo,\n input io_in_uop_bits_uses_ldq,\n input io_in_uop_bits_uses_stq,\n input io_in_uop_bits_is_sys_pc2epc,\n input io_in_uop_bits_is_unique,\n input io_in_uop_bits_flush_on_commit,\n input io_in_uop_bits_ldst_is_rs1,\n input [5:0] io_in_uop_bits_ldst,\n input [5:0] io_in_uop_bits_lrs1,\n input [5:0] io_in_uop_bits_lrs2,\n input [5:0] io_in_uop_bits_lrs3,\n input io_in_uop_bits_ldst_val,\n input [1:0] io_in_uop_bits_dst_rtype,\n input [1:0] io_in_uop_bits_lrs1_rtype,\n input [1:0] io_in_uop_bits_lrs2_rtype,\n input io_in_uop_bits_frs3_en,\n input io_in_uop_bits_fp_val,\n input io_in_uop_bits_fp_single,\n input io_in_uop_bits_xcpt_pf_if,\n input io_in_uop_bits_xcpt_ae_if,\n input io_in_uop_bits_xcpt_ma_if,\n input io_in_uop_bits_bp_debug_if,\n input io_in_uop_bits_bp_xcpt_if,\n input [1:0] io_in_uop_bits_debug_fsrc,\n input [1:0] io_in_uop_bits_debug_tsrc,\n output [6:0] io_out_uop_uopc,\n output [31:0] io_out_uop_inst,\n output [31:0] io_out_uop_debug_inst,\n output io_out_uop_is_rvc,\n output [39:0] io_out_uop_debug_pc,\n output [2:0] io_out_uop_iq_type,\n output [9:0] io_out_uop_fu_code,\n output [1:0] io_out_uop_iw_state,\n output io_out_uop_iw_p1_poisoned,\n output io_out_uop_iw_p2_poisoned,\n output io_out_uop_is_br,\n output io_out_uop_is_jalr,\n output io_out_uop_is_jal,\n output io_out_uop_is_sfb,\n output [7:0] io_out_uop_br_mask,\n output [2:0] io_out_uop_br_tag,\n output [3:0] io_out_uop_ftq_idx,\n output io_out_uop_edge_inst,\n output [5:0] io_out_uop_pc_lob,\n output io_out_uop_taken,\n output [19:0] io_out_uop_imm_packed,\n output [11:0] io_out_uop_csr_addr,\n output [4:0] io_out_uop_rob_idx,\n output [2:0] io_out_uop_ldq_idx,\n output [2:0] io_out_uop_stq_idx,\n output [1:0] io_out_uop_rxq_idx,\n output [5:0] io_out_uop_pdst,\n output [5:0] io_out_uop_prs1,\n output [5:0] io_out_uop_prs2,\n output [5:0] io_out_uop_prs3,\n output [3:0] io_out_uop_ppred,\n output io_out_uop_prs1_busy,\n output io_out_uop_prs2_busy,\n output io_out_uop_prs3_busy,\n output io_out_uop_ppred_busy,\n output [5:0] io_out_uop_stale_pdst,\n output io_out_uop_exception,\n output [63:0] io_out_uop_exc_cause,\n output io_out_uop_bypassable,\n output [4:0] io_out_uop_mem_cmd,\n output [1:0] io_out_uop_mem_size,\n output io_out_uop_mem_signed,\n output io_out_uop_is_fence,\n output io_out_uop_is_fencei,\n output io_out_uop_is_amo,\n output io_out_uop_uses_ldq,\n output io_out_uop_uses_stq,\n output io_out_uop_is_sys_pc2epc,\n output io_out_uop_is_unique,\n output io_out_uop_flush_on_commit,\n output io_out_uop_ldst_is_rs1,\n output [5:0] io_out_uop_ldst,\n output [5:0] io_out_uop_lrs1,\n output [5:0] io_out_uop_lrs2,\n output [5:0] io_out_uop_lrs3,\n output io_out_uop_ldst_val,\n output [1:0] io_out_uop_dst_rtype,\n output [1:0] io_out_uop_lrs1_rtype,\n output [1:0] io_out_uop_lrs2_rtype,\n output io_out_uop_frs3_en,\n output io_out_uop_fp_val,\n output io_out_uop_fp_single,\n output io_out_uop_xcpt_pf_if,\n output io_out_uop_xcpt_ae_if,\n output io_out_uop_xcpt_ma_if,\n output io_out_uop_bp_debug_if,\n output io_out_uop_bp_xcpt_if,\n output [1:0] io_out_uop_debug_fsrc,\n output [1:0] io_out_uop_debug_tsrc,\n output [6:0] io_uop_uopc,\n output [31:0] io_uop_inst,\n output [31:0] io_uop_debug_inst,\n output io_uop_is_rvc,\n output [39:0] io_uop_debug_pc,\n output [2:0] io_uop_iq_type,\n output [9:0] io_uop_fu_code,\n output [1:0] io_uop_iw_state,\n output io_uop_iw_p1_poisoned,\n output io_uop_iw_p2_poisoned,\n output io_uop_is_br,\n output io_uop_is_jalr,\n output io_uop_is_jal,\n output io_uop_is_sfb,\n output [7:0] io_uop_br_mask,\n output [2:0] io_uop_br_tag,\n output [3:0] io_uop_ftq_idx,\n output io_uop_edge_inst,\n output [5:0] io_uop_pc_lob,\n output io_uop_taken,\n output [19:0] io_uop_imm_packed,\n output [11:0] io_uop_csr_addr,\n output [4:0] io_uop_rob_idx,\n output [2:0] io_uop_ldq_idx,\n output [2:0] io_uop_stq_idx,\n output [1:0] io_uop_rxq_idx,\n output [5:0] io_uop_pdst,\n output [5:0] io_uop_prs1,\n output [5:0] io_uop_prs2,\n output [5:0] io_uop_prs3,\n output [3:0] io_uop_ppred,\n output io_uop_prs1_busy,\n output io_uop_prs2_busy,\n output io_uop_prs3_busy,\n output io_uop_ppred_busy,\n output [5:0] io_uop_stale_pdst,\n output io_uop_exception,\n output [63:0] io_uop_exc_cause,\n output io_uop_bypassable,\n output [4:0] io_uop_mem_cmd,\n output [1:0] io_uop_mem_size,\n output io_uop_mem_signed,\n output io_uop_is_fence,\n output io_uop_is_fencei,\n output io_uop_is_amo,\n output io_uop_uses_ldq,\n output io_uop_uses_stq,\n output io_uop_is_sys_pc2epc,\n output io_uop_is_unique,\n output io_uop_flush_on_commit,\n output io_uop_ldst_is_rs1,\n output [5:0] io_uop_ldst,\n output [5:0] io_uop_lrs1,\n output [5:0] io_uop_lrs2,\n output [5:0] io_uop_lrs3,\n output io_uop_ldst_val,\n output [1:0] io_uop_dst_rtype,\n output [1:0] io_uop_lrs1_rtype,\n output [1:0] io_uop_lrs2_rtype,\n output io_uop_frs3_en,\n output io_uop_fp_val,\n output io_uop_fp_single,\n output io_uop_xcpt_pf_if,\n output io_uop_xcpt_ae_if,\n output io_uop_xcpt_ma_if,\n output io_uop_bp_debug_if,\n output io_uop_bp_xcpt_if,\n output [1:0] io_uop_debug_fsrc,\n output [1:0] io_uop_debug_tsrc\n);\n\n reg [1:0] state;\n reg p1;\n reg p2;\n reg p3;\n reg ppred;\n reg p1_poisoned;\n reg p2_poisoned;\n wire next_p1_poisoned = io_in_uop_valid ? io_in_uop_bits_iw_p1_poisoned : p1_poisoned;\n wire next_p2_poisoned = io_in_uop_valid ? io_in_uop_bits_iw_p2_poisoned : p2_poisoned;\n reg [6:0] slot_uop_uopc;\n reg [31:0] slot_uop_inst;\n reg [31:0] slot_uop_debug_inst;\n reg slot_uop_is_rvc;\n reg [39:0] slot_uop_debug_pc;\n reg [2:0] slot_uop_iq_type;\n reg [9:0] slot_uop_fu_code;\n reg [1:0] slot_uop_iw_state;\n reg slot_uop_is_br;\n reg slot_uop_is_jalr;\n reg slot_uop_is_jal;\n reg slot_uop_is_sfb;\n reg [7:0] slot_uop_br_mask;\n reg [2:0] slot_uop_br_tag;\n reg [3:0] slot_uop_ftq_idx;\n reg slot_uop_edge_inst;\n reg [5:0] slot_uop_pc_lob;\n reg slot_uop_taken;\n reg [19:0] slot_uop_imm_packed;\n reg [11:0] slot_uop_csr_addr;\n reg [4:0] slot_uop_rob_idx;\n reg [2:0] slot_uop_ldq_idx;\n reg [2:0] slot_uop_stq_idx;\n reg [1:0] slot_uop_rxq_idx;\n reg [5:0] slot_uop_pdst;\n reg [5:0] slot_uop_prs1;\n reg [5:0] slot_uop_prs2;\n reg [5:0] slot_uop_prs3;\n reg [3:0] slot_uop_ppred;\n reg slot_uop_prs1_busy;\n reg slot_uop_prs2_busy;\n reg slot_uop_prs3_busy;\n reg slot_uop_ppred_busy;\n reg [5:0] slot_uop_stale_pdst;\n reg slot_uop_exception;\n reg [63:0] slot_uop_exc_cause;\n reg slot_uop_bypassable;\n reg [4:0] slot_uop_mem_cmd;\n reg [1:0] slot_uop_mem_size;\n reg slot_uop_mem_signed;\n reg slot_uop_is_fence;\n reg slot_uop_is_fencei;\n reg slot_uop_is_amo;\n reg slot_uop_uses_ldq;\n reg slot_uop_uses_stq;\n reg slot_uop_is_sys_pc2epc;\n reg slot_uop_is_unique;\n reg slot_uop_flush_on_commit;\n reg slot_uop_ldst_is_rs1;\n reg [5:0] slot_uop_ldst;\n reg [5:0] slot_uop_lrs1;\n reg [5:0] slot_uop_lrs2;\n reg [5:0] slot_uop_lrs3;\n reg slot_uop_ldst_val;\n reg [1:0] slot_uop_dst_rtype;\n reg [1:0] slot_uop_lrs1_rtype;\n reg [1:0] slot_uop_lrs2_rtype;\n reg slot_uop_frs3_en;\n reg slot_uop_fp_val;\n reg slot_uop_fp_single;\n reg slot_uop_xcpt_pf_if;\n reg slot_uop_xcpt_ae_if;\n reg slot_uop_xcpt_ma_if;\n reg slot_uop_bp_debug_if;\n reg slot_uop_bp_xcpt_if;\n reg [1:0] slot_uop_debug_fsrc;\n reg [1:0] slot_uop_debug_tsrc;\n wire [5:0] next_uop_prs1 = io_in_uop_valid ? io_in_uop_bits_prs1 : slot_uop_prs1;\n wire [5:0] next_uop_prs2 = io_in_uop_valid ? io_in_uop_bits_prs2 : slot_uop_prs2;\n wire _GEN = state == 2'h2;\n wire _GEN_0 = io_grant & _GEN;\n wire _GEN_1 = io_grant & state == 2'h1 | _GEN_0 & p1 & p2 & ppred;\n wire _GEN_2 = io_ldspec_miss & (p1_poisoned | p2_poisoned);\n wire _GEN_3 = _GEN_0 & ~_GEN_2;\n wire _GEN_4 = io_kill | _GEN_1;\n wire _GEN_5 = _GEN_4 | ~(_GEN_0 & ~_GEN_2 & p1);\n wire _GEN_6 = _GEN_4 | ~_GEN_3 | p1;\n wire _GEN_7 = io_ldspec_miss & next_p1_poisoned;\n wire _GEN_8 = io_ldspec_miss & next_p2_poisoned;\n wire _GEN_9 = io_spec_ld_wakeup_0_valid & io_spec_ld_wakeup_0_bits == next_uop_prs1 & (io_in_uop_valid ? io_in_uop_bits_lrs1_rtype : slot_uop_lrs1_rtype) == 2'h0;\n wire _GEN_10 = io_spec_ld_wakeup_0_valid & io_spec_ld_wakeup_0_bits == next_uop_prs2 & (io_in_uop_valid ? io_in_uop_bits_lrs2_rtype : slot_uop_lrs2_rtype) == 2'h0;\n wire [7:0] next_br_mask = slot_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n wire _GEN_11 = (|(io_brupdate_b1_mispredict_mask & slot_uop_br_mask)) | io_kill;\n wire _may_vacate_T = state == 2'h1;\n wire _may_vacate_T_1 = state == 2'h2;\n wire _GEN_12 = p1 & p2 & ppred;\n wire _GEN_13 = p1 & ppred;\n wire _GEN_14 = ~_may_vacate_T_1 | _GEN_12 | _GEN_13 | ~(p2 & ppred);\n wire [5:0] next_uop_prs3 = io_in_uop_valid ? io_in_uop_bits_prs3 : slot_uop_prs3;\n always @(posedge clock) begin\n if (reset) begin\n state <= 2'h0;\n p1 <= 1'h0;\n p2 <= 1'h0;\n p3 <= 1'h0;\n ppred <= 1'h0;\n p1_poisoned <= 1'h0;\n p2_poisoned <= 1'h0;\n slot_uop_uopc <= 7'h0;\n slot_uop_pdst <= 6'h0;\n slot_uop_bypassable <= 1'h0;\n slot_uop_uses_ldq <= 1'h0;\n slot_uop_uses_stq <= 1'h0;\n slot_uop_dst_rtype <= 2'h2;\n slot_uop_fp_val <= 1'h0;\n end\n else begin\n if (io_kill)\n state <= 2'h0;\n else if (io_in_uop_valid)\n state <= io_in_uop_bits_iw_state;\n else if (io_clear | _GEN_11)\n state <= 2'h0;\n else if (_GEN_1) begin\n if (~_GEN_2)\n state <= 2'h0;\n end\n else if (_GEN_3)\n state <= 2'h1;\n p1 <= _GEN_9 | io_wakeup_ports_2_valid & io_wakeup_ports_2_bits_pdst == next_uop_prs1 | io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs1 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs1 | ~_GEN_7 & (io_in_uop_valid ? ~io_in_uop_bits_prs1_busy : p1);\n p2 <= _GEN_10 | io_wakeup_ports_2_valid & io_wakeup_ports_2_bits_pdst == next_uop_prs2 | io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs2 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs2 | ~_GEN_8 & (io_in_uop_valid ? ~io_in_uop_bits_prs2_busy : p2);\n p3 <= io_wakeup_ports_2_valid & io_wakeup_ports_2_bits_pdst == next_uop_prs3 | io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs3 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs3 | (io_in_uop_valid ? ~io_in_uop_bits_prs3_busy : p3);\n if (io_in_uop_valid) begin\n ppred <= ~io_in_uop_bits_ppred_busy;\n slot_uop_uopc <= io_in_uop_bits_uopc;\n slot_uop_pdst <= io_in_uop_bits_pdst;\n slot_uop_bypassable <= io_in_uop_bits_bypassable;\n slot_uop_uses_ldq <= io_in_uop_bits_uses_ldq;\n slot_uop_uses_stq <= io_in_uop_bits_uses_stq;\n slot_uop_dst_rtype <= io_in_uop_bits_dst_rtype;\n slot_uop_fp_val <= io_in_uop_bits_fp_val;\n end\n else if (_GEN_5) begin\n end\n else\n slot_uop_uopc <= 7'h3;\n p1_poisoned <= _GEN_9;\n p2_poisoned <= _GEN_10;\n end\n if (io_in_uop_valid) begin\n slot_uop_inst <= io_in_uop_bits_inst;\n slot_uop_debug_inst <= io_in_uop_bits_debug_inst;\n slot_uop_is_rvc <= io_in_uop_bits_is_rvc;\n slot_uop_debug_pc <= io_in_uop_bits_debug_pc;\n slot_uop_iq_type <= io_in_uop_bits_iq_type;\n slot_uop_fu_code <= io_in_uop_bits_fu_code;\n slot_uop_iw_state <= io_in_uop_bits_iw_state;\n slot_uop_is_br <= io_in_uop_bits_is_br;\n slot_uop_is_jalr <= io_in_uop_bits_is_jalr;\n slot_uop_is_jal <= io_in_uop_bits_is_jal;\n slot_uop_is_sfb <= io_in_uop_bits_is_sfb;\n slot_uop_br_tag <= io_in_uop_bits_br_tag;\n slot_uop_ftq_idx <= io_in_uop_bits_ftq_idx;\n slot_uop_edge_inst <= io_in_uop_bits_edge_inst;\n slot_uop_pc_lob <= io_in_uop_bits_pc_lob;\n slot_uop_taken <= io_in_uop_bits_taken;\n slot_uop_imm_packed <= io_in_uop_bits_imm_packed;\n slot_uop_csr_addr <= io_in_uop_bits_csr_addr;\n slot_uop_rob_idx <= io_in_uop_bits_rob_idx;\n slot_uop_ldq_idx <= io_in_uop_bits_ldq_idx;\n slot_uop_stq_idx <= io_in_uop_bits_stq_idx;\n slot_uop_rxq_idx <= io_in_uop_bits_rxq_idx;\n slot_uop_prs1 <= io_in_uop_bits_prs1;\n slot_uop_prs2 <= io_in_uop_bits_prs2;\n slot_uop_prs3 <= io_in_uop_bits_prs3;\n slot_uop_ppred <= io_in_uop_bits_ppred;\n slot_uop_prs1_busy <= io_in_uop_bits_prs1_busy;\n slot_uop_prs2_busy <= io_in_uop_bits_prs2_busy;\n slot_uop_prs3_busy <= io_in_uop_bits_prs3_busy;\n slot_uop_ppred_busy <= io_in_uop_bits_ppred_busy;\n slot_uop_stale_pdst <= io_in_uop_bits_stale_pdst;\n slot_uop_exception <= io_in_uop_bits_exception;\n slot_uop_exc_cause <= io_in_uop_bits_exc_cause;\n slot_uop_mem_cmd <= io_in_uop_bits_mem_cmd;\n slot_uop_mem_size <= io_in_uop_bits_mem_size;\n slot_uop_mem_signed <= io_in_uop_bits_mem_signed;\n slot_uop_is_fence <= io_in_uop_bits_is_fence;\n slot_uop_is_fencei <= io_in_uop_bits_is_fencei;\n slot_uop_is_amo <= io_in_uop_bits_is_amo;\n slot_uop_is_sys_pc2epc <= io_in_uop_bits_is_sys_pc2epc;\n slot_uop_is_unique <= io_in_uop_bits_is_unique;\n slot_uop_flush_on_commit <= io_in_uop_bits_flush_on_commit;\n slot_uop_ldst_is_rs1 <= io_in_uop_bits_ldst_is_rs1;\n slot_uop_ldst <= io_in_uop_bits_ldst;\n slot_uop_lrs1 <= io_in_uop_bits_lrs1;\n slot_uop_lrs2 <= io_in_uop_bits_lrs2;\n slot_uop_lrs3 <= io_in_uop_bits_lrs3;\n slot_uop_ldst_val <= io_in_uop_bits_ldst_val;\n slot_uop_lrs1_rtype <= io_in_uop_bits_lrs1_rtype;\n slot_uop_lrs2_rtype <= io_in_uop_bits_lrs2_rtype;\n slot_uop_frs3_en <= io_in_uop_bits_frs3_en;\n slot_uop_fp_single <= io_in_uop_bits_fp_single;\n slot_uop_xcpt_pf_if <= io_in_uop_bits_xcpt_pf_if;\n slot_uop_xcpt_ae_if <= io_in_uop_bits_xcpt_ae_if;\n slot_uop_xcpt_ma_if <= io_in_uop_bits_xcpt_ma_if;\n slot_uop_bp_debug_if <= io_in_uop_bits_bp_debug_if;\n slot_uop_bp_xcpt_if <= io_in_uop_bits_bp_xcpt_if;\n slot_uop_debug_fsrc <= io_in_uop_bits_debug_fsrc;\n slot_uop_debug_tsrc <= io_in_uop_bits_debug_tsrc;\n end\n else begin\n if (_GEN_5) begin\n end\n else\n slot_uop_lrs1_rtype <= 2'h2;\n if (_GEN_6) begin\n end\n else\n slot_uop_lrs2_rtype <= 2'h2;\n end\n slot_uop_br_mask <= io_in_uop_valid ? io_in_uop_bits_br_mask : next_br_mask;\n end\n assign io_valid = |state;\n assign io_will_be_valid = (|state) & ~(io_grant & (_may_vacate_T | _may_vacate_T_1 & p1 & p2 & ppred) & ~(io_ldspec_miss & (p1_poisoned | p2_poisoned)));\n assign io_request = _may_vacate_T ? p1 & p2 & p3 & ppred & ~io_kill : _GEN & (p1 | p2) & ppred & ~io_kill;\n assign io_out_uop_uopc = _GEN_5 ? slot_uop_uopc : 7'h3;\n assign io_out_uop_inst = slot_uop_inst;\n assign io_out_uop_debug_inst = slot_uop_debug_inst;\n assign io_out_uop_is_rvc = slot_uop_is_rvc;\n assign io_out_uop_debug_pc = slot_uop_debug_pc;\n assign io_out_uop_iq_type = slot_uop_iq_type;\n assign io_out_uop_fu_code = slot_uop_fu_code;\n assign io_out_uop_iw_state = _GEN_11 ? 2'h0 : _GEN_1 ? (_GEN_2 ? state : 2'h0) : _GEN_3 ? 2'h1 : state;\n assign io_out_uop_iw_p1_poisoned = p1_poisoned;\n assign io_out_uop_iw_p2_poisoned = p2_poisoned;\n assign io_out_uop_is_br = slot_uop_is_br;\n assign io_out_uop_is_jalr = slot_uop_is_jalr;\n assign io_out_uop_is_jal = slot_uop_is_jal;\n assign io_out_uop_is_sfb = slot_uop_is_sfb;\n assign io_out_uop_br_mask = next_br_mask;\n assign io_out_uop_br_tag = slot_uop_br_tag;\n assign io_out_uop_ftq_idx = slot_uop_ftq_idx;\n assign io_out_uop_edge_inst = slot_uop_edge_inst;\n assign io_out_uop_pc_lob = slot_uop_pc_lob;\n assign io_out_uop_taken = slot_uop_taken;\n assign io_out_uop_imm_packed = slot_uop_imm_packed;\n assign io_out_uop_csr_addr = slot_uop_csr_addr;\n assign io_out_uop_rob_idx = slot_uop_rob_idx;\n assign io_out_uop_ldq_idx = slot_uop_ldq_idx;\n assign io_out_uop_stq_idx = slot_uop_stq_idx;\n assign io_out_uop_rxq_idx = slot_uop_rxq_idx;\n assign io_out_uop_pdst = slot_uop_pdst;\n assign io_out_uop_prs1 = slot_uop_prs1;\n assign io_out_uop_prs2 = slot_uop_prs2;\n assign io_out_uop_prs3 = slot_uop_prs3;\n assign io_out_uop_ppred = slot_uop_ppred;\n assign io_out_uop_prs1_busy = ~p1;\n assign io_out_uop_prs2_busy = ~p2;\n assign io_out_uop_prs3_busy = ~p3;\n assign io_out_uop_ppred_busy = ~ppred;\n assign io_out_uop_stale_pdst = slot_uop_stale_pdst;\n assign io_out_uop_exception = slot_uop_exception;\n assign io_out_uop_exc_cause = slot_uop_exc_cause;\n assign io_out_uop_bypassable = slot_uop_bypassable;\n assign io_out_uop_mem_cmd = slot_uop_mem_cmd;\n assign io_out_uop_mem_size = slot_uop_mem_size;\n assign io_out_uop_mem_signed = slot_uop_mem_signed;\n assign io_out_uop_is_fence = slot_uop_is_fence;\n assign io_out_uop_is_fencei = slot_uop_is_fencei;\n assign io_out_uop_is_amo = slot_uop_is_amo;\n assign io_out_uop_uses_ldq = slot_uop_uses_ldq;\n assign io_out_uop_uses_stq = slot_uop_uses_stq;\n assign io_out_uop_is_sys_pc2epc = slot_uop_is_sys_pc2epc;\n assign io_out_uop_is_unique = slot_uop_is_unique;\n assign io_out_uop_flush_on_commit = slot_uop_flush_on_commit;\n assign io_out_uop_ldst_is_rs1 = slot_uop_ldst_is_rs1;\n assign io_out_uop_ldst = slot_uop_ldst;\n assign io_out_uop_lrs1 = slot_uop_lrs1;\n assign io_out_uop_lrs2 = slot_uop_lrs2;\n assign io_out_uop_lrs3 = slot_uop_lrs3;\n assign io_out_uop_ldst_val = slot_uop_ldst_val;\n assign io_out_uop_dst_rtype = slot_uop_dst_rtype;\n assign io_out_uop_lrs1_rtype = _GEN_5 ? slot_uop_lrs1_rtype : 2'h2;\n assign io_out_uop_lrs2_rtype = _GEN_6 ? slot_uop_lrs2_rtype : 2'h2;\n assign io_out_uop_frs3_en = slot_uop_frs3_en;\n assign io_out_uop_fp_val = slot_uop_fp_val;\n assign io_out_uop_fp_single = slot_uop_fp_single;\n assign io_out_uop_xcpt_pf_if = slot_uop_xcpt_pf_if;\n assign io_out_uop_xcpt_ae_if = slot_uop_xcpt_ae_if;\n assign io_out_uop_xcpt_ma_if = slot_uop_xcpt_ma_if;\n assign io_out_uop_bp_debug_if = slot_uop_bp_debug_if;\n assign io_out_uop_bp_xcpt_if = slot_uop_bp_xcpt_if;\n assign io_out_uop_debug_fsrc = slot_uop_debug_fsrc;\n assign io_out_uop_debug_tsrc = slot_uop_debug_tsrc;\n assign io_uop_uopc = _GEN_14 ? slot_uop_uopc : 7'h3;\n assign io_uop_inst = slot_uop_inst;\n assign io_uop_debug_inst = slot_uop_debug_inst;\n assign io_uop_is_rvc = slot_uop_is_rvc;\n assign io_uop_debug_pc = slot_uop_debug_pc;\n assign io_uop_iq_type = slot_uop_iq_type;\n assign io_uop_fu_code = slot_uop_fu_code;\n assign io_uop_iw_state = slot_uop_iw_state;\n assign io_uop_iw_p1_poisoned = p1_poisoned;\n assign io_uop_iw_p2_poisoned = p2_poisoned;\n assign io_uop_is_br = slot_uop_is_br;\n assign io_uop_is_jalr = slot_uop_is_jalr;\n assign io_uop_is_jal = slot_uop_is_jal;\n assign io_uop_is_sfb = slot_uop_is_sfb;\n assign io_uop_br_mask = slot_uop_br_mask;\n assign io_uop_br_tag = slot_uop_br_tag;\n assign io_uop_ftq_idx = slot_uop_ftq_idx;\n assign io_uop_edge_inst = slot_uop_edge_inst;\n assign io_uop_pc_lob = slot_uop_pc_lob;\n assign io_uop_taken = slot_uop_taken;\n assign io_uop_imm_packed = slot_uop_imm_packed;\n assign io_uop_csr_addr = slot_uop_csr_addr;\n assign io_uop_rob_idx = slot_uop_rob_idx;\n assign io_uop_ldq_idx = slot_uop_ldq_idx;\n assign io_uop_stq_idx = slot_uop_stq_idx;\n assign io_uop_rxq_idx = slot_uop_rxq_idx;\n assign io_uop_pdst = slot_uop_pdst;\n assign io_uop_prs1 = slot_uop_prs1;\n assign io_uop_prs2 = slot_uop_prs2;\n assign io_uop_prs3 = slot_uop_prs3;\n assign io_uop_ppred = slot_uop_ppred;\n assign io_uop_prs1_busy = slot_uop_prs1_busy;\n assign io_uop_prs2_busy = slot_uop_prs2_busy;\n assign io_uop_prs3_busy = slot_uop_prs3_busy;\n assign io_uop_ppred_busy = slot_uop_ppred_busy;\n assign io_uop_stale_pdst = slot_uop_stale_pdst;\n assign io_uop_exception = slot_uop_exception;\n assign io_uop_exc_cause = slot_uop_exc_cause;\n assign io_uop_bypassable = slot_uop_bypassable;\n assign io_uop_mem_cmd = slot_uop_mem_cmd;\n assign io_uop_mem_size = slot_uop_mem_size;\n assign io_uop_mem_signed = slot_uop_mem_signed;\n assign io_uop_is_fence = slot_uop_is_fence;\n assign io_uop_is_fencei = slot_uop_is_fencei;\n assign io_uop_is_amo = slot_uop_is_amo;\n assign io_uop_uses_ldq = slot_uop_uses_ldq;\n assign io_uop_uses_stq = slot_uop_uses_stq;\n assign io_uop_is_sys_pc2epc = slot_uop_is_sys_pc2epc;\n assign io_uop_is_unique = slot_uop_is_unique;\n assign io_uop_flush_on_commit = slot_uop_flush_on_commit;\n assign io_uop_ldst_is_rs1 = slot_uop_ldst_is_rs1;\n assign io_uop_ldst = slot_uop_ldst;\n assign io_uop_lrs1 = slot_uop_lrs1;\n assign io_uop_lrs2 = slot_uop_lrs2;\n assign io_uop_lrs3 = slot_uop_lrs3;\n assign io_uop_ldst_val = slot_uop_ldst_val;\n assign io_uop_dst_rtype = slot_uop_dst_rtype;\n assign io_uop_lrs1_rtype = _GEN_14 ? slot_uop_lrs1_rtype : 2'h2;\n assign io_uop_lrs2_rtype = ~_may_vacate_T_1 | _GEN_12 | ~_GEN_13 ? slot_uop_lrs2_rtype : 2'h2;\n assign io_uop_frs3_en = slot_uop_frs3_en;\n assign io_uop_fp_val = slot_uop_fp_val;\n assign io_uop_fp_single = slot_uop_fp_single;\n assign io_uop_xcpt_pf_if = slot_uop_xcpt_pf_if;\n assign io_uop_xcpt_ae_if = slot_uop_xcpt_ae_if;\n assign io_uop_xcpt_ma_if = slot_uop_xcpt_ma_if;\n assign io_uop_bp_debug_if = slot_uop_bp_debug_if;\n assign io_uop_bp_xcpt_if = slot_uop_bp_xcpt_if;\n assign io_uop_debug_fsrc = slot_uop_debug_fsrc;\n assign io_uop_debug_tsrc = slot_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Execution Units\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// The issue window schedules micro-ops onto a specific execution pipeline\n// A given execution pipeline may contain multiple functional units; one or more\n// read ports, and one or more writeports.\n\npackage boom.v3.exu\n\nimport scala.collection.mutable.{ArrayBuffer}\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.rocket.{BP}\nimport freechips.rocketchip.tile\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.ifu.{GetPCFromFtqIO}\nimport boom.v3.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringPrefix}\n\n/**\n * Response from Execution Unit. Bundles a MicroOp with data\n *\n * @param dataWidth width of the data coming from the execution unit\n */\nclass ExeUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle\n with HasBoomUOP\n{\n val data = Bits(dataWidth.W)\n val predicated = Bool() // Was this predicated off?\n val fflags = new ValidIO(new FFlagsResp) // write fflags to ROB // TODO: Do this better\n}\n\n/**\n * Floating Point flag response\n */\nclass FFlagsResp(implicit p: Parameters) extends BoomBundle\n{\n val uop = new MicroOp()\n val flags = Bits(tile.FPConstants.FLAGS_SZ.W)\n}\n\n\n/**\n * Abstract Top level Execution Unit that wraps lower level functional units to make a\n * multi function execution unit.\n *\n * @param readsIrf does this exe unit need a integer regfile port\n * @param writesIrf does this exe unit need a integer regfile port\n * @param readsFrf does this exe unit need a integer regfile port\n * @param writesFrf does this exe unit need a integer regfile port\n * @param writesLlIrf does this exe unit need a integer regfile port\n * @param writesLlFrf does this exe unit need a integer regfile port\n * @param numBypassStages number of bypass ports for the exe unit\n * @param dataWidth width of the data coming out of the exe unit\n * @param bypassable is the exe unit able to be bypassed\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasAlu does the exe unit have a alu\n * @param hasFpu does the exe unit have a fpu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nabstract class ExecutionUnit(\n val readsIrf : Boolean = false,\n val writesIrf : Boolean = false,\n val readsFrf : Boolean = false,\n val writesFrf : Boolean = false,\n val writesLlIrf : Boolean = false,\n val writesLlFrf : Boolean = false,\n val numBypassStages : Int,\n val dataWidth : Int,\n val bypassable : Boolean = false, // TODO make override def for code clarity\n val alwaysBypassable : Boolean = false,\n val hasMem : Boolean = false,\n val hasCSR : Boolean = false,\n val hasJmpUnit : Boolean = false,\n val hasAlu : Boolean = false,\n val hasFpu : Boolean = false,\n val hasMul : Boolean = false,\n val hasDiv : Boolean = false,\n val hasFdiv : Boolean = false,\n val hasIfpu : Boolean = false,\n val hasFpiu : Boolean = false,\n val hasRocc : Boolean = false\n )(implicit p: Parameters) extends BoomModule\n{\n\n val io = IO(new Bundle {\n val fu_types = Output(Bits(FUC_SZ.W))\n\n val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))\n\n val iresp = if (writesIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val fresp = if (writesFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_iresp = if (writesLlIrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n val ll_fresp = if (writesLlFrf) new DecoupledIO(new ExeUnitResp(dataWidth)) else null\n\n\n val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))\n val brupdate = Input(new BrUpdateInfo())\n\n\n // only used by the rocc unit\n val rocc = if (hasRocc) new RoCCShimCoreIO else null\n\n // only used by the branch unit\n val brinfo = if (hasAlu) Output(new BrResolutionInfo()) else null\n val get_ftq_pc = if (hasJmpUnit) Flipped(new GetPCFromFtqIO()) else null\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n\n // only used by the fpu unit\n val fcsr_rm = if (hasFcsr) Input(Bits(tile.FPConstants.RM_SZ.W)) else null\n\n // only used by the mem unit\n val lsu_io = if (hasMem) Flipped(new boom.v3.lsu.LSUExeIO) else null\n val bp = if (hasMem) Input(Vec(nBreakpoints, new BP)) else null\n val mcontext = if (hasMem) Input(UInt(coreParams.mcontextWidth.W)) else null\n val scontext = if (hasMem) Input(UInt(coreParams.scontextWidth.W)) else null\n\n // TODO move this out of ExecutionUnit\n val com_exception = if (hasMem || hasRocc) Input(Bool()) else null\n })\n\n io.req.ready := false.B\n\n if (writesIrf) {\n io.iresp.valid := false.B\n io.iresp.bits := DontCare\n io.iresp.bits.fflags.valid := false.B\n io.iresp.bits.predicated := false.B\n assert(io.iresp.ready)\n }\n if (writesLlIrf) {\n io.ll_iresp.valid := false.B\n io.ll_iresp.bits := DontCare\n io.ll_iresp.bits.fflags.valid := false.B\n io.ll_iresp.bits.predicated := false.B\n }\n if (writesFrf) {\n io.fresp.valid := false.B\n io.fresp.bits := DontCare\n io.fresp.bits.fflags.valid := false.B\n io.fresp.bits.predicated := false.B\n assert(io.fresp.ready)\n }\n if (writesLlFrf) {\n io.ll_fresp.valid := false.B\n io.ll_fresp.bits := DontCare\n io.ll_fresp.bits.fflags.valid := false.B\n io.ll_fresp.bits.predicated := false.B\n }\n\n // TODO add \"number of fflag ports\", so we can properly account for FPU+Mem combinations\n def hasFFlags : Boolean = hasFpu || hasFdiv\n\n require ((hasFpu || hasFdiv) ^ (hasAlu || hasMul || hasMem || hasIfpu),\n \"[execute] we no longer support mixing FP and Integer functional units in the same exe unit.\")\n def hasFcsr = hasIfpu || hasFpu || hasFdiv\n\n require (bypassable || !alwaysBypassable,\n \"[execute] an execution unit must be bypassable if it is always bypassable\")\n\n def supportedFuncUnits = {\n new SupportedFuncUnits(\n alu = hasAlu,\n jmp = hasJmpUnit,\n mem = hasMem,\n muld = hasMul || hasDiv,\n fpu = hasFpu,\n csr = hasCSR,\n fdiv = hasFdiv,\n ifpu = hasIfpu)\n }\n}\n\n/**\n * ALU execution unit that can have a branch, alu, mul, div, int to FP,\n * and memory unit.\n *\n * @param hasBrUnit does the exe unit have a branch unit\n * @param hasCSR does the exe unit write to the CSRFile\n * @param hasAlu does the exe unit have a alu\n * @param hasMul does the exe unit have a multiplier\n * @param hasDiv does the exe unit have a divider\n * @param hasIfpu does the exe unit have a int to FP unit\n * @param hasMem does the exe unit have a MemAddrCalcUnit\n */\nclass ALUExeUnit(\n hasJmpUnit : Boolean = false,\n hasCSR : Boolean = false,\n hasAlu : Boolean = true,\n hasMul : Boolean = false,\n hasDiv : Boolean = false,\n hasIfpu : Boolean = false,\n hasMem : Boolean = false,\n hasRocc : Boolean = false)\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsIrf = true,\n writesIrf = hasAlu || hasMul || hasDiv,\n writesLlIrf = hasMem || hasRocc,\n writesLlFrf = (hasIfpu || hasMem) && p(tile.TileKey).core.fpu != None,\n numBypassStages =\n if (hasAlu && hasMul) 3 //TODO XXX p(tile.TileKey).core.imulLatency\n else if (hasAlu) 1 else 0,\n dataWidth = 64 + 1,\n bypassable = hasAlu,\n alwaysBypassable = hasAlu && !(hasMem || hasJmpUnit || hasMul || hasDiv || hasCSR || hasIfpu || hasRocc),\n hasCSR = hasCSR,\n hasJmpUnit = hasJmpUnit,\n hasAlu = hasAlu,\n hasMul = hasMul,\n hasDiv = hasDiv,\n hasIfpu = hasIfpu,\n hasMem = hasMem,\n hasRocc = hasRocc)\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n require(!(hasRocc && !hasCSR),\n \"RoCC needs to be shared with CSR unit\")\n require(!(hasMem && hasRocc),\n \"We do not support execution unit with both Mem and Rocc writebacks\")\n require(!(hasMem && hasIfpu),\n \"TODO. Currently do not support AluMemExeUnit with FP\")\n\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\") +\n (if (hasAlu) BoomCoreStringPrefix(\" - ALU\") else \"\") +\n (if (hasMul) BoomCoreStringPrefix(\" - Mul\") else \"\") +\n (if (hasDiv) BoomCoreStringPrefix(\" - Div\") else \"\") +\n (if (hasIfpu) BoomCoreStringPrefix(\" - IFPU\") else \"\") +\n (if (hasMem) BoomCoreStringPrefix(\" - Mem\") else \"\") +\n (if (hasRocc) BoomCoreStringPrefix(\" - RoCC\") else \"\")\n\n override def toString: String = out_str.toString\n\n val div_busy = WireInit(false.B)\n val ifpu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n // Specifically the functional units with fast writeback to IRF\n val iresp_fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasAlu.B, FU_ALU, 0.U) |\n Mux(hasMul.B, FU_MUL, 0.U) |\n Mux(!div_busy && hasDiv.B, FU_DIV, 0.U) |\n Mux(hasCSR.B, FU_CSR, 0.U) |\n Mux(hasJmpUnit.B, FU_JMP, 0.U) |\n Mux(!ifpu_busy && hasIfpu.B, FU_I2F, 0.U) |\n Mux(hasMem.B, FU_MEM, 0.U)\n\n // ALU Unit -------------------------------\n var alu: ALUUnit = null\n if (hasAlu) {\n alu = Module(new ALUUnit(isJmpUnit = hasJmpUnit,\n numStages = numBypassStages,\n dataWidth = xLen))\n alu.io.req.valid := (\n io.req.valid &&\n (io.req.bits.uop.fu_code === FU_ALU ||\n io.req.bits.uop.fu_code === FU_JMP ||\n (io.req.bits.uop.fu_code === FU_CSR && io.req.bits.uop.uopc =/= uopROCC)))\n //ROCC Rocc Commands are taken by the RoCC unit\n\n alu.io.req.bits.uop := io.req.bits.uop\n alu.io.req.bits.kill := io.req.bits.kill\n alu.io.req.bits.rs1_data := io.req.bits.rs1_data\n alu.io.req.bits.rs2_data := io.req.bits.rs2_data\n alu.io.req.bits.rs3_data := DontCare\n alu.io.req.bits.pred_data := io.req.bits.pred_data\n alu.io.resp.ready := DontCare\n alu.io.brupdate := io.brupdate\n\n iresp_fu_units += alu\n\n // Bypassing only applies to ALU\n io.bypass := alu.io.bypass\n\n // branch unit is embedded inside the ALU\n io.brinfo := alu.io.brinfo\n if (hasJmpUnit) {\n alu.io.get_ftq_pc <> io.get_ftq_pc\n }\n }\n\n var rocc: RoCCShim = null\n if (hasRocc) {\n rocc = Module(new RoCCShim)\n rocc.io.req.valid := io.req.valid && io.req.bits.uop.uopc === uopROCC\n rocc.io.req.bits := DontCare\n rocc.io.req.bits.uop := io.req.bits.uop\n rocc.io.req.bits.kill := io.req.bits.kill\n rocc.io.req.bits.rs1_data := io.req.bits.rs1_data\n rocc.io.req.bits.rs2_data := io.req.bits.rs2_data\n rocc.io.brupdate := io.brupdate // We should assert on this somewhere\n rocc.io.status := io.status\n rocc.io.exception := io.com_exception\n io.rocc <> rocc.io.core\n\n rocc.io.resp.ready := io.ll_iresp.ready\n io.ll_iresp.valid := rocc.io.resp.valid\n io.ll_iresp.bits.uop := rocc.io.resp.bits.uop\n io.ll_iresp.bits.data := rocc.io.resp.bits.data\n }\n\n\n // Pipelined, IMul Unit ------------------\n var imul: PipelinedMulUnit = null\n if (hasMul) {\n imul = Module(new PipelinedMulUnit(imulLatency, xLen))\n imul.io <> DontCare\n imul.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MUL)\n imul.io.req.bits.uop := io.req.bits.uop\n imul.io.req.bits.rs1_data := io.req.bits.rs1_data\n imul.io.req.bits.rs2_data := io.req.bits.rs2_data\n imul.io.req.bits.kill := io.req.bits.kill\n imul.io.brupdate := io.brupdate\n iresp_fu_units += imul\n }\n\n var ifpu: IntToFPUnit = null\n if (hasIfpu) {\n ifpu = Module(new IntToFPUnit(latency=intToFpLatency))\n ifpu.io.req <> io.req\n ifpu.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_I2F)\n ifpu.io.fcsr_rm := io.fcsr_rm\n ifpu.io.brupdate <> io.brupdate\n ifpu.io.resp.ready := DontCare\n\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = intToFpLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := ifpu.io.resp.valid\n queue.io.enq.bits.uop := ifpu.io.resp.bits.uop\n queue.io.enq.bits.data := ifpu.io.resp.bits.data\n queue.io.enq.bits.predicated := ifpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := ifpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n io.ll_fresp <> queue.io.deq\n ifpu_busy := !(queue.io.empty)\n assert (queue.io.enq.ready)\n }\n\n // Div/Rem Unit -----------------------\n var div: DivUnit = null\n val div_resp_val = WireInit(false.B)\n if (hasDiv) {\n div = Module(new DivUnit(xLen))\n div.io <> DontCare\n div.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV) && hasDiv.B\n div.io.req.bits.uop := io.req.bits.uop\n div.io.req.bits.rs1_data := io.req.bits.rs1_data\n div.io.req.bits.rs2_data := io.req.bits.rs2_data\n div.io.brupdate := io.brupdate\n div.io.req.bits.kill := io.req.bits.kill\n\n // share write port with the pipelined units\n div.io.resp.ready := !(iresp_fu_units.map(_.io.resp.valid).reduce(_|_))\n\n div_resp_val := div.io.resp.valid\n div_busy := !div.io.req.ready ||\n (io.req.valid && io.req.bits.uop.fu_code_is(FU_DIV))\n\n iresp_fu_units += div\n }\n\n // Mem Unit --------------------------\n if (hasMem) {\n require(!hasAlu)\n val maddrcalc = Module(new MemAddrCalcUnit)\n maddrcalc.io.req <> io.req\n maddrcalc.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_MEM)\n maddrcalc.io.brupdate <> io.brupdate\n maddrcalc.io.status := io.status\n maddrcalc.io.bp := io.bp\n maddrcalc.io.mcontext := io.mcontext\n maddrcalc.io.scontext := io.scontext\n maddrcalc.io.resp.ready := DontCare\n require(numBypassStages == 0)\n\n io.lsu_io.req := maddrcalc.io.resp\n\n io.ll_iresp <> io.lsu_io.iresp\n if (usingFPU) {\n io.ll_fresp <> io.lsu_io.fresp\n }\n }\n\n // Outputs (Write Port #0) ---------------\n if (writesIrf) {\n io.iresp.valid := iresp_fu_units.map(_.io.resp.valid).reduce(_|_)\n io.iresp.bits.uop := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.uop)).toSeq)\n io.iresp.bits.data := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.iresp.bits.predicated := PriorityMux(iresp_fu_units.map(f =>\n (f.io.resp.valid, f.io.resp.bits.predicated)).toSeq)\n\n // pulled out for critical path reasons\n // TODO: Does this make sense as part of the iresp bundle?\n if (hasAlu) {\n io.iresp.bits.uop.csr_addr := ImmGen(alu.io.resp.bits.uop.imm_packed, IS_I).asUInt\n io.iresp.bits.uop.ctrl.csr_cmd := alu.io.resp.bits.uop.ctrl.csr_cmd\n }\n }\n\n assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n (PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 2.U && (div_resp_val)),\n \"Multiple functional units are fighting over the write port.\")\n}\n\n/**\n * FPU-only unit, with optional second write-port for ToInt micro-ops.\n *\n * @param hasFpu does the exe unit have a fpu\n * @param hasFdiv does the exe unit have a FP divider\n * @param hasFpiu does the exe unit have a FP to int unit\n */\nclass FPUExeUnit(\n hasFpu : Boolean = true,\n hasFdiv : Boolean = false,\n hasFpiu : Boolean = false\n )\n (implicit p: Parameters)\n extends ExecutionUnit(\n readsFrf = true,\n writesFrf = true,\n writesLlIrf = hasFpiu,\n writesIrf = false,\n numBypassStages = 0,\n dataWidth = p(tile.TileKey).core.fpu.get.fLen + 1,\n bypassable = false,\n hasFpu = hasFpu,\n hasFdiv = hasFdiv,\n hasFpiu = hasFpiu) with tile.HasFPUParameters\n{\n val out_str =\n BoomCoreStringPrefix(\"==ExeUnit==\")\n (if (hasFpu) BoomCoreStringPrefix(\"- FPU (Latency: \" + dfmaLatency + \")\") else \"\") +\n (if (hasFdiv) BoomCoreStringPrefix(\"- FDiv/FSqrt\") else \"\") +\n (if (hasFpiu) BoomCoreStringPrefix(\"- FPIU (writes to Integer RF)\") else \"\")\n\n val fdiv_busy = WireInit(false.B)\n val fpiu_busy = WireInit(false.B)\n\n // The Functional Units --------------------\n val fu_units = ArrayBuffer[FunctionalUnit]()\n\n io.fu_types := Mux(hasFpu.B, FU_FPU, 0.U) |\n Mux(!fdiv_busy && hasFdiv.B, FU_FDV, 0.U) |\n Mux(!fpiu_busy && hasFpiu.B, FU_F2I, 0.U)\n\n // FPU Unit -----------------------\n var fpu: FPUUnit = null\n val fpu_resp_val = WireInit(false.B)\n val fpu_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fpu_resp_fflags.valid := false.B\n if (hasFpu) {\n fpu = Module(new FPUUnit())\n fpu.io.req.valid := io.req.valid &&\n (io.req.bits.uop.fu_code_is(FU_FPU) ||\n io.req.bits.uop.fu_code_is(FU_F2I)) // TODO move to using a separate unit\n fpu.io.req.bits.uop := io.req.bits.uop\n fpu.io.req.bits.rs1_data := io.req.bits.rs1_data\n fpu.io.req.bits.rs2_data := io.req.bits.rs2_data\n fpu.io.req.bits.rs3_data := io.req.bits.rs3_data\n fpu.io.req.bits.pred_data := false.B\n fpu.io.req.bits.kill := io.req.bits.kill\n fpu.io.fcsr_rm := io.fcsr_rm\n fpu.io.brupdate := io.brupdate\n fpu.io.resp.ready := DontCare\n fpu_resp_val := fpu.io.resp.valid\n fpu_resp_fflags := fpu.io.resp.bits.fflags\n\n fu_units += fpu\n }\n\n // FDiv/FSqrt Unit -----------------------\n var fdivsqrt: FDivSqrtUnit = null\n val fdiv_resp_fflags = Wire(new ValidIO(new FFlagsResp()))\n fdiv_resp_fflags := DontCare\n fdiv_resp_fflags.valid := false.B\n if (hasFdiv) {\n fdivsqrt = Module(new FDivSqrtUnit())\n fdivsqrt.io.req.valid := io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV)\n fdivsqrt.io.req.bits.uop := io.req.bits.uop\n fdivsqrt.io.req.bits.rs1_data := io.req.bits.rs1_data\n fdivsqrt.io.req.bits.rs2_data := io.req.bits.rs2_data\n fdivsqrt.io.req.bits.rs3_data := DontCare\n fdivsqrt.io.req.bits.pred_data := false.B\n fdivsqrt.io.req.bits.kill := io.req.bits.kill\n fdivsqrt.io.fcsr_rm := io.fcsr_rm\n fdivsqrt.io.brupdate := io.brupdate\n\n // share write port with the pipelined units\n fdivsqrt.io.resp.ready := !(fu_units.map(_.io.resp.valid).reduce(_|_)) // TODO PERF will get blocked by fpiu.\n\n fdiv_busy := !fdivsqrt.io.req.ready || (io.req.valid && io.req.bits.uop.fu_code_is(FU_FDV))\n\n fdiv_resp_fflags := fdivsqrt.io.resp.bits.fflags\n\n fu_units += fdivsqrt\n }\n\n // Outputs (Write Port #0) ---------------\n\n io.fresp.valid := fu_units.map(_.io.resp.valid).reduce(_|_) &&\n !(fpu.io.resp.valid && fpu.io.resp.bits.uop.fu_code_is(FU_F2I))\n io.fresp.bits.uop := PriorityMux(fu_units.map(f => (f.io.resp.valid,\n f.io.resp.bits.uop)).toSeq)\n io.fresp.bits.data:= PriorityMux(fu_units.map(f => (f.io.resp.valid, f.io.resp.bits.data)).toSeq)\n io.fresp.bits.fflags := Mux(fpu_resp_val, fpu_resp_fflags, fdiv_resp_fflags)\n\n // Outputs (Write Port #1) -- FpToInt Queuing Unit -----------------------\n\n if (hasFpiu) {\n // TODO instantiate our own fpiu; and remove it from fpu.scala.\n // buffer up results since we share write-port on integer regfile.\n val queue = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = dfmaLatency + 3)) // TODO being overly conservative\n queue.io.enq.valid := (fpu.io.resp.valid &&\n fpu.io.resp.bits.uop.fu_code_is(FU_F2I) &&\n fpu.io.resp.bits.uop.uopc =/= uopSTA) // STA means store data gen for floating point\n queue.io.enq.bits.uop := fpu.io.resp.bits.uop\n queue.io.enq.bits.data := fpu.io.resp.bits.data\n queue.io.enq.bits.predicated := fpu.io.resp.bits.predicated\n queue.io.enq.bits.fflags := fpu.io.resp.bits.fflags\n queue.io.brupdate := io.brupdate\n queue.io.flush := io.req.bits.kill\n\n assert (queue.io.enq.ready) // If this backs up, we've miscalculated the size of the queue.\n\n val fp_sdq = Module(new BranchKillableQueue(new ExeUnitResp(dataWidth),\n entries = 3)) // Lets us backpressure floating point store data\n fp_sdq.io.enq.valid := io.req.valid && io.req.bits.uop.uopc === uopSTA && !IsKilledByBranch(io.brupdate, io.req.bits.uop)\n fp_sdq.io.enq.bits.uop := io.req.bits.uop\n fp_sdq.io.enq.bits.data := ieee(io.req.bits.rs2_data)\n fp_sdq.io.enq.bits.predicated := false.B\n fp_sdq.io.enq.bits.fflags := DontCare\n fp_sdq.io.brupdate := io.brupdate\n fp_sdq.io.flush := io.req.bits.kill\n\n assert(!(fp_sdq.io.enq.valid && !fp_sdq.io.enq.ready))\n\n val resp_arb = Module(new Arbiter(new ExeUnitResp(dataWidth), 2))\n resp_arb.io.in(0) <> queue.io.deq\n resp_arb.io.in(1) <> fp_sdq.io.deq\n io.ll_iresp <> resp_arb.io.out\n\n fpiu_busy := !(queue.io.empty && fp_sdq.io.empty)\n }\n\n override def toString: String = out_str.toString\n}", + "response": "module ALUExeUnit_1(\n input clock,\n input reset,\n output [9:0] io_fu_types,\n input io_req_valid,\n input [6:0] io_req_bits_uop_uopc,\n input [31:0] io_req_bits_uop_inst,\n input [31:0] io_req_bits_uop_debug_inst,\n input io_req_bits_uop_is_rvc,\n input [39:0] io_req_bits_uop_debug_pc,\n input [2:0] io_req_bits_uop_iq_type,\n input [9:0] io_req_bits_uop_fu_code,\n input [3:0] io_req_bits_uop_ctrl_br_type,\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\n input io_req_bits_uop_ctrl_fcn_dw,\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\n input io_req_bits_uop_ctrl_is_load,\n input io_req_bits_uop_ctrl_is_sta,\n input io_req_bits_uop_ctrl_is_std,\n input [1:0] io_req_bits_uop_iw_state,\n input io_req_bits_uop_is_br,\n input io_req_bits_uop_is_jalr,\n input io_req_bits_uop_is_jal,\n input io_req_bits_uop_is_sfb,\n input [7:0] io_req_bits_uop_br_mask,\n input [2:0] io_req_bits_uop_br_tag,\n input [3:0] io_req_bits_uop_ftq_idx,\n input io_req_bits_uop_edge_inst,\n input [5:0] io_req_bits_uop_pc_lob,\n input io_req_bits_uop_taken,\n input [19:0] io_req_bits_uop_imm_packed,\n input [11:0] io_req_bits_uop_csr_addr,\n input [4:0] io_req_bits_uop_rob_idx,\n input [2:0] io_req_bits_uop_ldq_idx,\n input [2:0] io_req_bits_uop_stq_idx,\n input [1:0] io_req_bits_uop_rxq_idx,\n input [5:0] io_req_bits_uop_pdst,\n input [5:0] io_req_bits_uop_prs1,\n input [5:0] io_req_bits_uop_prs2,\n input [5:0] io_req_bits_uop_prs3,\n input [3:0] io_req_bits_uop_ppred,\n input io_req_bits_uop_prs1_busy,\n input io_req_bits_uop_prs2_busy,\n input io_req_bits_uop_prs3_busy,\n input io_req_bits_uop_ppred_busy,\n input [5:0] io_req_bits_uop_stale_pdst,\n input io_req_bits_uop_exception,\n input [63:0] io_req_bits_uop_exc_cause,\n input io_req_bits_uop_bypassable,\n input [4:0] io_req_bits_uop_mem_cmd,\n input [1:0] io_req_bits_uop_mem_size,\n input io_req_bits_uop_mem_signed,\n input io_req_bits_uop_is_fence,\n input io_req_bits_uop_is_fencei,\n input io_req_bits_uop_is_amo,\n input io_req_bits_uop_uses_ldq,\n input io_req_bits_uop_uses_stq,\n input io_req_bits_uop_is_sys_pc2epc,\n input io_req_bits_uop_is_unique,\n input io_req_bits_uop_flush_on_commit,\n input io_req_bits_uop_ldst_is_rs1,\n input [5:0] io_req_bits_uop_ldst,\n input [5:0] io_req_bits_uop_lrs1,\n input [5:0] io_req_bits_uop_lrs2,\n input [5:0] io_req_bits_uop_lrs3,\n input io_req_bits_uop_ldst_val,\n input [1:0] io_req_bits_uop_dst_rtype,\n input [1:0] io_req_bits_uop_lrs1_rtype,\n input [1:0] io_req_bits_uop_lrs2_rtype,\n input io_req_bits_uop_frs3_en,\n input io_req_bits_uop_fp_val,\n input io_req_bits_uop_fp_single,\n input io_req_bits_uop_xcpt_pf_if,\n input io_req_bits_uop_xcpt_ae_if,\n input io_req_bits_uop_xcpt_ma_if,\n input io_req_bits_uop_bp_debug_if,\n input io_req_bits_uop_bp_xcpt_if,\n input [1:0] io_req_bits_uop_debug_fsrc,\n input [1:0] io_req_bits_uop_debug_tsrc,\n input [64:0] io_req_bits_rs1_data,\n input [64:0] io_req_bits_rs2_data,\n input io_req_bits_kill,\n output io_iresp_valid,\n output [2:0] io_iresp_bits_uop_ctrl_csr_cmd,\n output [11:0] io_iresp_bits_uop_csr_addr,\n output [4:0] io_iresp_bits_uop_rob_idx,\n output [5:0] io_iresp_bits_uop_pdst,\n output io_iresp_bits_uop_bypassable,\n output io_iresp_bits_uop_is_amo,\n output io_iresp_bits_uop_uses_stq,\n output [1:0] io_iresp_bits_uop_dst_rtype,\n output [64:0] io_iresp_bits_data,\n input io_ll_fresp_ready,\n output io_ll_fresp_valid,\n output [6:0] io_ll_fresp_bits_uop_uopc,\n output [7:0] io_ll_fresp_bits_uop_br_mask,\n output [4:0] io_ll_fresp_bits_uop_rob_idx,\n output [2:0] io_ll_fresp_bits_uop_stq_idx,\n output [5:0] io_ll_fresp_bits_uop_pdst,\n output io_ll_fresp_bits_uop_is_amo,\n output io_ll_fresp_bits_uop_uses_stq,\n output [1:0] io_ll_fresp_bits_uop_dst_rtype,\n output io_ll_fresp_bits_uop_fp_val,\n output [64:0] io_ll_fresp_bits_data,\n output io_ll_fresp_bits_predicated,\n output io_ll_fresp_bits_fflags_valid,\n output [4:0] io_ll_fresp_bits_fflags_bits_uop_rob_idx,\n output [4:0] io_ll_fresp_bits_fflags_bits_flags,\n output io_bypass_0_valid,\n output [5:0] io_bypass_0_bits_uop_pdst,\n output [1:0] io_bypass_0_bits_uop_dst_rtype,\n output [64:0] io_bypass_0_bits_data,\n output io_bypass_1_valid,\n output [5:0] io_bypass_1_bits_uop_pdst,\n output [1:0] io_bypass_1_bits_uop_dst_rtype,\n output [64:0] io_bypass_1_bits_data,\n output io_bypass_2_valid,\n output [5:0] io_bypass_2_bits_uop_pdst,\n output [1:0] io_bypass_2_bits_uop_dst_rtype,\n output [64:0] io_bypass_2_bits_data,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n output io_brinfo_uop_is_rvc,\n output [7:0] io_brinfo_uop_br_mask,\n output [2:0] io_brinfo_uop_br_tag,\n output [3:0] io_brinfo_uop_ftq_idx,\n output io_brinfo_uop_edge_inst,\n output [5:0] io_brinfo_uop_pc_lob,\n output [4:0] io_brinfo_uop_rob_idx,\n output [2:0] io_brinfo_uop_ldq_idx,\n output [2:0] io_brinfo_uop_stq_idx,\n output io_brinfo_valid,\n output io_brinfo_mispredict,\n output io_brinfo_taken,\n output [2:0] io_brinfo_cfi_type,\n output [1:0] io_brinfo_pc_sel,\n output [39:0] io_brinfo_jalr_target,\n output [20:0] io_brinfo_target_offset,\n input io_get_ftq_pc_entry_cfi_idx_valid,\n input [1:0] io_get_ftq_pc_entry_cfi_idx_bits,\n input io_get_ftq_pc_entry_start_bank,\n input [39:0] io_get_ftq_pc_pc,\n input io_get_ftq_pc_next_val,\n input [39:0] io_get_ftq_pc_next_pc,\n input [2:0] io_fcsr_rm\n);\n\n wire div_busy;\n wire _DivUnit_io_req_ready;\n wire _DivUnit_io_resp_valid;\n wire [4:0] _DivUnit_io_resp_bits_uop_rob_idx;\n wire [5:0] _DivUnit_io_resp_bits_uop_pdst;\n wire _DivUnit_io_resp_bits_uop_bypassable;\n wire _DivUnit_io_resp_bits_uop_is_amo;\n wire _DivUnit_io_resp_bits_uop_uses_stq;\n wire [1:0] _DivUnit_io_resp_bits_uop_dst_rtype;\n wire [63:0] _DivUnit_io_resp_bits_data;\n wire _queue_io_enq_ready;\n wire _queue_io_empty;\n wire _IntToFPUnit_io_resp_valid;\n wire [6:0] _IntToFPUnit_io_resp_bits_uop_uopc;\n wire [31:0] _IntToFPUnit_io_resp_bits_uop_inst;\n wire [31:0] _IntToFPUnit_io_resp_bits_uop_debug_inst;\n wire _IntToFPUnit_io_resp_bits_uop_is_rvc;\n wire [39:0] _IntToFPUnit_io_resp_bits_uop_debug_pc;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_iq_type;\n wire [9:0] _IntToFPUnit_io_resp_bits_uop_fu_code;\n wire [3:0] _IntToFPUnit_io_resp_bits_uop_ctrl_br_type;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op1_sel;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op2_sel;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_imm_sel;\n wire [4:0] _IntToFPUnit_io_resp_bits_uop_ctrl_op_fcn;\n wire _IntToFPUnit_io_resp_bits_uop_ctrl_fcn_dw;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_ctrl_csr_cmd;\n wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_load;\n wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_sta;\n wire _IntToFPUnit_io_resp_bits_uop_ctrl_is_std;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_iw_state;\n wire _IntToFPUnit_io_resp_bits_uop_iw_p1_poisoned;\n wire _IntToFPUnit_io_resp_bits_uop_iw_p2_poisoned;\n wire _IntToFPUnit_io_resp_bits_uop_is_br;\n wire _IntToFPUnit_io_resp_bits_uop_is_jalr;\n wire _IntToFPUnit_io_resp_bits_uop_is_jal;\n wire _IntToFPUnit_io_resp_bits_uop_is_sfb;\n wire [7:0] _IntToFPUnit_io_resp_bits_uop_br_mask;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_br_tag;\n wire [3:0] _IntToFPUnit_io_resp_bits_uop_ftq_idx;\n wire _IntToFPUnit_io_resp_bits_uop_edge_inst;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_pc_lob;\n wire _IntToFPUnit_io_resp_bits_uop_taken;\n wire [19:0] _IntToFPUnit_io_resp_bits_uop_imm_packed;\n wire [11:0] _IntToFPUnit_io_resp_bits_uop_csr_addr;\n wire [4:0] _IntToFPUnit_io_resp_bits_uop_rob_idx;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_ldq_idx;\n wire [2:0] _IntToFPUnit_io_resp_bits_uop_stq_idx;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_rxq_idx;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_pdst;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs2;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_prs3;\n wire [3:0] _IntToFPUnit_io_resp_bits_uop_ppred;\n wire _IntToFPUnit_io_resp_bits_uop_prs1_busy;\n wire _IntToFPUnit_io_resp_bits_uop_prs2_busy;\n wire _IntToFPUnit_io_resp_bits_uop_prs3_busy;\n wire _IntToFPUnit_io_resp_bits_uop_ppred_busy;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_stale_pdst;\n wire _IntToFPUnit_io_resp_bits_uop_exception;\n wire [63:0] _IntToFPUnit_io_resp_bits_uop_exc_cause;\n wire _IntToFPUnit_io_resp_bits_uop_bypassable;\n wire [4:0] _IntToFPUnit_io_resp_bits_uop_mem_cmd;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_mem_size;\n wire _IntToFPUnit_io_resp_bits_uop_mem_signed;\n wire _IntToFPUnit_io_resp_bits_uop_is_fence;\n wire _IntToFPUnit_io_resp_bits_uop_is_fencei;\n wire _IntToFPUnit_io_resp_bits_uop_is_amo;\n wire _IntToFPUnit_io_resp_bits_uop_uses_ldq;\n wire _IntToFPUnit_io_resp_bits_uop_uses_stq;\n wire _IntToFPUnit_io_resp_bits_uop_is_sys_pc2epc;\n wire _IntToFPUnit_io_resp_bits_uop_is_unique;\n wire _IntToFPUnit_io_resp_bits_uop_flush_on_commit;\n wire _IntToFPUnit_io_resp_bits_uop_ldst_is_rs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_ldst;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs2;\n wire [5:0] _IntToFPUnit_io_resp_bits_uop_lrs3;\n wire _IntToFPUnit_io_resp_bits_uop_ldst_val;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_dst_rtype;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_lrs1_rtype;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_lrs2_rtype;\n wire _IntToFPUnit_io_resp_bits_uop_frs3_en;\n wire _IntToFPUnit_io_resp_bits_uop_fp_val;\n wire _IntToFPUnit_io_resp_bits_uop_fp_single;\n wire _IntToFPUnit_io_resp_bits_uop_xcpt_pf_if;\n wire _IntToFPUnit_io_resp_bits_uop_xcpt_ae_if;\n wire _IntToFPUnit_io_resp_bits_uop_xcpt_ma_if;\n wire _IntToFPUnit_io_resp_bits_uop_bp_debug_if;\n wire _IntToFPUnit_io_resp_bits_uop_bp_xcpt_if;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_debug_fsrc;\n wire [1:0] _IntToFPUnit_io_resp_bits_uop_debug_tsrc;\n wire [64:0] _IntToFPUnit_io_resp_bits_data;\n wire _IntToFPUnit_io_resp_bits_fflags_valid;\n wire [6:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_uopc;\n wire [31:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_inst;\n wire [31:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_inst;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_rvc;\n wire [39:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_pc;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_iq_type;\n wire [9:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_fu_code;\n wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel;\n wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_state;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_br;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jalr;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jal;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sfb;\n wire [7:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_br_mask;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_br_tag;\n wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ftq_idx;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_edge_inst;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_pc_lob;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_taken;\n wire [19:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_imm_packed;\n wire [11:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_csr_addr;\n wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_rob_idx;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldq_idx;\n wire [2:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_stq_idx;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_rxq_idx;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_pdst;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3;\n wire [3:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1_busy;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2_busy;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3_busy;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred_busy;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_stale_pdst;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_exception;\n wire [63:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_exc_cause;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bypassable;\n wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_cmd;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_size;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_signed;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fence;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fencei;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_amo;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_ldq;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_stq;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_is_unique;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_flush_on_commit;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2;\n wire [5:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs3;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_val;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_dst_rtype;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_frs3_en;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_val;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_single;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_debug_if;\n wire _IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_fsrc;\n wire [1:0] _IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_tsrc;\n wire [4:0] _IntToFPUnit_io_resp_bits_fflags_bits_flags;\n wire _PipelinedMulUnit_io_resp_valid;\n wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_rob_idx;\n wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_pdst;\n wire _PipelinedMulUnit_io_resp_bits_uop_bypassable;\n wire _PipelinedMulUnit_io_resp_bits_uop_is_amo;\n wire _PipelinedMulUnit_io_resp_bits_uop_uses_stq;\n wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_dst_rtype;\n wire [63:0] _PipelinedMulUnit_io_resp_bits_data;\n wire _ALUUnit_io_resp_valid;\n wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed;\n wire [4:0] _ALUUnit_io_resp_bits_uop_rob_idx;\n wire [5:0] _ALUUnit_io_resp_bits_uop_pdst;\n wire _ALUUnit_io_resp_bits_uop_bypassable;\n wire _ALUUnit_io_resp_bits_uop_is_amo;\n wire _ALUUnit_io_resp_bits_uop_uses_stq;\n wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype;\n wire [63:0] _ALUUnit_io_resp_bits_data;\n wire [63:0] _ALUUnit_io_bypass_0_bits_data;\n wire [63:0] _ALUUnit_io_bypass_1_bits_data;\n wire [63:0] _ALUUnit_io_bypass_2_bits_data;\n wire _io_iresp_valid_T = _ALUUnit_io_resp_valid | _PipelinedMulUnit_io_resp_valid;\n assign div_busy = ~_DivUnit_io_req_ready | io_req_valid & io_req_bits_uop_fu_code[4];\n ALUUnit ALUUnit (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid & (io_req_bits_uop_fu_code == 10'h1 | io_req_bits_uop_fu_code == 10'h2 | io_req_bits_uop_fu_code == 10'h20 & io_req_bits_uop_uopc != 7'h6C)),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),\n .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),\n .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),\n .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),\n .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),\n .io_req_bits_uop_is_br (io_req_bits_uop_is_br),\n .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),\n .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),\n .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),\n .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),\n .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),\n .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),\n .io_req_bits_uop_taken (io_req_bits_uop_taken),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),\n .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_prs1 (io_req_bits_uop_prs1),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_rs1_data (io_req_bits_rs1_data[63:0]),\n .io_req_bits_rs2_data (io_req_bits_rs2_data[63:0]),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_valid (_ALUUnit_io_resp_valid),\n .io_resp_bits_uop_ctrl_csr_cmd (io_iresp_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_uop_imm_packed (_ALUUnit_io_resp_bits_uop_imm_packed),\n .io_resp_bits_uop_rob_idx (_ALUUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_pdst (_ALUUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_bypassable (_ALUUnit_io_resp_bits_uop_bypassable),\n .io_resp_bits_uop_is_amo (_ALUUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_stq (_ALUUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_dst_rtype (_ALUUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_data (_ALUUnit_io_resp_bits_data),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_bypass_0_valid (io_bypass_0_valid),\n .io_bypass_0_bits_uop_pdst (io_bypass_0_bits_uop_pdst),\n .io_bypass_0_bits_uop_dst_rtype (io_bypass_0_bits_uop_dst_rtype),\n .io_bypass_0_bits_data (_ALUUnit_io_bypass_0_bits_data),\n .io_bypass_1_valid (io_bypass_1_valid),\n .io_bypass_1_bits_uop_pdst (io_bypass_1_bits_uop_pdst),\n .io_bypass_1_bits_uop_dst_rtype (io_bypass_1_bits_uop_dst_rtype),\n .io_bypass_1_bits_data (_ALUUnit_io_bypass_1_bits_data),\n .io_bypass_2_valid (io_bypass_2_valid),\n .io_bypass_2_bits_uop_pdst (io_bypass_2_bits_uop_pdst),\n .io_bypass_2_bits_uop_dst_rtype (io_bypass_2_bits_uop_dst_rtype),\n .io_bypass_2_bits_data (_ALUUnit_io_bypass_2_bits_data),\n .io_brinfo_uop_is_rvc (io_brinfo_uop_is_rvc),\n .io_brinfo_uop_br_mask (io_brinfo_uop_br_mask),\n .io_brinfo_uop_br_tag (io_brinfo_uop_br_tag),\n .io_brinfo_uop_ftq_idx (io_brinfo_uop_ftq_idx),\n .io_brinfo_uop_edge_inst (io_brinfo_uop_edge_inst),\n .io_brinfo_uop_pc_lob (io_brinfo_uop_pc_lob),\n .io_brinfo_uop_rob_idx (io_brinfo_uop_rob_idx),\n .io_brinfo_uop_ldq_idx (io_brinfo_uop_ldq_idx),\n .io_brinfo_uop_stq_idx (io_brinfo_uop_stq_idx),\n .io_brinfo_valid (io_brinfo_valid),\n .io_brinfo_mispredict (io_brinfo_mispredict),\n .io_brinfo_taken (io_brinfo_taken),\n .io_brinfo_cfi_type (io_brinfo_cfi_type),\n .io_brinfo_pc_sel (io_brinfo_pc_sel),\n .io_brinfo_jalr_target (io_brinfo_jalr_target),\n .io_brinfo_target_offset (io_brinfo_target_offset),\n .io_get_ftq_pc_entry_cfi_idx_valid (io_get_ftq_pc_entry_cfi_idx_valid),\n .io_get_ftq_pc_entry_cfi_idx_bits (io_get_ftq_pc_entry_cfi_idx_bits),\n .io_get_ftq_pc_entry_start_bank (io_get_ftq_pc_entry_start_bank),\n .io_get_ftq_pc_pc (io_get_ftq_pc_pc),\n .io_get_ftq_pc_next_val (io_get_ftq_pc_next_val),\n .io_get_ftq_pc_next_pc (io_get_ftq_pc_next_pc)\n );\n PipelinedMulUnit PipelinedMulUnit (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid & io_req_bits_uop_fu_code[3]),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_rs1_data (io_req_bits_rs1_data[63:0]),\n .io_req_bits_rs2_data (io_req_bits_rs2_data[63:0]),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_valid (_PipelinedMulUnit_io_resp_valid),\n .io_resp_bits_uop_rob_idx (_PipelinedMulUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_pdst (_PipelinedMulUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_bypassable (_PipelinedMulUnit_io_resp_bits_uop_bypassable),\n .io_resp_bits_uop_is_amo (_PipelinedMulUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_stq (_PipelinedMulUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_dst_rtype (_PipelinedMulUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_data (_PipelinedMulUnit_io_resp_bits_data),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask)\n );\n IntToFPUnit IntToFPUnit (\n .clock (clock),\n .reset (reset),\n .io_req_valid (io_req_valid & io_req_bits_uop_fu_code[8]),\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc),\n .io_req_bits_uop_inst (io_req_bits_uop_inst),\n .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst),\n .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc),\n .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc),\n .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type),\n .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code),\n .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type),\n .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel),\n .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel),\n .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd),\n .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load),\n .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta),\n .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std),\n .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state),\n .io_req_bits_uop_is_br (io_req_bits_uop_is_br),\n .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr),\n .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal),\n .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag),\n .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx),\n .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst),\n .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob),\n .io_req_bits_uop_taken (io_req_bits_uop_taken),\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed),\n .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx),\n .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx),\n .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_prs1 (io_req_bits_uop_prs1),\n .io_req_bits_uop_prs2 (io_req_bits_uop_prs2),\n .io_req_bits_uop_prs3 (io_req_bits_uop_prs3),\n .io_req_bits_uop_ppred (io_req_bits_uop_ppred),\n .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy),\n .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy),\n .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy),\n .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy),\n .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst),\n .io_req_bits_uop_exception (io_req_bits_uop_exception),\n .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd),\n .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size),\n .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed),\n .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence),\n .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc),\n .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique),\n .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit),\n .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1),\n .io_req_bits_uop_ldst (io_req_bits_uop_ldst),\n .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1),\n .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2),\n .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3),\n .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype),\n .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype),\n .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en),\n .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val),\n .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single),\n .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if),\n .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if),\n .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if),\n .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if),\n .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if),\n .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc),\n .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc),\n .io_req_bits_rs1_data (io_req_bits_rs1_data),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_valid (_IntToFPUnit_io_resp_valid),\n .io_resp_bits_uop_uopc (_IntToFPUnit_io_resp_bits_uop_uopc),\n .io_resp_bits_uop_inst (_IntToFPUnit_io_resp_bits_uop_inst),\n .io_resp_bits_uop_debug_inst (_IntToFPUnit_io_resp_bits_uop_debug_inst),\n .io_resp_bits_uop_is_rvc (_IntToFPUnit_io_resp_bits_uop_is_rvc),\n .io_resp_bits_uop_debug_pc (_IntToFPUnit_io_resp_bits_uop_debug_pc),\n .io_resp_bits_uop_iq_type (_IntToFPUnit_io_resp_bits_uop_iq_type),\n .io_resp_bits_uop_fu_code (_IntToFPUnit_io_resp_bits_uop_fu_code),\n .io_resp_bits_uop_ctrl_br_type (_IntToFPUnit_io_resp_bits_uop_ctrl_br_type),\n .io_resp_bits_uop_ctrl_op1_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_op1_sel),\n .io_resp_bits_uop_ctrl_op2_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_op2_sel),\n .io_resp_bits_uop_ctrl_imm_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_imm_sel),\n .io_resp_bits_uop_ctrl_op_fcn (_IntToFPUnit_io_resp_bits_uop_ctrl_op_fcn),\n .io_resp_bits_uop_ctrl_fcn_dw (_IntToFPUnit_io_resp_bits_uop_ctrl_fcn_dw),\n .io_resp_bits_uop_ctrl_csr_cmd (_IntToFPUnit_io_resp_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_uop_ctrl_is_load (_IntToFPUnit_io_resp_bits_uop_ctrl_is_load),\n .io_resp_bits_uop_ctrl_is_sta (_IntToFPUnit_io_resp_bits_uop_ctrl_is_sta),\n .io_resp_bits_uop_ctrl_is_std (_IntToFPUnit_io_resp_bits_uop_ctrl_is_std),\n .io_resp_bits_uop_iw_state (_IntToFPUnit_io_resp_bits_uop_iw_state),\n .io_resp_bits_uop_iw_p1_poisoned (_IntToFPUnit_io_resp_bits_uop_iw_p1_poisoned),\n .io_resp_bits_uop_iw_p2_poisoned (_IntToFPUnit_io_resp_bits_uop_iw_p2_poisoned),\n .io_resp_bits_uop_is_br (_IntToFPUnit_io_resp_bits_uop_is_br),\n .io_resp_bits_uop_is_jalr (_IntToFPUnit_io_resp_bits_uop_is_jalr),\n .io_resp_bits_uop_is_jal (_IntToFPUnit_io_resp_bits_uop_is_jal),\n .io_resp_bits_uop_is_sfb (_IntToFPUnit_io_resp_bits_uop_is_sfb),\n .io_resp_bits_uop_br_mask (_IntToFPUnit_io_resp_bits_uop_br_mask),\n .io_resp_bits_uop_br_tag (_IntToFPUnit_io_resp_bits_uop_br_tag),\n .io_resp_bits_uop_ftq_idx (_IntToFPUnit_io_resp_bits_uop_ftq_idx),\n .io_resp_bits_uop_edge_inst (_IntToFPUnit_io_resp_bits_uop_edge_inst),\n .io_resp_bits_uop_pc_lob (_IntToFPUnit_io_resp_bits_uop_pc_lob),\n .io_resp_bits_uop_taken (_IntToFPUnit_io_resp_bits_uop_taken),\n .io_resp_bits_uop_imm_packed (_IntToFPUnit_io_resp_bits_uop_imm_packed),\n .io_resp_bits_uop_csr_addr (_IntToFPUnit_io_resp_bits_uop_csr_addr),\n .io_resp_bits_uop_rob_idx (_IntToFPUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_ldq_idx (_IntToFPUnit_io_resp_bits_uop_ldq_idx),\n .io_resp_bits_uop_stq_idx (_IntToFPUnit_io_resp_bits_uop_stq_idx),\n .io_resp_bits_uop_rxq_idx (_IntToFPUnit_io_resp_bits_uop_rxq_idx),\n .io_resp_bits_uop_pdst (_IntToFPUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_prs1 (_IntToFPUnit_io_resp_bits_uop_prs1),\n .io_resp_bits_uop_prs2 (_IntToFPUnit_io_resp_bits_uop_prs2),\n .io_resp_bits_uop_prs3 (_IntToFPUnit_io_resp_bits_uop_prs3),\n .io_resp_bits_uop_ppred (_IntToFPUnit_io_resp_bits_uop_ppred),\n .io_resp_bits_uop_prs1_busy (_IntToFPUnit_io_resp_bits_uop_prs1_busy),\n .io_resp_bits_uop_prs2_busy (_IntToFPUnit_io_resp_bits_uop_prs2_busy),\n .io_resp_bits_uop_prs3_busy (_IntToFPUnit_io_resp_bits_uop_prs3_busy),\n .io_resp_bits_uop_ppred_busy (_IntToFPUnit_io_resp_bits_uop_ppred_busy),\n .io_resp_bits_uop_stale_pdst (_IntToFPUnit_io_resp_bits_uop_stale_pdst),\n .io_resp_bits_uop_exception (_IntToFPUnit_io_resp_bits_uop_exception),\n .io_resp_bits_uop_exc_cause (_IntToFPUnit_io_resp_bits_uop_exc_cause),\n .io_resp_bits_uop_bypassable (_IntToFPUnit_io_resp_bits_uop_bypassable),\n .io_resp_bits_uop_mem_cmd (_IntToFPUnit_io_resp_bits_uop_mem_cmd),\n .io_resp_bits_uop_mem_size (_IntToFPUnit_io_resp_bits_uop_mem_size),\n .io_resp_bits_uop_mem_signed (_IntToFPUnit_io_resp_bits_uop_mem_signed),\n .io_resp_bits_uop_is_fence (_IntToFPUnit_io_resp_bits_uop_is_fence),\n .io_resp_bits_uop_is_fencei (_IntToFPUnit_io_resp_bits_uop_is_fencei),\n .io_resp_bits_uop_is_amo (_IntToFPUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_ldq (_IntToFPUnit_io_resp_bits_uop_uses_ldq),\n .io_resp_bits_uop_uses_stq (_IntToFPUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_is_sys_pc2epc (_IntToFPUnit_io_resp_bits_uop_is_sys_pc2epc),\n .io_resp_bits_uop_is_unique (_IntToFPUnit_io_resp_bits_uop_is_unique),\n .io_resp_bits_uop_flush_on_commit (_IntToFPUnit_io_resp_bits_uop_flush_on_commit),\n .io_resp_bits_uop_ldst_is_rs1 (_IntToFPUnit_io_resp_bits_uop_ldst_is_rs1),\n .io_resp_bits_uop_ldst (_IntToFPUnit_io_resp_bits_uop_ldst),\n .io_resp_bits_uop_lrs1 (_IntToFPUnit_io_resp_bits_uop_lrs1),\n .io_resp_bits_uop_lrs2 (_IntToFPUnit_io_resp_bits_uop_lrs2),\n .io_resp_bits_uop_lrs3 (_IntToFPUnit_io_resp_bits_uop_lrs3),\n .io_resp_bits_uop_ldst_val (_IntToFPUnit_io_resp_bits_uop_ldst_val),\n .io_resp_bits_uop_dst_rtype (_IntToFPUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_uop_lrs1_rtype (_IntToFPUnit_io_resp_bits_uop_lrs1_rtype),\n .io_resp_bits_uop_lrs2_rtype (_IntToFPUnit_io_resp_bits_uop_lrs2_rtype),\n .io_resp_bits_uop_frs3_en (_IntToFPUnit_io_resp_bits_uop_frs3_en),\n .io_resp_bits_uop_fp_val (_IntToFPUnit_io_resp_bits_uop_fp_val),\n .io_resp_bits_uop_fp_single (_IntToFPUnit_io_resp_bits_uop_fp_single),\n .io_resp_bits_uop_xcpt_pf_if (_IntToFPUnit_io_resp_bits_uop_xcpt_pf_if),\n .io_resp_bits_uop_xcpt_ae_if (_IntToFPUnit_io_resp_bits_uop_xcpt_ae_if),\n .io_resp_bits_uop_xcpt_ma_if (_IntToFPUnit_io_resp_bits_uop_xcpt_ma_if),\n .io_resp_bits_uop_bp_debug_if (_IntToFPUnit_io_resp_bits_uop_bp_debug_if),\n .io_resp_bits_uop_bp_xcpt_if (_IntToFPUnit_io_resp_bits_uop_bp_xcpt_if),\n .io_resp_bits_uop_debug_fsrc (_IntToFPUnit_io_resp_bits_uop_debug_fsrc),\n .io_resp_bits_uop_debug_tsrc (_IntToFPUnit_io_resp_bits_uop_debug_tsrc),\n .io_resp_bits_data (_IntToFPUnit_io_resp_bits_data),\n .io_resp_bits_fflags_valid (_IntToFPUnit_io_resp_bits_fflags_valid),\n .io_resp_bits_fflags_bits_uop_uopc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uopc),\n .io_resp_bits_fflags_bits_uop_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_inst),\n .io_resp_bits_fflags_bits_uop_debug_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_inst),\n .io_resp_bits_fflags_bits_uop_is_rvc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_rvc),\n .io_resp_bits_fflags_bits_uop_debug_pc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_pc),\n .io_resp_bits_fflags_bits_uop_iq_type (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iq_type),\n .io_resp_bits_fflags_bits_uop_fu_code (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fu_code),\n .io_resp_bits_fflags_bits_uop_ctrl_br_type (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),\n .io_resp_bits_fflags_bits_uop_ctrl_op1_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_op2_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_imm_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),\n .io_resp_bits_fflags_bits_uop_ctrl_op_fcn (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),\n .io_resp_bits_fflags_bits_uop_ctrl_fcn_dw (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),\n .io_resp_bits_fflags_bits_uop_ctrl_csr_cmd (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),\n .io_resp_bits_fflags_bits_uop_ctrl_is_load (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),\n .io_resp_bits_fflags_bits_uop_ctrl_is_sta (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),\n .io_resp_bits_fflags_bits_uop_ctrl_is_std (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),\n .io_resp_bits_fflags_bits_uop_iw_state (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_state),\n .io_resp_bits_fflags_bits_uop_iw_p1_poisoned (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),\n .io_resp_bits_fflags_bits_uop_iw_p2_poisoned (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),\n .io_resp_bits_fflags_bits_uop_is_br (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_br),\n .io_resp_bits_fflags_bits_uop_is_jalr (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jalr),\n .io_resp_bits_fflags_bits_uop_is_jal (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jal),\n .io_resp_bits_fflags_bits_uop_is_sfb (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sfb),\n .io_resp_bits_fflags_bits_uop_br_mask (_IntToFPUnit_io_resp_bits_fflags_bits_uop_br_mask),\n .io_resp_bits_fflags_bits_uop_br_tag (_IntToFPUnit_io_resp_bits_fflags_bits_uop_br_tag),\n .io_resp_bits_fflags_bits_uop_ftq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ftq_idx),\n .io_resp_bits_fflags_bits_uop_edge_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_edge_inst),\n .io_resp_bits_fflags_bits_uop_pc_lob (_IntToFPUnit_io_resp_bits_fflags_bits_uop_pc_lob),\n .io_resp_bits_fflags_bits_uop_taken (_IntToFPUnit_io_resp_bits_fflags_bits_uop_taken),\n .io_resp_bits_fflags_bits_uop_imm_packed (_IntToFPUnit_io_resp_bits_fflags_bits_uop_imm_packed),\n .io_resp_bits_fflags_bits_uop_csr_addr (_IntToFPUnit_io_resp_bits_fflags_bits_uop_csr_addr),\n .io_resp_bits_fflags_bits_uop_rob_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_rob_idx),\n .io_resp_bits_fflags_bits_uop_ldq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldq_idx),\n .io_resp_bits_fflags_bits_uop_stq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_stq_idx),\n .io_resp_bits_fflags_bits_uop_rxq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_rxq_idx),\n .io_resp_bits_fflags_bits_uop_pdst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_pdst),\n .io_resp_bits_fflags_bits_uop_prs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1),\n .io_resp_bits_fflags_bits_uop_prs2 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2),\n .io_resp_bits_fflags_bits_uop_prs3 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3),\n .io_resp_bits_fflags_bits_uop_ppred (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred),\n .io_resp_bits_fflags_bits_uop_prs1_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1_busy),\n .io_resp_bits_fflags_bits_uop_prs2_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2_busy),\n .io_resp_bits_fflags_bits_uop_prs3_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3_busy),\n .io_resp_bits_fflags_bits_uop_ppred_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred_busy),\n .io_resp_bits_fflags_bits_uop_stale_pdst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_stale_pdst),\n .io_resp_bits_fflags_bits_uop_exception (_IntToFPUnit_io_resp_bits_fflags_bits_uop_exception),\n .io_resp_bits_fflags_bits_uop_exc_cause (_IntToFPUnit_io_resp_bits_fflags_bits_uop_exc_cause),\n .io_resp_bits_fflags_bits_uop_bypassable (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bypassable),\n .io_resp_bits_fflags_bits_uop_mem_cmd (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_cmd),\n .io_resp_bits_fflags_bits_uop_mem_size (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_size),\n .io_resp_bits_fflags_bits_uop_mem_signed (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_signed),\n .io_resp_bits_fflags_bits_uop_is_fence (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fence),\n .io_resp_bits_fflags_bits_uop_is_fencei (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fencei),\n .io_resp_bits_fflags_bits_uop_is_amo (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_amo),\n .io_resp_bits_fflags_bits_uop_uses_ldq (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_ldq),\n .io_resp_bits_fflags_bits_uop_uses_stq (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_stq),\n .io_resp_bits_fflags_bits_uop_is_sys_pc2epc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),\n .io_resp_bits_fflags_bits_uop_is_unique (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_unique),\n .io_resp_bits_fflags_bits_uop_flush_on_commit (_IntToFPUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),\n .io_resp_bits_fflags_bits_uop_ldst_is_rs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),\n .io_resp_bits_fflags_bits_uop_ldst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst),\n .io_resp_bits_fflags_bits_uop_lrs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1),\n .io_resp_bits_fflags_bits_uop_lrs2 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2),\n .io_resp_bits_fflags_bits_uop_lrs3 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs3),\n .io_resp_bits_fflags_bits_uop_ldst_val (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_val),\n .io_resp_bits_fflags_bits_uop_dst_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_dst_rtype),\n .io_resp_bits_fflags_bits_uop_lrs1_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),\n .io_resp_bits_fflags_bits_uop_lrs2_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),\n .io_resp_bits_fflags_bits_uop_frs3_en (_IntToFPUnit_io_resp_bits_fflags_bits_uop_frs3_en),\n .io_resp_bits_fflags_bits_uop_fp_val (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_val),\n .io_resp_bits_fflags_bits_uop_fp_single (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_single),\n .io_resp_bits_fflags_bits_uop_xcpt_pf_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),\n .io_resp_bits_fflags_bits_uop_xcpt_ae_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),\n .io_resp_bits_fflags_bits_uop_xcpt_ma_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),\n .io_resp_bits_fflags_bits_uop_bp_debug_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),\n .io_resp_bits_fflags_bits_uop_bp_xcpt_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),\n .io_resp_bits_fflags_bits_uop_debug_fsrc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),\n .io_resp_bits_fflags_bits_uop_debug_tsrc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),\n .io_resp_bits_fflags_bits_flags (_IntToFPUnit_io_resp_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_fcsr_rm (io_fcsr_rm)\n );\n BranchKillableQueue_3 queue (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (_queue_io_enq_ready),\n .io_enq_valid (_IntToFPUnit_io_resp_valid),\n .io_enq_bits_uop_uopc (_IntToFPUnit_io_resp_bits_uop_uopc),\n .io_enq_bits_uop_inst (_IntToFPUnit_io_resp_bits_uop_inst),\n .io_enq_bits_uop_debug_inst (_IntToFPUnit_io_resp_bits_uop_debug_inst),\n .io_enq_bits_uop_is_rvc (_IntToFPUnit_io_resp_bits_uop_is_rvc),\n .io_enq_bits_uop_debug_pc (_IntToFPUnit_io_resp_bits_uop_debug_pc),\n .io_enq_bits_uop_iq_type (_IntToFPUnit_io_resp_bits_uop_iq_type),\n .io_enq_bits_uop_fu_code (_IntToFPUnit_io_resp_bits_uop_fu_code),\n .io_enq_bits_uop_ctrl_br_type (_IntToFPUnit_io_resp_bits_uop_ctrl_br_type),\n .io_enq_bits_uop_ctrl_op1_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_op1_sel),\n .io_enq_bits_uop_ctrl_op2_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_op2_sel),\n .io_enq_bits_uop_ctrl_imm_sel (_IntToFPUnit_io_resp_bits_uop_ctrl_imm_sel),\n .io_enq_bits_uop_ctrl_op_fcn (_IntToFPUnit_io_resp_bits_uop_ctrl_op_fcn),\n .io_enq_bits_uop_ctrl_fcn_dw (_IntToFPUnit_io_resp_bits_uop_ctrl_fcn_dw),\n .io_enq_bits_uop_ctrl_csr_cmd (_IntToFPUnit_io_resp_bits_uop_ctrl_csr_cmd),\n .io_enq_bits_uop_ctrl_is_load (_IntToFPUnit_io_resp_bits_uop_ctrl_is_load),\n .io_enq_bits_uop_ctrl_is_sta (_IntToFPUnit_io_resp_bits_uop_ctrl_is_sta),\n .io_enq_bits_uop_ctrl_is_std (_IntToFPUnit_io_resp_bits_uop_ctrl_is_std),\n .io_enq_bits_uop_iw_state (_IntToFPUnit_io_resp_bits_uop_iw_state),\n .io_enq_bits_uop_iw_p1_poisoned (_IntToFPUnit_io_resp_bits_uop_iw_p1_poisoned),\n .io_enq_bits_uop_iw_p2_poisoned (_IntToFPUnit_io_resp_bits_uop_iw_p2_poisoned),\n .io_enq_bits_uop_is_br (_IntToFPUnit_io_resp_bits_uop_is_br),\n .io_enq_bits_uop_is_jalr (_IntToFPUnit_io_resp_bits_uop_is_jalr),\n .io_enq_bits_uop_is_jal (_IntToFPUnit_io_resp_bits_uop_is_jal),\n .io_enq_bits_uop_is_sfb (_IntToFPUnit_io_resp_bits_uop_is_sfb),\n .io_enq_bits_uop_br_mask (_IntToFPUnit_io_resp_bits_uop_br_mask),\n .io_enq_bits_uop_br_tag (_IntToFPUnit_io_resp_bits_uop_br_tag),\n .io_enq_bits_uop_ftq_idx (_IntToFPUnit_io_resp_bits_uop_ftq_idx),\n .io_enq_bits_uop_edge_inst (_IntToFPUnit_io_resp_bits_uop_edge_inst),\n .io_enq_bits_uop_pc_lob (_IntToFPUnit_io_resp_bits_uop_pc_lob),\n .io_enq_bits_uop_taken (_IntToFPUnit_io_resp_bits_uop_taken),\n .io_enq_bits_uop_imm_packed (_IntToFPUnit_io_resp_bits_uop_imm_packed),\n .io_enq_bits_uop_csr_addr (_IntToFPUnit_io_resp_bits_uop_csr_addr),\n .io_enq_bits_uop_rob_idx (_IntToFPUnit_io_resp_bits_uop_rob_idx),\n .io_enq_bits_uop_ldq_idx (_IntToFPUnit_io_resp_bits_uop_ldq_idx),\n .io_enq_bits_uop_stq_idx (_IntToFPUnit_io_resp_bits_uop_stq_idx),\n .io_enq_bits_uop_rxq_idx (_IntToFPUnit_io_resp_bits_uop_rxq_idx),\n .io_enq_bits_uop_pdst (_IntToFPUnit_io_resp_bits_uop_pdst),\n .io_enq_bits_uop_prs1 (_IntToFPUnit_io_resp_bits_uop_prs1),\n .io_enq_bits_uop_prs2 (_IntToFPUnit_io_resp_bits_uop_prs2),\n .io_enq_bits_uop_prs3 (_IntToFPUnit_io_resp_bits_uop_prs3),\n .io_enq_bits_uop_ppred (_IntToFPUnit_io_resp_bits_uop_ppred),\n .io_enq_bits_uop_prs1_busy (_IntToFPUnit_io_resp_bits_uop_prs1_busy),\n .io_enq_bits_uop_prs2_busy (_IntToFPUnit_io_resp_bits_uop_prs2_busy),\n .io_enq_bits_uop_prs3_busy (_IntToFPUnit_io_resp_bits_uop_prs3_busy),\n .io_enq_bits_uop_ppred_busy (_IntToFPUnit_io_resp_bits_uop_ppred_busy),\n .io_enq_bits_uop_stale_pdst (_IntToFPUnit_io_resp_bits_uop_stale_pdst),\n .io_enq_bits_uop_exception (_IntToFPUnit_io_resp_bits_uop_exception),\n .io_enq_bits_uop_exc_cause (_IntToFPUnit_io_resp_bits_uop_exc_cause),\n .io_enq_bits_uop_bypassable (_IntToFPUnit_io_resp_bits_uop_bypassable),\n .io_enq_bits_uop_mem_cmd (_IntToFPUnit_io_resp_bits_uop_mem_cmd),\n .io_enq_bits_uop_mem_size (_IntToFPUnit_io_resp_bits_uop_mem_size),\n .io_enq_bits_uop_mem_signed (_IntToFPUnit_io_resp_bits_uop_mem_signed),\n .io_enq_bits_uop_is_fence (_IntToFPUnit_io_resp_bits_uop_is_fence),\n .io_enq_bits_uop_is_fencei (_IntToFPUnit_io_resp_bits_uop_is_fencei),\n .io_enq_bits_uop_is_amo (_IntToFPUnit_io_resp_bits_uop_is_amo),\n .io_enq_bits_uop_uses_ldq (_IntToFPUnit_io_resp_bits_uop_uses_ldq),\n .io_enq_bits_uop_uses_stq (_IntToFPUnit_io_resp_bits_uop_uses_stq),\n .io_enq_bits_uop_is_sys_pc2epc (_IntToFPUnit_io_resp_bits_uop_is_sys_pc2epc),\n .io_enq_bits_uop_is_unique (_IntToFPUnit_io_resp_bits_uop_is_unique),\n .io_enq_bits_uop_flush_on_commit (_IntToFPUnit_io_resp_bits_uop_flush_on_commit),\n .io_enq_bits_uop_ldst_is_rs1 (_IntToFPUnit_io_resp_bits_uop_ldst_is_rs1),\n .io_enq_bits_uop_ldst (_IntToFPUnit_io_resp_bits_uop_ldst),\n .io_enq_bits_uop_lrs1 (_IntToFPUnit_io_resp_bits_uop_lrs1),\n .io_enq_bits_uop_lrs2 (_IntToFPUnit_io_resp_bits_uop_lrs2),\n .io_enq_bits_uop_lrs3 (_IntToFPUnit_io_resp_bits_uop_lrs3),\n .io_enq_bits_uop_ldst_val (_IntToFPUnit_io_resp_bits_uop_ldst_val),\n .io_enq_bits_uop_dst_rtype (_IntToFPUnit_io_resp_bits_uop_dst_rtype),\n .io_enq_bits_uop_lrs1_rtype (_IntToFPUnit_io_resp_bits_uop_lrs1_rtype),\n .io_enq_bits_uop_lrs2_rtype (_IntToFPUnit_io_resp_bits_uop_lrs2_rtype),\n .io_enq_bits_uop_frs3_en (_IntToFPUnit_io_resp_bits_uop_frs3_en),\n .io_enq_bits_uop_fp_val (_IntToFPUnit_io_resp_bits_uop_fp_val),\n .io_enq_bits_uop_fp_single (_IntToFPUnit_io_resp_bits_uop_fp_single),\n .io_enq_bits_uop_xcpt_pf_if (_IntToFPUnit_io_resp_bits_uop_xcpt_pf_if),\n .io_enq_bits_uop_xcpt_ae_if (_IntToFPUnit_io_resp_bits_uop_xcpt_ae_if),\n .io_enq_bits_uop_xcpt_ma_if (_IntToFPUnit_io_resp_bits_uop_xcpt_ma_if),\n .io_enq_bits_uop_bp_debug_if (_IntToFPUnit_io_resp_bits_uop_bp_debug_if),\n .io_enq_bits_uop_bp_xcpt_if (_IntToFPUnit_io_resp_bits_uop_bp_xcpt_if),\n .io_enq_bits_uop_debug_fsrc (_IntToFPUnit_io_resp_bits_uop_debug_fsrc),\n .io_enq_bits_uop_debug_tsrc (_IntToFPUnit_io_resp_bits_uop_debug_tsrc),\n .io_enq_bits_data (_IntToFPUnit_io_resp_bits_data),\n .io_enq_bits_fflags_valid (_IntToFPUnit_io_resp_bits_fflags_valid),\n .io_enq_bits_fflags_bits_uop_uopc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uopc),\n .io_enq_bits_fflags_bits_uop_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_inst),\n .io_enq_bits_fflags_bits_uop_debug_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_inst),\n .io_enq_bits_fflags_bits_uop_is_rvc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_rvc),\n .io_enq_bits_fflags_bits_uop_debug_pc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_pc),\n .io_enq_bits_fflags_bits_uop_iq_type (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iq_type),\n .io_enq_bits_fflags_bits_uop_fu_code (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fu_code),\n .io_enq_bits_fflags_bits_uop_ctrl_br_type (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_br_type),\n .io_enq_bits_fflags_bits_uop_ctrl_op1_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op1_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_op2_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op2_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_imm_sel (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_imm_sel),\n .io_enq_bits_fflags_bits_uop_ctrl_op_fcn (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_op_fcn),\n .io_enq_bits_fflags_bits_uop_ctrl_fcn_dw (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_fcn_dw),\n .io_enq_bits_fflags_bits_uop_ctrl_csr_cmd (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_csr_cmd),\n .io_enq_bits_fflags_bits_uop_ctrl_is_load (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_load),\n .io_enq_bits_fflags_bits_uop_ctrl_is_sta (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_sta),\n .io_enq_bits_fflags_bits_uop_ctrl_is_std (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ctrl_is_std),\n .io_enq_bits_fflags_bits_uop_iw_state (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_state),\n .io_enq_bits_fflags_bits_uop_iw_p1_poisoned (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p1_poisoned),\n .io_enq_bits_fflags_bits_uop_iw_p2_poisoned (_IntToFPUnit_io_resp_bits_fflags_bits_uop_iw_p2_poisoned),\n .io_enq_bits_fflags_bits_uop_is_br (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_br),\n .io_enq_bits_fflags_bits_uop_is_jalr (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jalr),\n .io_enq_bits_fflags_bits_uop_is_jal (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_jal),\n .io_enq_bits_fflags_bits_uop_is_sfb (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sfb),\n .io_enq_bits_fflags_bits_uop_br_mask (_IntToFPUnit_io_resp_bits_fflags_bits_uop_br_mask),\n .io_enq_bits_fflags_bits_uop_br_tag (_IntToFPUnit_io_resp_bits_fflags_bits_uop_br_tag),\n .io_enq_bits_fflags_bits_uop_ftq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ftq_idx),\n .io_enq_bits_fflags_bits_uop_edge_inst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_edge_inst),\n .io_enq_bits_fflags_bits_uop_pc_lob (_IntToFPUnit_io_resp_bits_fflags_bits_uop_pc_lob),\n .io_enq_bits_fflags_bits_uop_taken (_IntToFPUnit_io_resp_bits_fflags_bits_uop_taken),\n .io_enq_bits_fflags_bits_uop_imm_packed (_IntToFPUnit_io_resp_bits_fflags_bits_uop_imm_packed),\n .io_enq_bits_fflags_bits_uop_csr_addr (_IntToFPUnit_io_resp_bits_fflags_bits_uop_csr_addr),\n .io_enq_bits_fflags_bits_uop_rob_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_rob_idx),\n .io_enq_bits_fflags_bits_uop_ldq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldq_idx),\n .io_enq_bits_fflags_bits_uop_stq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_stq_idx),\n .io_enq_bits_fflags_bits_uop_rxq_idx (_IntToFPUnit_io_resp_bits_fflags_bits_uop_rxq_idx),\n .io_enq_bits_fflags_bits_uop_pdst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_pdst),\n .io_enq_bits_fflags_bits_uop_prs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1),\n .io_enq_bits_fflags_bits_uop_prs2 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2),\n .io_enq_bits_fflags_bits_uop_prs3 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3),\n .io_enq_bits_fflags_bits_uop_ppred (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred),\n .io_enq_bits_fflags_bits_uop_prs1_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs1_busy),\n .io_enq_bits_fflags_bits_uop_prs2_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs2_busy),\n .io_enq_bits_fflags_bits_uop_prs3_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_prs3_busy),\n .io_enq_bits_fflags_bits_uop_ppred_busy (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ppred_busy),\n .io_enq_bits_fflags_bits_uop_stale_pdst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_stale_pdst),\n .io_enq_bits_fflags_bits_uop_exception (_IntToFPUnit_io_resp_bits_fflags_bits_uop_exception),\n .io_enq_bits_fflags_bits_uop_exc_cause (_IntToFPUnit_io_resp_bits_fflags_bits_uop_exc_cause),\n .io_enq_bits_fflags_bits_uop_bypassable (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bypassable),\n .io_enq_bits_fflags_bits_uop_mem_cmd (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_cmd),\n .io_enq_bits_fflags_bits_uop_mem_size (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_size),\n .io_enq_bits_fflags_bits_uop_mem_signed (_IntToFPUnit_io_resp_bits_fflags_bits_uop_mem_signed),\n .io_enq_bits_fflags_bits_uop_is_fence (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fence),\n .io_enq_bits_fflags_bits_uop_is_fencei (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_fencei),\n .io_enq_bits_fflags_bits_uop_is_amo (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_amo),\n .io_enq_bits_fflags_bits_uop_uses_ldq (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_ldq),\n .io_enq_bits_fflags_bits_uop_uses_stq (_IntToFPUnit_io_resp_bits_fflags_bits_uop_uses_stq),\n .io_enq_bits_fflags_bits_uop_is_sys_pc2epc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_sys_pc2epc),\n .io_enq_bits_fflags_bits_uop_is_unique (_IntToFPUnit_io_resp_bits_fflags_bits_uop_is_unique),\n .io_enq_bits_fflags_bits_uop_flush_on_commit (_IntToFPUnit_io_resp_bits_fflags_bits_uop_flush_on_commit),\n .io_enq_bits_fflags_bits_uop_ldst_is_rs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_is_rs1),\n .io_enq_bits_fflags_bits_uop_ldst (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst),\n .io_enq_bits_fflags_bits_uop_lrs1 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1),\n .io_enq_bits_fflags_bits_uop_lrs2 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2),\n .io_enq_bits_fflags_bits_uop_lrs3 (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs3),\n .io_enq_bits_fflags_bits_uop_ldst_val (_IntToFPUnit_io_resp_bits_fflags_bits_uop_ldst_val),\n .io_enq_bits_fflags_bits_uop_dst_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_dst_rtype),\n .io_enq_bits_fflags_bits_uop_lrs1_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs1_rtype),\n .io_enq_bits_fflags_bits_uop_lrs2_rtype (_IntToFPUnit_io_resp_bits_fflags_bits_uop_lrs2_rtype),\n .io_enq_bits_fflags_bits_uop_frs3_en (_IntToFPUnit_io_resp_bits_fflags_bits_uop_frs3_en),\n .io_enq_bits_fflags_bits_uop_fp_val (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_val),\n .io_enq_bits_fflags_bits_uop_fp_single (_IntToFPUnit_io_resp_bits_fflags_bits_uop_fp_single),\n .io_enq_bits_fflags_bits_uop_xcpt_pf_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_pf_if),\n .io_enq_bits_fflags_bits_uop_xcpt_ae_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ae_if),\n .io_enq_bits_fflags_bits_uop_xcpt_ma_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_xcpt_ma_if),\n .io_enq_bits_fflags_bits_uop_bp_debug_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_debug_if),\n .io_enq_bits_fflags_bits_uop_bp_xcpt_if (_IntToFPUnit_io_resp_bits_fflags_bits_uop_bp_xcpt_if),\n .io_enq_bits_fflags_bits_uop_debug_fsrc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_fsrc),\n .io_enq_bits_fflags_bits_uop_debug_tsrc (_IntToFPUnit_io_resp_bits_fflags_bits_uop_debug_tsrc),\n .io_enq_bits_fflags_bits_flags (_IntToFPUnit_io_resp_bits_fflags_bits_flags),\n .io_deq_ready (io_ll_fresp_ready),\n .io_deq_valid (io_ll_fresp_valid),\n .io_deq_bits_uop_uopc (io_ll_fresp_bits_uop_uopc),\n .io_deq_bits_uop_br_mask (io_ll_fresp_bits_uop_br_mask),\n .io_deq_bits_uop_rob_idx (io_ll_fresp_bits_uop_rob_idx),\n .io_deq_bits_uop_stq_idx (io_ll_fresp_bits_uop_stq_idx),\n .io_deq_bits_uop_pdst (io_ll_fresp_bits_uop_pdst),\n .io_deq_bits_uop_is_amo (io_ll_fresp_bits_uop_is_amo),\n .io_deq_bits_uop_uses_stq (io_ll_fresp_bits_uop_uses_stq),\n .io_deq_bits_uop_dst_rtype (io_ll_fresp_bits_uop_dst_rtype),\n .io_deq_bits_uop_fp_val (io_ll_fresp_bits_uop_fp_val),\n .io_deq_bits_data (io_ll_fresp_bits_data),\n .io_deq_bits_predicated (io_ll_fresp_bits_predicated),\n .io_deq_bits_fflags_valid (io_ll_fresp_bits_fflags_valid),\n .io_deq_bits_fflags_bits_uop_rob_idx (io_ll_fresp_bits_fflags_bits_uop_rob_idx),\n .io_deq_bits_fflags_bits_flags (io_ll_fresp_bits_fflags_bits_flags),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask),\n .io_flush (io_req_bits_kill),\n .io_empty (_queue_io_empty)\n );\n DivUnit DivUnit (\n .clock (clock),\n .reset (reset),\n .io_req_ready (_DivUnit_io_req_ready),\n .io_req_valid (io_req_valid & io_req_bits_uop_fu_code[4]),\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn),\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw),\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask),\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx),\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst),\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable),\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo),\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq),\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype),\n .io_req_bits_rs1_data (io_req_bits_rs1_data[63:0]),\n .io_req_bits_rs2_data (io_req_bits_rs2_data[63:0]),\n .io_req_bits_kill (io_req_bits_kill),\n .io_resp_ready (~_io_iresp_valid_T),\n .io_resp_valid (_DivUnit_io_resp_valid),\n .io_resp_bits_uop_rob_idx (_DivUnit_io_resp_bits_uop_rob_idx),\n .io_resp_bits_uop_pdst (_DivUnit_io_resp_bits_uop_pdst),\n .io_resp_bits_uop_bypassable (_DivUnit_io_resp_bits_uop_bypassable),\n .io_resp_bits_uop_is_amo (_DivUnit_io_resp_bits_uop_is_amo),\n .io_resp_bits_uop_uses_stq (_DivUnit_io_resp_bits_uop_uses_stq),\n .io_resp_bits_uop_dst_rtype (_DivUnit_io_resp_bits_uop_dst_rtype),\n .io_resp_bits_data (_DivUnit_io_resp_bits_data),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask),\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask)\n );\n assign io_fu_types = {1'h0, _queue_io_empty, 3'h1, ~div_busy, 4'hB};\n assign io_iresp_valid = _io_iresp_valid_T | _DivUnit_io_resp_valid;\n assign io_iresp_bits_uop_csr_addr = _ALUUnit_io_resp_bits_uop_imm_packed[19:8];\n assign io_iresp_bits_uop_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_rob_idx : _DivUnit_io_resp_bits_uop_rob_idx;\n assign io_iresp_bits_uop_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_pdst : _DivUnit_io_resp_bits_uop_pdst;\n assign io_iresp_bits_uop_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_bypassable : _DivUnit_io_resp_bits_uop_bypassable;\n assign io_iresp_bits_uop_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_is_amo : _DivUnit_io_resp_bits_uop_is_amo;\n assign io_iresp_bits_uop_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_uses_stq : _DivUnit_io_resp_bits_uop_uses_stq;\n assign io_iresp_bits_uop_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_uop_dst_rtype : _DivUnit_io_resp_bits_uop_dst_rtype;\n assign io_iresp_bits_data = {1'h0, _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _PipelinedMulUnit_io_resp_valid ? _PipelinedMulUnit_io_resp_bits_data : _DivUnit_io_resp_bits_data};\n assign io_bypass_0_bits_data = {1'h0, _ALUUnit_io_bypass_0_bits_data};\n assign io_bypass_1_bits_data = {1'h0, _ALUUnit_io_bypass_1_bits_data};\n assign io_bypass_2_bits_data = {1'h0, _ALUUnit_io_bypass_2_bits_data};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket.Instructions32\nimport freechips.rocketchip.rocket.CustomInstructions._\nimport freechips.rocketchip.rocket.RVCExpander\nimport freechips.rocketchip.rocket.{CSR,Causes}\nimport freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf}\n\nimport FUConstants._\nimport boom.v3.common._\nimport boom.v3.util._\n\n// scalastyle:off\n/**\n * Abstract trait giving defaults and other relevant values to different Decode constants/\n */\nabstract trait DecodeConstants\n extends freechips.rocketchip.rocket.constants.ScalarOpConstants\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val xpr64 = Y // TODO inform this from xLen\n val DC2 = BitPat.dontCare(2) // Makes the listing below more readable\n def decode_default: List[BitPat] =\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n List(N, N, X, uopX , IQT_INT, FU_X , RT_X , DC2 ,DC2 ,X, IS_X, X, X, X, X, N, M_X, DC2, X, X, N, N, X, CSR.X)\n\n val table: Array[(BitPat, List[BitPat])]\n}\n// scalastyle:on\n\n/**\n * Decoded control signals\n */\nclass CtrlSigs extends Bundle\n{\n val legal = Bool()\n val fp_val = Bool()\n val fp_single = Bool()\n val uopc = UInt(UOPC_SZ.W)\n val iq_type = UInt(IQT_SZ.W)\n val fu_code = UInt(FUC_SZ.W)\n val dst_type = UInt(2.W)\n val rs1_type = UInt(2.W)\n val rs2_type = UInt(2.W)\n val frs3_en = Bool()\n val imm_sel = UInt(IS_X.getWidth.W)\n val uses_ldq = Bool()\n val uses_stq = Bool()\n val is_amo = Bool()\n val is_fence = Bool()\n val is_fencei = Bool()\n val mem_cmd = UInt(freechips.rocketchip.rocket.M_SZ.W)\n val wakeup_delay = UInt(2.W)\n val bypassable = Bool()\n val is_br = Bool()\n val is_sys_pc2epc = Bool()\n val inst_unique = Bool()\n val flush_on_commit = Bool()\n val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)\n val rocc = Bool()\n\n def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]) = {\n val decoder = freechips.rocketchip.rocket.DecodeLogic(inst, XDecode.decode_default, table)\n val sigs =\n Seq(legal, fp_val, fp_single, uopc, iq_type, fu_code, dst_type, rs1_type,\n rs2_type, frs3_en, imm_sel, uses_ldq, uses_stq, is_amo,\n is_fence, is_fencei, mem_cmd, wakeup_delay, bypassable,\n is_br, is_sys_pc2epc, inst_unique, flush_on_commit, csr_cmd)\n sigs zip decoder map {case(s,d) => s := d}\n rocc := false.B\n this\n }\n}\n\n// scalastyle:off\n/**\n * Decode constants for RV32\n */\nobject X32Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n Instructions32.SLLI ->\n List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRLI ->\n List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n Instructions32.SRAI ->\n List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Decode constants for RV64\n */\nobject X64Decode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LD -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LWU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n SD -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n SLLI -> List(Y, N, X, uopSLLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLI -> List(Y, N, X, uopSRLI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAI -> List(Y, N, X, uopSRAI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDIW -> List(Y, N, X, uopADDIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLIW -> List(Y, N, X, uopSLLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAIW -> List(Y, N, X, uopSRAIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLIW -> List(Y, N, X, uopSRLIW, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDW -> List(Y, N, X, uopADDW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUBW -> List(Y, N, X, uopSUBW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLLW -> List(Y, N, X, uopSLLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRAW -> List(Y, N, X, uopSRAW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRLW -> List(Y, N, X, uopSRLW , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * Overall Decode constants\n */\nobject XDecode extends DecodeConstants\n{\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | |\n LW -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LH -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LHU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LB -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n LBU -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM , RT_FIX, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 3.U, N, N, N, N, N, CSR.N),\n\n SW -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SH -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n SB -> List(Y, N, X, uopSTA , IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n LUI -> List(Y, N, X, uopLUI , IQT_INT, FU_ALU , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n ADDI -> List(Y, N, X, uopADDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ANDI -> List(Y, N, X, uopANDI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ORI -> List(Y, N, X, uopORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XORI -> List(Y, N, X, uopXORI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTI -> List(Y, N, X, uopSLTI , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTIU -> List(Y, N, X, uopSLTIU, IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n SLL -> List(Y, N, X, uopSLL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n ADD -> List(Y, N, X, uopADD , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SUB -> List(Y, N, X, uopSUB , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLT -> List(Y, N, X, uopSLT , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SLTU -> List(Y, N, X, uopSLTU , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n AND -> List(Y, N, X, uopAND , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n OR -> List(Y, N, X, uopOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n XOR -> List(Y, N, X, uopXOR , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRA -> List(Y, N, X, uopSRA , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_I, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n SRL -> List(Y, N, X, uopSRL , IQT_INT, FU_ALU , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 1.U, Y, N, N, N, N, CSR.N),\n\n MUL -> List(Y, N, X, uopMUL , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULH -> List(Y, N, X, uopMULH , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHU -> List(Y, N, X, uopMULHU, IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULHSU -> List(Y, N, X, uopMULHSU,IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n MULW -> List(Y, N, X, uopMULW , IQT_INT, FU_MUL , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n DIV -> List(Y, N, X, uopDIV , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVU -> List(Y, N, X, uopDIVU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REM -> List(Y, N, X, uopREM , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMU -> List(Y, N, X, uopREMU , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVW -> List(Y, N, X, uopDIVW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n DIVUW -> List(Y, N, X, uopDIVUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMW -> List(Y, N, X, uopREMW , IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n REMUW -> List(Y, N, X, uopREMUW, IQT_INT, FU_DIV , RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n AUIPC -> List(Y, N, X, uopAUIPC, IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_U, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N), // use BRU for the PC read\n JAL -> List(Y, N, X, uopJAL , IQT_INT, FU_JMP , RT_FIX, RT_X , RT_X , N, IS_J, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n JALR -> List(Y, N, X, uopJALR , IQT_INT, FU_JMP , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 1.U, N, N, N, N, N, CSR.N),\n BEQ -> List(Y, N, X, uopBEQ , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BNE -> List(Y, N, X, uopBNE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGE -> List(Y, N, X, uopBGE , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BGEU -> List(Y, N, X, uopBGEU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLT -> List(Y, N, X, uopBLT , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n BLTU -> List(Y, N, X, uopBLTU , IQT_INT, FU_ALU , RT_X , RT_FIX, RT_FIX, N, IS_B, N, N, N, N, N, M_X , 0.U, N, Y, N, N, N, CSR.N),\n\n // I-type, the immediate12 holds the CSR register.\n CSRRW -> List(Y, N, X, uopCSRRW, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRS -> List(Y, N, X, uopCSRRS, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRC -> List(Y, N, X, uopCSRRC, IQT_INT, FU_CSR , RT_FIX, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n CSRRWI -> List(Y, N, X, uopCSRRWI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.W),\n CSRRSI -> List(Y, N, X, uopCSRRSI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.S),\n CSRRCI -> List(Y, N, X, uopCSRRCI,IQT_INT, FU_CSR , RT_FIX, RT_PAS, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.C),\n\n SFENCE_VMA->List(Y,N, X, uopSFENCE,IQT_MEM, FU_MEM , RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N,M_SFENCE,0.U,N, N, N, Y, Y, CSR.N),\n ECALL -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n EBREAK -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, Y, Y, Y, CSR.I),\n SRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n MRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n DRET -> List(Y, N, X, uopERET ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n WFI -> List(Y, N, X, uopWFI ,IQT_INT, FU_CSR , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, Y, Y, CSR.I),\n\n FENCE_I -> List(Y, N, X, uopNOP , IQT_INT, FU_X , RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, Y, M_X , 0.U, N, N, N, Y, Y, CSR.N),\n FENCE -> List(Y, N, X, uopFENCE, IQT_INT, FU_MEM , RT_X , RT_X , RT_X , N, IS_X, N, Y, N, Y, N, M_X , 0.U, N, N, N, Y, Y, CSR.N), // TODO PERF make fence higher performance\n // currently serializes pipeline\n\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec? rs1 regtype | | | uses_stq | | |\n // | | | micro-code | rs2 type| | | | is_amo | | |\n // | | | | iq-type func unit | | | | | | | is_fence | | |\n // | | | | | | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // A-type | | | | | | | | | | | | | | | | | | | | | | | |\n AMOADD_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N), // TODO make AMOs higherperformance\n AMOXOR_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_W-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_W->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n AMOADD_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_ADD, 0.U,N, N, N, Y, Y, CSR.N),\n AMOXOR_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_XOR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOSWAP_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_SWAP,0.U,N, N, N, Y, Y, CSR.N),\n AMOAND_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_AND, 0.U,N, N, N, Y, Y, CSR.N),\n AMOOR_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_OR, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMIN_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MIN, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMINU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MINU,0.U,N, N, N, Y, Y, CSR.N),\n AMOMAX_D-> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAX, 0.U,N, N, N, Y, Y, CSR.N),\n AMOMAXU_D->List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XA_MAXU,0.U,N, N, N, Y, Y, CSR.N),\n\n LR_W -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n LR_D -> List(Y, N, X, uopLD , IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_X , N, IS_X, Y, N, N, N, N, M_XLR , 0.U,N, N, N, Y, Y, CSR.N),\n SC_W -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N),\n SC_D -> List(Y, N, X, uopAMO_AG, IQT_MEM, FU_MEM, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, Y, Y, N, N, M_XSC , 0.U,N, N, N, Y, Y, CSR.N)\n )\n}\n\n/**\n * FP Decode constants\n */\nobject FDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq_type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FLW -> List(Y, Y, Y, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FLD -> List(Y, Y, N, uopLD , IQT_MEM, FU_MEM, RT_FLT, RT_FIX, RT_X , N, IS_I, Y, N, N, N, N, M_XRD, 0.U, N, N, N, N, N, CSR.N),\n FSW -> List(Y, Y, Y, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N), // sort of a lie; broken into two micro-ops\n FSD -> List(Y, Y, N, uopSTA , IQT_MFP,FU_F2IMEM,RT_X , RT_FIX, RT_FLT, N, IS_S, N, Y, N, N, N, M_XWR, 0.U, N, N, N, N, N, CSR.N),\n\n FCLASS_S-> List(Y, Y, Y, uopFCLASS_S,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCLASS_D-> List(Y, Y, N, uopFCLASS_D,IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMV_W_X -> List(Y, Y, Y, uopFMV_W_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_D_X -> List(Y, Y, N, uopFMV_D_X, IQT_INT, FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_W -> List(Y, Y, Y, uopFMV_X_W, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMV_X_D -> List(Y, Y, N, uopFMV_X_D, IQT_FP , FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FSGNJ_S -> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJ_D -> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJX_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_S-> List(Y, Y, Y, uopFSGNJ_S, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSGNJN_D-> List(Y, Y, N, uopFSGNJ_D, IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to FP\n FCVT_S_D-> List(Y, Y, Y, uopFCVT_S_D,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_S-> List(Y, Y, N, uopFCVT_D_S,IQT_FP , FU_FPU, RT_FLT, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // Int to FP\n FCVT_S_W-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_WU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_L-> List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_S_LU->List(Y, Y, Y, uopFCVT_S_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_D_W-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_WU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_L-> List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_D_LU->List(Y, Y, N, uopFCVT_D_X, IQT_INT,FU_I2F, RT_FLT, RT_FIX, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // FP to Int\n FCVT_W_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_S-> List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_S->List(Y, Y, Y, uopFCVT_X_S, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FCVT_W_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_WU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_L_D-> List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FCVT_LU_D->List(Y, Y, N, uopFCVT_X_D, IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_X , N, IS_I, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n // \"fp_single\" is used for wb_data formatting (and debugging)\n FEQ_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_S ->List(Y, Y, Y, uopCMPR_S , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FEQ_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLT_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FLE_D ->List(Y, Y, N, uopCMPR_D , IQT_FP, FU_F2I, RT_FIX, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMIN_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_S ->List(Y, Y, Y,uopFMINMAX_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMIN_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMAX_D ->List(Y, Y, N,uopFMINMAX_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FADD_S ->List(Y, Y, Y, uopFADD_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_S ->List(Y, Y, Y, uopFSUB_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_S ->List(Y, Y, Y, uopFMUL_S , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FADD_D ->List(Y, Y, N, uopFADD_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSUB_D ->List(Y, Y, N, uopFSUB_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMUL_D ->List(Y, Y, N, uopFMUL_D , IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n\n FMADD_S ->List(Y, Y, Y, uopFMADD_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_S ->List(Y, Y, Y, uopFMSUB_S, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_S ->List(Y, Y, Y, uopFNMADD_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_S ->List(Y, Y, Y, uopFNMSUB_S,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMADD_D ->List(Y, Y, N, uopFMADD_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FMSUB_D ->List(Y, Y, N, uopFMSUB_D, IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMADD_D ->List(Y, Y, N, uopFNMADD_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FNMSUB_D ->List(Y, Y, N, uopFNMSUB_D,IQT_FP, FU_FPU, RT_FLT, RT_FLT, RT_FLT, Y, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n/**\n * FP Divide SquareRoot Constants\n */\nobject FDivSqrtDecode extends DecodeConstants\n{\n val table: Array[(BitPat, List[BitPat])] = Array(\n // frs3_en wakeup_delay\n // | imm sel | bypassable (aka, known/fixed latency)\n // | | uses_ldq | | is_br\n // is val inst? rs1 regtype | | | uses_stq | | |\n // | is fp inst? | rs2 type| | | | is_amo | | |\n // | | is dst single-prec? | | | | | | | is_fence | | |\n // | | | micro-opcode | | | | | | | | is_fencei | | | is breakpoint or ecall\n // | | | | iq-type func dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | unit regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n FDIV_S ->List(Y, Y, Y, uopFDIV_S , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FDIV_D ->List(Y, Y, N, uopFDIV_D , IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_FLT, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_S ->List(Y, Y, Y, uopFSQRT_S, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n FSQRT_D ->List(Y, Y, N, uopFSQRT_D, IQT_FP, FU_FDV, RT_FLT, RT_FLT, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n//scalastyle:on\n\n/**\n * RoCC initial decode\n */\nobject RoCCDecode extends DecodeConstants\n{\n // Note: We use FU_CSR since CSR instructions cannot co-execute with RoCC instructions\n // frs3_en wakeup_delay\n // is val inst? | imm sel | bypassable (aka, known/fixed latency)\n // | is fp inst? | | uses_ldq | | is_br\n // | | is single-prec rs1 regtype | | | uses_stq | | |\n // | | | | rs2 type| | | | is_amo | | |\n // | | | micro-code func unit | | | | | | | is_fence | | |\n // | | | | iq-type | | | | | | | | | is_fencei | | | is breakpoint or ecall?\n // | | | | | | dst | | | | | | | | | mem | | | | is unique? (clear pipeline for it)\n // | | | | | | regtype | | | | | | | | | cmd | | | | | flush on commit\n // | | | | | | | | | | | | | | | | | | | | | | | csr cmd\n // | | | | | | | | | | | | | | | | | | | | | | | |\n val table: Array[(BitPat, List[BitPat])] = Array(// | | | | | | | | | | | | | | | | | | |\n CUSTOM0 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM0_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM1_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM2_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_X , RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_X , RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_X , N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N),\n CUSTOM3_RD_RS1_RS2 ->List(Y, N, X, uopROCC , IQT_INT, FU_CSR, RT_FIX, RT_FIX, RT_FIX, N, IS_X, N, N, N, N, N, M_X , 0.U, N, N, N, N, N, CSR.N)\n )\n}\n\n\n\n\n\n/**\n * IO bundle for the Decode unit\n */\nclass DecodeUnitIo(implicit p: Parameters) extends BoomBundle\n{\n val enq = new Bundle { val uop = Input(new MicroOp()) }\n val deq = new Bundle { val uop = Output(new MicroOp()) }\n\n // from CSRFile\n val status = Input(new freechips.rocketchip.rocket.MStatus())\n val csr_decode = Flipped(new freechips.rocketchip.rocket.CSRDecodeIO)\n val interrupt = Input(Bool())\n val interrupt_cause = Input(UInt(xLen.W))\n}\n\n/**\n * Decode unit that takes in a single instruction and generates a MicroOp.\n */\nclass DecodeUnit(implicit p: Parameters) extends BoomModule\n with freechips.rocketchip.rocket.constants.MemoryOpConstants\n{\n val io = IO(new DecodeUnitIo)\n\n val uop = Wire(new MicroOp())\n uop := io.enq.uop\n\n var decode_table = XDecode.table\n if (usingFPU) decode_table ++= FDecode.table\n if (usingFPU && usingFDivSqrt) decode_table ++= FDivSqrtDecode.table\n if (usingRoCC) decode_table ++= RoCCDecode.table\n decode_table ++= (if (xLen == 64) X64Decode.table else X32Decode.table)\n\n val inst = uop.inst\n\n val cs = Wire(new CtrlSigs()).decode(inst, decode_table)\n\n // Exception Handling\n io.csr_decode.inst := inst\n val csr_en = cs.csr_cmd.isOneOf(CSR.S, CSR.C, CSR.W)\n val csr_ren = cs.csr_cmd.isOneOf(CSR.S, CSR.C) && uop.lrs1 === 0.U\n val system_insn = cs.csr_cmd === CSR.I\n val sfence = cs.uopc === uopSFENCE\n\n val cs_legal = cs.legal\n// dontTouch(cs_legal)\n\n val id_illegal_insn = !cs_legal ||\n cs.fp_val && io.csr_decode.fp_illegal || // TODO check for illegal rm mode: (io.fpu.illegal_rm)\n cs.rocc && io.csr_decode.rocc_illegal ||\n cs.is_amo && !io.status.isa('a'-'a') ||\n (cs.fp_val && !cs.fp_single) && !io.status.isa('d'-'a') ||\n csr_en && (io.csr_decode.read_illegal || !csr_ren && io.csr_decode.write_illegal) ||\n ((sfence || system_insn) && io.csr_decode.system_illegal)\n\n// cs.div && !csr.io.status.isa('m'-'a') || TODO check for illegal div instructions\n\n def checkExceptions(x: Seq[(Bool, UInt)]) =\n (x.map(_._1).reduce(_||_), PriorityMux(x))\n\n val (xcpt_valid, xcpt_cause) = checkExceptions(List(\n (io.interrupt && !io.enq.uop.is_sfb, io.interrupt_cause), // Disallow interrupts while we are handling a SFB\n (uop.bp_debug_if, (CSR.debugTriggerCause).U),\n (uop.bp_xcpt_if, (Causes.breakpoint).U),\n (uop.xcpt_pf_if, (Causes.fetch_page_fault).U),\n (uop.xcpt_ae_if, (Causes.fetch_access).U),\n (id_illegal_insn, (Causes.illegal_instruction).U)))\n\n uop.exception := xcpt_valid\n uop.exc_cause := xcpt_cause\n\n //-------------------------------------------------------------\n\n uop.uopc := cs.uopc\n uop.iq_type := cs.iq_type\n uop.fu_code := cs.fu_code\n\n // x-registers placed in 0-31, f-registers placed in 32-63.\n // This allows us to straight-up compare register specifiers and not need to\n // verify the rtypes (e.g., bypassing in rename).\n uop.ldst := inst(RD_MSB,RD_LSB)\n uop.lrs1 := inst(RS1_MSB,RS1_LSB)\n uop.lrs2 := inst(RS2_MSB,RS2_LSB)\n uop.lrs3 := inst(RS3_MSB,RS3_LSB)\n\n uop.ldst_val := cs.dst_type =/= RT_X && !(uop.ldst === 0.U && uop.dst_rtype === RT_FIX)\n uop.dst_rtype := cs.dst_type\n uop.lrs1_rtype := cs.rs1_type\n uop.lrs2_rtype := cs.rs2_type\n uop.frs3_en := cs.frs3_en\n\n uop.ldst_is_rs1 := uop.is_sfb_shadow\n // SFB optimization\n when (uop.is_sfb_shadow && cs.rs2_type === RT_X) {\n uop.lrs2_rtype := RT_FIX\n uop.lrs2 := inst(RD_MSB,RD_LSB)\n uop.ldst_is_rs1 := false.B\n } .elsewhen (uop.is_sfb_shadow && cs.uopc === uopADD && inst(RS1_MSB,RS1_LSB) === 0.U) {\n uop.uopc := uopMOV\n uop.lrs1 := inst(RD_MSB, RD_LSB)\n uop.ldst_is_rs1 := true.B\n }\n when (uop.is_sfb_br) {\n uop.fu_code := FU_JMP\n }\n\n\n uop.fp_val := cs.fp_val\n uop.fp_single := cs.fp_single // TODO use this signal instead of the FPU decode's table signal?\n\n uop.mem_cmd := cs.mem_cmd\n uop.mem_size := Mux(cs.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL), Cat(uop.lrs2 =/= 0.U, uop.lrs1 =/= 0.U), inst(13,12))\n uop.mem_signed := !inst(14)\n uop.uses_ldq := cs.uses_ldq\n uop.uses_stq := cs.uses_stq\n uop.is_amo := cs.is_amo\n uop.is_fence := cs.is_fence\n uop.is_fencei := cs.is_fencei\n uop.is_sys_pc2epc := cs.is_sys_pc2epc\n uop.is_unique := cs.inst_unique\n uop.flush_on_commit := cs.flush_on_commit || (csr_en && !csr_ren && io.csr_decode.write_flush)\n\n uop.bypassable := cs.bypassable\n\n //-------------------------------------------------------------\n // immediates\n\n // repackage the immediate, and then pass the fewest number of bits around\n val di24_20 = Mux(cs.imm_sel === IS_B || cs.imm_sel === IS_S, inst(11,7), inst(24,20))\n uop.imm_packed := Cat(inst(31,25), di24_20, inst(19,12))\n\n //-------------------------------------------------------------\n\n uop.is_br := cs.is_br\n uop.is_jal := (uop.uopc === uopJAL)\n uop.is_jalr := (uop.uopc === uopJALR)\n // uop.is_jump := cs.is_jal || (uop.uopc === uopJALR)\n // uop.is_ret := (uop.uopc === uopJALR) &&\n // (uop.ldst === X0) &&\n // (uop.lrs1 === RA)\n // uop.is_call := (uop.uopc === uopJALR || uop.uopc === uopJAL) &&\n // (uop.ldst === RA)\n\n //-------------------------------------------------------------\n\n io.deq.uop := uop\n}\n\n/**\n * Smaller Decode unit for the Frontend to decode different\n * branches.\n * Accepts EXPANDED RVC instructions\n */\n\nclass BranchDecodeSignals(implicit p: Parameters) extends BoomBundle\n{\n val is_ret = Bool()\n val is_call = Bool()\n val target = UInt(vaddrBitsExtended.W)\n val cfi_type = UInt(CFI_SZ.W)\n\n\n // Is this branch a short forwards jump?\n val sfb_offset = Valid(UInt(log2Ceil(icBlockBytes).W))\n // Is this instruction allowed to be inside a sfb?\n val shadowable = Bool()\n}\n\nclass BranchDecode(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val inst = Input(UInt(32.W))\n val pc = Input(UInt(vaddrBitsExtended.W))\n\n val out = Output(new BranchDecodeSignals)\n })\n\n val bpd_csignals =\n freechips.rocketchip.rocket.DecodeLogic(io.inst,\n List[BitPat](N, N, N, N, X),\n//// is br?\n//// | is jal?\n//// | | is jalr?\n//// | | |\n//// | | | shadowable\n//// | | | | has_rs2\n//// | | | | |\n Array[(BitPat, List[BitPat])](\n JAL -> List(N, Y, N, N, X),\n JALR -> List(N, N, Y, N, X),\n BEQ -> List(Y, N, N, N, X),\n BNE -> List(Y, N, N, N, X),\n BGE -> List(Y, N, N, N, X),\n BGEU -> List(Y, N, N, N, X),\n BLT -> List(Y, N, N, N, X),\n BLTU -> List(Y, N, N, N, X),\n\n SLLI -> List(N, N, N, Y, N),\n SRLI -> List(N, N, N, Y, N),\n SRAI -> List(N, N, N, Y, N),\n\n ADDIW -> List(N, N, N, Y, N),\n SLLIW -> List(N, N, N, Y, N),\n SRAIW -> List(N, N, N, Y, N),\n SRLIW -> List(N, N, N, Y, N),\n\n ADDW -> List(N, N, N, Y, Y),\n SUBW -> List(N, N, N, Y, Y),\n SLLW -> List(N, N, N, Y, Y),\n SRAW -> List(N, N, N, Y, Y),\n SRLW -> List(N, N, N, Y, Y),\n\n LUI -> List(N, N, N, Y, N),\n\n ADDI -> List(N, N, N, Y, N),\n ANDI -> List(N, N, N, Y, N),\n ORI -> List(N, N, N, Y, N),\n XORI -> List(N, N, N, Y, N),\n SLTI -> List(N, N, N, Y, N),\n SLTIU -> List(N, N, N, Y, N),\n\n SLL -> List(N, N, N, Y, Y),\n ADD -> List(N, N, N, Y, Y),\n SUB -> List(N, N, N, Y, Y),\n SLT -> List(N, N, N, Y, Y),\n SLTU -> List(N, N, N, Y, Y),\n AND -> List(N, N, N, Y, Y),\n OR -> List(N, N, N, Y, Y),\n XOR -> List(N, N, N, Y, Y),\n SRA -> List(N, N, N, Y, Y),\n SRL -> List(N, N, N, Y, Y)\n ))\n\n val cs_is_br = bpd_csignals(0)(0)\n val cs_is_jal = bpd_csignals(1)(0)\n val cs_is_jalr = bpd_csignals(2)(0)\n val cs_is_shadowable = bpd_csignals(3)(0)\n val cs_has_rs2 = bpd_csignals(4)(0)\n\n io.out.is_call := (cs_is_jal || cs_is_jalr) && GetRd(io.inst) === RA\n io.out.is_ret := cs_is_jalr && GetRs1(io.inst) === BitPat(\"b00?01\") && GetRd(io.inst) === X0\n\n io.out.target := Mux(cs_is_br, ComputeBranchTarget(io.pc, io.inst, xLen),\n ComputeJALTarget(io.pc, io.inst, xLen))\n io.out.cfi_type :=\n Mux(cs_is_jalr,\n CFI_JALR,\n Mux(cs_is_jal,\n CFI_JAL,\n Mux(cs_is_br,\n CFI_BR,\n CFI_X)))\n\n val br_offset = Cat(io.inst(7), io.inst(30,25), io.inst(11,8), 0.U(1.W))\n // Is a sfb if it points forwards (offset is positive)\n io.out.sfb_offset.valid := cs_is_br && !io.inst(31) && br_offset =/= 0.U && (br_offset >> log2Ceil(icBlockBytes)) === 0.U\n io.out.sfb_offset.bits := br_offset\n io.out.shadowable := cs_is_shadowable && (\n !cs_has_rs2 ||\n (GetRs1(io.inst) === GetRd(io.inst)) ||\n (io.inst === ADD && GetRs1(io.inst) === X0)\n )\n}\n\n/**\n * Track the current \"branch mask\", and give out the branch mask to each micro-op in Decode\n * (each micro-op in the machine has a branch mask which says which branches it\n * is being speculated under).\n *\n * @param pl_width pipeline width for the processor\n */\nclass BranchMaskGenerationLogic(val pl_width: Int)(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n // guess if the uop is a branch (we'll catch this later)\n val is_branch = Input(Vec(pl_width, Bool()))\n // lock in that it's actually a branch and will fire, so we update\n // the branch_masks.\n val will_fire = Input(Vec(pl_width, Bool()))\n\n // give out tag immediately (needed in rename)\n // mask can come later in the cycle\n val br_tag = Output(Vec(pl_width, UInt(brTagSz.W)))\n val br_mask = Output(Vec(pl_width, UInt(maxBrCount.W)))\n\n // tell decoders the branch mask has filled up, but on the granularity\n // of an individual micro-op (so some micro-ops can go through)\n val is_full = Output(Vec(pl_width, Bool()))\n\n val brupdate = Input(new BrUpdateInfo())\n val flush_pipeline = Input(Bool())\n\n val debug_branch_mask = Output(UInt(maxBrCount.W))\n })\n\n val branch_mask = RegInit(0.U(maxBrCount.W))\n\n //-------------------------------------------------------------\n // Give out the branch tag to each branch micro-op\n\n var allocate_mask = branch_mask\n val tag_masks = Wire(Vec(pl_width, UInt(maxBrCount.W)))\n\n for (w <- 0 until pl_width) {\n // TODO this is a loss of performance as we're blocking branches based on potentially fake branches\n io.is_full(w) := (allocate_mask === ~(0.U(maxBrCount.W))) && io.is_branch(w)\n\n // find br_tag and compute next br_mask\n val new_br_tag = Wire(UInt(brTagSz.W))\n new_br_tag := 0.U\n tag_masks(w) := 0.U\n\n for (i <- maxBrCount-1 to 0 by -1) {\n when (~allocate_mask(i)) {\n new_br_tag := i.U\n tag_masks(w) := (1.U << i.U)\n }\n }\n\n io.br_tag(w) := new_br_tag\n allocate_mask = Mux(io.is_branch(w), tag_masks(w) | allocate_mask, allocate_mask)\n }\n\n //-------------------------------------------------------------\n // Give out the branch mask to each micro-op\n // (kill off the bits that corresponded to branches that aren't going to fire)\n\n var curr_mask = branch_mask\n for (w <- 0 until pl_width) {\n io.br_mask(w) := GetNewBrMask(io.brupdate, curr_mask)\n curr_mask = Mux(io.will_fire(w), tag_masks(w) | curr_mask, curr_mask)\n }\n\n //-------------------------------------------------------------\n // Update the current branch_mask\n\n when (io.flush_pipeline) {\n branch_mask := 0.U\n } .otherwise {\n val mask = Mux(io.brupdate.b2.mispredict,\n io.brupdate.b2.uop.br_mask,\n ~(0.U(maxBrCount.W)))\n branch_mask := GetNewBrMask(io.brupdate, curr_mask) & mask\n }\n\n io.debug_branch_mask := branch_mask\n}", + "response": "module BranchDecode(\n input [31:0] io_inst,\n input [39:0] io_pc,\n output io_out_is_ret,\n output io_out_is_call,\n output [39:0] io_out_target,\n output [2:0] io_out_cfi_type,\n output io_out_sfb_offset_valid,\n output [5:0] io_out_sfb_offset_bits,\n output io_out_shadowable\n);\n\n wire [29:0] bpd_csignals_decoded_invInputs = ~(io_inst[31:2]);\n wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_2 = {io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[4], io_inst[5], bpd_csignals_decoded_invInputs[4], bpd_csignals_decoded_invInputs[10], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[12], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[29]};\n wire [13:0] _bpd_csignals_decoded_andMatrixOutputs_T_3 = {io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], io_inst[4], io_inst[5], bpd_csignals_decoded_invInputs[4], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[28], bpd_csignals_decoded_invInputs[29]};\n wire [9:0] _bpd_csignals_decoded_andMatrixOutputs_T_7 = {io_inst[0], io_inst[1], io_inst[2], bpd_csignals_decoded_invInputs[1], bpd_csignals_decoded_invInputs[2], io_inst[5], io_inst[6], bpd_csignals_decoded_invInputs[10], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[12]};\n wire [6:0] _bpd_csignals_decoded_andMatrixOutputs_T_8 = {io_inst[0], io_inst[1], io_inst[2], io_inst[3], bpd_csignals_decoded_invInputs[2], io_inst[5], io_inst[6]};\n wire [14:0] _bpd_csignals_decoded_andMatrixOutputs_T_15 = {io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[4], io_inst[5], bpd_csignals_decoded_invInputs[4], io_inst[12], bpd_csignals_decoded_invInputs[11], io_inst[14], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[29]};\n wire [1:0] _bpd_csignals_decoded_orMatrixOutputs_T_6 = {&{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], bpd_csignals_decoded_invInputs[2], io_inst[5], io_inst[6], bpd_csignals_decoded_invInputs[11]}, &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], bpd_csignals_decoded_invInputs[2], io_inst[5], io_inst[6], io_inst[14]}};\n assign io_out_is_ret = (&_bpd_csignals_decoded_andMatrixOutputs_T_7) & {io_inst[19:18], io_inst[16:15]} == 4'h1 & io_inst[11:7] == 5'h0;\n assign io_out_is_call = ((&_bpd_csignals_decoded_andMatrixOutputs_T_8) | (&_bpd_csignals_decoded_andMatrixOutputs_T_7)) & io_inst[11:7] == 5'h1;\n assign io_out_target = (|_bpd_csignals_decoded_orMatrixOutputs_T_6) ? io_pc + {{28{io_inst[31]}}, io_inst[7], io_inst[30:25], io_inst[11:8], 1'h0} & 40'hFFFFFFFFFE : io_pc + {{20{io_inst[31]}}, io_inst[19:12], io_inst[20], io_inst[30:21], 1'h0} & 40'hFFFFFFFFFE;\n assign io_out_cfi_type = (&_bpd_csignals_decoded_andMatrixOutputs_T_7) ? 3'h3 : (&_bpd_csignals_decoded_andMatrixOutputs_T_8) ? 3'h2 : {2'h0, |_bpd_csignals_decoded_orMatrixOutputs_T_6};\n assign io_out_sfb_offset_valid = (|_bpd_csignals_decoded_orMatrixOutputs_T_6) & ~(io_inst[31]) & (|{io_inst[7], io_inst[30:25], io_inst[11:8]}) & {io_inst[7], io_inst[30:26]} == 6'h0;\n assign io_out_sfb_offset_bits = {io_inst[25], io_inst[11:8], 1'h0};\n assign io_out_shadowable =\n (|{&{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], io_inst[4], bpd_csignals_decoded_invInputs[3], bpd_csignals_decoded_invInputs[4], bpd_csignals_decoded_invInputs[10]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[4], bpd_csignals_decoded_invInputs[3], bpd_csignals_decoded_invInputs[4], bpd_csignals_decoded_invInputs[10], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[12]},\n &_bpd_csignals_decoded_andMatrixOutputs_T_2,\n &_bpd_csignals_decoded_andMatrixOutputs_T_3,\n &{io_inst[0], io_inst[1], io_inst[2], bpd_csignals_decoded_invInputs[1], io_inst[4], io_inst[5], bpd_csignals_decoded_invInputs[4]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], io_inst[4], bpd_csignals_decoded_invInputs[3], bpd_csignals_decoded_invInputs[4], io_inst[12], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[28], bpd_csignals_decoded_invInputs[29]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[3], io_inst[4], bpd_csignals_decoded_invInputs[4], io_inst[12], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[28], bpd_csignals_decoded_invInputs[29]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], io_inst[4], bpd_csignals_decoded_invInputs[3], bpd_csignals_decoded_invInputs[4], io_inst[13]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], bpd_csignals_decoded_invInputs[1], io_inst[4], bpd_csignals_decoded_invInputs[3], bpd_csignals_decoded_invInputs[4], io_inst[12], bpd_csignals_decoded_invInputs[11], io_inst[14], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[29]},\n &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[3], io_inst[4], bpd_csignals_decoded_invInputs[4], io_inst[12], bpd_csignals_decoded_invInputs[11], io_inst[14], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[29]},\n &_bpd_csignals_decoded_andMatrixOutputs_T_15}) & ({&_bpd_csignals_decoded_andMatrixOutputs_T_2, &_bpd_csignals_decoded_andMatrixOutputs_T_3, &{io_inst[0], io_inst[1], bpd_csignals_decoded_invInputs[0], io_inst[4], io_inst[5], bpd_csignals_decoded_invInputs[4], bpd_csignals_decoded_invInputs[11], bpd_csignals_decoded_invInputs[12], bpd_csignals_decoded_invInputs[23], bpd_csignals_decoded_invInputs[24], bpd_csignals_decoded_invInputs[25], bpd_csignals_decoded_invInputs[26], bpd_csignals_decoded_invInputs[27], bpd_csignals_decoded_invInputs[28], bpd_csignals_decoded_invInputs[29]}, &_bpd_csignals_decoded_andMatrixOutputs_T_15} == 4'h0 | io_inst[19:15] == io_inst[11:7] | {io_inst[31:25], io_inst[14:12], io_inst[6:0]} == 17'h33 & io_inst[19:15] == 5'h0);\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Out-of-Order Load/Store Unit\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Load/Store Unit is made up of the Load Queue, the Store Queue (LDQ and STQ).\n//\n// Stores are sent to memory at (well, after) commit, loads are executed\n// optimstically ASAP. If a misspeculation was discovered, the pipeline is\n// cleared. Loads put to sleep are retried. If a LoadAddr and StoreAddr match,\n// the Load can receive its data by forwarding data out of the Store Queue.\n//\n// Currently, loads are sent to memory immediately, and in parallel do an\n// associative search of the STQ, on entering the LSU. If a hit on the STQ\n// search, the memory request is killed on the next cycle, and if the STQ entry\n// is valid, the store data is forwarded to the load (delayed to match the\n// load-use delay to delay with the write-port structural hazard). If the store\n// data is not present, or it's only a partial match (SB->LH), the load is put\n// to sleep in the LDQ.\n//\n// Memory ordering violations are detected by stores at their addr-gen time by\n// associatively searching the LDQ for newer loads that have been issued to\n// memory.\n//\n// The store queue contains both speculated and committed stores.\n//\n// Only one port to memory... loads and stores have to fight for it, West Side\n// Story style.\n//\n// TODO:\n// - Add predicting structure for ordering failures\n// - currently won't STD forward if DMEM is busy\n// - ability to turn off things if VM is disabled\n// - reconsider port count of the wakeup, retry stuff\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.util.Str\n\nimport boom.v3.common._\nimport boom.v3.exu.{BrUpdateInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp}\nimport boom.v3.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask}\n\nclass LSUExeIO(implicit p: Parameters) extends BoomBundle()(p)\n{\n // The \"resp\" of the maddrcalc is really a \"req\" to the LSU\n val req = Flipped(new ValidIO(new FuncUnitResp(xLen)))\n // Send load data to regfiles\n val iresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen))\n val fresp = new DecoupledIO(new boom.v3.exu.ExeUnitResp(xLen+1)) // TODO: Should this be fLen?\n}\n\nclass BoomDCacheReq(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = UInt(coreMaxAddrBits.W)\n val data = Bits(coreDataBits.W)\n val is_hella = Bool() // Is this the hellacache req? If so this is not tracked in LDQ or STQ\n}\n\nclass BoomDCacheResp(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val data = Bits(coreDataBits.W)\n val is_hella = Bool()\n}\n\nclass LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)\n{\n // In LSU's dmem stage, send the request\n val req = new DecoupledIO(Vec(memWidth, Valid(new BoomDCacheReq)))\n // In LSU's LCAM search stage, kill if order fail (or forwarding possible)\n val s1_kill = Output(Vec(memWidth, Bool()))\n // Get a request any cycle\n val resp = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheResp)))\n // In our response stage, if we get a nack, we need to reexecute\n val nack = Flipped(Vec(memWidth, new ValidIO(new BoomDCacheReq)))\n\n val brupdate = Output(new BrUpdateInfo)\n val exception = Output(Bool())\n val rob_pnr_idx = Output(UInt(robAddrSz.W))\n val rob_head_idx = Output(UInt(robAddrSz.W))\n\n val release = Flipped(new DecoupledIO(new TLBundleC(edge.bundle)))\n\n // Clears prefetching MSHRs\n val force_order = Output(Bool())\n val ordered = Input(Bool())\n\n val perf = Input(new Bundle {\n val acquire = Bool()\n val release = Bool()\n })\n\n}\n\nclass LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)\n{\n val exe = Vec(memWidth, new LSUExeIO)\n\n val dis_uops = Flipped(Vec(coreWidth, Valid(new MicroOp)))\n val dis_ldq_idx = Output(Vec(coreWidth, UInt(ldqAddrSz.W)))\n val dis_stq_idx = Output(Vec(coreWidth, UInt(stqAddrSz.W)))\n\n val ldq_full = Output(Vec(coreWidth, Bool()))\n val stq_full = Output(Vec(coreWidth, Bool()))\n\n val fp_stdata = Flipped(Decoupled(new ExeUnitResp(fLen)))\n\n val commit = Input(new CommitSignals)\n val commit_load_at_rob_head = Input(Bool())\n\n // Stores clear busy bit when stdata is received\n // memWidth for int, 1 for fp (to avoid back-pressure fpstdat)\n val clr_bsy = Output(Vec(memWidth + 1, Valid(UInt(robAddrSz.W))))\n\n // Speculatively safe load (barring memory ordering failure)\n val clr_unsafe = Output(Vec(memWidth, Valid(UInt(robAddrSz.W))))\n\n // Tell the DCache to clear prefetches/speculating misses\n val fence_dmem = Input(Bool())\n\n // Speculatively tell the IQs that we'll get load data back next cycle\n val spec_ld_wakeup = Output(Vec(memWidth, Valid(UInt(maxPregSz.W))))\n // Tell the IQs that the load we speculated last cycle was misspeculated\n val ld_miss = Output(Bool())\n\n val brupdate = Input(new BrUpdateInfo)\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n val exception = Input(Bool())\n\n val fencei_rdy = Output(Bool())\n\n val lxcpt = Output(Valid(new Exception))\n\n val tsc_reg = Input(UInt())\n\n val perf = Output(new Bundle {\n val acquire = Bool()\n val release = Bool()\n val tlbMiss = Bool()\n })\n}\n\nclass LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)\n{\n val ptw = new rocket.TLBPTWIO\n val core = new LSUCoreIO\n val dmem = new LSUDMemIO\n\n val hellacache = Flipped(new freechips.rocketchip.rocket.HellaCacheIO)\n}\n\nclass LDQEntry(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = Valid(UInt(coreMaxAddrBits.W))\n val addr_is_virtual = Bool() // Virtual address, we got a TLB miss\n val addr_is_uncacheable = Bool() // Uncacheable, wait until head of ROB to execute\n\n val executed = Bool() // load sent to memory, reset by NACKs\n val succeeded = Bool()\n val order_fail = Bool()\n val observed = Bool()\n\n val st_dep_mask = UInt(numStqEntries.W) // list of stores older than us\n val youngest_stq_idx = UInt(stqAddrSz.W) // index of the oldest store younger than us\n\n val forward_std_val = Bool()\n val forward_stq_idx = UInt(stqAddrSz.W) // Which store did we get the store-load forward from?\n\n val debug_wb_data = UInt(xLen.W)\n}\n\nclass STQEntry(implicit p: Parameters) extends BoomBundle()(p)\n with HasBoomUOP\n{\n val addr = Valid(UInt(coreMaxAddrBits.W))\n val addr_is_virtual = Bool() // Virtual address, we got a TLB miss\n val data = Valid(UInt(xLen.W))\n\n val committed = Bool() // committed by ROB\n val succeeded = Bool() // D$ has ack'd this, we don't need to maintain this anymore\n\n val debug_wb_data = UInt(xLen.W)\n}\n\nclass LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)\n with rocket.HasL1HellaCacheParameters\n{\n val io = IO(new LSUIO)\n io.hellacache := DontCare\n\n\n val ldq = Reg(Vec(numLdqEntries, Valid(new LDQEntry)))\n val stq = Reg(Vec(numStqEntries, Valid(new STQEntry)))\n\n\n\n val ldq_head = Reg(UInt(ldqAddrSz.W))\n val ldq_tail = Reg(UInt(ldqAddrSz.W))\n val stq_head = Reg(UInt(stqAddrSz.W)) // point to next store to clear from STQ (i.e., send to memory)\n val stq_tail = Reg(UInt(stqAddrSz.W))\n val stq_commit_head = Reg(UInt(stqAddrSz.W)) // point to next store to commit\n val stq_execute_head = Reg(UInt(stqAddrSz.W)) // point to next store to execute\n\n\n // If we got a mispredict, the tail will be misaligned for 1 extra cycle\n assert (io.core.brupdate.b2.mispredict ||\n stq(stq_execute_head).valid ||\n stq_head === stq_execute_head ||\n stq_tail === stq_execute_head,\n \"stq_execute_head got off track.\")\n\n val h_ready :: h_s1 :: h_s2 :: h_s2_nack :: h_wait :: h_replay :: h_dead :: Nil = Enum(7)\n // s1 : do TLB, if success and not killed, fire request go to h_s2\n // store s1_data to register\n // if tlb miss, go to s2_nack\n // if don't get TLB, go to s2_nack\n // store tlb xcpt\n // s2 : If kill, go to dead\n // If tlb xcpt, send tlb xcpt, go to dead\n // s2_nack : send nack, go to dead\n // wait : wait for response, if nack, go to replay\n // replay : refire request, use already translated address\n // dead : wait for response, ignore it\n val hella_state = RegInit(h_ready)\n val hella_req = Reg(new rocket.HellaCacheReq)\n val hella_data = Reg(new rocket.HellaCacheWriteData)\n val hella_paddr = Reg(UInt(paddrBits.W))\n val hella_xcpt = Reg(new rocket.HellaCacheExceptions)\n\n\n val dtlb = Module(new NBDTLB(\n instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBSets, dcacheParams.nTLBWays)))\n\n io.ptw <> dtlb.io.ptw\n io.core.perf.tlbMiss := io.ptw.req.fire\n io.core.perf.acquire := io.dmem.perf.acquire\n io.core.perf.release := io.dmem.perf.release\n\n\n\n val clear_store = WireInit(false.B)\n val live_store_mask = RegInit(0.U(numStqEntries.W))\n var next_live_store_mask = Mux(clear_store, live_store_mask & ~(1.U << stq_head),\n live_store_mask)\n\n\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Enqueue new entries\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // This is a newer store than existing loads, so clear the bit in all the store dependency masks\n for (i <- 0 until numLdqEntries)\n {\n when (clear_store)\n {\n ldq(i).bits.st_dep_mask := ldq(i).bits.st_dep_mask & ~(1.U << stq_head)\n }\n }\n\n // Decode stage\n var ld_enq_idx = ldq_tail\n var st_enq_idx = stq_tail\n\n val stq_nonempty = (0 until numStqEntries).map{ i => stq(i).valid }.reduce(_||_) =/= 0.U\n\n var ldq_full = Bool()\n var stq_full = Bool()\n\n for (w <- 0 until coreWidth)\n {\n ldq_full = WrapInc(ld_enq_idx, numLdqEntries) === ldq_head\n io.core.ldq_full(w) := ldq_full\n io.core.dis_ldq_idx(w) := ld_enq_idx\n\n stq_full = WrapInc(st_enq_idx, numStqEntries) === stq_head\n io.core.stq_full(w) := stq_full\n io.core.dis_stq_idx(w) := st_enq_idx\n\n val dis_ld_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_ldq && !io.core.dis_uops(w).bits.exception\n val dis_st_val = io.core.dis_uops(w).valid && io.core.dis_uops(w).bits.uses_stq && !io.core.dis_uops(w).bits.exception\n when (dis_ld_val)\n {\n ldq(ld_enq_idx).valid := true.B\n ldq(ld_enq_idx).bits.uop := io.core.dis_uops(w).bits\n ldq(ld_enq_idx).bits.youngest_stq_idx := st_enq_idx\n ldq(ld_enq_idx).bits.st_dep_mask := next_live_store_mask\n\n ldq(ld_enq_idx).bits.addr.valid := false.B\n ldq(ld_enq_idx).bits.executed := false.B\n ldq(ld_enq_idx).bits.succeeded := false.B\n ldq(ld_enq_idx).bits.order_fail := false.B\n ldq(ld_enq_idx).bits.observed := false.B\n ldq(ld_enq_idx).bits.forward_std_val := false.B\n\n assert (ld_enq_idx === io.core.dis_uops(w).bits.ldq_idx, \"[lsu] mismatch enq load tag.\")\n assert (!ldq(ld_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting ldq entries\")\n }\n .elsewhen (dis_st_val)\n {\n stq(st_enq_idx).valid := true.B\n stq(st_enq_idx).bits.uop := io.core.dis_uops(w).bits\n stq(st_enq_idx).bits.addr.valid := false.B\n stq(st_enq_idx).bits.data.valid := false.B\n stq(st_enq_idx).bits.committed := false.B\n stq(st_enq_idx).bits.succeeded := false.B\n\n assert (st_enq_idx === io.core.dis_uops(w).bits.stq_idx, \"[lsu] mismatch enq store tag.\")\n assert (!stq(st_enq_idx).valid, \"[lsu] Enqueuing uop is overwriting stq entries\")\n }\n\n ld_enq_idx = Mux(dis_ld_val, WrapInc(ld_enq_idx, numLdqEntries),\n ld_enq_idx)\n\n next_live_store_mask = Mux(dis_st_val, next_live_store_mask | (1.U << st_enq_idx),\n next_live_store_mask)\n st_enq_idx = Mux(dis_st_val, WrapInc(st_enq_idx, numStqEntries),\n st_enq_idx)\n\n assert(!(dis_ld_val && dis_st_val), \"A UOP is trying to go into both the LDQ and the STQ\")\n }\n\n ldq_tail := ld_enq_idx\n stq_tail := st_enq_idx\n\n io.dmem.force_order := io.core.fence_dmem\n io.core.fencei_rdy := !stq_nonempty && io.dmem.ordered\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Execute stage (access TLB, send requests to Memory)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // We can only report 1 exception per cycle.\n // Just be sure to report the youngest one\n val mem_xcpt_valid = Wire(Bool())\n val mem_xcpt_cause = Wire(UInt())\n val mem_xcpt_uop = Wire(new MicroOp)\n val mem_xcpt_vaddr = Wire(UInt())\n\n\n //---------------------------------------\n // Can-fire logic and wakeup/retry select\n //\n // First we determine what operations are waiting to execute.\n // These are the \"can_fire\"/\"will_fire\" signals\n\n val will_fire_load_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_stad_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_sta_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_std_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_sfence = Wire(Vec(memWidth, Bool()))\n val will_fire_hella_incoming = Wire(Vec(memWidth, Bool()))\n val will_fire_hella_wakeup = Wire(Vec(memWidth, Bool()))\n val will_fire_release = Wire(Vec(memWidth, Bool()))\n val will_fire_load_retry = Wire(Vec(memWidth, Bool()))\n val will_fire_sta_retry = Wire(Vec(memWidth, Bool()))\n val will_fire_store_commit = Wire(Vec(memWidth, Bool()))\n val will_fire_load_wakeup = Wire(Vec(memWidth, Bool()))\n\n val exe_req = WireInit(VecInit(io.core.exe.map(_.req)))\n // Sfence goes through all pipes\n for (i <- 0 until memWidth) {\n when (io.core.exe(i).req.bits.sfence.valid) {\n exe_req := VecInit(Seq.fill(memWidth) { io.core.exe(i).req })\n }\n }\n\n // -------------------------------\n // Assorted signals for scheduling\n\n // Don't wakeup a load if we just sent it last cycle or two cycles ago\n // The block_load_mask may be wrong, but the executing_load mask must be accurate\n val block_load_mask = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))\n val p1_block_load_mask = RegNext(block_load_mask)\n val p2_block_load_mask = RegNext(p1_block_load_mask)\n\n // Prioritize emptying the store queue when it is almost full\n val stq_almost_full = RegNext(WrapInc(WrapInc(st_enq_idx, numStqEntries), numStqEntries) === stq_head ||\n WrapInc(st_enq_idx, numStqEntries) === stq_head)\n\n // The store at the commit head needs the DCache to appear ordered\n // Delay firing load wakeups and retries now\n val store_needs_order = WireInit(false.B)\n\n val ldq_incoming_idx = widthMap(i => exe_req(i).bits.uop.ldq_idx)\n val ldq_incoming_e = widthMap(i => ldq(ldq_incoming_idx(i)))\n\n val stq_incoming_idx = widthMap(i => exe_req(i).bits.uop.stq_idx)\n val stq_incoming_e = widthMap(i => stq(stq_incoming_idx(i)))\n\n val ldq_retry_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i => {\n val e = ldq(i).bits\n val block = block_load_mask(i) || p1_block_load_mask(i)\n e.addr.valid && e.addr_is_virtual && !block\n }), ldq_head))\n val ldq_retry_e = ldq(ldq_retry_idx)\n\n val stq_retry_idx = RegNext(AgePriorityEncoder((0 until numStqEntries).map(i => {\n val e = stq(i).bits\n e.addr.valid && e.addr_is_virtual\n }), stq_commit_head))\n val stq_retry_e = stq(stq_retry_idx)\n\n val stq_commit_e = stq(stq_execute_head)\n\n val ldq_wakeup_idx = RegNext(AgePriorityEncoder((0 until numLdqEntries).map(i=> {\n val e = ldq(i).bits\n val block = block_load_mask(i) || p1_block_load_mask(i)\n e.addr.valid && !e.executed && !e.succeeded && !e.addr_is_virtual && !block\n }), ldq_head))\n val ldq_wakeup_e = ldq(ldq_wakeup_idx)\n\n // -----------------------\n // Determine what can fire\n\n // Can we fire a incoming load\n val can_fire_load_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_load)\n\n // Can we fire an incoming store addrgen + store datagen\n val can_fire_stad_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta\n && exe_req(w).bits.uop.ctrl.is_std)\n\n // Can we fire an incoming store addrgen\n val can_fire_sta_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_sta\n && !exe_req(w).bits.uop.ctrl.is_std)\n\n // Can we fire an incoming store datagen\n val can_fire_std_incoming = widthMap(w => exe_req(w).valid && exe_req(w).bits.uop.ctrl.is_std\n && !exe_req(w).bits.uop.ctrl.is_sta)\n\n // Can we fire an incoming sfence\n val can_fire_sfence = widthMap(w => exe_req(w).valid && exe_req(w).bits.sfence.valid)\n\n // Can we fire a request from dcache to release a line\n // This needs to go through LDQ search to mark loads as dangerous\n val can_fire_release = widthMap(w => (w == memWidth-1).B && io.dmem.release.valid)\n io.dmem.release.ready := will_fire_release.reduce(_||_)\n\n // Can we retry a load that missed in the TLB\n val can_fire_load_retry = widthMap(w =>\n ( ldq_retry_e.valid &&\n ldq_retry_e.bits.addr.valid &&\n ldq_retry_e.bits.addr_is_virtual &&\n !p1_block_load_mask(ldq_retry_idx) &&\n !p2_block_load_mask(ldq_retry_idx) &&\n RegNext(dtlb.io.miss_rdy) &&\n !store_needs_order &&\n (w == memWidth-1).B && // TODO: Is this best scheduling?\n !ldq_retry_e.bits.order_fail))\n\n // Can we retry a store addrgen that missed in the TLB\n // - Weird edge case when sta_retry and std_incoming for same entry in same cycle. Delay this\n val can_fire_sta_retry = widthMap(w =>\n ( stq_retry_e.valid &&\n stq_retry_e.bits.addr.valid &&\n stq_retry_e.bits.addr_is_virtual &&\n (w == memWidth-1).B &&\n RegNext(dtlb.io.miss_rdy) &&\n !(widthMap(i => (i != w).B &&\n can_fire_std_incoming(i) &&\n stq_incoming_idx(i) === stq_retry_idx).reduce(_||_))\n ))\n // Can we commit a store\n val can_fire_store_commit = widthMap(w =>\n ( stq_commit_e.valid &&\n !stq_commit_e.bits.uop.is_fence &&\n !mem_xcpt_valid &&\n !stq_commit_e.bits.uop.exception &&\n (w == 0).B &&\n (stq_commit_e.bits.committed || ( stq_commit_e.bits.uop.is_amo &&\n stq_commit_e.bits.addr.valid &&\n !stq_commit_e.bits.addr_is_virtual &&\n stq_commit_e.bits.data.valid))))\n\n // Can we wakeup a load that was nack'd\n val block_load_wakeup = WireInit(false.B)\n val can_fire_load_wakeup = widthMap(w =>\n ( ldq_wakeup_e.valid &&\n ldq_wakeup_e.bits.addr.valid &&\n !ldq_wakeup_e.bits.succeeded &&\n !ldq_wakeup_e.bits.addr_is_virtual &&\n !ldq_wakeup_e.bits.executed &&\n !ldq_wakeup_e.bits.order_fail &&\n !p1_block_load_mask(ldq_wakeup_idx) &&\n !p2_block_load_mask(ldq_wakeup_idx) &&\n !store_needs_order &&\n !block_load_wakeup &&\n (w == memWidth-1).B &&\n (!ldq_wakeup_e.bits.addr_is_uncacheable || (io.core.commit_load_at_rob_head &&\n ldq_head === ldq_wakeup_idx &&\n ldq_wakeup_e.bits.st_dep_mask.asUInt === 0.U))))\n\n // Can we fire an incoming hellacache request\n val can_fire_hella_incoming = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim ocntroller\n\n // Can we fire a hellacache request that the dcache nack'd\n val can_fire_hella_wakeup = WireInit(widthMap(w => false.B)) // This is assigned to in the hellashim controller\n\n //---------------------------------------------------------\n // Controller logic. Arbitrate which request actually fires\n\n val exe_tlb_valid = Wire(Vec(memWidth, Bool()))\n for (w <- 0 until memWidth) {\n var tlb_avail = true.B\n var dc_avail = true.B\n var lcam_avail = true.B\n var rob_avail = true.B\n\n def lsu_sched(can_fire: Bool, uses_tlb:Boolean, uses_dc:Boolean, uses_lcam: Boolean, uses_rob:Boolean): Bool = {\n val will_fire = can_fire && !(uses_tlb.B && !tlb_avail) &&\n !(uses_lcam.B && !lcam_avail) &&\n !(uses_dc.B && !dc_avail) &&\n !(uses_rob.B && !rob_avail)\n tlb_avail = tlb_avail && !(will_fire && uses_tlb.B)\n lcam_avail = lcam_avail && !(will_fire && uses_lcam.B)\n dc_avail = dc_avail && !(will_fire && uses_dc.B)\n rob_avail = rob_avail && !(will_fire && uses_rob.B)\n dontTouch(will_fire) // dontTouch these so we can inspect the will_fire signals\n will_fire\n }\n\n // The order of these statements is the priority\n // Some restrictions\n // - Incoming ops must get precedence, can't backpresure memaddrgen\n // - Incoming hellacache ops must get precedence over retrying ops (PTW must get precedence over retrying translation)\n // Notes on performance\n // - Prioritize releases, this speeds up cache line writebacks and refills\n // - Store commits are lowest priority, since they don't \"block\" younger instructions unless stq fills up\n will_fire_load_incoming (w) := lsu_sched(can_fire_load_incoming (w) , true , true , true , false) // TLB , DC , LCAM\n will_fire_stad_incoming (w) := lsu_sched(can_fire_stad_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB\n will_fire_sta_incoming (w) := lsu_sched(can_fire_sta_incoming (w) , true , false, true , true) // TLB , , LCAM , ROB\n will_fire_std_incoming (w) := lsu_sched(can_fire_std_incoming (w) , false, false, false, true) // , ROB\n will_fire_sfence (w) := lsu_sched(can_fire_sfence (w) , true , false, false, true) // TLB , , , ROB\n will_fire_release (w) := lsu_sched(can_fire_release (w) , false, false, true , false) // LCAM\n will_fire_hella_incoming(w) := lsu_sched(can_fire_hella_incoming(w) , true , true , false, false) // TLB , DC\n will_fire_hella_wakeup (w) := lsu_sched(can_fire_hella_wakeup (w) , false, true , false, false) // , DC\n will_fire_load_retry (w) := lsu_sched(can_fire_load_retry (w) , true , true , true , false) // TLB , DC , LCAM\n will_fire_sta_retry (w) := lsu_sched(can_fire_sta_retry (w) , true , false, true , true) // TLB , , LCAM , ROB // TODO: This should be higher priority\n will_fire_load_wakeup (w) := lsu_sched(can_fire_load_wakeup (w) , false, true , true , false) // , DC , LCAM1\n will_fire_store_commit (w) := lsu_sched(can_fire_store_commit (w) , false, true , false, false) // , DC\n\n\n assert(!(exe_req(w).valid && !(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) || will_fire_std_incoming(w) || will_fire_sfence(w))))\n\n when (will_fire_load_wakeup(w)) {\n block_load_mask(ldq_wakeup_idx) := true.B\n } .elsewhen (will_fire_load_incoming(w)) {\n block_load_mask(exe_req(w).bits.uop.ldq_idx) := true.B\n } .elsewhen (will_fire_load_retry(w)) {\n block_load_mask(ldq_retry_idx) := true.B\n }\n exe_tlb_valid(w) := !tlb_avail\n }\n assert((memWidth == 1).B ||\n (!(will_fire_sfence.reduce(_||_) && !will_fire_sfence.reduce(_&&_)) &&\n !will_fire_hella_incoming.reduce(_&&_) &&\n !will_fire_hella_wakeup.reduce(_&&_) &&\n !will_fire_load_retry.reduce(_&&_) &&\n !will_fire_sta_retry.reduce(_&&_) &&\n !will_fire_store_commit.reduce(_&&_) &&\n !will_fire_load_wakeup.reduce(_&&_)),\n \"Some operations is proceeding down multiple pipes\")\n\n require(memWidth <= 2)\n\n //--------------------------------------------\n // TLB Access\n\n assert(!(hella_state =/= h_ready && hella_req.cmd === rocket.M_SFENCE),\n \"SFENCE through hella interface not supported\")\n\n val exe_tlb_uop = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) , exe_req(w).bits.uop,\n Mux(will_fire_load_retry (w) , ldq_retry_e.bits.uop,\n Mux(will_fire_sta_retry (w) , stq_retry_e.bits.uop,\n Mux(will_fire_hella_incoming(w) , NullMicroOp,\n NullMicroOp)))))\n\n val exe_tlb_vaddr = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) , exe_req(w).bits.addr,\n Mux(will_fire_sfence (w) , exe_req(w).bits.sfence.bits.addr,\n Mux(will_fire_load_retry (w) , ldq_retry_e.bits.addr.bits,\n Mux(will_fire_sta_retry (w) , stq_retry_e.bits.addr.bits,\n Mux(will_fire_hella_incoming(w) , hella_req.addr,\n 0.U))))))\n\n val exe_sfence = WireInit((0.U).asTypeOf(Valid(new rocket.SFenceReq)))\n for (w <- 0 until memWidth) {\n when (will_fire_sfence(w)) {\n exe_sfence := exe_req(w).bits.sfence\n }\n }\n\n val exe_size = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) ||\n will_fire_load_retry (w) ||\n will_fire_sta_retry (w) , exe_tlb_uop(w).mem_size,\n Mux(will_fire_hella_incoming(w) , hella_req.size,\n 0.U)))\n val exe_cmd = widthMap(w =>\n Mux(will_fire_load_incoming (w) ||\n will_fire_stad_incoming (w) ||\n will_fire_sta_incoming (w) ||\n will_fire_sfence (w) ||\n will_fire_load_retry (w) ||\n will_fire_sta_retry (w) , exe_tlb_uop(w).mem_cmd,\n Mux(will_fire_hella_incoming(w) , hella_req.cmd,\n 0.U)))\n\n val exe_passthr= widthMap(w =>\n Mux(will_fire_hella_incoming(w) , hella_req.phys,\n false.B))\n val exe_kill = widthMap(w =>\n Mux(will_fire_hella_incoming(w) , io.hellacache.s1_kill,\n false.B))\n for (w <- 0 until memWidth) {\n dtlb.io.req(w).valid := exe_tlb_valid(w)\n dtlb.io.req(w).bits.vaddr := exe_tlb_vaddr(w)\n dtlb.io.req(w).bits.size := exe_size(w)\n dtlb.io.req(w).bits.cmd := exe_cmd(w)\n dtlb.io.req(w).bits.passthrough := exe_passthr(w)\n dtlb.io.req(w).bits.v := io.ptw.status.v\n dtlb.io.req(w).bits.prv := io.ptw.status.prv\n }\n dtlb.io.kill := exe_kill.reduce(_||_)\n dtlb.io.sfence := exe_sfence\n\n // exceptions\n val ma_ld = widthMap(w => will_fire_load_incoming(w) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc\n val ma_st = widthMap(w => (will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) && exe_req(w).bits.mxcpt.valid) // We get ma_ld in memaddrcalc\n val pf_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.ld && exe_tlb_uop(w).uses_ldq)\n val pf_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).pf.st && exe_tlb_uop(w).uses_stq)\n val ae_ld = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.ld && exe_tlb_uop(w).uses_ldq)\n val ae_st = widthMap(w => dtlb.io.req(w).valid && dtlb.io.resp(w).ae.st && exe_tlb_uop(w).uses_stq)\n\n // TODO check for xcpt_if and verify that never happens on non-speculative instructions.\n val mem_xcpt_valids = RegNext(widthMap(w =>\n (pf_ld(w) || pf_st(w) || ae_ld(w) || ae_st(w) || ma_ld(w) || ma_st(w)) &&\n !io.core.exception &&\n !IsKilledByBranch(io.core.brupdate, exe_tlb_uop(w))))\n val mem_xcpt_uops = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_tlb_uop(w))))\n val mem_xcpt_causes = RegNext(widthMap(w =>\n Mux(ma_ld(w), rocket.Causes.misaligned_load.U,\n Mux(ma_st(w), rocket.Causes.misaligned_store.U,\n Mux(pf_ld(w), rocket.Causes.load_page_fault.U,\n Mux(pf_st(w), rocket.Causes.store_page_fault.U,\n Mux(ae_ld(w), rocket.Causes.load_access.U,\n rocket.Causes.store_access.U)))))))\n val mem_xcpt_vaddrs = RegNext(exe_tlb_vaddr)\n\n for (w <- 0 until memWidth) {\n assert (!(dtlb.io.req(w).valid && exe_tlb_uop(w).is_fence), \"Fence is pretending to talk to the TLB\")\n assert (!((will_fire_load_incoming(w) || will_fire_sta_incoming(w) || will_fire_stad_incoming(w)) &&\n exe_req(w).bits.mxcpt.valid && dtlb.io.req(w).valid &&\n !(exe_tlb_uop(w).ctrl.is_load || exe_tlb_uop(w).ctrl.is_sta)),\n \"A uop that's not a load or store-address is throwing a memory exception.\")\n }\n\n mem_xcpt_valid := mem_xcpt_valids.reduce(_||_)\n mem_xcpt_cause := mem_xcpt_causes(0)\n mem_xcpt_uop := mem_xcpt_uops(0)\n mem_xcpt_vaddr := mem_xcpt_vaddrs(0)\n var xcpt_found = mem_xcpt_valids(0)\n var oldest_xcpt_rob_idx = mem_xcpt_uops(0).rob_idx\n for (w <- 1 until memWidth) {\n val is_older = WireInit(false.B)\n when (mem_xcpt_valids(w) &&\n (IsOlder(mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx, io.core.rob_head_idx) || !xcpt_found)) {\n is_older := true.B\n mem_xcpt_cause := mem_xcpt_causes(w)\n mem_xcpt_uop := mem_xcpt_uops(w)\n mem_xcpt_vaddr := mem_xcpt_vaddrs(w)\n }\n xcpt_found = xcpt_found || mem_xcpt_valids(w)\n oldest_xcpt_rob_idx = Mux(is_older, mem_xcpt_uops(w).rob_idx, oldest_xcpt_rob_idx)\n }\n\n val exe_tlb_miss = widthMap(w => dtlb.io.req(w).valid && (dtlb.io.resp(w).miss || !dtlb.io.req(w).ready))\n val exe_tlb_paddr = widthMap(w => Cat(dtlb.io.resp(w).paddr(paddrBits-1,corePgIdxBits),\n exe_tlb_vaddr(w)(corePgIdxBits-1,0)))\n val exe_tlb_uncacheable = widthMap(w => !(dtlb.io.resp(w).cacheable))\n\n for (w <- 0 until memWidth) {\n assert (exe_tlb_paddr(w) === dtlb.io.resp(w).paddr || exe_req(w).bits.sfence.valid, \"[lsu] paddrs should match.\")\n\n when (mem_xcpt_valids(w))\n {\n assert(RegNext(will_fire_load_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_incoming(w) ||\n will_fire_load_retry(w) || will_fire_sta_retry(w)))\n // Technically only faulting AMOs need this\n assert(mem_xcpt_uops(w).uses_ldq ^ mem_xcpt_uops(w).uses_stq)\n when (mem_xcpt_uops(w).uses_ldq)\n {\n ldq(mem_xcpt_uops(w).ldq_idx).bits.uop.exception := true.B\n }\n .otherwise\n {\n stq(mem_xcpt_uops(w).stq_idx).bits.uop.exception := true.B\n }\n }\n }\n\n\n\n //------------------------------\n // Issue Someting to Memory\n //\n // A memory op can come from many different places\n // The address either was freshly translated, or we are\n // reading a physical address from the LDQ,STQ, or the HellaCache adapter\n\n\n // defaults\n io.dmem.brupdate := io.core.brupdate\n io.dmem.exception := io.core.exception\n io.dmem.rob_head_idx := io.core.rob_head_idx\n io.dmem.rob_pnr_idx := io.core.rob_pnr_idx\n\n val dmem_req = Wire(Vec(memWidth, Valid(new BoomDCacheReq)))\n io.dmem.req.valid := dmem_req.map(_.valid).reduce(_||_)\n io.dmem.req.bits := dmem_req\n val dmem_req_fire = widthMap(w => dmem_req(w).valid && io.dmem.req.fire)\n\n val s0_executing_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B)))\n\n\n for (w <- 0 until memWidth) {\n dmem_req(w).valid := false.B\n dmem_req(w).bits.uop := NullMicroOp\n dmem_req(w).bits.addr := 0.U\n dmem_req(w).bits.data := 0.U\n dmem_req(w).bits.is_hella := false.B\n\n io.dmem.s1_kill(w) := false.B\n\n when (will_fire_load_incoming(w)) {\n dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.uop := exe_tlb_uop(w)\n\n s0_executing_loads(ldq_incoming_idx(w)) := dmem_req_fire(w)\n assert(!ldq_incoming_e(w).bits.executed)\n } .elsewhen (will_fire_load_retry(w)) {\n dmem_req(w).valid := !exe_tlb_miss(w) && !exe_tlb_uncacheable(w)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.uop := exe_tlb_uop(w)\n\n s0_executing_loads(ldq_retry_idx) := dmem_req_fire(w)\n assert(!ldq_retry_e.bits.executed)\n } .elsewhen (will_fire_store_commit(w)) {\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := stq_commit_e.bits.addr.bits\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n stq_commit_e.bits.uop.mem_size, 0.U,\n stq_commit_e.bits.data.bits,\n coreDataBytes)).data\n dmem_req(w).bits.uop := stq_commit_e.bits.uop\n\n stq_execute_head := Mux(dmem_req_fire(w),\n WrapInc(stq_execute_head, numStqEntries),\n stq_execute_head)\n\n stq(stq_execute_head).bits.succeeded := false.B\n } .elsewhen (will_fire_load_wakeup(w)) {\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := ldq_wakeup_e.bits.addr.bits\n dmem_req(w).bits.uop := ldq_wakeup_e.bits.uop\n\n s0_executing_loads(ldq_wakeup_idx) := dmem_req_fire(w)\n\n assert(!ldq_wakeup_e.bits.executed && !ldq_wakeup_e.bits.addr_is_virtual)\n } .elsewhen (will_fire_hella_incoming(w)) {\n assert(hella_state === h_s1)\n\n dmem_req(w).valid := !io.hellacache.s1_kill && (!exe_tlb_miss(w) || hella_req.phys)\n dmem_req(w).bits.addr := exe_tlb_paddr(w)\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n hella_req.size, 0.U,\n io.hellacache.s1_data.data,\n coreDataBytes)).data\n dmem_req(w).bits.uop.mem_cmd := hella_req.cmd\n dmem_req(w).bits.uop.mem_size := hella_req.size\n dmem_req(w).bits.uop.mem_signed := hella_req.signed\n dmem_req(w).bits.is_hella := true.B\n\n hella_paddr := exe_tlb_paddr(w)\n }\n .elsewhen (will_fire_hella_wakeup(w))\n {\n assert(hella_state === h_replay)\n dmem_req(w).valid := true.B\n dmem_req(w).bits.addr := hella_paddr\n dmem_req(w).bits.data := (new freechips.rocketchip.rocket.StoreGen(\n hella_req.size, 0.U,\n hella_data.data,\n coreDataBytes)).data\n dmem_req(w).bits.uop.mem_cmd := hella_req.cmd\n dmem_req(w).bits.uop.mem_size := hella_req.size\n dmem_req(w).bits.uop.mem_signed := hella_req.signed\n dmem_req(w).bits.is_hella := true.B\n }\n\n //-------------------------------------------------------------\n // Write Addr into the LAQ/SAQ\n when (will_fire_load_incoming(w) || will_fire_load_retry(w))\n {\n val ldq_idx = Mux(will_fire_load_incoming(w), ldq_incoming_idx(w), ldq_retry_idx)\n ldq(ldq_idx).bits.addr.valid := true.B\n ldq(ldq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))\n ldq(ldq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst\n ldq(ldq_idx).bits.addr_is_virtual := exe_tlb_miss(w)\n ldq(ldq_idx).bits.addr_is_uncacheable := exe_tlb_uncacheable(w) && !exe_tlb_miss(w)\n\n assert(!(will_fire_load_incoming(w) && ldq_incoming_e(w).bits.addr.valid),\n \"[lsu] Incoming load is overwriting a valid address\")\n }\n\n when (will_fire_sta_incoming(w) || will_fire_stad_incoming(w) || will_fire_sta_retry(w))\n {\n val stq_idx = Mux(will_fire_sta_incoming(w) || will_fire_stad_incoming(w),\n stq_incoming_idx(w), stq_retry_idx)\n\n stq(stq_idx).bits.addr.valid := !pf_st(w) // Prevent AMOs from executing!\n stq(stq_idx).bits.addr.bits := Mux(exe_tlb_miss(w), exe_tlb_vaddr(w), exe_tlb_paddr(w))\n stq(stq_idx).bits.uop.pdst := exe_tlb_uop(w).pdst // Needed for AMOs\n stq(stq_idx).bits.addr_is_virtual := exe_tlb_miss(w)\n\n assert(!(will_fire_sta_incoming(w) && stq_incoming_e(w).bits.addr.valid),\n \"[lsu] Incoming store is overwriting a valid address\")\n\n }\n\n //-------------------------------------------------------------\n // Write data into the STQ\n if (w == 0)\n io.core.fp_stdata.ready := !will_fire_std_incoming(w) && !will_fire_stad_incoming(w)\n val fp_stdata_fire = io.core.fp_stdata.fire && (w == 0).B\n when (will_fire_std_incoming(w) || will_fire_stad_incoming(w) || fp_stdata_fire)\n {\n val sidx = Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),\n stq_incoming_idx(w),\n io.core.fp_stdata.bits.uop.stq_idx)\n stq(sidx).bits.data.valid := true.B\n stq(sidx).bits.data.bits := Mux(will_fire_std_incoming(w) || will_fire_stad_incoming(w),\n exe_req(w).bits.data,\n io.core.fp_stdata.bits.data)\n assert(!(stq(sidx).bits.data.valid),\n \"[lsu] Incoming store is overwriting a valid data entry\")\n }\n }\n val will_fire_stdf_incoming = io.core.fp_stdata.fire\n require (xLen >= fLen) // for correct SDQ size\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Cache Access Cycle (Mem)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Note the DCache may not have accepted our request\n\n val exe_req_killed = widthMap(w => IsKilledByBranch(io.core.brupdate, exe_req(w).bits.uop))\n val stdf_killed = IsKilledByBranch(io.core.brupdate, io.core.fp_stdata.bits.uop)\n\n val fired_load_incoming = widthMap(w => RegNext(will_fire_load_incoming(w) && !exe_req_killed(w)))\n val fired_stad_incoming = widthMap(w => RegNext(will_fire_stad_incoming(w) && !exe_req_killed(w)))\n val fired_sta_incoming = widthMap(w => RegNext(will_fire_sta_incoming (w) && !exe_req_killed(w)))\n val fired_std_incoming = widthMap(w => RegNext(will_fire_std_incoming (w) && !exe_req_killed(w)))\n val fired_stdf_incoming = RegNext(will_fire_stdf_incoming && !stdf_killed)\n val fired_sfence = RegNext(will_fire_sfence)\n val fired_release = RegNext(will_fire_release)\n val fired_load_retry = widthMap(w => RegNext(will_fire_load_retry (w) && !IsKilledByBranch(io.core.brupdate, ldq_retry_e.bits.uop)))\n val fired_sta_retry = widthMap(w => RegNext(will_fire_sta_retry (w) && !IsKilledByBranch(io.core.brupdate, stq_retry_e.bits.uop)))\n val fired_store_commit = RegNext(will_fire_store_commit)\n val fired_load_wakeup = widthMap(w => RegNext(will_fire_load_wakeup (w) && !IsKilledByBranch(io.core.brupdate, ldq_wakeup_e.bits.uop)))\n val fired_hella_incoming = RegNext(will_fire_hella_incoming)\n val fired_hella_wakeup = RegNext(will_fire_hella_wakeup)\n\n val mem_incoming_uop = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, exe_req(w).bits.uop)))\n val mem_ldq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, ldq_incoming_e(w))))\n val mem_stq_incoming_e = RegNext(widthMap(w => UpdateBrMask(io.core.brupdate, stq_incoming_e(w))))\n val mem_ldq_wakeup_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_wakeup_e))\n val mem_ldq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, ldq_retry_e))\n val mem_stq_retry_e = RegNext(UpdateBrMask(io.core.brupdate, stq_retry_e))\n val mem_ldq_e = widthMap(w =>\n Mux(fired_load_incoming(w), mem_ldq_incoming_e(w),\n Mux(fired_load_retry (w), mem_ldq_retry_e,\n Mux(fired_load_wakeup (w), mem_ldq_wakeup_e, (0.U).asTypeOf(Valid(new LDQEntry))))))\n val mem_stq_e = widthMap(w =>\n Mux(fired_stad_incoming(w) ||\n fired_sta_incoming (w), mem_stq_incoming_e(w),\n Mux(fired_sta_retry (w), mem_stq_retry_e, (0.U).asTypeOf(Valid(new STQEntry)))))\n val mem_stdf_uop = RegNext(UpdateBrMask(io.core.brupdate, io.core.fp_stdata.bits.uop))\n\n\n val mem_tlb_miss = RegNext(exe_tlb_miss)\n val mem_tlb_uncacheable = RegNext(exe_tlb_uncacheable)\n val mem_paddr = RegNext(widthMap(w => dmem_req(w).bits.addr))\n\n // Task 1: Clr ROB busy bit\n val clr_bsy_valid = RegInit(widthMap(w => false.B))\n val clr_bsy_rob_idx = Reg(Vec(memWidth, UInt(robAddrSz.W)))\n val clr_bsy_brmask = Reg(Vec(memWidth, UInt(maxBrCount.W)))\n\n for (w <- 0 until memWidth) {\n clr_bsy_valid (w) := false.B\n clr_bsy_rob_idx (w) := 0.U\n clr_bsy_brmask (w) := 0.U\n\n\n when (fired_stad_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_sta_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n mem_stq_incoming_e(w).bits.data.valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_std_incoming(w)) {\n clr_bsy_valid (w) := mem_stq_incoming_e(w).valid &&\n mem_stq_incoming_e(w).bits.addr.valid &&\n !mem_stq_incoming_e(w).bits.addr_is_virtual &&\n !mem_stq_incoming_e(w).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_incoming_e(w).bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_incoming_e(w).bits.uop)\n } .elsewhen (fired_sfence(w)) {\n clr_bsy_valid (w) := (w == 0).B // SFence proceeds down all paths, only allow one to clr the rob\n clr_bsy_rob_idx (w) := mem_incoming_uop(w).rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_incoming_uop(w))\n } .elsewhen (fired_sta_retry(w)) {\n clr_bsy_valid (w) := mem_stq_retry_e.valid &&\n mem_stq_retry_e.bits.data.valid &&\n !mem_tlb_miss(w) &&\n !mem_stq_retry_e.bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stq_retry_e.bits.uop)\n clr_bsy_rob_idx (w) := mem_stq_retry_e.bits.uop.rob_idx\n clr_bsy_brmask (w) := GetNewBrMask(io.core.brupdate, mem_stq_retry_e.bits.uop)\n }\n\n io.core.clr_bsy(w).valid := clr_bsy_valid(w) &&\n !IsKilledByBranch(io.core.brupdate, clr_bsy_brmask(w)) &&\n !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))\n io.core.clr_bsy(w).bits := clr_bsy_rob_idx(w)\n }\n\n val stdf_clr_bsy_valid = RegInit(false.B)\n val stdf_clr_bsy_rob_idx = Reg(UInt(robAddrSz.W))\n val stdf_clr_bsy_brmask = Reg(UInt(maxBrCount.W))\n stdf_clr_bsy_valid := false.B\n stdf_clr_bsy_rob_idx := 0.U\n stdf_clr_bsy_brmask := 0.U\n when (fired_stdf_incoming) {\n val s_idx = mem_stdf_uop.stq_idx\n stdf_clr_bsy_valid := stq(s_idx).valid &&\n stq(s_idx).bits.addr.valid &&\n !stq(s_idx).bits.addr_is_virtual &&\n !stq(s_idx).bits.uop.is_amo &&\n !IsKilledByBranch(io.core.brupdate, mem_stdf_uop)\n stdf_clr_bsy_rob_idx := mem_stdf_uop.rob_idx\n stdf_clr_bsy_brmask := GetNewBrMask(io.core.brupdate, mem_stdf_uop)\n }\n\n\n\n io.core.clr_bsy(memWidth).valid := stdf_clr_bsy_valid &&\n !IsKilledByBranch(io.core.brupdate, stdf_clr_bsy_brmask) &&\n !io.core.exception && !RegNext(io.core.exception) && !RegNext(RegNext(io.core.exception))\n io.core.clr_bsy(memWidth).bits := stdf_clr_bsy_rob_idx\n\n\n\n // Task 2: Do LD-LD. ST-LD searches for ordering failures\n // Do LD-ST search for forwarding opportunities\n // We have the opportunity to kill a request we sent last cycle. Use it wisely!\n\n // We translated a store last cycle\n val do_st_search = widthMap(w => (fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w)) && !mem_tlb_miss(w))\n // We translated a load last cycle\n val do_ld_search = widthMap(w => ((fired_load_incoming(w) || fired_load_retry(w)) && !mem_tlb_miss(w)) ||\n fired_load_wakeup(w))\n // We are making a local line visible to other harts\n val do_release_search = widthMap(w => fired_release(w))\n\n // Store addrs don't go to memory yet, get it from the TLB response\n // Load wakeups don't go through TLB, get it through memory\n // Load incoming and load retries go through both\n\n val lcam_addr = widthMap(w => Mux(fired_stad_incoming(w) || fired_sta_incoming(w) || fired_sta_retry(w),\n RegNext(exe_tlb_paddr(w)),\n Mux(fired_release(w), RegNext(io.dmem.release.bits.address),\n mem_paddr(w))))\n val lcam_uop = widthMap(w => Mux(do_st_search(w), mem_stq_e(w).bits.uop,\n Mux(do_ld_search(w), mem_ldq_e(w).bits.uop, NullMicroOp)))\n\n val lcam_mask = widthMap(w => GenByteMask(lcam_addr(w), lcam_uop(w).mem_size))\n val lcam_st_dep_mask = widthMap(w => mem_ldq_e(w).bits.st_dep_mask)\n val lcam_is_release = widthMap(w => fired_release(w))\n val lcam_ldq_idx = widthMap(w =>\n Mux(fired_load_incoming(w), mem_incoming_uop(w).ldq_idx,\n Mux(fired_load_wakeup (w), RegNext(ldq_wakeup_idx),\n Mux(fired_load_retry (w), RegNext(ldq_retry_idx), 0.U))))\n val lcam_stq_idx = widthMap(w =>\n Mux(fired_stad_incoming(w) ||\n fired_sta_incoming (w), mem_incoming_uop(w).stq_idx,\n Mux(fired_sta_retry (w), RegNext(stq_retry_idx), 0.U)))\n\n val can_forward = WireInit(widthMap(w =>\n Mux(fired_load_incoming(w) || fired_load_retry(w), !mem_tlb_uncacheable(w),\n !ldq(lcam_ldq_idx(w)).bits.addr_is_uncacheable)))\n\n // Mask of stores which we conflict on address with\n val ldst_addr_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))\n // Mask of stores which we can forward from\n val ldst_forward_matches = WireInit(widthMap(w => VecInit((0 until numStqEntries).map(x=>false.B))))\n\n val failed_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which we will report as failures (throws a mini-exception)\n val nacking_loads = WireInit(VecInit((0 until numLdqEntries).map(x=>false.B))) // Loads which are being nacked by dcache in the next stage\n\n val s1_executing_loads = RegNext(s0_executing_loads)\n val s1_set_execute = WireInit(s1_executing_loads)\n\n val mem_forward_valid = Wire(Vec(memWidth, Bool()))\n val mem_forward_ldq_idx = lcam_ldq_idx\n val mem_forward_ld_addr = lcam_addr\n val mem_forward_stq_idx = Wire(Vec(memWidth, UInt(log2Ceil(numStqEntries).W)))\n\n val wb_forward_valid = RegNext(mem_forward_valid)\n val wb_forward_ldq_idx = RegNext(mem_forward_ldq_idx)\n val wb_forward_ld_addr = RegNext(mem_forward_ld_addr)\n val wb_forward_stq_idx = RegNext(mem_forward_stq_idx)\n\n for (i <- 0 until numLdqEntries) {\n val l_valid = ldq(i).valid\n val l_bits = ldq(i).bits\n val l_addr = ldq(i).bits.addr.bits\n val l_mask = GenByteMask(l_addr, l_bits.uop.mem_size)\n\n val l_forwarders = widthMap(w => wb_forward_valid(w) && wb_forward_ldq_idx(w) === i.U)\n val l_is_forwarding = l_forwarders.reduce(_||_)\n val l_forward_stq_idx = Mux(l_is_forwarding, Mux1H(l_forwarders, wb_forward_stq_idx), l_bits.forward_stq_idx)\n\n\n val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits)\n val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3))\n val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask)\n val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR)\n\n // Searcher is a store\n for (w <- 0 until memWidth) {\n\n when (do_release_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n block_addr_matches(w)) {\n // This load has been observed, so if a younger load to the same address has not\n // executed yet, this load must be squashed\n ldq(i).bits.observed := true.B\n } .elsewhen (do_st_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n (l_bits.executed || l_bits.succeeded || l_is_forwarding) &&\n !l_bits.addr_is_virtual &&\n l_bits.st_dep_mask(lcam_stq_idx(w)) &&\n dword_addr_matches(w) &&\n mask_overlap(w)) {\n\n val forwarded_is_older = IsOlder(l_forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx)\n // We are older than this load, which overlapped us.\n when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed\n ((l_forward_stq_idx =/= lcam_stq_idx(w)) && forwarded_is_older)) { // If the load forwarded from us, we might be ok\n ldq(i).bits.order_fail := true.B\n failed_loads(i) := true.B\n }\n } .elsewhen (do_ld_search(w) &&\n l_valid &&\n l_bits.addr.valid &&\n !l_bits.addr_is_virtual &&\n dword_addr_matches(w) &&\n mask_overlap(w)) {\n val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head)\n when (searcher_is_older) {\n when ((l_bits.executed || l_bits.succeeded || l_is_forwarding) &&\n !s1_executing_loads(i) && // If the load is proceeding in parallel we don't need to kill it\n l_bits.observed) { // Its only a ordering failure if the cache line was observed between the younger load and us\n ldq(i).bits.order_fail := true.B\n failed_loads(i) := true.B\n }\n } .elsewhen (lcam_ldq_idx(w) =/= i.U) {\n // The load is older, and either it hasn't executed, it was nacked, or it is ignoring its response\n // we need to kill ourselves, and prevent forwarding\n val older_nacked = nacking_loads(i) || RegNext(nacking_loads(i))\n when (!(l_bits.executed || l_bits.succeeded) || older_nacked) {\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n can_forward(w) := false.B\n }\n }\n }\n }\n }\n\n for (i <- 0 until numStqEntries) {\n val s_addr = stq(i).bits.addr.bits\n val s_uop = stq(i).bits.uop\n val dword_addr_matches = widthMap(w =>\n ( stq(i).bits.addr.valid &&\n !stq(i).bits.addr_is_virtual &&\n (s_addr(corePAddrBits-1,3) === lcam_addr(w)(corePAddrBits-1,3))))\n val write_mask = GenByteMask(s_addr, s_uop.mem_size)\n for (w <- 0 until memWidth) {\n when (do_ld_search(w) && stq(i).valid && lcam_st_dep_mask(w)(i)) {\n when (((lcam_mask(w) & write_mask) === lcam_mask(w)) && !s_uop.is_fence && !s_uop.is_amo && dword_addr_matches(w) && can_forward(w))\n {\n ldst_addr_matches(w)(i) := true.B\n ldst_forward_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n .elsewhen (((lcam_mask(w) & write_mask) =/= 0.U) && dword_addr_matches(w))\n {\n ldst_addr_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n .elsewhen (s_uop.is_fence || s_uop.is_amo)\n {\n ldst_addr_matches(w)(i) := true.B\n io.dmem.s1_kill(w) := RegNext(dmem_req_fire(w))\n s1_set_execute(lcam_ldq_idx(w)) := false.B\n }\n }\n }\n }\n\n // Set execute bit in LDQ\n for (i <- 0 until numLdqEntries) {\n when (s1_set_execute(i)) { ldq(i).bits.executed := true.B }\n }\n\n // Find the youngest store which the load is dependent on\n val forwarding_age_logic = Seq.fill(memWidth) { Module(new ForwardingAgeLogic(numStqEntries)) }\n for (w <- 0 until memWidth) {\n forwarding_age_logic(w).io.addr_matches := ldst_addr_matches(w).asUInt\n forwarding_age_logic(w).io.youngest_st_idx := lcam_uop(w).stq_idx\n }\n val forwarding_idx = widthMap(w => forwarding_age_logic(w).io.forwarding_idx)\n\n // Forward if st-ld forwarding is possible from the writemask and loadmask\n mem_forward_valid := widthMap(w =>\n (ldst_forward_matches(w)(forwarding_idx(w)) &&\n !IsKilledByBranch(io.core.brupdate, lcam_uop(w)) &&\n !io.core.exception && !RegNext(io.core.exception)))\n mem_forward_stq_idx := forwarding_idx\n\n // Avoid deadlock with a 1-w LSU prioritizing load wakeups > store commits\n // On a 2W machine, load wakeups and store commits occupy separate pipelines,\n // so only add this logic for 1-w LSU\n if (memWidth == 1) {\n // Wakeups may repeatedly find a st->ld addr conflict and fail to forward,\n // repeated wakeups may block the store from ever committing\n // Disallow load wakeups 1 cycle after this happens to allow the stores to drain\n when (RegNext(ldst_addr_matches(0).reduce(_||_) && !mem_forward_valid(0))) {\n block_load_wakeup := true.B\n }\n\n // If stores remain blocked for 15 cycles, block load wakeups to get a store through\n val store_blocked_counter = Reg(UInt(4.W))\n when (will_fire_store_commit(0) || !can_fire_store_commit(0)) {\n store_blocked_counter := 0.U\n } .elsewhen (can_fire_store_commit(0) && !will_fire_store_commit(0)) {\n store_blocked_counter := Mux(store_blocked_counter === 15.U, 15.U, store_blocked_counter + 1.U)\n }\n when (store_blocked_counter === 15.U) {\n block_load_wakeup := true.B\n }\n }\n\n\n // Task 3: Clr unsafe bit in ROB for succesful translations\n // Delay this a cycle to avoid going ahead of the exception broadcast\n // The unsafe bit is cleared on the first translation, so no need to fire for load wakeups\n for (w <- 0 until memWidth) {\n io.core.clr_unsafe(w).valid := RegNext((do_st_search(w) || do_ld_search(w)) && !fired_load_wakeup(w)) && false.B\n io.core.clr_unsafe(w).bits := RegNext(lcam_uop(w).rob_idx)\n }\n\n // detect which loads get marked as failures, but broadcast to the ROB the oldest failing load\n // TODO encapsulate this in an age-based priority-encoder\n // val l_idx = AgePriorityEncoder((Vec(Vec.tabulate(numLdqEntries)(i => failed_loads(i) && i.U >= laq_head)\n // ++ failed_loads)).asUInt)\n val temp_bits = (VecInit(VecInit.tabulate(numLdqEntries)(i =>\n failed_loads(i) && i.U >= ldq_head) ++ failed_loads)).asUInt\n val l_idx = PriorityEncoder(temp_bits)\n\n // one exception port, but multiple causes!\n // - 1) the incoming store-address finds a faulting load (it is by definition younger)\n // - 2) the incoming load or store address is excepting. It must be older and thus takes precedent.\n val r_xcpt_valid = RegInit(false.B)\n val r_xcpt = Reg(new Exception)\n\n val ld_xcpt_valid = failed_loads.reduce(_|_)\n val ld_xcpt_uop = ldq(Mux(l_idx >= numLdqEntries.U, l_idx - numLdqEntries.U, l_idx)).bits.uop\n\n val use_mem_xcpt = (mem_xcpt_valid && IsOlder(mem_xcpt_uop.rob_idx, ld_xcpt_uop.rob_idx, io.core.rob_head_idx)) || !ld_xcpt_valid\n\n val xcpt_uop = Mux(use_mem_xcpt, mem_xcpt_uop, ld_xcpt_uop)\n\n r_xcpt_valid := (ld_xcpt_valid || mem_xcpt_valid) &&\n !io.core.exception &&\n !IsKilledByBranch(io.core.brupdate, xcpt_uop)\n r_xcpt.uop := xcpt_uop\n r_xcpt.uop.br_mask := GetNewBrMask(io.core.brupdate, xcpt_uop)\n r_xcpt.cause := Mux(use_mem_xcpt, mem_xcpt_cause, MINI_EXCEPTION_MEM_ORDERING)\n r_xcpt.badvaddr := mem_xcpt_vaddr // TODO is there another register we can use instead?\n\n io.core.lxcpt.valid := r_xcpt_valid && !io.core.exception && !IsKilledByBranch(io.core.brupdate, r_xcpt.uop)\n io.core.lxcpt.bits := r_xcpt\n\n // Task 4: Speculatively wakeup loads 1 cycle before they come back\n for (w <- 0 until memWidth) {\n io.core.spec_ld_wakeup(w).valid := enableFastLoadUse.B &&\n fired_load_incoming(w) &&\n !mem_incoming_uop(w).fp_val &&\n mem_incoming_uop(w).pdst =/= 0.U\n io.core.spec_ld_wakeup(w).bits := mem_incoming_uop(w).pdst\n }\n\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // Writeback Cycle (St->Ld Forwarding Path)\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Handle Memory Responses and nacks\n //----------------------------------\n for (w <- 0 until memWidth) {\n io.core.exe(w).iresp.valid := false.B\n io.core.exe(w).iresp.bits := DontCare\n io.core.exe(w).fresp.valid := false.B\n io.core.exe(w).fresp.bits := DontCare\n }\n\n val dmem_resp_fired = WireInit(widthMap(w => false.B))\n\n for (w <- 0 until memWidth) {\n // Handle nacks\n when (io.dmem.nack(w).valid)\n {\n // We have to re-execute this!\n when (io.dmem.nack(w).bits.is_hella)\n {\n assert(hella_state === h_wait || hella_state === h_dead)\n }\n .elsewhen (io.dmem.nack(w).bits.uop.uses_ldq)\n {\n assert(ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed)\n ldq(io.dmem.nack(w).bits.uop.ldq_idx).bits.executed := false.B\n nacking_loads(io.dmem.nack(w).bits.uop.ldq_idx) := true.B\n }\n .otherwise\n {\n assert(io.dmem.nack(w).bits.uop.uses_stq)\n when (IsOlder(io.dmem.nack(w).bits.uop.stq_idx, stq_execute_head, stq_head)) {\n stq_execute_head := io.dmem.nack(w).bits.uop.stq_idx\n }\n }\n }\n // Handle the response\n when (io.dmem.resp(w).valid)\n {\n when (io.dmem.resp(w).bits.uop.uses_ldq)\n {\n assert(!io.dmem.resp(w).bits.is_hella)\n val ldq_idx = io.dmem.resp(w).bits.uop.ldq_idx\n val send_iresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FIX\n val send_fresp = ldq(ldq_idx).bits.uop.dst_rtype === RT_FLT\n\n io.core.exe(w).iresp.bits.uop := ldq(ldq_idx).bits.uop\n io.core.exe(w).fresp.bits.uop := ldq(ldq_idx).bits.uop\n io.core.exe(w).iresp.valid := send_iresp\n io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data\n io.core.exe(w).fresp.valid := send_fresp\n io.core.exe(w).fresp.bits.data := io.dmem.resp(w).bits.data\n\n assert(send_iresp ^ send_fresp)\n dmem_resp_fired(w) := true.B\n\n ldq(ldq_idx).bits.succeeded := io.core.exe(w).iresp.valid || io.core.exe(w).fresp.valid\n ldq(ldq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data\n }\n .elsewhen (io.dmem.resp(w).bits.uop.uses_stq)\n {\n assert(!io.dmem.resp(w).bits.is_hella)\n stq(io.dmem.resp(w).bits.uop.stq_idx).bits.succeeded := true.B\n when (io.dmem.resp(w).bits.uop.is_amo) {\n dmem_resp_fired(w) := true.B\n io.core.exe(w).iresp.valid := true.B\n io.core.exe(w).iresp.bits.uop := stq(io.dmem.resp(w).bits.uop.stq_idx).bits.uop\n io.core.exe(w).iresp.bits.data := io.dmem.resp(w).bits.data\n\n stq(io.dmem.resp(w).bits.uop.stq_idx).bits.debug_wb_data := io.dmem.resp(w).bits.data\n }\n }\n }\n\n\n when (dmem_resp_fired(w) && wb_forward_valid(w))\n {\n // Twiddle thumbs. Can't forward because dcache response takes precedence\n }\n .elsewhen (!dmem_resp_fired(w) && wb_forward_valid(w))\n {\n val f_idx = wb_forward_ldq_idx(w)\n val forward_uop = ldq(f_idx).bits.uop\n val stq_e = stq(wb_forward_stq_idx(w))\n val data_ready = stq_e.bits.data.valid\n val live = !IsKilledByBranch(io.core.brupdate, forward_uop)\n val storegen = new freechips.rocketchip.rocket.StoreGen(\n stq_e.bits.uop.mem_size, stq_e.bits.addr.bits,\n stq_e.bits.data.bits, coreDataBytes)\n val loadgen = new freechips.rocketchip.rocket.LoadGen(\n forward_uop.mem_size, forward_uop.mem_signed,\n wb_forward_ld_addr(w),\n storegen.data, false.B, coreDataBytes)\n\n io.core.exe(w).iresp.valid := (forward_uop.dst_rtype === RT_FIX) && data_ready && live\n io.core.exe(w).fresp.valid := (forward_uop.dst_rtype === RT_FLT) && data_ready && live\n io.core.exe(w).iresp.bits.uop := forward_uop\n io.core.exe(w).fresp.bits.uop := forward_uop\n io.core.exe(w).iresp.bits.data := loadgen.data\n io.core.exe(w).fresp.bits.data := loadgen.data\n\n when (data_ready && live) {\n ldq(f_idx).bits.succeeded := data_ready\n ldq(f_idx).bits.forward_std_val := true.B\n ldq(f_idx).bits.forward_stq_idx := wb_forward_stq_idx(w)\n\n ldq(f_idx).bits.debug_wb_data := loadgen.data\n }\n }\n }\n\n // Initially assume the speculative load wakeup failed\n io.core.ld_miss := RegNext(io.core.spec_ld_wakeup.map(_.valid).reduce(_||_))\n val spec_ld_succeed = widthMap(w =>\n !RegNext(io.core.spec_ld_wakeup(w).valid) ||\n (io.core.exe(w).iresp.valid &&\n io.core.exe(w).iresp.bits.uop.ldq_idx === RegNext(mem_incoming_uop(w).ldq_idx)\n )\n ).reduce(_&&_)\n when (spec_ld_succeed) {\n io.core.ld_miss := false.B\n }\n\n\n //-------------------------------------------------------------\n // Kill speculated entries on branch mispredict\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n // Kill stores\n val st_brkilled_mask = Wire(Vec(numStqEntries, Bool()))\n for (i <- 0 until numStqEntries)\n {\n st_brkilled_mask(i) := false.B\n\n when (stq(i).valid)\n {\n stq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, stq(i).bits.uop.br_mask)\n\n when (IsKilledByBranch(io.core.brupdate, stq(i).bits.uop))\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n st_brkilled_mask(i) := true.B\n }\n }\n\n assert (!(IsKilledByBranch(io.core.brupdate, stq(i).bits.uop) && stq(i).valid && stq(i).bits.committed),\n \"Branch is trying to clear a committed store.\")\n }\n\n // Kill loads\n for (i <- 0 until numLdqEntries)\n {\n when (ldq(i).valid)\n {\n ldq(i).bits.uop.br_mask := GetNewBrMask(io.core.brupdate, ldq(i).bits.uop.br_mask)\n when (IsKilledByBranch(io.core.brupdate, ldq(i).bits.uop))\n {\n ldq(i).valid := false.B\n ldq(i).bits.addr.valid := false.B\n }\n }\n }\n\n //-------------------------------------------------------------\n when (io.core.brupdate.b2.mispredict && !io.core.exception)\n {\n stq_tail := io.core.brupdate.b2.uop.stq_idx\n ldq_tail := io.core.brupdate.b2.uop.ldq_idx\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // dequeue old entries on commit\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n var temp_stq_commit_head = stq_commit_head\n var temp_ldq_head = ldq_head\n for (w <- 0 until coreWidth)\n {\n val commit_store = io.core.commit.valids(w) && io.core.commit.uops(w).uses_stq\n val commit_load = io.core.commit.valids(w) && io.core.commit.uops(w).uses_ldq\n val idx = Mux(commit_store, temp_stq_commit_head, temp_ldq_head)\n when (commit_store)\n {\n stq(idx).bits.committed := true.B\n } .elsewhen (commit_load) {\n assert (ldq(idx).valid, \"[lsu] trying to commit an un-allocated load entry.\")\n assert ((ldq(idx).bits.executed || ldq(idx).bits.forward_std_val) && ldq(idx).bits.succeeded ,\n \"[lsu] trying to commit an un-executed load entry.\")\n\n ldq(idx).valid := false.B\n ldq(idx).bits.addr.valid := false.B\n ldq(idx).bits.executed := false.B\n ldq(idx).bits.succeeded := false.B\n ldq(idx).bits.order_fail := false.B\n ldq(idx).bits.forward_std_val := false.B\n\n }\n\n if (MEMTRACE_PRINTF) {\n when (commit_store || commit_load) {\n val uop = Mux(commit_store, stq(idx).bits.uop, ldq(idx).bits.uop)\n val addr = Mux(commit_store, stq(idx).bits.addr.bits, ldq(idx).bits.addr.bits)\n val stdata = Mux(commit_store, stq(idx).bits.data.bits, 0.U)\n val wbdata = Mux(commit_store, stq(idx).bits.debug_wb_data, ldq(idx).bits.debug_wb_data)\n printf(\"MT %x %x %x %x %x %x %x\\n\",\n io.core.tsc_reg, uop.uopc, uop.mem_cmd, uop.mem_size, addr, stdata, wbdata)\n }\n }\n\n temp_stq_commit_head = Mux(commit_store,\n WrapInc(temp_stq_commit_head, numStqEntries),\n temp_stq_commit_head)\n\n temp_ldq_head = Mux(commit_load,\n WrapInc(temp_ldq_head, numLdqEntries),\n temp_ldq_head)\n }\n stq_commit_head := temp_stq_commit_head\n ldq_head := temp_ldq_head\n\n // store has been committed AND successfully sent data to memory\n when (stq(stq_head).valid && stq(stq_head).bits.committed)\n {\n when (stq(stq_head).bits.uop.is_fence && !io.dmem.ordered) {\n io.dmem.force_order := true.B\n store_needs_order := true.B\n }\n clear_store := Mux(stq(stq_head).bits.uop.is_fence, io.dmem.ordered,\n stq(stq_head).bits.succeeded)\n }\n\n when (clear_store)\n {\n stq(stq_head).valid := false.B\n stq(stq_head).bits.addr.valid := false.B\n stq(stq_head).bits.data.valid := false.B\n stq(stq_head).bits.succeeded := false.B\n stq(stq_head).bits.committed := false.B\n\n stq_head := WrapInc(stq_head, numStqEntries)\n when (stq(stq_head).bits.uop.is_fence)\n {\n stq_execute_head := WrapInc(stq_execute_head, numStqEntries)\n }\n }\n\n\n // -----------------------\n // Hellacache interface\n // We need to time things like a HellaCache would\n io.hellacache.req.ready := false.B\n io.hellacache.s2_nack := false.B\n io.hellacache.s2_xcpt := (0.U).asTypeOf(new rocket.HellaCacheExceptions)\n io.hellacache.resp.valid := false.B\n io.hellacache.store_pending := stq.map(_.valid).reduce(_||_)\n when (hella_state === h_ready) {\n io.hellacache.req.ready := true.B\n when (io.hellacache.req.fire) {\n hella_req := io.hellacache.req.bits\n hella_state := h_s1\n }\n } .elsewhen (hella_state === h_s1) {\n can_fire_hella_incoming(memWidth-1) := true.B\n\n hella_data := io.hellacache.s1_data\n hella_xcpt := dtlb.io.resp(memWidth-1)\n\n when (io.hellacache.s1_kill) {\n when (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_dead\n } .otherwise {\n hella_state := h_ready\n }\n } .elsewhen (will_fire_hella_incoming(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_s2\n } .otherwise {\n hella_state := h_s2_nack\n }\n } .elsewhen (hella_state === h_s2_nack) {\n io.hellacache.s2_nack := true.B\n hella_state := h_ready\n } .elsewhen (hella_state === h_s2) {\n io.hellacache.s2_xcpt := hella_xcpt\n when (io.hellacache.s2_kill || hella_xcpt.asUInt =/= 0.U) {\n hella_state := h_dead\n } .otherwise {\n hella_state := h_wait\n }\n } .elsewhen (hella_state === h_wait) {\n for (w <- 0 until memWidth) {\n when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {\n hella_state := h_ready\n\n io.hellacache.resp.valid := true.B\n io.hellacache.resp.bits.addr := hella_req.addr\n io.hellacache.resp.bits.tag := hella_req.tag\n io.hellacache.resp.bits.cmd := hella_req.cmd\n io.hellacache.resp.bits.signed := hella_req.signed\n io.hellacache.resp.bits.size := hella_req.size\n io.hellacache.resp.bits.data := io.dmem.resp(w).bits.data\n } .elsewhen (io.dmem.nack(w).valid && io.dmem.nack(w).bits.is_hella) {\n hella_state := h_replay\n }\n }\n } .elsewhen (hella_state === h_replay) {\n can_fire_hella_wakeup(memWidth-1) := true.B\n\n when (will_fire_hella_wakeup(memWidth-1) && dmem_req_fire(memWidth-1)) {\n hella_state := h_wait\n }\n } .elsewhen (hella_state === h_dead) {\n for (w <- 0 until memWidth) {\n when (io.dmem.resp(w).valid && io.dmem.resp(w).bits.is_hella) {\n hella_state := h_ready\n }\n }\n }\n\n //-------------------------------------------------------------\n // Exception / Reset\n\n // for the live_store_mask, need to kill stores that haven't been committed\n val st_exc_killed_mask = WireInit(VecInit((0 until numStqEntries).map(x=>false.B)))\n\n when (reset.asBool || io.core.exception)\n {\n ldq_head := 0.U\n ldq_tail := 0.U\n\n when (reset.asBool)\n {\n stq_head := 0.U\n stq_tail := 0.U\n stq_commit_head := 0.U\n stq_execute_head := 0.U\n\n for (i <- 0 until numStqEntries)\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n stq(i).bits.uop := NullMicroOp\n }\n }\n .otherwise // exception\n {\n stq_tail := stq_commit_head\n\n for (i <- 0 until numStqEntries)\n {\n when (!stq(i).bits.committed && !stq(i).bits.succeeded)\n {\n stq(i).valid := false.B\n stq(i).bits.addr.valid := false.B\n stq(i).bits.data.valid := false.B\n st_exc_killed_mask(i) := true.B\n }\n }\n }\n\n for (i <- 0 until numLdqEntries)\n {\n ldq(i).valid := false.B\n ldq(i).bits.addr.valid := false.B\n ldq(i).bits.executed := false.B\n }\n }\n\n //-------------------------------------------------------------\n // Live Store Mask\n // track a bit-array of stores that are alive\n // (could maybe be re-produced from the stq_head/stq_tail, but need to know include spec_killed entries)\n\n // TODO is this the most efficient way to compute the live store mask?\n live_store_mask := next_live_store_mask &\n ~(st_brkilled_mask.asUInt) &\n ~(st_exc_killed_mask.asUInt)\n\n\n}\n\n/**\n * Object to take an address and generate an 8-bit mask of which bytes within a\n * double-word.\n */\nobject GenByteMask\n{\n def apply(addr: UInt, size: UInt): UInt =\n {\n val mask = Wire(UInt(8.W))\n mask := MuxCase(255.U(8.W), Array(\n (size === 0.U) -> (1.U(8.W) << addr(2,0)),\n (size === 1.U) -> (3.U(8.W) << (addr(2,1) << 1.U)),\n (size === 2.U) -> Mux(addr(2), 240.U(8.W), 15.U(8.W)),\n (size === 3.U) -> 255.U(8.W)))\n mask\n }\n}\n\n/**\n * ...\n */\nclass ForwardingAgeLogic(num_entries: Int)(implicit p: Parameters) extends BoomModule()(p)\n{\n val io = IO(new Bundle\n {\n val addr_matches = Input(UInt(num_entries.W)) // bit vector of addresses that match\n // between the load and the SAQ\n val youngest_st_idx = Input(UInt(stqAddrSz.W)) // needed to get \"age\"\n\n val forwarding_val = Output(Bool())\n val forwarding_idx = Output(UInt(stqAddrSz.W))\n })\n\n // generating mask that zeroes out anything younger than tail\n val age_mask = Wire(Vec(num_entries, Bool()))\n for (i <- 0 until num_entries)\n {\n age_mask(i) := true.B\n when (i.U >= io.youngest_st_idx) // currently the tail points PAST last store, so use >=\n {\n age_mask(i) := false.B\n }\n }\n\n // Priority encoder with moving tail: double length\n val matches = Wire(UInt((2*num_entries).W))\n matches := Cat(io.addr_matches & age_mask.asUInt,\n io.addr_matches)\n\n val found_match = Wire(Bool())\n found_match := false.B\n io.forwarding_idx := 0.U\n\n // look for youngest, approach from the oldest side, let the last one found stick\n for (i <- 0 until (2*num_entries))\n {\n when (matches(i))\n {\n found_match := true.B\n io.forwarding_idx := (i % num_entries).U\n }\n }\n\n io.forwarding_val := found_match\n}", + "response": "module ForwardingAgeLogic(\n input [7:0] io_addr_matches,\n input [2:0] io_youngest_st_idx,\n output [2:0] io_forwarding_idx\n);\n\n wire [7:0] _matches_T_1 = io_addr_matches & {1'h0, &io_youngest_st_idx, io_youngest_st_idx > 3'h5, io_youngest_st_idx > 3'h4, io_youngest_st_idx[2], io_youngest_st_idx > 3'h2, |(io_youngest_st_idx[2:1]), |io_youngest_st_idx};\n assign io_forwarding_idx = _matches_T_1[7] ? 3'h7 : _matches_T_1[6] ? 3'h6 : _matches_T_1[5] ? 3'h5 : _matches_T_1[4] ? 3'h4 : _matches_T_1[3] ? 3'h3 : _matches_T_1[2] ? 3'h2 : _matches_T_1[1] ? 3'h1 : _matches_T_1[0] ? 3'h0 : io_addr_matches[7] ? 3'h7 : io_addr_matches[6] ? 3'h6 : io_addr_matches[5] ? 3'h5 : io_addr_matches[4] ? 3'h4 : io_addr_matches[3] ? 3'h3 : io_addr_matches[2] ? 3'h2 : {2'h0, io_addr_matches[1]};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*============================================================================\n\nThis Chisel source file is part of a pre-release version of the HardFloat IEEE\nFloating-Point Arithmetic Package, by John R. Hauser (with some contributions\nfrom Yunsup Lee and Andrew Waterman, mainly concerning testing).\n\nCopyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the\nUniversity of California. All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions, and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions, and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\n 3. Neither the name of the University nor the names of its contributors may\n be used to endorse or promote products derived from this software without\n specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS \"AS IS\", AND ANY\nEXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\nWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE\nDISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY\nDIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\nLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\nON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n=============================================================================*/\n\npackage hardfloat\n\nimport chisel3._\nimport chisel3.util.Fill\nimport consts._\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundAnyRawFNToRecFN(\n inExpWidth: Int,\n inSigWidth: Int,\n outExpWidth: Int,\n outSigWidth: Int,\n options: Int\n )\n extends RawModule\n{\n override def desiredName = s\"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(inExpWidth, inSigWidth))\n // (allowed exponent range has limits)\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((outExpWidth + outSigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)\n val effectiveInSigWidth =\n if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1\n val neverUnderflows =\n ((options &\n (flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)\n ) != 0) ||\n (inExpWidth < outExpWidth)\n val neverOverflows =\n ((options & flRoundOpt_neverOverflows) != 0) ||\n (inExpWidth < outExpWidth)\n val outNaNExp = BigInt(7)<<(outExpWidth - 2)\n val outInfExp = BigInt(6)<<(outExpWidth - 2)\n val outMaxFiniteExp = outInfExp - 1\n val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2\n val outMinNonzeroExp = outMinNormExp - outSigWidth + 1\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val roundingMode_near_even = (io.roundingMode === round_near_even)\n val roundingMode_minMag = (io.roundingMode === round_minMag)\n val roundingMode_min = (io.roundingMode === round_min)\n val roundingMode_max = (io.roundingMode === round_max)\n val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)\n val roundingMode_odd = (io.roundingMode === round_odd)\n\n val roundMagUp =\n (roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val sAdjustedExp =\n if (inExpWidth < outExpWidth)\n (io.in.sExp +&\n ((BigInt(1)<>1\n val roundPosMask = ~shiftedRoundMask & roundMask\n val roundPosBit = (adjustedSig & roundPosMask).orR\n val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR\n val anyRound = roundPosBit || anyRoundExtra\n\n val roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n roundPosBit) ||\n (roundMagUp && anyRound)\n val roundedSig: Bits =\n Mux(roundIncr,\n (((adjustedSig | roundMask)>>2) +& 1.U) &\n ~Mux(roundingMode_near_even && roundPosBit &&\n ! anyRoundExtra,\n roundMask>>1,\n 0.U((outSigWidth + 2).W)\n ),\n (adjustedSig & ~roundMask)>>2 |\n Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)\n )\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext\n\n common_expOut := sRoundedExp(outExpWidth, 0)\n common_fractOut :=\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth - 1, 1),\n roundedSig(outSigWidth - 2, 0)\n )\n common_overflow :=\n (if (neverOverflows) false.B else\n//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:\n (sRoundedExp>>(outExpWidth - 1) >= 3.S))\n common_totalUnderflow :=\n (if (neverUnderflows) false.B else\n//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:\n (sRoundedExp < outMinNonzeroExp.S))\n\n val unboundedRange_roundPosBit =\n Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))\n val unboundedRange_anyRound =\n (doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR\n val unboundedRange_roundIncr =\n ((roundingMode_near_even || roundingMode_near_maxMag) &&\n unboundedRange_roundPosBit) ||\n (roundMagUp && unboundedRange_anyRound)\n val roundCarry =\n Mux(doShiftSigDown1,\n roundedSig(outSigWidth + 1),\n roundedSig(outSigWidth)\n )\n common_underflow :=\n (if (neverUnderflows) false.B else\n common_totalUnderflow ||\n//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING\n//*** M.S. BIT OF SUBNORMAL SIG?\n (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&\n Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&\n ! ((io.detectTininess === tininess_afterRounding) &&\n ! Mux(doShiftSigDown1,\n roundMask(4),\n roundMask(3)\n ) &&\n roundCarry && roundPosBit &&\n unboundedRange_roundIncr)))\n\n common_inexact := common_totalUnderflow || anyRound\n }\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n val isNaNOut = io.invalidExc || io.in.isNaN\n val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf\n val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero\n val overflow = commonCase && common_overflow\n val underflow = commonCase && common_underflow\n val inexact = overflow || (commonCase && common_inexact)\n\n val overflow_roundMagUp =\n roundingMode_near_even || roundingMode_near_maxMag || roundMagUp\n val pegMinNonzeroMagOut =\n commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)\n val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp\n val notNaN_isInfOut =\n notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)\n\n val signOut = Mux(isNaNOut, false.B, io.in.sign)\n val expOut =\n (common_expOut &\n ~Mux(io.in.isZero || common_totalUnderflow,\n (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMinNonzeroMagOut,\n ~outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(pegMaxFiniteMagOut,\n (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),\n 0.U\n ) &\n ~Mux(notNaN_isInfOut,\n (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),\n 0.U\n )) |\n Mux(pegMinNonzeroMagOut,\n outMinNonzeroExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(pegMaxFiniteMagOut,\n outMaxFiniteExp.U((outExpWidth + 1).W),\n 0.U\n ) |\n Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |\n Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)\n val fractOut =\n Mux(isNaNOut || io.in.isZero || common_totalUnderflow,\n Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),\n common_fractOut\n ) |\n Fill(outSigWidth - 1, pegMaxFiniteMagOut)\n\n io.out := signOut ## expOut ## fractOut\n io.exceptionFlags :=\n io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact\n}\n\n//----------------------------------------------------------------------------\n//----------------------------------------------------------------------------\n\nclass\n RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)\n extends RawModule\n{\n override def desiredName = s\"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}\"\n val io = IO(new Bundle {\n val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'\n val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'\n val in = Input(new RawFloat(expWidth, sigWidth + 2))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n })\n\n val roundAnyRawFNToRecFN =\n Module(\n new RoundAnyRawFNToRecFN(\n expWidth, sigWidth + 2, expWidth, sigWidth, options))\n roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc\n roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc\n roundAnyRawFNToRecFN.io.in := io.in\n roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode\n roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess\n io.out := roundAnyRawFNToRecFN.io.out\n io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags\n}", + "response": "module RoundRawFNToRecFN_e5_s11(\n input io_invalidExc,\n input io_infiniteExc,\n input io_in_isNaN,\n input io_in_isInf,\n input io_in_isZero,\n input io_in_sign,\n input [6:0] io_in_sExp,\n input [13:0] io_in_sig,\n input [2:0] io_roundingMode,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 roundAnyRawFNToRecFN (\n .io_invalidExc (io_invalidExc),\n .io_infiniteExc (io_infiniteExc),\n .io_in_isNaN (io_in_isNaN),\n .io_in_isInf (io_in_isInf),\n .io_in_isZero (io_in_isZero),\n .io_in_sign (io_in_sign),\n .io_in_sExp (io_in_sExp),\n .io_in_sig (io_in_sig),\n .io_roundingMode (io_roundingMode),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module ListBuffer_PutBufferCEntry_q2_e16(\n input clock,\n input reset,\n output io_push_ready,\n input io_push_valid,\n input io_push_bits_index,\n input [63:0] io_push_bits_data_data,\n input io_push_bits_data_corrupt,\n output [1:0] io_valid,\n input io_pop_valid,\n input io_pop_bits,\n output [63:0] io_data_data,\n output io_data_corrupt\n);\n\n wire [64:0] _data_ext_R0_data;\n wire [3:0] _next_ext_R0_data;\n wire [3:0] _tail_ext_R0_data;\n wire [3:0] _tail_ext_R1_data;\n wire [3:0] _head_ext_R0_data;\n reg [1:0] valid;\n reg [15:0] used;\n wire [15:0] _freeOH_T_16 = ~used;\n wire [14:0] _freeOH_T_3 = _freeOH_T_16[14:0] | {_freeOH_T_16[13:0], 1'h0};\n wire [14:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[12:0], 2'h0};\n wire [14:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[10:0], 4'h0};\n wire [15:0] freeIdx_lo = {~(_freeOH_T_9 | {_freeOH_T_9[6:0], 8'h0}), 1'h1} & _freeOH_T_16;\n wire [6:0] _freeIdx_T_3 = freeIdx_lo[15:9] | freeIdx_lo[7:1];\n wire [2:0] _freeIdx_T_5 = _freeIdx_T_3[6:4] | _freeIdx_T_3[2:0];\n wire _freeIdx_T_7 = _freeIdx_T_5[2] | _freeIdx_T_5[0];\n wire [1:0] _GEN = {1'h0, io_push_bits_index};\n wire [1:0] _push_valid_T = valid >> _GEN;\n wire io_push_ready_0 = used != 16'hFFFF;\n wire data_MPORT_en = io_push_ready_0 & io_push_valid;\n wire [3:0] data_MPORT_addr = {|(freeIdx_lo[15:8]), |(_freeIdx_T_3[6:3]), |(_freeIdx_T_5[2:1]), _freeIdx_T_7};\n wire [1:0] _GEN_0 = {1'h0, io_pop_bits};\n always @(posedge clock) begin\n if (reset) begin\n valid <= 2'h0;\n used <= 16'h0;\n end\n else begin\n valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? 2'h1 << _GEN_0 : 2'h0) | (data_MPORT_en ? 2'h1 << _GEN : 2'h0);\n used <= used & ~(io_pop_valid ? 16'h1 << _head_ext_R0_data : 16'h0) | (data_MPORT_en ? freeIdx_lo : 16'h0);\n end\n end\n head_2x4 head_ext (\n .R0_addr (io_pop_bits),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_head_ext_R0_data),\n .W0_addr (io_pop_bits),\n .W0_en (io_pop_valid),\n .W0_clk (clock),\n .W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? {|(freeIdx_lo[15:8]), |(_freeIdx_T_3[6:3]), |(_freeIdx_T_5[2:1]), _freeIdx_T_7} : _next_ext_R0_data),\n .W1_addr (io_push_bits_index),\n .W1_en (data_MPORT_en & ~(_push_valid_T[0])),\n .W1_clk (clock),\n .W1_data (data_MPORT_addr)\n );\n tail_2x4 tail_ext (\n .R0_addr (io_push_bits_index),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_tail_ext_R0_data),\n .R1_addr (io_pop_bits),\n .R1_en (io_pop_valid),\n .R1_clk (clock),\n .R1_data (_tail_ext_R1_data),\n .W0_addr (io_push_bits_index),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data (data_MPORT_addr)\n );\n next_16x4 next_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (io_pop_valid),\n .R0_clk (clock),\n .R0_data (_next_ext_R0_data),\n .W0_addr (_tail_ext_R0_data),\n .W0_en (data_MPORT_en & _push_valid_T[0]),\n .W0_clk (clock),\n .W0_data (data_MPORT_addr)\n );\n data_16x65 data_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_data_ext_R0_data),\n .W0_addr (data_MPORT_addr),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data ({io_push_bits_data_corrupt, io_push_bits_data_data})\n );\n assign io_push_ready = io_push_ready_0;\n assign io_valid = valid;\n assign io_data_data = _data_ext_R0_data[63:0];\n assign io_data_corrupt = _data_ext_R0_data[64];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Issue Slot Logic\n//--------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Note: stores (and AMOs) are \"broken down\" into 2 uops, but stored within a single issue-slot.\n// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.\n// TODO Disable ldspec for FP queue.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\nimport FUConstants._\n\n/**\n * IO bundle to interact with Issue slot\n *\n * @param numWakeupPorts number of wakeup ports for the slot\n */\nclass IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle\n{\n val valid = Output(Bool())\n val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?\n val request = Output(Bool())\n val request_hp = Output(Bool())\n val grant = Input(Bool())\n\n val brupdate = Input(new BrUpdateInfo())\n val kill = Input(Bool()) // pipeline flush\n val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)\n val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.\n\n val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))\n val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))\n val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))\n val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!\n val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.\n val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.\n\n val debug = {\n val result = new Bundle {\n val p1 = Bool()\n val p2 = Bool()\n val p3 = Bool()\n val ppred = Bool()\n val state = UInt(width=2.W)\n }\n Output(result)\n }\n}\n\n/**\n * Single issue slot. Holds a uop within the issue queue\n *\n * @param numWakeupPorts number of wakeup ports\n */\nclass IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)\n extends BoomModule\n with IssueUnitConstants\n{\n val io = IO(new IssueSlotIO(numWakeupPorts))\n\n // slot invalid?\n // slot is valid, holding 1 uop\n // slot is valid, holds 2 uops (like a store)\n def is_invalid = state === s_invalid\n def is_valid = state =/= s_invalid\n\n val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)\n val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)\n val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)\n\n val state = RegInit(s_invalid)\n val p1 = RegInit(false.B)\n val p2 = RegInit(false.B)\n val p3 = RegInit(false.B)\n val ppred = RegInit(false.B)\n\n // Poison if woken up by speculative load.\n // Poison lasts 1 cycle (as ldMiss will come on the next cycle).\n // SO if poisoned is true, set it to false!\n val p1_poisoned = RegInit(false.B)\n val p2_poisoned = RegInit(false.B)\n p1_poisoned := false.B\n p2_poisoned := false.B\n val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)\n val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)\n\n val slot_uop = RegInit(NullMicroOp)\n val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)\n\n //-----------------------------------------------------------------------------\n // next slot state computation\n // compute the next state for THIS entry slot (in a collasping queue, the\n // current uop may get moved elsewhere, and a new uop can enter\n\n when (io.kill) {\n state := s_invalid\n } .elsewhen (io.in_uop.valid) {\n state := io.in_uop.bits.iw_state\n } .elsewhen (io.clear) {\n state := s_invalid\n } .otherwise {\n state := next_state\n }\n\n //-----------------------------------------------------------------------------\n // \"update\" state\n // compute the next state for the micro-op in this slot. This micro-op may\n // be moved elsewhere, so the \"next_state\" travels with it.\n\n // defaults\n next_state := state\n next_uopc := slot_uop.uopc\n next_lrs1_rtype := slot_uop.lrs1_rtype\n next_lrs2_rtype := slot_uop.lrs2_rtype\n\n when (io.kill) {\n next_state := s_invalid\n } .elsewhen ((io.grant && (state === s_valid_1)) ||\n (io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {\n // try to issue this uop.\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_invalid\n }\n } .elsewhen (io.grant && (state === s_valid_2)) {\n when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {\n next_state := s_valid_1\n when (p1) {\n slot_uop.uopc := uopSTD\n next_uopc := uopSTD\n slot_uop.lrs1_rtype := RT_X\n next_lrs1_rtype := RT_X\n } .otherwise {\n slot_uop.lrs2_rtype := RT_X\n next_lrs2_rtype := RT_X\n }\n }\n }\n\n when (io.in_uop.valid) {\n slot_uop := io.in_uop.bits\n assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n }\n\n // Wakeup Compare Logic\n\n // these signals are the \"next_p*\" for the current slot's micro-op.\n // they are important for shifting the current slot_uop up to an other entry.\n val next_p1 = WireInit(p1)\n val next_p2 = WireInit(p2)\n val next_p3 = WireInit(p3)\n val next_ppred = WireInit(ppred)\n\n when (io.in_uop.valid) {\n p1 := !(io.in_uop.bits.prs1_busy)\n p2 := !(io.in_uop.bits.prs2_busy)\n p3 := !(io.in_uop.bits.prs3_busy)\n ppred := !(io.in_uop.bits.ppred_busy)\n }\n\n when (io.ldspec_miss && next_p1_poisoned) {\n assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n p1 := false.B\n }\n when (io.ldspec_miss && next_p2_poisoned) {\n assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n p2 := false.B\n }\n\n for (i <- 0 until numWakeupPorts) {\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {\n p1 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {\n p2 := true.B\n }\n when (io.wakeup_ports(i).valid &&\n (io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {\n p3 := true.B\n }\n }\n when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {\n ppred := true.B\n }\n\n for (w <- 0 until memWidth) {\n assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n \"Loads to x0 should never speculatively wakeup other instructions\")\n }\n\n // TODO disable if FP IQ.\n for (w <- 0 until memWidth) {\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs1 &&\n next_uop.lrs1_rtype === RT_FIX) {\n p1 := true.B\n p1_poisoned := true.B\n assert (!next_p1_poisoned)\n }\n when (io.spec_ld_wakeup(w).valid &&\n io.spec_ld_wakeup(w).bits === next_uop.prs2 &&\n next_uop.lrs2_rtype === RT_FIX) {\n p2 := true.B\n p2_poisoned := true.B\n assert (!next_p2_poisoned)\n }\n }\n\n\n // Handle branch misspeculations\n val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)\n\n // was this micro-op killed by a branch? if yes, we can't let it be valid if\n // we compact it into an other entry\n when (IsKilledByBranch(io.brupdate, slot_uop)) {\n next_state := s_invalid\n }\n\n when (!io.in_uop.valid) {\n slot_uop.br_mask := next_br_mask\n }\n\n //-------------------------------------------------------------\n // Request Logic\n io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill\n val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr\n io.request_hp := io.request && high_priority\n\n when (state === s_valid_1) {\n io.request := p1 && p2 && p3 && ppred && !io.kill\n } .elsewhen (state === s_valid_2) {\n io.request := (p1 || p2) && ppred && !io.kill\n } .otherwise {\n io.request := false.B\n }\n\n //assign outputs\n io.valid := is_valid\n io.uop := slot_uop\n io.uop.iw_p1_poisoned := p1_poisoned\n io.uop.iw_p2_poisoned := p2_poisoned\n\n // micro-op will vacate due to grant.\n val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)\n val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)\n io.will_be_valid := is_valid && !(may_vacate && !squash_grant)\n\n io.out_uop := slot_uop\n io.out_uop.iw_state := next_state\n io.out_uop.uopc := next_uopc\n io.out_uop.lrs1_rtype := next_lrs1_rtype\n io.out_uop.lrs2_rtype := next_lrs2_rtype\n io.out_uop.br_mask := next_br_mask\n io.out_uop.prs1_busy := !p1\n io.out_uop.prs2_busy := !p2\n io.out_uop.prs3_busy := !p3\n io.out_uop.ppred_busy := !ppred\n io.out_uop.iw_p1_poisoned := p1_poisoned\n io.out_uop.iw_p2_poisoned := p2_poisoned\n\n when (state === s_valid_2) {\n when (p1 && p2 && ppred) {\n ; // send out the entire instruction as one uop\n } .elsewhen (p1 && ppred) {\n io.uop.uopc := slot_uop.uopc\n io.uop.lrs2_rtype := RT_X\n } .elsewhen (p2 && ppred) {\n io.uop.uopc := uopSTD\n io.uop.lrs1_rtype := RT_X\n }\n }\n\n // debug outputs\n io.debug.p1 := p1\n io.debug.p2 := p2\n io.debug.p3 := p3\n io.debug.ppred := ppred\n io.debug.state := state\n}", + "response": "module IssueSlot(\n input clock,\n input reset,\n output io_valid,\n output io_will_be_valid,\n output io_request,\n input io_grant,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask,\n input io_kill,\n input io_clear,\n input io_wakeup_ports_0_valid,\n input [5:0] io_wakeup_ports_0_bits_pdst,\n input io_wakeup_ports_1_valid,\n input [5:0] io_wakeup_ports_1_bits_pdst,\n input io_in_uop_valid,\n input [6:0] io_in_uop_bits_uopc,\n input [31:0] io_in_uop_bits_inst,\n input [31:0] io_in_uop_bits_debug_inst,\n input io_in_uop_bits_is_rvc,\n input [39:0] io_in_uop_bits_debug_pc,\n input [2:0] io_in_uop_bits_iq_type,\n input [9:0] io_in_uop_bits_fu_code,\n input [1:0] io_in_uop_bits_iw_state,\n input io_in_uop_bits_is_br,\n input io_in_uop_bits_is_jalr,\n input io_in_uop_bits_is_jal,\n input io_in_uop_bits_is_sfb,\n input [7:0] io_in_uop_bits_br_mask,\n input [2:0] io_in_uop_bits_br_tag,\n input [3:0] io_in_uop_bits_ftq_idx,\n input io_in_uop_bits_edge_inst,\n input [5:0] io_in_uop_bits_pc_lob,\n input io_in_uop_bits_taken,\n input [19:0] io_in_uop_bits_imm_packed,\n input [11:0] io_in_uop_bits_csr_addr,\n input [4:0] io_in_uop_bits_rob_idx,\n input [2:0] io_in_uop_bits_ldq_idx,\n input [2:0] io_in_uop_bits_stq_idx,\n input [1:0] io_in_uop_bits_rxq_idx,\n input [5:0] io_in_uop_bits_pdst,\n input [5:0] io_in_uop_bits_prs1,\n input [5:0] io_in_uop_bits_prs2,\n input [5:0] io_in_uop_bits_prs3,\n input [3:0] io_in_uop_bits_ppred,\n input io_in_uop_bits_prs1_busy,\n input io_in_uop_bits_prs2_busy,\n input io_in_uop_bits_prs3_busy,\n input io_in_uop_bits_ppred_busy,\n input [5:0] io_in_uop_bits_stale_pdst,\n input io_in_uop_bits_exception,\n input [63:0] io_in_uop_bits_exc_cause,\n input io_in_uop_bits_bypassable,\n input [4:0] io_in_uop_bits_mem_cmd,\n input [1:0] io_in_uop_bits_mem_size,\n input io_in_uop_bits_mem_signed,\n input io_in_uop_bits_is_fence,\n input io_in_uop_bits_is_fencei,\n input io_in_uop_bits_is_amo,\n input io_in_uop_bits_uses_ldq,\n input io_in_uop_bits_uses_stq,\n input io_in_uop_bits_is_sys_pc2epc,\n input io_in_uop_bits_is_unique,\n input io_in_uop_bits_flush_on_commit,\n input io_in_uop_bits_ldst_is_rs1,\n input [5:0] io_in_uop_bits_ldst,\n input [5:0] io_in_uop_bits_lrs1,\n input [5:0] io_in_uop_bits_lrs2,\n input [5:0] io_in_uop_bits_lrs3,\n input io_in_uop_bits_ldst_val,\n input [1:0] io_in_uop_bits_dst_rtype,\n input [1:0] io_in_uop_bits_lrs1_rtype,\n input [1:0] io_in_uop_bits_lrs2_rtype,\n input io_in_uop_bits_frs3_en,\n input io_in_uop_bits_fp_val,\n input io_in_uop_bits_fp_single,\n input io_in_uop_bits_xcpt_pf_if,\n input io_in_uop_bits_xcpt_ae_if,\n input io_in_uop_bits_xcpt_ma_if,\n input io_in_uop_bits_bp_debug_if,\n input io_in_uop_bits_bp_xcpt_if,\n input [1:0] io_in_uop_bits_debug_fsrc,\n input [1:0] io_in_uop_bits_debug_tsrc,\n output [6:0] io_out_uop_uopc,\n output [31:0] io_out_uop_inst,\n output [31:0] io_out_uop_debug_inst,\n output io_out_uop_is_rvc,\n output [39:0] io_out_uop_debug_pc,\n output [2:0] io_out_uop_iq_type,\n output [9:0] io_out_uop_fu_code,\n output [1:0] io_out_uop_iw_state,\n output io_out_uop_is_br,\n output io_out_uop_is_jalr,\n output io_out_uop_is_jal,\n output io_out_uop_is_sfb,\n output [7:0] io_out_uop_br_mask,\n output [2:0] io_out_uop_br_tag,\n output [3:0] io_out_uop_ftq_idx,\n output io_out_uop_edge_inst,\n output [5:0] io_out_uop_pc_lob,\n output io_out_uop_taken,\n output [19:0] io_out_uop_imm_packed,\n output [11:0] io_out_uop_csr_addr,\n output [4:0] io_out_uop_rob_idx,\n output [2:0] io_out_uop_ldq_idx,\n output [2:0] io_out_uop_stq_idx,\n output [1:0] io_out_uop_rxq_idx,\n output [5:0] io_out_uop_pdst,\n output [5:0] io_out_uop_prs1,\n output [5:0] io_out_uop_prs2,\n output [5:0] io_out_uop_prs3,\n output [3:0] io_out_uop_ppred,\n output io_out_uop_prs1_busy,\n output io_out_uop_prs2_busy,\n output io_out_uop_prs3_busy,\n output io_out_uop_ppred_busy,\n output [5:0] io_out_uop_stale_pdst,\n output io_out_uop_exception,\n output [63:0] io_out_uop_exc_cause,\n output io_out_uop_bypassable,\n output [4:0] io_out_uop_mem_cmd,\n output [1:0] io_out_uop_mem_size,\n output io_out_uop_mem_signed,\n output io_out_uop_is_fence,\n output io_out_uop_is_fencei,\n output io_out_uop_is_amo,\n output io_out_uop_uses_ldq,\n output io_out_uop_uses_stq,\n output io_out_uop_is_sys_pc2epc,\n output io_out_uop_is_unique,\n output io_out_uop_flush_on_commit,\n output io_out_uop_ldst_is_rs1,\n output [5:0] io_out_uop_ldst,\n output [5:0] io_out_uop_lrs1,\n output [5:0] io_out_uop_lrs2,\n output [5:0] io_out_uop_lrs3,\n output io_out_uop_ldst_val,\n output [1:0] io_out_uop_dst_rtype,\n output [1:0] io_out_uop_lrs1_rtype,\n output [1:0] io_out_uop_lrs2_rtype,\n output io_out_uop_frs3_en,\n output io_out_uop_fp_val,\n output io_out_uop_fp_single,\n output io_out_uop_xcpt_pf_if,\n output io_out_uop_xcpt_ae_if,\n output io_out_uop_xcpt_ma_if,\n output io_out_uop_bp_debug_if,\n output io_out_uop_bp_xcpt_if,\n output [1:0] io_out_uop_debug_fsrc,\n output [1:0] io_out_uop_debug_tsrc,\n output [6:0] io_uop_uopc,\n output [31:0] io_uop_inst,\n output [31:0] io_uop_debug_inst,\n output io_uop_is_rvc,\n output [39:0] io_uop_debug_pc,\n output [2:0] io_uop_iq_type,\n output [9:0] io_uop_fu_code,\n output [1:0] io_uop_iw_state,\n output io_uop_is_br,\n output io_uop_is_jalr,\n output io_uop_is_jal,\n output io_uop_is_sfb,\n output [7:0] io_uop_br_mask,\n output [2:0] io_uop_br_tag,\n output [3:0] io_uop_ftq_idx,\n output io_uop_edge_inst,\n output [5:0] io_uop_pc_lob,\n output io_uop_taken,\n output [19:0] io_uop_imm_packed,\n output [11:0] io_uop_csr_addr,\n output [4:0] io_uop_rob_idx,\n output [2:0] io_uop_ldq_idx,\n output [2:0] io_uop_stq_idx,\n output [1:0] io_uop_rxq_idx,\n output [5:0] io_uop_pdst,\n output [5:0] io_uop_prs1,\n output [5:0] io_uop_prs2,\n output [5:0] io_uop_prs3,\n output [3:0] io_uop_ppred,\n output io_uop_prs1_busy,\n output io_uop_prs2_busy,\n output io_uop_prs3_busy,\n output io_uop_ppred_busy,\n output [5:0] io_uop_stale_pdst,\n output io_uop_exception,\n output [63:0] io_uop_exc_cause,\n output io_uop_bypassable,\n output [4:0] io_uop_mem_cmd,\n output [1:0] io_uop_mem_size,\n output io_uop_mem_signed,\n output io_uop_is_fence,\n output io_uop_is_fencei,\n output io_uop_is_amo,\n output io_uop_uses_ldq,\n output io_uop_uses_stq,\n output io_uop_is_sys_pc2epc,\n output io_uop_is_unique,\n output io_uop_flush_on_commit,\n output io_uop_ldst_is_rs1,\n output [5:0] io_uop_ldst,\n output [5:0] io_uop_lrs1,\n output [5:0] io_uop_lrs2,\n output [5:0] io_uop_lrs3,\n output io_uop_ldst_val,\n output [1:0] io_uop_dst_rtype,\n output [1:0] io_uop_lrs1_rtype,\n output [1:0] io_uop_lrs2_rtype,\n output io_uop_frs3_en,\n output io_uop_fp_val,\n output io_uop_fp_single,\n output io_uop_xcpt_pf_if,\n output io_uop_xcpt_ae_if,\n output io_uop_xcpt_ma_if,\n output io_uop_bp_debug_if,\n output io_uop_bp_xcpt_if,\n output [1:0] io_uop_debug_fsrc,\n output [1:0] io_uop_debug_tsrc\n);\n\n reg [1:0] state;\n reg p1;\n reg p2;\n reg p3;\n reg ppred;\n reg [6:0] slot_uop_uopc;\n reg [31:0] slot_uop_inst;\n reg [31:0] slot_uop_debug_inst;\n reg slot_uop_is_rvc;\n reg [39:0] slot_uop_debug_pc;\n reg [2:0] slot_uop_iq_type;\n reg [9:0] slot_uop_fu_code;\n reg [1:0] slot_uop_iw_state;\n reg slot_uop_is_br;\n reg slot_uop_is_jalr;\n reg slot_uop_is_jal;\n reg slot_uop_is_sfb;\n reg [7:0] slot_uop_br_mask;\n reg [2:0] slot_uop_br_tag;\n reg [3:0] slot_uop_ftq_idx;\n reg slot_uop_edge_inst;\n reg [5:0] slot_uop_pc_lob;\n reg slot_uop_taken;\n reg [19:0] slot_uop_imm_packed;\n reg [11:0] slot_uop_csr_addr;\n reg [4:0] slot_uop_rob_idx;\n reg [2:0] slot_uop_ldq_idx;\n reg [2:0] slot_uop_stq_idx;\n reg [1:0] slot_uop_rxq_idx;\n reg [5:0] slot_uop_pdst;\n reg [5:0] slot_uop_prs1;\n reg [5:0] slot_uop_prs2;\n reg [5:0] slot_uop_prs3;\n reg [3:0] slot_uop_ppred;\n reg slot_uop_prs1_busy;\n reg slot_uop_prs2_busy;\n reg slot_uop_prs3_busy;\n reg slot_uop_ppred_busy;\n reg [5:0] slot_uop_stale_pdst;\n reg slot_uop_exception;\n reg [63:0] slot_uop_exc_cause;\n reg slot_uop_bypassable;\n reg [4:0] slot_uop_mem_cmd;\n reg [1:0] slot_uop_mem_size;\n reg slot_uop_mem_signed;\n reg slot_uop_is_fence;\n reg slot_uop_is_fencei;\n reg slot_uop_is_amo;\n reg slot_uop_uses_ldq;\n reg slot_uop_uses_stq;\n reg slot_uop_is_sys_pc2epc;\n reg slot_uop_is_unique;\n reg slot_uop_flush_on_commit;\n reg slot_uop_ldst_is_rs1;\n reg [5:0] slot_uop_ldst;\n reg [5:0] slot_uop_lrs1;\n reg [5:0] slot_uop_lrs2;\n reg [5:0] slot_uop_lrs3;\n reg slot_uop_ldst_val;\n reg [1:0] slot_uop_dst_rtype;\n reg [1:0] slot_uop_lrs1_rtype;\n reg [1:0] slot_uop_lrs2_rtype;\n reg slot_uop_frs3_en;\n reg slot_uop_fp_val;\n reg slot_uop_fp_single;\n reg slot_uop_xcpt_pf_if;\n reg slot_uop_xcpt_ae_if;\n reg slot_uop_xcpt_ma_if;\n reg slot_uop_bp_debug_if;\n reg slot_uop_bp_xcpt_if;\n reg [1:0] slot_uop_debug_fsrc;\n reg [1:0] slot_uop_debug_tsrc;\n wire _GEN = state == 2'h2;\n wire _GEN_0 = io_grant & _GEN;\n wire _GEN_1 = _GEN_0 & p1;\n wire _GEN_2 = io_grant & state == 2'h1 | _GEN_1 & p2 & ppred;\n wire _GEN_3 = io_kill | _GEN_2;\n wire _GEN_4 = _GEN_3 | ~_GEN_1;\n wire _GEN_5 = _GEN_3 | ~_GEN_0 | p1;\n wire [7:0] next_br_mask = slot_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n wire _GEN_6 = (|(io_brupdate_b1_mispredict_mask & slot_uop_br_mask)) | io_kill | _GEN_2;\n wire _may_vacate_T = state == 2'h1;\n wire _may_vacate_T_1 = state == 2'h2;\n wire _GEN_7 = p1 & p2 & ppred;\n wire _GEN_8 = p1 & ppred;\n wire _GEN_9 = ~_may_vacate_T_1 | _GEN_7 | _GEN_8 | ~(p2 & ppred);\n wire [5:0] next_uop_prs1 = io_in_uop_valid ? io_in_uop_bits_prs1 : slot_uop_prs1;\n wire [5:0] next_uop_prs2 = io_in_uop_valid ? io_in_uop_bits_prs2 : slot_uop_prs2;\n wire [5:0] next_uop_prs3 = io_in_uop_valid ? io_in_uop_bits_prs3 : slot_uop_prs3;\n always @(posedge clock) begin\n if (reset) begin\n state <= 2'h0;\n p1 <= 1'h0;\n p2 <= 1'h0;\n p3 <= 1'h0;\n ppred <= 1'h0;\n slot_uop_uopc <= 7'h0;\n slot_uop_pdst <= 6'h0;\n slot_uop_bypassable <= 1'h0;\n slot_uop_uses_ldq <= 1'h0;\n slot_uop_uses_stq <= 1'h0;\n slot_uop_dst_rtype <= 2'h2;\n slot_uop_fp_val <= 1'h0;\n end\n else begin\n if (io_kill)\n state <= 2'h0;\n else if (io_in_uop_valid)\n state <= io_in_uop_bits_iw_state;\n else if (io_clear | _GEN_6)\n state <= 2'h0;\n else if (_GEN_0)\n state <= 2'h1;\n p1 <= io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs1 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs1 | (io_in_uop_valid ? ~io_in_uop_bits_prs1_busy : p1);\n p2 <= io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs2 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs2 | (io_in_uop_valid ? ~io_in_uop_bits_prs2_busy : p2);\n p3 <= io_wakeup_ports_1_valid & io_wakeup_ports_1_bits_pdst == next_uop_prs3 | io_wakeup_ports_0_valid & io_wakeup_ports_0_bits_pdst == next_uop_prs3 | (io_in_uop_valid ? ~io_in_uop_bits_prs3_busy : p3);\n if (io_in_uop_valid) begin\n ppred <= ~io_in_uop_bits_ppred_busy;\n slot_uop_uopc <= io_in_uop_bits_uopc;\n slot_uop_pdst <= io_in_uop_bits_pdst;\n slot_uop_bypassable <= io_in_uop_bits_bypassable;\n slot_uop_uses_ldq <= io_in_uop_bits_uses_ldq;\n slot_uop_uses_stq <= io_in_uop_bits_uses_stq;\n slot_uop_dst_rtype <= io_in_uop_bits_dst_rtype;\n slot_uop_fp_val <= io_in_uop_bits_fp_val;\n end\n else if (_GEN_4) begin\n end\n else\n slot_uop_uopc <= 7'h3;\n end\n if (io_in_uop_valid) begin\n slot_uop_inst <= io_in_uop_bits_inst;\n slot_uop_debug_inst <= io_in_uop_bits_debug_inst;\n slot_uop_is_rvc <= io_in_uop_bits_is_rvc;\n slot_uop_debug_pc <= io_in_uop_bits_debug_pc;\n slot_uop_iq_type <= io_in_uop_bits_iq_type;\n slot_uop_fu_code <= io_in_uop_bits_fu_code;\n slot_uop_iw_state <= io_in_uop_bits_iw_state;\n slot_uop_is_br <= io_in_uop_bits_is_br;\n slot_uop_is_jalr <= io_in_uop_bits_is_jalr;\n slot_uop_is_jal <= io_in_uop_bits_is_jal;\n slot_uop_is_sfb <= io_in_uop_bits_is_sfb;\n slot_uop_br_tag <= io_in_uop_bits_br_tag;\n slot_uop_ftq_idx <= io_in_uop_bits_ftq_idx;\n slot_uop_edge_inst <= io_in_uop_bits_edge_inst;\n slot_uop_pc_lob <= io_in_uop_bits_pc_lob;\n slot_uop_taken <= io_in_uop_bits_taken;\n slot_uop_imm_packed <= io_in_uop_bits_imm_packed;\n slot_uop_csr_addr <= io_in_uop_bits_csr_addr;\n slot_uop_rob_idx <= io_in_uop_bits_rob_idx;\n slot_uop_ldq_idx <= io_in_uop_bits_ldq_idx;\n slot_uop_stq_idx <= io_in_uop_bits_stq_idx;\n slot_uop_rxq_idx <= io_in_uop_bits_rxq_idx;\n slot_uop_prs1 <= io_in_uop_bits_prs1;\n slot_uop_prs2 <= io_in_uop_bits_prs2;\n slot_uop_prs3 <= io_in_uop_bits_prs3;\n slot_uop_ppred <= io_in_uop_bits_ppred;\n slot_uop_prs1_busy <= io_in_uop_bits_prs1_busy;\n slot_uop_prs2_busy <= io_in_uop_bits_prs2_busy;\n slot_uop_prs3_busy <= io_in_uop_bits_prs3_busy;\n slot_uop_ppred_busy <= io_in_uop_bits_ppred_busy;\n slot_uop_stale_pdst <= io_in_uop_bits_stale_pdst;\n slot_uop_exception <= io_in_uop_bits_exception;\n slot_uop_exc_cause <= io_in_uop_bits_exc_cause;\n slot_uop_mem_cmd <= io_in_uop_bits_mem_cmd;\n slot_uop_mem_size <= io_in_uop_bits_mem_size;\n slot_uop_mem_signed <= io_in_uop_bits_mem_signed;\n slot_uop_is_fence <= io_in_uop_bits_is_fence;\n slot_uop_is_fencei <= io_in_uop_bits_is_fencei;\n slot_uop_is_amo <= io_in_uop_bits_is_amo;\n slot_uop_is_sys_pc2epc <= io_in_uop_bits_is_sys_pc2epc;\n slot_uop_is_unique <= io_in_uop_bits_is_unique;\n slot_uop_flush_on_commit <= io_in_uop_bits_flush_on_commit;\n slot_uop_ldst_is_rs1 <= io_in_uop_bits_ldst_is_rs1;\n slot_uop_ldst <= io_in_uop_bits_ldst;\n slot_uop_lrs1 <= io_in_uop_bits_lrs1;\n slot_uop_lrs2 <= io_in_uop_bits_lrs2;\n slot_uop_lrs3 <= io_in_uop_bits_lrs3;\n slot_uop_ldst_val <= io_in_uop_bits_ldst_val;\n slot_uop_lrs1_rtype <= io_in_uop_bits_lrs1_rtype;\n slot_uop_lrs2_rtype <= io_in_uop_bits_lrs2_rtype;\n slot_uop_frs3_en <= io_in_uop_bits_frs3_en;\n slot_uop_fp_single <= io_in_uop_bits_fp_single;\n slot_uop_xcpt_pf_if <= io_in_uop_bits_xcpt_pf_if;\n slot_uop_xcpt_ae_if <= io_in_uop_bits_xcpt_ae_if;\n slot_uop_xcpt_ma_if <= io_in_uop_bits_xcpt_ma_if;\n slot_uop_bp_debug_if <= io_in_uop_bits_bp_debug_if;\n slot_uop_bp_xcpt_if <= io_in_uop_bits_bp_xcpt_if;\n slot_uop_debug_fsrc <= io_in_uop_bits_debug_fsrc;\n slot_uop_debug_tsrc <= io_in_uop_bits_debug_tsrc;\n end\n else begin\n if (_GEN_4) begin\n end\n else\n slot_uop_lrs1_rtype <= 2'h2;\n if (_GEN_5) begin\n end\n else\n slot_uop_lrs2_rtype <= 2'h2;\n end\n slot_uop_br_mask <= io_in_uop_valid ? io_in_uop_bits_br_mask : next_br_mask;\n end\n assign io_valid = |state;\n assign io_will_be_valid = (|state) & ~(io_grant & (_may_vacate_T | _may_vacate_T_1 & p1 & p2 & ppred));\n assign io_request = _may_vacate_T ? p1 & p2 & p3 & ppred & ~io_kill : _GEN & (p1 | p2) & ppred & ~io_kill;\n assign io_out_uop_uopc = _GEN_4 ? slot_uop_uopc : 7'h3;\n assign io_out_uop_inst = slot_uop_inst;\n assign io_out_uop_debug_inst = slot_uop_debug_inst;\n assign io_out_uop_is_rvc = slot_uop_is_rvc;\n assign io_out_uop_debug_pc = slot_uop_debug_pc;\n assign io_out_uop_iq_type = slot_uop_iq_type;\n assign io_out_uop_fu_code = slot_uop_fu_code;\n assign io_out_uop_iw_state = _GEN_6 ? 2'h0 : _GEN_0 ? 2'h1 : state;\n assign io_out_uop_is_br = slot_uop_is_br;\n assign io_out_uop_is_jalr = slot_uop_is_jalr;\n assign io_out_uop_is_jal = slot_uop_is_jal;\n assign io_out_uop_is_sfb = slot_uop_is_sfb;\n assign io_out_uop_br_mask = next_br_mask;\n assign io_out_uop_br_tag = slot_uop_br_tag;\n assign io_out_uop_ftq_idx = slot_uop_ftq_idx;\n assign io_out_uop_edge_inst = slot_uop_edge_inst;\n assign io_out_uop_pc_lob = slot_uop_pc_lob;\n assign io_out_uop_taken = slot_uop_taken;\n assign io_out_uop_imm_packed = slot_uop_imm_packed;\n assign io_out_uop_csr_addr = slot_uop_csr_addr;\n assign io_out_uop_rob_idx = slot_uop_rob_idx;\n assign io_out_uop_ldq_idx = slot_uop_ldq_idx;\n assign io_out_uop_stq_idx = slot_uop_stq_idx;\n assign io_out_uop_rxq_idx = slot_uop_rxq_idx;\n assign io_out_uop_pdst = slot_uop_pdst;\n assign io_out_uop_prs1 = slot_uop_prs1;\n assign io_out_uop_prs2 = slot_uop_prs2;\n assign io_out_uop_prs3 = slot_uop_prs3;\n assign io_out_uop_ppred = slot_uop_ppred;\n assign io_out_uop_prs1_busy = ~p1;\n assign io_out_uop_prs2_busy = ~p2;\n assign io_out_uop_prs3_busy = ~p3;\n assign io_out_uop_ppred_busy = ~ppred;\n assign io_out_uop_stale_pdst = slot_uop_stale_pdst;\n assign io_out_uop_exception = slot_uop_exception;\n assign io_out_uop_exc_cause = slot_uop_exc_cause;\n assign io_out_uop_bypassable = slot_uop_bypassable;\n assign io_out_uop_mem_cmd = slot_uop_mem_cmd;\n assign io_out_uop_mem_size = slot_uop_mem_size;\n assign io_out_uop_mem_signed = slot_uop_mem_signed;\n assign io_out_uop_is_fence = slot_uop_is_fence;\n assign io_out_uop_is_fencei = slot_uop_is_fencei;\n assign io_out_uop_is_amo = slot_uop_is_amo;\n assign io_out_uop_uses_ldq = slot_uop_uses_ldq;\n assign io_out_uop_uses_stq = slot_uop_uses_stq;\n assign io_out_uop_is_sys_pc2epc = slot_uop_is_sys_pc2epc;\n assign io_out_uop_is_unique = slot_uop_is_unique;\n assign io_out_uop_flush_on_commit = slot_uop_flush_on_commit;\n assign io_out_uop_ldst_is_rs1 = slot_uop_ldst_is_rs1;\n assign io_out_uop_ldst = slot_uop_ldst;\n assign io_out_uop_lrs1 = slot_uop_lrs1;\n assign io_out_uop_lrs2 = slot_uop_lrs2;\n assign io_out_uop_lrs3 = slot_uop_lrs3;\n assign io_out_uop_ldst_val = slot_uop_ldst_val;\n assign io_out_uop_dst_rtype = slot_uop_dst_rtype;\n assign io_out_uop_lrs1_rtype = _GEN_4 ? slot_uop_lrs1_rtype : 2'h2;\n assign io_out_uop_lrs2_rtype = _GEN_5 ? slot_uop_lrs2_rtype : 2'h2;\n assign io_out_uop_frs3_en = slot_uop_frs3_en;\n assign io_out_uop_fp_val = slot_uop_fp_val;\n assign io_out_uop_fp_single = slot_uop_fp_single;\n assign io_out_uop_xcpt_pf_if = slot_uop_xcpt_pf_if;\n assign io_out_uop_xcpt_ae_if = slot_uop_xcpt_ae_if;\n assign io_out_uop_xcpt_ma_if = slot_uop_xcpt_ma_if;\n assign io_out_uop_bp_debug_if = slot_uop_bp_debug_if;\n assign io_out_uop_bp_xcpt_if = slot_uop_bp_xcpt_if;\n assign io_out_uop_debug_fsrc = slot_uop_debug_fsrc;\n assign io_out_uop_debug_tsrc = slot_uop_debug_tsrc;\n assign io_uop_uopc = _GEN_9 ? slot_uop_uopc : 7'h3;\n assign io_uop_inst = slot_uop_inst;\n assign io_uop_debug_inst = slot_uop_debug_inst;\n assign io_uop_is_rvc = slot_uop_is_rvc;\n assign io_uop_debug_pc = slot_uop_debug_pc;\n assign io_uop_iq_type = slot_uop_iq_type;\n assign io_uop_fu_code = slot_uop_fu_code;\n assign io_uop_iw_state = slot_uop_iw_state;\n assign io_uop_is_br = slot_uop_is_br;\n assign io_uop_is_jalr = slot_uop_is_jalr;\n assign io_uop_is_jal = slot_uop_is_jal;\n assign io_uop_is_sfb = slot_uop_is_sfb;\n assign io_uop_br_mask = slot_uop_br_mask;\n assign io_uop_br_tag = slot_uop_br_tag;\n assign io_uop_ftq_idx = slot_uop_ftq_idx;\n assign io_uop_edge_inst = slot_uop_edge_inst;\n assign io_uop_pc_lob = slot_uop_pc_lob;\n assign io_uop_taken = slot_uop_taken;\n assign io_uop_imm_packed = slot_uop_imm_packed;\n assign io_uop_csr_addr = slot_uop_csr_addr;\n assign io_uop_rob_idx = slot_uop_rob_idx;\n assign io_uop_ldq_idx = slot_uop_ldq_idx;\n assign io_uop_stq_idx = slot_uop_stq_idx;\n assign io_uop_rxq_idx = slot_uop_rxq_idx;\n assign io_uop_pdst = slot_uop_pdst;\n assign io_uop_prs1 = slot_uop_prs1;\n assign io_uop_prs2 = slot_uop_prs2;\n assign io_uop_prs3 = slot_uop_prs3;\n assign io_uop_ppred = slot_uop_ppred;\n assign io_uop_prs1_busy = slot_uop_prs1_busy;\n assign io_uop_prs2_busy = slot_uop_prs2_busy;\n assign io_uop_prs3_busy = slot_uop_prs3_busy;\n assign io_uop_ppred_busy = slot_uop_ppred_busy;\n assign io_uop_stale_pdst = slot_uop_stale_pdst;\n assign io_uop_exception = slot_uop_exception;\n assign io_uop_exc_cause = slot_uop_exc_cause;\n assign io_uop_bypassable = slot_uop_bypassable;\n assign io_uop_mem_cmd = slot_uop_mem_cmd;\n assign io_uop_mem_size = slot_uop_mem_size;\n assign io_uop_mem_signed = slot_uop_mem_signed;\n assign io_uop_is_fence = slot_uop_is_fence;\n assign io_uop_is_fencei = slot_uop_is_fencei;\n assign io_uop_is_amo = slot_uop_is_amo;\n assign io_uop_uses_ldq = slot_uop_uses_ldq;\n assign io_uop_uses_stq = slot_uop_uses_stq;\n assign io_uop_is_sys_pc2epc = slot_uop_is_sys_pc2epc;\n assign io_uop_is_unique = slot_uop_is_unique;\n assign io_uop_flush_on_commit = slot_uop_flush_on_commit;\n assign io_uop_ldst_is_rs1 = slot_uop_ldst_is_rs1;\n assign io_uop_ldst = slot_uop_ldst;\n assign io_uop_lrs1 = slot_uop_lrs1;\n assign io_uop_lrs2 = slot_uop_lrs2;\n assign io_uop_lrs3 = slot_uop_lrs3;\n assign io_uop_ldst_val = slot_uop_ldst_val;\n assign io_uop_dst_rtype = slot_uop_dst_rtype;\n assign io_uop_lrs1_rtype = _GEN_9 ? slot_uop_lrs1_rtype : 2'h2;\n assign io_uop_lrs2_rtype = ~_may_vacate_T_1 | _GEN_7 | ~_GEN_8 ? slot_uop_lrs2_rtype : 2'h2;\n assign io_uop_frs3_en = slot_uop_frs3_en;\n assign io_uop_fp_val = slot_uop_fp_val;\n assign io_uop_fp_single = slot_uop_fp_single;\n assign io_uop_xcpt_pf_if = slot_uop_xcpt_pf_if;\n assign io_uop_xcpt_ae_if = slot_uop_xcpt_ae_if;\n assign io_uop_xcpt_ma_if = slot_uop_xcpt_ma_if;\n assign io_uop_bp_debug_if = slot_uop_bp_debug_if;\n assign io_uop_bp_xcpt_if = slot_uop_bp_xcpt_if;\n assign io_uop_debug_fsrc = slot_uop_debug_fsrc;\n assign io_uop_debug_tsrc = slot_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module GenericDeserializer_TLBeatw88_f32_TestHarness_UNIQUIFIED(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_flit,\n input io_out_ready,\n output io_out_valid,\n output [85:0] io_out_bits_payload,\n output io_out_bits_head,\n output io_out_bits_tail\n);\n\n reg [31:0] data_0;\n reg [31:0] data_1;\n reg [1:0] beat;\n wire io_in_ready_0 = io_out_ready | beat != 2'h2;\n wire _beat_T = beat == 2'h2;\n wire _GEN = io_in_ready_0 & io_in_valid;\n wire _GEN_0 = beat == 2'h2;\n always @(posedge clock) begin\n if (~_GEN | _GEN_0 | beat[0]) begin\n end\n else\n data_0 <= io_in_bits_flit;\n if (~_GEN | _GEN_0 | ~(beat[0])) begin\n end\n else\n data_1 <= io_in_bits_flit;\n if (reset)\n beat <= 2'h0;\n else if (_GEN)\n beat <= _beat_T ? 2'h0 : beat + 2'h1;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_valid = io_in_valid & _beat_T;\n assign io_out_bits_payload = {io_in_bits_flit[23:0], data_1, data_0[31:2]};\n assign io_out_bits_head = data_0[1];\n assign io_out_bits_tail = data_0[0];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module FPUFMAPipe_l3_f16(\n input clock,\n input reset,\n input io_in_valid,\n input io_in_bits_ren3,\n input io_in_bits_swap23,\n input [2:0] io_in_bits_rm,\n input [1:0] io_in_bits_fmaCmd,\n input [64:0] io_in_bits_in1,\n input [64:0] io_in_bits_in2,\n input [64:0] io_in_bits_in3,\n output [64:0] io_out_bits_data,\n output [4:0] io_out_bits_exc\n);\n\n wire [16:0] _fma_io_out;\n reg valid;\n reg [2:0] in_rm;\n reg [1:0] in_fmaCmd;\n reg [64:0] in_in1;\n reg [64:0] in_in2;\n reg [64:0] in_in3;\n always @(posedge clock) begin\n valid <= io_in_valid;\n if (io_in_valid) begin\n in_rm <= io_in_bits_rm;\n in_fmaCmd <= io_in_bits_fmaCmd;\n in_in1 <= io_in_bits_in1;\n in_in2 <= io_in_bits_swap23 ? 65'h8000 : io_in_bits_in2;\n in_in3 <= io_in_bits_ren3 | io_in_bits_swap23 ? io_in_bits_in3 : {48'h0, (io_in_bits_in1[16:0] ^ io_in_bits_in2[16:0]) & 17'h10000};\n end\n end\n MulAddRecFNPipe_l2_e5_s11 fma (\n .clock (clock),\n .reset (reset),\n .io_validin (valid),\n .io_op (in_fmaCmd),\n .io_a (in_in1[16:0]),\n .io_b (in_in2[16:0]),\n .io_c (in_in3[16:0]),\n .io_roundingMode (in_rm),\n .io_out (_fma_io_out),\n .io_exceptionFlags (io_out_bits_exc)\n );\n assign io_out_bits_data = {48'h0, _fma_io_out};\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Rename FreeList\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\nimport boom.v3.common._\nimport boom.v3.util._\nimport org.chipsalliance.cde.config.Parameters\n\nclass RenameFreeList(\n val plWidth: Int,\n val numPregs: Int,\n val numLregs: Int)\n (implicit p: Parameters) extends BoomModule\n{\n private val pregSz = log2Ceil(numPregs)\n private val n = numPregs\n\n val io = IO(new BoomBundle()(p) {\n // Physical register requests.\n val reqs = Input(Vec(plWidth, Bool()))\n val alloc_pregs = Output(Vec(plWidth, Valid(UInt(pregSz.W))))\n\n // Pregs returned by the ROB.\n val dealloc_pregs = Input(Vec(plWidth, Valid(UInt(pregSz.W))))\n\n // Branch info for starting new allocation lists.\n val ren_br_tags = Input(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Mispredict info for recovering speculatively allocated registers.\n val brupdate = Input(new BrUpdateInfo)\n\n val debug = new Bundle {\n val pipeline_empty = Input(Bool())\n val freelist = Output(Bits(numPregs.W))\n val isprlist = Output(Bits(numPregs.W))\n }\n })\n // The free list register array and its branch allocation lists.\n val free_list = RegInit(UInt(numPregs.W), ~(1.U(numPregs.W)))\n val br_alloc_lists = Reg(Vec(maxBrCount, UInt(numPregs.W)))\n\n // Select pregs from the free list.\n val sels = SelectFirstN(free_list, plWidth)\n val sel_fire = Wire(Vec(plWidth, Bool()))\n\n // Allocations seen by branches in each pipeline slot.\n val allocs = io.alloc_pregs map (a => UIntToOH(a.bits))\n val alloc_masks = (allocs zip io.reqs).scanRight(0.U(n.W)) { case ((a,r),m) => m | a & Fill(n,r) }\n\n // Masks that modify the freelist array.\n val sel_mask = (sels zip sel_fire) map { case (s,f) => s & Fill(n,f) } reduce(_|_)\n val br_deallocs = br_alloc_lists(io.brupdate.b2.uop.br_tag) & Fill(n, io.brupdate.b2.mispredict)\n val dealloc_mask = io.dealloc_pregs.map(d => UIntToOH(d.bits)(numPregs-1,0) & Fill(n,d.valid)).reduce(_|_) | br_deallocs\n\n val br_slots = VecInit(io.ren_br_tags.map(tag => tag.valid)).asUInt\n // Create branch allocation lists.\n for (i <- 0 until maxBrCount) {\n val list_req = VecInit(io.ren_br_tags.map(tag => UIntToOH(tag.bits)(i))).asUInt & br_slots\n val new_list = list_req.orR\n br_alloc_lists(i) := Mux(new_list, Mux1H(list_req, alloc_masks.slice(1, plWidth+1)),\n br_alloc_lists(i) & ~br_deallocs | alloc_masks(0))\n }\n\n // Update the free list.\n free_list := (free_list & ~sel_mask | dealloc_mask) & ~(1.U(numPregs.W))\n\n // Pipeline logic | hookup outputs.\n for (w <- 0 until plWidth) {\n val can_sel = sels(w).orR\n val r_valid = RegInit(false.B)\n val r_sel = RegEnable(OHToUInt(sels(w)), sel_fire(w))\n\n r_valid := r_valid && !io.reqs(w) || can_sel\n sel_fire(w) := (!r_valid || io.reqs(w)) && can_sel\n\n io.alloc_pregs(w).bits := r_sel\n io.alloc_pregs(w).valid := r_valid\n }\n\n io.debug.freelist := free_list | io.alloc_pregs.map(p => UIntToOH(p.bits) & Fill(n,p.valid)).reduce(_|_)\n io.debug.isprlist := 0.U // TODO track commit free list.\n\n assert (!(io.debug.freelist & dealloc_mask).orR, \"[freelist] Returning a free physical register.\")\n assert (!io.debug.pipeline_empty || PopCount(io.debug.freelist) >= (numPregs - numLregs - 1).U,\n \"[freelist] Leaking physical registers.\")\n}", + "response": "module RenameFreeList_1(\n input clock,\n input reset,\n input io_reqs_0,\n output io_alloc_pregs_0_valid,\n output [5:0] io_alloc_pregs_0_bits,\n input io_dealloc_pregs_0_valid,\n input [5:0] io_dealloc_pregs_0_bits,\n input io_ren_br_tags_0_valid,\n input [2:0] io_ren_br_tags_0_bits,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_debug_pipeline_empty\n);\n\n reg [5:0] r_sel;\n reg [47:0] free_list;\n reg [47:0] br_alloc_lists_0;\n reg [47:0] br_alloc_lists_1;\n reg [47:0] br_alloc_lists_2;\n reg [47:0] br_alloc_lists_3;\n reg [47:0] br_alloc_lists_4;\n reg [47:0] br_alloc_lists_5;\n reg [47:0] br_alloc_lists_6;\n reg [47:0] br_alloc_lists_7;\n wire [47:0] sels_0 = free_list[0] ? 48'h1 : free_list[1] ? 48'h2 : free_list[2] ? 48'h4 : free_list[3] ? 48'h8 : free_list[4] ? 48'h10 : free_list[5] ? 48'h20 : free_list[6] ? 48'h40 : free_list[7] ? 48'h80 : free_list[8] ? 48'h100 : free_list[9] ? 48'h200 : free_list[10] ? 48'h400 : free_list[11] ? 48'h800 : free_list[12] ? 48'h1000 : free_list[13] ? 48'h2000 : free_list[14] ? 48'h4000 : free_list[15] ? 48'h8000 : free_list[16] ? 48'h10000 : free_list[17] ? 48'h20000 : free_list[18] ? 48'h40000 : free_list[19] ? 48'h80000 : free_list[20] ? 48'h100000 : free_list[21] ? 48'h200000 : free_list[22] ? 48'h400000 : free_list[23] ? 48'h800000 : free_list[24] ? 48'h1000000 : free_list[25] ? 48'h2000000 : free_list[26] ? 48'h4000000 : free_list[27] ? 48'h8000000 : free_list[28] ? 48'h10000000 : free_list[29] ? 48'h20000000 : free_list[30] ? 48'h40000000 : free_list[31] ? 48'h80000000 : free_list[32] ? 48'h100000000 : free_list[33] ? 48'h200000000 : free_list[34] ? 48'h400000000 : free_list[35] ? 48'h800000000 : free_list[36] ? 48'h1000000000 : free_list[37] ? 48'h2000000000 : free_list[38] ? 48'h4000000000 : free_list[39] ? 48'h8000000000 : free_list[40] ? 48'h10000000000 : free_list[41] ? 48'h20000000000 : free_list[42] ? 48'h40000000000 : free_list[43] ? 48'h80000000000 : free_list[44] ? 48'h100000000000 : free_list[45] ? 48'h200000000000 : free_list[46] ? 48'h400000000000 : {free_list[47], 47'h0};\n wire [63:0] allocs_0 = 64'h1 << r_sel;\n wire [7:0][47:0] _GEN = {{br_alloc_lists_7}, {br_alloc_lists_6}, {br_alloc_lists_5}, {br_alloc_lists_4}, {br_alloc_lists_3}, {br_alloc_lists_2}, {br_alloc_lists_1}, {br_alloc_lists_0}};\n wire [47:0] br_deallocs = _GEN[io_brupdate_b2_uop_br_tag] & {48{io_brupdate_b2_mispredict}};\n wire [63:0] _dealloc_mask_T = 64'h1 << io_dealloc_pregs_0_bits;\n wire [47:0] dealloc_mask = _dealloc_mask_T[47:0] & {48{io_dealloc_pregs_0_valid}} | br_deallocs;\n reg r_valid;\n wire sel_fire_0 = (~r_valid | io_reqs_0) & (|sels_0);\n wire [30:0] _r_sel_T_1 = {16'h0, sels_0[47:33]} | sels_0[31:1];\n wire [14:0] _r_sel_T_3 = _r_sel_T_1[30:16] | _r_sel_T_1[14:0];\n wire [6:0] _r_sel_T_5 = _r_sel_T_3[14:8] | _r_sel_T_3[6:0];\n wire [2:0] _r_sel_T_7 = _r_sel_T_5[6:4] | _r_sel_T_5[2:0];\n wire [47:0] _GEN_0 = allocs_0[47:0] & {48{io_reqs_0}};\n always @(posedge clock) begin\n if (reset) begin\n free_list <= 48'hFFFFFFFFFFFE;\n r_valid <= 1'h0;\n end\n else begin\n free_list <= (free_list & ~(sels_0 & {48{sel_fire_0}}) | dealloc_mask) & 48'hFFFFFFFFFFFE;\n r_valid <= |{r_valid & ~io_reqs_0, sels_0};\n end\n br_alloc_lists_0 <= io_ren_br_tags_0_bits == 3'h0 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_0 & ~br_deallocs | _GEN_0;\n br_alloc_lists_1 <= io_ren_br_tags_0_bits == 3'h1 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_1 & ~br_deallocs | _GEN_0;\n br_alloc_lists_2 <= io_ren_br_tags_0_bits == 3'h2 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_2 & ~br_deallocs | _GEN_0;\n br_alloc_lists_3 <= io_ren_br_tags_0_bits == 3'h3 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_3 & ~br_deallocs | _GEN_0;\n br_alloc_lists_4 <= io_ren_br_tags_0_bits == 3'h4 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_4 & ~br_deallocs | _GEN_0;\n br_alloc_lists_5 <= io_ren_br_tags_0_bits == 3'h5 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_5 & ~br_deallocs | _GEN_0;\n br_alloc_lists_6 <= io_ren_br_tags_0_bits == 3'h6 & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_6 & ~br_deallocs | _GEN_0;\n br_alloc_lists_7 <= (&io_ren_br_tags_0_bits) & io_ren_br_tags_0_valid ? 48'h0 : br_alloc_lists_7 & ~br_deallocs | _GEN_0;\n if (sel_fire_0)\n r_sel <= {|(sels_0[47:32]), |(_r_sel_T_1[30:15]), |(_r_sel_T_3[14:7]), |(_r_sel_T_5[6:3]), |(_r_sel_T_7[2:1]), _r_sel_T_7[2] | _r_sel_T_7[0]};\n end\n assign io_alloc_pregs_0_valid = r_valid;\n assign io_alloc_pregs_0_bits = r_sel;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2018, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Register Read\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\n\n/**\n * Handle the register read and bypass network for the OoO backend\n * interfaces with the issue window on the enqueue side, and the execution\n * pipelines on the dequeue side.\n *\n * @param issueWidth total issue width from all issue queues\n * @param supportedUnitsArray seq of SupportedFuncUnits classes indicating what the functional units do\n * @param numTotalReadPorts number of read ports\n * @param numReadPortsArray execution units read port sequence\n * @param numTotalBypassPorts number of bypass ports out of the execution units\n * @param registerWidth size of register in bits\n */\nclass RegisterRead(\n issueWidth: Int,\n supportedUnitsArray: Seq[SupportedFuncUnits],\n numTotalReadPorts: Int,\n numReadPortsArray: Seq[Int],\n // each exe_unit must tell us how many max\n // operands it can accept (the sum should equal\n // numTotalReadPorts)\n numTotalBypassPorts: Int,\n numTotalPredBypassPorts: Int,\n registerWidth: Int\n)(implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n // issued micro-ops\n val iss_valids = Input(Vec(issueWidth, Bool()))\n val iss_uops = Input(Vec(issueWidth, new MicroOp()))\n\n // interface with register file's read ports\n val rf_read_ports = Flipped(Vec(numTotalReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth)))\n val prf_read_ports = Flipped(Vec(issueWidth, new RegisterFileReadPortIO(log2Ceil(ftqSz), 1)))\n\n val bypass = Input(Vec(numTotalBypassPorts, Valid(new ExeUnitResp(registerWidth))))\n val pred_bypass = Input(Vec(numTotalPredBypassPorts, Valid(new ExeUnitResp(1))))\n\n // send micro-ops to the execution pipelines\n val exe_reqs = Vec(issueWidth, (new DecoupledIO(new FuncUnitReq(registerWidth))))\n\n val kill = Input(Bool())\n val brupdate = Input(new BrUpdateInfo())\n })\n\n val rrd_valids = Wire(Vec(issueWidth, Bool()))\n val rrd_uops = Wire(Vec(issueWidth, new MicroOp()))\n\n val exe_reg_valids = RegInit(VecInit(Seq.fill(issueWidth) { false.B }))\n val exe_reg_uops = Reg(Vec(issueWidth, new MicroOp()))\n val exe_reg_rs1_data = Reg(Vec(issueWidth, Bits(registerWidth.W)))\n val exe_reg_rs2_data = Reg(Vec(issueWidth, Bits(registerWidth.W)))\n val exe_reg_rs3_data = Reg(Vec(issueWidth, Bits(registerWidth.W)))\n val exe_reg_pred_data = Reg(Vec(issueWidth, Bool()))\n\n //-------------------------------------------------------------\n // hook up inputs\n\n for (w <- 0 until issueWidth) {\n val rrd_decode_unit = Module(new RegisterReadDecode(supportedUnitsArray(w)))\n rrd_decode_unit.io.iss_valid := io.iss_valids(w)\n rrd_decode_unit.io.iss_uop := io.iss_uops(w)\n\n rrd_valids(w) := RegNext(rrd_decode_unit.io.rrd_valid &&\n !IsKilledByBranch(io.brupdate, rrd_decode_unit.io.rrd_uop))\n rrd_uops(w) := RegNext(GetNewUopAndBrMask(rrd_decode_unit.io.rrd_uop, io.brupdate))\n }\n\n //-------------------------------------------------------------\n // read ports\n\n require (numTotalReadPorts == numReadPortsArray.reduce(_+_))\n\n val rrd_rs1_data = Wire(Vec(issueWidth, Bits(registerWidth.W)))\n val rrd_rs2_data = Wire(Vec(issueWidth, Bits(registerWidth.W)))\n val rrd_rs3_data = Wire(Vec(issueWidth, Bits(registerWidth.W)))\n val rrd_pred_data = Wire(Vec(issueWidth, Bool()))\n rrd_rs1_data := DontCare\n rrd_rs2_data := DontCare\n rrd_rs3_data := DontCare\n rrd_pred_data := DontCare\n\n io.prf_read_ports := DontCare\n\n var idx = 0 // index into flattened read_ports array\n for (w <- 0 until issueWidth) {\n val numReadPorts = numReadPortsArray(w)\n\n // NOTE:\n // rrdLatency==1, we need to send read address at end of ISS stage,\n // in order to get read data back at end of RRD stage.\n\n val rs1_addr = io.iss_uops(w).prs1\n val rs2_addr = io.iss_uops(w).prs2\n val rs3_addr = io.iss_uops(w).prs3\n val pred_addr = io.iss_uops(w).ppred\n\n if (numReadPorts > 0) io.rf_read_ports(idx+0).addr := rs1_addr\n if (numReadPorts > 1) io.rf_read_ports(idx+1).addr := rs2_addr\n if (numReadPorts > 2) io.rf_read_ports(idx+2).addr := rs3_addr\n\n if (enableSFBOpt) io.prf_read_ports(w).addr := pred_addr\n\n if (numReadPorts > 0) rrd_rs1_data(w) := Mux(RegNext(rs1_addr === 0.U), 0.U, io.rf_read_ports(idx+0).data)\n if (numReadPorts > 1) rrd_rs2_data(w) := Mux(RegNext(rs2_addr === 0.U), 0.U, io.rf_read_ports(idx+1).data)\n if (numReadPorts > 2) rrd_rs3_data(w) := Mux(RegNext(rs3_addr === 0.U), 0.U, io.rf_read_ports(idx+2).data)\n\n if (enableSFBOpt) rrd_pred_data(w) := Mux(RegNext(io.iss_uops(w).is_sfb_shadow), io.prf_read_ports(w).data, false.B)\n\n val rrd_kill = io.kill || IsKilledByBranch(io.brupdate, rrd_uops(w))\n\n exe_reg_valids(w) := Mux(rrd_kill, false.B, rrd_valids(w))\n // TODO use only the valids signal, don't require us to set nullUop\n exe_reg_uops(w) := Mux(rrd_kill, NullMicroOp, rrd_uops(w))\n\n exe_reg_uops(w).br_mask := GetNewBrMask(io.brupdate, rrd_uops(w))\n\n idx += numReadPorts\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // BYPASS MUXES -----------------------------------------------\n // performed at the end of the register read stage\n\n // NOTES: this code is fairly hard-coded. Sorry.\n // ASSUMPTIONS:\n // - rs3 is used for FPU ops which are NOT bypassed (so don't check\n // them!).\n // - only bypass integer registers.\n\n val bypassed_rs1_data = Wire(Vec(issueWidth, Bits(registerWidth.W)))\n val bypassed_rs2_data = Wire(Vec(issueWidth, Bits(registerWidth.W)))\n val bypassed_pred_data = Wire(Vec(issueWidth, Bool()))\n bypassed_pred_data := DontCare\n\n for (w <- 0 until issueWidth) {\n val numReadPorts = numReadPortsArray(w)\n var rs1_cases = Array((false.B, 0.U(registerWidth.W)))\n var rs2_cases = Array((false.B, 0.U(registerWidth.W)))\n var pred_cases = Array((false.B, 0.U(1.W)))\n\n val prs1 = rrd_uops(w).prs1\n val lrs1_rtype = rrd_uops(w).lrs1_rtype\n val prs2 = rrd_uops(w).prs2\n val lrs2_rtype = rrd_uops(w).lrs2_rtype\n val ppred = rrd_uops(w).ppred\n\n for (b <- 0 until numTotalBypassPorts)\n {\n val bypass = io.bypass(b)\n // can't use \"io.bypass.valid(b) since it would create a combinational loop on branch kills\"\n rs1_cases ++= Array((bypass.valid && (prs1 === bypass.bits.uop.pdst) && bypass.bits.uop.rf_wen\n && bypass.bits.uop.dst_rtype === RT_FIX && lrs1_rtype === RT_FIX && (prs1 =/= 0.U), bypass.bits.data))\n rs2_cases ++= Array((bypass.valid && (prs2 === bypass.bits.uop.pdst) && bypass.bits.uop.rf_wen\n && bypass.bits.uop.dst_rtype === RT_FIX && lrs2_rtype === RT_FIX && (prs2 =/= 0.U), bypass.bits.data))\n }\n\n for (b <- 0 until numTotalPredBypassPorts)\n {\n val bypass = io.pred_bypass(b)\n pred_cases ++= Array((bypass.valid && (ppred === bypass.bits.uop.pdst) && bypass.bits.uop.is_sfb_br, bypass.bits.data))\n }\n\n if (numReadPorts > 0) bypassed_rs1_data(w) := MuxCase(rrd_rs1_data(w), rs1_cases)\n if (numReadPorts > 1) bypassed_rs2_data(w) := MuxCase(rrd_rs2_data(w), rs2_cases)\n if (enableSFBOpt) bypassed_pred_data(w) := MuxCase(rrd_pred_data(w), pred_cases)\n }\n\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n // **** Execute Stage ****\n //-------------------------------------------------------------\n //-------------------------------------------------------------\n\n for (w <- 0 until issueWidth) {\n val numReadPorts = numReadPortsArray(w)\n if (numReadPorts > 0) exe_reg_rs1_data(w) := bypassed_rs1_data(w)\n if (numReadPorts > 1) exe_reg_rs2_data(w) := bypassed_rs2_data(w)\n if (numReadPorts > 2) exe_reg_rs3_data(w) := rrd_rs3_data(w)\n if (enableSFBOpt) exe_reg_pred_data(w) := bypassed_pred_data(w)\n // ASSUMPTION: rs3 is FPU which is NOT bypassed\n }\n // TODO add assert to detect bypass conflicts on non-bypassable things\n // TODO add assert that checks bypassing to verify there isn't something it hits rs3\n\n //-------------------------------------------------------------\n // set outputs to execute pipelines\n for (w <- 0 until issueWidth) {\n val numReadPorts = numReadPortsArray(w)\n\n io.exe_reqs(w).valid := exe_reg_valids(w)\n io.exe_reqs(w).bits := DontCare\n io.exe_reqs(w).bits.uop := exe_reg_uops(w)\n if (numReadPorts > 0) io.exe_reqs(w).bits.rs1_data := exe_reg_rs1_data(w)\n if (numReadPorts > 1) io.exe_reqs(w).bits.rs2_data := exe_reg_rs2_data(w)\n if (numReadPorts > 2) io.exe_reqs(w).bits.rs3_data := exe_reg_rs3_data(w)\n if (enableSFBOpt) io.exe_reqs(w).bits.pred_data := exe_reg_pred_data(w)\n }\n}", + "response": "module RegisterRead(\n input clock,\n input reset,\n input io_iss_valids_0,\n input [6:0] io_iss_uops_0_uopc,\n input [31:0] io_iss_uops_0_inst,\n input [31:0] io_iss_uops_0_debug_inst,\n input io_iss_uops_0_is_rvc,\n input [39:0] io_iss_uops_0_debug_pc,\n input [2:0] io_iss_uops_0_iq_type,\n input [9:0] io_iss_uops_0_fu_code,\n input [1:0] io_iss_uops_0_iw_state,\n input io_iss_uops_0_is_br,\n input io_iss_uops_0_is_jalr,\n input io_iss_uops_0_is_jal,\n input io_iss_uops_0_is_sfb,\n input [7:0] io_iss_uops_0_br_mask,\n input [2:0] io_iss_uops_0_br_tag,\n input [3:0] io_iss_uops_0_ftq_idx,\n input io_iss_uops_0_edge_inst,\n input [5:0] io_iss_uops_0_pc_lob,\n input io_iss_uops_0_taken,\n input [19:0] io_iss_uops_0_imm_packed,\n input [11:0] io_iss_uops_0_csr_addr,\n input [4:0] io_iss_uops_0_rob_idx,\n input [2:0] io_iss_uops_0_ldq_idx,\n input [2:0] io_iss_uops_0_stq_idx,\n input [1:0] io_iss_uops_0_rxq_idx,\n input [5:0] io_iss_uops_0_pdst,\n input [5:0] io_iss_uops_0_prs1,\n input [5:0] io_iss_uops_0_prs2,\n input [5:0] io_iss_uops_0_prs3,\n input [3:0] io_iss_uops_0_ppred,\n input io_iss_uops_0_prs1_busy,\n input io_iss_uops_0_prs2_busy,\n input io_iss_uops_0_prs3_busy,\n input io_iss_uops_0_ppred_busy,\n input [5:0] io_iss_uops_0_stale_pdst,\n input io_iss_uops_0_exception,\n input [63:0] io_iss_uops_0_exc_cause,\n input io_iss_uops_0_bypassable,\n input [4:0] io_iss_uops_0_mem_cmd,\n input [1:0] io_iss_uops_0_mem_size,\n input io_iss_uops_0_mem_signed,\n input io_iss_uops_0_is_fence,\n input io_iss_uops_0_is_fencei,\n input io_iss_uops_0_is_amo,\n input io_iss_uops_0_uses_ldq,\n input io_iss_uops_0_uses_stq,\n input io_iss_uops_0_is_sys_pc2epc,\n input io_iss_uops_0_is_unique,\n input io_iss_uops_0_flush_on_commit,\n input io_iss_uops_0_ldst_is_rs1,\n input [5:0] io_iss_uops_0_ldst,\n input [5:0] io_iss_uops_0_lrs1,\n input [5:0] io_iss_uops_0_lrs2,\n input [5:0] io_iss_uops_0_lrs3,\n input io_iss_uops_0_ldst_val,\n input [1:0] io_iss_uops_0_dst_rtype,\n input [1:0] io_iss_uops_0_lrs1_rtype,\n input [1:0] io_iss_uops_0_lrs2_rtype,\n input io_iss_uops_0_frs3_en,\n input io_iss_uops_0_fp_val,\n input io_iss_uops_0_fp_single,\n input io_iss_uops_0_xcpt_pf_if,\n input io_iss_uops_0_xcpt_ae_if,\n input io_iss_uops_0_xcpt_ma_if,\n input io_iss_uops_0_bp_debug_if,\n input io_iss_uops_0_bp_xcpt_if,\n input [1:0] io_iss_uops_0_debug_fsrc,\n input [1:0] io_iss_uops_0_debug_tsrc,\n output [5:0] io_rf_read_ports_0_addr,\n input [64:0] io_rf_read_ports_0_data,\n output [5:0] io_rf_read_ports_1_addr,\n input [64:0] io_rf_read_ports_1_data,\n output [5:0] io_rf_read_ports_2_addr,\n input [64:0] io_rf_read_ports_2_data,\n output io_exe_reqs_0_valid,\n output [6:0] io_exe_reqs_0_bits_uop_uopc,\n output [31:0] io_exe_reqs_0_bits_uop_inst,\n output [31:0] io_exe_reqs_0_bits_uop_debug_inst,\n output io_exe_reqs_0_bits_uop_is_rvc,\n output [39:0] io_exe_reqs_0_bits_uop_debug_pc,\n output [2:0] io_exe_reqs_0_bits_uop_iq_type,\n output [9:0] io_exe_reqs_0_bits_uop_fu_code,\n output [3:0] io_exe_reqs_0_bits_uop_ctrl_br_type,\n output [1:0] io_exe_reqs_0_bits_uop_ctrl_op1_sel,\n output [2:0] io_exe_reqs_0_bits_uop_ctrl_op2_sel,\n output [2:0] io_exe_reqs_0_bits_uop_ctrl_imm_sel,\n output [4:0] io_exe_reqs_0_bits_uop_ctrl_op_fcn,\n output io_exe_reqs_0_bits_uop_ctrl_fcn_dw,\n output [2:0] io_exe_reqs_0_bits_uop_ctrl_csr_cmd,\n output io_exe_reqs_0_bits_uop_ctrl_is_load,\n output io_exe_reqs_0_bits_uop_ctrl_is_sta,\n output io_exe_reqs_0_bits_uop_ctrl_is_std,\n output [1:0] io_exe_reqs_0_bits_uop_iw_state,\n output io_exe_reqs_0_bits_uop_iw_p1_poisoned,\n output io_exe_reqs_0_bits_uop_iw_p2_poisoned,\n output io_exe_reqs_0_bits_uop_is_br,\n output io_exe_reqs_0_bits_uop_is_jalr,\n output io_exe_reqs_0_bits_uop_is_jal,\n output io_exe_reqs_0_bits_uop_is_sfb,\n output [7:0] io_exe_reqs_0_bits_uop_br_mask,\n output [2:0] io_exe_reqs_0_bits_uop_br_tag,\n output [3:0] io_exe_reqs_0_bits_uop_ftq_idx,\n output io_exe_reqs_0_bits_uop_edge_inst,\n output [5:0] io_exe_reqs_0_bits_uop_pc_lob,\n output io_exe_reqs_0_bits_uop_taken,\n output [19:0] io_exe_reqs_0_bits_uop_imm_packed,\n output [11:0] io_exe_reqs_0_bits_uop_csr_addr,\n output [4:0] io_exe_reqs_0_bits_uop_rob_idx,\n output [2:0] io_exe_reqs_0_bits_uop_ldq_idx,\n output [2:0] io_exe_reqs_0_bits_uop_stq_idx,\n output [1:0] io_exe_reqs_0_bits_uop_rxq_idx,\n output [5:0] io_exe_reqs_0_bits_uop_pdst,\n output [5:0] io_exe_reqs_0_bits_uop_prs1,\n output [5:0] io_exe_reqs_0_bits_uop_prs2,\n output [5:0] io_exe_reqs_0_bits_uop_prs3,\n output [3:0] io_exe_reqs_0_bits_uop_ppred,\n output io_exe_reqs_0_bits_uop_prs1_busy,\n output io_exe_reqs_0_bits_uop_prs2_busy,\n output io_exe_reqs_0_bits_uop_prs3_busy,\n output io_exe_reqs_0_bits_uop_ppred_busy,\n output [5:0] io_exe_reqs_0_bits_uop_stale_pdst,\n output io_exe_reqs_0_bits_uop_exception,\n output [63:0] io_exe_reqs_0_bits_uop_exc_cause,\n output io_exe_reqs_0_bits_uop_bypassable,\n output [4:0] io_exe_reqs_0_bits_uop_mem_cmd,\n output [1:0] io_exe_reqs_0_bits_uop_mem_size,\n output io_exe_reqs_0_bits_uop_mem_signed,\n output io_exe_reqs_0_bits_uop_is_fence,\n output io_exe_reqs_0_bits_uop_is_fencei,\n output io_exe_reqs_0_bits_uop_is_amo,\n output io_exe_reqs_0_bits_uop_uses_ldq,\n output io_exe_reqs_0_bits_uop_uses_stq,\n output io_exe_reqs_0_bits_uop_is_sys_pc2epc,\n output io_exe_reqs_0_bits_uop_is_unique,\n output io_exe_reqs_0_bits_uop_flush_on_commit,\n output io_exe_reqs_0_bits_uop_ldst_is_rs1,\n output [5:0] io_exe_reqs_0_bits_uop_ldst,\n output [5:0] io_exe_reqs_0_bits_uop_lrs1,\n output [5:0] io_exe_reqs_0_bits_uop_lrs2,\n output [5:0] io_exe_reqs_0_bits_uop_lrs3,\n output io_exe_reqs_0_bits_uop_ldst_val,\n output [1:0] io_exe_reqs_0_bits_uop_dst_rtype,\n output [1:0] io_exe_reqs_0_bits_uop_lrs1_rtype,\n output [1:0] io_exe_reqs_0_bits_uop_lrs2_rtype,\n output io_exe_reqs_0_bits_uop_frs3_en,\n output io_exe_reqs_0_bits_uop_fp_val,\n output io_exe_reqs_0_bits_uop_fp_single,\n output io_exe_reqs_0_bits_uop_xcpt_pf_if,\n output io_exe_reqs_0_bits_uop_xcpt_ae_if,\n output io_exe_reqs_0_bits_uop_xcpt_ma_if,\n output io_exe_reqs_0_bits_uop_bp_debug_if,\n output io_exe_reqs_0_bits_uop_bp_xcpt_if,\n output [1:0] io_exe_reqs_0_bits_uop_debug_fsrc,\n output [1:0] io_exe_reqs_0_bits_uop_debug_tsrc,\n output [64:0] io_exe_reqs_0_bits_rs1_data,\n output [64:0] io_exe_reqs_0_bits_rs2_data,\n output [64:0] io_exe_reqs_0_bits_rs3_data,\n input io_kill,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [7:0] io_brupdate_b1_mispredict_mask\n);\n\n wire _rrd_decode_unit_io_rrd_valid;\n wire [6:0] _rrd_decode_unit_io_rrd_uop_uopc;\n wire [31:0] _rrd_decode_unit_io_rrd_uop_inst;\n wire [31:0] _rrd_decode_unit_io_rrd_uop_debug_inst;\n wire _rrd_decode_unit_io_rrd_uop_is_rvc;\n wire [39:0] _rrd_decode_unit_io_rrd_uop_debug_pc;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_iq_type;\n wire [9:0] _rrd_decode_unit_io_rrd_uop_fu_code;\n wire [3:0] _rrd_decode_unit_io_rrd_uop_ctrl_br_type;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_ctrl_op1_sel;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_ctrl_op2_sel;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_ctrl_imm_sel;\n wire [4:0] _rrd_decode_unit_io_rrd_uop_ctrl_op_fcn;\n wire _rrd_decode_unit_io_rrd_uop_ctrl_fcn_dw;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_ctrl_csr_cmd;\n wire _rrd_decode_unit_io_rrd_uop_ctrl_is_load;\n wire _rrd_decode_unit_io_rrd_uop_ctrl_is_sta;\n wire _rrd_decode_unit_io_rrd_uop_ctrl_is_std;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_iw_state;\n wire _rrd_decode_unit_io_rrd_uop_is_br;\n wire _rrd_decode_unit_io_rrd_uop_is_jalr;\n wire _rrd_decode_unit_io_rrd_uop_is_jal;\n wire _rrd_decode_unit_io_rrd_uop_is_sfb;\n wire [7:0] _rrd_decode_unit_io_rrd_uop_br_mask;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_br_tag;\n wire [3:0] _rrd_decode_unit_io_rrd_uop_ftq_idx;\n wire _rrd_decode_unit_io_rrd_uop_edge_inst;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_pc_lob;\n wire _rrd_decode_unit_io_rrd_uop_taken;\n wire [19:0] _rrd_decode_unit_io_rrd_uop_imm_packed;\n wire [11:0] _rrd_decode_unit_io_rrd_uop_csr_addr;\n wire [4:0] _rrd_decode_unit_io_rrd_uop_rob_idx;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_ldq_idx;\n wire [2:0] _rrd_decode_unit_io_rrd_uop_stq_idx;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_rxq_idx;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_pdst;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_prs1;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_prs2;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_prs3;\n wire [3:0] _rrd_decode_unit_io_rrd_uop_ppred;\n wire _rrd_decode_unit_io_rrd_uop_prs1_busy;\n wire _rrd_decode_unit_io_rrd_uop_prs2_busy;\n wire _rrd_decode_unit_io_rrd_uop_prs3_busy;\n wire _rrd_decode_unit_io_rrd_uop_ppred_busy;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_stale_pdst;\n wire _rrd_decode_unit_io_rrd_uop_exception;\n wire [63:0] _rrd_decode_unit_io_rrd_uop_exc_cause;\n wire _rrd_decode_unit_io_rrd_uop_bypassable;\n wire [4:0] _rrd_decode_unit_io_rrd_uop_mem_cmd;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_mem_size;\n wire _rrd_decode_unit_io_rrd_uop_mem_signed;\n wire _rrd_decode_unit_io_rrd_uop_is_fence;\n wire _rrd_decode_unit_io_rrd_uop_is_fencei;\n wire _rrd_decode_unit_io_rrd_uop_is_amo;\n wire _rrd_decode_unit_io_rrd_uop_uses_ldq;\n wire _rrd_decode_unit_io_rrd_uop_uses_stq;\n wire _rrd_decode_unit_io_rrd_uop_is_sys_pc2epc;\n wire _rrd_decode_unit_io_rrd_uop_is_unique;\n wire _rrd_decode_unit_io_rrd_uop_flush_on_commit;\n wire _rrd_decode_unit_io_rrd_uop_ldst_is_rs1;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_ldst;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_lrs1;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_lrs2;\n wire [5:0] _rrd_decode_unit_io_rrd_uop_lrs3;\n wire _rrd_decode_unit_io_rrd_uop_ldst_val;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_dst_rtype;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_lrs1_rtype;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_lrs2_rtype;\n wire _rrd_decode_unit_io_rrd_uop_frs3_en;\n wire _rrd_decode_unit_io_rrd_uop_fp_val;\n wire _rrd_decode_unit_io_rrd_uop_fp_single;\n wire _rrd_decode_unit_io_rrd_uop_xcpt_pf_if;\n wire _rrd_decode_unit_io_rrd_uop_xcpt_ae_if;\n wire _rrd_decode_unit_io_rrd_uop_xcpt_ma_if;\n wire _rrd_decode_unit_io_rrd_uop_bp_debug_if;\n wire _rrd_decode_unit_io_rrd_uop_bp_xcpt_if;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_debug_fsrc;\n wire [1:0] _rrd_decode_unit_io_rrd_uop_debug_tsrc;\n reg exe_reg_valids_0;\n reg [6:0] exe_reg_uops_0_uopc;\n reg [31:0] exe_reg_uops_0_inst;\n reg [31:0] exe_reg_uops_0_debug_inst;\n reg exe_reg_uops_0_is_rvc;\n reg [39:0] exe_reg_uops_0_debug_pc;\n reg [2:0] exe_reg_uops_0_iq_type;\n reg [9:0] exe_reg_uops_0_fu_code;\n reg [3:0] exe_reg_uops_0_ctrl_br_type;\n reg [1:0] exe_reg_uops_0_ctrl_op1_sel;\n reg [2:0] exe_reg_uops_0_ctrl_op2_sel;\n reg [2:0] exe_reg_uops_0_ctrl_imm_sel;\n reg [4:0] exe_reg_uops_0_ctrl_op_fcn;\n reg exe_reg_uops_0_ctrl_fcn_dw;\n reg [2:0] exe_reg_uops_0_ctrl_csr_cmd;\n reg exe_reg_uops_0_ctrl_is_load;\n reg exe_reg_uops_0_ctrl_is_sta;\n reg exe_reg_uops_0_ctrl_is_std;\n reg [1:0] exe_reg_uops_0_iw_state;\n reg exe_reg_uops_0_iw_p1_poisoned;\n reg exe_reg_uops_0_iw_p2_poisoned;\n reg exe_reg_uops_0_is_br;\n reg exe_reg_uops_0_is_jalr;\n reg exe_reg_uops_0_is_jal;\n reg exe_reg_uops_0_is_sfb;\n reg [7:0] exe_reg_uops_0_br_mask;\n reg [2:0] exe_reg_uops_0_br_tag;\n reg [3:0] exe_reg_uops_0_ftq_idx;\n reg exe_reg_uops_0_edge_inst;\n reg [5:0] exe_reg_uops_0_pc_lob;\n reg exe_reg_uops_0_taken;\n reg [19:0] exe_reg_uops_0_imm_packed;\n reg [11:0] exe_reg_uops_0_csr_addr;\n reg [4:0] exe_reg_uops_0_rob_idx;\n reg [2:0] exe_reg_uops_0_ldq_idx;\n reg [2:0] exe_reg_uops_0_stq_idx;\n reg [1:0] exe_reg_uops_0_rxq_idx;\n reg [5:0] exe_reg_uops_0_pdst;\n reg [5:0] exe_reg_uops_0_prs1;\n reg [5:0] exe_reg_uops_0_prs2;\n reg [5:0] exe_reg_uops_0_prs3;\n reg [3:0] exe_reg_uops_0_ppred;\n reg exe_reg_uops_0_prs1_busy;\n reg exe_reg_uops_0_prs2_busy;\n reg exe_reg_uops_0_prs3_busy;\n reg exe_reg_uops_0_ppred_busy;\n reg [5:0] exe_reg_uops_0_stale_pdst;\n reg exe_reg_uops_0_exception;\n reg [63:0] exe_reg_uops_0_exc_cause;\n reg exe_reg_uops_0_bypassable;\n reg [4:0] exe_reg_uops_0_mem_cmd;\n reg [1:0] exe_reg_uops_0_mem_size;\n reg exe_reg_uops_0_mem_signed;\n reg exe_reg_uops_0_is_fence;\n reg exe_reg_uops_0_is_fencei;\n reg exe_reg_uops_0_is_amo;\n reg exe_reg_uops_0_uses_ldq;\n reg exe_reg_uops_0_uses_stq;\n reg exe_reg_uops_0_is_sys_pc2epc;\n reg exe_reg_uops_0_is_unique;\n reg exe_reg_uops_0_flush_on_commit;\n reg exe_reg_uops_0_ldst_is_rs1;\n reg [5:0] exe_reg_uops_0_ldst;\n reg [5:0] exe_reg_uops_0_lrs1;\n reg [5:0] exe_reg_uops_0_lrs2;\n reg [5:0] exe_reg_uops_0_lrs3;\n reg exe_reg_uops_0_ldst_val;\n reg [1:0] exe_reg_uops_0_dst_rtype;\n reg [1:0] exe_reg_uops_0_lrs1_rtype;\n reg [1:0] exe_reg_uops_0_lrs2_rtype;\n reg exe_reg_uops_0_frs3_en;\n reg exe_reg_uops_0_fp_val;\n reg exe_reg_uops_0_fp_single;\n reg exe_reg_uops_0_xcpt_pf_if;\n reg exe_reg_uops_0_xcpt_ae_if;\n reg exe_reg_uops_0_xcpt_ma_if;\n reg exe_reg_uops_0_bp_debug_if;\n reg exe_reg_uops_0_bp_xcpt_if;\n reg [1:0] exe_reg_uops_0_debug_fsrc;\n reg [1:0] exe_reg_uops_0_debug_tsrc;\n reg [64:0] exe_reg_rs1_data_0;\n reg [64:0] exe_reg_rs2_data_0;\n reg [64:0] exe_reg_rs3_data_0;\n reg rrd_valids_0_REG;\n reg [6:0] rrd_uops_0_REG_uopc;\n reg [31:0] rrd_uops_0_REG_inst;\n reg [31:0] rrd_uops_0_REG_debug_inst;\n reg rrd_uops_0_REG_is_rvc;\n reg [39:0] rrd_uops_0_REG_debug_pc;\n reg [2:0] rrd_uops_0_REG_iq_type;\n reg [9:0] rrd_uops_0_REG_fu_code;\n reg [3:0] rrd_uops_0_REG_ctrl_br_type;\n reg [1:0] rrd_uops_0_REG_ctrl_op1_sel;\n reg [2:0] rrd_uops_0_REG_ctrl_op2_sel;\n reg [2:0] rrd_uops_0_REG_ctrl_imm_sel;\n reg [4:0] rrd_uops_0_REG_ctrl_op_fcn;\n reg rrd_uops_0_REG_ctrl_fcn_dw;\n reg [2:0] rrd_uops_0_REG_ctrl_csr_cmd;\n reg rrd_uops_0_REG_ctrl_is_load;\n reg rrd_uops_0_REG_ctrl_is_sta;\n reg rrd_uops_0_REG_ctrl_is_std;\n reg [1:0] rrd_uops_0_REG_iw_state;\n reg rrd_uops_0_REG_iw_p1_poisoned;\n reg rrd_uops_0_REG_iw_p2_poisoned;\n reg rrd_uops_0_REG_is_br;\n reg rrd_uops_0_REG_is_jalr;\n reg rrd_uops_0_REG_is_jal;\n reg rrd_uops_0_REG_is_sfb;\n reg [7:0] rrd_uops_0_REG_br_mask;\n reg [2:0] rrd_uops_0_REG_br_tag;\n reg [3:0] rrd_uops_0_REG_ftq_idx;\n reg rrd_uops_0_REG_edge_inst;\n reg [5:0] rrd_uops_0_REG_pc_lob;\n reg rrd_uops_0_REG_taken;\n reg [19:0] rrd_uops_0_REG_imm_packed;\n reg [11:0] rrd_uops_0_REG_csr_addr;\n reg [4:0] rrd_uops_0_REG_rob_idx;\n reg [2:0] rrd_uops_0_REG_ldq_idx;\n reg [2:0] rrd_uops_0_REG_stq_idx;\n reg [1:0] rrd_uops_0_REG_rxq_idx;\n reg [5:0] rrd_uops_0_REG_pdst;\n reg [5:0] rrd_uops_0_REG_prs1;\n reg [5:0] rrd_uops_0_REG_prs2;\n reg [5:0] rrd_uops_0_REG_prs3;\n reg [3:0] rrd_uops_0_REG_ppred;\n reg rrd_uops_0_REG_prs1_busy;\n reg rrd_uops_0_REG_prs2_busy;\n reg rrd_uops_0_REG_prs3_busy;\n reg rrd_uops_0_REG_ppred_busy;\n reg [5:0] rrd_uops_0_REG_stale_pdst;\n reg rrd_uops_0_REG_exception;\n reg [63:0] rrd_uops_0_REG_exc_cause;\n reg rrd_uops_0_REG_bypassable;\n reg [4:0] rrd_uops_0_REG_mem_cmd;\n reg [1:0] rrd_uops_0_REG_mem_size;\n reg rrd_uops_0_REG_mem_signed;\n reg rrd_uops_0_REG_is_fence;\n reg rrd_uops_0_REG_is_fencei;\n reg rrd_uops_0_REG_is_amo;\n reg rrd_uops_0_REG_uses_ldq;\n reg rrd_uops_0_REG_uses_stq;\n reg rrd_uops_0_REG_is_sys_pc2epc;\n reg rrd_uops_0_REG_is_unique;\n reg rrd_uops_0_REG_flush_on_commit;\n reg rrd_uops_0_REG_ldst_is_rs1;\n reg [5:0] rrd_uops_0_REG_ldst;\n reg [5:0] rrd_uops_0_REG_lrs1;\n reg [5:0] rrd_uops_0_REG_lrs2;\n reg [5:0] rrd_uops_0_REG_lrs3;\n reg rrd_uops_0_REG_ldst_val;\n reg [1:0] rrd_uops_0_REG_dst_rtype;\n reg [1:0] rrd_uops_0_REG_lrs1_rtype;\n reg [1:0] rrd_uops_0_REG_lrs2_rtype;\n reg rrd_uops_0_REG_frs3_en;\n reg rrd_uops_0_REG_fp_val;\n reg rrd_uops_0_REG_fp_single;\n reg rrd_uops_0_REG_xcpt_pf_if;\n reg rrd_uops_0_REG_xcpt_ae_if;\n reg rrd_uops_0_REG_xcpt_ma_if;\n reg rrd_uops_0_REG_bp_debug_if;\n reg rrd_uops_0_REG_bp_xcpt_if;\n reg [1:0] rrd_uops_0_REG_debug_fsrc;\n reg [1:0] rrd_uops_0_REG_debug_tsrc;\n reg rrd_rs1_data_0_REG;\n reg rrd_rs2_data_0_REG;\n reg rrd_rs3_data_0_REG;\n wire [8:0] _GEN = {io_kill, io_brupdate_b1_mispredict_mask & rrd_uops_0_REG_br_mask};\n always @(posedge clock) begin\n if (reset)\n exe_reg_valids_0 <= 1'h0;\n else\n exe_reg_valids_0 <= ~(|_GEN) & rrd_valids_0_REG;\n exe_reg_uops_0_uopc <= (|_GEN) ? 7'h0 : rrd_uops_0_REG_uopc;\n exe_reg_uops_0_inst <= (|_GEN) ? 32'h0 : rrd_uops_0_REG_inst;\n exe_reg_uops_0_debug_inst <= (|_GEN) ? 32'h0 : rrd_uops_0_REG_debug_inst;\n exe_reg_uops_0_is_rvc <= ~(|_GEN) & rrd_uops_0_REG_is_rvc;\n exe_reg_uops_0_debug_pc <= (|_GEN) ? 40'h0 : rrd_uops_0_REG_debug_pc;\n exe_reg_uops_0_iq_type <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_iq_type;\n exe_reg_uops_0_fu_code <= (|_GEN) ? 10'h0 : rrd_uops_0_REG_fu_code;\n exe_reg_uops_0_ctrl_br_type <= (|_GEN) ? 4'h0 : rrd_uops_0_REG_ctrl_br_type;\n exe_reg_uops_0_ctrl_op1_sel <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_ctrl_op1_sel;\n exe_reg_uops_0_ctrl_op2_sel <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_ctrl_op2_sel;\n exe_reg_uops_0_ctrl_imm_sel <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_ctrl_imm_sel;\n exe_reg_uops_0_ctrl_op_fcn <= (|_GEN) ? 5'h0 : rrd_uops_0_REG_ctrl_op_fcn;\n exe_reg_uops_0_ctrl_fcn_dw <= ~(|_GEN) & rrd_uops_0_REG_ctrl_fcn_dw;\n exe_reg_uops_0_ctrl_csr_cmd <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_ctrl_csr_cmd;\n exe_reg_uops_0_ctrl_is_load <= ~(|_GEN) & rrd_uops_0_REG_ctrl_is_load;\n exe_reg_uops_0_ctrl_is_sta <= ~(|_GEN) & rrd_uops_0_REG_ctrl_is_sta;\n exe_reg_uops_0_ctrl_is_std <= ~(|_GEN) & rrd_uops_0_REG_ctrl_is_std;\n exe_reg_uops_0_iw_state <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_iw_state;\n exe_reg_uops_0_iw_p1_poisoned <= ~(|_GEN) & rrd_uops_0_REG_iw_p1_poisoned;\n exe_reg_uops_0_iw_p2_poisoned <= ~(|_GEN) & rrd_uops_0_REG_iw_p2_poisoned;\n exe_reg_uops_0_is_br <= ~(|_GEN) & rrd_uops_0_REG_is_br;\n exe_reg_uops_0_is_jalr <= ~(|_GEN) & rrd_uops_0_REG_is_jalr;\n exe_reg_uops_0_is_jal <= ~(|_GEN) & rrd_uops_0_REG_is_jal;\n exe_reg_uops_0_is_sfb <= ~(|_GEN) & rrd_uops_0_REG_is_sfb;\n exe_reg_uops_0_br_mask <= rrd_uops_0_REG_br_mask & ~io_brupdate_b1_resolve_mask;\n exe_reg_uops_0_br_tag <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_br_tag;\n exe_reg_uops_0_ftq_idx <= (|_GEN) ? 4'h0 : rrd_uops_0_REG_ftq_idx;\n exe_reg_uops_0_edge_inst <= ~(|_GEN) & rrd_uops_0_REG_edge_inst;\n exe_reg_uops_0_pc_lob <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_pc_lob;\n exe_reg_uops_0_taken <= ~(|_GEN) & rrd_uops_0_REG_taken;\n exe_reg_uops_0_imm_packed <= (|_GEN) ? 20'h0 : rrd_uops_0_REG_imm_packed;\n exe_reg_uops_0_csr_addr <= (|_GEN) ? 12'h0 : rrd_uops_0_REG_csr_addr;\n exe_reg_uops_0_rob_idx <= (|_GEN) ? 5'h0 : rrd_uops_0_REG_rob_idx;\n exe_reg_uops_0_ldq_idx <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_ldq_idx;\n exe_reg_uops_0_stq_idx <= (|_GEN) ? 3'h0 : rrd_uops_0_REG_stq_idx;\n exe_reg_uops_0_rxq_idx <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_rxq_idx;\n exe_reg_uops_0_pdst <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_pdst;\n exe_reg_uops_0_prs1 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_prs1;\n exe_reg_uops_0_prs2 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_prs2;\n exe_reg_uops_0_prs3 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_prs3;\n exe_reg_uops_0_ppred <= (|_GEN) ? 4'h0 : rrd_uops_0_REG_ppred;\n exe_reg_uops_0_prs1_busy <= ~(|_GEN) & rrd_uops_0_REG_prs1_busy;\n exe_reg_uops_0_prs2_busy <= ~(|_GEN) & rrd_uops_0_REG_prs2_busy;\n exe_reg_uops_0_prs3_busy <= ~(|_GEN) & rrd_uops_0_REG_prs3_busy;\n exe_reg_uops_0_ppred_busy <= ~(|_GEN) & rrd_uops_0_REG_ppred_busy;\n exe_reg_uops_0_stale_pdst <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_stale_pdst;\n exe_reg_uops_0_exception <= ~(|_GEN) & rrd_uops_0_REG_exception;\n exe_reg_uops_0_exc_cause <= (|_GEN) ? 64'h0 : rrd_uops_0_REG_exc_cause;\n exe_reg_uops_0_bypassable <= ~(|_GEN) & rrd_uops_0_REG_bypassable;\n exe_reg_uops_0_mem_cmd <= (|_GEN) ? 5'h0 : rrd_uops_0_REG_mem_cmd;\n exe_reg_uops_0_mem_size <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_mem_size;\n exe_reg_uops_0_mem_signed <= ~(|_GEN) & rrd_uops_0_REG_mem_signed;\n exe_reg_uops_0_is_fence <= ~(|_GEN) & rrd_uops_0_REG_is_fence;\n exe_reg_uops_0_is_fencei <= ~(|_GEN) & rrd_uops_0_REG_is_fencei;\n exe_reg_uops_0_is_amo <= ~(|_GEN) & rrd_uops_0_REG_is_amo;\n exe_reg_uops_0_uses_ldq <= ~(|_GEN) & rrd_uops_0_REG_uses_ldq;\n exe_reg_uops_0_uses_stq <= ~(|_GEN) & rrd_uops_0_REG_uses_stq;\n exe_reg_uops_0_is_sys_pc2epc <= ~(|_GEN) & rrd_uops_0_REG_is_sys_pc2epc;\n exe_reg_uops_0_is_unique <= ~(|_GEN) & rrd_uops_0_REG_is_unique;\n exe_reg_uops_0_flush_on_commit <= ~(|_GEN) & rrd_uops_0_REG_flush_on_commit;\n exe_reg_uops_0_ldst_is_rs1 <= ~(|_GEN) & rrd_uops_0_REG_ldst_is_rs1;\n exe_reg_uops_0_ldst <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_ldst;\n exe_reg_uops_0_lrs1 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_lrs1;\n exe_reg_uops_0_lrs2 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_lrs2;\n exe_reg_uops_0_lrs3 <= (|_GEN) ? 6'h0 : rrd_uops_0_REG_lrs3;\n exe_reg_uops_0_ldst_val <= ~(|_GEN) & rrd_uops_0_REG_ldst_val;\n exe_reg_uops_0_dst_rtype <= (|_GEN) ? 2'h2 : rrd_uops_0_REG_dst_rtype;\n exe_reg_uops_0_lrs1_rtype <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_lrs1_rtype;\n exe_reg_uops_0_lrs2_rtype <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_lrs2_rtype;\n exe_reg_uops_0_frs3_en <= ~(|_GEN) & rrd_uops_0_REG_frs3_en;\n exe_reg_uops_0_fp_val <= ~(|_GEN) & rrd_uops_0_REG_fp_val;\n exe_reg_uops_0_fp_single <= ~(|_GEN) & rrd_uops_0_REG_fp_single;\n exe_reg_uops_0_xcpt_pf_if <= ~(|_GEN) & rrd_uops_0_REG_xcpt_pf_if;\n exe_reg_uops_0_xcpt_ae_if <= ~(|_GEN) & rrd_uops_0_REG_xcpt_ae_if;\n exe_reg_uops_0_xcpt_ma_if <= ~(|_GEN) & rrd_uops_0_REG_xcpt_ma_if;\n exe_reg_uops_0_bp_debug_if <= ~(|_GEN) & rrd_uops_0_REG_bp_debug_if;\n exe_reg_uops_0_bp_xcpt_if <= ~(|_GEN) & rrd_uops_0_REG_bp_xcpt_if;\n exe_reg_uops_0_debug_fsrc <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_debug_fsrc;\n exe_reg_uops_0_debug_tsrc <= (|_GEN) ? 2'h0 : rrd_uops_0_REG_debug_tsrc;\n exe_reg_rs1_data_0 <= rrd_rs1_data_0_REG ? 65'h0 : io_rf_read_ports_0_data;\n exe_reg_rs2_data_0 <= rrd_rs2_data_0_REG ? 65'h0 : io_rf_read_ports_1_data;\n exe_reg_rs3_data_0 <= rrd_rs3_data_0_REG ? 65'h0 : io_rf_read_ports_2_data;\n rrd_valids_0_REG <= _rrd_decode_unit_io_rrd_valid & (io_brupdate_b1_mispredict_mask & _rrd_decode_unit_io_rrd_uop_br_mask) == 8'h0;\n rrd_uops_0_REG_uopc <= _rrd_decode_unit_io_rrd_uop_uopc;\n rrd_uops_0_REG_inst <= _rrd_decode_unit_io_rrd_uop_inst;\n rrd_uops_0_REG_debug_inst <= _rrd_decode_unit_io_rrd_uop_debug_inst;\n rrd_uops_0_REG_is_rvc <= _rrd_decode_unit_io_rrd_uop_is_rvc;\n rrd_uops_0_REG_debug_pc <= _rrd_decode_unit_io_rrd_uop_debug_pc;\n rrd_uops_0_REG_iq_type <= _rrd_decode_unit_io_rrd_uop_iq_type;\n rrd_uops_0_REG_fu_code <= _rrd_decode_unit_io_rrd_uop_fu_code;\n rrd_uops_0_REG_ctrl_br_type <= _rrd_decode_unit_io_rrd_uop_ctrl_br_type;\n rrd_uops_0_REG_ctrl_op1_sel <= _rrd_decode_unit_io_rrd_uop_ctrl_op1_sel;\n rrd_uops_0_REG_ctrl_op2_sel <= _rrd_decode_unit_io_rrd_uop_ctrl_op2_sel;\n rrd_uops_0_REG_ctrl_imm_sel <= _rrd_decode_unit_io_rrd_uop_ctrl_imm_sel;\n rrd_uops_0_REG_ctrl_op_fcn <= _rrd_decode_unit_io_rrd_uop_ctrl_op_fcn;\n rrd_uops_0_REG_ctrl_fcn_dw <= _rrd_decode_unit_io_rrd_uop_ctrl_fcn_dw;\n rrd_uops_0_REG_ctrl_csr_cmd <= _rrd_decode_unit_io_rrd_uop_ctrl_csr_cmd;\n rrd_uops_0_REG_ctrl_is_load <= _rrd_decode_unit_io_rrd_uop_ctrl_is_load;\n rrd_uops_0_REG_ctrl_is_sta <= _rrd_decode_unit_io_rrd_uop_ctrl_is_sta;\n rrd_uops_0_REG_ctrl_is_std <= _rrd_decode_unit_io_rrd_uop_ctrl_is_std;\n rrd_uops_0_REG_iw_state <= _rrd_decode_unit_io_rrd_uop_iw_state;\n rrd_uops_0_REG_iw_p1_poisoned <= 1'h0;\n rrd_uops_0_REG_iw_p2_poisoned <= 1'h0;\n rrd_uops_0_REG_is_br <= _rrd_decode_unit_io_rrd_uop_is_br;\n rrd_uops_0_REG_is_jalr <= _rrd_decode_unit_io_rrd_uop_is_jalr;\n rrd_uops_0_REG_is_jal <= _rrd_decode_unit_io_rrd_uop_is_jal;\n rrd_uops_0_REG_is_sfb <= _rrd_decode_unit_io_rrd_uop_is_sfb;\n rrd_uops_0_REG_br_mask <= _rrd_decode_unit_io_rrd_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n rrd_uops_0_REG_br_tag <= _rrd_decode_unit_io_rrd_uop_br_tag;\n rrd_uops_0_REG_ftq_idx <= _rrd_decode_unit_io_rrd_uop_ftq_idx;\n rrd_uops_0_REG_edge_inst <= _rrd_decode_unit_io_rrd_uop_edge_inst;\n rrd_uops_0_REG_pc_lob <= _rrd_decode_unit_io_rrd_uop_pc_lob;\n rrd_uops_0_REG_taken <= _rrd_decode_unit_io_rrd_uop_taken;\n rrd_uops_0_REG_imm_packed <= _rrd_decode_unit_io_rrd_uop_imm_packed;\n rrd_uops_0_REG_csr_addr <= _rrd_decode_unit_io_rrd_uop_csr_addr;\n rrd_uops_0_REG_rob_idx <= _rrd_decode_unit_io_rrd_uop_rob_idx;\n rrd_uops_0_REG_ldq_idx <= _rrd_decode_unit_io_rrd_uop_ldq_idx;\n rrd_uops_0_REG_stq_idx <= _rrd_decode_unit_io_rrd_uop_stq_idx;\n rrd_uops_0_REG_rxq_idx <= _rrd_decode_unit_io_rrd_uop_rxq_idx;\n rrd_uops_0_REG_pdst <= _rrd_decode_unit_io_rrd_uop_pdst;\n rrd_uops_0_REG_prs1 <= _rrd_decode_unit_io_rrd_uop_prs1;\n rrd_uops_0_REG_prs2 <= _rrd_decode_unit_io_rrd_uop_prs2;\n rrd_uops_0_REG_prs3 <= _rrd_decode_unit_io_rrd_uop_prs3;\n rrd_uops_0_REG_ppred <= _rrd_decode_unit_io_rrd_uop_ppred;\n rrd_uops_0_REG_prs1_busy <= _rrd_decode_unit_io_rrd_uop_prs1_busy;\n rrd_uops_0_REG_prs2_busy <= _rrd_decode_unit_io_rrd_uop_prs2_busy;\n rrd_uops_0_REG_prs3_busy <= _rrd_decode_unit_io_rrd_uop_prs3_busy;\n rrd_uops_0_REG_ppred_busy <= _rrd_decode_unit_io_rrd_uop_ppred_busy;\n rrd_uops_0_REG_stale_pdst <= _rrd_decode_unit_io_rrd_uop_stale_pdst;\n rrd_uops_0_REG_exception <= _rrd_decode_unit_io_rrd_uop_exception;\n rrd_uops_0_REG_exc_cause <= _rrd_decode_unit_io_rrd_uop_exc_cause;\n rrd_uops_0_REG_bypassable <= _rrd_decode_unit_io_rrd_uop_bypassable;\n rrd_uops_0_REG_mem_cmd <= _rrd_decode_unit_io_rrd_uop_mem_cmd;\n rrd_uops_0_REG_mem_size <= _rrd_decode_unit_io_rrd_uop_mem_size;\n rrd_uops_0_REG_mem_signed <= _rrd_decode_unit_io_rrd_uop_mem_signed;\n rrd_uops_0_REG_is_fence <= _rrd_decode_unit_io_rrd_uop_is_fence;\n rrd_uops_0_REG_is_fencei <= _rrd_decode_unit_io_rrd_uop_is_fencei;\n rrd_uops_0_REG_is_amo <= _rrd_decode_unit_io_rrd_uop_is_amo;\n rrd_uops_0_REG_uses_ldq <= _rrd_decode_unit_io_rrd_uop_uses_ldq;\n rrd_uops_0_REG_uses_stq <= _rrd_decode_unit_io_rrd_uop_uses_stq;\n rrd_uops_0_REG_is_sys_pc2epc <= _rrd_decode_unit_io_rrd_uop_is_sys_pc2epc;\n rrd_uops_0_REG_is_unique <= _rrd_decode_unit_io_rrd_uop_is_unique;\n rrd_uops_0_REG_flush_on_commit <= _rrd_decode_unit_io_rrd_uop_flush_on_commit;\n rrd_uops_0_REG_ldst_is_rs1 <= _rrd_decode_unit_io_rrd_uop_ldst_is_rs1;\n rrd_uops_0_REG_ldst <= _rrd_decode_unit_io_rrd_uop_ldst;\n rrd_uops_0_REG_lrs1 <= _rrd_decode_unit_io_rrd_uop_lrs1;\n rrd_uops_0_REG_lrs2 <= _rrd_decode_unit_io_rrd_uop_lrs2;\n rrd_uops_0_REG_lrs3 <= _rrd_decode_unit_io_rrd_uop_lrs3;\n rrd_uops_0_REG_ldst_val <= _rrd_decode_unit_io_rrd_uop_ldst_val;\n rrd_uops_0_REG_dst_rtype <= _rrd_decode_unit_io_rrd_uop_dst_rtype;\n rrd_uops_0_REG_lrs1_rtype <= _rrd_decode_unit_io_rrd_uop_lrs1_rtype;\n rrd_uops_0_REG_lrs2_rtype <= _rrd_decode_unit_io_rrd_uop_lrs2_rtype;\n rrd_uops_0_REG_frs3_en <= _rrd_decode_unit_io_rrd_uop_frs3_en;\n rrd_uops_0_REG_fp_val <= _rrd_decode_unit_io_rrd_uop_fp_val;\n rrd_uops_0_REG_fp_single <= _rrd_decode_unit_io_rrd_uop_fp_single;\n rrd_uops_0_REG_xcpt_pf_if <= _rrd_decode_unit_io_rrd_uop_xcpt_pf_if;\n rrd_uops_0_REG_xcpt_ae_if <= _rrd_decode_unit_io_rrd_uop_xcpt_ae_if;\n rrd_uops_0_REG_xcpt_ma_if <= _rrd_decode_unit_io_rrd_uop_xcpt_ma_if;\n rrd_uops_0_REG_bp_debug_if <= _rrd_decode_unit_io_rrd_uop_bp_debug_if;\n rrd_uops_0_REG_bp_xcpt_if <= _rrd_decode_unit_io_rrd_uop_bp_xcpt_if;\n rrd_uops_0_REG_debug_fsrc <= _rrd_decode_unit_io_rrd_uop_debug_fsrc;\n rrd_uops_0_REG_debug_tsrc <= _rrd_decode_unit_io_rrd_uop_debug_tsrc;\n rrd_rs1_data_0_REG <= io_iss_uops_0_prs1 == 6'h0;\n rrd_rs2_data_0_REG <= io_iss_uops_0_prs2 == 6'h0;\n rrd_rs3_data_0_REG <= io_iss_uops_0_prs3 == 6'h0;\n end\n RegisterReadDecode rrd_decode_unit (\n .io_iss_valid (io_iss_valids_0),\n .io_iss_uop_uopc (io_iss_uops_0_uopc),\n .io_iss_uop_inst (io_iss_uops_0_inst),\n .io_iss_uop_debug_inst (io_iss_uops_0_debug_inst),\n .io_iss_uop_is_rvc (io_iss_uops_0_is_rvc),\n .io_iss_uop_debug_pc (io_iss_uops_0_debug_pc),\n .io_iss_uop_iq_type (io_iss_uops_0_iq_type),\n .io_iss_uop_fu_code (io_iss_uops_0_fu_code),\n .io_iss_uop_iw_state (io_iss_uops_0_iw_state),\n .io_iss_uop_is_br (io_iss_uops_0_is_br),\n .io_iss_uop_is_jalr (io_iss_uops_0_is_jalr),\n .io_iss_uop_is_jal (io_iss_uops_0_is_jal),\n .io_iss_uop_is_sfb (io_iss_uops_0_is_sfb),\n .io_iss_uop_br_mask (io_iss_uops_0_br_mask),\n .io_iss_uop_br_tag (io_iss_uops_0_br_tag),\n .io_iss_uop_ftq_idx (io_iss_uops_0_ftq_idx),\n .io_iss_uop_edge_inst (io_iss_uops_0_edge_inst),\n .io_iss_uop_pc_lob (io_iss_uops_0_pc_lob),\n .io_iss_uop_taken (io_iss_uops_0_taken),\n .io_iss_uop_imm_packed (io_iss_uops_0_imm_packed),\n .io_iss_uop_csr_addr (io_iss_uops_0_csr_addr),\n .io_iss_uop_rob_idx (io_iss_uops_0_rob_idx),\n .io_iss_uop_ldq_idx (io_iss_uops_0_ldq_idx),\n .io_iss_uop_stq_idx (io_iss_uops_0_stq_idx),\n .io_iss_uop_rxq_idx (io_iss_uops_0_rxq_idx),\n .io_iss_uop_pdst (io_iss_uops_0_pdst),\n .io_iss_uop_prs1 (io_iss_uops_0_prs1),\n .io_iss_uop_prs2 (io_iss_uops_0_prs2),\n .io_iss_uop_prs3 (io_iss_uops_0_prs3),\n .io_iss_uop_ppred (io_iss_uops_0_ppred),\n .io_iss_uop_prs1_busy (io_iss_uops_0_prs1_busy),\n .io_iss_uop_prs2_busy (io_iss_uops_0_prs2_busy),\n .io_iss_uop_prs3_busy (io_iss_uops_0_prs3_busy),\n .io_iss_uop_ppred_busy (io_iss_uops_0_ppred_busy),\n .io_iss_uop_stale_pdst (io_iss_uops_0_stale_pdst),\n .io_iss_uop_exception (io_iss_uops_0_exception),\n .io_iss_uop_exc_cause (io_iss_uops_0_exc_cause),\n .io_iss_uop_bypassable (io_iss_uops_0_bypassable),\n .io_iss_uop_mem_cmd (io_iss_uops_0_mem_cmd),\n .io_iss_uop_mem_size (io_iss_uops_0_mem_size),\n .io_iss_uop_mem_signed (io_iss_uops_0_mem_signed),\n .io_iss_uop_is_fence (io_iss_uops_0_is_fence),\n .io_iss_uop_is_fencei (io_iss_uops_0_is_fencei),\n .io_iss_uop_is_amo (io_iss_uops_0_is_amo),\n .io_iss_uop_uses_ldq (io_iss_uops_0_uses_ldq),\n .io_iss_uop_uses_stq (io_iss_uops_0_uses_stq),\n .io_iss_uop_is_sys_pc2epc (io_iss_uops_0_is_sys_pc2epc),\n .io_iss_uop_is_unique (io_iss_uops_0_is_unique),\n .io_iss_uop_flush_on_commit (io_iss_uops_0_flush_on_commit),\n .io_iss_uop_ldst_is_rs1 (io_iss_uops_0_ldst_is_rs1),\n .io_iss_uop_ldst (io_iss_uops_0_ldst),\n .io_iss_uop_lrs1 (io_iss_uops_0_lrs1),\n .io_iss_uop_lrs2 (io_iss_uops_0_lrs2),\n .io_iss_uop_lrs3 (io_iss_uops_0_lrs3),\n .io_iss_uop_ldst_val (io_iss_uops_0_ldst_val),\n .io_iss_uop_dst_rtype (io_iss_uops_0_dst_rtype),\n .io_iss_uop_lrs1_rtype (io_iss_uops_0_lrs1_rtype),\n .io_iss_uop_lrs2_rtype (io_iss_uops_0_lrs2_rtype),\n .io_iss_uop_frs3_en (io_iss_uops_0_frs3_en),\n .io_iss_uop_fp_val (io_iss_uops_0_fp_val),\n .io_iss_uop_fp_single (io_iss_uops_0_fp_single),\n .io_iss_uop_xcpt_pf_if (io_iss_uops_0_xcpt_pf_if),\n .io_iss_uop_xcpt_ae_if (io_iss_uops_0_xcpt_ae_if),\n .io_iss_uop_xcpt_ma_if (io_iss_uops_0_xcpt_ma_if),\n .io_iss_uop_bp_debug_if (io_iss_uops_0_bp_debug_if),\n .io_iss_uop_bp_xcpt_if (io_iss_uops_0_bp_xcpt_if),\n .io_iss_uop_debug_fsrc (io_iss_uops_0_debug_fsrc),\n .io_iss_uop_debug_tsrc (io_iss_uops_0_debug_tsrc),\n .io_rrd_valid (_rrd_decode_unit_io_rrd_valid),\n .io_rrd_uop_uopc (_rrd_decode_unit_io_rrd_uop_uopc),\n .io_rrd_uop_inst (_rrd_decode_unit_io_rrd_uop_inst),\n .io_rrd_uop_debug_inst (_rrd_decode_unit_io_rrd_uop_debug_inst),\n .io_rrd_uop_is_rvc (_rrd_decode_unit_io_rrd_uop_is_rvc),\n .io_rrd_uop_debug_pc (_rrd_decode_unit_io_rrd_uop_debug_pc),\n .io_rrd_uop_iq_type (_rrd_decode_unit_io_rrd_uop_iq_type),\n .io_rrd_uop_fu_code (_rrd_decode_unit_io_rrd_uop_fu_code),\n .io_rrd_uop_ctrl_br_type (_rrd_decode_unit_io_rrd_uop_ctrl_br_type),\n .io_rrd_uop_ctrl_op1_sel (_rrd_decode_unit_io_rrd_uop_ctrl_op1_sel),\n .io_rrd_uop_ctrl_op2_sel (_rrd_decode_unit_io_rrd_uop_ctrl_op2_sel),\n .io_rrd_uop_ctrl_imm_sel (_rrd_decode_unit_io_rrd_uop_ctrl_imm_sel),\n .io_rrd_uop_ctrl_op_fcn (_rrd_decode_unit_io_rrd_uop_ctrl_op_fcn),\n .io_rrd_uop_ctrl_fcn_dw (_rrd_decode_unit_io_rrd_uop_ctrl_fcn_dw),\n .io_rrd_uop_ctrl_csr_cmd (_rrd_decode_unit_io_rrd_uop_ctrl_csr_cmd),\n .io_rrd_uop_ctrl_is_load (_rrd_decode_unit_io_rrd_uop_ctrl_is_load),\n .io_rrd_uop_ctrl_is_sta (_rrd_decode_unit_io_rrd_uop_ctrl_is_sta),\n .io_rrd_uop_ctrl_is_std (_rrd_decode_unit_io_rrd_uop_ctrl_is_std),\n .io_rrd_uop_iw_state (_rrd_decode_unit_io_rrd_uop_iw_state),\n .io_rrd_uop_is_br (_rrd_decode_unit_io_rrd_uop_is_br),\n .io_rrd_uop_is_jalr (_rrd_decode_unit_io_rrd_uop_is_jalr),\n .io_rrd_uop_is_jal (_rrd_decode_unit_io_rrd_uop_is_jal),\n .io_rrd_uop_is_sfb (_rrd_decode_unit_io_rrd_uop_is_sfb),\n .io_rrd_uop_br_mask (_rrd_decode_unit_io_rrd_uop_br_mask),\n .io_rrd_uop_br_tag (_rrd_decode_unit_io_rrd_uop_br_tag),\n .io_rrd_uop_ftq_idx (_rrd_decode_unit_io_rrd_uop_ftq_idx),\n .io_rrd_uop_edge_inst (_rrd_decode_unit_io_rrd_uop_edge_inst),\n .io_rrd_uop_pc_lob (_rrd_decode_unit_io_rrd_uop_pc_lob),\n .io_rrd_uop_taken (_rrd_decode_unit_io_rrd_uop_taken),\n .io_rrd_uop_imm_packed (_rrd_decode_unit_io_rrd_uop_imm_packed),\n .io_rrd_uop_csr_addr (_rrd_decode_unit_io_rrd_uop_csr_addr),\n .io_rrd_uop_rob_idx (_rrd_decode_unit_io_rrd_uop_rob_idx),\n .io_rrd_uop_ldq_idx (_rrd_decode_unit_io_rrd_uop_ldq_idx),\n .io_rrd_uop_stq_idx (_rrd_decode_unit_io_rrd_uop_stq_idx),\n .io_rrd_uop_rxq_idx (_rrd_decode_unit_io_rrd_uop_rxq_idx),\n .io_rrd_uop_pdst (_rrd_decode_unit_io_rrd_uop_pdst),\n .io_rrd_uop_prs1 (_rrd_decode_unit_io_rrd_uop_prs1),\n .io_rrd_uop_prs2 (_rrd_decode_unit_io_rrd_uop_prs2),\n .io_rrd_uop_prs3 (_rrd_decode_unit_io_rrd_uop_prs3),\n .io_rrd_uop_ppred (_rrd_decode_unit_io_rrd_uop_ppred),\n .io_rrd_uop_prs1_busy (_rrd_decode_unit_io_rrd_uop_prs1_busy),\n .io_rrd_uop_prs2_busy (_rrd_decode_unit_io_rrd_uop_prs2_busy),\n .io_rrd_uop_prs3_busy (_rrd_decode_unit_io_rrd_uop_prs3_busy),\n .io_rrd_uop_ppred_busy (_rrd_decode_unit_io_rrd_uop_ppred_busy),\n .io_rrd_uop_stale_pdst (_rrd_decode_unit_io_rrd_uop_stale_pdst),\n .io_rrd_uop_exception (_rrd_decode_unit_io_rrd_uop_exception),\n .io_rrd_uop_exc_cause (_rrd_decode_unit_io_rrd_uop_exc_cause),\n .io_rrd_uop_bypassable (_rrd_decode_unit_io_rrd_uop_bypassable),\n .io_rrd_uop_mem_cmd (_rrd_decode_unit_io_rrd_uop_mem_cmd),\n .io_rrd_uop_mem_size (_rrd_decode_unit_io_rrd_uop_mem_size),\n .io_rrd_uop_mem_signed (_rrd_decode_unit_io_rrd_uop_mem_signed),\n .io_rrd_uop_is_fence (_rrd_decode_unit_io_rrd_uop_is_fence),\n .io_rrd_uop_is_fencei (_rrd_decode_unit_io_rrd_uop_is_fencei),\n .io_rrd_uop_is_amo (_rrd_decode_unit_io_rrd_uop_is_amo),\n .io_rrd_uop_uses_ldq (_rrd_decode_unit_io_rrd_uop_uses_ldq),\n .io_rrd_uop_uses_stq (_rrd_decode_unit_io_rrd_uop_uses_stq),\n .io_rrd_uop_is_sys_pc2epc (_rrd_decode_unit_io_rrd_uop_is_sys_pc2epc),\n .io_rrd_uop_is_unique (_rrd_decode_unit_io_rrd_uop_is_unique),\n .io_rrd_uop_flush_on_commit (_rrd_decode_unit_io_rrd_uop_flush_on_commit),\n .io_rrd_uop_ldst_is_rs1 (_rrd_decode_unit_io_rrd_uop_ldst_is_rs1),\n .io_rrd_uop_ldst (_rrd_decode_unit_io_rrd_uop_ldst),\n .io_rrd_uop_lrs1 (_rrd_decode_unit_io_rrd_uop_lrs1),\n .io_rrd_uop_lrs2 (_rrd_decode_unit_io_rrd_uop_lrs2),\n .io_rrd_uop_lrs3 (_rrd_decode_unit_io_rrd_uop_lrs3),\n .io_rrd_uop_ldst_val (_rrd_decode_unit_io_rrd_uop_ldst_val),\n .io_rrd_uop_dst_rtype (_rrd_decode_unit_io_rrd_uop_dst_rtype),\n .io_rrd_uop_lrs1_rtype (_rrd_decode_unit_io_rrd_uop_lrs1_rtype),\n .io_rrd_uop_lrs2_rtype (_rrd_decode_unit_io_rrd_uop_lrs2_rtype),\n .io_rrd_uop_frs3_en (_rrd_decode_unit_io_rrd_uop_frs3_en),\n .io_rrd_uop_fp_val (_rrd_decode_unit_io_rrd_uop_fp_val),\n .io_rrd_uop_fp_single (_rrd_decode_unit_io_rrd_uop_fp_single),\n .io_rrd_uop_xcpt_pf_if (_rrd_decode_unit_io_rrd_uop_xcpt_pf_if),\n .io_rrd_uop_xcpt_ae_if (_rrd_decode_unit_io_rrd_uop_xcpt_ae_if),\n .io_rrd_uop_xcpt_ma_if (_rrd_decode_unit_io_rrd_uop_xcpt_ma_if),\n .io_rrd_uop_bp_debug_if (_rrd_decode_unit_io_rrd_uop_bp_debug_if),\n .io_rrd_uop_bp_xcpt_if (_rrd_decode_unit_io_rrd_uop_bp_xcpt_if),\n .io_rrd_uop_debug_fsrc (_rrd_decode_unit_io_rrd_uop_debug_fsrc),\n .io_rrd_uop_debug_tsrc (_rrd_decode_unit_io_rrd_uop_debug_tsrc)\n );\n assign io_rf_read_ports_0_addr = io_iss_uops_0_prs1;\n assign io_rf_read_ports_1_addr = io_iss_uops_0_prs2;\n assign io_rf_read_ports_2_addr = io_iss_uops_0_prs3;\n assign io_exe_reqs_0_valid = exe_reg_valids_0;\n assign io_exe_reqs_0_bits_uop_uopc = exe_reg_uops_0_uopc;\n assign io_exe_reqs_0_bits_uop_inst = exe_reg_uops_0_inst;\n assign io_exe_reqs_0_bits_uop_debug_inst = exe_reg_uops_0_debug_inst;\n assign io_exe_reqs_0_bits_uop_is_rvc = exe_reg_uops_0_is_rvc;\n assign io_exe_reqs_0_bits_uop_debug_pc = exe_reg_uops_0_debug_pc;\n assign io_exe_reqs_0_bits_uop_iq_type = exe_reg_uops_0_iq_type;\n assign io_exe_reqs_0_bits_uop_fu_code = exe_reg_uops_0_fu_code;\n assign io_exe_reqs_0_bits_uop_ctrl_br_type = exe_reg_uops_0_ctrl_br_type;\n assign io_exe_reqs_0_bits_uop_ctrl_op1_sel = exe_reg_uops_0_ctrl_op1_sel;\n assign io_exe_reqs_0_bits_uop_ctrl_op2_sel = exe_reg_uops_0_ctrl_op2_sel;\n assign io_exe_reqs_0_bits_uop_ctrl_imm_sel = exe_reg_uops_0_ctrl_imm_sel;\n assign io_exe_reqs_0_bits_uop_ctrl_op_fcn = exe_reg_uops_0_ctrl_op_fcn;\n assign io_exe_reqs_0_bits_uop_ctrl_fcn_dw = exe_reg_uops_0_ctrl_fcn_dw;\n assign io_exe_reqs_0_bits_uop_ctrl_csr_cmd = exe_reg_uops_0_ctrl_csr_cmd;\n assign io_exe_reqs_0_bits_uop_ctrl_is_load = exe_reg_uops_0_ctrl_is_load;\n assign io_exe_reqs_0_bits_uop_ctrl_is_sta = exe_reg_uops_0_ctrl_is_sta;\n assign io_exe_reqs_0_bits_uop_ctrl_is_std = exe_reg_uops_0_ctrl_is_std;\n assign io_exe_reqs_0_bits_uop_iw_state = exe_reg_uops_0_iw_state;\n assign io_exe_reqs_0_bits_uop_iw_p1_poisoned = exe_reg_uops_0_iw_p1_poisoned;\n assign io_exe_reqs_0_bits_uop_iw_p2_poisoned = exe_reg_uops_0_iw_p2_poisoned;\n assign io_exe_reqs_0_bits_uop_is_br = exe_reg_uops_0_is_br;\n assign io_exe_reqs_0_bits_uop_is_jalr = exe_reg_uops_0_is_jalr;\n assign io_exe_reqs_0_bits_uop_is_jal = exe_reg_uops_0_is_jal;\n assign io_exe_reqs_0_bits_uop_is_sfb = exe_reg_uops_0_is_sfb;\n assign io_exe_reqs_0_bits_uop_br_mask = exe_reg_uops_0_br_mask;\n assign io_exe_reqs_0_bits_uop_br_tag = exe_reg_uops_0_br_tag;\n assign io_exe_reqs_0_bits_uop_ftq_idx = exe_reg_uops_0_ftq_idx;\n assign io_exe_reqs_0_bits_uop_edge_inst = exe_reg_uops_0_edge_inst;\n assign io_exe_reqs_0_bits_uop_pc_lob = exe_reg_uops_0_pc_lob;\n assign io_exe_reqs_0_bits_uop_taken = exe_reg_uops_0_taken;\n assign io_exe_reqs_0_bits_uop_imm_packed = exe_reg_uops_0_imm_packed;\n assign io_exe_reqs_0_bits_uop_csr_addr = exe_reg_uops_0_csr_addr;\n assign io_exe_reqs_0_bits_uop_rob_idx = exe_reg_uops_0_rob_idx;\n assign io_exe_reqs_0_bits_uop_ldq_idx = exe_reg_uops_0_ldq_idx;\n assign io_exe_reqs_0_bits_uop_stq_idx = exe_reg_uops_0_stq_idx;\n assign io_exe_reqs_0_bits_uop_rxq_idx = exe_reg_uops_0_rxq_idx;\n assign io_exe_reqs_0_bits_uop_pdst = exe_reg_uops_0_pdst;\n assign io_exe_reqs_0_bits_uop_prs1 = exe_reg_uops_0_prs1;\n assign io_exe_reqs_0_bits_uop_prs2 = exe_reg_uops_0_prs2;\n assign io_exe_reqs_0_bits_uop_prs3 = exe_reg_uops_0_prs3;\n assign io_exe_reqs_0_bits_uop_ppred = exe_reg_uops_0_ppred;\n assign io_exe_reqs_0_bits_uop_prs1_busy = exe_reg_uops_0_prs1_busy;\n assign io_exe_reqs_0_bits_uop_prs2_busy = exe_reg_uops_0_prs2_busy;\n assign io_exe_reqs_0_bits_uop_prs3_busy = exe_reg_uops_0_prs3_busy;\n assign io_exe_reqs_0_bits_uop_ppred_busy = exe_reg_uops_0_ppred_busy;\n assign io_exe_reqs_0_bits_uop_stale_pdst = exe_reg_uops_0_stale_pdst;\n assign io_exe_reqs_0_bits_uop_exception = exe_reg_uops_0_exception;\n assign io_exe_reqs_0_bits_uop_exc_cause = exe_reg_uops_0_exc_cause;\n assign io_exe_reqs_0_bits_uop_bypassable = exe_reg_uops_0_bypassable;\n assign io_exe_reqs_0_bits_uop_mem_cmd = exe_reg_uops_0_mem_cmd;\n assign io_exe_reqs_0_bits_uop_mem_size = exe_reg_uops_0_mem_size;\n assign io_exe_reqs_0_bits_uop_mem_signed = exe_reg_uops_0_mem_signed;\n assign io_exe_reqs_0_bits_uop_is_fence = exe_reg_uops_0_is_fence;\n assign io_exe_reqs_0_bits_uop_is_fencei = exe_reg_uops_0_is_fencei;\n assign io_exe_reqs_0_bits_uop_is_amo = exe_reg_uops_0_is_amo;\n assign io_exe_reqs_0_bits_uop_uses_ldq = exe_reg_uops_0_uses_ldq;\n assign io_exe_reqs_0_bits_uop_uses_stq = exe_reg_uops_0_uses_stq;\n assign io_exe_reqs_0_bits_uop_is_sys_pc2epc = exe_reg_uops_0_is_sys_pc2epc;\n assign io_exe_reqs_0_bits_uop_is_unique = exe_reg_uops_0_is_unique;\n assign io_exe_reqs_0_bits_uop_flush_on_commit = exe_reg_uops_0_flush_on_commit;\n assign io_exe_reqs_0_bits_uop_ldst_is_rs1 = exe_reg_uops_0_ldst_is_rs1;\n assign io_exe_reqs_0_bits_uop_ldst = exe_reg_uops_0_ldst;\n assign io_exe_reqs_0_bits_uop_lrs1 = exe_reg_uops_0_lrs1;\n assign io_exe_reqs_0_bits_uop_lrs2 = exe_reg_uops_0_lrs2;\n assign io_exe_reqs_0_bits_uop_lrs3 = exe_reg_uops_0_lrs3;\n assign io_exe_reqs_0_bits_uop_ldst_val = exe_reg_uops_0_ldst_val;\n assign io_exe_reqs_0_bits_uop_dst_rtype = exe_reg_uops_0_dst_rtype;\n assign io_exe_reqs_0_bits_uop_lrs1_rtype = exe_reg_uops_0_lrs1_rtype;\n assign io_exe_reqs_0_bits_uop_lrs2_rtype = exe_reg_uops_0_lrs2_rtype;\n assign io_exe_reqs_0_bits_uop_frs3_en = exe_reg_uops_0_frs3_en;\n assign io_exe_reqs_0_bits_uop_fp_val = exe_reg_uops_0_fp_val;\n assign io_exe_reqs_0_bits_uop_fp_single = exe_reg_uops_0_fp_single;\n assign io_exe_reqs_0_bits_uop_xcpt_pf_if = exe_reg_uops_0_xcpt_pf_if;\n assign io_exe_reqs_0_bits_uop_xcpt_ae_if = exe_reg_uops_0_xcpt_ae_if;\n assign io_exe_reqs_0_bits_uop_xcpt_ma_if = exe_reg_uops_0_xcpt_ma_if;\n assign io_exe_reqs_0_bits_uop_bp_debug_if = exe_reg_uops_0_bp_debug_if;\n assign io_exe_reqs_0_bits_uop_bp_xcpt_if = exe_reg_uops_0_bp_xcpt_if;\n assign io_exe_reqs_0_bits_uop_debug_fsrc = exe_reg_uops_0_debug_fsrc;\n assign io_exe_reqs_0_bits_uop_debug_tsrc = exe_reg_uops_0_debug_tsrc;\n assign io_exe_reqs_0_bits_rs1_data = exe_reg_rs1_data_0;\n assign io_exe_reqs_0_bits_rs2_data = exe_reg_rs2_data_0;\n assign io_exe_reqs_0_bits_rs3_data = exe_reg_rs3_data_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2012 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// RISCV Processor Datapath: Rename Logic\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n//\n// Supports 1-cycle and 2-cycle latencies. (aka, passthrough versus registers between ren1 and ren2).\n// - ren1: read the map tables and allocate a new physical register from the freelist.\n// - ren2: read the busy table for the physical operands.\n//\n// Ren1 data is provided as an output to be fed directly into the ROB.\n\npackage boom.v3.exu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\n\nimport boom.v3.common._\nimport boom.v3.util._\n\n/**\n * IO bundle to interface with the Register Rename logic\n *\n * @param plWidth pipeline width\n * @param numIntPregs number of int physical registers\n * @param numFpPregs number of FP physical registers\n * @param numWbPorts number of int writeback ports\n * @param numWbPorts number of FP writeback ports\n */\nclass RenameStageIO(\n val plWidth: Int,\n val numPhysRegs: Int,\n val numWbPorts: Int)\n (implicit p: Parameters) extends BoomBundle\n\n\n/**\n * IO bundle to debug the rename stage\n */\nclass DebugRenameStageIO(val numPhysRegs: Int)(implicit p: Parameters) extends BoomBundle\n{\n val freelist = Bits(numPhysRegs.W)\n val isprlist = Bits(numPhysRegs.W)\n val busytable = UInt(numPhysRegs.W)\n}\n\nabstract class AbstractRenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int)\n (implicit p: Parameters) extends BoomModule\n{\n val io = IO(new Bundle {\n val ren_stalls = Output(Vec(plWidth, Bool()))\n\n val kill = Input(Bool())\n\n val dec_fire = Input(Vec(plWidth, Bool())) // will commit state updates\n val dec_uops = Input(Vec(plWidth, new MicroOp()))\n\n // physical specifiers available AND busy/ready status available.\n val ren2_mask = Vec(plWidth, Output(Bool())) // mask of valid instructions\n val ren2_uops = Vec(plWidth, Output(new MicroOp()))\n\n // branch resolution (execute)\n val brupdate = Input(new BrUpdateInfo())\n\n val dis_fire = Input(Vec(coreWidth, Bool()))\n val dis_ready = Input(Bool())\n\n // wakeup ports\n val wakeups = Flipped(Vec(numWbPorts, Valid(new ExeUnitResp(xLen))))\n\n // commit stage\n val com_valids = Input(Vec(plWidth, Bool()))\n val com_uops = Input(Vec(plWidth, new MicroOp()))\n val rbk_valids = Input(Vec(plWidth, Bool()))\n val rollback = Input(Bool())\n\n val debug_rob_empty = Input(Bool())\n val debug = Output(new DebugRenameStageIO(numPhysRegs))\n })\n\n io.ren_stalls.foreach(_ := false.B)\n io.debug := DontCare\n\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp\n\n //-------------------------------------------------------------\n // Pipeline State & Wires\n\n // Stage 1\n val ren1_fire = Wire(Vec(plWidth, Bool()))\n val ren1_uops = Wire(Vec(plWidth, new MicroOp))\n\n\n // Stage 2\n val ren2_fire = io.dis_fire\n val ren2_ready = io.dis_ready\n val ren2_valids = Wire(Vec(plWidth, Bool()))\n val ren2_uops = Wire(Vec(plWidth, new MicroOp))\n val ren2_alloc_reqs = Wire(Vec(plWidth, Bool()))\n\n\n //-------------------------------------------------------------\n // pipeline registers\n\n for (w <- 0 until plWidth) {\n ren1_fire(w) := io.dec_fire(w)\n ren1_uops(w) := io.dec_uops(w)\n }\n\n for (w <- 0 until plWidth) {\n val r_valid = RegInit(false.B)\n val r_uop = Reg(new MicroOp)\n val next_uop = Wire(new MicroOp)\n\n next_uop := r_uop\n\n when (io.kill) {\n r_valid := false.B\n } .elsewhen (ren2_ready) {\n r_valid := ren1_fire(w)\n next_uop := ren1_uops(w)\n } .otherwise {\n r_valid := r_valid && !ren2_fire(w) // clear bit if uop gets dispatched\n next_uop := r_uop\n }\n\n r_uop := GetNewUopAndBrMask(BypassAllocations(next_uop, ren2_uops, ren2_alloc_reqs), io.brupdate)\n\n ren2_valids(w) := r_valid\n ren2_uops(w) := r_uop\n }\n\n //-------------------------------------------------------------\n // Outputs\n\n io.ren2_mask := ren2_valids\n\n\n}\n\n\n/**\n * Rename stage that connets the map table, free list, and busy table.\n * Can be used in both the FP pipeline and the normal execute pipeline.\n *\n * @param plWidth pipeline width\n * @param numWbPorts number of int writeback ports\n * @param numWbPorts number of FP writeback ports\n */\nclass RenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int,\n float: Boolean)\n(implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)\n{\n val pregSz = log2Ceil(numPhysRegs)\n val rtype = if (float) RT_FLT else RT_FIX\n\n //-------------------------------------------------------------\n // Helper Functions\n\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {\n val bypassed_uop = Wire(new MicroOp)\n bypassed_uop := uop\n\n val bypass_hits_rs1 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs1 }\n val bypass_hits_rs2 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs2 }\n val bypass_hits_rs3 = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.lrs3 }\n val bypass_hits_dst = (older_uops zip alloc_reqs) map { case (r,a) => a && r.ldst === uop.ldst }\n\n val bypass_sel_rs1 = PriorityEncoderOH(bypass_hits_rs1.reverse).reverse\n val bypass_sel_rs2 = PriorityEncoderOH(bypass_hits_rs2.reverse).reverse\n val bypass_sel_rs3 = PriorityEncoderOH(bypass_hits_rs3.reverse).reverse\n val bypass_sel_dst = PriorityEncoderOH(bypass_hits_dst.reverse).reverse\n\n val do_bypass_rs1 = bypass_hits_rs1.reduce(_||_)\n val do_bypass_rs2 = bypass_hits_rs2.reduce(_||_)\n val do_bypass_rs3 = bypass_hits_rs3.reduce(_||_)\n val do_bypass_dst = bypass_hits_dst.reduce(_||_)\n\n val bypass_pdsts = older_uops.map(_.pdst)\n\n when (do_bypass_rs1) { bypassed_uop.prs1 := Mux1H(bypass_sel_rs1, bypass_pdsts) }\n when (do_bypass_rs2) { bypassed_uop.prs2 := Mux1H(bypass_sel_rs2, bypass_pdsts) }\n when (do_bypass_rs3) { bypassed_uop.prs3 := Mux1H(bypass_sel_rs3, bypass_pdsts) }\n when (do_bypass_dst) { bypassed_uop.stale_pdst := Mux1H(bypass_sel_dst, bypass_pdsts) }\n\n bypassed_uop.prs1_busy := uop.prs1_busy || do_bypass_rs1\n bypassed_uop.prs2_busy := uop.prs2_busy || do_bypass_rs2\n bypassed_uop.prs3_busy := uop.prs3_busy || do_bypass_rs3\n\n if (!float) {\n bypassed_uop.prs3 := DontCare\n bypassed_uop.prs3_busy := false.B\n }\n\n bypassed_uop\n }\n\n //-------------------------------------------------------------\n // Rename Structures\n\n val maptable = Module(new RenameMapTable(\n plWidth,\n 32,\n numPhysRegs,\n false,\n float))\n val freelist = Module(new RenameFreeList(\n plWidth,\n numPhysRegs,\n if (float) 32 else 31))\n val busytable = Module(new RenameBusyTable(\n plWidth,\n numPhysRegs,\n numWbPorts,\n false,\n float))\n\n\n\n val ren2_br_tags = Wire(Vec(plWidth, Valid(UInt(brTagSz.W))))\n\n // Commit/Rollback\n val com_valids = Wire(Vec(plWidth, Bool()))\n val rbk_valids = Wire(Vec(plWidth, Bool()))\n\n for (w <- 0 until plWidth) {\n ren2_alloc_reqs(w) := ren2_uops(w).ldst_val && ren2_uops(w).dst_rtype === rtype && ren2_fire(w)\n ren2_br_tags(w).valid := ren2_fire(w) && ren2_uops(w).allocate_brtag\n\n com_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.com_valids(w)\n rbk_valids(w) := io.com_uops(w).ldst_val && io.com_uops(w).dst_rtype === rtype && io.rbk_valids(w)\n ren2_br_tags(w).bits := ren2_uops(w).br_tag\n }\n\n //-------------------------------------------------------------\n // Rename Table\n\n // Maptable inputs.\n val map_reqs = Wire(Vec(plWidth, new MapReq(lregSz)))\n val remap_reqs = Wire(Vec(plWidth, new RemapReq(lregSz, pregSz)))\n\n // Generate maptable requests.\n for ((((ren1,ren2),com),w) <- (ren1_uops zip ren2_uops zip io.com_uops.reverse).zipWithIndex) {\n map_reqs(w).lrs1 := ren1.lrs1\n map_reqs(w).lrs2 := ren1.lrs2\n map_reqs(w).lrs3 := ren1.lrs3\n map_reqs(w).ldst := ren1.ldst\n\n remap_reqs(w).ldst := Mux(io.rollback, com.ldst , ren2.ldst)\n remap_reqs(w).pdst := Mux(io.rollback, com.stale_pdst, ren2.pdst)\n }\n ren2_alloc_reqs zip rbk_valids.reverse zip remap_reqs map {\n case ((a,r),rr) => rr.valid := a || r}\n\n // Hook up inputs.\n maptable.io.map_reqs := map_reqs\n maptable.io.remap_reqs := remap_reqs\n maptable.io.ren_br_tags := ren2_br_tags\n maptable.io.brupdate := io.brupdate\n maptable.io.rollback := io.rollback\n\n // Maptable outputs.\n for ((uop, w) <- ren1_uops.zipWithIndex) {\n val mappings = maptable.io.map_resps(w)\n\n uop.prs1 := mappings.prs1\n uop.prs2 := mappings.prs2\n uop.prs3 := mappings.prs3 // only FP has 3rd operand\n uop.stale_pdst := mappings.stale_pdst\n }\n\n\n\n //-------------------------------------------------------------\n // Free List\n\n // Freelist inputs.\n freelist.io.reqs := ren2_alloc_reqs\n freelist.io.dealloc_pregs zip com_valids zip rbk_valids map\n {case ((d,c),r) => d.valid := c || r}\n freelist.io.dealloc_pregs zip io.com_uops map\n {case (d,c) => d.bits := Mux(io.rollback, c.pdst, c.stale_pdst)}\n freelist.io.ren_br_tags := ren2_br_tags\n freelist.io.brupdate := io.brupdate\n freelist.io.debug.pipeline_empty := io.debug_rob_empty\n\n assert (ren2_alloc_reqs zip freelist.io.alloc_pregs map {case (r,p) => !r || p.bits =/= 0.U} reduce (_&&_),\n \"[rename-stage] A uop is trying to allocate the zero physical register.\")\n\n // Freelist outputs.\n for ((uop, w) <- ren2_uops.zipWithIndex) {\n val preg = freelist.io.alloc_pregs(w).bits\n uop.pdst := Mux(uop.ldst =/= 0.U || float.B, preg, 0.U)\n }\n\n //-------------------------------------------------------------\n // Busy Table\n\n busytable.io.ren_uops := ren2_uops // expects pdst to be set up.\n busytable.io.rebusy_reqs := ren2_alloc_reqs\n busytable.io.wb_valids := io.wakeups.map(_.valid)\n busytable.io.wb_pdsts := io.wakeups.map(_.bits.uop.pdst)\n\n assert (!(io.wakeups.map(x => x.valid && x.bits.uop.dst_rtype =/= rtype).reduce(_||_)),\n \"[rename] Wakeup has wrong rtype.\")\n\n for ((uop, w) <- ren2_uops.zipWithIndex) {\n val busy = busytable.io.busy_resps(w)\n\n uop.prs1_busy := uop.lrs1_rtype === rtype && busy.prs1_busy\n uop.prs2_busy := uop.lrs2_rtype === rtype && busy.prs2_busy\n uop.prs3_busy := uop.frs3_en && busy.prs3_busy\n\n val valid = ren2_valids(w)\n assert (!(valid && busy.prs1_busy && rtype === RT_FIX && uop.lrs1 === 0.U), \"[rename] x0 is busy??\")\n assert (!(valid && busy.prs2_busy && rtype === RT_FIX && uop.lrs2 === 0.U), \"[rename] x0 is busy??\")\n }\n\n //-------------------------------------------------------------\n // Outputs\n\n for (w <- 0 until plWidth) {\n val can_allocate = freelist.io.alloc_pregs(w).valid\n\n // Push back against Decode stage if Rename1 can't proceed.\n io.ren_stalls(w) := (ren2_uops(w).dst_rtype === rtype) && !can_allocate\n\n val bypassed_uop = Wire(new MicroOp)\n if (w > 0) bypassed_uop := BypassAllocations(ren2_uops(w), ren2_uops.slice(0,w), ren2_alloc_reqs.slice(0,w))\n else bypassed_uop := ren2_uops(w)\n\n io.ren2_uops(w) := GetNewUopAndBrMask(bypassed_uop, io.brupdate)\n }\n\n //-------------------------------------------------------------\n // Debug signals\n\n io.debug.freelist := freelist.io.debug.freelist\n io.debug.isprlist := freelist.io.debug.isprlist\n io.debug.busytable := busytable.io.debug.busytable\n}\n\nclass PredRenameStage(\n plWidth: Int,\n numPhysRegs: Int,\n numWbPorts: Int)\n (implicit p: Parameters) extends AbstractRenameStage(plWidth, numPhysRegs, numWbPorts)(p)\n{\n def BypassAllocations(uop: MicroOp, older_uops: Seq[MicroOp], alloc_reqs: Seq[Bool]): MicroOp = {\n uop\n }\n\n ren2_alloc_reqs := DontCare\n\n val busy_table = RegInit(VecInit(0.U(ftqSz.W).asBools))\n val to_busy = WireInit(VecInit(0.U(ftqSz.W).asBools))\n val unbusy = WireInit(VecInit(0.U(ftqSz.W).asBools))\n\n val current_ftq_idx = Reg(UInt(log2Ceil(ftqSz).W))\n var next_ftq_idx = current_ftq_idx\n\n for (w <- 0 until plWidth) {\n io.ren2_uops(w) := ren2_uops(w)\n\n val is_sfb_br = ren2_uops(w).is_sfb_br && ren2_fire(w)\n val is_sfb_shadow = ren2_uops(w).is_sfb_shadow && ren2_fire(w)\n\n val ftq_idx = ren2_uops(w).ftq_idx\n when (is_sfb_br) {\n io.ren2_uops(w).pdst := ftq_idx\n to_busy(ftq_idx) := true.B\n }\n next_ftq_idx = Mux(is_sfb_br, ftq_idx, next_ftq_idx)\n\n when (is_sfb_shadow) {\n io.ren2_uops(w).ppred := next_ftq_idx\n io.ren2_uops(w).ppred_busy := (busy_table(next_ftq_idx) || to_busy(next_ftq_idx)) && !unbusy(next_ftq_idx)\n }\n }\n\n for (w <- 0 until numWbPorts) {\n when (io.wakeups(w).valid) {\n unbusy(io.wakeups(w).bits.uop.pdst) := true.B\n }\n }\n\n current_ftq_idx := next_ftq_idx\n\n busy_table := ((busy_table.asUInt | to_busy.asUInt) & ~unbusy.asUInt).asBools\n}", + "response": "module RenameStage(\n input clock,\n input reset,\n output io_ren_stalls_0,\n input io_kill,\n input io_dec_fire_0,\n input [6:0] io_dec_uops_0_uopc,\n input [31:0] io_dec_uops_0_inst,\n input [31:0] io_dec_uops_0_debug_inst,\n input io_dec_uops_0_is_rvc,\n input [39:0] io_dec_uops_0_debug_pc,\n input [2:0] io_dec_uops_0_iq_type,\n input [9:0] io_dec_uops_0_fu_code,\n input io_dec_uops_0_is_br,\n input io_dec_uops_0_is_jalr,\n input io_dec_uops_0_is_jal,\n input io_dec_uops_0_is_sfb,\n input [7:0] io_dec_uops_0_br_mask,\n input [2:0] io_dec_uops_0_br_tag,\n input [3:0] io_dec_uops_0_ftq_idx,\n input io_dec_uops_0_edge_inst,\n input [5:0] io_dec_uops_0_pc_lob,\n input io_dec_uops_0_taken,\n input [19:0] io_dec_uops_0_imm_packed,\n input io_dec_uops_0_exception,\n input [63:0] io_dec_uops_0_exc_cause,\n input io_dec_uops_0_bypassable,\n input [4:0] io_dec_uops_0_mem_cmd,\n input [1:0] io_dec_uops_0_mem_size,\n input io_dec_uops_0_mem_signed,\n input io_dec_uops_0_is_fence,\n input io_dec_uops_0_is_fencei,\n input io_dec_uops_0_is_amo,\n input io_dec_uops_0_uses_ldq,\n input io_dec_uops_0_uses_stq,\n input io_dec_uops_0_is_sys_pc2epc,\n input io_dec_uops_0_is_unique,\n input io_dec_uops_0_flush_on_commit,\n input [5:0] io_dec_uops_0_ldst,\n input [5:0] io_dec_uops_0_lrs1,\n input [5:0] io_dec_uops_0_lrs2,\n input [5:0] io_dec_uops_0_lrs3,\n input io_dec_uops_0_ldst_val,\n input [1:0] io_dec_uops_0_dst_rtype,\n input [1:0] io_dec_uops_0_lrs1_rtype,\n input [1:0] io_dec_uops_0_lrs2_rtype,\n input io_dec_uops_0_frs3_en,\n input io_dec_uops_0_fp_val,\n input io_dec_uops_0_fp_single,\n input io_dec_uops_0_xcpt_pf_if,\n input io_dec_uops_0_xcpt_ae_if,\n input io_dec_uops_0_bp_debug_if,\n input io_dec_uops_0_bp_xcpt_if,\n input [1:0] io_dec_uops_0_debug_fsrc,\n output io_ren2_mask_0,\n output [6:0] io_ren2_uops_0_uopc,\n output [31:0] io_ren2_uops_0_inst,\n output [31:0] io_ren2_uops_0_debug_inst,\n output io_ren2_uops_0_is_rvc,\n output [39:0] io_ren2_uops_0_debug_pc,\n output [2:0] io_ren2_uops_0_iq_type,\n output [9:0] io_ren2_uops_0_fu_code,\n output [3:0] io_ren2_uops_0_ctrl_br_type,\n output [1:0] io_ren2_uops_0_ctrl_op1_sel,\n output [2:0] io_ren2_uops_0_ctrl_op2_sel,\n output [2:0] io_ren2_uops_0_ctrl_imm_sel,\n output [4:0] io_ren2_uops_0_ctrl_op_fcn,\n output io_ren2_uops_0_ctrl_fcn_dw,\n output [2:0] io_ren2_uops_0_ctrl_csr_cmd,\n output io_ren2_uops_0_ctrl_is_load,\n output io_ren2_uops_0_ctrl_is_sta,\n output io_ren2_uops_0_ctrl_is_std,\n output [1:0] io_ren2_uops_0_iw_state,\n output io_ren2_uops_0_iw_p1_poisoned,\n output io_ren2_uops_0_iw_p2_poisoned,\n output io_ren2_uops_0_is_br,\n output io_ren2_uops_0_is_jalr,\n output io_ren2_uops_0_is_jal,\n output io_ren2_uops_0_is_sfb,\n output [7:0] io_ren2_uops_0_br_mask,\n output [2:0] io_ren2_uops_0_br_tag,\n output [3:0] io_ren2_uops_0_ftq_idx,\n output io_ren2_uops_0_edge_inst,\n output [5:0] io_ren2_uops_0_pc_lob,\n output io_ren2_uops_0_taken,\n output [19:0] io_ren2_uops_0_imm_packed,\n output [11:0] io_ren2_uops_0_csr_addr,\n output [1:0] io_ren2_uops_0_rxq_idx,\n output [5:0] io_ren2_uops_0_pdst,\n output [5:0] io_ren2_uops_0_prs1,\n output [5:0] io_ren2_uops_0_prs2,\n output io_ren2_uops_0_prs1_busy,\n output io_ren2_uops_0_prs2_busy,\n output [5:0] io_ren2_uops_0_stale_pdst,\n output io_ren2_uops_0_exception,\n output [63:0] io_ren2_uops_0_exc_cause,\n output io_ren2_uops_0_bypassable,\n output [4:0] io_ren2_uops_0_mem_cmd,\n output [1:0] io_ren2_uops_0_mem_size,\n output io_ren2_uops_0_mem_signed,\n output io_ren2_uops_0_is_fence,\n output io_ren2_uops_0_is_fencei,\n output io_ren2_uops_0_is_amo,\n output io_ren2_uops_0_uses_ldq,\n output io_ren2_uops_0_uses_stq,\n output io_ren2_uops_0_is_sys_pc2epc,\n output io_ren2_uops_0_is_unique,\n output io_ren2_uops_0_flush_on_commit,\n output io_ren2_uops_0_ldst_is_rs1,\n output [5:0] io_ren2_uops_0_ldst,\n output [5:0] io_ren2_uops_0_lrs1,\n output [5:0] io_ren2_uops_0_lrs2,\n output [5:0] io_ren2_uops_0_lrs3,\n output io_ren2_uops_0_ldst_val,\n output [1:0] io_ren2_uops_0_dst_rtype,\n output [1:0] io_ren2_uops_0_lrs1_rtype,\n output [1:0] io_ren2_uops_0_lrs2_rtype,\n output io_ren2_uops_0_frs3_en,\n output io_ren2_uops_0_fp_val,\n output io_ren2_uops_0_fp_single,\n output io_ren2_uops_0_xcpt_pf_if,\n output io_ren2_uops_0_xcpt_ae_if,\n output io_ren2_uops_0_xcpt_ma_if,\n output io_ren2_uops_0_bp_debug_if,\n output io_ren2_uops_0_bp_xcpt_if,\n output [1:0] io_ren2_uops_0_debug_fsrc,\n output [1:0] io_ren2_uops_0_debug_tsrc,\n input [7:0] io_brupdate_b1_resolve_mask,\n input [2:0] io_brupdate_b2_uop_br_tag,\n input io_brupdate_b2_mispredict,\n input io_dis_fire_0,\n input io_dis_ready,\n input io_wakeups_0_valid,\n input [5:0] io_wakeups_0_bits_uop_pdst,\n input [1:0] io_wakeups_0_bits_uop_dst_rtype,\n input io_wakeups_1_valid,\n input [5:0] io_wakeups_1_bits_uop_pdst,\n input [1:0] io_wakeups_1_bits_uop_dst_rtype,\n input io_wakeups_2_valid,\n input [5:0] io_wakeups_2_bits_uop_pdst,\n input [1:0] io_wakeups_2_bits_uop_dst_rtype,\n input io_com_valids_0,\n input [5:0] io_com_uops_0_pdst,\n input [5:0] io_com_uops_0_stale_pdst,\n input [5:0] io_com_uops_0_ldst,\n input io_com_uops_0_ldst_val,\n input [1:0] io_com_uops_0_dst_rtype,\n input io_rbk_valids_0,\n input io_rollback,\n input io_debug_rob_empty\n);\n\n wire [5:0] bypassed_uop_pdst;\n wire _busytable_io_busy_resps_0_prs1_busy;\n wire _busytable_io_busy_resps_0_prs2_busy;\n wire _freelist_io_alloc_pregs_0_valid;\n wire [5:0] _freelist_io_alloc_pregs_0_bits;\n wire [5:0] _maptable_io_map_resps_0_prs1;\n wire [5:0] _maptable_io_map_resps_0_prs2;\n wire [5:0] _maptable_io_map_resps_0_stale_pdst;\n reg r_valid;\n reg [6:0] r_uop_uopc;\n reg [31:0] r_uop_inst;\n reg [31:0] r_uop_debug_inst;\n reg r_uop_is_rvc;\n reg [39:0] r_uop_debug_pc;\n reg [2:0] r_uop_iq_type;\n reg [9:0] r_uop_fu_code;\n reg [3:0] r_uop_ctrl_br_type;\n reg [1:0] r_uop_ctrl_op1_sel;\n reg [2:0] r_uop_ctrl_op2_sel;\n reg [2:0] r_uop_ctrl_imm_sel;\n reg [4:0] r_uop_ctrl_op_fcn;\n reg r_uop_ctrl_fcn_dw;\n reg [2:0] r_uop_ctrl_csr_cmd;\n reg r_uop_ctrl_is_load;\n reg r_uop_ctrl_is_sta;\n reg r_uop_ctrl_is_std;\n reg [1:0] r_uop_iw_state;\n reg r_uop_iw_p1_poisoned;\n reg r_uop_iw_p2_poisoned;\n reg r_uop_is_br;\n reg r_uop_is_jalr;\n reg r_uop_is_jal;\n reg r_uop_is_sfb;\n reg [7:0] r_uop_br_mask;\n reg [2:0] r_uop_br_tag;\n reg [3:0] r_uop_ftq_idx;\n reg r_uop_edge_inst;\n reg [5:0] r_uop_pc_lob;\n reg r_uop_taken;\n reg [19:0] r_uop_imm_packed;\n reg [11:0] r_uop_csr_addr;\n reg [1:0] r_uop_rxq_idx;\n reg [5:0] r_uop_prs1;\n reg [5:0] r_uop_prs2;\n reg [5:0] r_uop_stale_pdst;\n reg r_uop_exception;\n reg [63:0] r_uop_exc_cause;\n reg r_uop_bypassable;\n reg [4:0] r_uop_mem_cmd;\n reg [1:0] r_uop_mem_size;\n reg r_uop_mem_signed;\n reg r_uop_is_fence;\n reg r_uop_is_fencei;\n reg r_uop_is_amo;\n reg r_uop_uses_ldq;\n reg r_uop_uses_stq;\n reg r_uop_is_sys_pc2epc;\n reg r_uop_is_unique;\n reg r_uop_flush_on_commit;\n reg r_uop_ldst_is_rs1;\n reg [5:0] r_uop_ldst;\n reg [5:0] r_uop_lrs1;\n reg [5:0] r_uop_lrs2;\n reg [5:0] r_uop_lrs3;\n reg r_uop_ldst_val;\n reg [1:0] r_uop_dst_rtype;\n reg [1:0] r_uop_lrs1_rtype;\n reg [1:0] r_uop_lrs2_rtype;\n reg r_uop_frs3_en;\n reg r_uop_fp_val;\n reg r_uop_fp_single;\n reg r_uop_xcpt_pf_if;\n reg r_uop_xcpt_ae_if;\n reg r_uop_xcpt_ma_if;\n reg r_uop_bp_debug_if;\n reg r_uop_bp_xcpt_if;\n reg [1:0] r_uop_debug_fsrc;\n reg [1:0] r_uop_debug_tsrc;\n wire _io_ren_stalls_0_T = r_uop_dst_rtype == 2'h0;\n wire freelist_io_reqs_0 = r_uop_ldst_val & _io_ren_stalls_0_T & io_dis_fire_0;\n wire ren2_br_tags_0_valid = io_dis_fire_0 & (r_uop_is_br & ~r_uop_is_sfb | r_uop_is_jalr);\n wire _rbk_valids_0_T = io_com_uops_0_dst_rtype == 2'h0;\n wire rbk_valids_0 = io_com_uops_0_ldst_val & _rbk_valids_0_T & io_rbk_valids_0;\n assign bypassed_uop_pdst = (|r_uop_ldst) ? _freelist_io_alloc_pregs_0_bits : 6'h0;\n wire _GEN = io_kill | ~io_dis_ready;\n always @(posedge clock) begin\n if (reset)\n r_valid <= 1'h0;\n else\n r_valid <= ~io_kill & (io_dis_ready ? io_dec_fire_0 : r_valid & ~io_dis_fire_0);\n if (_GEN) begin\n end\n else begin\n r_uop_uopc <= io_dec_uops_0_uopc;\n r_uop_inst <= io_dec_uops_0_inst;\n r_uop_debug_inst <= io_dec_uops_0_debug_inst;\n r_uop_is_rvc <= io_dec_uops_0_is_rvc;\n r_uop_debug_pc <= io_dec_uops_0_debug_pc;\n r_uop_iq_type <= io_dec_uops_0_iq_type;\n r_uop_fu_code <= io_dec_uops_0_fu_code;\n r_uop_ctrl_br_type <= 4'h0;\n r_uop_ctrl_op1_sel <= 2'h0;\n r_uop_ctrl_op2_sel <= 3'h0;\n r_uop_ctrl_imm_sel <= 3'h0;\n r_uop_ctrl_op_fcn <= 5'h0;\n end\n r_uop_ctrl_fcn_dw <= _GEN & r_uop_ctrl_fcn_dw;\n if (_GEN) begin\n end\n else\n r_uop_ctrl_csr_cmd <= 3'h0;\n r_uop_ctrl_is_load <= _GEN & r_uop_ctrl_is_load;\n r_uop_ctrl_is_sta <= _GEN & r_uop_ctrl_is_sta;\n r_uop_ctrl_is_std <= _GEN & r_uop_ctrl_is_std;\n if (_GEN) begin\n end\n else\n r_uop_iw_state <= 2'h0;\n r_uop_iw_p1_poisoned <= _GEN & r_uop_iw_p1_poisoned;\n r_uop_iw_p2_poisoned <= _GEN & r_uop_iw_p2_poisoned;\n if (_GEN) begin\n end\n else begin\n r_uop_is_br <= io_dec_uops_0_is_br;\n r_uop_is_jalr <= io_dec_uops_0_is_jalr;\n r_uop_is_jal <= io_dec_uops_0_is_jal;\n r_uop_is_sfb <= io_dec_uops_0_is_sfb;\n end\n r_uop_br_mask <= (_GEN ? r_uop_br_mask : io_dec_uops_0_br_mask) & ~io_brupdate_b1_resolve_mask;\n if (_GEN) begin\n end\n else begin\n r_uop_br_tag <= io_dec_uops_0_br_tag;\n r_uop_ftq_idx <= io_dec_uops_0_ftq_idx;\n r_uop_edge_inst <= io_dec_uops_0_edge_inst;\n r_uop_pc_lob <= io_dec_uops_0_pc_lob;\n r_uop_taken <= io_dec_uops_0_taken;\n r_uop_imm_packed <= io_dec_uops_0_imm_packed;\n r_uop_csr_addr <= 12'h0;\n r_uop_rxq_idx <= 2'h0;\n end\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs1 : io_dec_uops_0_lrs1))\n r_uop_prs1 <= bypassed_uop_pdst;\n else if (_GEN) begin\n end\n else\n r_uop_prs1 <= _maptable_io_map_resps_0_prs1;\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_lrs2 : io_dec_uops_0_lrs2))\n r_uop_prs2 <= bypassed_uop_pdst;\n else if (_GEN) begin\n end\n else\n r_uop_prs2 <= _maptable_io_map_resps_0_prs2;\n if (freelist_io_reqs_0 & r_uop_ldst == (_GEN ? r_uop_ldst : io_dec_uops_0_ldst))\n r_uop_stale_pdst <= bypassed_uop_pdst;\n else if (_GEN) begin\n end\n else\n r_uop_stale_pdst <= _maptable_io_map_resps_0_stale_pdst;\n if (_GEN) begin\n end\n else begin\n r_uop_exception <= io_dec_uops_0_exception;\n r_uop_exc_cause <= io_dec_uops_0_exc_cause;\n r_uop_bypassable <= io_dec_uops_0_bypassable;\n r_uop_mem_cmd <= io_dec_uops_0_mem_cmd;\n r_uop_mem_size <= io_dec_uops_0_mem_size;\n r_uop_mem_signed <= io_dec_uops_0_mem_signed;\n r_uop_is_fence <= io_dec_uops_0_is_fence;\n r_uop_is_fencei <= io_dec_uops_0_is_fencei;\n r_uop_is_amo <= io_dec_uops_0_is_amo;\n r_uop_uses_ldq <= io_dec_uops_0_uses_ldq;\n r_uop_uses_stq <= io_dec_uops_0_uses_stq;\n r_uop_is_sys_pc2epc <= io_dec_uops_0_is_sys_pc2epc;\n r_uop_is_unique <= io_dec_uops_0_is_unique;\n r_uop_flush_on_commit <= io_dec_uops_0_flush_on_commit;\n end\n r_uop_ldst_is_rs1 <= _GEN & r_uop_ldst_is_rs1;\n if (_GEN) begin\n end\n else begin\n r_uop_ldst <= io_dec_uops_0_ldst;\n r_uop_lrs1 <= io_dec_uops_0_lrs1;\n r_uop_lrs2 <= io_dec_uops_0_lrs2;\n r_uop_lrs3 <= io_dec_uops_0_lrs3;\n r_uop_ldst_val <= io_dec_uops_0_ldst_val;\n r_uop_dst_rtype <= io_dec_uops_0_dst_rtype;\n r_uop_lrs1_rtype <= io_dec_uops_0_lrs1_rtype;\n r_uop_lrs2_rtype <= io_dec_uops_0_lrs2_rtype;\n r_uop_frs3_en <= io_dec_uops_0_frs3_en;\n r_uop_fp_val <= io_dec_uops_0_fp_val;\n r_uop_fp_single <= io_dec_uops_0_fp_single;\n r_uop_xcpt_pf_if <= io_dec_uops_0_xcpt_pf_if;\n r_uop_xcpt_ae_if <= io_dec_uops_0_xcpt_ae_if;\n end\n r_uop_xcpt_ma_if <= _GEN & r_uop_xcpt_ma_if;\n if (_GEN) begin\n end\n else begin\n r_uop_bp_debug_if <= io_dec_uops_0_bp_debug_if;\n r_uop_bp_xcpt_if <= io_dec_uops_0_bp_xcpt_if;\n r_uop_debug_fsrc <= io_dec_uops_0_debug_fsrc;\n r_uop_debug_tsrc <= 2'h0;\n end\n end\n RenameMapTable maptable (\n .clock (clock),\n .reset (reset),\n .io_map_reqs_0_lrs1 (io_dec_uops_0_lrs1),\n .io_map_reqs_0_lrs2 (io_dec_uops_0_lrs2),\n .io_map_reqs_0_ldst (io_dec_uops_0_ldst),\n .io_map_resps_0_prs1 (_maptable_io_map_resps_0_prs1),\n .io_map_resps_0_prs2 (_maptable_io_map_resps_0_prs2),\n .io_map_resps_0_stale_pdst (_maptable_io_map_resps_0_stale_pdst),\n .io_remap_reqs_0_ldst (io_rollback ? io_com_uops_0_ldst : r_uop_ldst),\n .io_remap_reqs_0_pdst (io_rollback ? io_com_uops_0_stale_pdst : bypassed_uop_pdst),\n .io_remap_reqs_0_valid (freelist_io_reqs_0 | rbk_valids_0),\n .io_ren_br_tags_0_valid (ren2_br_tags_0_valid),\n .io_ren_br_tags_0_bits (r_uop_br_tag),\n .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),\n .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),\n .io_rollback (io_rollback)\n );\n RenameFreeList freelist (\n .clock (clock),\n .reset (reset),\n .io_reqs_0 (freelist_io_reqs_0),\n .io_alloc_pregs_0_valid (_freelist_io_alloc_pregs_0_valid),\n .io_alloc_pregs_0_bits (_freelist_io_alloc_pregs_0_bits),\n .io_dealloc_pregs_0_valid (io_com_uops_0_ldst_val & _rbk_valids_0_T & io_com_valids_0 | rbk_valids_0),\n .io_dealloc_pregs_0_bits (io_rollback ? io_com_uops_0_pdst : io_com_uops_0_stale_pdst),\n .io_ren_br_tags_0_valid (ren2_br_tags_0_valid),\n .io_ren_br_tags_0_bits (r_uop_br_tag),\n .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag),\n .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict),\n .io_debug_pipeline_empty (io_debug_rob_empty)\n );\n RenameBusyTable busytable (\n .clock (clock),\n .reset (reset),\n .io_ren_uops_0_pdst (bypassed_uop_pdst),\n .io_ren_uops_0_prs1 (r_uop_prs1),\n .io_ren_uops_0_prs2 (r_uop_prs2),\n .io_busy_resps_0_prs1_busy (_busytable_io_busy_resps_0_prs1_busy),\n .io_busy_resps_0_prs2_busy (_busytable_io_busy_resps_0_prs2_busy),\n .io_rebusy_reqs_0 (freelist_io_reqs_0),\n .io_wb_pdsts_0 (io_wakeups_0_bits_uop_pdst),\n .io_wb_pdsts_1 (io_wakeups_1_bits_uop_pdst),\n .io_wb_pdsts_2 (io_wakeups_2_bits_uop_pdst),\n .io_wb_valids_0 (io_wakeups_0_valid),\n .io_wb_valids_1 (io_wakeups_1_valid),\n .io_wb_valids_2 (io_wakeups_2_valid)\n );\n assign io_ren_stalls_0 = _io_ren_stalls_0_T & ~_freelist_io_alloc_pregs_0_valid;\n assign io_ren2_mask_0 = r_valid;\n assign io_ren2_uops_0_uopc = r_uop_uopc;\n assign io_ren2_uops_0_inst = r_uop_inst;\n assign io_ren2_uops_0_debug_inst = r_uop_debug_inst;\n assign io_ren2_uops_0_is_rvc = r_uop_is_rvc;\n assign io_ren2_uops_0_debug_pc = r_uop_debug_pc;\n assign io_ren2_uops_0_iq_type = r_uop_iq_type;\n assign io_ren2_uops_0_fu_code = r_uop_fu_code;\n assign io_ren2_uops_0_ctrl_br_type = r_uop_ctrl_br_type;\n assign io_ren2_uops_0_ctrl_op1_sel = r_uop_ctrl_op1_sel;\n assign io_ren2_uops_0_ctrl_op2_sel = r_uop_ctrl_op2_sel;\n assign io_ren2_uops_0_ctrl_imm_sel = r_uop_ctrl_imm_sel;\n assign io_ren2_uops_0_ctrl_op_fcn = r_uop_ctrl_op_fcn;\n assign io_ren2_uops_0_ctrl_fcn_dw = r_uop_ctrl_fcn_dw;\n assign io_ren2_uops_0_ctrl_csr_cmd = r_uop_ctrl_csr_cmd;\n assign io_ren2_uops_0_ctrl_is_load = r_uop_ctrl_is_load;\n assign io_ren2_uops_0_ctrl_is_sta = r_uop_ctrl_is_sta;\n assign io_ren2_uops_0_ctrl_is_std = r_uop_ctrl_is_std;\n assign io_ren2_uops_0_iw_state = r_uop_iw_state;\n assign io_ren2_uops_0_iw_p1_poisoned = r_uop_iw_p1_poisoned;\n assign io_ren2_uops_0_iw_p2_poisoned = r_uop_iw_p2_poisoned;\n assign io_ren2_uops_0_is_br = r_uop_is_br;\n assign io_ren2_uops_0_is_jalr = r_uop_is_jalr;\n assign io_ren2_uops_0_is_jal = r_uop_is_jal;\n assign io_ren2_uops_0_is_sfb = r_uop_is_sfb;\n assign io_ren2_uops_0_br_mask = r_uop_br_mask & ~io_brupdate_b1_resolve_mask;\n assign io_ren2_uops_0_br_tag = r_uop_br_tag;\n assign io_ren2_uops_0_ftq_idx = r_uop_ftq_idx;\n assign io_ren2_uops_0_edge_inst = r_uop_edge_inst;\n assign io_ren2_uops_0_pc_lob = r_uop_pc_lob;\n assign io_ren2_uops_0_taken = r_uop_taken;\n assign io_ren2_uops_0_imm_packed = r_uop_imm_packed;\n assign io_ren2_uops_0_csr_addr = r_uop_csr_addr;\n assign io_ren2_uops_0_rxq_idx = r_uop_rxq_idx;\n assign io_ren2_uops_0_pdst = bypassed_uop_pdst;\n assign io_ren2_uops_0_prs1 = r_uop_prs1;\n assign io_ren2_uops_0_prs2 = r_uop_prs2;\n assign io_ren2_uops_0_prs1_busy = r_uop_lrs1_rtype == 2'h0 & _busytable_io_busy_resps_0_prs1_busy;\n assign io_ren2_uops_0_prs2_busy = r_uop_lrs2_rtype == 2'h0 & _busytable_io_busy_resps_0_prs2_busy;\n assign io_ren2_uops_0_stale_pdst = r_uop_stale_pdst;\n assign io_ren2_uops_0_exception = r_uop_exception;\n assign io_ren2_uops_0_exc_cause = r_uop_exc_cause;\n assign io_ren2_uops_0_bypassable = r_uop_bypassable;\n assign io_ren2_uops_0_mem_cmd = r_uop_mem_cmd;\n assign io_ren2_uops_0_mem_size = r_uop_mem_size;\n assign io_ren2_uops_0_mem_signed = r_uop_mem_signed;\n assign io_ren2_uops_0_is_fence = r_uop_is_fence;\n assign io_ren2_uops_0_is_fencei = r_uop_is_fencei;\n assign io_ren2_uops_0_is_amo = r_uop_is_amo;\n assign io_ren2_uops_0_uses_ldq = r_uop_uses_ldq;\n assign io_ren2_uops_0_uses_stq = r_uop_uses_stq;\n assign io_ren2_uops_0_is_sys_pc2epc = r_uop_is_sys_pc2epc;\n assign io_ren2_uops_0_is_unique = r_uop_is_unique;\n assign io_ren2_uops_0_flush_on_commit = r_uop_flush_on_commit;\n assign io_ren2_uops_0_ldst_is_rs1 = r_uop_ldst_is_rs1;\n assign io_ren2_uops_0_ldst = r_uop_ldst;\n assign io_ren2_uops_0_lrs1 = r_uop_lrs1;\n assign io_ren2_uops_0_lrs2 = r_uop_lrs2;\n assign io_ren2_uops_0_lrs3 = r_uop_lrs3;\n assign io_ren2_uops_0_ldst_val = r_uop_ldst_val;\n assign io_ren2_uops_0_dst_rtype = r_uop_dst_rtype;\n assign io_ren2_uops_0_lrs1_rtype = r_uop_lrs1_rtype;\n assign io_ren2_uops_0_lrs2_rtype = r_uop_lrs2_rtype;\n assign io_ren2_uops_0_frs3_en = r_uop_frs3_en;\n assign io_ren2_uops_0_fp_val = r_uop_fp_val;\n assign io_ren2_uops_0_fp_single = r_uop_fp_single;\n assign io_ren2_uops_0_xcpt_pf_if = r_uop_xcpt_pf_if;\n assign io_ren2_uops_0_xcpt_ae_if = r_uop_xcpt_ae_if;\n assign io_ren2_uops_0_xcpt_ma_if = r_uop_xcpt_ma_if;\n assign io_ren2_uops_0_bp_debug_if = r_uop_bp_debug_if;\n assign io_ren2_uops_0_bp_xcpt_if = r_uop_bp_xcpt_if;\n assign io_ren2_uops_0_debug_fsrc = r_uop_debug_fsrc;\n assign io_ren2_uops_0_debug_tsrc = r_uop_debug_tsrc;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}", + "response": "module OptimizationBarrier_EntryData(\n input [19:0] io_x_ppn,\n input io_x_u,\n input io_x_ae,\n input io_x_sw,\n input io_x_sx,\n input io_x_sr,\n input io_x_pw,\n input io_x_pr,\n input io_x_pal,\n input io_x_paa,\n input io_x_eff,\n input io_x_c,\n output [19:0] io_y_ppn,\n output io_y_u,\n output io_y_ae,\n output io_y_sw,\n output io_y_sx,\n output io_y_sr,\n output io_y_pw,\n output io_y_pr,\n output io_y_pal,\n output io_y_paa,\n output io_y_eff,\n output io_y_c\n);\n\n assign io_y_ppn = io_x_ppn;\n assign io_y_u = io_x_u;\n assign io_y_ae = io_x_ae;\n assign io_y_sw = io_x_sw;\n assign io_y_sx = io_x_sx;\n assign io_y_sr = io_x_sr;\n assign io_y_pw = io_x_pw;\n assign io_y_pr = io_x_pr;\n assign io_y_pal = io_x_pal;\n assign io_y_paa = io_x_paa;\n assign io_y_eff = io_x_eff;\n assign io_y_c = io_x_c;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\n\nclass SinkXRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)\n{\n val address = UInt(params.inner.bundle.addressBits.W)\n}\n\nclass SinkX(params: InclusiveCacheParameters) extends Module\n{\n val io = IO(new Bundle {\n val req = Decoupled(new FullRequest(params))\n val x = Flipped(Decoupled(new SinkXRequest(params)))\n })\n\n val x = Queue(io.x, 1)\n val (tag, set, offset) = params.parseAddress(x.bits.address)\n\n x.ready := io.req.ready\n io.req.valid := x.valid\n params.ccover(x.valid && !x.ready, \"SINKX_STALL\", \"Backpressure when accepting a control message\")\n\n io.req.bits.prio := VecInit(1.U(3.W).asBools) // same prio as A\n io.req.bits.control:= true.B\n io.req.bits.opcode := 0.U\n io.req.bits.param := 0.U\n io.req.bits.size := params.offsetBits.U\n // The source does not matter, because a flush command never allocates a way.\n // However, it must be a legal source, otherwise assertions might spuriously fire.\n io.req.bits.source := params.inner.client.clients.map(_.sourceId.start).min.U\n io.req.bits.offset := 0.U\n io.req.bits.set := set\n io.req.bits.tag := tag\n io.req.bits.put := 0.U\n}", + "response": "module SinkX(\n input clock,\n input reset,\n input io_req_ready,\n output io_req_valid,\n output [12:0] io_req_bits_tag,\n output [9:0] io_req_bits_set,\n output io_x_ready,\n input io_x_valid,\n input [31:0] io_x_bits_address\n);\n\n wire [31:0] _x_q_io_deq_bits_address;\n Queue1_SinkXRequest x_q (\n .clock (clock),\n .reset (reset),\n .io_enq_ready (io_x_ready),\n .io_enq_valid (io_x_valid),\n .io_enq_bits_address (io_x_bits_address),\n .io_deq_ready (io_req_ready),\n .io_deq_valid (io_req_valid),\n .io_deq_bits_address (_x_q_io_deq_bits_address)\n );\n assign io_req_bits_tag = {_x_q_io_deq_bits_address[31], _x_q_io_deq_bits_address[27:16]};\n assign io_req_bits_set = _x_q_io_deq_bits_address[15:6];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLEFromBeat_serial_tl_0_a64d64s8k8z8c(\n input clock,\n input reset,\n output io_beat_ready,\n input io_beat_valid,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~(_GEN & io_beat_bits_head) & is_const;\n end\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.Berkeley for license details.\n// See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.tile\n\nimport chisel3._\nimport chisel3.util._\nimport chisel3.{DontCare, WireInit, withClock, withReset}\nimport chisel3.experimental.SourceInfo\nimport chisel3.experimental.dataview._\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.util.property\n\ncase class FPUParams(\n minFLen: Int = 32,\n fLen: Int = 64,\n divSqrt: Boolean = true,\n sfmaLatency: Int = 3,\n dfmaLatency: Int = 4,\n fpmuLatency: Int = 2,\n ifpuLatency: Int = 2\n)\n\nobject FPConstants\n{\n val RM_SZ = 3\n val FLAGS_SZ = 5\n}\n\ntrait HasFPUCtrlSigs {\n val ldst = Bool()\n val wen = Bool()\n val ren1 = Bool()\n val ren2 = Bool()\n val ren3 = Bool()\n val swap12 = Bool()\n val swap23 = Bool()\n val typeTagIn = UInt(2.W)\n val typeTagOut = UInt(2.W)\n val fromint = Bool()\n val toint = Bool()\n val fastpipe = Bool()\n val fma = Bool()\n val div = Bool()\n val sqrt = Bool()\n val wflags = Bool()\n val vec = Bool()\n}\n\nclass FPUCtrlSigs extends Bundle with HasFPUCtrlSigs\n\nclass FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new Bundle {\n val inst = Input(Bits(32.W))\n val sigs = Output(new FPUCtrlSigs())\n })\n\n private val X2 = BitPat.dontCare(2)\n\n val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)\n val h: Array[(BitPat, List[BitPat])] =\n Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),\n FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),\n FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),\n FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),\n FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),\n FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),\n FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),\n FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),\n FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),\n FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),\n FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),\n FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),\n FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),\n FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))\n val f: Array[(BitPat, List[BitPat])] =\n Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),\n FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),\n FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),\n FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),\n FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),\n FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),\n FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),\n FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),\n FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),\n FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),\n FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),\n FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),\n FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))\n val d: Array[(BitPat, List[BitPat])] =\n Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),\n FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),\n FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),\n FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),\n FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),\n FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),\n FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),\n FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),\n FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),\n FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),\n FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),\n FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),\n FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),\n FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),\n FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),\n FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))\n val fcvt_hd: Array[(BitPat, List[BitPat])] =\n Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),\n FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))\n val vfmv_f_s: Array[(BitPat, List[BitPat])] =\n Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))\n\n val insns = ((minFLen, fLen) match {\n case (32, 32) => f\n case (16, 32) => h ++ f\n case (32, 64) => f ++ d\n case (16, 64) => h ++ f ++ d ++ fcvt_hd\n case other => throw new Exception(s\"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration\")\n }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())\n val decoder = DecodeLogic(io.inst, default, insns)\n val s = io.sigs\n val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,\n s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,\n s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)\n sigs zip decoder map {case(s,d) => s := d}\n}\n\nclass FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {\n val hartid = Input(UInt(hartIdLen.W))\n val time = Input(UInt(xLen.W))\n\n val inst = Input(Bits(32.W))\n val fromint_data = Input(Bits(xLen.W))\n\n val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))\n val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))\n\n val v_sew = Input(UInt(3.W))\n\n val store_data = Output(Bits(fLen.W))\n val toint_data = Output(Bits(xLen.W))\n\n val ll_resp_val = Input(Bool())\n val ll_resp_type = Input(Bits(3.W))\n val ll_resp_tag = Input(UInt(5.W))\n val ll_resp_data = Input(Bits(fLen.W))\n\n val valid = Input(Bool())\n val fcsr_rdy = Output(Bool())\n val nack_mem = Output(Bool())\n val illegal_rm = Output(Bool())\n val killx = Input(Bool())\n val killm = Input(Bool())\n val dec = Output(new FPUCtrlSigs())\n val sboard_set = Output(Bool())\n val sboard_clr = Output(Bool())\n val sboard_clra = Output(UInt(5.W))\n\n val keep_clock_enabled = Input(Bool())\n}\n\nclass FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {\n val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs\n val cp_resp = Decoupled(new FPResult())\n}\n\nclass FPResult(implicit p: Parameters) extends CoreBundle()(p) {\n val data = Bits((fLen+1).W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n}\n\nclass IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val typ = Bits(2.W)\n val in1 = Bits(xLen.W)\n}\n\nclass FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {\n val rm = Bits(FPConstants.RM_SZ.W)\n val fmaCmd = Bits(2.W)\n val typ = Bits(2.W)\n val fmt = Bits(2.W)\n val in1 = Bits((fLen+1).W)\n val in2 = Bits((fLen+1).W)\n val in3 = Bits((fLen+1).W)\n\n}\n\ncase class FType(exp: Int, sig: Int) {\n def ieeeWidth = exp + sig\n def recodedWidth = ieeeWidth + 1\n\n def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)\n def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)\n def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR\n def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)\n\n def classify(x: UInt) = {\n val sign = x(sig + exp)\n val code = x(exp + sig - 1, exp + sig - 3)\n val codeHi = code(2, 1)\n val isSpecial = codeHi === 3.U\n\n val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U\n val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn\n val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U\n val isZero = code === 0.U\n val isInf = isSpecial && !code(0)\n val isNaN = code.andR\n val isSNaN = isNaN && !x(sig-2)\n val isQNaN = isNaN && x(sig-2)\n\n Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,\n isSubnormal && !sign, isZero && !sign, isZero && sign,\n isSubnormal && sign, isNormal && sign, isInf && sign)\n }\n\n // convert between formats, ignoring rounding, range, NaN\n def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {\n val sign = x(sig + exp)\n val fractIn = x(sig - 2, 0)\n val expIn = x(sig + exp - 1, sig - 1)\n val fractOut = fractIn << to.sig >> sig\n val expOut = {\n val expCode = expIn(exp, exp - 2)\n val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U\n Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))\n }\n Cat(sign, expOut, fractOut)\n }\n\n private def ieeeBundle = {\n val expWidth = exp\n class IEEEBundle extends Bundle {\n val sign = Bool()\n val exp = UInt(expWidth.W)\n val sig = UInt((ieeeWidth-expWidth-1).W)\n }\n new IEEEBundle\n }\n\n def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)\n\n def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)\n def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)\n}\n\nobject FType {\n val H = new FType(5, 11)\n val S = new FType(8, 24)\n val D = new FType(11, 53)\n\n val all = List(H, S, D)\n}\n\ntrait HasFPUParameters {\n require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))\n val minFLen: Int\n val fLen: Int\n def xLen: Int\n val minXLen = 32\n val nIntTypes = log2Ceil(xLen/minXLen) + 1\n def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)\n def minType = floatTypes.head\n def maxType = floatTypes.last\n def prevType(t: FType) = floatTypes(typeTag(t) - 1)\n def maxExpWidth = maxType.exp\n def maxSigWidth = maxType.sig\n def typeTag(t: FType) = floatTypes.indexOf(t)\n def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U\n def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U\n // typeTag\n def H = typeTagGroup(FType.H)\n def S = typeTagGroup(FType.S)\n def D = typeTagGroup(FType.D)\n def I = typeTag(maxType).U\n\n private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR\n\n private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {\n require(xt.ieeeWidth == 2 * yt.ieeeWidth)\n val swizzledNaN = Cat(\n x(xt.sig + xt.exp, xt.sig + xt.exp - 3),\n x(xt.sig - 2, yt.recodedWidth - 1).andR,\n x(xt.sig + xt.exp - 5, xt.sig),\n y(yt.recodedWidth - 2),\n x(xt.sig - 2, yt.recodedWidth - 1),\n y(yt.recodedWidth - 1),\n y(yt.recodedWidth - 3, 0))\n Mux(xt.isNaN(x), swizzledNaN, x)\n }\n\n // implement NaN unboxing for FU inputs\n def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {\n val outType = exactType.getOrElse(maxType)\n def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {\n val prev =\n if (t == minType) {\n Seq()\n } else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prev = helper(unswizzled, prevT)\n val isbox = isBox(x, t)\n prev.map(p => (isbox && p._1, p._2))\n }\n prev :+ (true.B, t.unsafeConvert(x, outType))\n }\n\n val (oks, floats) = helper(x, maxType).unzip\n if (exactType.isEmpty || floatTypes.size == 1) {\n Mux(oks(tag), floats(tag), maxType.qNaN)\n } else {\n val t = exactType.get\n floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)\n }\n }\n\n // make sure that the redundant bits in the NaN-boxed encoding are consistent\n def consistent(x: UInt): Bool = {\n def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {\n val prevT = prevType(t)\n val unswizzled = Cat(\n x(prevT.sig + prevT.exp - 1),\n x(t.sig - 1),\n x(prevT.sig + prevT.exp - 2, 0))\n val prevOK = !isBox(x, t) || helper(unswizzled, prevT)\n val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR\n prevOK && curOK\n }\n helper(x, maxType)\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, t: FType): UInt = {\n if (t == maxType) {\n x\n } else {\n val nt = floatTypes(typeTag(t) + 1)\n val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)\n bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U\n }\n }\n\n // generate a NaN box from an FU result\n def box(x: UInt, tag: UInt): UInt = {\n val opts = floatTypes.map(t => box(x, t))\n opts(tag)\n }\n\n // zap bits that hardfloat thinks are don't-cares, but we do care about\n def sanitizeNaN(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n x\n } else {\n val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)\n Mux(t.isNaN(x), maskedNaN, x)\n }\n }\n\n // implement NaN boxing and recoding for FL*/fmv.*.x\n def recode(x: UInt, tag: UInt): UInt = {\n def helper(x: UInt, t: FType): UInt = {\n if (typeTag(t) == 0) {\n t.recode(x)\n } else {\n val prevT = prevType(t)\n box(t.recode(x), t, helper(x, prevT), prevT)\n }\n }\n\n // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value\n val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)\n helper(boxes(tag) | x, maxType)\n }\n\n // implement NaN unboxing and un-recoding for FS*/fmv.x.*\n def ieee(x: UInt, t: FType = maxType): UInt = {\n if (typeTag(t) == 0) {\n t.ieee(x)\n } else {\n val unrecoded = t.ieee(x)\n val prevT = prevType(t)\n val prevRecoded = Cat(\n x(prevT.recodedWidth-2),\n x(t.sig-1),\n x(prevT.recodedWidth-3, 0))\n val prevUnrecoded = ieee(prevRecoded, prevT)\n Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))\n }\n }\n}\n\nabstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters\n\nclass FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n class Output extends Bundle {\n val in = new FPInput\n val lt = Bool()\n val store = Bits(fLen.W)\n val toint = Bits(xLen.W)\n val exc = Bits(FPConstants.FLAGS_SZ.W)\n }\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new Output)\n })\n\n val in = RegEnable(io.in.bits, io.in.valid)\n val valid = RegNext(io.in.valid)\n\n val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))\n dcmp.io.a := in.in1\n dcmp.io.b := in.in2\n dcmp.io.signaling := !in.rm(1)\n\n val tag = in.typeTagOut\n val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))\n else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n\n val toint = WireDefault(toint_ieee)\n val intType = WireDefault(in.fmt(0))\n io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)\n io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)\n io.out.bits.exc := 0.U\n\n when (in.rm(0)) {\n val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)\n toint := classify_out | (toint_ieee >> minXLen << minXLen)\n intType := false.B\n }\n\n when (in.wflags) { // feq/flt/fle, fcvt\n toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)\n io.out.bits.exc := dcmp.io.exceptionFlags\n intType := false.B\n\n when (!in.ren2) { // fcvt\n val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)\n intType := cvtType\n val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))\n conv.io.in := in.in1\n conv.io.roundingMode := in.rm\n conv.io.signedOut := ~in.typ(0)\n toint := conv.io.out\n io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))\n\n for (i <- 0 until nIntTypes-1) {\n val w = minXLen << i\n when (cvtType === i.U) {\n val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))\n narrow.io.in := in.in1\n narrow.io.roundingMode := in.rm\n narrow.io.signedOut := ~in.typ(0)\n\n val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)\n val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))\n val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)\n when (invalid) { toint := Cat(conv.io.out >> w, excOut) }\n io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))\n }\n }\n }\n }\n\n io.out.valid := valid\n io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)\n io.out.bits.in := in\n}\n\nclass IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new IntToFPInput))\n val out = Valid(new FPResult)\n })\n\n val in = Pipe(io.in)\n val tag = in.bits.typeTagIn\n\n val mux = Wire(new FPResult)\n mux.exc := 0.U\n mux.data := recode(in.bits.in1, tag)\n\n val intValue = {\n val res = WireDefault(in.bits.in1.asSInt)\n for (i <- 0 until nIntTypes-1) {\n val smallInt = in.bits.in1((minXLen << i) - 1, 0)\n when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {\n res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)\n }\n }\n res.asUInt\n }\n\n when (in.bits.wflags) { // fcvt\n // could be improved for RVD/RVQ with a single variable-position rounding\n // unit, rather than N fixed-position ones\n val i2fResults = for (t <- floatTypes) yield {\n val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))\n i2f.io.signedIn := ~in.bits.typ(0)\n i2f.io.in := intValue\n i2f.io.roundingMode := in.bits.rm\n i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding\n (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)\n }\n\n val (data, exc) = i2fResults.unzip\n val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last\n mux.data := dataPadded(tag)\n mux.exc := exc(tag)\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n val lt = Input(Bool()) // from FPToInt\n })\n\n val in = Pipe(io.in)\n\n val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))\n val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))\n\n val fsgnjMux = Wire(new FPResult)\n fsgnjMux.exc := 0.U\n fsgnjMux.data := fsgnj\n\n when (in.bits.wflags) { // fmin/fmax\n val isnan1 = maxType.isNaN(in.bits.in1)\n val isnan2 = maxType.isNaN(in.bits.in2)\n val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)\n val isNaNOut = isnan1 && isnan2\n val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1\n fsgnjMux.exc := isInvalid << 4\n fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))\n }\n\n val inTag = in.bits.typeTagIn\n val outTag = in.bits.typeTagOut\n val mux = WireDefault(fsgnjMux)\n for (t <- floatTypes.init) {\n when (outTag === typeTag(t).U) {\n mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))\n }\n }\n\n when (in.bits.wflags && !in.bits.ren2) { // fcvt\n if (floatTypes.size > 1) {\n // widening conversions simply canonicalize NaN operands\n val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)\n fsgnjMux.data := widened\n fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4\n\n // narrowing conversions require rounding (for RVQ, this could be\n // optimized to use a single variable-position rounding unit, rather\n // than two fixed-position ones)\n for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {\n val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))\n narrower.io.in := in.bits.in1\n narrower.io.roundingMode := in.bits.rm\n narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding\n val narrowed = sanitizeNaN(narrower.io.out, outType)\n mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)\n mux.exc := narrower.io.exceptionFlags\n }\n }\n }\n\n io.out <> Pipe(in.valid, mux, latency-1)\n}\n\nclass MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module\n{\n override def desiredName = s\"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}\"\n require(latency<=2)\n\n val io = IO(new Bundle {\n val validin = Input(Bool())\n val op = Input(Bits(2.W))\n val a = Input(Bits((expWidth + sigWidth + 1).W))\n val b = Input(Bits((expWidth + sigWidth + 1).W))\n val c = Input(Bits((expWidth + sigWidth + 1).W))\n val roundingMode = Input(UInt(3.W))\n val detectTininess = Input(UInt(1.W))\n val out = Output(Bits((expWidth + sigWidth + 1).W))\n val exceptionFlags = Output(Bits(5.W))\n val validout = Output(Bool())\n })\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))\n val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))\n\n mulAddRecFNToRaw_preMul.io.op := io.op\n mulAddRecFNToRaw_preMul.io.a := io.a\n mulAddRecFNToRaw_preMul.io.b := io.b\n mulAddRecFNToRaw_preMul.io.c := io.c\n\n val mulAddResult =\n (mulAddRecFNToRaw_preMul.io.mulAddA *\n mulAddRecFNToRaw_preMul.io.mulAddB) +&\n mulAddRecFNToRaw_preMul.io.mulAddC\n\n val valid_stage0 = Wire(Bool())\n val roundingMode_stage0 = Wire(UInt(3.W))\n val detectTininess_stage0 = Wire(UInt(1.W))\n\n val postmul_regs = if(latency>0) 1 else 0\n mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits\n mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits\n detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits\n valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid\n\n //------------------------------------------------------------------------\n //------------------------------------------------------------------------\n\n val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))\n\n val round_regs = if(latency==2) 1 else 0\n roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits\n roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits\n roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits\n roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits\n io.validout := Pipe(valid_stage0, false.B, round_regs).valid\n\n roundRawFNToRecFN.io.infiniteExc := false.B\n\n io.out := roundRawFNToRecFN.io.out\n io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags\n}\n\nclass FPUFMAPipe(val latency: Int, val t: FType)\n (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {\n override def desiredName = s\"FPUFMAPipe_l${latency}_f${t.ieeeWidth}\"\n require(latency>0)\n\n val io = IO(new Bundle {\n val in = Flipped(Valid(new FPInput))\n val out = Valid(new FPResult)\n })\n\n val valid = RegNext(io.in.valid)\n val in = Reg(new FPInput)\n when (io.in.valid) {\n val one = 1.U << (t.sig + t.exp - 1)\n val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))\n val cmd_fma = io.in.bits.ren3\n val cmd_addsub = io.in.bits.swap23\n in := io.in.bits\n when (cmd_addsub) { in.in2 := one }\n when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }\n }\n\n val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))\n fma.io.validin := valid\n fma.io.op := in.fmaCmd\n fma.io.roundingMode := in.rm\n fma.io.detectTininess := hardfloat.consts.tininess_afterRounding\n fma.io.a := in.in1\n fma.io.b := in.in2\n fma.io.c := in.in3\n\n val res = Wire(new FPResult)\n res.data := sanitizeNaN(fma.io.out, t)\n res.exc := fma.io.exceptionFlags\n\n io.out := Pipe(fma.io.validout, res, (latency-3) max 0)\n}\n\nclass FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {\n val io = IO(new FPUIO)\n\n val (useClockGating, useDebugROB) = coreParams match {\n case r: RocketCoreParams =>\n val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1\n (r.clockGate, sz < 1)\n case _ => (false, false)\n }\n val clock_en_reg = Reg(Bool())\n val clock_en = clock_en_reg || io.cp_req.valid\n val gated_clock =\n if (!useClockGating) clock\n else ClockGate(clock, clock_en, \"fpu_clock_gate\")\n\n val fp_decoder = Module(new FPUDecoder)\n fp_decoder.io.inst := io.inst\n val id_ctrl = WireInit(fp_decoder.io.sigs)\n coreParams match { case r: RocketCoreParams => r.vector.map(v => {\n val v_decode = v.decoder(p) // Only need to get ren1\n v_decode.io.inst := io.inst\n v_decode.io.vconfig := DontCare // core deals with this\n when (v_decode.io.legal && v_decode.io.read_frs1) {\n id_ctrl.ren1 := true.B\n id_ctrl.swap12 := false.B\n id_ctrl.toint := true.B\n id_ctrl.typeTagIn := I\n id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)\n }\n when (v_decode.io.write_frd) { id_ctrl.wen := true.B }\n })}\n\n val ex_reg_valid = RegNext(io.valid, false.B)\n val ex_reg_inst = RegEnable(io.inst, io.valid)\n val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)\n val ex_ra = List.fill(3)(Reg(UInt()))\n\n // load/vector response\n val load_wb = RegNext(io.ll_resp_val)\n val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)\n val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)\n val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)\n\n class FPUImpl { // entering gated-clock domain\n\n val req_valid = ex_reg_valid || io.cp_req.valid\n val ex_cp_valid = io.cp_req.fire\n val mem_cp_valid = RegNext(ex_cp_valid, false.B)\n val wb_cp_valid = RegNext(mem_cp_valid, false.B)\n val mem_reg_valid = RegInit(false.B)\n val killm = (io.killm || io.nack_mem) && !mem_cp_valid\n // Kill X-stage instruction if M-stage is killed. This prevents it from\n // speculatively being sent to the div-sqrt unit, which can cause priority\n // inversion for two back-to-back divides, the first of which is killed.\n val killx = io.killx || mem_reg_valid && killm\n mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid\n val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)\n val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)\n\n val cp_ctrl = Wire(new FPUCtrlSigs)\n cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)\n io.cp_resp.valid := false.B\n io.cp_resp.bits.data := 0.U\n io.cp_resp.bits.exc := DontCare\n\n val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)\n val mem_ctrl = RegEnable(ex_ctrl, req_valid)\n val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)\n\n // CoreMonitorBundle to monitor fp register file writes\n val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))\n frfWriteBundle.foreach { i =>\n i.clock := clock\n i.reset := reset\n i.hartid := io.hartid\n i.timer := io.time(31,0)\n i.valid := false.B\n i.wrenx := false.B\n i.wrenf := false.B\n i.excpt := false.B\n }\n\n // regfile\n val regfile = Mem(32, Bits((fLen+1).W))\n when (load_wb) {\n val wdata = recode(load_wb_data, load_wb_typeTag)\n regfile(load_wb_tag) := wdata\n assert(consistent(wdata))\n if (enableCommitLog)\n printf(\"f%d p%d 0x%x\\n\", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))\n if (useDebugROB)\n DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))\n frfWriteBundle(0).wrdst := load_wb_tag\n frfWriteBundle(0).wrenf := true.B\n frfWriteBundle(0).wrdata := ieee(wdata)\n }\n\n val ex_rs = ex_ra.map(a => regfile(a))\n when (io.valid) {\n when (id_ctrl.ren1) {\n when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }\n when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }\n }\n when (id_ctrl.ren2) {\n when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }\n when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }\n when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }\n }\n when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }\n }\n val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))\n\n def fuInput(minT: Option[FType]): FPInput = {\n val req = Wire(new FPInput)\n val tag = ex_ctrl.typeTagIn\n req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)\n req.rm := ex_rm\n req.in1 := unbox(ex_rs(0), tag, minT)\n req.in2 := unbox(ex_rs(1), tag, minT)\n req.in3 := unbox(ex_rs(2), tag, minT)\n req.typ := ex_reg_inst(21,20)\n req.fmt := ex_reg_inst(26,25)\n req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))\n when (ex_cp_valid) {\n req := io.cp_req.bits\n when (io.cp_req.bits.swap12) {\n req.in1 := io.cp_req.bits.in2\n req.in2 := io.cp_req.bits.in1\n }\n when (io.cp_req.bits.swap23) {\n req.in2 := io.cp_req.bits.in3\n req.in3 := io.cp_req.bits.in2\n }\n }\n req\n }\n\n val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))\n sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S\n sfma.io.in.bits := fuInput(Some(sfma.t))\n\n val fpiu = Module(new FPToInt)\n fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))\n fpiu.io.in.bits := fuInput(None)\n io.store_data := fpiu.io.out.bits.store\n io.toint_data := fpiu.io.out.bits.toint\n when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){\n io.cp_resp.bits.data := fpiu.io.out.bits.toint\n io.cp_resp.valid := true.B\n }\n\n val ifpu = Module(new IntToFP(cfg.ifpuLatency))\n ifpu.io.in.valid := req_valid && ex_ctrl.fromint\n ifpu.io.in.bits := fpiu.io.in.bits\n ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)\n\n val fpmu = Module(new FPToFP(cfg.fpmuLatency))\n fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe\n fpmu.io.in.bits := fpiu.io.in.bits\n fpmu.io.lt := fpiu.io.out.bits.lt\n\n val divSqrt_wen = WireDefault(false.B)\n val divSqrt_inFlight = WireDefault(false.B)\n val divSqrt_waddr = Reg(UInt(5.W))\n val divSqrt_cp = Reg(Bool())\n val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))\n val divSqrt_wdata = Wire(UInt((fLen+1).W))\n val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))\n divSqrt_typeTag := DontCare\n divSqrt_wdata := DontCare\n divSqrt_flags := DontCare\n // writeback arbitration\n case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)\n val pipes = List(\n Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),\n Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),\n Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++\n (fLen > 32).option({\n val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))\n dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D\n dfma.io.in.bits := fuInput(Some(dfma.t))\n Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)\n }) ++\n (minFLen == 16).option({\n val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))\n hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H\n hfma.io.in.bits := fuInput(Some(hfma.t))\n Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)\n })\n def latencyMask(c: FPUCtrlSigs, offset: Int) = {\n require(pipes.forall(_.lat >= offset))\n pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)\n }\n def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)\n val maxLatency = pipes.map(_.lat).max\n val memLatencyMask = latencyMask(mem_ctrl, 2)\n\n class WBInfo extends Bundle {\n val rd = UInt(5.W)\n val typeTag = UInt(log2Up(floatTypes.size).W)\n val cp = Bool()\n val pipeid = UInt(log2Ceil(pipes.size).W)\n }\n\n val wen = RegInit(0.U((maxLatency-1).W))\n val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))\n val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)\n val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)\n ccover(mem_reg_valid && write_port_busy, \"WB_STRUCTURAL\", \"structural hazard on writeback\")\n\n for (i <- 0 until maxLatency-2) {\n when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }\n }\n wen := wen >> 1\n when (mem_wen) {\n when (!killm) {\n wen := wen >> 1 | memLatencyMask\n }\n for (i <- 0 until maxLatency-1) {\n when (!write_port_busy && memLatencyMask(i)) {\n wbInfo(i).cp := mem_cp_valid\n wbInfo(i).typeTag := mem_ctrl.typeTagOut\n wbInfo(i).pipeid := pipeid(mem_ctrl)\n wbInfo(i).rd := mem_reg_inst(11,7)\n }\n }\n }\n\n val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)\n val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)\n val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)\n val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)\n val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)\n when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {\n assert(consistent(wdata))\n regfile(waddr) := wdata\n if (enableCommitLog) {\n printf(\"f%d p%d 0x%x\\n\", waddr, waddr + 32.U, ieee(wdata))\n }\n frfWriteBundle(1).wrdst := waddr\n frfWriteBundle(1).wrenf := true.B\n frfWriteBundle(1).wrdata := ieee(wdata)\n }\n if (useDebugROB) {\n DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))\n }\n\n when (wb_cp && (wen(0) || divSqrt_wen)) {\n io.cp_resp.bits.data := wdata\n io.cp_resp.valid := true.B\n }\n\n assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n s\"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}\")\n // Avoid structural hazards and nacking of external requests\n // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs\n io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight\n\n val wb_toint_valid = wb_reg_valid && wb_ctrl.toint\n val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)\n io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)\n io.fcsr_flags.bits :=\n Mux(wb_toint_valid, wb_toint_exc, 0.U) |\n Mux(divSqrt_wen, divSqrt_flags, 0.U) |\n Mux(wen(0), wexc, 0.U)\n\n val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR\n io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)\n io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid\n io.dec <> id_ctrl\n def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)\n io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)\n io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))\n io.sboard_clra := waddr\n ccover(io.sboard_clr && load_wb, \"DUAL_WRITEBACK\", \"load and FMA writeback on same cycle\")\n // we don't currently support round-max-magnitude (rm=4)\n io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U\n\n if (cfg.divSqrt) {\n val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight\n val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)\n when (divSqrt_inValid) {\n divSqrt_waddr := mem_reg_inst(11,7)\n divSqrt_cp := mem_cp_valid\n }\n\n ccover(divSqrt_inFlight && divSqrt_killed, \"DIV_KILLED\", \"divide killed after issued to divider\")\n ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), \"DIV_BUSY\", \"divider structural hazard\")\n ccover(mem_reg_valid && divSqrt_write_port_busy, \"DIV_WB_STRUCTURAL\", \"structural hazard on division writeback\")\n\n for (t <- floatTypes) {\n val tag = mem_ctrl.typeTagOut\n val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }\n divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U\n divSqrt.io.sqrtOp := mem_ctrl.sqrt\n divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)\n divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)\n divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm\n divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding\n\n when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight\n\n when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {\n divSqrt_wen := !divSqrt_killed\n divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)\n divSqrt_flags := divSqrt.io.exceptionFlags\n divSqrt_typeTag := typeTag(t).U\n }\n }\n\n when (divSqrt_killed) { divSqrt_inFlight := false.B }\n } else {\n when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }\n }\n\n // gate the clock\n clock_en_reg := !useClockGating.B ||\n io.keep_clock_enabled || // chicken bit\n io.valid || // ID stage\n req_valid || // EX stage\n mem_reg_valid || mem_cp_valid || // MEM stage\n wb_reg_valid || wb_cp_valid || // WB stage\n wen.orR || divSqrt_inFlight || // post-WB stage\n io.ll_resp_val // load writeback\n\n } // leaving gated-clock domain\n val fpuImpl = withClock (gated_clock) { new FPUImpl }\n\n def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =\n property.cover(cond, s\"FPU_$label\", \"Core;;\" + desc)\n}", + "response": "module MulAddRecFNPipe_l2_e5_s11(\n input clock,\n input reset,\n input io_validin,\n input [1:0] io_op,\n input [16:0] io_a,\n input [16:0] io_b,\n input [16:0] io_c,\n input [2:0] io_roundingMode,\n output [16:0] io_out,\n output [4:0] io_exceptionFlags\n);\n\n wire _mulAddRecFNToRaw_postMul_io_invalidExc;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n wire _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n wire [6:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n wire [13:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddA;\n wire [10:0] _mulAddRecFNToRaw_preMul_io_mulAddB;\n wire [21:0] _mulAddRecFNToRaw_preMul_io_mulAddC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n wire [6:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n wire [3:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC;\n reg [6:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant;\n reg [3:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist;\n reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC;\n reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC;\n reg [22:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b;\n reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b;\n reg [2:0] roundingMode_stage0_pipe_b;\n reg valid_stage0_pipe_v;\n reg roundRawFNToRecFN_io_invalidExc_pipe_b;\n reg roundRawFNToRecFN_io_in_pipe_b_isNaN;\n reg roundRawFNToRecFN_io_in_pipe_b_isInf;\n reg roundRawFNToRecFN_io_in_pipe_b_isZero;\n reg roundRawFNToRecFN_io_in_pipe_b_sign;\n reg [6:0] roundRawFNToRecFN_io_in_pipe_b_sExp;\n reg [13:0] roundRawFNToRecFN_io_in_pipe_b_sig;\n reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b;\n always @(posedge clock) begin\n if (io_validin) begin\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC;\n mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC;\n mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= {1'h0, {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {11'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC};\n mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode;\n roundingMode_stage0_pipe_b <= io_roundingMode;\n end\n if (valid_stage0_pipe_v) begin\n roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc;\n roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN;\n roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf;\n roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero;\n roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign;\n roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp;\n roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig;\n roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0_pipe_b;\n end\n if (reset)\n valid_stage0_pipe_v <= 1'h0;\n else\n valid_stage0_pipe_v <= io_validin;\n end\n MulAddRecFNToRaw_preMul_e5_s11 mulAddRecFNToRaw_preMul (\n .io_op (io_op),\n .io_a (io_a),\n .io_b (io_b),\n .io_c (io_c),\n .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),\n .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),\n .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),\n .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),\n .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),\n .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),\n .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),\n .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),\n .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),\n .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),\n .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),\n .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),\n .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),\n .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),\n .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),\n .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),\n .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),\n .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),\n .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)\n );\n MulAddRecFNToRaw_postMul_e5_s11 mulAddRecFNToRaw_postMul (\n .io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny),\n .io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB),\n .io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA),\n .io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA),\n .io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB),\n .io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB),\n .io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd),\n .io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC),\n .io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC),\n .io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC),\n .io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum),\n .io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags),\n .io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant),\n .io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist),\n .io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC),\n .io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC),\n .io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b),\n .io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b),\n .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),\n .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),\n .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),\n .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),\n .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),\n .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),\n .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)\n );\n RoundRawFNToRecFN_e5_s11 roundRawFNToRecFN (\n .io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_b),\n .io_infiniteExc (1'h0),\n .io_in_isNaN (roundRawFNToRecFN_io_in_pipe_b_isNaN),\n .io_in_isInf (roundRawFNToRecFN_io_in_pipe_b_isInf),\n .io_in_isZero (roundRawFNToRecFN_io_in_pipe_b_isZero),\n .io_in_sign (roundRawFNToRecFN_io_in_pipe_b_sign),\n .io_in_sExp (roundRawFNToRecFN_io_in_pipe_b_sExp),\n .io_in_sig (roundRawFNToRecFN_io_in_pipe_b_sig),\n .io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_b),\n .io_out (io_out),\n .io_exceptionFlags (io_exceptionFlags)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix}\n\nimport scala.math.min\n\ncase class BoomBTBParams(\n nSets: Int = 128,\n nWays: Int = 2,\n offsetSz: Int = 13,\n extendedNSets: Int = 128\n)\n\n\nclass BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n override val nSets = params.nSets\n override val nWays = params.nWays\n val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1\n val offsetSz = params.offsetSz\n val extendedNSets = params.extendedNSets\n\n require(isPow2(nSets))\n require(isPow2(extendedNSets) || extendedNSets == 0)\n require(extendedNSets <= nSets)\n require(extendedNSets >= 1)\n\n class BTBEntry extends Bundle {\n val offset = SInt(offsetSz.W)\n val extended = Bool()\n }\n val btbEntrySz = offsetSz + 1\n\n class BTBMeta extends Bundle {\n val is_br = Bool()\n val tag = UInt(tagSz.W)\n }\n val btbMetaSz = tagSz + 1\n\n class BTBPredictMeta extends Bundle {\n val write_way = UInt(log2Ceil(nWays).W)\n }\n\n val s1_meta = Wire(new BTBPredictMeta)\n val f3_meta = RegNext(RegNext(s1_meta))\n\n\n io.f3_meta := f3_meta.asUInt\n\n override val metaSz = s1_meta.asUInt.getWidth\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nSets).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nSets-1).U) { doing_reset := false.B }\n\n val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) }\n val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) }\n val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))\n\n val mems = (((0 until nWays) map ({w:Int => Seq(\n (f\"btb_meta_way$w\", nSets, bankWidth * btbMetaSz),\n (f\"btb_data_way$w\", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq((\"ebtb\", extendedNSets, vaddrBitsExtended)))\n\n val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) })\n val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) })\n val s1_req_rebtb = ebtb.read(s0_idx, s0_valid)\n val s1_req_tag = s1_idx >> log2Ceil(nSets)\n\n val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))\n val s1_is_br = Wire(Vec(bankWidth, Bool()))\n val s1_is_jal = Wire(Vec(bankWidth, Bool()))\n\n val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>\n VecInit((0 until nWays) map { w =>\n s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)\n })\n })\n val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }\n val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }\n\n for (w <- 0 until bankWidth) {\n val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)\n val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w)\n s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)\n s1_resp(w).bits := Mux(\n entry_btb.extended,\n s1_req_rebtb,\n (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)\n s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br\n s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br\n\n\n io.resp.f2(w) := io.resp_in(0).f2(w)\n io.resp.f3(w) := io.resp_in(0).f3(w)\n when (RegNext(s1_hits(w))) {\n io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))\n io.resp.f2(w).is_br := RegNext(s1_is_br(w))\n io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))\n when (RegNext(s1_is_jal(w))) {\n io.resp.f2(w).taken := true.B\n }\n }\n when (RegNext(RegNext(s1_hits(w)))) {\n io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)\n io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)\n io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)\n when (RegNext(RegNext(s1_is_jal(w)))) {\n io.resp.f3(w).taken := true.B\n }\n }\n }\n\n val alloc_way = if (nWays > 1) {\n val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))\n val l = log2Ceil(nWays)\n val nChunks = (r_metas.getWidth + l - 1) / l\n val chunks = (0 until nChunks) map { i =>\n r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)\n }\n chunks.reduce(_^_)\n } else {\n 0.U\n }\n s1_meta.write_way := Mux(s1_hits.reduce(_||_),\n PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),\n alloc_way)\n\n val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)\n\n val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt\n val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt\n val new_offset_value = (s1_update.bits.target.asSInt -\n (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)\n val offset_is_extended = (new_offset_value > max_offset_value ||\n new_offset_value < min_offset_value)\n\n\n val s1_update_wbtb_data = Wire(new BTBEntry)\n s1_update_wbtb_data.extended := offset_is_extended\n s1_update_wbtb_data.offset := new_offset_value\n val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &\n Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))\n\n val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &\n (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |\n (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)\n )\n )\n val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))\n\n for (w <- 0 until bankWidth) {\n s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))\n s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)\n }\n\n for (w <- 0 until nWays) {\n when (doing_reset || s1_update_meta.write_way === w.U || (w == 0 && nWays == 1).B) {\n btb(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),\n VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wbtb_mask).asBools\n )\n meta(w).write(\n Mux(doing_reset,\n reset_idx,\n s1_update_idx),\n Mux(doing_reset,\n VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),\n VecInit(s1_update_wmeta_data.map(_.asUInt))),\n Mux(doing_reset,\n (~(0.U(bankWidth.W))),\n s1_update_wmeta_mask).asBools\n )\n\n\n }\n }\n when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {\n ebtb.write(s1_update_idx, s1_update.bits.target)\n }\n\n}", + "response": "module btb_0(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [55:0] R0_data,\n input [6:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [55:0] W0_data,\n input [3:0] W0_mask\n);\n\n btb_0_ext btb_0_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (W0_en),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.diplomacy._\nimport org.chipsalliance.cde.config._\n\nclass GenericSerializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericSerializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(t))\n val out = Decoupled(new Flit(flitWidth))\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.flit := Mux(beat === 0.U, io.in.bits.asUInt, data(beat))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(flitWidth.W)))\n data(0) := DontCare // unused, DCE this\n }\n }\n\n io.busy := io.out.valid\n}\n\nclass GenericDeserializer[T <: Data](t: T, flitWidth: Int) extends Module {\n override def desiredName = s\"GenericDeserializer_${t.typeName}w${t.getWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(t)\n val busy = Output(Bool())\n })\n\n val dataBits = t.getWidth.max(flitWidth)\n val dataBeats = (dataBits - 1) / flitWidth + 1\n require(dataBeats >= 1)\n val data = Reg(Vec(dataBeats-1, UInt(flitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits := (if (dataBeats == 1) {\n io.in.bits.flit.asTypeOf(t)\n } else {\n Cat(io.in.bits.flit, data.asUInt).asTypeOf(t)\n })\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat(log2Ceil(dataBeats-1)-1,0)) := io.in.bits.flit\n }\n }\n }\n\n io.busy := beat =/= 0.U\n}\n\nclass FlitToPhit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"FlitToPhit_f${flitWidth}_p${phitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Phit(phitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready && beat === 0.U\n io.out.valid := io.in.valid || beat =/= 0.U\n io.out.bits.phit := (if (dataBeats == 1) io.in.bits.flit else Mux(beat === 0.U, io.in.bits.flit, data(beat-1.U)))\n\n when (io.out.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) {\n data := io.in.bits.asTypeOf(Vec(dataBeats, UInt(phitWidth.W))).tail\n }\n }\n}\n\nobject FlitToPhit {\n def apply(flit: DecoupledIO[Flit], phitWidth: Int): DecoupledIO[Phit] = {\n val flit2phit = Module(new FlitToPhit(flit.bits.flitWidth, phitWidth))\n flit2phit.io.in <> flit\n flit2phit.io.out\n }\n}\n\nclass PhitToFlit(flitWidth: Int, phitWidth: Int) extends Module {\n override def desiredName = s\"PhitToFlit_p${phitWidth}_f${flitWidth}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n })\n require(flitWidth >= phitWidth)\n\n val dataBeats = (flitWidth - 1) / phitWidth + 1\n val data = Reg(Vec(dataBeats-1, UInt(phitWidth.W)))\n val beat = RegInit(0.U(log2Ceil(dataBeats).W))\n\n io.in.ready := io.out.ready || beat =/= (dataBeats-1).U\n io.out.valid := io.in.valid && beat === (dataBeats-1).U\n io.out.bits.flit := (if (dataBeats == 1) io.in.bits.phit else Cat(io.in.bits.phit, data.asUInt))\n\n when (io.in.fire) {\n beat := Mux(beat === (dataBeats-1).U, 0.U, beat + 1.U)\n if (dataBeats > 1) {\n when (beat =/= (dataBeats-1).U) {\n data(beat) := io.in.bits.phit\n }\n }\n }\n}\n\nobject PhitToFlit {\n def apply(phit: DecoupledIO[Phit], flitWidth: Int): DecoupledIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in <> phit\n phit2flit.io.out\n }\n def apply(phit: ValidIO[Phit], flitWidth: Int): ValidIO[Flit] = {\n val phit2flit = Module(new PhitToFlit(flitWidth, phit.bits.phitWidth))\n phit2flit.io.in.valid := phit.valid\n phit2flit.io.in.bits := phit.bits\n when (phit.valid) { assert(phit2flit.io.in.ready) }\n val out = Wire(Valid(new Flit(flitWidth)))\n out.valid := phit2flit.io.out.valid\n out.bits := phit2flit.io.out.bits\n phit2flit.io.out.ready := true.B\n out\n }\n}\n\nclass PhitArbiter(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitArbiter_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Vec(channels, Decoupled(new Phit(phitWidth))))\n val out = Decoupled(new Phit(phitWidth))\n })\n if (channels == 1) {\n io.out <> io.in(0)\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val chosen_reg = Reg(UInt(headerWidth.W))\n val chosen_prio = PriorityEncoder(io.in.map(_.valid))\n val chosen = Mux(beat === 0.U, chosen_prio, chosen_reg)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.out.valid := VecInit(io.in.map(_.valid))(chosen)\n io.out.bits.phit := Mux(beat < headerBeats.U,\n chosen.asTypeOf(Vec(headerBeats, UInt(phitWidth.W)))(header_idx),\n VecInit(io.in.map(_.bits.phit))(chosen))\n\n for (i <- 0 until channels) {\n io.in(i).ready := io.out.ready && beat >= headerBeats.U && chosen_reg === i.U\n }\n\n when (io.out.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat === 0.U) { chosen_reg := chosen_prio }\n }\n }\n}\n\nclass PhitDemux(phitWidth: Int, flitWidth: Int, channels: Int) extends Module {\n override def desiredName = s\"PhitDemux_p${phitWidth}_f${flitWidth}_n${channels}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Phit(phitWidth)))\n val out = Vec(channels, Decoupled(new Phit(phitWidth)))\n })\n if (channels == 1) {\n io.out(0) <> io.in\n } else {\n val headerWidth = log2Ceil(channels)\n val headerBeats = (headerWidth - 1) / phitWidth + 1\n val flitBeats = (flitWidth - 1) / phitWidth + 1\n val beats = headerBeats + flitBeats\n val beat = RegInit(0.U(log2Ceil(beats).W))\n val channel_vec = Reg(Vec(headerBeats, UInt(phitWidth.W)))\n val channel = channel_vec.asUInt(log2Ceil(channels)-1,0)\n val header_idx = if (headerBeats == 1) 0.U else beat(log2Ceil(headerBeats)-1,0)\n\n io.in.ready := beat < headerBeats.U || VecInit(io.out.map(_.ready))(channel)\n for (c <- 0 until channels) {\n io.out(c).valid := io.in.valid && beat >= headerBeats.U && channel === c.U\n io.out(c).bits.phit := io.in.bits.phit\n }\n\n when (io.in.fire) {\n beat := Mux(beat === (beats-1).U, 0.U, beat + 1.U)\n when (beat < headerBeats.U) {\n channel_vec(header_idx) := io.in.bits.phit\n }\n }\n }\n}\n\nclass DecoupledFlitToCreditedFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"DecoupledFlitToCreditedFlit_f${flitWidth}_b${bufferSz}\"\n\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Flipped(Decoupled(new Flit(flitWidth)))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = io.out.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credits + credit_incr - Mux(io.credit.valid, io.credit.bits.flit +& 1.U, 0.U)\n }\n\n io.out.valid := io.in.valid && credits < bufferSz.U\n io.out.bits.flit := io.in.bits.flit\n io.in.ready := io.out.ready && credits < bufferSz.U\n\n io.credit.ready := true.B\n}\n\nclass CreditedFlitToDecoupledFlit(flitWidth: Int, bufferSz: Int) extends Module {\n override def desiredName = s\"CreditedFlitToDecoupledFlit_f${flitWidth}_b${bufferSz}\"\n val io = IO(new Bundle {\n val in = Flipped(Decoupled(new Flit(flitWidth)))\n val out = Decoupled(new Flit(flitWidth))\n val credit = Decoupled(new Flit(flitWidth))\n })\n val creditWidth = log2Ceil(bufferSz)\n require(creditWidth <= flitWidth)\n val buffer = Module(new Queue(new Flit(flitWidth), bufferSz))\n val credits = RegInit(0.U((creditWidth+1).W))\n val credit_incr = buffer.io.deq.fire\n val credit_decr = io.credit.fire\n when (credit_incr || credit_decr) {\n credits := credit_incr + Mux(credit_decr, 0.U, credits)\n }\n\n buffer.io.enq.valid := io.in.valid\n buffer.io.enq.bits := io.in.bits\n io.in.ready := true.B\n when (io.in.valid) { assert(buffer.io.enq.ready) }\n\n io.out <> buffer.io.deq\n\n io.credit.valid := credits =/= 0.U\n io.credit.bits.flit := credits - 1.U\n}", + "response": "module PhitDemux_p32_f32_n5(\n input clock,\n input reset,\n output io_in_ready,\n input io_in_valid,\n input [31:0] io_in_bits_phit,\n input io_out_0_ready,\n output io_out_0_valid,\n output [31:0] io_out_0_bits_phit,\n input io_out_1_ready,\n output io_out_1_valid,\n output [31:0] io_out_1_bits_phit,\n input io_out_2_ready,\n output io_out_2_valid,\n output [31:0] io_out_2_bits_phit,\n input io_out_3_ready,\n output io_out_3_valid,\n output [31:0] io_out_3_bits_phit,\n input io_out_4_ready,\n output io_out_4_valid,\n output [31:0] io_out_4_bits_phit\n);\n\n reg beat;\n reg [31:0] channel_vec_0;\n wire [7:0] _GEN = {{io_out_0_ready}, {io_out_0_ready}, {io_out_0_ready}, {io_out_4_ready}, {io_out_3_ready}, {io_out_2_ready}, {io_out_1_ready}, {io_out_0_ready}};\n wire io_in_ready_0 = ~beat | _GEN[channel_vec_0[2:0]];\n wire _GEN_0 = io_in_ready_0 & io_in_valid;\n always @(posedge clock) begin\n if (reset)\n beat <= 1'h0;\n else if (_GEN_0)\n beat <= ~beat & beat - 1'h1;\n if (_GEN_0 & ~beat)\n channel_vec_0 <= io_in_bits_phit;\n end\n assign io_in_ready = io_in_ready_0;\n assign io_out_0_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h0;\n assign io_out_0_bits_phit = io_in_bits_phit;\n assign io_out_1_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h1;\n assign io_out_1_bits_phit = io_in_bits_phit;\n assign io_out_2_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h2;\n assign io_out_2_bits_phit = io_in_bits_phit;\n assign io_out_3_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h3;\n assign io_out_3_bits_phit = io_in_bits_phit;\n assign io_out_4_valid = io_in_valid & beat & channel_vec_0[2:0] == 3'h4;\n assign io_out_4_bits_phit = io_in_bits_phit;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip\n\nimport chisel3._\nimport chisel3.util._\nimport scala.math.min\nimport scala.collection.{immutable, mutable}\n\npackage object util {\n implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {\n def unzip = (x.map(_._1), x.map(_._2))\n }\n\n implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {\n def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR\n \n def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)\n }\n\n implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {\n\n /** Like Vec.apply(idx), but tolerates indices of mismatched width */\n def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))\n }\n\n implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {\n def apply(idx: UInt): T = {\n if (x.size <= 1) {\n x.head\n } else if (!isPow2(x.size)) {\n // For non-power-of-2 seqs, reflect elements to simplify decoder\n (x ++ x.takeRight(x.size & -x.size)).toSeq(idx)\n } else {\n // Ignore MSBs of idx\n val truncIdx =\n if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx\n else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)\n x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }\n }\n }\n\n def extract(idx: UInt): T = VecInit(x).extract(idx)\n\n def asUInt: UInt = Cat(x.map(_.asUInt).reverse)\n\n def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)\n\n def rotate(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n\n def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)\n\n def rotateRight(n: UInt): Seq[T] = {\n if (x.size <= 1) {\n x\n } else {\n require(isPow2(x.size))\n val amt = n.padTo(log2Ceil(x.size))\n (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })\n }\n }\n }\n\n // allow bitwise ops on Seq[Bool] just like UInt\n implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {\n def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }\n def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }\n def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }\n def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x\n def >> (n: Int): Seq[Bool] = x drop n\n def unary_~ : Seq[Bool] = x.map(!_)\n def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)\n def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)\n def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)\n\n private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)\n }\n\n implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {\n def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))\n\n def getElements: Seq[Element] = x match {\n case e: Element => Seq(e)\n case a: Aggregate => a.getElements.flatMap(_.getElements)\n }\n }\n\n /** Any Data subtype that has a Bool member named valid. */\n type DataCanBeValid = Data { val valid: Bool }\n\n implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {\n def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)\n }\n\n implicit class StringToAugmentedString(private val x: String) extends AnyVal {\n /** converts from camel case to to underscores, also removing all spaces */\n def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + \"\") getOrElse \"\") {\n case (acc, c) if c.isUpper => acc + \"_\" + c.toLower\n case (acc, c) if c == ' ' => acc\n case (acc, c) => acc + c\n }\n\n /** converts spaces or underscores to hyphens, also lowering case */\n def kebab: String = x.toLowerCase map {\n case ' ' => '-'\n case '_' => '-'\n case c => c\n }\n\n def named(name: Option[String]): String = {\n x + name.map(\"_named_\" + _ ).getOrElse(\"_with_no_name\")\n }\n\n def named(name: String): String = named(Some(name))\n }\n\n implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)\n implicit def wcToUInt(c: WideCounter): UInt = c.value\n\n implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {\n def sextTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)\n }\n\n def padTo(n: Int): UInt = {\n require(x.getWidth <= n)\n if (x.getWidth == n) x\n else Cat(0.U((n - x.getWidth).W), x)\n }\n\n // shifts left by n if n >= 0, or right by -n if n < 0\n def << (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << n(w-1, 0)\n Mux(n(w), shifted >> (1 << w), shifted)\n }\n\n // shifts right by n if n >= 0, or left by -n if n < 0\n def >> (n: SInt): UInt = {\n val w = n.getWidth - 1\n require(w <= 30)\n\n val shifted = x << (1 << w) >> n(w-1, 0)\n Mux(n(w), shifted, shifted >> (1 << w))\n }\n\n // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts\n def extract(hi: Int, lo: Int): UInt = {\n require(hi >= lo-1)\n if (hi == lo-1) 0.U\n else x(hi, lo)\n }\n\n // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts\n def extractOption(hi: Int, lo: Int): Option[UInt] = {\n require(hi >= lo-1)\n if (hi == lo-1) None\n else Some(x(hi, lo))\n }\n\n // like x & ~y, but first truncate or zero-extend y to x's width\n def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))\n\n def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)\n\n def rotateRight(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))\n }\n }\n\n def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))\n\n def rotateLeft(n: UInt): UInt = {\n if (x.getWidth <= 1) {\n x\n } else {\n val amt = n.padTo(log2Ceil(x.getWidth))\n (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))\n }\n }\n\n // compute (this + y) % n, given (this < n) and (y < n)\n def addWrap(y: UInt, n: Int): UInt = {\n val z = x +& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)\n }\n\n // compute (this - y) % n, given (this < n) and (y < n)\n def subWrap(y: UInt, n: Int): UInt = {\n val z = x -& y\n if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)\n }\n\n def grouped(width: Int): Seq[UInt] =\n (0 until x.getWidth by width).map(base => x(base + width - 1, base))\n\n def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds\n\n def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)\n\n // Like >=, but prevents x-prop for ('x >= 0)\n def >== (y: UInt): Bool = x >= y || y === 0.U\n }\n\n implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {\n def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)\n def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)\n }\n\n implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {\n def toInt: Int = if (x) 1 else 0\n\n // this one's snagged from scalaz\n def option[T](z: => T): Option[T] = if (x) Some(z) else None\n }\n\n implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {\n // exact log2\n def log2: Int = {\n require(isPow2(x))\n log2Ceil(x)\n }\n }\n\n def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)\n def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))\n def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)\n def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)\n\n def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None\n\n // Fill 1s from low bits to high bits\n def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)\n def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))\n helper(1, x)(width-1, 0)\n }\n\n // Fill 1s form high bits to low bits\n def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)\n def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {\n val stop = min(width, cap)\n def helper(s: Int, x: UInt): UInt =\n if (s >= stop) x else helper(s+s, x | (x >> s))\n helper(1, x)(width-1, 0)\n }\n\n def OptimizationBarrier[T <: Data](in: T): T = {\n val barrier = Module(new Module {\n val io = IO(new Bundle {\n val x = Input(chiselTypeOf(in))\n val y = Output(chiselTypeOf(in))\n })\n io.y := io.x\n override def desiredName = s\"OptimizationBarrier_${in.typeName}\"\n })\n barrier.io.x := in\n barrier.io.y\n }\n\n /** Similar to Seq.groupBy except this returns a Seq instead of a Map\n * Useful for deterministic code generation\n */\n def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {\n val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]\n for (x <- xs) {\n val key = f(x)\n val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])\n l += x\n }\n map.view.map({ case (k, vs) => k -> vs.toList }).toList\n }\n\n def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {\n case 1 => List.fill(n)(in.head)\n case x if x == n => in\n case _ => throw new Exception(s\"must provide exactly 1 or $n of some field, but got:\\n$in\")\n }\n\n // HeterogeneousBag moved to standalond diplomacy\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)\n @deprecated(\"HeterogeneousBag has been absorbed into standalone diplomacy library\", \"rocketchip 2.0.0\")\n val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag\n}", + "response": "module OptimizationBarrier_UInt(\n input [2:0] io_x,\n output [2:0] io_y\n);\n\n assign io_y = io_x;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package boom.v3.ifu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.{Field, Parameters}\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\n\nimport boom.v3.common._\nimport boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc}\n\nimport scala.math.min\n\n\n\n\n\nclass TageResp extends Bundle {\n val ctr = UInt(3.W)\n val u = UInt(2.W)\n}\n\nclass TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int)\n (implicit p: Parameters) extends BoomModule()(p)\n with HasBoomFrontendParameters\n{\n require(histLength <= globalHistoryLength)\n\n val nWrBypassEntries = 2\n val io = IO( new Bundle {\n val f1_req_valid = Input(Bool())\n val f1_req_pc = Input(UInt(vaddrBitsExtended.W))\n val f1_req_ghist = Input(UInt(globalHistoryLength.W))\n\n val f3_resp = Output(Vec(bankWidth, Valid(new TageResp)))\n\n val update_mask = Input(Vec(bankWidth, Bool()))\n val update_taken = Input(Vec(bankWidth, Bool()))\n val update_alloc = Input(Vec(bankWidth, Bool()))\n val update_old_ctr = Input(Vec(bankWidth, UInt(3.W)))\n\n val update_pc = Input(UInt())\n val update_hist = Input(UInt())\n\n val update_u_mask = Input(Vec(bankWidth, Bool()))\n val update_u = Input(Vec(bankWidth, UInt(2.W)))\n })\n\n def compute_folded_hist(hist: UInt, l: Int) = {\n val nChunks = (histLength + l - 1) / l\n val hist_chunks = (0 until nChunks) map {i =>\n hist(min((i+1)*l, histLength)-1, i*l)\n }\n hist_chunks.reduce(_^_)\n }\n\n def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = {\n val idx_history = compute_folded_hist(hist, log2Ceil(nRows))\n val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0)\n val tag_history = compute_folded_hist(hist, tagSz)\n val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0)\n (idx, tag)\n }\n\n def inc_ctr(ctr: UInt, taken: Bool): UInt = {\n Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U),\n Mux(ctr === 7.U, 7.U, ctr + 1.U))\n }\n\n\n val doing_reset = RegInit(true.B)\n val reset_idx = RegInit(0.U(log2Ceil(nRows).W))\n reset_idx := reset_idx + doing_reset\n when (reset_idx === (nRows-1).U) { doing_reset := false.B }\n\n\n class TageEntry extends Bundle {\n val valid = Bool() // TODO: Remove this valid bit\n val tag = UInt(tagSz.W)\n val ctr = UInt(3.W)\n }\n\n\n val tageEntrySz = 1 + tagSz + 3\n\n val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist)\n\n val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool()))\n val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W)))\n\n val mems = Seq((f\"tage_l$histLength\", nRows, bankWidth * tageEntrySz))\n\n val s2_tag = RegNext(s1_tag)\n\n val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry)))\n val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid)\n val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset))\n\n for (w <- 0 until bankWidth) {\n // This bit indicates the TAGE table matched here\n io.f3_resp(w).valid := RegNext(s2_req_rhits(w))\n io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w)))\n io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr)\n }\n\n val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W))\n when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U }\n\n val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U\n val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U\n val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U\n val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod)\n\n val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist)\n\n val update_wdata = Wire(Vec(bankWidth, new TageEntry))\n\n table.write(\n Mux(doing_reset, reset_idx , update_idx),\n Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))),\n Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools\n )\n\n val update_hi_wdata = Wire(Vec(bankWidth, Bool()))\n hi_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata),\n Mux(doing_reset || doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val update_lo_wdata = Wire(Vec(bankWidth, Bool()))\n lo_us.write(\n Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)),\n Mux(doing_reset || doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata),\n Mux(doing_reset || doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools\n )\n\n val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W)))\n val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W)))\n val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W))))\n val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))\n\n val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>\n !doing_reset &&\n wrbypass_tags(i) === update_tag &&\n wrbypass_idxs(i) === update_idx\n })\n val wrbypass_hit = wrbypass_hits.reduce(_||_)\n val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)\n\n for (w <- 0 until bankWidth) {\n update_wdata(w).ctr := Mux(io.update_alloc(w),\n Mux(io.update_taken(w), 4.U,\n 3.U\n ),\n Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)),\n inc_ctr(io.update_old_ctr(w), io.update_taken(w))\n )\n )\n update_wdata(w).valid := true.B\n update_wdata(w).tag := update_tag\n\n update_hi_wdata(w) := io.update_u(w)(1)\n update_lo_wdata(w) := io.update_u(w)(0)\n }\n\n when (io.update_mask.reduce(_||_)) {\n when (wrbypass_hits.reduce(_||_)) {\n wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr))\n } .otherwise {\n wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr))\n wrbypass_tags(wrbypass_enq_idx) := update_tag\n wrbypass_idxs(wrbypass_enq_idx) := update_idx\n wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)\n }\n }\n\n\n\n}\n\n\ncase class BoomTageParams(\n // nSets, histLen, tagSz\n tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7),\n ( 128, 4, 7),\n ( 256, 8, 8),\n ( 256, 16, 8),\n ( 128, 32, 9),\n ( 128, 64, 9)),\n uBitPeriod: Int = 2048\n)\n\n\nclass TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p)\n{\n val tageUBitPeriod = params.uBitPeriod\n val tageNTables = params.tableInfo.size\n\n class TageMeta extends Bundle\n {\n val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n val alt_differs = Vec(bankWidth, Output(Bool()))\n val provider_u = Vec(bankWidth, Output(UInt(2.W)))\n val provider_ctr = Vec(bankWidth, Output(UInt(3.W)))\n val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W)))\n }\n\n val f3_meta = Wire(new TageMeta)\n override val metaSz = f3_meta.asUInt.getWidth\n require(metaSz <= bpdMaxMetaLength)\n\n def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = {\n Mux(!alt_differs, u,\n Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U),\n Mux(u === 3.U, 3.U, u + 1.U)))\n }\n\n val tt = params.tableInfo map {\n case (n, l, s) => {\n val t = Module(new TageTable(n, s, l, params.uBitPeriod))\n t.io.f1_req_valid := RegNext(io.f0_valid)\n t.io.f1_req_pc := RegNext(io.f0_pc)\n t.io.f1_req_ghist := io.f1_ghist\n (t, t.mems)\n }\n }\n val tables = tt.map(_._1)\n val mems = tt.map(_._2).flatten\n\n val f3_resps = VecInit(tables.map(_.io.f3_resp))\n\n val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta)\n val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) &\n Fill(bankWidth, s1_update.bits.cfi_mispredicted)\n\n val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool()))))\n val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W)))))\n\n val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W))))\n val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool())))\n val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W))))\n\n s1_update_taken := DontCare\n s1_update_old_ctr := DontCare\n s1_update_alloc := DontCare\n s1_update_u := DontCare\n\n\n for (w <- 0 until bankWidth) {\n var altpred = io.resp_in(0).f3(w).taken\n val final_altpred = WireInit(io.resp_in(0).f3(w).taken)\n var provided = false.B\n var provider = 0.U\n io.resp.f3(w).taken := io.resp_in(0).f3(w).taken\n\n for (i <- 0 until tageNTables) {\n val hit = f3_resps(i)(w).valid\n val ctr = f3_resps(i)(w).bits.ctr\n when (hit) {\n io.resp.f3(w).taken := Mux(ctr === 3.U || ctr === 4.U, altpred, ctr(2))\n final_altpred := altpred\n }\n\n provided = provided || hit\n provider = Mux(hit, i.U, provider)\n altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred)\n }\n f3_meta.provider(w).valid := provided\n f3_meta.provider(w).bits := provider\n f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken\n f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u\n f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr\n\n // Create a mask of tables which did not hit our query, and also contain useless entries\n // and also uses a longer history than the provider\n val allocatable_slots = (\n VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt &\n ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided))\n )\n val alloc_lfsr = random.LFSR(tageNTables max 2)\n\n val first_entry = PriorityEncoder(allocatable_slots)\n val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr)\n val alloc_entry = Mux(allocatable_slots(masked_entry),\n masked_entry,\n first_entry)\n\n f3_meta.allocate(w).valid := allocatable_slots =/= 0.U\n f3_meta.allocate(w).bits := alloc_entry\n\n val update_was_taken = (s1_update.bits.cfi_idx.valid &&\n (s1_update.bits.cfi_idx.bits === w.U) &&\n s1_update.bits.cfi_taken)\n when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) {\n when (s1_update_meta.provider(w).valid) {\n val provider = s1_update_meta.provider(w).bits\n\n s1_update_mask(provider)(w) := true.B\n s1_update_u_mask(provider)(w) := true.B\n\n val new_u = inc_u(s1_update_meta.provider_u(w),\n s1_update_meta.alt_differs(w),\n s1_update_mispredict_mask(w))\n s1_update_u (provider)(w) := new_u\n s1_update_taken (provider)(w) := update_was_taken\n s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w)\n s1_update_alloc (provider)(w) := false.B\n\n }\n }\n }\n when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) {\n val idx = s1_update.bits.cfi_idx.bits\n val allocate = s1_update_meta.allocate(idx)\n when (allocate.valid) {\n s1_update_mask (allocate.bits)(idx) := true.B\n s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken\n s1_update_alloc(allocate.bits)(idx) := true.B\n\n s1_update_u_mask(allocate.bits)(idx) := true.B\n s1_update_u (allocate.bits)(idx) := 0.U\n\n } .otherwise {\n val provider = s1_update_meta.provider(idx)\n val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U)\n\n for (i <- 0 until tageNTables) {\n when (decr_mask(i)) {\n s1_update_u_mask(i)(idx) := true.B\n s1_update_u (i)(idx) := 0.U\n }\n }\n }\n\n }\n\n\n for (i <- 0 until tageNTables) {\n for (w <- 0 until bankWidth) {\n tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w))\n tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w))\n tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w))\n tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w))\n\n tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w))\n tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w))\n }\n tables(i).io.update_pc := RegNext(s1_update.bits.pc)\n tables(i).io.update_hist := RegNext(s1_update.bits.ghist)\n }\n\n\n //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0))\n io.f3_meta := f3_meta.asUInt\n}", + "response": "module hi_us_3(\n input [6:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input [6:0] W0_addr,\n input W0_clk,\n input [3:0] W0_data,\n input [3:0] W0_mask\n);\n\n hi_us_ext hi_us_ext (\n .R0_addr (R0_addr),\n .R0_en (R0_en),\n .R0_clk (R0_clk),\n .R0_data (R0_data),\n .W0_addr (W0_addr),\n .W0_en (1'h1),\n .W0_clk (W0_clk),\n .W0_data (W0_data),\n .W0_mask (W0_mask)\n );\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Ported from Rocket-Chip\n// See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details.\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.lsu\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config.Parameters\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.tilelink._\nimport freechips.rocketchip.tile._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.rocket._\n\nimport boom.v3.common._\nimport boom.v3.exu.BrUpdateInfo\nimport boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc}\n\nclass BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p)\n with HasL1HellaCacheParameters\n{\n // miss info\n val tag_match = Bool()\n val old_meta = new L1Metadata\n val way_en = UInt(nWays.W)\n\n // Used in the MSHRs\n val sdq_id = UInt(log2Ceil(cfg.nSDQ).W)\n}\n\n\nclass BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val id = Input(UInt())\n\n val req_pri_val = Input(Bool())\n val req_pri_rdy = Output(Bool())\n val req_sec_val = Input(Bool())\n val req_sec_rdy = Output(Bool())\n\n val clear_prefetch = Input(Bool())\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val req = Input(new BoomDCacheReqInternal)\n val req_is_probe = Input(Bool())\n\n val idx = Output(Valid(UInt()))\n val way = Output(Valid(UInt()))\n val tag = Output(Valid(UInt()))\n\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val refill = Decoupled(new L1DataWriteReq)\n\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n // To inform the prefetcher when we are commiting the fetch of this line\n val commit_val = Output(Bool())\n val commit_addr = Output(UInt(coreMaxAddrBits.W))\n val commit_coh = Output(new ClientMetadata)\n\n // Reading from the line buffer\n val lb_read = Decoupled(new LineBufferReadReq)\n val lb_resp = Input(UInt(encRowBits.W))\n val lb_write = Decoupled(new LineBufferWriteReq)\n\n // Replays go through the cache pipeline again\n val replay = Decoupled(new BoomDCacheReqInternal)\n // Resp go straight out to the core\n val resp = Decoupled(new BoomDCacheResp)\n\n // Writeback unit tells us when it is done processing our wb\n val wb_resp = Input(Bool())\n\n val probe_rdy = Output(Bool())\n })\n\n // TODO: Optimize this. We don't want to mess with cache during speculation\n // s_refill_req : Make a request for a new cache line\n // s_refill_resp : Store the refill response into our buffer\n // s_drain_rpq_loads : Drain out loads from the rpq\n // : If miss was misspeculated, go to s_invalid\n // s_wb_req : Write back the evicted cache line\n // s_wb_resp : Finish writing back the evicted cache line\n // s_meta_write_req : Write the metadata for new cache lne\n // s_meta_write_resp :\n\n val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18)\n val state = RegInit(s_invalid)\n\n val req = Reg(new BoomDCacheReqInternal)\n val req_idx = req.addr(untagBits-1, blockOffBits)\n val req_tag = req.addr >> untagBits\n val req_block_addr = (req.addr >> blockOffBits) << blockOffBits\n val req_needs_wb = RegInit(false.B)\n\n val new_coh = RegInit(ClientMetadata.onReset)\n val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH)\n val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2\n val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param)\n\n // We only accept secondary misses if the original request had sufficient permissions\n val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) =\n new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd)\n\n val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant)\n val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe &&\n !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses\n\n val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false))\n rpq.io.brupdate := io.brupdate\n rpq.io.flush := io.exception\n assert(!(state === s_invalid && !rpq.io.empty))\n\n rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) || (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd)\n rpq.io.enq.bits := io.req\n rpq.io.deq.ready := false.B\n\n\n val grantack = Reg(Valid(new TLBundleE(edge.bundle)))\n val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W))\n val commit_line = Reg(Bool())\n val grant_had_data = Reg(Bool())\n val finish_to_prefetch = Reg(Bool())\n\n // Block probes if a tag write we started is still in the pipeline\n val meta_hazard = RegInit(0.U(2.W))\n when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }\n when (io.meta_write.fire) { meta_hazard := 1.U }\n io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) || (state === s_meta_read && grantack.valid)))\n io.idx.valid := state =/= s_invalid\n io.tag.valid := state =/= s_invalid\n io.way.valid := !state.isOneOf(s_invalid, s_prefetch)\n io.idx.bits := req_idx\n io.tag.bits := req_tag\n io.way.bits := req.way_en\n\n io.meta_write.valid := false.B\n io.meta_write.bits := DontCare\n io.req_pri_rdy := false.B\n io.req_sec_rdy := sec_rdy && rpq.io.enq.ready\n io.mem_acquire.valid := false.B\n io.mem_acquire.bits := DontCare\n io.refill.valid := false.B\n io.refill.bits := DontCare\n io.replay.valid := false.B\n io.replay.bits := DontCare\n io.wb_req.valid := false.B\n io.wb_req.bits := DontCare\n io.resp.valid := false.B\n io.resp.bits := DontCare\n io.commit_val := false.B\n io.commit_addr := req.addr\n io.commit_coh := coh_on_grant\n io.meta_read.valid := false.B\n io.meta_read.bits := DontCare\n io.mem_finish.valid := false.B\n io.mem_finish.bits := DontCare\n io.lb_write.valid := false.B\n io.lb_write.bits := DontCare\n io.lb_read.valid := false.B\n io.lb_read.bits := DontCare\n io.mem_grant.ready := false.B\n\n when (io.req_sec_val && io.req_sec_rdy) {\n req.uop.mem_cmd := dirtier_cmd\n when (is_hit_again) {\n new_coh := dirtier_coh\n }\n }\n\n def handle_pri_req(old_state: UInt): UInt = {\n val new_state = WireInit(old_state)\n grantack.valid := false.B\n refill_ctr := 0.U\n assert(rpq.io.enq.ready)\n req := io.req\n val old_coh = io.req.old_meta.coh\n req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back\n when (io.req.tag_match) {\n val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // set dirty bit\n assert(isWrite(io.req.uop.mem_cmd))\n new_coh := coh_on_hit\n new_state := s_drain_rpq\n } .otherwise { // upgrade permissions\n new_coh := old_coh\n new_state := s_refill_req\n }\n } .otherwise { // refill and writeback if necessary\n new_coh := ClientMetadata.onReset\n new_state := s_refill_req\n }\n new_state\n }\n\n when (state === s_invalid) {\n io.req_pri_rdy := true.B\n grant_had_data := false.B\n\n when (io.req_pri_val && io.req_pri_rdy) {\n state := handle_pri_req(state)\n }\n } .elsewhen (state === s_refill_req) {\n io.mem_acquire.valid := true.B\n // TODO: Use AcquirePerm if just doing permissions acquire\n io.mem_acquire.bits := edge.AcquireBlock(\n fromSource = io.id,\n toAddress = Cat(req_tag, req_idx) << blockOffBits,\n lgSize = lgCacheBlockBytes.U,\n growPermissions = grow_param)._2\n when (io.mem_acquire.fire) {\n state := s_refill_resp\n }\n } .elsewhen (state === s_refill_resp) {\n when (edge.hasData(io.mem_grant.bits)) {\n io.mem_grant.ready := io.lb_write.ready\n io.lb_write.valid := io.mem_grant.valid\n io.lb_write.bits.id := io.id\n io.lb_write.bits.offset := refill_address_inc >> rowOffBits\n io.lb_write.bits.data := io.mem_grant.bits.data\n } .otherwise {\n io.mem_grant.ready := true.B\n }\n\n when (io.mem_grant.fire) {\n grant_had_data := edge.hasData(io.mem_grant.bits)\n }\n when (refill_done) {\n grantack.valid := edge.isRequest(io.mem_grant.bits)\n grantack.bits := edge.GrantAck(io.mem_grant.bits)\n state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq)\n assert(!(!grant_had_data && req_needs_wb))\n commit_line := false.B\n new_coh := coh_on_grant\n\n }\n } .elsewhen (state === s_drain_rpq_loads) {\n val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) &&\n !isWrite(rpq.io.deq.bits.uop.mem_cmd) &&\n (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay\n // drain all loads for now\n val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))\n val data = io.lb_resp\n val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W))\n val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed,\n Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)),\n data_word, false.B, wordBytes)\n\n\n rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load\n io.lb_read.valid := rpq.io.deq.valid && drain_load\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits\n\n io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load\n io.resp.bits.uop := rpq.io.deq.bits.uop\n io.resp.bits.data := loadgen.data\n io.resp.bits.is_hella := rpq.io.deq.bits.is_hella\n when (rpq.io.deq.fire) {\n commit_line := true.B\n }\n .elsewhen (rpq.io.empty && !commit_line)\n {\n when (!rpq.io.enq.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := enablePrefetching.B\n }\n } .elsewhen (rpq.io.empty || (rpq.io.deq.valid && !drain_load)) {\n // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired\n // The prefetcher should consider fetching the next line\n io.commit_val := true.B\n state := s_meta_read\n }\n } .elsewhen (state === s_meta_read) {\n io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)\n io.meta_read.bits.idx := req_idx\n io.meta_read.bits.tag := req_tag\n io.meta_read.bits.way_en := req.way_en\n when (io.meta_read.fire) {\n state := s_meta_resp_1\n }\n } .elsewhen (state === s_meta_resp_1) {\n state := s_meta_resp_2\n } .elsewhen (state === s_meta_resp_2) {\n val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1\n state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read\n Mux(needs_wb, s_meta_clear, s_commit_line))\n } .elsewhen (state === s_meta_clear) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := coh_on_clear\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n\n when (io.meta_write.fire) {\n state := s_wb_req\n }\n } .elsewhen (state === s_wb_req) {\n io.wb_req.valid := true.B\n\n io.wb_req.bits.tag := req.old_meta.tag\n io.wb_req.bits.idx := req_idx\n io.wb_req.bits.param := shrink_param\n io.wb_req.bits.way_en := req.way_en\n io.wb_req.bits.source := io.id\n io.wb_req.bits.voluntary := true.B\n when (io.wb_req.fire) {\n state := s_wb_resp\n }\n } .elsewhen (state === s_wb_resp) {\n when (io.wb_resp) {\n state := s_commit_line\n }\n } .elsewhen (state === s_commit_line) {\n io.lb_read.valid := true.B\n io.lb_read.bits.id := io.id\n io.lb_read.bits.offset := refill_ctr\n\n io.refill.valid := io.lb_read.fire\n io.refill.bits.addr := req_block_addr | (refill_ctr << rowOffBits)\n io.refill.bits.way_en := req.way_en\n io.refill.bits.wmask := ~(0.U(rowWords.W))\n io.refill.bits.data := io.lb_resp\n when (io.refill.fire) {\n refill_ctr := refill_ctr + 1.U\n when (refill_ctr === (cacheDataBeats - 1).U) {\n state := s_drain_rpq\n }\n }\n } .elsewhen (state === s_drain_rpq) {\n io.replay <> rpq.io.deq\n io.replay.bits.way_en := req.way_en\n io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0))\n when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) {\n // Set dirty bit\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd)\n assert(is_hit, \"We still don't have permissions for this store\")\n new_coh := coh_on_hit\n }\n when (rpq.io.empty && !rpq.io.enq.valid) {\n state := s_meta_write_req\n }\n } .elsewhen (state === s_meta_write_req) {\n io.meta_write.valid := true.B\n io.meta_write.bits.idx := req_idx\n io.meta_write.bits.data.coh := new_coh\n io.meta_write.bits.data.tag := req_tag\n io.meta_write.bits.way_en := req.way_en\n when (io.meta_write.fire) {\n state := s_mem_finish_1\n finish_to_prefetch := false.B\n }\n } .elsewhen (state === s_mem_finish_1) {\n io.mem_finish.valid := grantack.valid\n io.mem_finish.bits := grantack.bits\n when (io.mem_finish.fire || !grantack.valid) {\n grantack.valid := false.B\n state := s_mem_finish_2\n }\n } .elsewhen (state === s_mem_finish_2) {\n state := Mux(finish_to_prefetch, s_prefetch, s_invalid)\n } .elsewhen (state === s_prefetch) {\n io.req_pri_rdy := true.B\n when ((io.req_sec_val && !io.req_sec_rdy) || io.clear_prefetch) {\n state := s_invalid\n } .elsewhen (io.req_sec_val && io.req_sec_rdy) {\n val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd)\n when (is_hit) { // Proceed with refill\n new_coh := coh_on_hit\n state := s_meta_read\n } .otherwise { // Reacquire this line\n new_coh := ClientMetadata.onReset\n state := s_refill_req\n }\n } .elsewhen (io.req_pri_val && io.req_pri_rdy) {\n grant_had_data := false.B\n state := handle_pri_req(state)\n }\n }\n}\n\nclass BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Decoupled(new BoomDCacheReq))\n val resp = Decoupled(new BoomDCacheResp)\n val mem_access = Decoupled(new TLBundleA(edge.bundle))\n val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle)))\n\n // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative\n })\n\n def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits)\n\n def wordFromBeat(addr: UInt, dat: UInt) = {\n val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W))\n (dat >> shift)(wordBits-1, 0)\n }\n\n val req = Reg(new BoomDCacheReq)\n val grant_word = Reg(UInt(wordBits.W))\n\n val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4)\n\n val state = RegInit(s_idle)\n io.req.ready := state === s_idle\n\n val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes)\n\n val a_source = id.U\n val a_address = req.addr\n val a_size = req.uop.mem_size\n val a_data = Fill(beatWords, req.data)\n\n val get = edge.Get(a_source, a_address, a_size)._2\n val put = edge.Put(a_source, a_address, a_size, a_data)._2\n val atomics = if (edge.manager.anySupportLogical) {\n MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(\n M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,\n M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,\n M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2,\n M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2,\n M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2,\n M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2,\n M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2,\n M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2,\n M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2))\n } else {\n // If no managers support atomics, assert fail if processor asks for them\n assert(state === s_idle || !isAMO(req.uop.mem_cmd))\n (0.U).asTypeOf(new TLBundleA(edge.bundle))\n }\n assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n\n io.mem_access.valid := state === s_mem_access\n io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put))\n\n val send_resp = isRead(req.uop.mem_cmd)\n\n io.resp.valid := (state === s_resp) && send_resp\n io.resp.bits.is_hella := req.is_hella\n io.resp.bits.uop := req.uop\n io.resp.bits.data := loadgen.data\n\n when (io.req.fire) {\n req := io.req.bits\n state := s_mem_access\n }\n when (io.mem_access.fire) {\n state := s_mem_ack\n }\n when (state === s_mem_ack && io.mem_ack.valid) {\n state := s_resp\n when (isRead(req.uop.mem_cmd)) {\n grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data)\n }\n }\n when (state === s_resp) {\n when (!send_resp || io.resp.fire) {\n state := s_idle\n }\n }\n}\n\nclass LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val offset = UInt(log2Ceil(cacheDataBeats).W)\n def lb_addr = Cat(id, offset)\n}\n\nclass LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p)\n{\n val data = UInt(encRowBits.W)\n}\n\nclass LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p)\n{\n val id = UInt(log2Ceil(nLBEntries).W)\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p)\n with HasL1HellaCacheParameters\n{\n val coh = new ClientMetadata\n val addr = UInt(coreMaxAddrBits.W)\n}\n\nclass BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)\n with HasL1HellaCacheParameters\n{\n val io = IO(new Bundle {\n val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe\n val req_is_probe = Input(Vec(memWidth, Bool()))\n val resp = Decoupled(new BoomDCacheResp)\n val secondary_miss = Output(Vec(memWidth, Bool()))\n val block_hit = Output(Vec(memWidth, Bool()))\n\n val brupdate = Input(new BrUpdateInfo)\n val exception = Input(Bool())\n val rob_pnr_idx = Input(UInt(robAddrSz.W))\n val rob_head_idx = Input(UInt(robAddrSz.W))\n\n val mem_acquire = Decoupled(new TLBundleA(edge.bundle))\n val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle)))\n val mem_finish = Decoupled(new TLBundleE(edge.bundle))\n\n val refill = Decoupled(new L1DataWriteReq)\n val meta_write = Decoupled(new L1MetaWriteReq)\n val meta_read = Decoupled(new L1MetaReadReq)\n val meta_resp = Input(Valid(new L1Metadata))\n val replay = Decoupled(new BoomDCacheReqInternal)\n val prefetch = Decoupled(new BoomDCacheReq)\n val wb_req = Decoupled(new WritebackReq(edge.bundle))\n\n val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))\n\n val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence\n\n val wb_resp = Input(Bool())\n\n val fence_rdy = Output(Bool())\n val probe_rdy = Output(Bool())\n })\n\n val req_idx = OHToUInt(io.req.map(_.valid))\n val req = io.req(req_idx)\n val req_is_probe = io.req_is_probe(0)\n\n for (w <- 0 until memWidth)\n io.req(w).ready := false.B\n\n val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher)\n else Module(new NullPrefetcher)\n\n io.prefetch <> prefetcher.io.prefetch\n\n\n val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U)\n\n // --------------------\n // The MSHR SDQ\n val sdq_val = RegInit(0.U(cfg.nSDQ.W))\n val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))\n val sdq_rdy = !sdq_val.andR\n val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd)\n val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W))\n\n when (sdq_enq) {\n sdq(sdq_alloc_id) := req.bits.data\n }\n\n // --------------------\n // The LineBuffer Data\n // Holds refilling lines, prefetched lines\n val lb = Mem(nLBEntries * cacheDataBeats, UInt(encRowBits.W))\n val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs))\n val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs))\n\n lb_read_arb.io.out.ready := false.B\n lb_write_arb.io.out.ready := true.B\n\n val lb_read_data = WireInit(0.U(encRowBits.W))\n when (lb_write_arb.io.out.fire) {\n lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data)\n } .otherwise {\n lb_read_arb.io.out.ready := true.B\n when (lb_read_arb.io.out.fire) {\n lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr)\n }\n }\n def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f))\n\n\n\n\n val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool())))\n\n val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w)))\n val idx_match = widthMap(w => idx_matches(w).reduce(_||_))\n val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w)))\n\n val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W)))\n\n val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs))\n val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs))\n val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs))\n val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs))\n val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs))\n val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs))\n\n val commit_vals = Wire(Vec(cfg.nMSHRs, Bool()))\n val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W)))\n val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata))\n\n var sec_rdy = false.B\n\n io.fence_rdy := true.B\n io.probe_rdy := true.B\n io.mem_grant.ready := false.B\n\n val mshr_alloc_idx = Wire(UInt())\n val pri_rdy = WireInit(false.B)\n val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx)\n val mshrs = (0 until cfg.nMSHRs) map { i =>\n val mshr = Module(new BoomMSHR)\n mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W)\n\n for (w <- 0 until memWidth) {\n idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits)\n tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits\n way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en\n }\n wb_tag_list(i) := mshr.io.wb_req.bits.tag\n\n\n\n mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val\n when (i.U === mshr_alloc_idx) {\n pri_rdy := mshr.io.req_pri_rdy\n }\n\n mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable\n mshr.io.req := req.bits\n mshr.io.req_is_probe := req_is_probe\n mshr.io.req.sdq_id := sdq_alloc_id\n\n // Clear because of a FENCE, a request to the same idx as a prefetched line,\n // a probe to that prefetched line, all mshrs are in use\n mshr.io.clear_prefetch := ((io.clear_all && !req.valid)||\n (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) ||\n (req_is_probe && idx_matches(req_idx)(i)))\n mshr.io.brupdate := io.brupdate\n mshr.io.exception := io.exception\n mshr.io.rob_pnr_idx := io.rob_pnr_idx\n mshr.io.rob_head_idx := io.rob_head_idx\n\n mshr.io.prober_state := io.prober_state\n\n mshr.io.wb_resp := io.wb_resp\n\n meta_write_arb.io.in(i) <> mshr.io.meta_write\n meta_read_arb.io.in(i) <> mshr.io.meta_read\n mshr.io.meta_resp := io.meta_resp\n wb_req_arb.io.in(i) <> mshr.io.wb_req\n replay_arb.io.in(i) <> mshr.io.replay\n refill_arb.io.in(i) <> mshr.io.refill\n\n lb_read_arb.io.in(i) <> mshr.io.lb_read\n mshr.io.lb_resp := lb_read_data\n lb_write_arb.io.in(i) <> mshr.io.lb_write\n\n commit_vals(i) := mshr.io.commit_val\n commit_addrs(i) := mshr.io.commit_addr\n commit_cohs(i) := mshr.io.commit_coh\n\n mshr.io.mem_grant.valid := false.B\n mshr.io.mem_grant.bits := DontCare\n when (io.mem_grant.bits.source === i.U) {\n mshr.io.mem_grant <> io.mem_grant\n }\n\n sec_rdy = sec_rdy || (mshr.io.req_sec_rdy && mshr.io.req_sec_val)\n resp_arb.io.in(i) <> mshr.io.resp\n\n when (!mshr.io.req_pri_rdy) {\n io.fence_rdy := false.B\n }\n for (w <- 0 until memWidth) {\n when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) {\n io.probe_rdy := false.B\n }\n }\n\n mshr\n }\n\n // Try to round-robin the MSHRs\n val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W))\n mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head))\n when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) }\n\n\n\n io.meta_write <> meta_write_arb.io.out\n io.meta_read <> meta_read_arb.io.out\n io.wb_req <> wb_req_arb.io.out\n\n val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs))\n\n\n var mmio_rdy = false.B\n\n val mmios = (0 until nIOMSHRs) map { i =>\n val id = cfg.nMSHRs + 1 + i // +1 for wb unit\n val mshr = Module(new BoomIOMSHR(id))\n\n mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready\n mmio_alloc_arb.io.in(i).bits := DontCare\n mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready\n mshr.io.req.bits := req.bits\n\n mmio_rdy = mmio_rdy || mshr.io.req.ready\n\n mshr.io.mem_ack.bits := io.mem_grant.bits\n mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U\n when (io.mem_grant.bits.source === id.U) {\n io.mem_grant.ready := true.B\n }\n\n resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp\n when (!mshr.io.req.ready) {\n io.fence_rdy := false.B\n }\n mshr\n }\n\n mmio_alloc_arb.io.out.ready := req.valid && !cacheable\n\n TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access))\n TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish))\n\n val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false))\n respq.io.brupdate := io.brupdate\n respq.io.flush := io.exception\n respq.io.enq <> resp_arb.io.out\n io.resp <> respq.io.deq\n\n for (w <- 0 until memWidth) {\n io.req(w).ready := (w.U === req_idx) &&\n Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy))\n io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w)\n io.block_hit(w) := idx_match(w) && tag_match(w)\n }\n io.refill <> refill_arb.io.out\n\n val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd)\n\n io.replay <> replay_arb.io.out\n io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id)\n\n when (io.replay.valid || sdq_enq) {\n sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) |\n PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq)\n }\n\n prefetcher.io.mshr_avail := RegNext(pri_rdy)\n prefetcher.io.req_val := RegNext(commit_vals.reduce(_||_))\n prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs))\n prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs))\n}", + "response": "module sdq_17x64(\n input [4:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [63:0] R0_data,\n input [4:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [63:0] W0_data\n);\n\n reg [63:0] Memory[0:16];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 64'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module ListBuffer_QueuedRequest_q15_e35(\n input clock,\n input reset,\n output io_push_ready,\n input io_push_valid,\n input [3:0] io_push_bits_index,\n input io_push_bits_data_control,\n input [2:0] io_push_bits_data_opcode,\n input [2:0] io_push_bits_data_param,\n input [2:0] io_push_bits_data_size,\n input [5:0] io_push_bits_data_source,\n input [12:0] io_push_bits_data_tag,\n input [5:0] io_push_bits_data_offset,\n input [5:0] io_push_bits_data_put,\n output [14:0] io_valid,\n input io_pop_valid,\n input [3:0] io_pop_bits,\n output io_data_prio_0,\n output io_data_prio_2,\n output io_data_control,\n output [2:0] io_data_opcode,\n output [2:0] io_data_param,\n output [2:0] io_data_size,\n output [5:0] io_data_source,\n output [12:0] io_data_tag,\n output [5:0] io_data_offset,\n output [5:0] io_data_put\n);\n\n wire [42:0] _data_ext_R0_data;\n wire [5:0] _next_ext_R0_data;\n wire [5:0] _tail_ext_R0_data;\n wire [5:0] _tail_ext_R1_data;\n wire [5:0] _head_ext_R0_data;\n reg [14:0] valid;\n reg [34:0] used;\n wire [34:0] _freeOH_T_22 = ~used;\n wire [33:0] _freeOH_T_3 = _freeOH_T_22[33:0] | {_freeOH_T_22[32:0], 1'h0};\n wire [33:0] _freeOH_T_6 = _freeOH_T_3 | {_freeOH_T_3[31:0], 2'h0};\n wire [33:0] _freeOH_T_9 = _freeOH_T_6 | {_freeOH_T_6[29:0], 4'h0};\n wire [33:0] _freeOH_T_12 = _freeOH_T_9 | {_freeOH_T_9[25:0], 8'h0};\n wire [33:0] _freeOH_T_15 = _freeOH_T_12 | {_freeOH_T_12[17:0], 16'h0};\n wire [34:0] _GEN = {~(_freeOH_T_15 | {_freeOH_T_15[1:0], 32'h0}), 1'h1} & _freeOH_T_22;\n wire [30:0] _freeIdx_T_1 = {29'h0, _GEN[34:33]} | _GEN[31:1];\n wire [14:0] _freeIdx_T_3 = _freeIdx_T_1[30:16] | _freeIdx_T_1[14:0];\n wire [6:0] _freeIdx_T_5 = _freeIdx_T_3[14:8] | _freeIdx_T_3[6:0];\n wire [2:0] _freeIdx_T_7 = _freeIdx_T_5[6:4] | _freeIdx_T_5[2:0];\n wire [5:0] freeIdx = {|(_GEN[34:32]), |(_freeIdx_T_1[30:15]), |(_freeIdx_T_3[14:7]), |(_freeIdx_T_5[6:3]), |(_freeIdx_T_7[2:1]), _freeIdx_T_7[2] | _freeIdx_T_7[0]};\n wire [14:0] _push_valid_T = valid >> io_push_bits_index;\n wire io_push_ready_0 = used != 35'h7FFFFFFFF;\n wire data_MPORT_en = io_push_ready_0 & io_push_valid;\n wire [15:0] _valid_clr_T = 16'h1 << io_pop_bits;\n wire [15:0] _valid_set_T = 16'h1 << io_push_bits_index;\n wire [63:0] _used_clr_T = 64'h1 << _head_ext_R0_data;\n always @(posedge clock) begin\n if (reset) begin\n valid <= 15'h0;\n used <= 35'h0;\n end\n else begin\n valid <= valid & ~(io_pop_valid & _head_ext_R0_data == _tail_ext_R1_data ? _valid_clr_T[14:0] : 15'h0) | (data_MPORT_en ? _valid_set_T[14:0] : 15'h0);\n used <= used & ~(io_pop_valid ? _used_clr_T[34:0] : 35'h0) | (data_MPORT_en ? _GEN : 35'h0);\n end\n end\n head_15x6 head_ext (\n .R0_addr (io_pop_bits),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_head_ext_R0_data),\n .W0_addr (io_pop_bits),\n .W0_en (io_pop_valid),\n .W0_clk (clock),\n .W0_data (data_MPORT_en & _push_valid_T[0] & _tail_ext_R0_data == _head_ext_R0_data ? freeIdx : _next_ext_R0_data),\n .W1_addr (io_push_bits_index),\n .W1_en (data_MPORT_en & ~(_push_valid_T[0])),\n .W1_clk (clock),\n .W1_data (freeIdx)\n );\n tail_15x6 tail_ext (\n .R0_addr (io_push_bits_index),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_tail_ext_R0_data),\n .R1_addr (io_pop_bits),\n .R1_en (io_pop_valid),\n .R1_clk (clock),\n .R1_data (_tail_ext_R1_data),\n .W0_addr (io_push_bits_index),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n next_35x6 next_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (io_pop_valid),\n .R0_clk (clock),\n .R0_data (_next_ext_R0_data),\n .W0_addr (_tail_ext_R0_data),\n .W0_en (data_MPORT_en & _push_valid_T[0]),\n .W0_clk (clock),\n .W0_data (freeIdx)\n );\n data_35x43 data_ext (\n .R0_addr (_head_ext_R0_data),\n .R0_en (1'h1),\n .R0_clk (clock),\n .R0_data (_data_ext_R0_data),\n .W0_addr (freeIdx),\n .W0_en (data_MPORT_en),\n .W0_clk (clock),\n .W0_data ({io_push_bits_data_put, io_push_bits_data_offset, io_push_bits_data_tag, io_push_bits_data_source, io_push_bits_data_size, io_push_bits_data_param, io_push_bits_data_opcode, io_push_bits_data_control, 2'h1})\n );\n assign io_push_ready = io_push_ready_0;\n assign io_valid = valid;\n assign io_data_prio_0 = _data_ext_R0_data[0];\n assign io_data_prio_2 = _data_ext_R0_data[1];\n assign io_data_control = _data_ext_R0_data[2];\n assign io_data_opcode = _data_ext_R0_data[5:3];\n assign io_data_param = _data_ext_R0_data[8:6];\n assign io_data_size = _data_ext_R0_data[11:9];\n assign io_data_source = _data_ext_R0_data[17:12];\n assign io_data_tag = _data_ext_R0_data[30:18];\n assign io_data_offset = _data_ext_R0_data[36:31];\n assign io_data_put = _data_ext_R0_data[42:37];\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code /*\n * Copyright 2019 SiFive, Inc.\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You should have received a copy of LICENSE.Apache2 along with\n * this software. If not, you may obtain a copy at\n *\n * https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\npackage sifive.blocks.inclusivecache\n\nimport chisel3._\nimport chisel3.util._\nimport freechips.rocketchip.util._\n\ncase class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)\n{\n val queueBits = log2Up(queues)\n val entryBits = log2Up(entries)\n}\n\nclass ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle\n{\n val index = UInt(params.queueBits.W)\n val data = Output(params.gen)\n}\n\nclass ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module\n{\n override def desiredName = s\"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}\"\n val io = IO(new Bundle {\n // push is visible on the same cycle; flow queues\n val push = Flipped(Decoupled(new ListBufferPush(params)))\n val valid = UInt(params.queues.W)\n val pop = Flipped(Valid(UInt(params.queueBits.W)))\n val data = Output(params.gen)\n })\n\n val valid = RegInit(0.U(params.queues.W))\n val head = Mem(params.queues, UInt(params.entryBits.W))\n val tail = Mem(params.queues, UInt(params.entryBits.W))\n val used = RegInit(0.U(params.entries.W))\n val next = Mem(params.entries, UInt(params.entryBits.W))\n val data = Mem(params.entries, params.gen)\n\n val freeOH = ~(leftOR(~used) << 1) & ~used\n val freeIdx = OHToUInt(freeOH)\n\n val valid_set = WireDefault(0.U(params.queues.W))\n val valid_clr = WireDefault(0.U(params.queues.W))\n val used_set = WireDefault(0.U(params.entries.W))\n val used_clr = WireDefault(0.U(params.entries.W))\n\n val push_tail = tail.read(io.push.bits.index)\n val push_valid = valid(io.push.bits.index)\n\n io.push.ready := !used.andR\n when (io.push.fire) {\n valid_set := UIntToOH(io.push.bits.index, params.queues)\n used_set := freeOH\n data.write(freeIdx, io.push.bits.data)\n when (push_valid) {\n next.write(push_tail, freeIdx)\n } .otherwise {\n head.write(io.push.bits.index, freeIdx)\n }\n tail.write(io.push.bits.index, freeIdx)\n }\n\n val pop_head = head.read(io.pop.bits)\n val pop_valid = valid(io.pop.bits)\n\n // Bypass push data to the peek port\n io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))\n io.valid := (if (!params.bypass) valid else (valid | valid_set))\n\n // It is an error to pop something that is not valid\n assert (!io.pop.fire || (io.valid)(io.pop.bits))\n\n when (io.pop.fire) {\n used_clr := UIntToOH(pop_head, params.entries)\n when (pop_head === tail.read(io.pop.bits)) {\n valid_clr := UIntToOH(io.pop.bits, params.queues)\n }\n head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))\n }\n\n // Empty bypass changes no state\n when ((!params.bypass).B || !io.pop.valid || pop_valid) {\n used := (used & ~used_clr) | used_set\n valid := (valid & ~valid_clr) | valid_set\n }\n}", + "response": "module head_2x4(\n input R0_addr,\n input R0_en,\n input R0_clk,\n output [3:0] R0_data,\n input W0_addr,\n input W0_en,\n input W0_clk,\n input [3:0] W0_data,\n input W1_addr,\n input W1_en,\n input W1_clk,\n input [3:0] W1_data\n);\n\n reg [3:0] Memory[0:1];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n if (W1_en & 1'h1)\n Memory[W1_addr] <= W1_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code // See LICENSE.SiFive for license details.\n\npackage freechips.rocketchip.util\n\nimport chisel3._\nimport chisel3.util.{Decoupled, DecoupledIO}\n\n// A Repeater passes its input to its output, unless repeat is asserted.\n// When repeat is asserted, the Repeater copies the input and repeats it next cycle.\nclass Repeater[T <: Data](gen: T) extends Module\n{\n override def desiredName = s\"Repeater_${gen.typeName}\"\n val io = IO( new Bundle {\n val repeat = Input(Bool())\n val full = Output(Bool())\n val enq = Flipped(Decoupled(gen.cloneType))\n val deq = Decoupled(gen.cloneType)\n } )\n\n val full = RegInit(false.B)\n val saved = Reg(gen.cloneType)\n\n // When !full, a repeater is pass-through\n io.deq.valid := io.enq.valid || full\n io.enq.ready := io.deq.ready && !full\n io.deq.bits := Mux(full, saved, io.enq.bits)\n io.full := full\n\n when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }\n when (io.deq.fire && !io.repeat) { full := false.B }\n}\n\nobject Repeater\n{\n def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {\n val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))\n repeater.io.repeat := repeat\n repeater.io.enq <> enq\n repeater.io.deq\n }\n}", + "response": "module Repeater_TLBundleA_a17d64s7k1z3u(\n input clock,\n input reset,\n input io_repeat,\n output io_full,\n output io_enq_ready,\n input io_enq_valid,\n input [2:0] io_enq_bits_opcode,\n input [2:0] io_enq_bits_param,\n input [2:0] io_enq_bits_size,\n input [6:0] io_enq_bits_source,\n input [16:0] io_enq_bits_address,\n input [7:0] io_enq_bits_mask,\n input io_enq_bits_corrupt,\n input io_deq_ready,\n output io_deq_valid,\n output [2:0] io_deq_bits_opcode,\n output [2:0] io_deq_bits_param,\n output [2:0] io_deq_bits_size,\n output [6:0] io_deq_bits_source,\n output [16:0] io_deq_bits_address,\n output [7:0] io_deq_bits_mask,\n output io_deq_bits_corrupt\n);\n\n reg full;\n reg [2:0] saved_opcode;\n reg [2:0] saved_param;\n reg [2:0] saved_size;\n reg [6:0] saved_source;\n reg [16:0] saved_address;\n reg [7:0] saved_mask;\n reg saved_corrupt;\n wire io_deq_valid_0 = io_enq_valid | full;\n wire io_enq_ready_0 = io_deq_ready & ~full;\n wire _GEN = io_enq_ready_0 & io_enq_valid & io_repeat;\n always @(posedge clock) begin\n if (reset)\n full <= 1'h0;\n else\n full <= ~(io_deq_ready & io_deq_valid_0 & ~io_repeat) & (_GEN | full);\n if (_GEN) begin\n saved_opcode <= io_enq_bits_opcode;\n saved_param <= io_enq_bits_param;\n saved_size <= io_enq_bits_size;\n saved_source <= io_enq_bits_source;\n saved_address <= io_enq_bits_address;\n saved_mask <= io_enq_bits_mask;\n saved_corrupt <= io_enq_bits_corrupt;\n end\n end\n assign io_full = full;\n assign io_enq_ready = io_enq_ready_0;\n assign io_deq_valid = io_deq_valid_0;\n assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode;\n assign io_deq_bits_param = full ? saved_param : io_enq_bits_param;\n assign io_deq_bits_size = full ? saved_size : io_enq_bits_size;\n assign io_deq_bits_source = full ? saved_source : io_enq_bits_source;\n assign io_deq_bits_address = full ? saved_address : io_enq_bits_address;\n assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask;\n assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code //******************************************************************************\n// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).\n// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.\n//------------------------------------------------------------------------------\n\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n// Utility Functions\n//------------------------------------------------------------------------------\n//------------------------------------------------------------------------------\n\npackage boom.v3.util\n\nimport chisel3._\nimport chisel3.util._\n\nimport freechips.rocketchip.rocket.Instructions._\nimport freechips.rocketchip.rocket._\nimport freechips.rocketchip.util.{Str}\nimport org.chipsalliance.cde.config.{Parameters}\nimport freechips.rocketchip.tile.{TileKey}\n\nimport boom.v3.common.{MicroOp}\nimport boom.v3.exu.{BrUpdateInfo}\n\n/**\n * Object to XOR fold a input register of fullLength into a compressedLength.\n */\nobject Fold\n{\n def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {\n val clen = compressedLength\n val hlen = fullLength\n if (hlen <= clen) {\n input\n } else {\n var res = 0.U(clen.W)\n var remaining = input.asUInt\n for (i <- 0 to hlen-1 by clen) {\n val len = if (i + clen > hlen ) (hlen - i) else clen\n require(len > 0)\n res = res(clen-1,0) ^ remaining(len-1,0)\n remaining = remaining >> len.U\n }\n res\n }\n }\n}\n\n/**\n * Object to check if MicroOp was killed due to a branch mispredict.\n * Uses \"Fast\" branch masks\n */\nobject IsKilledByBranch\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)\n }\n\n def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {\n return maskMatch(brupdate.b1.mispredict_mask, uop_mask)\n }\n}\n\n/**\n * Object to return new MicroOp with a new BR mask given a MicroOp mask\n * and old BR mask.\n */\nobject GetNewUopAndBrMask\n{\n def apply(uop: MicroOp, brupdate: BrUpdateInfo)\n (implicit p: Parameters): MicroOp = {\n val newuop = WireInit(uop)\n newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask\n newuop\n }\n}\n\n/**\n * Object to return a BR mask given a MicroOp mask and old BR mask.\n */\nobject GetNewBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {\n return uop.br_mask & ~brupdate.b1.resolve_mask\n }\n\n def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {\n return br_mask & ~brupdate.b1.resolve_mask\n }\n}\n\nobject UpdateBrMask\n{\n def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {\n val out = WireInit(uop)\n out.br_mask := GetNewBrMask(brupdate, uop)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {\n val out = WireInit(bundle)\n out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)\n out\n }\n def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {\n val out = WireInit(bundle)\n out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)\n out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)\n out\n }\n}\n\n/**\n * Object to check if at least 1 bit matches in two masks\n */\nobject maskMatch\n{\n def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U\n}\n\n/**\n * Object to clear one bit in a mask given an index\n */\nobject clearMaskBit\n{\n def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)\n}\n\n/**\n * Object to shift a register over by one bit and concat a new one\n */\nobject PerformShiftRegister\n{\n def apply(reg_val: UInt, new_bit: Bool): UInt = {\n reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt\n reg_val\n }\n}\n\n/**\n * Object to shift a register over by one bit, wrapping the top bit around to the bottom\n * (XOR'ed with a new-bit), and evicting a bit at index HLEN.\n * This is used to simulate a longer HLEN-width shift register that is folded\n * down to a compressed CLEN.\n */\nobject PerformCircularShiftRegister\n{\n def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {\n val carry = csr(clen-1)\n val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)\n newval\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapAdd\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, amt: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + amt)(log2Ceil(n)-1,0)\n } else {\n val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)\n Mux(sum >= n.U,\n sum - n.U,\n sum)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapSub\n{\n // \"n\" is the number of increments, so we wrap to n-1.\n def apply(value: UInt, amt: Int, n: Int): UInt = {\n if (isPow2(n)) {\n (value - amt.U)(log2Ceil(n)-1,0)\n } else {\n val v = Cat(0.U(1.W), value)\n val b = Cat(0.U(1.W), amt.U)\n Mux(value >= amt.U,\n value - amt.U,\n n.U - amt.U + value)\n }\n }\n}\n\n/**\n * Object to increment an input value, wrapping it if\n * necessary.\n */\nobject WrapInc\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value + 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === (n-1).U)\n Mux(wrap, 0.U, value + 1.U)\n }\n }\n}\n\n/**\n * Object to decrement an input value, wrapping it if\n * necessary.\n */\nobject WrapDec\n{\n // \"n\" is the number of increments, so we wrap at n-1.\n def apply(value: UInt, n: Int): UInt = {\n if (isPow2(n)) {\n (value - 1.U)(log2Ceil(n)-1,0)\n } else {\n val wrap = (value === 0.U)\n Mux(wrap, (n-1).U, value - 1.U)\n }\n }\n}\n\n/**\n * Object to mask off lower bits of a PC to align to a \"b\"\n * Byte boundary.\n */\nobject AlignPCToBoundary\n{\n def apply(pc: UInt, b: Int): UInt = {\n // Invert for scenario where pc longer than b\n // (which would clear all bits above size(b)).\n ~(~pc | (b-1).U)\n }\n}\n\n/**\n * Object to rotate a signal left by one\n */\nobject RotateL1\n{\n def apply(signal: UInt): UInt = {\n val w = signal.getWidth\n val out = Cat(signal(w-2,0), signal(w-1))\n\n return out\n }\n}\n\n/**\n * Object to sext a value to a particular length.\n */\nobject Sext\n{\n def apply(x: UInt, length: Int): UInt = {\n if (x.getWidth == length) return x\n else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)\n }\n}\n\n/**\n * Object to translate from BOOM's special \"packed immediate\" to a 32b signed immediate\n * Asking for U-type gives it shifted up 12 bits.\n */\nobject ImmGen\n{\n import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}\n def apply(ip: UInt, isel: UInt): SInt = {\n val sign = ip(LONGEST_IMM_SZ-1).asSInt\n val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)\n val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)\n val i11 = Mux(isel === IS_U, 0.S,\n Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))\n val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)\n val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)\n val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)\n\n return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt\n }\n}\n\n/**\n * Object to get the FP rounding mode out of a packed immediate.\n */\nobject ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }\n\n/**\n * Object to get the FP function fype from a packed immediate.\n * Note: only works if !(IS_B or IS_S)\n */\nobject ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }\n\n/**\n * Object to see if an instruction is a JALR.\n */\nobject DebugIsJALR\n{\n def apply(inst: UInt): Bool = {\n // TODO Chisel not sure why this won't compile\n// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),\n// Array(\n// JALR -> Bool(true)))\n inst(6,0) === \"b1100111\".U\n }\n}\n\n/**\n * Object to take an instruction and output its branch or jal target. Only used\n * for a debug assert (no where else would we jump straight from instruction\n * bits to a target).\n */\nobject DebugGetBJImm\n{\n def apply(inst: UInt): UInt = {\n // TODO Chisel not sure why this won't compile\n //val csignals =\n //rocket.DecodeLogic(inst,\n // List(Bool(false), Bool(false)),\n // Array(\n // BEQ -> List(Bool(true ), Bool(false)),\n // BNE -> List(Bool(true ), Bool(false)),\n // BGE -> List(Bool(true ), Bool(false)),\n // BGEU -> List(Bool(true ), Bool(false)),\n // BLT -> List(Bool(true ), Bool(false)),\n // BLTU -> List(Bool(true ), Bool(false))\n // ))\n //val is_br :: nothing :: Nil = csignals\n\n val is_br = (inst(6,0) === \"b1100011\".U)\n\n val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))\n val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))\n\n Mux(is_br, br_targ, jal_targ)\n }\n}\n\n/**\n * Object to return the lowest bit position after the head.\n */\nobject AgePriorityEncoder\n{\n def apply(in: Seq[Bool], head: UInt): UInt = {\n val n = in.size\n val width = log2Ceil(in.size)\n val n_padded = 1 << width\n val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in\n val idx = PriorityEncoder(temp_vec)\n idx(width-1, 0) //discard msb\n }\n}\n\n/**\n * Object to determine whether queue\n * index i0 is older than index i1.\n */\nobject IsOlder\n{\n def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))\n}\n\n/**\n * Set all bits at or below the highest order '1'.\n */\nobject MaskLower\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => in >> i.U).reduce(_|_)\n }\n}\n\n/**\n * Set all bits at or above the lowest order '1'.\n */\nobject MaskUpper\n{\n def apply(in: UInt) = {\n val n = in.getWidth\n (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)\n }\n}\n\n/**\n * Transpose a matrix of Chisel Vecs.\n */\nobject Transpose\n{\n def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {\n val n = in(0).size\n VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))\n }\n}\n\n/**\n * N-wide one-hot priority encoder.\n */\nobject SelectFirstN\n{\n def apply(in: UInt, n: Int) = {\n val sels = Wire(Vec(n, UInt(in.getWidth.W)))\n var mask = in\n\n for (i <- 0 until n) {\n sels(i) := PriorityEncoderOH(mask)\n mask = mask & ~sels(i)\n }\n\n sels\n }\n}\n\n/**\n * Connect the first k of n valid input interfaces to k output interfaces.\n */\nclass Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module\n{\n require(n >= k)\n\n val io = IO(new Bundle {\n val in = Vec(n, Flipped(DecoupledIO(gen)))\n val out = Vec(k, DecoupledIO(gen))\n })\n\n if (n == k) {\n io.out <> io.in\n } else {\n val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))\n val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>\n (col zip io.in.map(_.valid)) map {case (c,v) => c && v})\n val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))\n val out_valids = sels map (col => col.reduce(_||_))\n val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))\n\n in_readys zip io.in foreach {case (r,i) => i.ready := r}\n out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}\n }\n}\n\n/**\n * Create a queue that can be killed with a branch kill signal.\n * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).\n */\nclass BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)\n (implicit p: org.chipsalliance.cde.config.Parameters)\n extends boom.v3.common.BoomModule()(p)\n with boom.v3.common.HasBoomCoreParameters\n{\n val io = IO(new Bundle {\n val enq = Flipped(Decoupled(gen))\n val deq = Decoupled(gen)\n\n val brupdate = Input(new BrUpdateInfo())\n val flush = Input(Bool())\n\n val empty = Output(Bool())\n val count = Output(UInt(log2Ceil(entries).W))\n })\n\n val ram = Mem(entries, gen)\n val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))\n val uops = Reg(Vec(entries, new MicroOp))\n\n val enq_ptr = Counter(entries)\n val deq_ptr = Counter(entries)\n val maybe_full = RegInit(false.B)\n\n val ptr_match = enq_ptr.value === deq_ptr.value\n io.empty := ptr_match && !maybe_full\n val full = ptr_match && maybe_full\n val do_enq = WireInit(io.enq.fire)\n val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)\n\n for (i <- 0 until entries) {\n val mask = uops(i).br_mask\n val uop = uops(i)\n valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))\n when (valids(i)) {\n uops(i).br_mask := GetNewBrMask(io.brupdate, mask)\n }\n }\n\n when (do_enq) {\n ram(enq_ptr.value) := io.enq.bits\n valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n uops(enq_ptr.value) := io.enq.bits.uop\n uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n enq_ptr.inc()\n }\n\n when (do_deq) {\n valids(deq_ptr.value) := false.B\n deq_ptr.inc()\n }\n\n when (do_enq =/= do_deq) {\n maybe_full := do_enq\n }\n\n io.enq.ready := !full\n\n val out = Wire(gen)\n out := ram(deq_ptr.value)\n out.uop := uops(deq_ptr.value)\n io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))\n io.deq.bits := out\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)\n\n // For flow queue behavior.\n if (flow) {\n when (io.empty) {\n io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)\n io.deq.bits := io.enq.bits\n io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)\n\n do_deq := false.B\n when (io.deq.ready) { do_enq := false.B }\n }\n }\n private val ptr_diff = enq_ptr.value - deq_ptr.value\n if (isPow2(entries)) {\n io.count := Cat(maybe_full && ptr_match, ptr_diff)\n }\n else {\n io.count := Mux(ptr_match,\n Mux(maybe_full,\n entries.asUInt, 0.U),\n Mux(deq_ptr.value > enq_ptr.value,\n entries.asUInt + ptr_diff, ptr_diff))\n }\n}\n\n// ------------------------------------------\n// Printf helper functions\n// ------------------------------------------\n\nobject BoolToChar\n{\n /**\n * Take in a Chisel Bool and convert it into a Str\n * based on the Chars given\n *\n * @param c_bool Chisel Bool\n * @param trueChar Scala Char if bool is true\n * @param falseChar Scala Char if bool is false\n * @return UInt ASCII Char for \"trueChar\" or \"falseChar\"\n */\n def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {\n Mux(c_bool, Str(trueChar), Str(falseChar))\n }\n}\n\nobject CfiTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param cfi_type specific cfi type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(cfi_type: UInt) = {\n val strings = Seq(\"----\", \"BR \", \"JAL \", \"JALR\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(cfi_type)\n }\n}\n\nobject BpdTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param bpd_type specific bpd type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(bpd_type: UInt) = {\n val strings = Seq(\"BR \", \"JUMP\", \"----\", \"RET \", \"----\", \"CALL\", \"----\", \"----\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(bpd_type)\n }\n}\n\nobject RobTypeToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param rob_type specific rob type\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(rob_type: UInt) = {\n val strings = Seq(\"RST\", \"NML\", \"RBK\", \" WT\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(rob_type)\n }\n}\n\nobject XRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param xreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(xreg: UInt) = {\n val strings = Seq(\" x0\", \" ra\", \" sp\", \" gp\",\n \" tp\", \" t0\", \" t1\", \" t2\",\n \" s0\", \" s1\", \" a0\", \" a1\",\n \" a2\", \" a3\", \" a4\", \" a5\",\n \" a6\", \" a7\", \" s2\", \" s3\",\n \" s4\", \" s5\", \" s6\", \" s7\",\n \" s8\", \" s9\", \"s10\", \"s11\",\n \" t3\", \" t4\", \" t5\", \" t6\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(xreg)\n }\n}\n\nobject FPRegToChars\n{\n /**\n * Get a Vec of Strs that can be used for printing\n *\n * @param fpreg specific register number\n * @return Vec of Strs (must be indexed to get specific char)\n */\n def apply(fpreg: UInt) = {\n val strings = Seq(\" ft0\", \" ft1\", \" ft2\", \" ft3\",\n \" ft4\", \" ft5\", \" ft6\", \" ft7\",\n \" fs0\", \" fs1\", \" fa0\", \" fa1\",\n \" fa2\", \" fa3\", \" fa4\", \" fa5\",\n \" fa6\", \" fa7\", \" fs2\", \" fs3\",\n \" fs4\", \" fs5\", \" fs6\", \" fs7\",\n \" fs8\", \" fs9\", \"fs10\", \"fs11\",\n \" ft8\", \" ft9\", \"ft10\", \"ft11\")\n val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })\n multiVec(fpreg)\n }\n}\n\nobject BoomCoreStringPrefix\n{\n /**\n * Add prefix to BOOM strings (currently only adds the hartId)\n *\n * @param strs list of strings\n * @return String combining the list with the prefix per line\n */\n def apply(strs: String*)(implicit p: Parameters) = {\n val prefix = \"[C\" + s\"${p(TileKey).tileId}\" + \"] \"\n strs.map(str => prefix + str + \"\\n\").mkString(\"\")\n }\n}", + "response": "module ram_5x77(\n input [2:0] R0_addr,\n input R0_en,\n input R0_clk,\n output [76:0] R0_data,\n input [2:0] W0_addr,\n input W0_en,\n input W0_clk,\n input [76:0] W0_data\n);\n\n reg [76:0] Memory[0:4];\n always @(posedge W0_clk) begin\n if (W0_en & 1'h1)\n Memory[W0_addr] <= W0_data;\n end\n assign R0_data = R0_en ? Memory[R0_addr] : 77'bx;\nendmodule" + }, + { + "prompt": "Generate the Verilog code corresponding to this Chisel code package testchipip.serdes\n\nimport chisel3._\nimport chisel3.util._\n\nimport org.chipsalliance.cde.config._\nimport freechips.rocketchip.diplomacy._\nimport freechips.rocketchip.util._\nimport freechips.rocketchip.tilelink._\n\ntrait TLFieldHelper {\n def getBodyFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)\n case b: TLBundleC => Seq( b.data, b.corrupt)\n case b: TLBundleD => Seq( b.data, b.corrupt)\n case b: TLBundleE => Seq()\n }\n def getConstFields(b: TLChannel): Seq[Data] = b match {\n case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )\n case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )\n case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)\n case b: TLBundleE => Seq( b.sink )\n }\n def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max\n def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max\n def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))\n}\n\nclass TLBeat(val beatWidth: Int) extends Bundle {\n val payload = UInt(beatWidth.W)\n val head = Bool()\n val tail = Bool()\n}\n\nabstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Flipped(Decoupled(gen))\n val beat = Decoupled(new TLBeat(beatWidth))\n })\n def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B\n\n // convert decoupled to irrevocable\n val q = Module(new Queue(gen, 1, pipe=true, flow=true))\n q.io.enq <> io.protocol\n val protocol = q.io.deq\n\n val has_body = Wire(Bool())\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n val head = edge.first(protocol.bits, protocol.fire)\n val tail = edge.last(protocol.bits, protocol.fire)\n\n val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))\n val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))\n\n val is_body = RegInit(false.B)\n io.beat.valid := protocol.valid\n protocol.ready := io.beat.ready && (is_body || !has_body)\n\n io.beat.bits.head := head && !is_body\n io.beat.bits.tail := tail && (is_body || !has_body)\n io.beat.bits.payload := Mux(is_body, body, const)\n\n when (io.beat.fire && io.beat.bits.head) { is_body := true.B }\n when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }\n}\n\nabstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {\n override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString(\"_\")\n val beatWidth = minTLPayloadWidth(gen)\n val io = IO(new Bundle {\n val protocol = Decoupled(gen)\n val beat = Flipped(Decoupled(new TLBeat(beatWidth)))\n })\n\n // Handle size = 1 gracefully (Chisel3 empty range is broken)\n def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)\n\n val protocol = Wire(Decoupled(gen))\n io.protocol <> protocol\n val body_fields = getBodyFields(protocol.bits)\n val const_fields = getConstFields(protocol.bits)\n\n val is_const = RegInit(true.B)\n val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))\n val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)\n io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready\n protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid\n\n def assign(i: UInt, sigs: Seq[Data]) = {\n var t = i\n for (s <- sigs.reverse) {\n s := t.asTypeOf(s.cloneType)\n t = t >> s.getWidth\n }\n }\n assign(const, const_fields)\n assign(io.beat.bits.payload, body_fields)\n\n when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }\n when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }\n}\n\nclass TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)\n}\n\nclass TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {\n when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }\n}\n\nclass TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)\n\nclass TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {\n has_body := edgeOut.hasData(protocol.bits)\n}\n\nclass TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)\n\nclass TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {\n has_body := edgeIn.hasData(protocol.bits)\n}\n\nclass TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)", + "response": "module TLDFromBeat_SerialRAM_a64d64s8k8z8c(\n input clock,\n input reset,\n input io_protocol_ready,\n output io_protocol_valid,\n output [2:0] io_protocol_bits_opcode,\n output [1:0] io_protocol_bits_param,\n output [7:0] io_protocol_bits_size,\n output [7:0] io_protocol_bits_source,\n output [7:0] io_protocol_bits_sink,\n output io_protocol_bits_denied,\n output [63:0] io_protocol_bits_data,\n output io_protocol_bits_corrupt,\n output io_beat_ready,\n input io_beat_valid,\n input [64:0] io_beat_bits_payload,\n input io_beat_bits_head,\n input io_beat_bits_tail\n);\n\n reg is_const;\n reg [29:0] const_reg;\n wire [29:0] const_0 = io_beat_bits_head ? io_beat_bits_payload[29:0] : const_reg;\n wire io_beat_ready_0 = is_const & ~io_beat_bits_tail | io_protocol_ready;\n wire _GEN = io_beat_ready_0 & io_beat_valid;\n wire _GEN_0 = _GEN & io_beat_bits_head;\n always @(posedge clock) begin\n if (reset)\n is_const <= 1'h1;\n else\n is_const <= _GEN & io_beat_bits_tail | ~_GEN_0 & is_const;\n if (_GEN_0)\n const_reg <= io_beat_bits_payload[29:0];\n end\n assign io_protocol_valid = (~is_const | io_beat_bits_tail) & io_beat_valid;\n assign io_protocol_bits_opcode = const_0[29:27];\n assign io_protocol_bits_param = const_0[26:25];\n assign io_protocol_bits_size = const_0[24:17];\n assign io_protocol_bits_source = const_0[16:9];\n assign io_protocol_bits_sink = const_0[8:1];\n assign io_protocol_bits_denied = const_0[0];\n assign io_protocol_bits_data = io_beat_bits_payload[64:1];\n assign io_protocol_bits_corrupt = io_beat_bits_payload[0];\n assign io_beat_ready = io_beat_ready_0;\nendmodule" + } +] \ No newline at end of file