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--******************************************************************************--
-- Author: Weihao Ming --
-- Date: 2014-01-13 --
-- Module: EE3A1 RISC Microprocessor --
-- Description: Re-order buffer. Placing before instruction decoder --
-- and automatic re-order instruction for --
-- microprocessor. --
--******************************************************************************--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY reorderBuffer IS
PORT( in1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk: IN STD_LOGIC);
END ENTITY reorderBuffer;
ARCHITECTURE rtl OF reorderBuffer IS
TYPE buffer_array IS ARRAY( 0 TO 5) OF STD_LOGIC_VECTOR ( 31 DOWNTO 0);
SIGNAL buffer_data: buffer_array:= (X"00000000", X"00000000", X"00000000", -- 6 addresses buffer.
X"00000000", X"00000000", X"00000000");
BEGIN
PROCESS(clk)
variable i: integer := 2; -- i is for pre-running instruction.
variable j: integer := 0; -- j is for post-running instruction.
variable c: integer := 0; -- 0 for incomplete output. 1 for complete.
variable output1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000"; -- Temperaryly store output.
variable buffer_temp : buffer_array := buffer_data; -- Copy all the data in buffer to
BEGIN -- re-order it. and pushing everything
IF(rising_edge(clk)) THEN -- forward to fullfill empty address.
i := 2;
j := 0;
c := 0;
WHILE ( i < 6 ) LOOP -- Storing incoming instruction in an empty address.
IF( buffer_data(i) /= X"00000000")THEN
i := i + 1;
ELSE
buffer_data(i) <= in1;
buffer_temp(i) := in1;
i := 0;
EXIT;
END IF;
END LOOP;
i := 2;
j := 0;
c := 0;
WHILE ( i < 6 ) LOOP
IF( buffer_data(0) = X"00000000") -- If previous two instructions are both no-op,
AND (buffer_data(1) = X"00000000") THEN -- then output first no no-op instruction.
IF(buffer_data(i) /= X"00000000") THEN
out1 <= buffer_data(i);
buffer_data(i) <= X"00000000";
buffer_temp(i) := X"00000000";
output1 := buffer_data(i);
i := 2;
c := 1;
EXIT;
ELSE
i := i+1;
END IF;
ELSIF (buffer_data(1)(15 DOWNTO 11) = buffer_data(2)(25 DOWNTO 21)) THEN -- If current reading is previous written,
out1 <= buffer_data(2); -- then output to meet multiplexer funtion.
output1 := buffer_data(2);
buffer_data(2) <= X"00000000";
buffer_temp(2) := X"00000000";
i :=2;
c :=1;
EXIT;
ELSE
j := 0; -- Check if there is data hazard. if so, then reorder.
WHILE ( j < 3 ) LOOP
IF(buffer_data(j) /= X"00000000") THEN
IF( buffer_data(i)(25 DOWNTO 21) /= buffer_data(j)(15 DOWNTO 11)) THEN
IF(buffer_data(i)(20 DOWNTO 16) /= buffer_data(j)(15 DOWNTO 11)) THEN
IF(buffer_data(i) /= X"00000000") THEN
out1 <= buffer_data(i);
output1 := buffer_data(i);
buffer_data(i) <= X"00000000";
buffer_temp(i) := X"00000000";
i := 2;
j := 0;
c := 1;
EXIT;
ELSE
j := j+1;
END IF;
ELSE
j := j+1;
END IF;
ELSE
j := j+1;
END IF;
ELSE
j := j + 1;
END IF;
END LOOP;
END IF;
IF ( c = 0) THEN
i := i + 1;
ELSE
i := 2;
j := 0;
EXIT;
END IF;
END LOOP;
IF ( c = 0) THEN -- If there will be data harzard for all buffer instruction,
out1 <= X"00000000"; -- then output no-op.
output1 := X"00000000";
c := 1;
END IF;
buffer_data(0) <= buffer_data(1);
buffer_data(1) <= output1;
i := 2;
WHILE( i < 5) LOOP -- Pushing buffer data forward to fullfill empty address.
IF(buffer_temp(i) = X"00000000") THEN
buffer_temp(i) := buffer_temp(i+1);
buffer_temp(i+1) := X"00000000";
END IF;
i := i+1;
END LOOP;
i:=2;
WHILE( i < 6) LOOP -- Writing temperary data to address.
buffer_data(i) <= buffer_temp(i);
i := i+1;
END LOOP;
END IF;
END PROCESS;
END ARCHITECTURE rtl; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity:
-- File: sysmon_unisim.vhd
-- Author: Jan Andersson - Gaisler Research
-- Description: Xilinx System Monitor
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.SYSMON;
-- pragma translate_on
-------------------------------------------------------------------------------
-- Virtex 5 System Monitor
-------------------------------------------------------------------------------
entity sysmon_virtex5 is
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end sysmon_virtex5;
architecture struct of sysmon_virtex5 is
component SYSMON
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port (
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
begin -- struct
sysmon0 : SYSMON
generic map (INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end struct;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY multiplier IS
GENERIC(
WIDTH : integer := 16
);
PORT(
multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
twocomp : IN std_logic
);
END multiplier ;
architecture rtl of multiplier is
function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
twoc : in std_logic) -- Signed/Unsigned
return std_logic_vector is
variable rec_v : std_logic_vector (WIDTH-1 downto 0);
begin
if ((r(WIDTH-1) and twoc)='1') then
rec_v := not(r);
else
rec_v := r;
end if;
return (rec_v + (r(WIDTH-1) and twoc));
end;
signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
signal sign_s : std_logic;
begin
multiplicant_s <= rectify(multiplicant,twocomp);
multiplier_s <= rectify(multiplier,twocomp);
sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
product_s <= multiplicant_s * multiplier_s;
product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity FA10_tb is
end FA10_tb;
architecture tb of FA10_tb is
component FA10
port(
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0);
Sout : out std_logic_vector(9 downto 0);
Cout : out std_logic
);
end component;
signal A : std_logic_vector(9 downto 0);
signal B : std_logic_vector(9 downto 0);
signal Sout : std_logic_vector(9 downto 0);
signal Cout : std_logic;
begin
mapping: FA10 port map(A,B,Sout,Cout);
-- A(0)<='0';
-- A(1)<='0';
-- A(2)<='0';
-- A(3)<='0';
-- A(4)<='0';
-- A(5)<='0';
-- A(6)<='0';
-- A(7)<='0';
-- A(8)<='0';
-- A(9)<='0';
-- B(0)<='0';
-- B(1)<='0';
-- B(2)<='0';
-- B(3)<='0';
-- B(4)<='0';
-- B(5)<='0';
-- B(6)<='0';
-- B(7)<='0';
-- B(8)<='0';
-- B(9)<='0';
process
begin
A(0)<='0'; wait for 1 ns;
A(0)<='1'; wait for 1 ns;
end process;
process
begin
A(1)<='0'; wait for 2 ns;
A(1)<='1'; wait for 2 ns;
end process;
process
begin
A(2)<='0'; wait for 4 ns;
A(2)<='1'; wait for 4 ns;
end process;
process
begin
A(3)<='0'; wait for 8 ns;
A(3)<='1'; wait for 8 ns;
end process;
process
begin
A(4)<='0'; wait for 16 ns;
A(4)<='1'; wait for 16 ns;
end process;
process
begin
A(5)<='0'; wait for 32 ns;
A(5)<='1'; wait for 32 ns;
end process;
process
begin
A(6)<='0'; wait for 64 ns;
A(6)<='1'; wait for 64 ns;
end process;
process
begin
A(7)<='0'; wait for 128 ns;
A(7)<='1'; wait for 128 ns;
end process;
process
begin
A(8)<='0'; wait for 256 ns;
A(8)<='1'; wait for 256 ns;
end process;
process
begin
A(9)<='0'; wait for 512 ns;
A(9)<='1'; wait for 512 ns;
end process;
process
begin
B(0)<='0'; wait for 1024 ns;
B(0)<='1'; wait for 1024 ns;
end process;
process
begin
B(1)<='0'; wait for 2048 ns;
B(1)<='1'; wait for 2048 ns;
end process;
process
begin
B(2)<='0'; wait for 4096 ns;
B(2)<='1'; wait for 4096 ns;
end process;
process
begin
B(3)<='0'; wait for 8192 ns;
B(3)<='1'; wait for 8192 ns;
end process;
process
begin
B(4)<='0'; wait for 16384 ns;
B(4)<='1'; wait for 16384 ns;
end process;
process
begin
B(5)<='0'; wait for 32768 ns;
B(5)<='1'; wait for 32768 ns;
end process;
process
begin
B(6)<='0'; wait for 65536 ns;
B(6)<='1'; wait for 65536 ns;
end process;
process
begin
B(7)<='0'; wait for 131072 ns;
B(7)<='1'; wait for 131072 ns;
end process;
process
begin
B(8)<='0'; wait for 262144 ns;
B(8)<='1'; wait for 262144 ns;
end process;
process
begin
B(9)<='0'; wait for 524288 ns;
B(9)<='1'; wait for 524288 ns;
end process;
end tb;
configuration cfg_tb of FA10_tb is
for tb
end for;
end cfg_tb; |
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
--
-- Grab bag of miscellaneous VHDL-2008 syntax
--
entity vhdl2008 is
end entity;
package genpack is
generic ( x : integer := 5; y : boolean ); -- OK
generic map ( x => 5, y => false ); -- OK
constant c : bit_vector(1 to x) := (1 to x => '1');
end package;
package genpack2 is
generic ( x : integer := 5; y : boolean ); -- OK
function add_x_if_y ( arg : integer ) return integer;
end package;
package body genpack2 is
function add_x_if_y ( arg : integer ) return integer is
begin
if y then
return arg + x;
else
return arg;
end if;
end function;
end package body;
package primary_genpack2 is new work.genpack2 generic map (4, false); -- OK
architecture test of vhdl2008 is
type my_utype is (a, b, c);
type my_utype_vector is array (natural range <>) of my_utype;
function resolved (s : my_utype_vector) return my_utype;
subtype my_type is resolved my_utype;
subtype my_type_vector is (resolved) my_utype_vector; -- OK
type my_logical_vec is array (natural range <>) of bit;
type my_bool is (true, false);
package my_genpack2 is new work.genpack2 generic map (1, true); -- OK
begin
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := or v; -- OK
if or v = '1' then end if; -- OK
b := and v; -- OK
b := xor v; -- OK
b := xnor v; -- OK
b := nand v; -- OK
b := nor v; -- OK
end process;
process is
variable b : bit;
variable v : my_logical_vec(1 to 3);
begin
b := b ?= '1'; -- OK
b := b ?/= '1'; -- OK
b := b ?< '0'; -- OK
b := b ?> '0'; -- OK
b := b ?<= '1'; -- OK
b := b ?>= '1'; -- OK
b := v ?= "101"; -- OK
b := v ?/= "111"; -- OK
end process;
process is
variable b : bit;
variable i : integer;
function "??"(x : integer) return boolean;
begin
if b then end if; -- OK
if b xor '1' then end if; -- OK
while b and '1' loop end loop; -- OK
if i + 1 then end if; -- OK
if now + 1 ns then end if; -- Error
while true loop
exit when b or '1'; -- OK
next when b or '1'; -- OK
end loop;
wait until b xor '0'; -- OK
assert b nor '1'; -- OK
assert ?? 1; -- OK
end process;
/* This is a comment */
/* Comments /* do not nest */
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
end process;
process is
variable x : string(7 downto 0);
begin
x := 8x"0"; -- OK
x := 6x"a"; -- OK
x := 4x"4"; -- OK
x := 2x"4"; -- Error
x := 0x"5"; -- Error
x := 18x"383fe"; -- OK
x := 0b"0000"; -- OK
x := d"5"; -- OK
x := 5d"25"; -- OK
x := 120d"83298148949012041209428481024019511"; -- Error
x := uo"5"; -- OK
x := 5sb"11"; -- OK
x := 2sb"1111110"; -- OK
x := 2sb"10110101"; -- Error
x := 4x"0f"; -- OK
x := Uo"2C"; -- OK
x := d"C4"; -- Error
x := 8x"-"; -- OK
x := 12d"13"; -- OK
end process;
b2: block is
signal s : integer;
begin
process is
begin
s <= 1 when s < 0 else 5; -- OK
end process;
end block;
process is
type int_vec2 is array (natural range <>) of integer_vector; -- OK
constant a : int_vec2(1 to 3)(1 to 2) := ( -- OK
(1, 2), (3, 4), (5, 6) );
begin
assert a(1)(1) = 1; -- OK
end process;
b3: block is
signal s : integer;
begin
process is
begin
s <= force 1; -- OK
s <= force out 1; -- OK
s <= force in 2; -- OK
s <= release; -- OK
s <= release out; -- OK
end process;
end block;
process is
variable x : bit_vector(1 to 3);
begin
case? x is -- OK
when "010" => null;
when others => null;
end case?;
case? x is
when others => null;
end case; -- Error
case x is
when others => null;
end case ?; -- Error
end process;
b4: block is
procedure foo (x : integer_vector; y : integer) is
variable a : x'subtype; -- OK
variable b : integer'subtype; -- OK
variable c : b4'subtype; -- Error
variable d : x'element; -- OK
variable e : y'element; -- Error
variable f : b4'element; -- Error
begin
end procedure;
begin
end block;
b5: block is
function gen1 generic (n : integer) (x : integer) return integer is
begin -- OK
return 1;
end function;
function gen2 generic (n : integer) -- OK
parameter (x : integer) return integer;
function gen3 generic (type t; p : t) (x : t) return integer; -- Ok
function my_gen1 is new gen1 generic map (5); -- OK
begin
end block;
b6: block is
constant c1 : string := to_string(100); -- OK
begin
end block;
b7: block is
signal s : integer;
signal b : bit;
begin
s <= 1 when b else 2; -- OK
s <= 2 when '1' else 6; -- OK
process is
variable v : integer;
begin
v := 1 when b else 5; -- OK
s <= 5 when b else 7; -- OK
end process;
end block;
g1: if g1a: true generate -- OK
elsif g2: false generate
begin
end g2;
else generate
end generate;
g1: if true generate
end g1; -- Error
else foo: generate
end bar; -- Error
end generate;
end architecture;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tcp_extract_header - Behavioral
--
-- Description: Extract the TCP header fields
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_extract_header is
port(
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0) := (others => '0');
data_valid_in : in std_logic := '0';
data_out : out std_logic_vector(7 downto 0) := (others => '0');
data_valid_out : out std_logic := '0';
tcp_hdr_valid : out std_logic := '0';
tcp_src_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
tcp_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
tcp_window : out std_logic_vector(15 downto 0) := (others => '0');
tcp_flag_urg : out std_logic := '0';
tcp_flag_ack : out std_logic := '0';
tcp_flag_psh : out std_logic := '0';
tcp_flag_rst : out std_logic := '0';
tcp_flag_syn : out std_logic := '0';
tcp_flag_fin : out std_logic := '0';
tcp_checksum : out std_logic_vector(15 downto 0) := (others => '0');
tcp_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0'));
end tcp_extract_header;
architecture Behavioral of tcp_extract_header is
signal i_tcp_hdr_valid : std_logic := '0';
signal i_tcp_src_port : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_dst_port : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_seq_num : std_logic_vector(31 downto 0) := (others => '0');
signal i_tcp_ack_num : std_logic_vector(31 downto 0) := (others => '0');
signal i_tcp_window : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_flag_urg : std_logic := '0';
signal i_tcp_flag_ack : std_logic := '0';
signal i_tcp_flag_psh : std_logic := '0';
signal i_tcp_flag_rst : std_logic := '0';
signal i_tcp_flag_syn : std_logic := '0';
signal i_tcp_flag_fin : std_logic := '0';
signal i_tcp_checksum : std_logic_vector(15 downto 0) := (others => '0');
signal i_tcp_urgent_ptr : std_logic_vector(15 downto 0) := (others => '0');
signal byte_hdr_len : unsigned(10 downto 0) := (others => '0');
signal data_count : unsigned(10 downto 0) := (others => '0');
signal count : unsigned( 4 downto 0) := (others => '0');
begin
tcp_hdr_valid <= i_tcp_hdr_valid;
tcp_src_port <= i_tcp_src_port;
tcp_dst_port <= i_tcp_dst_port;
tcp_seq_num <= i_tcp_seq_num;
tcp_ack_num <= i_tcp_ack_num;
tcp_window <= i_tcp_window;
tcp_flag_urg <= i_tcp_flag_urg;
tcp_flag_ack <= i_tcp_flag_ack;
tcp_flag_psh <= i_tcp_flag_psh;
tcp_flag_rst <= i_tcp_flag_rst;
tcp_flag_syn <= i_tcp_flag_syn;
tcp_flag_fin <= i_tcp_flag_fin;
tcp_checksum <= i_tcp_checksum;
tcp_urgent_ptr <= i_tcp_urgent_ptr;
process(clk)
begin
if rising_edge(clk) then
data_valid_out <= '0';
data_out <= (others => '0');
i_tcp_hdr_valid <= '0';
if data_valid_in = '1' then
case count is
when "00000" => i_tcp_src_port(15 downto 8) <= data_in;
when "00001" => i_tcp_src_port( 7 downto 0) <= data_in;
when "00010" => i_tcp_dst_port(15 downto 8) <= data_in;
when "00011" => i_tcp_dst_port( 7 downto 0) <= data_in;
when "00100" => i_tcp_seq_num(31 downto 24) <= data_in;
when "00101" => i_tcp_seq_num(23 downto 16) <= data_in;
when "00110" => i_tcp_seq_num(15 downto 8) <= data_in;
when "00111" => i_tcp_seq_num( 7 downto 0) <= data_in;
when "01000" => i_tcp_ack_num(31 downto 24) <= data_in;
when "01001" => i_tcp_ack_num(23 downto 16) <= data_in;
when "01010" => i_tcp_ack_num(15 downto 8) <= data_in;
when "01011" => i_tcp_ack_num( 7 downto 0) <= data_in;
when "01100" => byte_hdr_len(5 downto 2) <= unsigned(data_in( 7 downto 4));
when "01101" => i_tcp_flag_urg <= data_in(5);
i_tcp_flag_ack <= data_in(4);
i_tcp_flag_psh <= data_in(3);
i_tcp_flag_rst <= data_in(2);
i_tcp_flag_syn <= data_in(1);
i_tcp_flag_fin <= data_in(0);
when "01110" => i_tcp_window(15 downto 8) <= data_in;
when "01111" => i_tcp_window( 7 downto 0) <= data_in;
when "10000" => i_tcp_checksum(15 downto 8) <= data_in;
when "10001" => i_tcp_checksum( 7 downto 0) <= data_in;
when "10010" => i_tcp_urgent_ptr(15 downto 8) <= data_in;
when "10011" => i_tcp_urgent_ptr( 7 downto 0) <= data_in;
when others => if data_count = byte_hdr_len then
data_valid_out <= data_valid_in;
data_out <= data_in;
i_tcp_hdr_valid <= '1';
elsif data_count > byte_hdr_len then
data_valid_out <= data_valid_in;
data_out <= data_in;
i_tcp_hdr_valid <= '0';
end if;
end case;
if count /= "11111" then
count <= count+1;
end if;
data_count <= data_count + 1;
else
-- For when TCP packets have no data
if data_count = byte_hdr_len and byte_hdr_len /= 0 then
i_tcp_hdr_valid <= '1';
end if;
data_valid_out <= '0';
data_out <= data_in;
count <= (others => '0');
data_count <= (others => '0');
end if;
end if;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:26:49 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBCU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBCU IS
END TBCU;
ARCHITECTURE behavior OF TBCU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
Instruction : IN std_logic_vector(31 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal ALUOP : std_logic_vector(5 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
Instruction => Instruction,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "00000000000000000000000000000000";
wait for 100 ns;
Instruction <= "00001000000000000000000000000000";
wait for 100 ns;
Instruction <= "00000000100000000000000000000000";
wait for 100 ns;
Instruction <= "00001111100000000000000000000000";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 12:37:55 10/28/2009
-- Description: a register pair of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_16 is
port ( I_CLK : in std_logic;
I_D : in std_logic_vector (15 downto 0);
I_WE : in std_logic_vector ( 1 downto 0);
Q : out std_logic_vector (15 downto 0));
end reg_16;
architecture Behavioral of reg_16 is
signal L : std_logic_vector (15 downto 0) := X"7777";
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE(1) = '1') then
L(15 downto 8) <= I_D(15 downto 8);
end if;
if (I_WE(0) = '1') then
L( 7 downto 0) <= I_D( 7 downto 0);
end if;
end if;
end process;
Q <= L;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 12:37:55 10/28/2009
-- Description: a register pair of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_16 is
port ( I_CLK : in std_logic;
I_D : in std_logic_vector (15 downto 0);
I_WE : in std_logic_vector ( 1 downto 0);
Q : out std_logic_vector (15 downto 0));
end reg_16;
architecture Behavioral of reg_16 is
signal L : std_logic_vector (15 downto 0) := X"7777";
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE(1) = '1') then
L(15 downto 8) <= I_D(15 downto 8);
end if;
if (I_WE(0) = '1') then
L( 7 downto 0) <= I_D( 7 downto 0);
end if;
end if;
end process;
Q <= L;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 12:37:55 10/28/2009
-- Description: a register pair of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_16 is
port ( I_CLK : in std_logic;
I_D : in std_logic_vector (15 downto 0);
I_WE : in std_logic_vector ( 1 downto 0);
Q : out std_logic_vector (15 downto 0));
end reg_16;
architecture Behavioral of reg_16 is
signal L : std_logic_vector (15 downto 0) := X"7777";
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE(1) = '1') then
L(15 downto 8) <= I_D(15 downto 8);
end if;
if (I_WE(0) = '1') then
L( 7 downto 0) <= I_D( 7 downto 0);
end if;
end if;
end process;
Q <= L;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:15 09/10/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Stepper
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestStepper IS
END TestStepper;
ARCHITECTURE behavior OF TestStepper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Stepper
PORT(
iac_pulse : IN std_logic;
iac_clockwise : IN std_logic;
iac_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal iac_pulse : std_logic := '0';
signal iac_clockwise : std_logic := '0';
--Outputs
signal iac_out : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Stepper PORT MAP (
iac_pulse => iac_pulse,
iac_clockwise => iac_clockwise,
iac_out => iac_out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
iac_clockwise <= '1';
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:32 06/15/2015
-- Design Name:
-- Module Name: Stepper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Stepper is
port(
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0')
);
end Stepper;
architecture Behavioral of Stepper is
signal phase : std_logic_vector(1 downto 0) := (others => '0');
begin
process(iac_pulse) begin
if (falling_edge(iac_pulse)) then
if (iac_clockwise = '1') then
phase <= phase + 1;
else
phase <= phase - 1;
end if;
end if;
if (iac_pulse = '1') then
case phase is
when "00" => iac_out <= "10010000";
when "01" => iac_out <= "00001001";
when "10" => iac_out <= "01100000";
when "11" => iac_out <= "00000110";
when others => iac_out <= (others => '0');
end case;
else
iac_out <= (others => '0');
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_975;
architecture augh of cmp_975 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_975 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_975;
architecture augh of cmp_975 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COLOR_BRIDGE;
ARCHITECTURE main OF COLOR_BRIDGE IS
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(BRG_EN = '1') THEN
CASE COLOR IS
--BLACK
WHEN x"0" =>
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
--DARK RED
WHEN x"1" =>
R <= "0111111111";
G <= "0000000000";
B <= "0000000000";
--DARK GREEN
WHEN x"2" =>
R <= "0000000000";
G <= "0111111111";
B <= "0000000000";
--DARK YELLOW
WHEN x"3" =>
R <= "0111111111";
G <= "0111111111";
B <= "0000000000";
--DARK BLUE
WHEN x"4" =>
R <= "0000000000";
G <= "0000000000";
B <= "0111111111";
--PURPLE
WHEN x"5" =>
R <= "0111111111";
G <= "0000000000";
B <= "0111111111";
--GREENISH BLUE
WHEN x"6" =>
R <= "0000000000";
G <= "0111111111";
B <= "0111111111";
--LIGHT GRAY
WHEN x"7" =>
R <= "1011111111";
G <= "1011111111";
B <= "1011111111";
--GRAY
WHEN x"8" =>
R <= "0111111111";
G <= "0111111111";
B <= "0111111111";
--RED
WHEN x"9" =>
R <= "1111111111";
G <= "0000000000";
B <= "0000000000";
--GREEN
WHEN x"A" =>
R <= "0000000000";
G <= "1111111111";
B <= "0000000000";
--YELLOW
WHEN x"B" =>
R <= "1111111111";
G <= "1111111111";
B <= "0000000000";
--BLUE
WHEN x"C" =>
R <= "0000000000";
G <= "0000000000";
B <= "1111111111";
--PINK
WHEN x"D" =>
R <= "1111111111";
G <= "0000000000";
B <= "1111111111";
--SKY BLUE
WHEN x"E" =>
R <= "0000000000";
G <= "1111111111";
B <= "1111111111";
--WHITE
WHEN x"F" =>
R <= "1111111111";
G <= "1111111111";
B <= "1111111111";
WHEN OTHERS =>
END CASE;
ELSE
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
END IF;
END IF;
END PROCESS;
END main;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COLOR_BRIDGE;
ARCHITECTURE main OF COLOR_BRIDGE IS
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(BRG_EN = '1') THEN
CASE COLOR IS
--BLACK
WHEN x"0" =>
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
--DARK RED
WHEN x"1" =>
R <= "0111111111";
G <= "0000000000";
B <= "0000000000";
--DARK GREEN
WHEN x"2" =>
R <= "0000000000";
G <= "0111111111";
B <= "0000000000";
--DARK YELLOW
WHEN x"3" =>
R <= "0111111111";
G <= "0111111111";
B <= "0000000000";
--DARK BLUE
WHEN x"4" =>
R <= "0000000000";
G <= "0000000000";
B <= "0111111111";
--PURPLE
WHEN x"5" =>
R <= "0111111111";
G <= "0000000000";
B <= "0111111111";
--GREENISH BLUE
WHEN x"6" =>
R <= "0000000000";
G <= "0111111111";
B <= "0111111111";
--LIGHT GRAY
WHEN x"7" =>
R <= "1011111111";
G <= "1011111111";
B <= "1011111111";
--GRAY
WHEN x"8" =>
R <= "0111111111";
G <= "0111111111";
B <= "0111111111";
--RED
WHEN x"9" =>
R <= "1111111111";
G <= "0000000000";
B <= "0000000000";
--GREEN
WHEN x"A" =>
R <= "0000000000";
G <= "1111111111";
B <= "0000000000";
--YELLOW
WHEN x"B" =>
R <= "1111111111";
G <= "1111111111";
B <= "0000000000";
--BLUE
WHEN x"C" =>
R <= "0000000000";
G <= "0000000000";
B <= "1111111111";
--PINK
WHEN x"D" =>
R <= "1111111111";
G <= "0000000000";
B <= "1111111111";
--SKY BLUE
WHEN x"E" =>
R <= "0000000000";
G <= "1111111111";
B <= "1111111111";
--WHITE
WHEN x"F" =>
R <= "1111111111";
G <= "1111111111";
B <= "1111111111";
WHEN OTHERS =>
END CASE;
ELSE
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
END IF;
END IF;
END PROCESS;
END main;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY COLOR_BRIDGE IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
BRG_EN : IN STD_LOGIC;
COLOR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
G : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
B : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COLOR_BRIDGE;
ARCHITECTURE main OF COLOR_BRIDGE IS
BEGIN
PROCESS(CLK, RST)
BEGIN
IF(RST = '1') THEN
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(BRG_EN = '1') THEN
CASE COLOR IS
--BLACK
WHEN x"0" =>
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
--DARK RED
WHEN x"1" =>
R <= "0111111111";
G <= "0000000000";
B <= "0000000000";
--DARK GREEN
WHEN x"2" =>
R <= "0000000000";
G <= "0111111111";
B <= "0000000000";
--DARK YELLOW
WHEN x"3" =>
R <= "0111111111";
G <= "0111111111";
B <= "0000000000";
--DARK BLUE
WHEN x"4" =>
R <= "0000000000";
G <= "0000000000";
B <= "0111111111";
--PURPLE
WHEN x"5" =>
R <= "0111111111";
G <= "0000000000";
B <= "0111111111";
--GREENISH BLUE
WHEN x"6" =>
R <= "0000000000";
G <= "0111111111";
B <= "0111111111";
--LIGHT GRAY
WHEN x"7" =>
R <= "1011111111";
G <= "1011111111";
B <= "1011111111";
--GRAY
WHEN x"8" =>
R <= "0111111111";
G <= "0111111111";
B <= "0111111111";
--RED
WHEN x"9" =>
R <= "1111111111";
G <= "0000000000";
B <= "0000000000";
--GREEN
WHEN x"A" =>
R <= "0000000000";
G <= "1111111111";
B <= "0000000000";
--YELLOW
WHEN x"B" =>
R <= "1111111111";
G <= "1111111111";
B <= "0000000000";
--BLUE
WHEN x"C" =>
R <= "0000000000";
G <= "0000000000";
B <= "1111111111";
--PINK
WHEN x"D" =>
R <= "1111111111";
G <= "0000000000";
B <= "1111111111";
--SKY BLUE
WHEN x"E" =>
R <= "0000000000";
G <= "1111111111";
B <= "1111111111";
--WHITE
WHEN x"F" =>
R <= "1111111111";
G <= "1111111111";
B <= "1111111111";
WHEN OTHERS =>
END CASE;
ELSE
R <= "0000000000";
G <= "0000000000";
B <= "0000000000";
END IF;
END IF;
END PROCESS;
END main;
|
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port
(i_foo : in std_logic;
o_foo : out std_logic;
clock : in std_logic);
end entity issue;
architecture beh of issue is
begin
process (clock)
variable v_foo : std_logic := i_foo;
begin
-- works without the if
if rising_edge (clock) then
v_foo := v_foo xor v_foo;
o_foo <= v_foo;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BiStableLatch is port(
Q : out std_logic;
nQ : out std_logic
);
end BiStableLatch;
architecture structual of BiStableLatch is
component NOT1 is port(
a: in std_logic;
z: out std_logic);
end component;
component REP is port(
a: in std_logic;
z: out std_logic);
end component;
signal pointQ, pointnQ : std_logic;
begin
M1 : NOT1 port map (pointQ, pointnQ);
M2 : REP port map (pointnQ, nQ);
M3 : NOT1 port map (pointnQ, pointQ);
M4 : REP port map (pointQ, Q);
end structual;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity frame_buffer is
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(11 downto 0);
addrB : in std_logic_vector(10 downto 0);
diA : in std_logic_vector(3 downto 0);
diB : in std_logic_vector(7 downto 0);
doA : out std_logic_vector(3 downto 0);
doB : out std_logic_vector(7 downto 0)
);
end frame_buffer;
architecture behavioral of frame_buffer is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
constant minWIDTH : integer := 4;
constant maxWIDTH : integer := 8;
constant maxSIZE : integer := 4096;
constant RATIO : integer := maxWIDTH / minWIDTH;
-- An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
-- array of array object. Its aspect ratio corresponds to the port with the
-- lower data width (larger depth)
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
-- You need to declare <ram> as a shared variable when :
-- - the RAM has two write ports,
-- - the RAM has only one write port whose data width is maxWIDTH
-- In all other cases, <ram> can be a signal.
shared variable ram : ramType := (others => (others => '0'));
--signal ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(3 downto 0):= (others => '0');
signal readB : std_logic_vector(7 downto 0):= (others => '0');
signal regA : std_logic_vector(3 downto 0):= (others => '0');
signal regB : std_logic_vector(7 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
readA <= diA;
else
readA <= ram(conv_integer(addrA));
end if;
end if;
regA <= readA;
end if;
end process;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
for i in 0 to RATIO-1 loop
if weB = '1' then
ram(conv_integer(addrB)) := diB(3 downto 0);
end if;
-- The read statement below is placed after the write statement on purpose
-- to ensure write-first synchronization through the variable mechanism
readB((i+1)*4-1 downto i*4) <= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO))));
end loop;
end if;
regB <= readB;
end if;
end process;
doA <= regA;
doB <= regB;
end behavioral;
|
-- DATASHEET: https://drive.google.com/open?id=0BxW0H68Pf2sKWXYxVkhYYUw2dVE
--timer mode reset is needed before timer starts.
-- clock : input
-- reset : input
-- data_in[]: input params [5], input address_base [22]
-- params : input [3]
-- read_params : input
-- write_params : input
-- reconfig : input
-- reset_timer : input
-- read_source : input [2]
-- data_out[]: ouput [29]
-- busy : output
--
--
-- For Cyclone III devices, mapping to each parameter type and corresponding parameter bit width is defined as follows:
-- *000 - Master State Machine Current State Mode (Read Only) - width of 2. Values are defined as follows:
-- 00 Factory mode
-- 01 Application mode
-- 11 Application mode with Master State Machine
-- User Watchdog Timer Enabled
-- 001 - Force early CONF_DONE (Cd_early) check - width of 1.
-- *010 - Watchdog Timeout Value - width of 29 when reading and width of 12 when writing. Note that the 12 bits for writing are the upper 12 bits of the 29-bit Watchdog Timeout Value.
-- *011 - Watchdog Enable - width of 1
-- *100 - Boot Address- width of 24 when reading and width of
-- 22 when writing. Note that the boot address should be written to the upper 22 bits of the 24-bit Boot Address.
-- *101 - (illegal value)
-- *110 - Force the internal oscillator as startup state machine clock (Osc_int) option bit - width of 1
-- *111 - Reconfiguration trigger conditions (Read Only) -
-- width of 5. Trigger bits are defined as follows:
-- Bit 4: nconfig_source: external configuration reset (nCONFIG) assertion
-- Bit 3: crcerror_source: CRC error during applicationconfiguration
-- Bit 2: nstatus_source: nSTATUS asserted by an external device as the result of an error
-- Bit 1: wdtimer_source: User Watchdog Timer timeout
-- Bit 0: runconfig_source: configuration reset triggered from logic array
-- All parameters can be written in Factory configuration mode only
--
--Usage.
-- write params at address 0x0 then write Data or read Data
-- Write Data at address 0x1 (wd timer value, boot address, we enable ,etc
-- Write anything to ox2 to start RECONFIG
-- Write anything to 0x3 to reset WD timer
-- Read from params at address 0x0
--WBADR[5:2] param
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity wb_rsu is
generic (
dat_sz : natural := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
--
-- Whishbone Interface
--
dat_i : in std_logic_vector((dat_sz - 1) downto 0);
dat_o : out std_logic_vector((dat_sz - 1) downto 0);
adr_i : in std_logic_vector(3 downto 0);
cyc_i : in std_logic;
sel_i : in std_logic_vector(3 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
halt_o: out std_logic;
stb_i : in std_logic;
--
-- RSU Interface/ALTREMOTE_UPDATE ip design
--
rsu_clock : out std_logic;
rsu_reset : out std_logic;
rsu_datain : out std_logic_vector (21 downto 0);
rsu_dataout: in std_logic_vector(28 downto 0);
rsu_params : out std_logic_vector(2 downto 0);
rsu_readparams: out std_logic;
rsu_writeparams: out std_logic;
rsu_reconfig: out std_logic;
rsu_resettimer: out std_logic;
rsu_busy : in std_logic;
rsu_readsource: out std_logic_vector(1 downto 0)
);
end wb_rsu;
architecture Behavioral of wb_rsu is
-- Internal Signals
signal reg_params : std_logic_vector(2 downto 0);
signal reg_readparams : std_logic;
signal reg_writeparams : std_logic;
signal reg_data_in : std_logic_vector(21 downto 0);
TYPE State_type IS (START, READSOURCE, READPARAMS, WRITEPARAMS, BUSY, BUSY2, WAIT1, WAIT2); -- Define the states
SIGNAL State : State_Type; -- Create a signal that uses
-- the different states
BEGIN
-- always
rsu_datain <= dat_i(21 downto 0);
--rsu_readsource <= "00"; -- always reading current state.
rsu_clock <= clk_i;
rsu_reset <= rst_i;
err_o <= '0';
rty_o <= '0';
PROCESS (clk_i, rst_i) BEGIN
If (rst_i = '1') THEN -- Upon reset, set the state to A
rsu_readsource <= "11";
State <= START;
ELSIF rising_edge(clk_i) THEN -- if there is a rising edge of the
-- clock, then do the stuff below
rsu_params <= reg_params;
rsu_readparams <= reg_readparams;
rsu_writeparams <= reg_writeparams;
rsu_reconfig <= '0';
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_resettimer <= '0';
ack_o <= '0';
halt_o <= '0';
-- The CASE statement checks the value of the State variable,
-- and based on the value and any other control signals, changes
-- to a new state.
CASE State IS
-- If the current state is A and P is set to 1, then the
-- next state is B
WHEN START =>
if (stb_i = '1') then
-- ack_o <= '1';
ack_o <= '0';
halt_o <= '0';
rsu_reconfig <= '0';
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_resettimer <= '0';
--------------------------------------------------------------------
--------------------------------------------------------------------
--WRITE
--------------------------------------------------------------------
--------------------------------------------------------------------
if (we_i = '1') then --write:
case adr_i is
--------------------------------------------------------------------
when "0000" =>-- Master State machine (RO)
-- not WRITE to this address/do nothing
ack_o <= '0';
halt_o <= '0';
State <= START;
--------------------------------------------------------------------
when "0001" =>-- Force early CONF_DONE check (RW)
reg_params <= adr_i(2 downto 0);
reg_data_in <= "000000000000000000000" & dat_i(0);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0010" =>-- Watchdog Timer Value (RW) [Read: 29bits, Write: 12bits]
reg_params <= adr_i(2 downto 0);
reg_data_in <= "0000000000" & dat_i(11 downto 0);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0011" =>-- Watchdog Enable (RW)
reg_params <= adr_i(2 downto 0);
reg_data_in <= "000000000000000000000" & dat_i(0);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0100" =>-- Boot Address (RW) [Read: 24bits, Write: 22bits]
reg_params <= adr_i(2 downto 0);
reg_data_in <= dat_i(21 downto 0);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0101" =>-- NA
--reg_params <= adr_i(5 downto 2);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0110" =>-- Force internal OSC for state machine
reg_params <= adr_i(2 downto 0);
reg_data_in <= "000000000000000000000" & dat_i(0);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "0111" =>-- Reconfigure trigger condition (RO) 5 bits
--reg_params <= adr_i(5 downto 2);
reg_writeparams <= '1';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= WRITEPARAMS;
--------------------------------------------------------------------
when "1000" =>-- read_source
rsu_readsource <= dat_i(1 downto 0);
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
ack_o <= '1';
State <= READSOURCE;
--------------------------------------------------------------------
when "1001" =>-- reconfig
rsu_reconfig <= '1';
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_resettimer <= '0';
ack_o <= '0';
halt_o <= '0';
State <= START;
--------------------------------------------------------------------
when "1010" =>-- reset WD timer
rsu_reconfig <= '0';
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_resettimer <= '1';
ack_o <= '0';
halt_o <= '0';
State <= START;
--------------------------------------------------------------------
when others =>
--dat_o <= (others => '-');
end case;
else --Read
case adr_i is
--------------------------------------------------------------------
when "0000" =>-- Master State machine (RO)
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0001" =>-- Force early CONF_DONE check (RW)
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0010" =>-- Watchdog Timer Value (RW) [Read: 29bits, Write: 12bits]
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0011" =>-- Watchdog Enable (RW)
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0100" =>-- Boot Address (RW) [Read: 24bits, Write: 22bits]
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0101" =>-- NA
--reg_params <= adr_i(5 downto 2);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= START;
--------------------------------------------------------------------
when "0110" =>-- Force internal OSC for state machine
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
when "0111" =>-- Reconfigure trigger condition (RO) 5 bits
reg_params <= adr_i(2 downto 0);
reg_writeparams <= '0';
reg_readparams <= '1';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
State <= READPARAMS;
--------------------------------------------------------------------
-- when "1000" =>-- read_source
-- dat_o <= "000000000000000000000000000000" & rsu_readsource;
-- --read_source <= dat_i(1 downto 0);
-- reg_writeparams <= '0';
-- reg_readparams <= '0';
-- rsu_reconfig <= '0';
-- rsu_resettimer <= '0';
-- State <= START;
when others =>
dat_o <= (others => '-');
ack_o <= '0';
halt_o <= '0';
State <= START;
end case;
end if; -- we_i
else -- stb=0
ack_o <= '0';
halt_o <= '0';
State <= START;
end if; -- stb -
WHEN READSOURCE =>
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
halt_o <= '0';
ack_o <= '1';
State <= WAIT2;
WHEN WRITEPARAMS =>
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
halt_o <= '1';
ack_o <= '0';
State <= BUSY;
WHEN READPARAMS =>
reg_writeparams <= '0';
reg_readparams <= '0';
rsu_reconfig <= '0';
rsu_resettimer <= '0';
halt_o <= '1';
ack_o <= '0';
State <= BUSY;
WHEN BUSY => -- busy reading or writing.
halt_o <= '1';
ack_o <= '0';
State <= BUSY2;
WHEN BUSY2 => -- busy reading or writing.
ack_o <= '0';
IF rsu_busy='1' THEN
State <= BUSY2;
halt_o <= '1';
ack_o <= '0';
ELSE
halt_o <= '0';
ack_o <= '1';
State <= WAIT1;
case reg_params is
--------------------------------------------------------------------
when "000" =>-- Master State machine (RO)
dat_o <= "000000000000000000000000000000" & rsu_dataout(1 downto 0);
--------------------------------------------------------------------
when "001" =>-- Force early CONF_DONE check (RW)
dat_o <= "0000000000000000000000000000000"& rsu_dataout(0);
--------------------------------------------------------------------
when "010" =>-- Watchdog Timer Value (RW) [Read: 29bits, Write: 12bits]
dat_o <= "000"&rsu_dataout(28 downto 0);
--------------------------------------------------------------------
when "011" =>-- Watchdog Enable (RW)
dat_o <= "0000000000000000000000000000000"&rsu_dataout(0);
--------------------------------------------------------------------
when "100" =>-- Boot Address (RW) [Read: 24bits, Write: 22bits]
dat_o <= "00000000"&rsu_dataout(23 downto 0);
--------------------------------------------------------------------
when "101" =>-- NA
dat_o <= (others => '-');
--------------------------------------------------------------------
when "110" =>-- Force internal OSC for state machine
dat_o <= "0000000000000000000000000000000"&rsu_dataout(0);
--------------------------------------------------------------------
when "111" =>-- Reconfigure trigger condition (RO) 5 bits
dat_o <= "000000000000000000000000000"&rsu_dataout(4 downto 0);
--------------------------------------------------------------------
when others =>
dat_o <= (others => '-');
end case;
END IF;
--State <= START;
WHEN WAIT1 =>
halt_o <= '0';
ack_o <= '0';
State <= WAIT2;
WHEN WAIT2 =>
halt_o <= '0';
ack_o <= '0';
State <= START;
WHEN others =>
State <= START;
END CASE;
END IF;
END PROCESS;
end Behavioral; --WAIT1
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoriaDeDatos is
--generic( P: integer:=32; -- ancho de palabra 32 bits
-- N: integer:=32; -- nº de palabras 32 de 32
--M: integer:= 64; -- grupos de 4 palabras (2^32 / 4)=1073741824
--tam_addr: integer:=5); -- ancho dirección 2^5=32
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic;
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end MemoriaDeDatos;
architecture Behavioral of MemoriaDeDatos is
type mem_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp_mem: mem_type:=(
"00000000000000010000000000100000",--suma
"00000000010000110000000000100000",
"00000000100001010000000000100000",
"00000000110001110000000000100000",
"00000001000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100010",--resta
"00000000000000010000000000100010",
"00000000000000010000000000100010",
"00000000000000010000000000100101",--or
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100100",--and
"00010000000000000000000000000011",--beq
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000");
begin
--registros
reg0 <= tmp_mem(conv_integer(0));
reg1 <= tmp_mem(conv_integer(1));
reg2 <= tmp_mem(conv_integer(2));
reg3 <= tmp_mem(conv_integer(3));
-- Lectura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(R = '1') then
DR <= tmp_mem(conv_integer(ADDR));
else
DR <= (DR' range => 'Z');
end if;
end if;
end process;
-- Escritura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(W = '1') then
tmp_mem(conv_integer(write_addr))<= DW;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end entity priority_encoder;
architecture rtl of priority_encoder is
signal any_previous : std_logic_vector(2**encoded_word_size-1 downto 0);
signal highest_bit_only : std_logic_vector(2**encoded_word_size-1 downto 0);
type encoded_sig_type is array(2**encoded_word_size-1 downto 0) of std_logic_vector(encoded_word_size-1 downto 0);
signal encoded_sig : encoded_sig_type;
begin
any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
encoded_sig(2**encoded_word_size-1) <= std_logic_vector(to_unsigned(2**encoded_word_size-1, encoded_word_size));
encode: for i in 2**encoded_word_size-2 downto 0 generate
begin
any_previous(i) <= input(i) or any_previous(i+1);
encoded_sig(i) <= std_logic_vector(to_unsigned(i, encoded_word_size)) when any_previous(i+1) = '0' else encoded_sig(i+1);
end generate;
output <= encoded_sig(0);
end architecture rtl; |
-- 1 bit synchronizer based of n flip-flops for clock-domain crossings.
-- drive constant `data_in` to use as a reset synchronizer
--
-- Original author: Colm Ryan
--
-- Copyright (c) 2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer is
generic (
RESET_VALUE : std_logic := '0'; -- reset value of all flip-flops in the chain
NUM_FLIP_FLOPS : natural := 2 -- number of flip-flops in the synchronizer chain
);
port(
rst : in std_logic; -- asynchronous, high-active
clk : in std_logic; -- destination clock
data_in : in std_logic;
data_out : out std_logic
);
end synchronizer;
architecture arch of synchronizer is
--synchronizer chain of flip-flops
signal sync_chain : std_logic_vector(NUM_FLIP_FLOPS-1 downto 0) := (others => RESET_VALUE);
-- Xilinx XST: disable shift-register LUT (SRL) extraction
attribute shreg_extract : string;
attribute shreg_extract of sync_chain : signal is "no";
-- Vivado: set ASYNC_REG to specify registers receive asynchronous data
-- also acts as DONT_TOUCH
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_chain : signal is "TRUE";
begin
main : process(clk, rst)
begin
if rst = '1' then
sync_chain <= (others => RESET_VALUE);
elsif rising_edge(clk) then
sync_chain <= sync_chain(sync_chain'high-1 downto 0) & data_in;
end if;
end process;
data_out <= sync_chain(sync_chain'high);
end architecture;
|
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- this block decode the Non-Return-to-Zero Inverted encoded data on USB bus.
ENTITY NRZIdecode is
port(clk, rst, data0: IN STD_LOGIC; -- data0 = data+, data1 = data-, clk goes to normal clock
enable: IN STD_LOGIC; -- when this line is high (for a clock cycle), the decoder will be updated for the current value on the BUS. Thus this line should only be high after a successful data shift in.
EOP: IN STD_LOGIC; -- END of Packet, tell the block to stop itself.
data_out: OUT STD_LOGIC -- the decoded data.
);
end NRZIdecode;
architecture NRZI of NRZIdecode is
signal data0_buf0: STD_LOGIC;
--signal nxt_data_out: STD_LOGIC;
begin
seq1: process(clk, rst, data0, enable)
begin
if rst = '0' then
data_out <= '1'; -- PAY attention here! go back to IDLE, not 0
data0_buf0 <= '1'; -- so as the data buffer.
elsif (clk'event and clk = '1') then
if EOP = '1' then
data0_buf0 <= '1'; -- idle high
else
if data0 = data0_buf0 then
data_out <= '1'; -- NRZI decoding by XOR logic on every clock cycle.
else
data_out <= '0'; -- NRZI decoding by XOR logic on every clock cycle.
end if;
end if;
end if;
if enable = '1' then
data0_buf0 <= data0; -- update stored value
end if;
end process;
end architecture;
|
entity func_test3 is
generic (NBITS: natural := 6);
end entity;
architecture fum of func_test3 is
type remains is (r0, r1, r2, r3, r4); -- remainder values
function mod5 (dividend: bit_vector) return boolean is
type remain_array is array (NBITS downto 0) of remains;
type branch is array (remains, bit) of remains;
constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
r1 => ('0' => r2, '1' => r3),
r2 => ('0' => r4, '1' => r0),
r3 => ('0' => r1, '1' => r2),
r4 => ('0' => r3, '1' => r4)
);
variable remaind: remains := r0;
variable tbit: bit_vector (NBITS - 1 downto 0) := dividend;
begin
for i in dividend'length - 1 downto 0 loop
remaind := br_table(remaind,tbit(i));
end loop;
return remaind = r0;
end function;
begin
assert mod5("101000");
end architecture;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
-- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 25.10.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
EN_BIT_0 : out std_logic; --Ausgangsvariable
EN_BIT_1 : out std_logic; --Ausgangsvariable
EN_BIT_2 : out std_logic; --Ausgangsvariable
EN_BIT_3 : out std_logic; --Ausgangsvariable
EN_BIT_4 : out std_logic; --Ausgangsvariable
EN_BIT_5 : out std_logic; --Ausgangsvariable
EN_BIT_6 : out std_logic; --Ausgangsvariable
EN_BIT_7 : out std_logic; --Ausgangsvariable
EN_BIT_8 : out std_logic; --Ausgangsvariable
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0) --Folgezustand Zahl2, binärzahl
);
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is (ST_CTRL_00, --Zustaende
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13); --19
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (19 downto 0); --Zaehler, Vektor, 20 Bit
signal n_COUNT : std_logic_vector (19 downto 0); --Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_M : std_logic_vector (19 downto 0); --Zaehler, Ausgang Master, Vektor, 20 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
constant CNTS30 : std_logic_vector := x"2625A"; --Konstanten
constant CNTT01 : std_logic_vector := x"00A2C";
constant CNTT02 : std_logic_vector := x"01E84";
constant CNTT03 : std_logic_vector := x"032DC";
constant CNTT04 : std_logic_vector := x"04735";
constant CNTT05 : std_logic_vector := x"05B8B";
constant CNTT06 : std_logic_vector := x"06FE4";
constant CNTT07 : std_logic_vector := x"08441";
constant CNTT08 : std_logic_vector := x"09872";
constant CNTT09 : std_logic_vector := x"0ACEE";
constant CNTT10 : std_logic_vector := x"0C147";
constant CNTT11 : std_logic_vector := x"0D59F";
constant CNTT12 : std_logic_vector := x"0EE09";
constant CNTT13 : std_logic_vector := x"0FA3E";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV)
begin
case SV is
when ST_CTRL_00 =>
-- VAS00
COUNT <= x"00000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
if (InAB_S = '1')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (n_COUNT >= CNTS30) --156250
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT <= COUNT+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (n_COUNT >= CNTT01) --2604
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; --Error
end if;
when ST_CTRL_05 =>
if (ERROR_QUIT = '0') -- Error nicht bestätigt
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Fehlerschleife
else --ERROR_QUIT = '1'
-- VAS00
n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
end if;
when ST_CTRL_06 =>
if (n_COUNT >= CNTT02) --7812
then
-- VAS03
n_COUNT <= COUNT+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (n_COUNT >= CNTT03) --13020
then
-- VAS04
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (n_COUNT >= CNTT04) --18229
then
-- VAS05
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (n_COUNT >= CNTT05) --23435
then
-- VAS06
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (n_COUNT >= CNTT06) --28644
then
-- VAS07
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (n_COUNT >= CNTT07) --33854
then
-- VAS08
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (n_COUNT >= CNTT08) --39062
then
-- VAS09
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (n_COUNT >= CNTT09) --44270
then
-- VAS10
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (n_COUNT >= CNTT10) --49479
then
-- VAS11
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (n_COUNT >= CNTT11) --54687
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS02
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_05; -- Error: Kein Stoppbit
else --InAB_S = '1'
-- VAS12
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (n_COUNT >= CNTT12) --60937
then
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Zaehlschleife
end if;
when ST_CTRL_12 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
COUNT <= x"00000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 1
end if;
when ST_CTRL_13 =>
if (n_COUNT >= CNTT13) --64062
then
-- VAS00
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS01
n_COUNT <= COUNT+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife Teil 2
end if;
when others => n_SV <= ST_CTRL_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
end process;
end Behavioral;
|
--========================================================================
-- mytypes.vhd :: Nova global type definitions
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.ALL;
package my_types IS
--=======================================
-- opcode formats
--=======================================
type OP_FORMAT_TYPE is (
ALU_FORMAT,
MEM_FORMAT,
LDA_FORMAT,
STA_FORMAT,
IOU_FORMAT,
EXT_FORMAT,
UII_FORMAT
);
--=======================================
-- Addressing modes
--=======================================
type ADDR_MODE_TYPE is (
ADM_OK,
ADM_EA
);
--=======================================
-- ALU operations
--=======================================
type ALU_OP_TYPE is (
COM, -- complement
NEG, -- negate
INC, -- increment
DEC, -- decrement
ADC, -- add complement
SUB, -- subtract
ADD, -- add
ANA, -- logical and
TA -- transfer A
);
--=======================================
-- Shifter control
--=======================================
type SHIFT_CTL_TYPE is (
NOP, -- no shift
LEFT, -- shift left
RIGHT, -- shift right
SWAP -- swap hi and lo bytes
);
--=======================================
-- Carry control
--=======================================
type CARRY_CTL_TYPE is (
NOP, -- no change
CLEAR, -- clear carry
SET, -- set carry
INVERT -- invert carry
);
--=======================================
-- Skip control
--=======================================
type SKIP_CTL_TYPE is (
NOP, -- no skip
SKP, -- skip
SKC, -- skip if carry zero
SNC, -- skip if carry non-zero
SZR, -- skip if result zero
SNR, -- skip if result non-zero
SEZ, -- skip if either zero
SBN, -- skip if both non-zero
SKPBN, -- skip if busy is set
SKPBZ, -- skip if busy is zero
SKPDN, -- skip if done is set
SKPDZ, -- skip if done is zero
SKPIE, -- skip if Int enabled
SKPID, -- skip if Int disabled
SKPPF, -- skip if power failed
SKPPO -- skip if power OK
);
--=======================================
-- Program flow-control functions
--=======================================
type FLOW_CTL_TYPE is (
JMP, -- jump to address
JSR, -- jump to subroutine
ISZ, -- incr and skip if zero
DSZ -- decr and skip if zero
);
--=======================================
-- address index control
--=======================================
type IDX_CTL_TYPE is (
ZPG, -- page zero
REL, -- PC relative
IDX2, -- index reg 2
IDX3 -- index reg 3
);
--=======================================
-- address index control
--=======================================
type XFER_CTL_TYPE is (
NOP, -- no I/O transfer
DIA, -- data in from buffer A
DOA, -- data out to buffer A
DIB, -- data in from buffer B
DOB, -- data out to buffer B
DIC, -- data in from buffer C
DOC, -- data out to buffer C
SKP -- skip on condition
);
--=======================================
-- I/O Unit control
--=======================================
type IOU_CTL_TYPE is (
NOP, -- no operation
SBCD, -- set busy; clear done
CBCD, -- clear busy and done
PULSE -- issue a pulse
);
--=======================================
-- Extended opcodes
--=======================================
type EXT_OP_TYPE is (
MUL, -- unsigned multiply
DIV, -- unsigned divide
MULS, -- signed multiply
DIVS, -- signed divide
SAV, -- save registers to stack
RET, -- return from subroutine
PSHA, -- push accumulator
POPA, -- push accumulator
MTSP, -- move to stack pointer
MFSP, -- move from stack pointer
MTFP, -- move to frame pointer
MFFP, -- move from frame pointer
LDB, -- load byte
STB, -- store byte
NOP -- no operation
);
--=======================================
-- Address adder operations
--=======================================
type SX_OP_TYPE is (
REL, -- Relative
INC2, -- Increment by 2
INC1, -- Increment by 1
DEC1 -- Decrement by 1
);
END my_types;
|
-- NEED RESULT: ARCH00094.P1: Multi transport transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094.P2: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094.P3: Multi transport transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: One transport transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00094: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00094
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00094(ARCH00094)
-- ENT00094_Test_Bench(ARCH00094_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00094 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= transport c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= transport c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00094.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= transport c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00094" ,
"One transport transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00094" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00094 ;
--
architecture ARCH00094 of ENT00094 is
begin
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3 )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
end process P3 ;
--
--
end ARCH00094 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00094_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00094_Test_Bench ;
--
architecture ARCH00094_Test_Bench of ENT00094_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00094 ( ARCH00094 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00094_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: xorop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_xorop IS
END tb_xorop;
ARCHITECTURE behavior OF tb_xorop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xorop PORT MAP (
A => A,
B => B,
O => O
);
A <= "0000000000000000", "1111111000111111" after 300ns;
B <= "0111011101110111", "0000000000000000" after 300ns;
end behavior;
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
--
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for <clock>_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
--END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: xorop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_xorop IS
END tb_xorop;
ARCHITECTURE behavior OF tb_xorop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xorop PORT MAP (
A => A,
B => B,
O => O
);
A <= "0000000000000000", "1111111000111111" after 300ns;
B <= "0111011101110111", "0000000000000000" after 300ns;
end behavior;
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
--
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for <clock>_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
--END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: xorop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_xorop IS
END tb_xorop;
ARCHITECTURE behavior OF tb_xorop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xorop PORT MAP (
A => A,
B => B,
O => O
);
A <= "0000000000000000", "1111111000111111" after 300ns;
B <= "0111011101110111", "0000000000000000" after 300ns;
end behavior;
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
--
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for <clock>_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
--END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 12:48:57 11/02/2015
-- Design Name:
-- Module Name: /home/ga69kaw/vhdl_system_design_lab/workspace/Exercise1/direct_implementation/tb_xorop.vhd
-- Project Name: direct_implementation
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: xorop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_xorop IS
END tb_xorop;
ARCHITECTURE behavior OF tb_xorop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(15 downto 0) := (others => '0');
signal B : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal O : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: xorop PORT MAP (
A => A,
B => B,
O => O
);
A <= "0000000000000000", "1111111000111111" after 300ns;
B <= "0111011101110111", "0000000000000000" after 300ns;
end behavior;
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
--
-- -- Stimulus process
-- stim_proc: process
-- begin
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
--
-- wait for <clock>_period*10;
--
-- -- insert stimulus here
--
-- wait;
-- end process;
--END;
|
-- $Id: sys_conf_ba3_msim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf_ba4_msim
-- Description: Definitions for tb_sramif2migui_core (bawidth=3;btyp=msim)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-16 1069 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sys_conf is
-- define constants --------------------------------------------------------
constant c_btyp_msim : string := "MSIM";
constant c_btyp_bram : string := "BRAM";
-- configure ---------------------------------------------------------------
constant sys_conf_mawidth : positive := 28;
constant sys_conf_bawidth : positive := 3; -- 64 bit data path
constant sys_conf_sawidth : positive := 19; -- msim memory size
constant sys_conf_rawidth : positive := 19; -- bram memory size
constant sys_conf_rdelay : positive := 1; -- bram read delay
constant sys_conf_btyp : string := c_btyp_msim;
end package sys_conf;
|
-------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
--
-- Written by Michael Walle <[email protected]>, 2010.
-- Based on fjmem_config_pack_spartan3-p.vhd by Arnim Laeuger.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package fjmem_config_pack is
-----------------------------------------------------------------------------
-- Specify the active levels of trst_i, shift_i and res_i
--
constant trst_act_level_c : std_logic := '1';
constant shift_act_level_c : std_logic := '1';
constant res_act_level_c : std_logic := '1';
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Adapt the number of used blocks and the number of bits that are
-- required for the block field (2 ** num_block_field_c >= num_blocks_c)
--
-- number of used blocks
constant num_blocks_c : natural := 2;
-- number of bits for block field
constant num_block_field_c : natural := 1;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Don't change the array type
--
type block_desc_t is
record
addr_width : natural;
data_width : natural;
end record;
type block_array_t is array (natural range 0 to num_blocks_c-1) of block_desc_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fill in the array for all your used blocks
--
constant blocks_c : block_array_t :=
((addr_width => 24, -- block #0, FLASH
data_width => 16),
(addr_width => 8, -- block #1, dummy
data_width => 8)
);
--
-- And specify the maximum address and data width
--
constant max_addr_width_c : natural := 24;
constant max_data_width_c : natural := 16;
--
-----------------------------------------------------------------------------
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Wed Oct 18 11:23:39 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.vhdl
-- Design : srio_gen2_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
sys_clkp : in STD_LOGIC;
sys_clkn : in STD_LOGIC;
sys_rst : in STD_LOGIC;
log_clk_out : out STD_LOGIC;
phy_clk_out : out STD_LOGIC;
gt_clk_out : out STD_LOGIC;
gt_pcs_clk_out : out STD_LOGIC;
drpclk_out : out STD_LOGIC;
refclk_out : out STD_LOGIC;
clk_lock_out : out STD_LOGIC;
cfg_rst_out : out STD_LOGIC;
log_rst_out : out STD_LOGIC;
buf_rst_out : out STD_LOGIC;
phy_rst_out : out STD_LOGIC;
gt_pcs_rst_out : out STD_LOGIC;
gt0_qpll_clk_out : out STD_LOGIC;
gt0_qpll_out_refclk_out : out STD_LOGIC;
srio_rxn0 : in STD_LOGIC;
srio_rxp0 : in STD_LOGIC;
srio_rxn1 : in STD_LOGIC;
srio_rxp1 : in STD_LOGIC;
srio_txn0 : out STD_LOGIC;
srio_txp0 : out STD_LOGIC;
srio_txn1 : out STD_LOGIC;
srio_txp1 : out STD_LOGIC;
s_axis_iotx_tvalid : in STD_LOGIC;
s_axis_iotx_tready : out STD_LOGIC;
s_axis_iotx_tlast : in STD_LOGIC;
s_axis_iotx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axis_iotx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_iotx_tuser : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_iorx_tvalid : out STD_LOGIC;
m_axis_iorx_tready : in STD_LOGIC;
m_axis_iorx_tlast : out STD_LOGIC;
m_axis_iorx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axis_iorx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_iorx_tuser : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rst : in STD_LOGIC;
s_axi_maintr_awvalid : in STD_LOGIC;
s_axi_maintr_awready : out STD_LOGIC;
s_axi_maintr_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_wvalid : in STD_LOGIC;
s_axi_maintr_wready : out STD_LOGIC;
s_axi_maintr_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_bvalid : out STD_LOGIC;
s_axi_maintr_bready : in STD_LOGIC;
s_axi_maintr_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_maintr_arvalid : in STD_LOGIC;
s_axi_maintr_arready : out STD_LOGIC;
s_axi_maintr_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rvalid : out STD_LOGIC;
s_axi_maintr_rready : in STD_LOGIC;
s_axi_maintr_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_maintr_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
sim_train_en : in STD_LOGIC;
force_reinit : in STD_LOGIC;
phy_mce : in STD_LOGIC;
phy_link_reset : in STD_LOGIC;
phy_rcvd_mce : out STD_LOGIC;
phy_rcvd_link_reset : out STD_LOGIC;
phy_debug : out STD_LOGIC_VECTOR ( 223 downto 0 );
gtrx_disperr_or : out STD_LOGIC;
gtrx_notintable_or : out STD_LOGIC;
port_error : out STD_LOGIC;
port_timeout : out STD_LOGIC_VECTOR ( 23 downto 0 );
srio_host : out STD_LOGIC;
port_decode_error : out STD_LOGIC;
deviceid : out STD_LOGIC_VECTOR ( 15 downto 0 );
idle2_selected : out STD_LOGIC;
phy_lcl_master_enable_out : out STD_LOGIC;
buf_lcl_response_only_out : out STD_LOGIC;
buf_lcl_tx_flow_control_out : out STD_LOGIC;
buf_lcl_phy_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_next_fm_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_last_ack_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_phy_rewind_out : out STD_LOGIC;
phy_lcl_phy_rcvd_buf_stat_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
phy_lcl_maint_only_out : out STD_LOGIC;
port_initialized : out STD_LOGIC;
link_initialized : out STD_LOGIC;
idle_selected : out STD_LOGIC;
mode_1x : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_txn0,srio_txp0,srio_txn1,srio_txp1,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "srio_gen2_v4_0_5,Vivado 2015.1.0";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1038.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01038pkg is
type THREE is range 1 to 3;
type A2 is array (THREE, THREE) of BOOLEAN;
function Af2 (g : integer) return A2;
end c06s04b00x00p02n01i01038pkg;
package body c06s04b00x00p02n01i01038pkg is
function Af2 (g : integer) return A2 is
variable vaf1 : A2;
begin
return Vaf1;
end Af2;
end c06s04b00x00p02n01i01038pkg;
use work.c06s04b00x00p02n01i01038pkg.all;
ENTITY c06s04b00x00p02n01i01038ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT2 : A2;
attribute AT2 of PT : signal is Af2(g) ;
END c06s04b00x00p02n01i01038ent;
ARCHITECTURE c06s04b00x00p02n01i01038arch OF c06s04b00x00p02n01i01038ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT2(2, 3);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01038"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01038 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01038arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1038.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01038pkg is
type THREE is range 1 to 3;
type A2 is array (THREE, THREE) of BOOLEAN;
function Af2 (g : integer) return A2;
end c06s04b00x00p02n01i01038pkg;
package body c06s04b00x00p02n01i01038pkg is
function Af2 (g : integer) return A2 is
variable vaf1 : A2;
begin
return Vaf1;
end Af2;
end c06s04b00x00p02n01i01038pkg;
use work.c06s04b00x00p02n01i01038pkg.all;
ENTITY c06s04b00x00p02n01i01038ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT2 : A2;
attribute AT2 of PT : signal is Af2(g) ;
END c06s04b00x00p02n01i01038ent;
ARCHITECTURE c06s04b00x00p02n01i01038arch OF c06s04b00x00p02n01i01038ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT2(2, 3);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01038"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01038 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01038arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1038.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s04b00x00p02n01i01038pkg is
type THREE is range 1 to 3;
type A2 is array (THREE, THREE) of BOOLEAN;
function Af2 (g : integer) return A2;
end c06s04b00x00p02n01i01038pkg;
package body c06s04b00x00p02n01i01038pkg is
function Af2 (g : integer) return A2 is
variable vaf1 : A2;
begin
return Vaf1;
end Af2;
end c06s04b00x00p02n01i01038pkg;
use work.c06s04b00x00p02n01i01038pkg.all;
ENTITY c06s04b00x00p02n01i01038ent IS
generic (g : integer := 2);
port (PT: BOOLEAN) ;
attribute AT2 : A2;
attribute AT2 of PT : signal is Af2(g) ;
END c06s04b00x00p02n01i01038ent;
ARCHITECTURE c06s04b00x00p02n01i01038arch OF c06s04b00x00p02n01i01038ent IS
BEGIN
TESTING: PROCESS
variable V: BOOLEAN;
BEGIN
V := PT'AT2(2, 3);
assert NOT(V=false)
report "***PASSED TEST: c06s04b00x00p02n01i01038"
severity NOTE;
assert (V=false)
report "***FAILED TEST: c06s04b00x00p02n01i01038 - Indexed name be an attribute name test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p02n01i01038arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz : entity is "system_clk_wiz_0_0_clk_wiz";
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 36.500000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
entity snum04 is
port (ok : out boolean);
end snum04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum04 is
-- add uns nat
constant a1 : unsigned (7 downto 0) := x"1d";
constant b1 : unsigned (3 downto 0) := x"5";
constant r1 : unsigned (11 downto 0) := a1 * b1;
signal er1 : unsigned (11 downto 0) := x"091";
begin
-- ok <= r1 = x"20";
ok <= r1 = er1;
end behav;
|
entity sub is
generic ( W : natural );
port ( o : out bit_vector(1 to 2);
p : in bit_vector(1 to W) );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity directmap3 is
end entity;
architecture test of directmap3 is
constant K : natural := 4;
signal o1, o2 : bit;
signal p : bit_vector(1 to 3);
begin
u: entity work.sub
generic map ( K - 1 )
port map ( o(1) => o1, o(2) => o2, p => p );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.fLink_definitions.ALL;
entity loopbackDevice_v1_0_S00_AXI is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end loopbackDevice_v1_0_S00_AXI;
architecture arch_imp of loopbackDevice_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rlast : std_logic;
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS => '0');
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4,C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_register_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4,C_S_AXI_ADDR_WIDTH));
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0013";
CONSTANT subtype_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
CONSTANT interface_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');
CONSTANT number_of_channels : INTEGER range 0 to 100 := 8;
TYPE t_mem_reg IS ARRAY(number_of_channels-1 downto 0) OF STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
CONSTANT REG_RESET : t_mem_reg := ((OTHERS=> (OTHERS=>'0')));
SIGNAL mem_reg : t_mem_reg := REG_RESET;
SIGNAL mem_reg_next : t_mem_reg := REG_RESET;
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= (OTHERS => '0');
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= (OTHERS => '0');
S_AXI_RLAST <= axi_rlast;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
IF(S_AXI_AWSIZE = "000") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_AWSIZE = "001") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_AWSIZE = "010") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_AWSIZE = "011") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_AWSIZE = "100") THEN
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_awaddr <= axi_awaddr;
END IF;
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
IF(S_AXI_ARSIZE = "000") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 1);
ELSIF(S_AXI_ARSIZE = "001") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 2);
ELSIF(S_AXI_ARSIZE = "010") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 4);
ELSIF(S_AXI_ARSIZE = "011") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 8);
ELSIF(S_AXI_ARSIZE = "100") THEN
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto 0)) + 16);
ELSE
axi_araddr <= axi_araddr;
END IF;
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
--read data
process( axi_rvalid,axi_araddr,mem_reg ) is
VARIABLE reg_number: INTEGER := 0;
begin
if (axi_rvalid = '1') then
-- output the read dada
IF(axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF(axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF(axi_araddr = c_number_of_channels_address)THEN
axi_rdata <= std_logic_vector(to_unsigned(number_of_channels, axi_rdata'length));
ELSIF(axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF(axi_araddr >= c_usig_register_address) THEN
reg_number := (to_integer(unsigned(axi_araddr)) - to_integer(UNSIGNED(c_usig_register_address)))/4;
axi_rdata <= mem_reg(reg_number);
ELSE
axi_rdata <= (others => '0');
END IF;
else
axi_rdata <= (others => '0');
end if;
end process;
process( axi_wready,S_AXI_WVALID,S_AXI_WDATA,mem_reg,axi_awaddr,S_AXI_WSTRB)
VARIABLE reg_number: INTEGER := 0;
VARIABLE v_mem_reg: t_mem_reg := REG_RESET;
BEGIN
v_mem_reg := mem_reg;
IF(axi_wready = '1') THEN
IF(axi_awaddr >= c_usig_register_address) THEN
reg_number := (to_integer(unsigned(axi_awaddr)) - to_integer(UNSIGNED(c_usig_register_address)))/4;
IF(S_AXI_WSTRB(0) = '1')THEN
v_mem_reg(reg_number)(7 DOWNTO 0) := S_AXI_WDATA(7 DOWNTO 0);
END IF;
IF(S_AXI_WSTRB(1) = '1')THEN
v_mem_reg(reg_number)(15 DOWNTO 8) := S_AXI_WDATA(15 DOWNTO 8);
END IF;
IF(S_AXI_WSTRB(2) = '1')THEN
v_mem_reg(reg_number)(23 DOWNTO 16) := S_AXI_WDATA(23 DOWNTO 16);
END IF;
IF(S_AXI_WSTRB(3) = '1')THEN
v_mem_reg(reg_number)(31 DOWNTO 24) := S_AXI_WDATA(31 DOWNTO 24);
END IF;
END IF;
END IF;
mem_reg_next <= v_mem_reg;
END PROCESS;
reg_proc : PROCESS (S_AXI_ACLK)
BEGIN
IF rising_edge(S_AXI_ACLK) THEN
mem_reg <= mem_reg_next;
END IF;
END PROCESS reg_proc;
-- Add user logic here
-- User logic ends
end arch_imp;
|
-------------------------------------------------------------------------------
--
-- $Id$
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
--
-- Written by Arnim Laeuger <[email protected]>, 2008.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package fjmem_config_pack is
-----------------------------------------------------------------------------
-- Specify the active levels of trst_i, shift_i and res_i
--
constant trst_act_level_c : std_logic := '1';
constant shift_act_level_c : std_logic := '1';
constant res_act_level_c : std_logic := '1';
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Adapt the number of used blocks and the number of bits that are
-- required for the block field (2 ** num_block_field_c >= num_blocks_c)
--
-- number of used blocks
constant num_blocks_c : natural := 4;
-- number of bits for block field
constant num_block_field_c : natural := 2;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Don't change the array type
--
type block_desc_t is
record
addr_width : natural;
data_width : natural;
end record;
type block_array_t is array (natural range 0 to num_blocks_c-1) of block_desc_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fill in the array for all your used blocks
--
constant blocks_c : block_array_t :=
((addr_width => 18, -- block #0
data_width => 16),
(addr_width => 18, -- block #1
data_width => 16),
(addr_width => 19, -- block #2
data_width => 8),
(addr_width => 8, -- block #3
data_width => 8)
);
--
-- And specify the maximum address and data width
--
constant max_addr_width_c : natural := 19;
constant max_data_width_c : natural := 16;
--
-----------------------------------------------------------------------------
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity complemento4 is
Port ( entrada : in STD_LOGIC_VECTOR (3 downto 0) := "0000";
sel : in STD_LOGIC := '1';
saida : out STD_LOGIC_VECTOR (3 downto 0)
);
end complemento4;
architecture Behavioral of complemento4 is
signal aux : STD_LOGIC_VECTOR (3 downto 0);
begin
process (entrada,sel,aux)
begin
if (sel = '1') then
aux <= entrada xor "1111";
else
aux <= entrada;
end if;
end process;
saida <= aux;
end Behavioral;
|
--Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_A26CnV
-- /___/ /\ Timestamp : 04/06/2014 00:33:30
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
entity AddressGenerator is
port ( busy_in : in std_logic;
clk : in std_logic;
imgBaseAddr : in std_logic_vector (31 downto 0);
kptCoordX : in std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : in std_logic_vector (KPT_COORD_BW-1 downto 0); --keypoint's row possition
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
kptOctave : in std_logic_vector(KPT_OCTAVE_BW-1 downto 0);--keypoint's octave
request_in : in std_logic;
rst : in std_logic;
kptScaleOut : out std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
addr : out std_logic_vector (31 downto 0);
busy_out : out std_logic;
request_out : out std_logic
);
end AddressGenerator;
architecture BEHAVIORAL of AddressGenerator is
type points_coord_type is array(11 downto 0) of integer range -23 to 23;
type rom_coord_type is array (20 downto 0) of points_coord_type;
--coordinates of each point on the retina pattern, from OUTER to INNER
constant rom_coord_data : rom_coord_type :=
(
0 => (23,0,12,20,-12,20,-23,0,-12,-20,12,-20),
1 => (15,9,0,17,-15,9,-15,-9,0,-17,15,-9),
2 => (13,0,6,11,-6,11,-13,0,-6,-11,6,-11),
3 => (8,4,0,9,-8,4,-8,-4,0,-9,8,-4),
4 => (6,0,3,5,-3,5,-6,0,-3,-5,3,-5),
5 => (3,2,0,4,-3,2,-3,-2,0,-4,3,-2),
6 => (3,0,1,3,-1,3,-3,0,-1,-3,1,-3),
7 => (18,0,9,16,-9,16,-18,0,-9,-16,9,-16),
8 => (12,7,0,14,-12,7,-12,-7,0,-14,12,-7),
9 => (10,0,5,9,-5,9,-10,0,-5,-9,5,-9),
10 => (6,3,0,7,-6,3,-6,-3,0,-7,6,-3),
11 => (5,0,2,4,-2,4,-5,0,-2,-4,2,-4),
12 => (3,2,0,3,-3,2,-3,-2,0,-3,3,-2),
13 => (2,0,1,2,-1,2,-2,0,-1,-2,1,-2),
14 => (15,0,7,13,-7,13,-15,0,-7,-13,7,-13),
15 => (10,5,0,11,-10,6,-10,-5,0,-11,10,-5),
16 => (8,0,4,7,-4,7,-8,0,-4,-7,4,-7),
17 => (5,3,0,6,-5,3,-5,-3,0,-6,5,-3),
18 => (4,0,2,3,-2,3,-4,0,-2,-3,2,-3),
19 => (2,1,0,2,-2,1,-2,-1,0,-2,2,-1),
20 => (2,0,1,2,-1,2,-2,0,-1,-2,1,-2)
);
signal point_set_id: integer range 0 to 7;--describes each point set included the center of the retina pattern(the keypoint's possition)
signal point_addr: std_logic_vector(31 downto 0);
signal select_pair: integer range 0 to 5;
type consumer_FSM_states is (INIT, REQ, WAITING, READY);
signal s_consumerState: consumer_FSM_states;
type producer_FSM_states is (INIT, REQ);
signal s_producerState: producer_FSM_states;
begin
consumer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_consumerState <= INIT;
request_out <= '0';
else
case s_consumerState is
when INIT =>
if busy_in = '0' then
request_out <= '1';
s_consumerState <= REQ;
end if;
when REQ =>
if busy_in = '1' then
request_out <= '0';
s_consumerState <= WAITING;
end if;
when WAITING =>
if busy_in = '0' then
s_consumerState <= READY;
end if;
when READY =>
if select_pair = 5 and point_set_id = 7 then
s_consumerState <= INIT;
end if;
end case;
end if;
end if;
end process;
producer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_producerState <= INIT;
busy_out <= '0';
else
case s_producerState is
when INIT =>
if request_in = '1' then
busy_out <= '1';
s_producerState <= REQ;
end if;
when REQ =>
if s_consumerState = READY then
busy_out <= '0';
s_producerState <= INIT;
end if;
end case;
end if;
end if;
end process;
addr_generation_proc: process(clk)
--variable tmp1: integer range -1023 to 1023;
--variable tmp2: integer range -1023*IMAGE_WIDTH to 1023*IMAGE_WIDTH;
variable coordArray: points_coord_type;
begin
if rising_edge(clk) then
if rst = '1' then
point_set_id <= 0;
select_pair <= 5;
point_addr <= (others => '0');
kptScaleOut <= (others => '0');
elsif s_consumerState = READY and s_producerState = REQ then
if point_set_id = 7 then
point_addr <= std_logic_vector(
to_unsigned(
to_integer(unsigned(imgBaseAddr)) +
to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
to_integer(unsigned(kptCoordX)) +
(to_integer(unsigned(kptCoordY)))*IMAGE_WIDTH
, point_addr'length)
);
else
coordArray := rom_coord_data(point_set_id + 7*to_integer(unsigned(kptScale)));
point_addr <= std_logic_vector(
to_unsigned(
to_integer(unsigned(imgBaseAddr)) +
to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
to_integer(unsigned(kptCoordX)) + coordArray(select_pair*2+1) +
(to_integer(unsigned(kptCoordY)) + coordArray(select_pair*2))*IMAGE_WIDTH
, point_addr'length)
);
end if;
-- if point_set_id = 7 then
-- tmp1 := to_integer(unsigned(kptCoordX));
-- tmp2 := (to_integer(unsigned(kptCoordY)))*IMAGE_WIDTH;
-- else
-- coordArray := rom_coord_data(point_set_id + 7*to_integer(unsigned(kptScale)));
-- tmp1 := to_integer(unsigned(kptCoordX)) + coordArray(select_pair*2+1);--column possition offset
-- tmp2 := (to_integer(unsigned(kptCoordY)) + coordArray(select_pair*2))*IMAGE_WIDTH;--row possition offset
-- end if;
-- point_addr <= std_logic_vector(
-- to_unsigned(
-- to_integer(unsigned(imgBaseAddr)) +
-- to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
--
-- tmp1 + tmp2
--
--
-- , point_addr'length)
-- );
kptScaleOut <= kptScale;
if point_set_id = 7 then
point_set_id <= 0;
select_pair <= 5;
elsif select_pair = 0 then
select_pair <= 5;
point_set_id <= point_set_id + 1;
else
select_pair <= select_pair -1;
end if;
end if;
end if;--rising_edge(clk)
end process;
addr <= point_addr;
end BEHAVIORAL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0; -- Internal req and gnt signals
drivereset : integer := 0; -- Drive PCI rst with outpad
constidsel : integer := 0; -- pci_idsel is tied to local constant
level : integer := pci33; -- input/output level
voltage : integer := x33v -- input/output voltage
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) --:= conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
-- Reset
rstpad : if noreset = 0 generate
nodrive: if drivereset = 0 generate
pci_rst_pad : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => 0)
port map (pci_rst, pcio.rst, pcii.rst);
end generate nodrive;
drive: if drivereset /= 0 generate
pci_rst_pad : outpad generic map (tech => padtech, level => level,
voltage => voltage)
port map (pci_rst, pcio.rst);
pcii.rst <= pcio.rst;
end generate drive;
end generate;
norstpad : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
localgnt: if onchipreqgnt = 1 generate
pcii.gnt <= pci_gnt;
pci_req <= pcio.req when pcio.reqen = conv_std_logic(oepol=1) else '1';
end generate localgnt;
extgnt: if onchipreqgnt = 0 generate
pad_pci_gnt : inpad generic map (padtech, level, voltage) port map (pci_gnt, pcii.gnt);
pad_pci_req : toutpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
end generate extgnt;
idsel_pad: if constidsel = 0 generate
pad_pci_idsel : inpad generic map (padtech, level, voltage) port map (pci_idsel, pcii.idsel);
end generate idsel_pad;
idsel_local: if constidsel /= 0 generate
pcii.idsel <= pci_idsel;
end generate idsel_local;
onlyhost : if host = 2 generate
pcii.host <= '0'; -- Always host
end generate;
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, level, voltage) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
do66 : if no66 = 0 generate
pad_pci_66 : inpad generic map (padtech, level, voltage) port map (pci_66, pcii.pci66);
end generate;
dono66 : if no66 = 1 generate
pcii.pci66 <= '0';
end generate;
pad_pci_lock : iopad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => level,
voltage => voltage, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_serr : iopad generic map (tech => padtech, level => level, voltage => voltage, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int = 14 => PCI_INT[A,B,C,D] = in
-- int = 100 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 101 => PCI_INT[A,B] = out, PCI_INT[C,D] = Not connected
-- int = 102 => PCI_INT[A,B,C] = out, PCI_INT[D] = Not connected
-- int = 103 => PCI_INT[A,B,C,D] = out
-- int = 110 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 111 => PCI_INT[A,B] = inout, PCI_INT[C,D] = in
-- int = 112 => PCI_INT[A,B,C] = inout, PCI_INT[D] = in
-- int = 113 => PCI_INT[A,B,C,D] = inout
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xonon : if i /= int - 1 and int < 10 and int < 100 generate
pci_int(i) <= '1';
end generate;
xio : if i = (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 and int < 100 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
x2o : if i <= (int - 100) and int < 110 and int >= 100 generate
pad_pci_int : odpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i));
end generate;
x2onon : if i > (int - 100) and int < 110 and int >= 100 generate
pci_int(i) <= '1';
end generate;
x2oi : if i <= (int - 110) and int >= 110 generate
pad_pci_int : iodpad generic map (tech => padtech, level => level,
voltage => voltage, oepol => oepol)
port map (pci_int(i), pcio.vinten(i), pcii.int(i));
end generate;
x2i : if i > (int - 110) and int >= 110 generate
pad_pci_int : inpad generic map (tech => padtech, level => level, voltage => voltage)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
nointerrupt : if int = 0 generate
pcii.int <= (others => '0');
end generate;
pcii.pme_status <= '0';
end;
|
---------------------------------------------------------------------------
-- edge-detector.vhd --
-- Raj Vinjamuri --
-- 3-13 --
-- --
-- Purpose/Description --
-- Takes FPGA clock and ps2Clk and outputs rising/falling/0/1 --
-- --
-- --
-- --
-- Final Modifications by Raj Vinjamuri and Sai Koppula --
-- --
-- --
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity edge_detector is
Port ( mod_Clk, ps2Clk : in std_logic;
status : out std_logic_vector(1 downto 0));
end edge_detector;
architecture Behavioral of edge_detector is
component Dreg is
port( D, clk, reset, ld: in std_logic;
Q : out std_logic);
end component Dreg;
signal chain : std_logic_vector(1 downto 0); --internal bus to hold outputs
begin
dff1: Dreg
port map( D => ps2Clk,
clk => mod_clk,
reset => '0',
ld => '1',
Q => chain(0)); --feeds into other d-ff
dff2: Dreg
port map( D => chain(0),
clk => mod_clk,
reset => '0',
ld => '1',
Q => chain(1));
status <= chain; --set output
end Behavioral; |
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo'length;
end;
begin
result := nested_function;
end;
end package body;
-------------------------------------------------------------------------------
entity issue123 is
end entity;
use work.nested_function_bug.all;
architecture test of issue123 is
begin
process is
variable result : integer;
begin
proc(5, result);
assert result = 6;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo'length;
end;
begin
result := nested_function;
end;
end package body;
-------------------------------------------------------------------------------
entity issue123 is
end entity;
use work.nested_function_bug.all;
architecture test of issue123 is
begin
process is
variable result : integer;
begin
proc(5, result);
assert result = 6;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo'length;
end;
begin
result := nested_function;
end;
end package body;
-------------------------------------------------------------------------------
entity issue123 is
end entity;
use work.nested_function_bug.all;
architecture test of issue123 is
begin
process is
variable result : integer;
begin
proc(5, result);
assert result = 6;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo'length;
end;
begin
result := nested_function;
end;
end package body;
-------------------------------------------------------------------------------
entity issue123 is
end entity;
use work.nested_function_bug.all;
architecture test of issue123 is
begin
process is
variable result : integer;
begin
proc(5, result);
assert result = 6;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
variable foo : bit_vector(0 to param);
impure function nested_function return integer is
begin
return foo'length;
end;
begin
result := nested_function;
end;
end package body;
-------------------------------------------------------------------------------
entity issue123 is
end entity;
use work.nested_function_bug.all;
architecture test of issue123 is
begin
process is
variable result : integer;
begin
proc(5, result);
assert result = 6;
wait;
end process;
end architecture;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
end entity FIFO;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
|
------------------------------------
-- 32 BIT CARRY LOOK AHEAD ADDER --
-- PORT MAPPING --
-- A : 32 bit input value --
-- B : 32 bit input value --
-- CIN : 1 bit input carry --
------------------------------------
-- C : 32 bit output value A+B --
-- COUT : 1 bit output carry --
------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder IS
PORT
(
in_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_cin : IN STD_LOGIC;
---------------------------------------------
out_c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_cout : OUT STD_LOGIC
);
END adder;
ARCHITECTURE behavioral OF adder IS
-- Sum values without carry
SIGNAL s_sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry generators
SIGNAL s_generate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry propagators
SIGNAL s_propagate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Calculated carry values
SIGNAL s_carry : STD_LOGIC_VECTOR(31 DOWNTO 1);
BEGIN
-- Calculate the sum a + b discarding carry
s_sum <= in_a XOR in_b;
-- Calculate carry generators
s_generate <= in_a AND in_b;
-- Calculate carry propagators
s_propagate <= in_a OR in_b;
-- Pre calculate each carry
PROCESS(s_generate, s_propagate, s_carry, in_cin)
BEGIN
-- C(i+1) = G(i) + (P(i)C(i))
-- Calculate base case
s_carry(1) <= s_generate(0) OR (s_propagate(0) AND in_cin);
FOR i IN 1 TO 30 LOOP
-- Recursively calculate all intermediate carries
s_carry(i + 1) <= s_generate(i) OR (s_propagate(i) AND s_carry(i));
END LOOP;
-- Calculate carry out --
out_cout <= s_generate(31) OR (s_propagate(31) AND s_carry(31));
END PROCESS;
-- Calculate final sum --
out_c(0) <= s_sum(0) XOR in_cin;
out_c(31 DOWNTO 1) <= s_sum(31 DOWNTO 1) XOR s_carry(31 DOWNTO 1);
END behavioral; |
-------------------------------------------------------------------------------
--! @file onewire_control.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Control all 1-wire interfaces.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
use work.onewire_idtemp_pkg.all;
--! @brief Entity declaration of onewire_control
entity onewire_control is
generic (
--! System clock frequency in Hz
clk_frequency_g : natural := 40e6;
--! Maximum number of devices on a bus
max_devices_g : positive := 16);
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Status and control signals
--! @{
--! Discover devices on the 1-wire bus
discover_i : in std_ulogic;
--! Convert and retrieve temperature values
get_temp_i : in std_ulogic;
--! Busy flag
busy_o : out std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! Number of detected devices
device_count_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g + 1)))) - 1 downto 0);
--! Error flag if too many devices are detected
error_too_many_o : out std_ulogic;
--! Enable strong pull-up circuit to provide more current during temperature conversion
strong_pullup_o : out std_ulogic;
--! @}
--! @name Internal signals
--! @{
--! Start search algorithm
discover_o : out std_ulogic;
--! Discovered device ID enable
id_en_i : in std_ulogic;
--! Done flag
done_i : in std_ulogic;
--! @}
--! @name Memory interface signals
--! @{
--! Write address
mem_wr_addr_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g * 2)))) - 1 downto 0);
--! Write enable
mem_wr_en_o : out std_ulogic;
--! Data output
mem_wr_data_o : out std_ulogic_vector(63 downto 0);
--! Write done flag
mem_wr_done_i : in std_ulogic;
--! Read address
mem_rd_addr_o : out std_ulogic_vector(natural(ceil(log2(real(max_devices_g * 2)))) - 1 downto 0);
--! Read enable
mem_rd_en_o : out std_ulogic;
--! Data input
mem_rd_data_i : in std_ulogic_vector(63 downto 0);
--! Data input enable
mem_rd_data_en_i : in std_ulogic;
--! @}
--! @name Bus interface signals
--! @{
--! Send a bus reset command
bus_rst_o : out std_ulogic;
--! Send data bit
bit_send_o : out std_ulogic;
--! The data bit to be sent
bit_o : out std_ulogic;
--! Receive data bit
bit_recv_o : out std_ulogic;
--! The received data bit
bit_i : in std_ulogic;
--! The received data bit enable
bit_en_i : in std_ulogic;
--! Done flag
bit_done_i : in std_ulogic);
--! @}
end entity onewire_control;
--! RTL implementation of onewire_control
architecture rtl of onewire_control is
-----------------------------------------------------------------------------
--! @name Types and Constants
-----------------------------------------------------------------------------
--! @{
--! Time to hold strong pull-up high during conversion
constant t_pullup_c : real := 0.750;
--! Time to recover from strong pull-up
constant t_pullup_recvr_c : real := t_pullup_c + 0.000002;
constant clk_period_c : real := 1.0 / real(clk_frequency_g);
constant cnt_pullup_c : natural := natural(ceil(t_pullup_c / clk_period_c));
constant cnt_pullup_recvr_c : natural := natural(ceil(t_pullup_recvr_c / clk_period_c));
constant lfsr_len_c : natural := lfsr_length(cnt_pullup_recvr_c);
subtype lfsr_t is std_ulogic_vector(lfsr_len_c - 1 downto 0);
constant lfsr_seed_c : lfsr_t := lfsr_seed(lfsr_len_c);
constant max_id_c : lfsr_t := lfsr_shift(lfsr_seed_c, mem_wr_data_o'length - 1);
constant max_cmd_c : lfsr_t := lfsr_shift(lfsr_seed_c, cmd_match_c'length - 1);
constant max_pullup_c : lfsr_t := "1110100111110000010100010"; --lfsr_shift(lfsr_seed_c, cnt_pullup_c - 1);
constant max_pullup_recvr_c : lfsr_t := "0101100010000101001011101"; --lfsr_shift(lfsr_seed_c, cnt_pullup_recvr_c - 1);
type state_t is (IDLE, ERASE, DISCOVER, CONVERT, SKIP_COMMAND, CONVERT_COMMAND,
WAIT_CONVERSION, WAIT_RESET, MATCH_COMMAND, GET_ID, SEND_ID, READ_COMMAND,
SCRATCHPAD, SCRATCHPAD_CRC, SAVE_DATA, CHECK_NUM);
type reg_t is record
state : state_t;
lfsr : lfsr_t;
busy : std_ulogic;
done : std_ulogic;
device_count : unsigned(device_count_o'range);
too_many : std_ulogic;
strong_pullup : std_ulogic;
discover : std_ulogic;
mem_addr : unsigned(mem_wr_addr_o'range);
mem_wr_en : std_ulogic;
mem_rd_en : std_ulogic;
crc_reset : std_ulogic;
bus_rst : std_ulogic;
bit_send : std_ulogic;
bit_recv : std_ulogic;
data : std_ulogic_vector(mem_wr_data_o'range);
end record;
constant init_c : reg_t := (
state => IDLE,
lfsr => lfsr_seed_c,
busy => '0',
done => '0',
device_count => to_unsigned(0, device_count_o'length),
too_many => '0',
strong_pullup => '0',
discover => '0',
mem_addr => to_unsigned(0, mem_wr_addr_o'length),
mem_wr_en => '0',
mem_rd_en => '0',
crc_reset => '0',
bus_rst => '0',
bit_send => '0',
bit_recv => '0',
data => (others => '0'));
--! @}
-----------------------------------------------------------------------------
--! @name Internal Registers
-----------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
-----------------------------------------------------------------------------
--! @name Internal Wires
-----------------------------------------------------------------------------
--! @{
signal nxt_reg : reg_t;
signal crc_valid : std_ulogic;
--! @}
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
busy_o <= reg.busy;
done_o <= reg.done;
device_count_o <= std_ulogic_vector(reg.device_count);
error_too_many_o <= reg.too_many;
strong_pullup_o <= reg.strong_pullup;
discover_o <= reg.discover;
mem_wr_addr_o <= std_ulogic_vector(reg.mem_addr);
mem_wr_en_o <= reg.mem_wr_en;
mem_wr_data_o <= reg.data;
mem_rd_addr_o <= std_ulogic_vector(reg.mem_addr);
mem_rd_en_o <= reg.mem_rd_en;
bus_rst_o <= reg.bus_rst;
bit_send_o <= reg.bit_send;
bit_o <= reg.data(reg.data'low);
bit_recv_o <= reg.bit_recv;
-----------------------------------------------------------------------------
-- Instantiations
-----------------------------------------------------------------------------
crc_inst : entity work.onewire_crc
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
reset_i => reg.crc_reset,
data_i => bit_i,
data_en_i => bit_en_i,
valid_o => crc_valid);
-----------------------------------------------------------------------------
-- Registers
-----------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= nxt_reg;
end if;
end if;
end process regs;
-----------------------------------------------------------------------------
-- Combinatorics
-----------------------------------------------------------------------------
comb : process (reg, discover_i, get_temp_i, id_en_i, done_i, crc_valid,
mem_wr_done_i, mem_rd_data_i, mem_rd_data_en_i, bit_i, bit_en_i, bit_done_i) is
begin -- process comb
-- Defaults
nxt_reg <= reg;
nxt_reg.done <= init_c.done;
nxt_reg.discover <= init_c.discover;
nxt_reg.mem_wr_en <= init_c.mem_wr_en;
nxt_reg.mem_rd_en <= init_c.mem_rd_en;
nxt_reg.bus_rst <= init_c.bus_rst;
nxt_reg.bit_send <= init_c.bit_send;
nxt_reg.bit_recv <= init_c.bit_recv;
nxt_reg.crc_reset <= init_c.crc_reset;
case reg.state is
when IDLE =>
if discover_i = '1' then
nxt_reg <= init_c;
nxt_reg.busy <= '1';
nxt_reg.mem_wr_en <= '1';
nxt_reg.state <= ERASE;
elsif get_temp_i = '1' then
nxt_reg.busy <= '1';
nxt_reg.bus_rst <= '1';
nxt_reg.mem_addr <= init_c.mem_addr;
nxt_reg.state <= CONVERT;
end if;
when ERASE =>
if mem_wr_done_i = '1' then
if to_integer(reg.mem_addr) < (max_devices_g * 2) - 1 then
nxt_reg.mem_wr_en <= '1';
nxt_reg.mem_addr <= reg.mem_addr + 1;
else
nxt_reg.discover <= '1';
nxt_reg.mem_addr <= init_c.mem_addr;
nxt_reg.state <= DISCOVER;
end if;
end if;
when DISCOVER =>
if id_en_i = '1' then
nxt_reg.device_count <= reg.device_count + 1;
nxt_reg.mem_addr <= reg.mem_addr + 2;
if to_integer(reg.device_count) = max_devices_g then
nxt_reg.too_many <= '1';
end if;
end if;
if done_i = '1' then
nxt_reg.state <= IDLE;
nxt_reg.busy <= '0';
nxt_reg.done <= '1';
end if;
when CONVERT =>
if bit_done_i = '1' then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_skip_c;
nxt_reg.state <= SKIP_COMMAND;
end if;
when SKIP_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_convert_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= CONVERT_COMMAND;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when CONVERT_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.strong_pullup <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= WAIT_CONVERSION;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when WAIT_CONVERSION =>
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
if reg.lfsr = max_pullup_c then
nxt_reg.strong_pullup <= '0';
end if;
if reg.lfsr = max_pullup_recvr_c then
nxt_reg.bus_rst <= '1';
nxt_reg.state <= WAIT_RESET;
end if;
when WAIT_RESET =>
if bit_done_i = '1' then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_match_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= MATCH_COMMAND;
end if;
when MATCH_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.mem_rd_en <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= GET_ID;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when GET_ID =>
if mem_rd_data_en_i = '1' then
if mem_rd_data_i(7 downto 0) = code_ds18b20_c then
nxt_reg.data <= mem_rd_data_i;
nxt_reg.bit_send <= '1';
nxt_reg.state <= SEND_ID;
else
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.state <= CHECK_NUM;
end if;
end if;
when SEND_ID =>
if bit_done_i = '1' then
if reg.lfsr = max_id_c then
nxt_reg.bit_send <= '1';
nxt_reg.data(7 downto 0) <= cmd_read_sp_c;
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= READ_COMMAND;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when READ_COMMAND =>
if bit_done_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.bit_recv <= '1';
nxt_reg.crc_reset <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= SCRATCHPAD;
else
nxt_reg.bit_send <= '1';
nxt_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SCRATCHPAD =>
if bit_en_i = '1' then
nxt_reg.data <= bit_i & reg.data(reg.data'high downto reg.data'low + 1);
if reg.lfsr = max_id_c then
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= init_c.lfsr;
nxt_reg.state <= SCRATCHPAD_CRC;
else
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SCRATCHPAD_CRC =>
if bit_en_i = '1' then
if reg.lfsr = max_cmd_c then
nxt_reg.state <= SAVE_DATA;
else
nxt_reg.bit_recv <= '1';
nxt_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
end if;
when SAVE_DATA =>
if crc_valid = '0' then
nxt_reg.data <= (others => '1');
end if;
nxt_reg.mem_wr_en <= '1';
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.state <= CHECK_NUM;
when CHECK_NUM =>
if reg.mem_addr < (max_devices_g * 2) - 1 then
nxt_reg.mem_addr <= reg.mem_addr + 1;
nxt_reg.bus_rst <= '1';
nxt_reg.state <= WAIT_RESET;
else
nxt_reg.state <= IDLE;
nxt_reg.busy <= '0';
nxt_reg.done <= '1';
end if;
end case;
end process comb;
end architecture rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
begin
end;
|
-- Fichier : clk_exemple.vhdl
-- created by Yann Guidon / ygdes.com
-- jeu. avril 15 15:28:24 CEST 2010
-- jeu. avril 15 21:05:36 CEST 2010
-- clk_exemple.vhdl : just an example for the use of the synchronised clock generator
-- Copyright (C) 2010 Yann GUIDON
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rt_utils.all;
entity clk_exemple is
-- rien
end entity;
architecture exemple of clk_exemple is
-- ne pas oublier d'initialiser clk
-- sinon l'horloge ne peut pas osciller
-- aussi, stop doit etre maintenu à '0'
signal clk, stop: std_ulogic:='0';
begin
-- instanciation de l'horloge :
horloge : entity work.rt_clk
generic map(ms => 500)
port map(clk => clk, stop => stop);
process(clk) is
variable compteur: integer := 0;
begin
if rising_edge(clk) then
compteur := compteur + 1;
if compteur > 10 then
stop <= '1';
end if;
end if;
end process;
observe_std_ulogic("clk",clk);
end exemple;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : std_logic;
I_DATA : std_logic_vector(31 downto 0);
I_RD_EN : std_logic;
O_DATA : std_logic_vector(31 downto 0)
);
end entity FIFO;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY instruction_memory_tb IS
END instruction_memory_tb;
ARCHITECTURE behavior OF instruction_memory_tb IS
constant PROGRAM_FILENAME : string := "F:\Projects\MyStuff\TIS100\Assembler\multiply.prg";
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT instruction_memory
GENERIC(filename : string := PROGRAM_FILENAME);
PORT(
I_addr : IN std_logic_vector(5 downto 0);
O_instr : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal I_addr : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal O_instr : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: instruction_memory
GENERIC MAP (filename => PROGRAM_FILENAME)
PORT MAP (
I_addr => I_addr,
O_instr => O_instr
);
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
I_addr <= "000000";
wait for 10 ns;
assert O_instr = X"80800005" report "Invalid instruction @ addr 0" severity error;
I_addr <= "000001";
wait for 10 ns;
assert O_instr = X"01100000" report "Invalid instruction @ addr 1" severity error;
I_addr <= "000100";
wait for 10ns;
assert O_instr = X"10000000" report "Invalid instruction @ addr 4" severity error;
wait;
end process;
END;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55712)
`protect data_block
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`protect end_protected
|
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_get is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: out std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_get;
architecture behavioral of fsio_get is
begin
dat <= fso(len - 1 downto 0);
req <= hso xor hsi;
fso <= fsi;
ctl: process(clk)
begin
if rising_edge(clk) then
hso <= hso xor (req and ack);
end if;
end process ctl;
end behavioral;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use gaisler.gr1553b_pkg.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 21; -- ram address depth
srambanks : integer := 2; -- number of ram banks
rsedac : integer := CFG_MCTRLFT_EDAC/3 -- use RS encoding
);
port (
pci_rst : inout std_ulogic; -- PCI bus
pci_clk : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic;
pci_serr : inout std_ulogic;
pci_host : in std_ulogic := '1';
pci_66 : in std_ulogic := '0'
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col : std_logic := '0';
signal eth_gtxclk, erx_crs, etx_en, etx_er : std_logic :='0';
signal eth_macclk : std_logic := '0';
signal erxd, etxd : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emddis : std_logic;
signal epwrdwn : std_logic;
signal ereset : std_logic;
signal esleep : std_logic;
signal epause : std_logic;
signal emdintn : std_logic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(63 downto 0);
signal pci_arb_req, pci_arb_gnt : std_logic_vector(0 to 3);
signal can_txd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_rxd : std_logic_vector(0 to CFG_CAN_NUM-1);
signal can_stb : std_ulogic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal usb_clkout : std_ulogic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
signal usb_id : std_ulogic;
signal usb_fault : std_ulogic;
signal usb_enablen : std_ulogic;
signal usb_csn : std_ulogic;
signal usb_faultn : std_ulogic;
signal usb_clock : std_ulogic;
signal usb_vbus : std_ulogic;
signal cb : std_logic_vector(7 downto 0);
signal busainen : std_logic_vector(0 to 0);
signal busainp : std_logic_vector(0 to 0);
signal busainn : std_logic_vector(0 to 0);
signal busaoutin : std_logic_vector(0 to 0);
signal busaoutp : std_logic_vector(0 to 0);
signal busaoutn : std_logic_vector(0 to 0);
signal busbinen : std_logic_vector(0 to 0);
signal busbinp : std_logic_vector(0 to 0);
signal busbinn : std_logic_vector(0 to 0);
signal busboutin : std_logic_vector(0 to 0);
signal busboutp : std_logic_vector(0 to 0);
signal busboutn : std_logic_vector(0 to 0);
signal milbusA,milbusB: wire1553;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
dsuen <= '1'; dsubre <= '0'; rxd1 <= '1';
can_rxd <= (others => 'H'); bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "LHL";
gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
pci_arb_req <= "HHHH";
eth_macclk <= not eth_macclk after 4 ns;
emdintn <= 'H';
-- spacewire loop-back
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, sdclk, error, wdogn, address(27 downto 0), data, cb,
sa, sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact, txd1, rxd1,
txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
emdio, eth_macclk, etx_clk, erx_clk, erxd, erx_dv, erx_er,
erx_col, erx_crs, emdintn, etxd, etx_en, etx_er, emdc,
pci_rst, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66, pci_arb_req, pci_arb_gnt,
can_txd, can_rxd,
spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp,
spw_txdn, spw_txsp, spw_txsn,
usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
-- usb_id, usb_fault, usb_enablen, usb_csn, usb_faultn, usb_clock, usb_vbus,
usb_resetn,
busainen,busainp,busainn,busaoutin,busaoutp,busaoutn,
busbinen,busbinp,busbinn,busboutin,busboutp,busboutn
);
cbbits : if CFG_MCTRLFT_EDAC /= 0 generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8+rsedac*7, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
cb1: ftmt48lc16m16a2 generic map (index => 8+rsedac*7, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
nocbbits : if CFG_MCTRLFT_EDAC = 0 generate
u0: mt48lc16m16a2 generic map (index => 64, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 80, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 64, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 80, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u5: mt48lc16m16a2 generic map (index => 48, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
u7: mt48lc16m16a2 generic map (index => 48, fname => sdramfile)
PORT MAP(
Dq => sd(47 downto 32), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(1),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(5 downto 4));
end generate;
u4: mt48lc16m16a2 generic map (index => 32, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
u6: mt48lc16m16a2 generic map (index => 32, fname => sdramfile)
PORT MAP(
Dq => sd(63 downto 48), Addr => sa(12 downto 0),
Ba => sa(14 downto 13), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(7 downto 6));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(address => 1)
port map(rst, emdio, etx_clk, erx_clk, erxd, erx_dv,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, eth_macclk);
end generate;
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
error <= 'H'; -- ERROR pull-up
miltr: if (CFG_GR1553B_ENABLE = 1) generate
x: simtrans1553
port map (milbusA,milbusB,
busainen(0), busaoutin(0),
busaoutp(0), busaoutn(0), busainp(0), busainn(0),
busbinen(0), busboutin(0),
busboutp(0), busboutn(0), busbinp(0), busbinn(0));
end generate;
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
-- data <= buskeep(data), (others => 'H') after 250 ns;
data <= buskeep(data) after 5 ns;
-- sd <= buskeep(sd), (others => 'H') after 250 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2013 13:49:00
-- Design Name:
-- Module Name: main_sim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main_sim is
Port ( uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic);
end main_sim;
architecture sim_arch of main_sim is
component main
Port ( clk : in std_ulogic;
reset_switch : in std_ulogic;
uart_tx : out std_ulogic;
sd_cs_out : out std_ulogic;
sd_clk_out : out std_ulogic;
sd_mosi : out std_ulogic;
sd_miso : in std_ulogic);
end component;
signal clk : std_ulogic := '0';
signal sd_miso : std_ulogic := '0';
signal reset : std_ulogic := '1';
begin
main_being_tested: main
port map( clk => clk,
reset_switch => reset,
uart_tx => uart_tx,
sd_cs_out =>sd_cs_out,
sd_clk_out => sd_clk_out,
sd_mosi => sd_mosi,
sd_miso => sd_miso);
input_clock: process begin
clk <= '0';
sd_miso <= '1';
wait for 10ns;
clk <= '1';
sd_miso <= '0';
wait for 10ns;
end process;
end sim_arch;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 36096)
`protect data_block
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`protect end_protected
|
architecture RTL of FIFO is
function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
function func1 return integer is
begin
end function func1;
-- Violations follow
function func1 return integer;
function func1 return integer;
pure function func1 return integer;
pure function func1 return integer;
impure function func1 return integer;
impure function func1 return integer;
begin
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2650.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02650ent IS
END c13s03b01x00p02n01i02650ent;
ARCHITECTURE c13s03b01x00p02n01i02650arch OF c13s03b01x00p02n01i02650ent IS
BEGIN
TESTING: PROCESS
variable *k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02650 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2650.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02650ent IS
END c13s03b01x00p02n01i02650ent;
ARCHITECTURE c13s03b01x00p02n01i02650arch OF c13s03b01x00p02n01i02650ent IS
BEGIN
TESTING: PROCESS
variable *k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02650 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2650.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02650ent IS
END c13s03b01x00p02n01i02650ent;
ARCHITECTURE c13s03b01x00p02n01i02650arch OF c13s03b01x00p02n01i02650ent IS
BEGIN
TESTING: PROCESS
variable *k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02650 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02650arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01707ent IS
END c09s02b00x00p07n01i01707ent;
ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
procedure call_wait (variable dly : in time;
variable bool : out boolean) is
--
-- This procedure simply waits for the time specified in its argument.
--
begin
wait for dly;
bool := false;
end call_wait;
signal trigger : bit;
BEGIN
trigger <= '1' after 5 ns;
TESTING: PROCESS( trigger )
variable delay : time := 2 ns;
variable bool : boolean := true;
BEGIN
call_wait(delay, bool); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p07n01i01707arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01707ent IS
END c09s02b00x00p07n01i01707ent;
ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
procedure call_wait (variable dly : in time;
variable bool : out boolean) is
--
-- This procedure simply waits for the time specified in its argument.
--
begin
wait for dly;
bool := false;
end call_wait;
signal trigger : bit;
BEGIN
trigger <= '1' after 5 ns;
TESTING: PROCESS( trigger )
variable delay : time := 2 ns;
variable bool : boolean := true;
BEGIN
call_wait(delay, bool); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p07n01i01707arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p07n01i01707ent IS
END c09s02b00x00p07n01i01707ent;
ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
procedure call_wait (variable dly : in time;
variable bool : out boolean) is
--
-- This procedure simply waits for the time specified in its argument.
--
begin
wait for dly;
bool := false;
end call_wait;
signal trigger : bit;
BEGIN
trigger <= '1' after 5 ns;
TESTING: PROCESS( trigger )
variable delay : time := 2 ns;
variable bool : boolean := true;
BEGIN
call_wait(delay, bool); -- use wait indirectly
assert FALSE
report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list."
severity ERROR;
END PROCESS TESTING;
END c09s02b00x00p07n01i01707arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
ELSE
EN_R <= EN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_R='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
ELSE
EN_R <= EN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_R='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.package1.ALL;
entity top1 is
port(
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
top_sh : in std_logic; -- for shift register
top_in : in std_logic_vector(1 downto 0);
top_out : out std_logic_vector(decWidth - 1 downto 0)
);
end top1;
architecture struct of top1 is
signal tmpReg2Sh, tmpSh2Enc : std_logic_vector(3 downto 0);
signal tmpEnc2Dec : std_logic_vector(1 downto 0);
begin
-- I will use positional mapping here
COMP1 : ckt_reg port map(clk, rst, en, top_in, tmpReg2Sh);
COMP2 : shiftReg port map(clk, rst, en, top_sh, tmpReg2Sh, tmpSh2Enc);
COMP3 : encode1 port map(tmpSh2Enc, tmpEnc2Dec);
COMP4 : decode1 port map(clk, rst, tmpEnc2Dec, top_out);
end struct;
----------------------------------------------------------------------------------------------------------
|
-- Package for helping to implement midi synthesis on an FPGA
-- Midi enumerates musical notes. This package contains functions to help
-- implementation of this on an FPGA.
--
-- To generate notes, we will generate sine waves. this will be implemented
-- using lookup tables which store sin(x).
--
-- the following chart shows the format and scaling of what is stored in the
-- LUT.
--
-- SINE LUT LAYOUT
-- 1.0
-- |
-- s | ---
-- i | / \
-- n | / \
-- e | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
--0.0/0.0 x 1.0
--
-- Note that x and y values are both stored in an arbitrary scaling from 0.0 to
-- 1.0
--
--
--
-- ------------------------------------------------------------------------------
-- The most common audio sampling rate is 44.1 kHz. We will thus perform one
-- LUT lookup every 1/44,100 sec. This time is called the 'audio period'
-- Different frequencies are achieved by indexing through this table
-- faster or slower through time.
--
-- Notes that are low frequency will be sampled far apart in the sine wave LUT,
-- as in the following table where samples are indicated by S:
--
-- LOW FREQ NOTE SINE LOOKUP
-- |
-- | ---
-- | / \
-- | / \
-- | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
-- S S S
-- <----->
--
--
-- Notes that are high frequency are sampled close together in the sine wave LUT:
--
-- HIGH FREQ NOTE SINE LOOKUP
-- |
-- | ---
-- | / \
-- | / \
-- | / \
-- | \ /
-- | \ /
-- | ---
-- |__________________
-- S S S S S S
-- <-->
--
-- The distance between audio samples (indicated by arrows in the
-- diagrams above) is called the 'stride'
--
--
--
-- ------------------------------------------------------------------------------
-- We need to consider a few implementation details here:
-- * We want to prevent alisaing in the x axis: Because FPGAs have no
-- multiplier, indexing through the LUTs is achieved by successive addition
-- of the stride once per audio period. Thus we should calculate the number
-- of entries in the sine LUT and the size of the counter which indexes into
-- it differently... The counter may need more precision in order to
-- eliminate cumulative error
--
-- I do not know exactly how much error is permissible. There is a wikipedia
-- article on just-noticeable differences (JND) in pitch which states that
-- minimum JND for two different pitches played independently is 0.6%.
-- However the article says that it is easier to tell the difference for
-- chords but it does not give a minimum JND for it. I will thus treat 0.6%
-- as a upper bound for pitch accuracy.
--
--
-- * We want to prevent aliasing in the Y axis. this is a topic that has been
-- well researched. I will implement 16-bit accuracy.
--
-- * Also the number of LUT entries has an effect on aliasing in both the X and
-- Y axis. I have not reasoned about this yet.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.sine_lut_pkg.all;
package midi_pkg is
constant sample_rate : integer := 44_100;
constant sample_period : time := 1 sec / sample_rate;
-- This is the enumeration of midi notes as defined in some midi spec.
subtype midi_note_t is integer range 21 to 108;
-- For each midi note, holds the number of sample periods that exist in one
-- period of that note.
-- e.g for 440hz, there are 1 sec / 440 * 44100 hz = 100.2 sample periods in
-- one period of that note.
type period_arr_t is array (midi_note_t'low to midi_note_t'high) of real;
function calc_midi_note_periods return period_arr_t;
-- This table holds the rates at which the sine LUTs must be indexed through
-- to output sine waves at the correct frequency.
type stride_arr_t is array (midi_note_t'low to midi_note_t'high) of integer;
function calc_midi_note_strides return stride_arr_t;
-- I can't remember how I derived this exact value. See reasoning in the
-- header for an explanation of the concept.
constant midi_counter_width : integer := 17;
-- A type that allows us to use generate statements to build sine generators.
--
-- TODO: this is very implementation specific. Sounds like it should not
-- beling here.
type midi_note_arr_t is array(0 to num_sines - 1) of midi_note_t;
-----------------------------------------------------------------------------
-- Common midi data typres
type errors_t is record
no_mthd : std_logic;
not_format_1 : std_logic;
end record;
type chunk_data_t is record
base_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
length : unsigned(31 downto 0);
end record;
type chunk_data_t_arr is array(integer range 0 to max_num_tracks - 1) of chunk_data_t;
type midi_pulse_arr is array (1 to max_num_tracks - 1) of std_logic;
end;
package body midi_pkg is
constant midi_counter_max : integer := 2 ** midi_counter_width;
-- There is a direct formula to convert midi numbers and frequencies.
-- Sourced from https://newt.phys.unsw.edu.au/jw/notes.html
function calc_freq_from_midi_no(midi_no : in integer) return real is
begin
return
(2 ** (real(midi_no - 69) /
12.0))
* 440.0;
end;
function calc_midi_note_periods return period_arr_t is
variable freq : real;
variable ret : period_arr_t;
begin
for i in midi_note_t'low to midi_note_t'high loop
freq := calc_freq_from_midi_no(i);
-- the ideal calculation is real(1.0 sec / freq / sample_period), but
-- rounding problems.
ret(i) := 1.0 / freq / (1.0 / real(sample_rate));
end loop;
return ret;
end;
function calc_midi_note_strides return stride_arr_t is
variable freq : real;
variable samples_in_current_note : real;
variable ret : stride_arr_t;
begin
for i in midi_note_t'low to midi_note_t'high loop
freq := calc_freq_from_midi_no(i);
-- the ideal calculation is real(1.0 sec / freq / sample_rate), but that
-- has rounding problems
samples_in_current_note := 1.0 / freq / (1.0 / real(sample_rate));
ret(i) := integer(real(midi_counter_max) / samples_in_current_note);
end loop;
return ret;
end;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethc
-- File: grethc.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library ethlib;
use ethlib.types_eth.all;
entity grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end entity;
architecture rtl of grethc64 is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := capbil(4) or capbil(3) or capbil(2);
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
-- constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--tranceiver constants
constant maxsizetx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus1,
etdone, getlen, ahberror, fill_fifo2, wrbus2);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
status : eth_mac_status_type;
--master tx interface
tmsto : eth_tx_ahb_in_type;
tmsto2 : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxrenable : std_ulogic;
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrok : std_ulogic;
addrdone : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
msbgood : std_ulogic;
rxburstav : std_ulogic;
hashlookup : std_ulogic;
mcast : std_ulogic;
mcastacc : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_logic_vector(mdiohold-1 downto 0);
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
init_busy : std_ulogic;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
mdint_sync : std_logic_vector(2 downto 0);
--edcl
erenable : std_ulogic;
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
edclsepahb : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal r, rin : reg_type;
begin
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.status.reset;
irst <= rst and not r.status.reset;
comb : process(rst, irst, ctrli, cmdi, r, rmsti, tmsti, txo, rxo,
erdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, edcladdr, mdint, tmsti2, edcldisable,
edclsepahb) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vrdbgdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic; --rising mdio clk edge
variable nmclk : std_ulogic; --falling mdio clk edge
variable mclkvec : std_logic_vector(mdiohold downto 0);
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vrdbgdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;
if edcl /= 0 then
veri.renable := r.erenable;
veri.datain := rxo.dataout;
veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
end if;
vtxfi.renable := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt;
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := r.rxrenable; vrxenable := r.status.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
if enable_mdint = 1 then
v.mdint_sync(0) := mdint;
v.mdint_sync(1) := r.mdint_sync(0);
v.mdint_sync(2) := r.mdint_sync(1);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
if cmdi.set_speed = '1' then v.status.speed := '1';
elsif cmdi.clr_speed = '1' then v.status.speed := '0';
end if;
if cmdi.set_reset = '1' then v.status.reset := '1';
elsif cmdi.clr_reset = '1' then v.status.reset := '0';
end if;
if cmdi.set_full_duplex = '1' then v.status.full_duplex := '1';
elsif cmdi.clr_full_duplex = '1' then v.status.full_duplex := '0';
end if;
if cmdi.set_rxena = '1' then v.status.rxen := '1';
elsif cmdi.clr_rxena = '1' then v.status.rxen := '0';
end if;
if cmdi.set_txena = '1' then v.status.txen := '1';
elsif cmdi.clr_txena = '1' then v.status.txen := '0';
end if;
if cmdi.clr_status_phystat = '1' then v.status.phystat := '0'; end if;
if cmdi.clr_status_invaddr = '1' then v.status.invaddr := '0'; end if;
if cmdi.clr_status_toosmall = '1' then v.status.toosmall := '0'; end if;
if cmdi.clr_status_txahberr = '1' then v.status.txahberr := '0'; end if;
if cmdi.clr_status_rxahberr = '1' then v.status.rxahberr := '0'; end if;
if cmdi.clr_status_tx_int = '1' then v.status.tx_int := '0'; end if;
if cmdi.clr_status_rx_int = '1' then v.status.rx_int := '0'; end if;
if cmdi.clr_status_tx_err = '1' then v.status.tx_err := '0'; end if;
if cmdi.clr_status_rx_err = '1' then v.status.rx_err := '0'; end if;
if cmdi.mdio_cmd.valid = '1' then
v.status.mdio.cmd.data := cmdi.mdio_cmd.data;
v.status.mdio.cmd.regadr := cmdi.mdio_cmd.regadr;
v.status.mdio.cmd.read := cmdi.mdio_cmd.read;
v.status.mdio.cmd.write := cmdi.mdio_cmd.write;
v.status.mdio.busy := cmdi.mdio_cmd.read or cmdi.mdio_cmd.write;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_TX_BUFFER then
vtxfi.write := cmdi.dbg_wr_ena;
vtxfi.waddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.datain := cmdi.dbg_wdata;
vtxfi.raddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := txrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_RX_BUFFER then
vrxfi.write := cmdi.dbg_wr_ena;
vrxfi.waddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.datain := cmdi.dbg_wdata;
vrxfi.raddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := rxrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_EDCL_BUFFER then
veri.writem := cmdi.dbg_wr_ena;
veri.writel := cmdi.dbg_wr_ena;
veri.waddressm := cmdi.dbg_addr(eabits+1 downto 2);
veri.waddressl := cmdi.dbg_addr(eabits+1 downto 2);
veri.datain := cmdi.dbg_wdata;
veri.raddress := cmdi.dbg_addr(eabits+1 downto 2);
veri.renable := cmdi.dbg_rd_ena;
vrdbgdata := erdata;
end if;
--PHY STATUS DETECTION
if enable_mdint = 1 then
if mdint_pol = 0 then
if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
else
if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
end if;
end if;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
if (conv_integer(r.abufs) /= 0) then
v.status.edcltx_idle := '0';
else
v.status.edcltx_idle := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0'; v.erenable := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and
(ctrli.edcldis = '0') then
v.erenable := '1'; v.status.edcltx_idle := '0';
if r.erenable = '1' then
v.txdstate := getlen;
end if;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.status.txen = '1' then
v.txdstate := read_desc;
v.tmsto.write := '0';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.req := '1';
--! AXI_ENABLE: burst transaction size in bytes
v.tmsto.burst_bytes := conv_std_logic_vector(8, 11);
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4;
if r.txburstcnt(0) = '1' then
v.tmsto.req := '0';
end if;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1;
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.status.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (unsigned(r.txlength) > unsigned(maxsizetx)) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result;
v.tmsto.req := '1';
v.tmsto.write := '1';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data := (others => '0');
--! AXI_ENABLE: length of transaction not defined so use simple DMA access
v.tmsto.burst_bytes := conv_std_logic_vector(4,11);
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00";
v.txcnt(10 downto 0) := r.txlength;
--! AXI_ENABLE: length of transaction defined
v.tmsto.burst_bytes := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
if (edclsepahbg = 0) or (edcl = 0) or
(r.edclsepahb = '0') or (r.tedcl = '0') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
else
v.tmsto2.req := '1'; v.txdstate := fill_fifo2;
end if;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when fill_fifo2 =>
if edclsepahbg = 1 then
v.txburstav := '0';
vtxfi.datain := tmsti2.data;
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then
v.tmsto2.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto2.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := ctrli.tx_irqen and r.txirq;
if r.txwrap = '0' then v.status.txdsel := r.status.txdsel + 1;
else v.status.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.status.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
if ramdebug = 0 then
vtxfi.renable := v.txdataav;
else
vtxfi.renable := vtxfi.renable or v.txdataav;
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
if r.status.rxen = '1' then
v.rxdstate := read_desc;
v.rmsto.req := '1';
v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
--! AXI_ENABLE: burst transaction descriptor header size in bytes
v.rmsto.burst_bytes := conv_std_logic_vector(8, 11);
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4;
if r.rxburstcnt(0) = '1' then
v.rmsto.req := '0';
--! AXI_ENABLE: don't use burst operation:
v.rmsto.burst_bytes := conv_std_logic_vector(4,11);
end if;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1;
case r.rxcnt(1 downto 0) is
when "00" =>
v.status.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
v.rxrenable := '1';
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
v.rxdstate := write_status2;
if multicast = 1 then
v.rmsto.data := "00000" & r.mcastacc & "0000000" &
r.rxstatus & "000" & r.rxlength;
else
v.rmsto.data := "0000000000000" &
r.rxstatus & "000" & r.rxlength;
end if;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (ctrli.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.status.rxdsel := (others => '0');
else
v.status.rxdsel := r.status.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
if r.rxstatus(3) = '1' then
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.rxdstate := idle;
elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if ctrli.prom = '1' then
v.addrok := '1';
end if;
v.mcast := r.checkdata(24);
if r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
if r.checkdata = ctrli.mac_addr(47 downto 16) then
v.msbgood := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) = broadcast(15 downto 0) then
if r.bcast = '1' then
v.addrok := '1';
end if;
else
v.bcast := '0';
end if;
if r.checkdata(31 downto 16) = ctrli.mac_addr(15 downto 0) then
if r.msbgood = '1' then
v.addrok := '1';
end if;
end if;
if multicast = 1 then
v.hashlookup := ctrli.hash(conv_integer(rxo.mcasthash));
end if;
when "011" =>
if multicast = 1 then
if (r.hashlookup and ctrli.mcasten and r.mcast) = '1' then
v.addrok := '1';
if r.bcast = '0' then
v.mcastacc := '1';
end if;
end if;
end if;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
v.addrdone := '1';
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
v.rxdoneack := not r.rxdoneack;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
if (ramdebug = 0) or (ctrli.ramdebugen = '0') then
vrxfi.raddress := v.rfrpnt;
end if;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclkvec := r.mdioclkold & r.mdioclk;
mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold);
nmclk := mclkvec(1) and not mclkvec(0);
v.mdioclkold := mclkvec(mdiohold-1 downto 0);
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
case r.mdio_state is
when idle =>
if (enable_mdio = 1) and (edcl = 0) and (r.status.reset = '1') then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if mclk = '1' then
v.cnt := (others => '0');
if r.status.mdio.busy = '1' then
v.status.mdio.linkfail := '0';
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
end if;
when preamble =>
if mclk = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
end if;
when startst =>
if mclk = '1' then
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
end if;
when op =>
if mclk = '1' then
v.mdio_state := op2;
if r.status.mdio.cmd.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
end if;
when op2 =>
if mclk = '1' then
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
end if;
when phyadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := ctrli.mdio_phyadr(4);
when 1 => v.mdioo := ctrli.mdio_phyadr(3);
when 2 => v.mdioo := ctrli.mdio_phyadr(2);
when 3 => v.mdioo := ctrli.mdio_phyadr(1);
when 4 => v.mdioo := ctrli.mdio_phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
end if;
when regadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.status.mdio.cmd.regadr(4);
when 1 => v.mdioo := r.status.mdio.cmd.regadr(3);
when 2 => v.mdioo := r.status.mdio.cmd.regadr(2);
when 3 => v.mdioo := r.status.mdio.cmd.regadr(1);
when 4 => v.mdioo := r.status.mdio.cmd.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
end if;
when ta =>
if mclk = '1' then
v.mdio_state := ta2;
if r.status.mdio.cmd.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
end if;
when ta2 =>
if mclk = '1' then
v.cnt := "01111"; v.mdio_state := ta3;
if r.status.mdio.cmd.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
end if;
when ta3 =>
if mclk = '1' then
v.mdio_state := data;
end if;
if nmclk = '1' then
if r.mdioi /= '0' then
v.status.mdio.linkfail := '1';
end if;
end if;
when data =>
if mclk = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
if r.status.mdio.cmd.read = '0' then
v.mdioo := r.status.mdio.cmd.data(mdioindex);
end if;
end if;
if nmclk = '1' then
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.data(mdioindex) := r.mdioi;
end if;
end if;
when dataend =>
if mclk = '1' then
if (rmii = 1) or (edcl /= 0) then
v.init_busy := '0';
if (r.duplexstate = done or ctrli.edcldis = '1' or ctrli.disableduplex = '1') then
v.status.mdio.busy := '0';
end if;
else
v.status.mdio.busy := '0';
end if;
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
when others =>
null;
end case;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
vrxenable := '1';
end if;
swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0';
if vrxwrite = '1' then
if ctrli.edcldis = '0' then
v.rxwriteack := not r.rxwriteack;
end if;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0'; v.status.edclrx_idle := '1';
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
if (rxstart and not ctrli.edcldis) = '1' then
v.edclrstate := wrda; v.edclactive := '0'; v.status.edclrx_idle := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (ctrli.emacaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (ctrli.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
if r.nak = '0' then
v.seq := r.seq + 1;
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := ctrli.emacaddr(31 downto 16) & ctrli.emacaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := ctrli.emacaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= ctrli.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= ctrli.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := ctrli.emacaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := ctrli.emacaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto.burst_bytes := r.txcnt;
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.addr := r.txaddr & "00";
v.tmsto2.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto2.burst_bytes := r.txcnt;
end if;
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
v.tmsto.req := '0';
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.req := '0';
end if;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.tedcl := '1';
v.tcnt := r.tcnt + 1;
if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then
v.tmsto.req := '1'; v.tmsto.data := erdata;
v.txdstate := wrbus1;
else
v.tmsto2.req := '1'; v.tmsto2.data := erdata;
v.txdstate := wrbus2;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus1 =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
when wrbus2 =>
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready or tmsti2.error) = '1' then
v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto2.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti2.retry = '1' then
v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1';
end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
if (ramdebug /= 2) or (edcl = 0) or (cmdi.dbg_rd_ena = '0') then
veri.raddress := r.tpnt & v.tcnt;
end if;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
if (ctrli.edcldis = '0' and ctrli.disableduplex = '0') then
v.status.mdio.cmd.regadr := r.regaddr; v.init_busy := '1';
v.status.mdio.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.status.mdio.cmd.write := '1';
else
v.status.mdio.cmd.read := '1';
end if;
if r.rstphy = '1' then
v.status.mdio.cmd.data := X"9000";
end if;
end if;
when waitop =>
if r.init_busy = '0' then
if r.status.mdio.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.status.mdio.cmd.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.status.mdio.cmd.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00001" =>
v.ext := r.status.mdio.cmd.data(8); --extended status register
v.extcap := r.status.mdio.cmd.data(1); --extended register capabilities
v.duplexstate := start;
if r.status.mdio.cmd.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.status.mdio.cmd.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.status.mdio.cmd.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.status.mdio.cmd.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.status.mdio.cmd.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done; v.status.mdio.busy := '0';
if r.phywr = '1' then
v.status.full_duplex := '0'; v.status.speed := '0';
else
sel_op_mode(r.capbil, v.status.speed, v.status.full_duplex);
end if;
when done =>
null;
end case;
-- MDIO Disable
if ctrli.edcldis = '1' or ctrli.disableduplex = '1' then
if v.duplexstate /= start then
v.duplexstate := start;
v.status.mdio.cmd.regadr := (others => '0');
v.status.mdio.busy := '0';
v.init_busy := '0';
v.status.mdio.cmd.write := '0';
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.data := X"0000";
end if;
end if;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
if (edclsepahbg /= 0) and (edcl /= 0) then
--transmitter retry
if tmsti2.retry = '1' then
v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto2.req := '0'; v.txdstate := ahberror;
end if;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.rfwpnt := (others => '0');
v.rfcnt := (others => '0');
v.status.txen := '0';
v.status.tx_int := '0';
v.status.rx_int := '0';
v.status.tx_err := '0';
v.status.rx_err := '0';
v.status.txahberr := '0';
v.status.rxahberr := '0';
v.txirqgen := '0'; v.status.rxen := '0';
v.status.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.status.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.status.invaddr := '0'; v.status.toosmall := '0';
v.status.full_duplex := '0'; v.writeok := '1';
if (enable_mdio = 0) or (edcl /= 0) then
v.status.reset := '0';
end if;
if enable_mdint = 1 then
v.status.phystat := '0';
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
end if;
if (rmii = 1) then
v.status.speed := '1';
else
v.status.speed := '1';
end if;
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
v.seq := (others => '0');
v.mdioo := '0';
if (enable_mdio = 1) then
v.mdccnt := divisor; v.mdioclk := '0';
end if;
v.status.reset := '0';
if (enable_mdio = 1) then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.valid := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0'; v.status.mdio.linkfail := '1';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
v.cnt := (others => '0');
end if;
if edclsepahbg /= 0 then
v.edclsepahb := edclsepahb;
end if;
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
v.tedcl := '0'; v.erenable := '0';
v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
v.gotframe := '0';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.txburstav := '0'; v.txdataav := '0';
v.txstatus := (others => '0'); v.txstart := '0';
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0'); v.txaddr := (others => '0');
v.txdata := (others => '0');
v.txvalid := '0';
v.txlength := (others => '0');
v.cnt := (others => '0');
v.rxaddr := (others => '0');
v.rxstatus := (others => '0');
v.rxwrap := '0'; v.rxden := '0';
v.rmsto.req := '0';
v.rmsto.write := '0';
v.rmsto.addr := (others => '0');
v.rmsto.data := (others => '0');
v.tmsto.req := '0';
v.tmsto.write := '0';
v.tmsto.addr := (others => '0');
v.tmsto.data := (others => '0');
v.tmsto2.req := '0';
v.tmsto2.write := '0';
v.tmsto2.addr := (others => '0');
v.tmsto2.data := (others => '0');
v.nak := '0'; v.ewr := '0';
v.write := (others => '0');
v.applength := (others => '0');
v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0');
v.txwrap := '0';
v.txden := '0';
v.txirq := '0';
v.rxirq := '0';
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
rdbgdatao <= vrdbgdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
statuso <= r.status;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.status.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
rxi.rx_en <= rx_en;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.status.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.status.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
txi.datavalid <= tx_dv;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
tmsto2 <= r.tmsto2;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
speed <= r.status.speed;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
--! Tx FIFO
tx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => txfabits,
dbits => 32,
sepclk => 0
) port map (
clk,
txrenable,
txraddress(txfabits-1 downto 0),
txrdata,
clk,
txwrite,
txwaddress(txfabits-1 downto 0),
txwdata
);
--! Rx FIFO
rx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => fabits,
dbits => 32,
sepclk => 0
) port map (
clk,
rxrenable,
rxraddress(fabits-1 downto 0),
rxrdata,
clk,
rxwrite,
rxwaddress(fabits-1 downto 0),
rxwdata
);
--! EDCL buffer ram
edclramnft : if (edcl /= 0) generate
r0 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map (
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(31 downto 16),
clk,
ewritem,
ewaddressm(eabits-1 downto 0),
ewdata(31 downto 16)
);
r1 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map(
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(15 downto 0),
clk,
ewritel,
ewaddressl(eabits-1 downto 0),
ewdata(15 downto 0)
);
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_136 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_136;
architecture augh of cmp_136 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_136 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_136;
architecture augh of cmp_136 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
------------------ Dataflow_HA ------------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder_dataflow --
entity half_adder_dataflow is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end half_adder_dataflow;
-- Architecture dataflow --
architecture dataflow of half_adder_dataflow is
begin
sum <= a xor b;
carry <= a and b;
end dataflow; |
------------------ Dataflow_HA ------------------------
-------------- Library statements -------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration half_adder_dataflow --
entity half_adder_dataflow is
port (a, b : in std_logic;
sum, carry : out std_logic
);
end half_adder_dataflow;
-- Architecture dataflow --
architecture dataflow of half_adder_dataflow is
begin
sum <= a xor b;
carry <= a and b;
end dataflow; |
library verilog;
use verilog.vl_types.all;
entity altera_reset_controller is
generic(
NUM_RESET_INPUTS: integer := 6;
USE_RESET_REQUEST_IN0: integer := 0;
USE_RESET_REQUEST_IN1: integer := 0;
USE_RESET_REQUEST_IN2: integer := 0;
USE_RESET_REQUEST_IN3: integer := 0;
USE_RESET_REQUEST_IN4: integer := 0;
USE_RESET_REQUEST_IN5: integer := 0;
USE_RESET_REQUEST_IN6: integer := 0;
USE_RESET_REQUEST_IN7: integer := 0;
USE_RESET_REQUEST_IN8: integer := 0;
USE_RESET_REQUEST_IN9: integer := 0;
USE_RESET_REQUEST_IN10: integer := 0;
USE_RESET_REQUEST_IN11: integer := 0;
USE_RESET_REQUEST_IN12: integer := 0;
USE_RESET_REQUEST_IN13: integer := 0;
USE_RESET_REQUEST_IN14: integer := 0;
USE_RESET_REQUEST_IN15: integer := 0;
OUTPUT_RESET_SYNC_EDGES: string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT: integer := 0;
RESET_REQ_WAIT_TIME: integer := 3;
MIN_RST_ASSERTION_TIME: integer := 11;
RESET_REQ_EARLY_DSRT_TIME: integer := 4;
ADAPT_RESET_REQUEST: integer := 0
);
port(
reset_in0 : in vl_logic;
reset_in1 : in vl_logic;
reset_in2 : in vl_logic;
reset_in3 : in vl_logic;
reset_in4 : in vl_logic;
reset_in5 : in vl_logic;
reset_in6 : in vl_logic;
reset_in7 : in vl_logic;
reset_in8 : in vl_logic;
reset_in9 : in vl_logic;
reset_in10 : in vl_logic;
reset_in11 : in vl_logic;
reset_in12 : in vl_logic;
reset_in13 : in vl_logic;
reset_in14 : in vl_logic;
reset_in15 : in vl_logic;
reset_req_in0 : in vl_logic;
reset_req_in1 : in vl_logic;
reset_req_in2 : in vl_logic;
reset_req_in3 : in vl_logic;
reset_req_in4 : in vl_logic;
reset_req_in5 : in vl_logic;
reset_req_in6 : in vl_logic;
reset_req_in7 : in vl_logic;
reset_req_in8 : in vl_logic;
reset_req_in9 : in vl_logic;
reset_req_in10 : in vl_logic;
reset_req_in11 : in vl_logic;
reset_req_in12 : in vl_logic;
reset_req_in13 : in vl_logic;
reset_req_in14 : in vl_logic;
reset_req_in15 : in vl_logic;
clk : in vl_logic;
reset_out : out vl_logic;
reset_req : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of NUM_RESET_INPUTS : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN0 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN1 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN2 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN3 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN4 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN5 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN6 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN7 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN8 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN9 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN10 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN11 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN12 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN13 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN14 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN15 : constant is 1;
attribute mti_svvh_generic_type of OUTPUT_RESET_SYNC_EDGES : constant is 1;
attribute mti_svvh_generic_type of SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESET_REQUEST_PRESENT : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_WAIT_TIME : constant is 1;
attribute mti_svvh_generic_type of MIN_RST_ASSERTION_TIME : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_EARLY_DSRT_TIME : constant is 1;
attribute mti_svvh_generic_type of ADAPT_RESET_REQUEST : constant is 1;
end altera_reset_controller;
|
library verilog;
use verilog.vl_types.all;
entity altera_reset_controller is
generic(
NUM_RESET_INPUTS: integer := 6;
USE_RESET_REQUEST_IN0: integer := 0;
USE_RESET_REQUEST_IN1: integer := 0;
USE_RESET_REQUEST_IN2: integer := 0;
USE_RESET_REQUEST_IN3: integer := 0;
USE_RESET_REQUEST_IN4: integer := 0;
USE_RESET_REQUEST_IN5: integer := 0;
USE_RESET_REQUEST_IN6: integer := 0;
USE_RESET_REQUEST_IN7: integer := 0;
USE_RESET_REQUEST_IN8: integer := 0;
USE_RESET_REQUEST_IN9: integer := 0;
USE_RESET_REQUEST_IN10: integer := 0;
USE_RESET_REQUEST_IN11: integer := 0;
USE_RESET_REQUEST_IN12: integer := 0;
USE_RESET_REQUEST_IN13: integer := 0;
USE_RESET_REQUEST_IN14: integer := 0;
USE_RESET_REQUEST_IN15: integer := 0;
OUTPUT_RESET_SYNC_EDGES: string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT: integer := 0;
RESET_REQ_WAIT_TIME: integer := 3;
MIN_RST_ASSERTION_TIME: integer := 11;
RESET_REQ_EARLY_DSRT_TIME: integer := 4;
ADAPT_RESET_REQUEST: integer := 0
);
port(
reset_in0 : in vl_logic;
reset_in1 : in vl_logic;
reset_in2 : in vl_logic;
reset_in3 : in vl_logic;
reset_in4 : in vl_logic;
reset_in5 : in vl_logic;
reset_in6 : in vl_logic;
reset_in7 : in vl_logic;
reset_in8 : in vl_logic;
reset_in9 : in vl_logic;
reset_in10 : in vl_logic;
reset_in11 : in vl_logic;
reset_in12 : in vl_logic;
reset_in13 : in vl_logic;
reset_in14 : in vl_logic;
reset_in15 : in vl_logic;
reset_req_in0 : in vl_logic;
reset_req_in1 : in vl_logic;
reset_req_in2 : in vl_logic;
reset_req_in3 : in vl_logic;
reset_req_in4 : in vl_logic;
reset_req_in5 : in vl_logic;
reset_req_in6 : in vl_logic;
reset_req_in7 : in vl_logic;
reset_req_in8 : in vl_logic;
reset_req_in9 : in vl_logic;
reset_req_in10 : in vl_logic;
reset_req_in11 : in vl_logic;
reset_req_in12 : in vl_logic;
reset_req_in13 : in vl_logic;
reset_req_in14 : in vl_logic;
reset_req_in15 : in vl_logic;
clk : in vl_logic;
reset_out : out vl_logic;
reset_req : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of NUM_RESET_INPUTS : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN0 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN1 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN2 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN3 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN4 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN5 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN6 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN7 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN8 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN9 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN10 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN11 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN12 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN13 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN14 : constant is 1;
attribute mti_svvh_generic_type of USE_RESET_REQUEST_IN15 : constant is 1;
attribute mti_svvh_generic_type of OUTPUT_RESET_SYNC_EDGES : constant is 1;
attribute mti_svvh_generic_type of SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESET_REQUEST_PRESENT : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_WAIT_TIME : constant is 1;
attribute mti_svvh_generic_type of MIN_RST_ASSERTION_TIME : constant is 1;
attribute mti_svvh_generic_type of RESET_REQ_EARLY_DSRT_TIME : constant is 1;
attribute mti_svvh_generic_type of ADAPT_RESET_REQUEST : constant is 1;
end altera_reset_controller;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-----------------------------------------------------------------------------
-- Entity: ssrctrl_unisim
-- file: ssrctrl_unisim.vhd
-- Description: 32-bit SSRAM memory controller with PROM 16-bit bus support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity ssrctrl_unisim is
port(
rst : in std_logic;
clk : in std_logic;
n_ahbsi_hsel : in std_logic_vector (0 to 15);
n_ahbsi_haddr : in std_logic_vector (31 downto 0);
n_ahbsi_hwrite : in std_logic;
n_ahbsi_htrans : in std_logic_vector (1 downto 0);
n_ahbsi_hsize : in std_logic_vector (2 downto 0);
n_ahbsi_hburst : in std_logic_vector (2 downto 0);
n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
n_ahbsi_hprot : in std_logic_vector (3 downto 0);
n_ahbsi_hready : in std_logic;
n_ahbsi_hmaster : in std_logic_vector (3 downto 0);
n_ahbsi_hmastlock : in std_logic;
n_ahbsi_hmbsel : in std_logic_vector (0 to 3);
n_ahbsi_hcache : in std_logic;
n_ahbsi_hirq : in std_logic_vector (31 downto 0);
n_ahbso_hready : out std_logic;
n_ahbso_hresp : out std_logic_vector (1 downto 0);
n_ahbso_hrdata : out std_logic_vector (31 downto 0);
n_ahbso_hsplit : out std_logic_vector (15 downto 0);
n_ahbso_hcache : out std_logic;
n_ahbso_hirq : out std_logic_vector (31 downto 0);
n_apbi_psel : in std_logic_vector (0 to 15);
n_apbi_penable : in std_logic;
n_apbi_paddr : in std_logic_vector (31 downto 0);
n_apbi_pwrite : in std_logic;
n_apbi_pwdata : in std_logic_vector (31 downto 0);
n_apbi_pirq : in std_logic_vector (31 downto 0);
n_apbo_prdata : out std_logic_vector (31 downto 0);
n_apbo_pirq : out std_logic_vector (31 downto 0);
n_sri_data : in std_logic_vector (31 downto 0);
n_sri_brdyn : in std_logic;
n_sri_bexcn : in std_logic;
n_sri_writen : in std_logic;
n_sri_wrn : in std_logic_vector (3 downto 0);
n_sri_bwidth : in std_logic_vector (1 downto 0);
n_sri_sd : in std_logic_vector (63 downto 0);
n_sri_cb : in std_logic_vector (7 downto 0);
n_sri_scb : in std_logic_vector (7 downto 0);
n_sri_edac : in std_logic;
n_sro_address : out std_logic_vector (31 downto 0);
n_sro_data : out std_logic_vector (31 downto 0);
n_sro_sddata : out std_logic_vector (63 downto 0);
n_sro_ramsn : out std_logic_vector (7 downto 0);
n_sro_ramoen : out std_logic_vector (7 downto 0);
n_sro_ramn : out std_logic;
n_sro_romn : out std_logic;
n_sro_mben : out std_logic_vector (3 downto 0);
n_sro_iosn : out std_logic;
n_sro_romsn : out std_logic_vector (7 downto 0);
n_sro_oen : out std_logic;
n_sro_writen : out std_logic;
n_sro_wrn : out std_logic_vector (3 downto 0);
n_sro_bdrive : out std_logic_vector (3 downto 0);
n_sro_vbdrive : out std_logic_vector (31 downto 0);
n_sro_svbdrive : out std_logic_vector (63 downto 0);
n_sro_read : out std_logic;
n_sro_sa : out std_logic_vector (14 downto 0);
n_sro_cb : out std_logic_vector (7 downto 0);
n_sro_scb : out std_logic_vector (7 downto 0);
n_sro_vcdrive : out std_logic_vector (7 downto 0);
n_sro_svcdrive : out std_logic_vector (7 downto 0);
n_sro_ce : out std_logic);
end ssrctrl_unisim;
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity ssrctrl_unisim_netlist is
port(
n_sro_vbdrive : out std_logic_vector (31 downto 0);
n_ahbso_hrdata : out std_logic_vector (31 downto 0);
iows_0 : out std_logic;
iows_3 : out std_logic;
romwws_0 : out std_logic;
romwws_3 : out std_logic;
romrws_0 : out std_logic;
romrws_3 : out std_logic;
NoName_cnst : in std_logic_vector (0 downto 0);
n_sri_bwidth : in std_logic_vector (1 downto 0);
n_apbi_pwdata_19 : in std_logic;
n_apbi_pwdata_11 : in std_logic;
n_apbi_pwdata_9 : in std_logic;
n_apbi_pwdata_8 : in std_logic;
n_apbi_pwdata_23 : in std_logic;
n_apbi_pwdata_22 : in std_logic;
n_apbi_pwdata_21 : in std_logic;
n_apbi_pwdata_20 : in std_logic;
n_apbi_pwdata_3 : in std_logic;
n_apbi_pwdata_2 : in std_logic;
n_apbi_pwdata_1 : in std_logic;
n_apbi_pwdata_0 : in std_logic;
n_apbi_pwdata_7 : in std_logic;
n_apbi_pwdata_6 : in std_logic;
n_apbi_pwdata_5 : in std_logic;
n_apbi_pwdata_4 : in std_logic;
n_apbi_psel : in std_logic_vector (0 downto 0);
n_apbi_paddr : in std_logic_vector (5 downto 2);
n_apbo_prdata_0 : out std_logic;
n_apbo_prdata_4 : out std_logic;
n_apbo_prdata_20 : out std_logic;
n_apbo_prdata_23 : out std_logic;
n_apbo_prdata_22 : out std_logic;
n_apbo_prdata_21 : out std_logic;
n_apbo_prdata_19 : out std_logic;
n_apbo_prdata_7 : out std_logic;
n_apbo_prdata_6 : out std_logic;
n_apbo_prdata_5 : out std_logic;
n_apbo_prdata_3 : out std_logic;
n_apbo_prdata_2 : out std_logic;
n_apbo_prdata_1 : out std_logic;
n_apbo_prdata_11 : out std_logic;
n_apbo_prdata_9 : out std_logic;
n_apbo_prdata_8 : out std_logic;
n_apbo_prdata_28 : out std_logic;
n_sro_romsn : out std_logic_vector (0 downto 0);
n_ahbsi_hsel : in std_logic_vector (0 downto 0);
prstate_fast : out std_logic_vector (2 downto 2);
n_ahbsi_htrans : in std_logic_vector (1 downto 0);
ssrstate_1_m1 : inout std_logic_vector (4 downto 3) := (others => 'Z');
hsel_1 : in std_logic_vector (0 downto 0);
hmbsel_4 : out std_logic_vector (1 downto 1);
n_sro_bdrive : out std_logic_vector (3 downto 3);
ws_1_0 : in std_logic;
ws_1_3 : in std_logic;
ws : out std_logic_vector (3 downto 0);
ssrstate_1_2 : in std_logic;
n_ahbsi_haddr : in std_logic_vector (31 downto 0);
n_ahbsi_hmbsel : in std_logic_vector (2 downto 0);
n_sri_data : in std_logic_vector (31 downto 0);
ssrstate : out std_logic_vector (4 downto 0);
n_ahbsi_hwdata : in std_logic_vector (31 downto 0);
n_ahbsi_hsize : in std_logic_vector (1 downto 0);
size : out std_logic_vector (1 downto 0);
n_sro_data : out std_logic_vector (31 downto 0);
n_sro_ramsn : out std_logic_vector (0 downto 0);
n_sro_wrn : out std_logic_vector (3 downto 0);
haddr_0 : in std_logic;
bwn_1_0_o3_0 : in std_logic;
hsize_1 : in std_logic_vector (1 downto 1);
prstate_1_i_o4_s : in std_logic_vector (2 downto 2);
prstate : out std_logic_vector (5 downto 0);
hmbsel : out std_logic_vector (2 downto 0);
n_sro_address : out std_logic_vector (31 downto 0);
hready_2 : in std_logic;
n_ahbso_hready : out std_logic;
ssrhready_8 : in std_logic;
loadcount : out std_logic;
n_sro_writen : out std_logic;
ssrstatec : in std_logic;
prhready : out std_logic;
d_m2_0_a2_0 : in std_logic;
ssrstate17_2_0_m6_i_a3_a2 : out std_logic;
N_319_1 : out std_logic;
ws_0_sqmuxa_c : out std_logic;
N_365 : in std_logic;
ws_0_sqmuxa_0_c : out std_logic;
ws_2_sqmuxa_3_0_4 : out std_logic;
change_1_sqmuxa_0 : in std_logic;
d16mux_0_sqmuxa : in std_logic;
ssrstate_2_sqmuxa_1 : in std_logic;
un7_bus16en : in std_logic;
N_646 : in std_logic;
loadcount_1_sqmuxa : in std_logic;
ssrstate_1_sqmuxa_1_0_m3_0_1 : out std_logic;
n_apbi_penable : in std_logic;
n_apbi_pwrite : in std_logic;
d_m1_e_0_0 : in std_logic;
hsel_1_0_L3 : out std_logic;
ssrhready_8_f0_L8 : out std_logic;
ssrstate_1_sqmuxa_1 : in std_logic;
ssrhready : out std_logic;
ssrhready_8_f0_L5 : out std_logic;
ssrstate17_1_xx_mm_N_4 : in std_logic;
ws_1_sqmuxa : out std_logic;
ws_4_sqmuxa_0 : in std_logic;
ws_2_sqmuxa_0 : in std_logic;
ssrstate17_2_0_m6_i_1 : out std_logic;
ws_2_sqmuxa_3_0_x : out std_logic;
ws_3_sqmuxa_1 : out std_logic;
ws_2_sqmuxa_3_0_2 : out std_logic;
ssrstate_2_i : out std_logic;
ws_2_sqmuxa_3_d : out std_logic;
ws_0_sqmuxa_1 : out std_logic;
g0_30 : in std_logic;
hsel_4 : in std_logic;
n_ahbsi_hready : in std_logic;
hsel : out std_logic;
g0_25 : in std_logic;
bwn_0_sqmuxa_1 : in std_logic;
prstate_2_rep1 : out std_logic;
N_662 : out std_logic;
ssrstate_6_sqmuxa : out std_logic;
g0_52_x1 : in std_logic;
g0_52_x0 : in std_logic;
ssrhready_2_sqmuxa_0_0 : out std_logic;
change_1_sqmuxa_N_3 : out std_logic;
ssrstate6_xx_mm_m3 : out std_logic;
ssrstate6_1_d_0_L1 : out std_logic;
N_656 : out std_logic;
hsel_5 : out std_logic;
change_3_f0 : in std_logic;
un1_ahbsi : out std_logic;
change : out std_logic;
n_ahbsi_hwrite : in std_logic;
N_574_i : in std_logic;
n_sro_iosn : out std_logic;
N_618_i : in std_logic;
clk : in std_logic;
n_sro_oen : out std_logic;
rst : in std_logic;
bwn_1_sqmuxa_2_d : in std_logic;
bwn_1_sqmuxa_2_d_0_2 : in std_logic;
ssrstate_2_sqmuxa_i : in std_logic;
g0_23 : in std_logic;
N_371 : out std_logic;
loadcount_7 : in std_logic;
bus16en : out std_logic;
d16muxc_0_4 : out std_logic;
change_3_f1_d_0_0 : in std_logic;
g0_1_0 : in std_logic;
g0_44 : in std_logic);
end ssrctrl_unisim_netlist;
architecture beh of ssrctrl_unisim_netlist is
signal ACOUNT_QXU : std_logic_vector (9 downto 1);
signal ACOUNT_LM_0_1 : std_logic_vector (0 to 0);
signal ACOUNT_LM : std_logic_vector (9 downto 0);
signal WS_1_0_BM : std_logic_vector (1 to 1);
signal WS_1_0_RN_1 : std_logic_vector (1 to 1);
signal WS_1 : std_logic_vector (2 downto 1);
signal SSRSTATE_1_0_D_BM : std_logic_vector (3 to 3);
signal SSRSTATE_1_0_1 : std_logic_vector (3 to 3);
signal SSRSTATE_1 : std_logic_vector (3 downto 2);
signal BWN_1_0_O3 : std_logic_vector (1 to 1);
signal PRSTATE_I : std_logic_vector (1 to 1);
signal HWDATAOUT_1 : std_logic_vector (31 downto 0);
signal ROMWIDTH : std_logic_vector (1 downto 0);
signal ROMWIDTH_1 : std_logic_vector (1 downto 0);
signal DATA16 : std_logic_vector (15 downto 0);
signal HRDATA : std_logic_vector (31 downto 0);
signal HWDATA : std_logic_vector (31 downto 0);
signal HADDR : std_logic_vector (11 downto 2);
signal SSRSTATE_1_0_D_AM : std_logic_vector (3 to 3);
signal HMBSEL_4_X1 : std_logic_vector (1 to 1);
signal WS_1_2_0_D : std_logic_vector (2 downto 1);
signal WS_1_0_AM_1 : std_logic_vector (1 to 1);
signal BWN_1_0_0 : std_logic_vector (3 to 3);
signal IOWS_1 : std_logic_vector (3 downto 0);
signal ACOUNT_S : std_logic_vector (9 downto 1);
signal SSRSTATE_11 : std_logic_vector (0 to 0);
signal SSRSTATE23_U_0_AM : std_logic_vector (4 to 4);
signal SSRSTATE23_U_0_BM : std_logic_vector (4 to 4);
signal ROMRWS : std_logic_vector (2 downto 1);
signal IOWS : std_logic_vector (2 downto 1);
signal ROMWWS : std_logic_vector (2 downto 1);
signal D16MUX : std_logic_vector (1 downto 0);
signal ACOUNT_CRY : std_logic_vector (8 downto 1);
signal ROMSN_1_IV_L1 : std_logic ;
signal CHANGE_3 : std_logic ;
signal ROMSN_1 : std_logic ;
signal PRHREADY_6 : std_logic ;
signal N_635_I_1 : std_logic ;
signal N_635_I : std_logic ;
signal D16MUXC_0_1 : std_logic ;
signal D16MUXC_0_1_0 : std_logic ;
signal D16MUXC_0_4_INT_73 : std_logic ;
signal D16MUXC_0 : std_logic ;
signal N_371_INT_71 : std_logic ;
signal WS_1_L1 : std_logic ;
signal WS_1_L1_0 : std_logic ;
signal SSRSTATE_1_M2S2_0 : std_logic ;
signal IOSN_9_IV_L1 : std_logic ;
signal PRSTATE_0_INT_27 : std_logic ;
signal IOSN_9 : std_logic ;
signal N_317 : std_logic ;
signal N_619_I_L1 : std_logic ;
signal N_619_I : std_logic ;
signal N_620_I : std_logic ;
signal PRSTATE_1_INT_28 : std_logic ;
signal RST_I : std_logic ;
signal OEN_1 : std_logic ;
signal OEN_1_SQMUXA_2_I : std_logic ;
signal BWN_1_SQMUXA_3_I : std_logic ;
signal N_617_I : std_logic ;
signal N_599_I : std_logic ;
signal SSRSTATE_9 : std_logic ;
signal BEXCEN_1_SQMUXA_I : std_logic ;
signal DATA16_0_SQMUXA : std_logic ;
signal HMBSEL_0_SQMUXA : std_logic ;
signal HWRITE : std_logic ;
signal SSRSTATE_1_INT_21 : std_logic ;
signal HMBSEL_0_INT_33 : std_logic ;
signal HMBSEL_2_INT_35 : std_logic ;
signal BDRIVE_1 : std_logic ;
signal N_SRO_ADDRESS_2_INT_38 : std_logic ;
signal N_SRO_ADDRESS_3_INT_39 : std_logic ;
signal N_SRO_ADDRESS_4_INT_40 : std_logic ;
signal N_SRO_ADDRESS_5_INT_41 : std_logic ;
signal N_SRO_ADDRESS_6_INT_42 : std_logic ;
signal N_SRO_ADDRESS_7_INT_43 : std_logic ;
signal N_SRO_ADDRESS_8_INT_44 : std_logic ;
signal N_SRO_ADDRESS_9_INT_45 : std_logic ;
signal N_SRO_ADDRESS_10_INT_46 : std_logic ;
signal OEN_1_SQMUXA_2_I_L4 : std_logic ;
signal PRSTATE_1 : std_logic ;
signal OEN_1_SQMUXA_2_I_L6 : std_logic ;
signal N_654 : std_logic ;
signal SSRSTATE_2_INT_22 : std_logic ;
signal SSRSTATE_12_1 : std_logic ;
signal WS_1_0_BM_L1 : std_logic ;
signal WS_1_0_BM_L3 : std_logic ;
signal UN1_AHBSI_INT_68 : std_logic ;
signal HSEL_5_INT_67 : std_logic ;
signal WS_1_0_BM_L5 : std_logic ;
signal HMBSEL_4_1_INT_14 : std_logic ;
signal N_619_I_L1_L1 : std_logic ;
signal SSRSTATE6_XX_MM_M3_INT_64 : std_logic ;
signal HMBSEL_1_INT_34 : std_logic ;
signal SSRSTATE_6_SQMUXA_1 : std_logic ;
signal N_SRO_ADDRESS_0_INT_36 : std_logic ;
signal SIZE_0_INT_25 : std_logic ;
signal BWN_1_0_O3_0_L1 : std_logic ;
signal BWN_1_0_O3_0_L3 : std_logic ;
signal BWN_1_0_O3_0_L5 : std_logic ;
signal PRSTATE_2_REP1_INT_59 : std_logic ;
signal PRSTATEC_0_REP1 : std_logic ;
signal N_336 : std_logic ;
signal PRSTATEC_0_FAST : std_logic ;
signal WS_1_INT_17 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_1 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1 : std_logic ;
signal BDRIVE_0_SQMUXA_2_C : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_L1 : std_logic ;
signal BDRIVE_1_TZ : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1 : std_logic ;
signal N_SRO_BDRIVE_3_INT_15 : std_logic ;
signal BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3 : std_logic ;
signal N_668 : std_logic ;
signal BDRIVE_1_SQMUXA : std_logic ;
signal N_662_INT_60 : std_logic ;
signal SSRSTATE6_XX_MM_M3_L1 : std_logic ;
signal PRSTATE_5_INT_32 : std_logic ;
signal SSRSTATE_4_INT_24 : std_logic ;
signal SSRSTATE6_XX_MM_M3_L3 : std_logic ;
signal WS_2_SQMUXA_3_0_SX : std_logic ;
signal WS_0_SQMUXA_1_INT_57 : std_logic ;
signal WS_2_SQMUXA_3_D_INT_56 : std_logic ;
signal SSRSTATE17_2_0_M6_I_A3_A0_1 : std_logic ;
signal CHANGE_3_F1_D_0_L1 : std_logic ;
signal CHANGE_INT_69 : std_logic ;
signal PRSTATE_2_INT_29 : std_logic ;
signal WRITEN_2_SQMUXA_L1 : std_logic ;
signal WRITEN_2_SQMUXA_L3 : std_logic ;
signal WRITEN_2_SQMUXA_L5 : std_logic ;
signal WRITEN_2_SQMUXA_TZ_0 : std_logic ;
signal BWN_1_SQMUXA_2_D_0 : std_logic ;
signal WRITEN_2_SQMUXA : std_logic ;
signal WS_3_SQMUXA_1_INT_53 : std_logic ;
signal WS_1_L1_L1 : std_logic ;
signal WS_2_INT_18 : std_logic ;
signal WS_2_SQMUXA_3_0_2_L1 : std_logic ;
signal WS_2_SQMUXA_3_0_2_INT_54 : std_logic ;
signal WS_0_INT_16 : std_logic ;
signal SSRSTATE_3_INT_23 : std_logic ;
signal SSRSTATE6_1_D_0_L1_INT_65 : std_logic ;
signal WS_3_SQMUXA_0_1 : std_logic ;
signal WS_3_SQMUXA_1_A0_2 : std_logic ;
signal N_SRO_ROMSN_0_INT_12 : std_logic ;
signal PRSTATE_8_1 : std_logic ;
signal N_656_INT_66 : std_logic ;
signal N_SRO_IOSN_INT_70 : std_logic ;
signal PRSTATE_FAST_2_INT_13 : std_logic ;
signal BEXCEN_1_SQMUXA_I_1 : std_logic ;
signal HSEL_INT_58 : std_logic ;
signal PRSTATE_12_M7_I_A6_0 : std_logic ;
signal PRSTATE_12_I : std_logic ;
signal HWRITE_1 : std_logic ;
signal PRSTATE_12_0 : std_logic ;
signal PRSTATE_12_M7_I_A6 : std_logic ;
signal PRSTATE_4_INT_31 : std_logic ;
signal SIZE_1_INT_26 : std_logic ;
signal PRSTATE_1_SQMUXA : std_logic ;
signal BUS16EN_INT_72 : std_logic ;
signal N_382 : std_logic ;
signal N_383 : std_logic ;
signal N_384 : std_logic ;
signal N_385 : std_logic ;
signal N_386 : std_logic ;
signal N_387 : std_logic ;
signal N_388 : std_logic ;
signal N_389 : std_logic ;
signal N_390 : std_logic ;
signal N_391 : std_logic ;
signal N_392 : std_logic ;
signal N_393 : std_logic ;
signal N_394 : std_logic ;
signal N_395 : std_logic ;
signal N_396 : std_logic ;
signal N_397 : std_logic ;
signal N_626_I : std_logic ;
signal N_625_I : std_logic ;
signal N_624_I : std_logic ;
signal N_623_I : std_logic ;
signal N_630_I : std_logic ;
signal N_629_I : std_logic ;
signal N_628_I : std_logic ;
signal N_627_I : std_logic ;
signal ROMWRITE_1 : std_logic ;
signal IOEN_1 : std_logic ;
signal SSRSTATE_6_SQMUXA_INT_61 : std_logic ;
signal BDRIVE_1_IV_0_A0 : std_logic ;
signal BDRIVE_1_IV_0_A1 : std_logic ;
signal BDRIVE_1_IV_M9_I_0_0 : std_logic ;
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
signal NN_3 : std_logic ;
signal NN_4 : std_logic ;
signal NN_5 : std_logic ;
signal NN_6 : std_logic ;
signal NN_7 : std_logic ;
signal NN_8 : std_logic ;
signal NN_9 : std_logic ;
signal D16MUXC_1 : std_logic ;
signal D16MUXC_2 : std_logic ;
signal D16MUXC : std_logic ;
signal BDRIVE_1_IV_0_1 : std_logic ;
signal BDRIVE_1_IV_M9_I_0 : std_logic ;
signal RBDRIVEC_18 : std_logic ;
signal SSRSTATE_5_I : std_logic ;
signal SSRSTATEC_0 : std_logic ;
signal SSRSTATE23_1 : std_logic ;
signal WS_3_INT_19 : std_logic ;
signal PRSTATEC_1 : std_logic ;
signal N_337_I : std_logic ;
signal PRSTATEC_0 : std_logic ;
signal PRSTATE_3_INT_30 : std_logic ;
signal PRSTATEC : std_logic ;
signal N_342 : std_logic ;
signal PRSTATESR_0 : std_logic ;
signal PRSTATES_I : std_logic ;
signal N_SRO_ADDRESS_11_INT_47 : std_logic ;
signal WRITEN_0_SQMUXA_0_2 : std_logic ;
signal WRITEN_0_SQMUXA_D : std_logic ;
signal RBDRIVEC : std_logic ;
signal SSRSTATE_2_I_INT_55 : std_logic ;
signal HADDR_0_SQMUXA_A0_0 : std_logic ;
signal WRITEN_0_SQMUXA_0_0 : std_logic ;
signal BDRIVE_1_SQMUXA_2 : std_logic ;
signal WS_0_SQMUXA_0_0_0 : std_logic ;
signal CHANGE_1_SQMUXA_N_3_INT_63 : std_logic ;
signal SSRHREADY_2_SQMUXA_0_0_INT_62 : std_logic ;
signal N_362 : std_logic ;
signal N_363 : std_logic ;
signal SETBDRIVE : std_logic ;
signal N_341 : std_logic ;
signal BDRIVE_0_SQMUXA_2_0_0 : std_logic ;
signal BDRIVE_1_IV_0_A4_0 : std_logic ;
signal SSRSTATE_0_INT_20 : std_logic ;
signal PRHREADY_0_SQMUXA : std_logic ;
signal SSRSTATE10 : std_logic ;
signal WS_0_SQMUXA_0_C_INT_50 : std_logic ;
signal N_SRO_ADDRESS_1_INT_37 : std_logic ;
signal UN17_BUS16EN : std_logic ;
signal WS_1_SQMUXA_INT_52 : std_logic ;
signal SSRSTATE_3 : std_logic ;
signal WS_0_SQMUXA_C_INT_49 : std_logic ;
signal ROMWRITE : std_logic ;
signal IOEN : std_logic ;
signal N_APBO_PRDATA_28_INT_11 : std_logic ;
signal NN_10 : std_logic ;
signal N_481 : std_logic ;
signal N_480 : std_logic ;
signal IOWS_3_INT_6 : std_logic ;
signal IOWS_0_INT_5 : std_logic ;
signal ROMRWS_3_INT_10 : std_logic ;
signal ROMRWS_0_INT_9 : std_logic ;
signal ROMWWS_3_INT_8 : std_logic ;
signal ROMWWS_0_INT_7 : std_logic ;
signal SSRHREADY_INT_51 : std_logic ;
signal PRHREADY_INT_48 : std_logic ;
signal NN_11 : std_logic ;
begin
II_r_acount_qxuHAKL1HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_3_INT_39,
O => ACOUNT_QXU(1));
II_r_acount_qxuHAKL2HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_4_INT_40,
O => ACOUNT_QXU(2));
II_r_acount_qxuHAKL3HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_5_INT_41,
O => ACOUNT_QXU(3));
II_r_acount_qxuHAKL4HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_6_INT_42,
O => ACOUNT_QXU(4));
II_r_acount_qxuHAKL5HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_7_INT_43,
O => ACOUNT_QXU(5));
II_r_acount_qxuHAKL6HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_8_INT_44,
O => ACOUNT_QXU(6));
II_r_acount_qxuHAKL7HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_9_INT_45,
O => ACOUNT_QXU(7));
II_r_acount_qxuHAKL8HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_10_INT_46,
O => ACOUNT_QXU(8));
II_ctrl_v_romsn_1_iv: LUT4_L
generic map(
INIT => X"0EEE"
)
port map (
I0 => ROMSN_1_IV_L1,
I1 => CHANGE_3,
I2 => HMBSEL_0_INT_33,
I3 => PRSTATE_0_INT_27,
LO => ROMSN_1);
II_v_prstate_1_i_o4_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"80AA"
)
port map (
I0 => g0_44,
I1 => g0_1_0,
I2 => change_3_f1_d_0_0,
I3 => prstate_1_i_o4_s(2),
LO => PRHREADY_6);
II_v_N_635_i: LUT4_L
generic map(
INIT => X"888B"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_INT_29,
I3 => N_635_I_1,
LO => N_635_I);
II_r_d16muxc_0: LUT4_L
generic map(
INIT => X"8000"
)
port map (
I0 => BUS16EN_INT_72,
I1 => D16MUXC_0_1,
I2 => D16MUXC_0_1_0,
I3 => D16MUXC_0_4_INT_73,
LO => D16MUXC_0);
II_r_acount_lm_0HAKL0HAKR: LUT3_L
generic map(
INIT => X"1D"
)
port map (
I0 => N_SRO_ADDRESS_2_INT_38,
I1 => loadcount_7,
I2 => ACOUNT_LM_0_1(0),
LO => ACOUNT_LM(0));
II_ctrl_v_ws_1_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => N_371_INT_71,
I1 => WS_1_0_BM(1),
I2 => WS_1_0_RN_1(1),
LO => WS_1(1));
II_ctrl_v_ws_1HAKL2HAKR: LUT4_L
generic map(
INIT => X"1141"
)
port map (
I0 => N_371_INT_71,
I1 => WS_1_L1,
I2 => g0_23,
I3 => WS_1_L1_0,
LO => WS_1(2));
II_ctrl_v_ssrstate_1_0HAKL3HAKR: LUT4_L
generic map(
INIT => X"B333"
)
port map (
I0 => SSRSTATE_1_0_D_BM(3),
I1 => SSRSTATE_1_0_1(3),
I2 => SSRSTATE_1_M2S2_0,
I3 => ssrstate_2_sqmuxa_i,
LO => SSRSTATE_1(3));
II_ctrl_v_iosn_9_iv: LUT4_L
generic map(
INIT => X"0EEE"
)
port map (
I0 => IOSN_9_IV_L1,
I1 => CHANGE_3,
I2 => HMBSEL_2_INT_35,
I3 => PRSTATE_0_INT_27,
LO => IOSN_9);
II_ctrl_v_N_619_i: LUT4_L
generic map(
INIT => X"AFBF"
)
port map (
I0 => N_317,
I1 => N_619_I_L1,
I2 => BWN_1_0_O3(1),
I3 => bwn_1_sqmuxa_2_d_0_2,
LO => N_619_I);
II_ctrl_v_N_620_i: LUT4_L
generic map(
INIT => X"73FF"
)
port map (
I0 => hsize_1(1),
I1 => bwn_1_0_o3_0,
I2 => haddr_0,
I3 => bwn_1_sqmuxa_2_d,
LO => N_620_I);
II_r_prstate_iHAKL1HAKR: INV port map (
I => PRSTATE_1_INT_28,
O => PRSTATE_I(1));
II_ctrl_v_rst_i: INV port map (
I => rst,
O => RST_I);
II_r_oen: FDPE port map (
Q => n_sro_oen,
D => OEN_1,
C => clk,
PRE => RST_I,
CE => OEN_1_SQMUXA_2_I);
II_r_bwnHAKL0HAKR: FDE port map (
Q => n_sro_wrn(0),
D => N_620_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL1HAKR: FDE port map (
Q => n_sro_wrn(1),
D => N_619_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL2HAKR: FDE port map (
Q => n_sro_wrn(2),
D => N_618_i,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_bwnHAKL3HAKR: FDE port map (
Q => n_sro_wrn(3),
D => N_617_I,
C => clk,
CE => BWN_1_SQMUXA_3_I);
II_r_iosn: FDPE port map (
Q => N_SRO_IOSN_INT_70,
D => IOSN_9,
C => clk,
PRE => RST_I,
CE => N_599_I);
II_r_ramsn: FDPE port map (
Q => n_sro_ramsn(0),
D => N_574_i,
C => clk,
PRE => RST_I,
CE => SSRSTATE_9);
II_r_hwdataoutHAKL0HAKR: FDE port map (
Q => n_sro_data(0),
D => HWDATAOUT_1(0),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL1HAKR: FDE port map (
Q => n_sro_data(1),
D => HWDATAOUT_1(1),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL2HAKR: FDE port map (
Q => n_sro_data(2),
D => HWDATAOUT_1(2),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL3HAKR: FDE port map (
Q => n_sro_data(3),
D => HWDATAOUT_1(3),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL4HAKR: FDE port map (
Q => n_sro_data(4),
D => HWDATAOUT_1(4),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL5HAKR: FDE port map (
Q => n_sro_data(5),
D => HWDATAOUT_1(5),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL6HAKR: FDE port map (
Q => n_sro_data(6),
D => HWDATAOUT_1(6),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL7HAKR: FDE port map (
Q => n_sro_data(7),
D => HWDATAOUT_1(7),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL8HAKR: FDE port map (
Q => n_sro_data(8),
D => HWDATAOUT_1(8),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL9HAKR: FDE port map (
Q => n_sro_data(9),
D => HWDATAOUT_1(9),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL10HAKR: FDE port map (
Q => n_sro_data(10),
D => HWDATAOUT_1(10),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL11HAKR: FDE port map (
Q => n_sro_data(11),
D => HWDATAOUT_1(11),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL12HAKR: FDE port map (
Q => n_sro_data(12),
D => HWDATAOUT_1(12),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL13HAKR: FDE port map (
Q => n_sro_data(13),
D => HWDATAOUT_1(13),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL14HAKR: FDE port map (
Q => n_sro_data(14),
D => HWDATAOUT_1(14),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL15HAKR: FDE port map (
Q => n_sro_data(15),
D => HWDATAOUT_1(15),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL16HAKR: FDE port map (
Q => n_sro_data(16),
D => HWDATAOUT_1(16),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL17HAKR: FDE port map (
Q => n_sro_data(17),
D => HWDATAOUT_1(17),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL18HAKR: FDE port map (
Q => n_sro_data(18),
D => HWDATAOUT_1(18),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL19HAKR: FDE port map (
Q => n_sro_data(19),
D => HWDATAOUT_1(19),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL20HAKR: FDE port map (
Q => n_sro_data(20),
D => HWDATAOUT_1(20),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL21HAKR: FDE port map (
Q => n_sro_data(21),
D => HWDATAOUT_1(21),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL22HAKR: FDE port map (
Q => n_sro_data(22),
D => HWDATAOUT_1(22),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL23HAKR: FDE port map (
Q => n_sro_data(23),
D => HWDATAOUT_1(23),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL24HAKR: FDE port map (
Q => n_sro_data(24),
D => HWDATAOUT_1(24),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL25HAKR: FDE port map (
Q => n_sro_data(25),
D => HWDATAOUT_1(25),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL26HAKR: FDE port map (
Q => n_sro_data(26),
D => HWDATAOUT_1(26),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL27HAKR: FDE port map (
Q => n_sro_data(27),
D => HWDATAOUT_1(27),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL28HAKR: FDE port map (
Q => n_sro_data(28),
D => HWDATAOUT_1(28),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL29HAKR: FDE port map (
Q => n_sro_data(29),
D => HWDATAOUT_1(29),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL30HAKR: FDE port map (
Q => n_sro_data(30),
D => HWDATAOUT_1(30),
C => clk,
CE => PRSTATE_I(1));
II_r_hwdataoutHAKL31HAKR: FDE port map (
Q => n_sro_data(31),
D => HWDATAOUT_1(31),
C => clk,
CE => PRSTATE_I(1));
II_r_mcfg1_romwidthHAKL0HAKR: FDE port map (
Q => ROMWIDTH(0),
D => ROMWIDTH_1(0),
C => clk,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwidthHAKL1HAKR: FDE port map (
Q => ROMWIDTH(1),
D => ROMWIDTH_1(1),
C => clk,
CE => BEXCEN_1_SQMUXA_I);
II_r_data16HAKL0HAKR: FDE port map (
Q => DATA16(0),
D => HRDATA(16),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL1HAKR: FDE port map (
Q => DATA16(1),
D => HRDATA(17),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL2HAKR: FDE port map (
Q => DATA16(2),
D => HRDATA(18),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL3HAKR: FDE port map (
Q => DATA16(3),
D => HRDATA(19),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL4HAKR: FDE port map (
Q => DATA16(4),
D => HRDATA(20),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL5HAKR: FDE port map (
Q => DATA16(5),
D => HRDATA(21),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL6HAKR: FDE port map (
Q => DATA16(6),
D => HRDATA(22),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL7HAKR: FDE port map (
Q => DATA16(7),
D => HRDATA(23),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL8HAKR: FDE port map (
Q => DATA16(8),
D => HRDATA(24),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL9HAKR: FDE port map (
Q => DATA16(9),
D => HRDATA(25),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL10HAKR: FDE port map (
Q => DATA16(10),
D => HRDATA(26),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL11HAKR: FDE port map (
Q => DATA16(11),
D => HRDATA(27),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL12HAKR: FDE port map (
Q => DATA16(12),
D => HRDATA(28),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL13HAKR: FDE port map (
Q => DATA16(13),
D => HRDATA(29),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL14HAKR: FDE port map (
Q => DATA16(14),
D => HRDATA(30),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_data16HAKL15HAKR: FDE port map (
Q => DATA16(15),
D => HRDATA(31),
C => clk,
CE => DATA16_0_SQMUXA);
II_r_sizeHAKL0HAKR: FDE port map (
Q => SIZE_0_INT_25,
D => n_ahbsi_hsize(0),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_sizeHAKL1HAKR: FDE port map (
Q => SIZE_1_INT_26,
D => n_ahbsi_hsize(1),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hwrite: FDE port map (
Q => HWRITE,
D => n_ahbsi_hwrite,
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hwdataHAKL0HAKR: FDE port map (
Q => HWDATA(0),
D => n_ahbsi_hwdata(0),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL1HAKR: FDE port map (
Q => HWDATA(1),
D => n_ahbsi_hwdata(1),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL2HAKR: FDE port map (
Q => HWDATA(2),
D => n_ahbsi_hwdata(2),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL3HAKR: FDE port map (
Q => HWDATA(3),
D => n_ahbsi_hwdata(3),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL4HAKR: FDE port map (
Q => HWDATA(4),
D => n_ahbsi_hwdata(4),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL5HAKR: FDE port map (
Q => HWDATA(5),
D => n_ahbsi_hwdata(5),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL6HAKR: FDE port map (
Q => HWDATA(6),
D => n_ahbsi_hwdata(6),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL7HAKR: FDE port map (
Q => HWDATA(7),
D => n_ahbsi_hwdata(7),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL8HAKR: FDE port map (
Q => HWDATA(8),
D => n_ahbsi_hwdata(8),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL9HAKR: FDE port map (
Q => HWDATA(9),
D => n_ahbsi_hwdata(9),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL10HAKR: FDE port map (
Q => HWDATA(10),
D => n_ahbsi_hwdata(10),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL11HAKR: FDE port map (
Q => HWDATA(11),
D => n_ahbsi_hwdata(11),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL12HAKR: FDE port map (
Q => HWDATA(12),
D => n_ahbsi_hwdata(12),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL13HAKR: FDE port map (
Q => HWDATA(13),
D => n_ahbsi_hwdata(13),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL14HAKR: FDE port map (
Q => HWDATA(14),
D => n_ahbsi_hwdata(14),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL15HAKR: FDE port map (
Q => HWDATA(15),
D => n_ahbsi_hwdata(15),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL16HAKR: FDE port map (
Q => HWDATA(16),
D => n_ahbsi_hwdata(16),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL17HAKR: FDE port map (
Q => HWDATA(17),
D => n_ahbsi_hwdata(17),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL18HAKR: FDE port map (
Q => HWDATA(18),
D => n_ahbsi_hwdata(18),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL19HAKR: FDE port map (
Q => HWDATA(19),
D => n_ahbsi_hwdata(19),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL20HAKR: FDE port map (
Q => HWDATA(20),
D => n_ahbsi_hwdata(20),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL21HAKR: FDE port map (
Q => HWDATA(21),
D => n_ahbsi_hwdata(21),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL22HAKR: FDE port map (
Q => HWDATA(22),
D => n_ahbsi_hwdata(22),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL23HAKR: FDE port map (
Q => HWDATA(23),
D => n_ahbsi_hwdata(23),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL24HAKR: FDE port map (
Q => HWDATA(24),
D => n_ahbsi_hwdata(24),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL25HAKR: FDE port map (
Q => HWDATA(25),
D => n_ahbsi_hwdata(25),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL26HAKR: FDE port map (
Q => HWDATA(26),
D => n_ahbsi_hwdata(26),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL27HAKR: FDE port map (
Q => HWDATA(27),
D => n_ahbsi_hwdata(27),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL28HAKR: FDE port map (
Q => HWDATA(28),
D => n_ahbsi_hwdata(28),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL29HAKR: FDE port map (
Q => HWDATA(29),
D => n_ahbsi_hwdata(29),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL30HAKR: FDE port map (
Q => HWDATA(30),
D => n_ahbsi_hwdata(30),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hwdataHAKL31HAKR: FDE port map (
Q => HWDATA(31),
D => n_ahbsi_hwdata(31),
C => clk,
CE => SSRSTATE_1_INT_21);
II_r_hrdataHAKL22HAKR: FD port map (
Q => HRDATA(22),
D => n_sri_data(22),
C => clk);
II_r_hrdataHAKL23HAKR: FD port map (
Q => HRDATA(23),
D => n_sri_data(23),
C => clk);
II_r_hrdataHAKL24HAKR: FD port map (
Q => HRDATA(24),
D => n_sri_data(24),
C => clk);
II_r_hrdataHAKL25HAKR: FD port map (
Q => HRDATA(25),
D => n_sri_data(25),
C => clk);
II_r_hrdataHAKL26HAKR: FD port map (
Q => HRDATA(26),
D => n_sri_data(26),
C => clk);
II_r_hrdataHAKL27HAKR: FD port map (
Q => HRDATA(27),
D => n_sri_data(27),
C => clk);
II_r_hrdataHAKL28HAKR: FD port map (
Q => HRDATA(28),
D => n_sri_data(28),
C => clk);
II_r_hrdataHAKL29HAKR: FD port map (
Q => HRDATA(29),
D => n_sri_data(29),
C => clk);
II_r_hrdataHAKL30HAKR: FD port map (
Q => HRDATA(30),
D => n_sri_data(30),
C => clk);
II_r_hrdataHAKL31HAKR: FD port map (
Q => HRDATA(31),
D => n_sri_data(31),
C => clk);
II_r_hrdataHAKL7HAKR: FD port map (
Q => HRDATA(7),
D => n_sri_data(7),
C => clk);
II_r_hrdataHAKL8HAKR: FD port map (
Q => HRDATA(8),
D => n_sri_data(8),
C => clk);
II_r_hrdataHAKL9HAKR: FD port map (
Q => HRDATA(9),
D => n_sri_data(9),
C => clk);
II_r_hrdataHAKL10HAKR: FD port map (
Q => HRDATA(10),
D => n_sri_data(10),
C => clk);
II_r_hrdataHAKL11HAKR: FD port map (
Q => HRDATA(11),
D => n_sri_data(11),
C => clk);
II_r_hrdataHAKL12HAKR: FD port map (
Q => HRDATA(12),
D => n_sri_data(12),
C => clk);
II_r_hrdataHAKL13HAKR: FD port map (
Q => HRDATA(13),
D => n_sri_data(13),
C => clk);
II_r_hrdataHAKL14HAKR: FD port map (
Q => HRDATA(14),
D => n_sri_data(14),
C => clk);
II_r_hrdataHAKL15HAKR: FD port map (
Q => HRDATA(15),
D => n_sri_data(15),
C => clk);
II_r_hrdataHAKL16HAKR: FD port map (
Q => HRDATA(16),
D => n_sri_data(16),
C => clk);
II_r_hrdataHAKL17HAKR: FD port map (
Q => HRDATA(17),
D => n_sri_data(17),
C => clk);
II_r_hrdataHAKL18HAKR: FD port map (
Q => HRDATA(18),
D => n_sri_data(18),
C => clk);
II_r_hrdataHAKL19HAKR: FD port map (
Q => HRDATA(19),
D => n_sri_data(19),
C => clk);
II_r_hrdataHAKL20HAKR: FD port map (
Q => HRDATA(20),
D => n_sri_data(20),
C => clk);
II_r_hrdataHAKL21HAKR: FD port map (
Q => HRDATA(21),
D => n_sri_data(21),
C => clk);
II_r_hrdataHAKL0HAKR: FD port map (
Q => HRDATA(0),
D => n_sri_data(0),
C => clk);
II_r_hrdataHAKL1HAKR: FD port map (
Q => HRDATA(1),
D => n_sri_data(1),
C => clk);
II_r_hrdataHAKL2HAKR: FD port map (
Q => HRDATA(2),
D => n_sri_data(2),
C => clk);
II_r_hrdataHAKL3HAKR: FD port map (
Q => HRDATA(3),
D => n_sri_data(3),
C => clk);
II_r_hrdataHAKL4HAKR: FD port map (
Q => HRDATA(4),
D => n_sri_data(4),
C => clk);
II_r_hrdataHAKL5HAKR: FD port map (
Q => HRDATA(5),
D => n_sri_data(5),
C => clk);
II_r_hrdataHAKL6HAKR: FD port map (
Q => HRDATA(6),
D => n_sri_data(6),
C => clk);
II_r_hmbselHAKL0HAKR: FDCE port map (
Q => HMBSEL_0_INT_33,
D => n_ahbsi_hmbsel(0),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL21HAKR: FDE port map (
Q => n_sro_address(21),
D => n_ahbsi_haddr(21),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL22HAKR: FDE port map (
Q => n_sro_address(22),
D => n_ahbsi_haddr(22),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL23HAKR: FDE port map (
Q => n_sro_address(23),
D => n_ahbsi_haddr(23),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL24HAKR: FDE port map (
Q => n_sro_address(24),
D => n_ahbsi_haddr(24),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL25HAKR: FDE port map (
Q => n_sro_address(25),
D => n_ahbsi_haddr(25),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL26HAKR: FDE port map (
Q => n_sro_address(26),
D => n_ahbsi_haddr(26),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL27HAKR: FDE port map (
Q => n_sro_address(27),
D => n_ahbsi_haddr(27),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL28HAKR: FDE port map (
Q => n_sro_address(28),
D => n_ahbsi_haddr(28),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL29HAKR: FDE port map (
Q => n_sro_address(29),
D => n_ahbsi_haddr(29),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL30HAKR: FDE port map (
Q => n_sro_address(30),
D => n_ahbsi_haddr(30),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL31HAKR: FDE port map (
Q => n_sro_address(31),
D => n_ahbsi_haddr(31),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_hmbselHAKL2HAKR: FDCE port map (
Q => HMBSEL_2_INT_35,
D => n_ahbsi_hmbsel(2),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_hmbselHAKL1HAKR: FDCE port map (
Q => HMBSEL_1_INT_34,
D => n_ahbsi_hmbsel(1),
C => clk,
CLR => RST_I,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL6HAKR: FDE port map (
Q => HADDR(6),
D => n_ahbsi_haddr(6),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL7HAKR: FDE port map (
Q => HADDR(7),
D => n_ahbsi_haddr(7),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL8HAKR: FDE port map (
Q => HADDR(8),
D => n_ahbsi_haddr(8),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL9HAKR: FDE port map (
Q => HADDR(9),
D => n_ahbsi_haddr(9),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL10HAKR: FDE port map (
Q => HADDR(10),
D => n_ahbsi_haddr(10),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL11HAKR: FDE port map (
Q => HADDR(11),
D => n_ahbsi_haddr(11),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL12HAKR: FDE port map (
Q => n_sro_address(12),
D => n_ahbsi_haddr(12),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL13HAKR: FDE port map (
Q => n_sro_address(13),
D => n_ahbsi_haddr(13),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL14HAKR: FDE port map (
Q => n_sro_address(14),
D => n_ahbsi_haddr(14),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL15HAKR: FDE port map (
Q => n_sro_address(15),
D => n_ahbsi_haddr(15),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL16HAKR: FDE port map (
Q => n_sro_address(16),
D => n_ahbsi_haddr(16),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL17HAKR: FDE port map (
Q => n_sro_address(17),
D => n_ahbsi_haddr(17),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL18HAKR: FDE port map (
Q => n_sro_address(18),
D => n_ahbsi_haddr(18),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL19HAKR: FDE port map (
Q => n_sro_address(19),
D => n_ahbsi_haddr(19),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL20HAKR: FDE port map (
Q => n_sro_address(20),
D => n_ahbsi_haddr(20),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_ssrstateHAKL4HAKR: FD port map (
Q => SSRSTATE_4_INT_24,
D => ssrstate_1_2,
C => clk);
II_r_ssrstateHAKL3HAKR: FD port map (
Q => SSRSTATE_3_INT_23,
D => SSRSTATE_1(3),
C => clk);
II_r_ssrstateHAKL2HAKR: FD port map (
Q => SSRSTATE_2_INT_22,
D => SSRSTATE_1(2),
C => clk);
II_r_haddrHAKL0HAKR: FDE port map (
Q => N_SRO_ADDRESS_0_INT_36,
D => n_ahbsi_haddr(0),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL2HAKR: FDE port map (
Q => HADDR(2),
D => n_ahbsi_haddr(2),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL3HAKR: FDE port map (
Q => HADDR(3),
D => n_ahbsi_haddr(3),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL4HAKR: FDE port map (
Q => HADDR(4),
D => n_ahbsi_haddr(4),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_haddrHAKL5HAKR: FDE port map (
Q => HADDR(5),
D => n_ahbsi_haddr(5),
C => clk,
CE => HMBSEL_0_SQMUXA);
II_r_wsHAKL2HAKR: FD port map (
Q => WS_2_INT_18,
D => WS_1(2),
C => clk);
II_r_wsHAKL3HAKR: FD port map (
Q => WS_3_INT_19,
D => ws_1_3,
C => clk);
II_r_wsHAKL0HAKR: FD port map (
Q => WS_0_INT_16,
D => ws_1_0,
C => clk);
II_r_wsHAKL1HAKR: FD port map (
Q => WS_1_INT_17,
D => WS_1(1),
C => clk);
II_r_bdrive: FDP port map (
Q => N_SRO_BDRIVE_3_INT_15,
D => BDRIVE_1,
C => clk,
PRE => RST_I);
II_r_change: FDC port map (
Q => CHANGE_INT_69,
D => CHANGE_3,
C => clk,
CLR => RST_I);
II_r_acountHAKL0HAKR: FD port map (
Q => N_SRO_ADDRESS_2_INT_38,
D => ACOUNT_LM(0),
C => clk);
II_r_acountHAKL1HAKR: FD port map (
Q => N_SRO_ADDRESS_3_INT_39,
D => ACOUNT_LM(1),
C => clk);
II_r_acountHAKL2HAKR: FD port map (
Q => N_SRO_ADDRESS_4_INT_40,
D => ACOUNT_LM(2),
C => clk);
II_r_acountHAKL3HAKR: FD port map (
Q => N_SRO_ADDRESS_5_INT_41,
D => ACOUNT_LM(3),
C => clk);
II_r_acountHAKL4HAKR: FD port map (
Q => N_SRO_ADDRESS_6_INT_42,
D => ACOUNT_LM(4),
C => clk);
II_r_acountHAKL5HAKR: FD port map (
Q => N_SRO_ADDRESS_7_INT_43,
D => ACOUNT_LM(5),
C => clk);
II_r_acountHAKL6HAKR: FD port map (
Q => N_SRO_ADDRESS_8_INT_44,
D => ACOUNT_LM(6),
C => clk);
II_r_acountHAKL7HAKR: FD port map (
Q => N_SRO_ADDRESS_9_INT_45,
D => ACOUNT_LM(7),
C => clk);
II_r_acountHAKL8HAKR: FD port map (
Q => N_SRO_ADDRESS_10_INT_46,
D => ACOUNT_LM(8),
C => clk);
II_r_acountHAKL9HAKR: FD port map (
Q => N_SRO_ADDRESS_11_INT_47,
D => ACOUNT_LM(9),
C => clk);
II_v_oen_1_sqmuxa_2_i_L4: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => change_3_f0,
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
LO => OEN_1_SQMUXA_2_I_L4);
II_v_oen_1_sqmuxa_2_i_L6: LUT4_L
generic map(
INIT => X"4303"
)
port map (
I0 => OEN_1_SQMUXA_2_I_L4,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATE_1,
I3 => hsel_1(0),
LO => OEN_1_SQMUXA_2_I_L6);
II_v_oen_1_sqmuxa_2_i: LUT4
generic map(
INIT => X"DFCC"
)
port map (
I0 => N_654,
I1 => OEN_1_SQMUXA_2_I_L6,
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE_12_1,
O => OEN_1_SQMUXA_2_I);
II_ctrl_v_ssrstate_1_0_1HAKL3HAKR: LUT3
generic map(
INIT => X"35"
)
port map (
I0 => SSRSTATE_1_0_D_AM(3),
I1 => ssrstate_1_m1(3),
I2 => ssrstate_2_sqmuxa_i,
O => SSRSTATE_1_0_1(3));
II_ctrl_v_ws_1_0_bm_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_1_INT_21,
O => WS_1_0_BM_L1);
II_ctrl_v_ws_1_0_bm_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_656_INT_66,
I1 => rst,
O => WS_1_0_BM_L3);
II_ctrl_v_ws_1_0_bm_L5: LUT4
generic map(
INIT => X"0E00"
)
port map (
I0 => SSRSTATE6_1_D_0_L1_INT_65,
I1 => WS_1_0_BM_L1,
I2 => UN1_AHBSI_INT_68,
I3 => HSEL_5_INT_67,
O => WS_1_0_BM_L5);
II_ctrl_v_ws_1_0_bmHAKL1HAKR: LUT4
generic map(
INIT => X"80AA"
)
port map (
I0 => WS_1_0_BM_L3,
I1 => WS_1_0_BM_L5,
I2 => HMBSEL_4_1_INT_14,
I3 => SSRSTATE6_XX_MM_M3_INT_64,
O => WS_1_0_BM(1));
II_ctrl_v_N_619_i_L1_L1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => CHANGE_1_SQMUXA_N_3_INT_63,
I1 => SSRHREADY_2_SQMUXA_0_0_INT_62,
O => N_619_I_L1_L1);
II_ctrl_v_N_619_i_L1: LUT4
generic map(
INIT => X"80CC"
)
port map (
I0 => N_619_I_L1_L1,
I1 => n_ahbsi_hwrite,
I2 => HMBSEL_4_1_INT_14,
I3 => SSRSTATE6_XX_MM_M3_INT_64,
O => N_619_I_L1);
II_ctrl_v_hmbsel_4HAKL1HAKR: LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => HMBSEL_4_X1(1),
I1 => n_ahbsi_htrans(1),
I2 => HMBSEL_1_INT_34,
O => HMBSEL_4_1_INT_14);
II_v_ssrstate_6_sqmuxa: LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => g0_52_x0,
I1 => g0_52_x1,
I2 => n_ahbsi_htrans(1),
I3 => SSRSTATE_6_SQMUXA_1,
O => SSRSTATE_6_SQMUXA_INT_61);
II_v_ssrstate_6_sqmuxa_1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => SSRSTATE_2_INT_22,
O => SSRSTATE_6_SQMUXA_1);
II_ctrl_v_bwn_1_0_o3_0_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => N_SRO_ADDRESS_0_INT_36,
I1 => SIZE_0_INT_25,
O => BWN_1_0_O3_0_L1);
II_ctrl_v_bwn_1_0_o3_0_L3: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_haddr(0),
I1 => n_ahbsi_hsize(0),
O => BWN_1_0_O3_0_L3);
II_ctrl_v_bwn_1_0_o3_0_L5: LUT4_L
generic map(
INIT => X"00E4"
)
port map (
I0 => N_662_INT_60,
I1 => BWN_1_0_O3_0_L1,
I2 => BWN_1_0_O3_0_L3,
I3 => hsize_1(1),
LO => BWN_1_0_O3_0_L5);
II_ctrl_v_bwn_1_0_o3_0HAKL1HAKR: LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => BWN_1_0_O3_0_L5,
I1 => rst,
I2 => PRSTATE_2_REP1_INT_59,
I3 => bwn_0_sqmuxa_1,
O => BWN_1_0_O3(1));
II_r_prstate_2_rep1: FDR port map (
Q => PRSTATE_2_REP1_INT_59,
D => PRSTATEC_0_REP1,
C => clk,
R => RST_I);
II_r_prstatec_0_rep1: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0_REP1);
II_r_prstate_fastHAKL2HAKR: FDR port map (
Q => PRSTATE_FAST_2_INT_13,
D => PRSTATEC_0_FAST,
C => clk,
R => RST_I);
II_r_prstatec_0_fast: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0_FAST);
II_ctrl_v_ws_1_0_rnHAKL1HAKR: LUT4_L
generic map(
INIT => X"4EE4"
)
port map (
I0 => g0_25,
I1 => WS_1_2_0_D(1),
I2 => WS_1_0_AM_1(1),
I3 => WS_1_INT_17,
LO => WS_1_0_RN_1(1));
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_L1: LUT4_L
generic map(
INIT => X"3100"
)
port map (
I0 => BDRIVE_1_IV_M9_I_A4_0_2_1,
I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1,
I2 => SSRSTATE_1_INT_21,
I3 => BDRIVE_0_SQMUXA_2_C,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_L1);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2: LUT4
generic map(
INIT => X"D5F5"
)
port map (
I0 => BDRIVE_1_IV_M9_I_A4_0_2_2_L1,
I1 => UN1_AHBSI_INT_68,
I2 => BDRIVE_1_IV_M9_I_A4_0_2_1,
I3 => HSEL_5_INT_67,
O => BDRIVE_1_TZ);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1_L3: LUT4_L
generic map(
INIT => X"1015"
)
port map (
I0 => N_SRO_BDRIVE_3_INT_15,
I1 => D16MUXC_0_4_INT_73,
I2 => PRSTATE_1_INT_28,
I3 => PRSTATE_2_REP1_INT_59,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_2_1: LUT4_L
generic map(
INIT => X"0F8F"
)
port map (
I0 => N_668,
I1 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L1,
I2 => BDRIVE_1_IV_M9_I_A4_0_2_2_1_L3,
I3 => BDRIVE_1_SQMUXA,
LO => BDRIVE_1_IV_M9_I_A4_0_2_2_1);
II_ctrl_v_romsn_1_iv_L1: LUT4_L
generic map(
INIT => X"27FF"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hmbsel(0),
I2 => HMBSEL_0_INT_33,
I3 => prstate_1_i_o4_s(2),
LO => ROMSN_1_IV_L1);
II_ctrl_v_iosn_9_iv_L1: LUT4_L
generic map(
INIT => X"27FF"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hmbsel(2),
I2 => HMBSEL_2_INT_35,
I3 => prstate_1_i_o4_s(2),
LO => IOSN_9_IV_L1);
II_ctrl_v_ssrstate6_xx_mm_m3_L1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => HMBSEL_1_INT_34,
I1 => HSEL_INT_58,
O => SSRSTATE6_XX_MM_M3_L1);
II_ctrl_v_ssrstate6_xx_mm_m3_L3: LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => PRSTATE_5_INT_32,
I3 => SSRSTATE_4_INT_24,
O => SSRSTATE6_XX_MM_M3_L3);
II_ctrl_v_ssrstate6_xx_mm_m3: LUT4
generic map(
INIT => X"CEFE"
)
port map (
I0 => SSRSTATE6_XX_MM_M3_L1,
I1 => SSRSTATE6_XX_MM_M3_L3,
I2 => n_ahbsi_hready,
I3 => hsel_4,
O => SSRSTATE6_XX_MM_M3_INT_64);
II_v_ws_2_sqmuxa_3_0: LUT4
generic map(
INIT => X"0700"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_SX,
I3 => WS_2_SQMUXA_3_D_INT_56,
O => N_371_INT_71);
II_v_ws_2_sqmuxa_3_0_sx: LUT4_L
generic map(
INIT => X"CF4F"
)
port map (
I0 => SSRSTATE_2_I_INT_55,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_2_INT_54,
I3 => WS_3_SQMUXA_1_INT_53,
LO => WS_2_SQMUXA_3_0_SX);
II_v_ws_2_sqmuxa_3_0_x: LUT3_L
generic map(
INIT => X"70"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_D_INT_56,
LO => ws_2_sqmuxa_3_0_x);
II_ctrl_v_hmbsel_4_x1HAKL1HAKR: LUT4_L
generic map(
INIT => X"BF80"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => n_ahbsi_hsel(0),
I3 => HMBSEL_1_INT_34,
LO => HMBSEL_4_X1(1));
II_un1_v_ssrstate17_2_0_m6_i_1: LUT4
generic map(
INIT => X"4F0F"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_htrans(0),
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE17_2_0_M6_I_A3_A0_1,
O => ssrstate17_2_0_m6_i_1);
II_ctrl_v_change_3_f1_d_0_L1: LUT4_L
generic map(
INIT => X"4440"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
I3 => SSRSTATE_2_INT_22,
LO => CHANGE_3_F1_D_0_L1);
II_ctrl_v_change_3_f1_d_0: LUT4
generic map(
INIT => X"00F2"
)
port map (
I0 => CHANGE_3_F1_D_0_L1,
I1 => HMBSEL_4_1_INT_14,
I2 => CHANGE_INT_69,
I3 => SSRSTATE_4_INT_24,
O => CHANGE_3);
II_ctrl_un1_v_ssrstate17: LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
O => N_654);
II_un1_v_writen_2_sqmuxa_L1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => PRSTATE_2_INT_29,
O => WRITEN_2_SQMUXA_L1);
II_un1_v_writen_2_sqmuxa_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
O => WRITEN_2_SQMUXA_L3);
II_un1_v_writen_2_sqmuxa_L5: LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => WRITEN_2_SQMUXA_L3,
I1 => HMBSEL_4_1_INT_14,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_2_INT_22,
O => WRITEN_2_SQMUXA_L5);
II_un1_v_writen_2_sqmuxa: LUT4
generic map(
INIT => X"7555"
)
port map (
I0 => WRITEN_2_SQMUXA_L1,
I1 => WRITEN_2_SQMUXA_L5,
I2 => WRITEN_2_SQMUXA_TZ_0,
I3 => BWN_1_SQMUXA_2_D_0,
O => WRITEN_2_SQMUXA);
II_ctrl_v_ws_1_L1_L1: LUT3_L
generic map(
INIT => X"37"
)
port map (
I0 => g0_30,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_3_SQMUXA_1_INT_53,
LO => WS_1_L1_L1);
II_ctrl_v_ws_1_L1: LUT4_L
generic map(
INIT => X"B11B"
)
port map (
I0 => g0_25,
I1 => WS_1_2_0_D(2),
I2 => WS_1_L1_L1,
I3 => WS_2_INT_18,
LO => WS_1_L1);
II_v_ws_2_sqmuxa_3_0_2_L1: LUT4
generic map(
INIT => X"0013"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => PRSTATE_1_INT_28,
I2 => ws_2_sqmuxa_0,
I3 => ws_4_sqmuxa_0,
O => WS_2_SQMUXA_3_0_2_L1);
II_v_ws_2_sqmuxa_3_0_2: LUT4
generic map(
INIT => X"003B"
)
port map (
I0 => WS_2_SQMUXA_3_0_2_L1,
I1 => rst,
I2 => PRSTATE_3_INT_30,
I3 => WS_1_SQMUXA_INT_52,
O => WS_2_SQMUXA_3_0_2_INT_54);
II_ctrl_v_ws_1_L1_0: LUT3
generic map(
INIT => X"57"
)
port map (
I0 => g0_25,
I1 => WS_0_INT_16,
I2 => WS_1_INT_17,
O => WS_1_L1_0);
II_ctrl_v_ssrhready_8_f0_L5: LUT3_L
generic map(
INIT => X"2F"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => ssrstate17_1_xx_mm_N_4,
I2 => SSRSTATE_1_INT_21,
LO => ssrhready_8_f0_L5);
II_ctrl_v_ssrhready_8_f0_L8: LUT4
generic map(
INIT => X"0013"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SSRHREADY_INT_51,
I2 => SSRSTATE_3_INT_23,
I3 => ssrstate_1_sqmuxa_1,
O => ssrhready_8_f0_L8);
II_un1_v_hsel_1_0_L3: LUT2_L
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_hmbsel(0),
I1 => n_ahbsi_hmbsel(2),
LO => hsel_1_0_L3);
II_un1_v_ssrstate6_1_d_0_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
O => SSRSTATE6_1_D_0_L1_INT_65);
II_v_ws_3_sqmuxa_0: LUT4
generic map(
INIT => X"8B03"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => WS_3_SQMUXA_0_1,
I3 => WS_3_SQMUXA_1_A0_2,
O => WS_3_SQMUXA_1_INT_53);
II_v_ws_3_sqmuxa_0_1: LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => d_m1_e_0_0,
I1 => n_ahbsi_htrans(0),
I2 => SSRSTATE_1_INT_21,
O => WS_3_SQMUXA_0_1);
II_un1_r_prstate_8: LUT4
generic map(
INIT => X"0301"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_5_INT_32,
I3 => PRSTATE_8_1,
O => N_656_INT_66);
II_un1_r_prstate_8_1: LUT3_L
generic map(
INIT => X"57"
)
port map (
I0 => N_SRO_IOSN_INT_70,
I1 => PRSTATE_4_INT_31,
I2 => PRSTATE_FAST_2_INT_13,
LO => PRSTATE_8_1);
II_v_mcfg1_bexcen_1_sqmuxa_i: LUT4
generic map(
INIT => X"B333"
)
port map (
I0 => n_apbi_pwrite,
I1 => rst,
I2 => N_APBO_PRDATA_28_INT_11,
I3 => BEXCEN_1_SQMUXA_I_1,
O => BEXCEN_1_SQMUXA_I);
II_v_mcfg1_bexcen_1_sqmuxa_i_1: LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => n_apbi_paddr(4),
I1 => n_apbi_paddr(5),
I2 => n_apbi_penable,
I3 => n_apbi_psel(0),
O => BEXCEN_1_SQMUXA_I_1);
II_un1_v_ssrstate_1_sqmuxa_1_0_m3_0_1: LUT4
generic map(
INIT => X"0D08"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => HSEL_INT_58,
O => ssrstate_1_sqmuxa_1_0_m3_0_1);
II_un1_r_prstate: LUT4
generic map(
INIT => X"1911"
)
port map (
I0 => PRSTATE_5_INT_32,
I1 => PRSTATE_1,
I2 => PRSTATE_12_M7_I_A6_0,
I3 => hsel_1(0),
O => PRSTATE_12_I);
II_un1_r_prstate_1_0: LUT4
generic map(
INIT => X"0343"
)
port map (
I0 => HWRITE_1,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATE_12_0,
I3 => PRSTATE_12_M7_I_A6,
O => PRSTATE_1);
II_ctrl_v_ws_1_0_am_1HAKL1HAKR: LUT4_L
generic map(
INIT => X"0515"
)
port map (
I0 => WS_0_INT_16,
I1 => g0_30,
I2 => WS_0_SQMUXA_1_INT_57,
I3 => WS_3_SQMUXA_1_INT_53,
LO => WS_1_0_AM_1(1));
II_r_d16muxc_0_1_0: LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => PRSTATE_4_INT_31,
I2 => SIZE_0_INT_25,
I3 => SIZE_1_INT_26,
O => D16MUXC_0_1_0);
II_r_acount_lm_0_1HAKL0HAKR: LUT3
generic map(
INIT => X"27"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(2),
I2 => HADDR(2),
O => ACOUNT_LM_0_1(0));
II_v_N_635_i_1: LUT3_L
generic map(
INIT => X"0D"
)
port map (
I0 => SSRSTATE_1_INT_21,
I1 => loadcount_1_sqmuxa,
I2 => ssrstate_1_sqmuxa_1,
LO => N_635_I_1);
II_ctrl_v_oen_1_iv: LUT3_L
generic map(
INIT => X"E2"
)
port map (
I0 => SSRSTATE6_XX_MM_M3_INT_64,
I1 => PRSTATE_12_I,
I2 => PRSTATE_1_SQMUXA,
LO => OEN_1);
II_ctrl_v_N_617_i: LUT4_L
generic map(
INIT => X"0FBF"
)
port map (
I0 => N_646,
I1 => n_ahbsi_hwrite,
I2 => BWN_1_0_0(3),
I3 => bwn_1_sqmuxa_2_d_0_2,
LO => N_617_I);
II_ctrl_v_hwdataout_1_0HAKL0HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(0),
I1 => BUS16EN_INT_72,
I2 => HWDATA(0),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(0));
II_ctrl_v_hwdataout_1_0HAKL1HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(1),
I1 => BUS16EN_INT_72,
I2 => HWDATA(1),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(1));
II_ctrl_v_hwdataout_1_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(2),
I1 => BUS16EN_INT_72,
I2 => HWDATA(2),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(2));
II_ctrl_v_hwdataout_1_0HAKL3HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(3),
I1 => BUS16EN_INT_72,
I2 => HWDATA(3),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(3));
II_ctrl_v_hwdataout_1_0HAKL4HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(4),
I1 => BUS16EN_INT_72,
I2 => HWDATA(4),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(4));
II_ctrl_v_hwdataout_1_0HAKL5HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(5),
I1 => BUS16EN_INT_72,
I2 => HWDATA(5),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(5));
II_ctrl_v_hwdataout_1_0HAKL6HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(6),
I1 => BUS16EN_INT_72,
I2 => HWDATA(6),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(6));
II_ctrl_v_hwdataout_1_0HAKL7HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(7),
I1 => BUS16EN_INT_72,
I2 => HWDATA(7),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(7));
II_ctrl_v_hwdataout_1_0HAKL8HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(8),
I1 => BUS16EN_INT_72,
I2 => HWDATA(8),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(8));
II_ctrl_v_hwdataout_1_0HAKL9HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(9),
I1 => BUS16EN_INT_72,
I2 => HWDATA(9),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(9));
II_ctrl_v_hwdataout_1_0HAKL10HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(10),
I1 => BUS16EN_INT_72,
I2 => HWDATA(10),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(10));
II_ctrl_v_hwdataout_1_0HAKL11HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(11),
I1 => BUS16EN_INT_72,
I2 => HWDATA(11),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(11));
II_ctrl_v_hwdataout_1_0HAKL12HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(12),
I1 => BUS16EN_INT_72,
I2 => HWDATA(12),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(12));
II_ctrl_v_hwdataout_1_0HAKL13HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(13),
I1 => BUS16EN_INT_72,
I2 => HWDATA(13),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(13));
II_ctrl_v_hwdataout_1_0HAKL14HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(14),
I1 => BUS16EN_INT_72,
I2 => HWDATA(14),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(14));
II_ctrl_v_hwdataout_1_0HAKL15HAKR: LUT4_L
generic map(
INIT => X"E2F0"
)
port map (
I0 => n_ahbsi_hwdata(15),
I1 => BUS16EN_INT_72,
I2 => HWDATA(15),
I3 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(15));
II_ctrl_v_hwdataout_1_0HAKL16HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_382,
I1 => HWDATA(16),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(16));
II_ctrl_v_hwdataout_1_0HAKL17HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_383,
I1 => HWDATA(17),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(17));
II_ctrl_v_hwdataout_1_0HAKL18HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_384,
I1 => HWDATA(18),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(18));
II_ctrl_v_hwdataout_1_0HAKL19HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_385,
I1 => HWDATA(19),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(19));
II_ctrl_v_hwdataout_1_0HAKL20HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_386,
I1 => HWDATA(20),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(20));
II_ctrl_v_hwdataout_1_0HAKL21HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_387,
I1 => HWDATA(21),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(21));
II_ctrl_v_hwdataout_1_0HAKL22HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_388,
I1 => HWDATA(22),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(22));
II_ctrl_v_hwdataout_1_0HAKL23HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_389,
I1 => HWDATA(23),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(23));
II_ctrl_v_hwdataout_1_0HAKL24HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_390,
I1 => HWDATA(24),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(24));
II_ctrl_v_hwdataout_1_0HAKL25HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_391,
I1 => HWDATA(25),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(25));
II_ctrl_v_hwdataout_1_0HAKL26HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_392,
I1 => HWDATA(26),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(26));
II_ctrl_v_hwdataout_1_0HAKL27HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_393,
I1 => HWDATA(27),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(27));
II_ctrl_v_hwdataout_1_0HAKL28HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_394,
I1 => HWDATA(28),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(28));
II_ctrl_v_hwdataout_1_0HAKL29HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_395,
I1 => HWDATA(29),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(29));
II_ctrl_v_hwdataout_1_0HAKL30HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_396,
I1 => HWDATA(30),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(30));
II_ctrl_v_hwdataout_1_0HAKL31HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => N_397,
I1 => HWDATA(31),
I2 => PRSTATE_2_INT_29,
LO => HWDATAOUT_1(31));
II_ctrl_v_mcfg1_N_626_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_4,
I1 => rst,
LO => N_626_I);
II_ctrl_v_mcfg1_N_625_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_5,
I1 => rst,
LO => N_625_I);
II_ctrl_v_mcfg1_N_624_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_6,
I1 => rst,
LO => N_624_I);
II_ctrl_v_mcfg1_N_623_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_7,
I1 => rst,
LO => N_623_I);
II_ctrl_v_mcfg1_N_630_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_0,
I1 => rst,
LO => N_630_I);
II_ctrl_v_mcfg1_N_629_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_1,
I1 => rst,
LO => N_629_I);
II_ctrl_v_mcfg1_N_628_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_2,
I1 => rst,
LO => N_628_I);
II_ctrl_v_mcfg1_N_627_i: LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => n_apbi_pwdata_3,
I1 => rst,
LO => N_627_I);
II_ctrl_v_mcfg1_iows_1HAKL0HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_20,
I1 => rst,
LO => IOWS_1(0));
II_ctrl_v_mcfg1_iows_1HAKL1HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_21,
I1 => rst,
LO => IOWS_1(1));
II_ctrl_v_mcfg1_iows_1HAKL2HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_22,
I1 => rst,
LO => IOWS_1(2));
II_ctrl_v_mcfg1_iows_1HAKL3HAKR: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_23,
I1 => rst,
LO => IOWS_1(3));
II_ctrl_v_mcfg1_romwidth_1_0HAKL0HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => n_apbi_pwdata_8,
I1 => n_sri_bwidth(0),
I2 => rst,
LO => ROMWIDTH_1(0));
II_ctrl_v_mcfg1_romwidth_1_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"AC"
)
port map (
I0 => n_apbi_pwdata_9,
I1 => n_sri_bwidth(1),
I2 => rst,
LO => ROMWIDTH_1(1));
II_ctrl_v_mcfg1_romwrite_1: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_11,
I1 => rst,
LO => ROMWRITE_1);
II_ctrl_v_mcfg1_ioen_1: LUT2_L
generic map(
INIT => X"8"
)
port map (
I0 => n_apbi_pwdata_19,
I1 => rst,
LO => IOEN_1);
II_ctrl_v_ssrstate_1_0HAKL2HAKR: LUT4_L
generic map(
INIT => X"8A80"
)
port map (
I0 => rst,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_3_INT_23,
I3 => SSRSTATE_6_SQMUXA_INT_61,
LO => SSRSTATE_1(2));
II_ctrl_v_bdrive_1_iv_m9_i: LUT4_L
generic map(
INIT => X"1000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_A1,
I2 => BDRIVE_1_IV_M9_I_0_0,
I3 => BDRIVE_1_TZ,
LO => BDRIVE_1);
II_r_acount_lm_0HAKL1HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_1,
I2 => ACOUNT_S(1),
LO => ACOUNT_LM(1));
II_r_acount_lm_0HAKL2HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_2,
I2 => ACOUNT_S(2),
LO => ACOUNT_LM(2));
II_r_acount_lm_0HAKL3HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_3,
I2 => ACOUNT_S(3),
LO => ACOUNT_LM(3));
II_r_acount_lm_0HAKL4HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_4,
I2 => ACOUNT_S(4),
LO => ACOUNT_LM(4));
II_r_acount_lm_0HAKL5HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_5,
I2 => ACOUNT_S(5),
LO => ACOUNT_LM(5));
II_r_acount_lm_0HAKL6HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_6,
I2 => ACOUNT_S(6),
LO => ACOUNT_LM(6));
II_r_acount_lm_0HAKL7HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_7,
I2 => ACOUNT_S(7),
LO => ACOUNT_LM(7));
II_r_acount_lm_0HAKL8HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_8,
I2 => ACOUNT_S(8),
LO => ACOUNT_LM(8));
II_r_acount_lm_0HAKL9HAKR: LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => loadcount_7,
I1 => NN_9,
I2 => ACOUNT_S(9),
LO => ACOUNT_LM(9));
II_r_d16muxc: LUT3_L
generic map(
INIT => X"40"
)
port map (
I0 => un7_bus16en,
I1 => D16MUXC_1,
I2 => D16MUXC_2,
LO => D16MUXC);
II_rbdrivec_18: LUT4_L
generic map(
INIT => X"4000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_1,
I2 => BDRIVE_1_IV_M9_I_0,
I3 => BDRIVE_1_TZ,
LO => RBDRIVEC_18);
II_r_ssrstatec_0: LUT4_L
generic map(
INIT => X"0B08"
)
port map (
I0 => NoName_cnst(0),
I1 => SSRSTATE_5_I,
I2 => ssrstate_2_sqmuxa_1,
I3 => SSRSTATE_11(0),
LO => SSRSTATEC_0);
II_r_prstatec_1: LUT4_L
generic map(
INIT => X"0008"
)
port map (
I0 => SSRSTATE23_1,
I1 => PRSTATE_1_INT_28,
I2 => WS_0_INT_16,
I3 => WS_3_INT_19,
LO => PRSTATEC_1);
II_v_N_337_i: LUT3_L
generic map(
INIT => X"74"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_INT_29,
LO => N_337_I);
II_r_prstatec_0: LUT4_L
generic map(
INIT => X"A2A0"
)
port map (
I0 => N_336,
I1 => CHANGE_3,
I2 => PRSTATE_0_INT_27,
I3 => prstate_1_i_o4_s(2),
LO => PRSTATEC_0);
II_r_prstatec: LUT3_L
generic map(
INIT => X"0E"
)
port map (
I0 => PRSTATE_3_INT_30,
I1 => PRSTATE_4_INT_31,
I2 => d16mux_0_sqmuxa,
LO => PRSTATEC);
II_v_prstate_1_0_a3_0HAKL4HAKR: LUT4_L
generic map(
INIT => X"0200"
)
port map (
I0 => rst,
I1 => HWRITE_1,
I2 => CHANGE_3,
I3 => prstate_1_i_o4_s(2),
LO => N_342);
II_r_prstates_i: LUT4_L
generic map(
INIT => X"8FCF"
)
port map (
I0 => CHANGE_3,
I1 => PRSTATE_5_INT_32,
I2 => PRSTATESR_0,
I3 => hsel_1(0),
LO => PRSTATES_I);
II_r_acount_qxuHAKL9HAKR: LUT1
generic map(
INIT => X"2"
)
port map (
I0 => N_SRO_ADDRESS_11_INT_47,
O => ACOUNT_QXU(9));
II_un1_v_ssrstate23_u_0HAKL4HAKR: MUXF5 port map (
I0 => SSRSTATE23_U_0_AM(4),
I1 => SSRSTATE23_U_0_BM(4),
S => SSRSTATE_5_I,
O => ssrstate_1_m1(4));
II_v_bwn_1_sqmuxa_3_i: LUT4
generic map(
INIT => X"D555"
)
port map (
I0 => bwn_0_sqmuxa_1,
I1 => BWN_1_SQMUXA_2_D_0,
I2 => WRITEN_0_SQMUXA_0_2,
I3 => WRITEN_0_SQMUXA_D,
O => BWN_1_SQMUXA_3_I);
II_rbdrivec_19: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => BDRIVE_1_IV_0_A0,
I1 => BDRIVE_1_IV_0_1,
I2 => BDRIVE_1_IV_M9_I_0,
I3 => BDRIVE_1_TZ,
O => RBDRIVEC);
II_ctrl_v_ssrstate_1_m2s2_0: LUT4_L
generic map(
INIT => X"0010"
)
port map (
I0 => NoName_cnst(0),
I1 => SSRSTATE_1_INT_21,
I2 => change_1_sqmuxa_0,
I3 => SSRSTATE_6_SQMUXA_INT_61,
LO => SSRSTATE_1_M2S2_0);
II_ctrl_v_bwn_1_0_0HAKL3HAKR: LUT3
generic map(
INIT => X"C8"
)
port map (
I0 => hsize_1(1),
I1 => BWN_1_0_O3(1),
I2 => haddr_0,
O => BWN_1_0_0(3));
II_v_ws_2_sqmuxa_3_0_4: LUT4
generic map(
INIT => X"30B0"
)
port map (
I0 => SSRSTATE_2_I_INT_55,
I1 => WS_0_SQMUXA_1_INT_57,
I2 => WS_2_SQMUXA_3_0_2_INT_54,
I3 => WS_3_SQMUXA_1_INT_53,
O => ws_2_sqmuxa_3_0_4);
II_un1_v_N_599_i: LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => PRSTATE_1_INT_28,
I2 => HADDR_0_SQMUXA_A0_0,
I3 => PRSTATE_1_SQMUXA,
O => N_599_I);
II_ctrl_v_ssrstate_1_0_d_bmHAKL3HAKR: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => ssrstate_1_sqmuxa_1,
O => SSRSTATE_1_0_D_BM(3));
II_ctrl_v_ssrstate_1_0_d_amHAKL3HAKR: LUT3
generic map(
INIT => X"20"
)
port map (
I0 => rst,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_3_INT_23,
O => SSRSTATE_1_0_D_AM(3));
II_v_writen_0_sqmuxa_0_2: LUT4
generic map(
INIT => X"0E00"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => SSRSTATE6_XX_MM_M3_INT_64,
I2 => ssrstate_1_sqmuxa_1,
I3 => WRITEN_0_SQMUXA_0_0,
O => WRITEN_0_SQMUXA_0_2);
II_un1_r_ssrstate_12_1: LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => SSRSTATE_3_INT_23,
I1 => BDRIVE_1_SQMUXA_2,
I2 => WS_0_SQMUXA_0_0_0,
I3 => WS_0_SQMUXA_0_C_INT_50,
O => SSRSTATE_12_1);
II_v_ws_2_sqmuxa_3_d: LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
I3 => WS_0_SQMUXA_1_INT_57,
O => WS_2_SQMUXA_3_D_INT_56);
II_un1_v_writen_2_sqmuxa_tz_0: LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => SSRSTATE6_XX_MM_M3_INT_64,
I2 => SSRSTATE_2_I_INT_55,
I3 => WS_3_SQMUXA_1_INT_53,
O => WRITEN_2_SQMUXA_TZ_0);
II_un1_r_ssrstate_9: LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => N_654,
I1 => SSRSTATE_2_INT_22,
I2 => SSRSTATE_2_I_INT_55,
I3 => WS_3_SQMUXA_1_INT_53,
O => SSRSTATE_9);
II_ctrl_v_bdrive_1_iv_m9_i_0_0: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => BDRIVE_1_IV_0_1,
I1 => BDRIVE_1_IV_M9_I_0,
O => BDRIVE_1_IV_M9_I_0_0);
II_un1_r_prstate_12_m7_i_a6_0: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => change_3_f0,
I2 => HMBSEL_4_1_INT_14,
I3 => HSEL_5_INT_67,
LO => PRSTATE_12_M7_I_A6_0);
II_v_bwn_1_sqmuxa_2_d_0: LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => HMBSEL_4_1_INT_14,
I2 => CHANGE_1_SQMUXA_N_3_INT_63,
I3 => SSRHREADY_2_SQMUXA_0_0_INT_62,
O => BWN_1_SQMUXA_2_D_0);
II_un1_v_ssrstate23_u_0_bmHAKL4HAKR: LUT3
generic map(
INIT => X"B0"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_2_INT_22,
O => SSRSTATE23_U_0_BM(4));
II_un1_v_ssrstate23_u_0_amHAKL4HAKR: LUT3
generic map(
INIT => X"02"
)
port map (
I0 => SSRSTATE23_1,
I1 => WS_0_INT_16,
I2 => WS_3_INT_19,
O => SSRSTATE23_U_0_AM(4));
II_v_writen_0_sqmuxa_d: LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HMBSEL_4_1_INT_14,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_2_INT_22,
O => WRITEN_0_SQMUXA_D);
II_ctrl_v_ws_1_2_0_dHAKL1HAKR: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => N_362,
I1 => N_365,
I2 => ROMRWS(1),
O => WS_1_2_0_D(1));
II_ctrl_v_ws_1_2_0_dHAKL2HAKR: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => N_363,
I1 => N_365,
I2 => ROMRWS(2),
O => WS_1_2_0_D(2));
II_r_prstatesr_0: LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_1_SQMUXA,
O => PRSTATESR_0);
II_un1_v_haddr_0_sqmuxa_a0_0: LUT3
generic map(
INIT => X"07"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => PRSTATE_5_INT_32,
O => HADDR_0_SQMUXA_A0_0);
II_ctrl_v_bdrive_1_iv_0_a1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SETBDRIVE,
I2 => BDRIVE_1_SQMUXA,
O => BDRIVE_1_IV_0_A1);
II_v_prstate_1_0_a3HAKL4HAKR: LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rst,
I1 => un7_bus16en,
I2 => d16mux_0_sqmuxa,
O => N_341);
II_v_bdrive_0_sqmuxa_2_0: LUT4
generic map(
INIT => X"FF10"
)
port map (
I0 => N_668,
I1 => D16MUXC_0_4_INT_73,
I2 => PRSTATE_1_INT_28,
I3 => BDRIVE_0_SQMUXA_2_0_0,
O => BDRIVE_0_SQMUXA_2_C);
II_ctrl_v_bdrive_1_iv_m9_i_0: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => BDRIVE_1_IV_0_A4_0,
I1 => PRSTATE_2_REP1_INT_59,
I2 => BDRIVE_1_SQMUXA,
O => BDRIVE_1_IV_M9_I_0);
II_v_ws_0_sqmuxa_0_0_0: LUT4
generic map(
INIT => X"3133"
)
port map (
I0 => HSEL_5_INT_67,
I1 => D16MUXC_0_4_INT_73,
I2 => SSRSTATE_0_INT_20,
I3 => WS_0_SQMUXA_C_INT_49,
O => WS_0_SQMUXA_0_0_0);
II_v_prhready_0_sqmuxa: LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => un7_bus16en,
I1 => PRSTATE_0_INT_27,
I2 => d16mux_0_sqmuxa,
O => PRHREADY_0_SQMUXA);
II_v_ws_0_sqmuxa_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_656_INT_66,
I1 => rst,
O => WS_0_SQMUXA_1_INT_57);
II_v_ws_0_sqmuxa_0: LUT4
generic map(
INIT => X"040F"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_0_INT_20,
I3 => SSRSTATE_1_INT_21,
O => SSRSTATE_5_I);
II_v_prstate_1_i_m4_0HAKL2HAKR: LUT3
generic map(
INIT => X"CA"
)
port map (
I0 => HWRITE_1,
I1 => un7_bus16en,
I2 => PRSTATE_0_INT_27,
O => N_336);
II_v_bdrive_1_sqmuxa_2: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => HSEL_5_INT_67,
I2 => SSRSTATE_1_INT_21,
O => BDRIVE_1_SQMUXA_2);
II_ctrl_v_bdrive_1_iv_0_a0: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => UN1_AHBSI_INT_68,
I1 => BDRIVE_1_IV_0_A4_0,
I2 => HSEL_5_INT_67,
I3 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_0_A0);
II_ctrl_v_bdrive_1_iv_m9_i_a4_0_2_1: LUT4
generic map(
INIT => X"80A0"
)
port map (
I0 => N_668,
I1 => SSRSTATE10,
I2 => D16MUXC_0_4_INT_73,
I3 => SSRSTATE_3_INT_23,
O => BDRIVE_1_IV_M9_I_A4_0_2_1);
II_v_ws_0_sqmuxa_0_c: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_1_INT_21,
O => WS_0_SQMUXA_0_C_INT_50);
II_un1_r_prstate_12_m7_i_a6: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => change_3_f0,
I1 => CHANGE_INT_69,
O => PRSTATE_12_M7_I_A6);
II_v_prstate_1_sqmuxa: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => un7_bus16en,
I1 => d16mux_0_sqmuxa,
O => PRSTATE_1_SQMUXA);
II_ctrl_v_hwdataout_1_0_0HAKL16HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(0),
I1 => n_ahbsi_hwdata(16),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_382);
II_ctrl_v_hwdataout_1_0_0HAKL17HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(1),
I1 => n_ahbsi_hwdata(17),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_383);
II_ctrl_v_hwdataout_1_0_0HAKL18HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(2),
I1 => n_ahbsi_hwdata(18),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_384);
II_ctrl_v_hwdataout_1_0_0HAKL19HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(3),
I1 => n_ahbsi_hwdata(19),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_385);
II_ctrl_v_hwdataout_1_0_0HAKL20HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(4),
I1 => n_ahbsi_hwdata(20),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_386);
II_ctrl_v_hwdataout_1_0_0HAKL21HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(5),
I1 => n_ahbsi_hwdata(21),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_387);
II_ctrl_v_hwdataout_1_0_0HAKL22HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(6),
I1 => n_ahbsi_hwdata(22),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_388);
II_ctrl_v_hwdataout_1_0_0HAKL23HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(7),
I1 => n_ahbsi_hwdata(23),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_389);
II_ctrl_v_hwdataout_1_0_0HAKL24HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(8),
I1 => n_ahbsi_hwdata(24),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_390);
II_ctrl_v_hwdataout_1_0_0HAKL25HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(9),
I1 => n_ahbsi_hwdata(25),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_391);
II_ctrl_v_hwdataout_1_0_0HAKL26HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(10),
I1 => n_ahbsi_hwdata(26),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_392);
II_ctrl_v_hwdataout_1_0_0HAKL27HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(11),
I1 => n_ahbsi_hwdata(27),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_393);
II_ctrl_v_hwdataout_1_0_0HAKL28HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(12),
I1 => n_ahbsi_hwdata(28),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_394);
II_ctrl_v_hwdataout_1_0_0HAKL29HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(13),
I1 => n_ahbsi_hwdata(29),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_395);
II_ctrl_v_hwdataout_1_0_0HAKL30HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(14),
I1 => n_ahbsi_hwdata(30),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_396);
II_ctrl_v_hwdataout_1_0_0HAKL31HAKR: LUT4_L
generic map(
INIT => X"ACCC"
)
port map (
I0 => n_ahbsi_hwdata(15),
I1 => n_ahbsi_hwdata(31),
I2 => N_SRO_ADDRESS_1_INT_37,
I3 => BUS16EN_INT_72,
LO => N_397);
II_ctrl_v_bwn_1_0_a3_0_1HAKL0HAKR: LUT4_L
generic map(
INIT => X"0207"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hsize(0),
I2 => hsize_1(1),
I3 => SIZE_0_INT_25,
LO => N_319_1);
II_ctrl_v_bwn_1_0_a3HAKL0HAKR: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => hsize_1(1),
I1 => haddr_0,
O => N_317);
II_v_writen_0_sqmuxa_0_0: LUT4
generic map(
INIT => X"4F00"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
I3 => SSRSTATE_2_I_INT_55,
O => WRITEN_0_SQMUXA_0_0);
II_v_ssrhready_2_sqmuxa_0_0: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_2_INT_22,
O => SSRHREADY_2_SQMUXA_0_0_INT_62);
II_v_bdrive_0_sqmuxa_2_0_0: LUT4_L
generic map(
INIT => X"01FF"
)
port map (
I0 => N_668,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_REP1_INT_59,
I3 => SETBDRIVE,
LO => BDRIVE_0_SQMUXA_2_0_0);
II_r_d16muxc_0_1: LUT4
generic map(
INIT => X"000E"
)
port map (
I0 => N_SRO_ADDRESS_1_INT_37,
I1 => UN17_BUS16EN,
I2 => PRSTATE_0_INT_27,
I3 => PRSTATE_5_INT_32,
O => D16MUXC_0_1);
II_ctrl_v_bdrive_1_iv_0_1: LUT4
generic map(
INIT => X"BBBF"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SETBDRIVE,
I2 => SSRSTATE_0_INT_20,
I3 => SSRSTATE_1_INT_21,
O => BDRIVE_1_IV_0_1);
II_v_ssrstate_11HAKL0HAKR: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => D16MUXC_0_4_INT_73,
I1 => SSRSTATE_0_INT_20,
O => SSRSTATE_11(0));
II_v_bdrive_1_sqmuxa: LUT4
generic map(
INIT => X"CC4C"
)
port map (
I0 => SSRSTATE23_1,
I1 => SSRSTATE_3_INT_23,
I2 => WS_0_INT_16,
I3 => WS_3_INT_19,
O => BDRIVE_1_SQMUXA);
II_v_ssrhready_2_sqmuxa_m2: LUT4
generic map(
INIT => X"2A7F"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(1),
I3 => HSEL_INT_58,
O => CHANGE_1_SQMUXA_N_3_INT_63);
II_ctrl_hwrite_1_0: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_hwrite,
I2 => HWRITE,
O => HWRITE_1);
II_haddr_0HAKL3HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(3),
I2 => HADDR(3),
O => NN_1);
II_haddr_0HAKL4HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(4),
I2 => HADDR(4),
O => NN_2);
II_haddr_0HAKL5HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(5),
I2 => HADDR(5),
O => NN_3);
II_haddr_0HAKL6HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(6),
I2 => HADDR(6),
O => NN_4);
II_haddr_0HAKL7HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(7),
I2 => HADDR(7),
O => NN_5);
II_haddr_0HAKL8HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(8),
I2 => HADDR(8),
O => NN_6);
II_haddr_0HAKL9HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(9),
I2 => HADDR(9),
O => NN_7);
II_haddr_0HAKL10HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(10),
I2 => HADDR(10),
O => NN_8);
II_haddr_0HAKL11HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662_INT_60,
I1 => n_ahbsi_haddr(11),
I2 => HADDR(11),
O => NN_9);
II_ctrl_v_hsel_5_0: LUT4
generic map(
INIT => X"D580"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(1),
I3 => HSEL_INT_58,
O => HSEL_5_INT_67);
II_ctrl_v_ws_1_1_0HAKL2HAKR: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => IOWS(2),
I3 => ROMWWS(2),
O => N_363);
II_ctrl_v_ws_1_1_0HAKL1HAKR: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => IOWS(1),
I3 => ROMWWS(1),
O => N_362);
II_v_ws_3_sqmuxa_1_a0_2: LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => n_ahbsi_hsel(0),
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => SSRSTATE_1_INT_21,
O => WS_3_SQMUXA_1_A0_2);
II_r_d16muxc_2: LUT3
generic map(
INIT => X"02"
)
port map (
I0 => BUS16EN_INT_72,
I1 => WS_0_INT_16,
I2 => WS_3_INT_19,
O => D16MUXC_2);
II_r_d16muxc_1: LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => PRSTATE_3_INT_30,
I1 => SIZE_0_INT_25,
I2 => SIZE_1_INT_26,
I3 => WS_1_INT_17,
O => D16MUXC_1);
II_un1_v_ssrstate17_2_0_m6_i_a3_a0_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => HMBSEL_1_INT_34,
I1 => HSEL_INT_58,
O => SSRSTATE17_2_0_M6_I_A3_A0_1);
II_un1_v_ssrstate17_2_0_m6_i_a3_a2: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => n_ahbsi_hsel(0),
I3 => n_ahbsi_htrans(1),
O => ssrstate17_2_0_m6_i_a3_a2);
II_v_ws_1_sqmuxa: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => N_SRO_ROMSN_0_INT_12,
I1 => rst,
I2 => PRSTATE_4_INT_31,
O => WS_1_SQMUXA_INT_52);
II_ctrl_v_ssrstate10: LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => WS_0_INT_16,
I1 => WS_1_INT_17,
I2 => WS_2_INT_18,
I3 => WS_3_INT_19,
O => SSRSTATE10);
II_r_d16muxc_0_4: LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => WS_0_INT_16,
I1 => WS_1_INT_17,
I2 => WS_2_INT_18,
I3 => WS_3_INT_19,
O => D16MUXC_0_4_INT_73);
II_un1_r_ssrstate_3: LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => d_m2_0_a2_0,
I1 => SETBDRIVE,
I2 => SSRSTATE_3_INT_23,
O => SSRSTATE_3);
II_v_ws_0_sqmuxa_c: LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => SSRSTATE_1_INT_21,
O => WS_0_SQMUXA_C_INT_49);
II_un1_r_prstate_12_0: LUT3
generic map(
INIT => X"01"
)
port map (
I0 => PRSTATE_0_INT_27,
I1 => PRSTATE_1_INT_28,
I2 => PRSTATE_2_REP1_INT_59,
O => PRSTATE_12_0);
II_regsdHAKL8HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWIDTH(0),
O => n_apbo_prdata_8);
II_regsdHAKL9HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWIDTH(1),
O => n_apbo_prdata_9);
II_regsdHAKL11HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWRITE,
O => n_apbo_prdata_11);
II_regsdHAKL1HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS(1),
O => n_apbo_prdata_1);
II_regsdHAKL2HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS(2),
O => n_apbo_prdata_2);
II_regsdHAKL3HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS_3_INT_10,
O => n_apbo_prdata_3);
II_regsdHAKL5HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS(1),
O => n_apbo_prdata_5);
II_regsdHAKL6HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS(2),
O => n_apbo_prdata_6);
II_regsdHAKL7HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS_3_INT_8,
O => n_apbo_prdata_7);
II_regsdHAKL19HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOEN,
O => n_apbo_prdata_19);
II_regsdHAKL21HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS(1),
O => n_apbo_prdata_21);
II_regsdHAKL22HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS(2),
O => n_apbo_prdata_22);
II_regsdHAKL23HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS_3_INT_6,
O => n_apbo_prdata_23);
II_regsdHAKL20HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => IOWS_0_INT_5,
O => n_apbo_prdata_20);
II_regsdHAKL4HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMWWS_0_INT_7,
O => n_apbo_prdata_4);
II_regsdHAKL0HAKR: LUT3
generic map(
INIT => X"10"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
I2 => ROMRWS_0_INT_9,
O => n_apbo_prdata_0);
II_v_hmbsel_0_sqmuxa: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => n_ahbsi_hready,
I1 => hsel_4,
O => HMBSEL_0_SQMUXA);
II_v_data16_0_sqmuxa: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => BUS16EN_INT_72,
I1 => PRSTATE_4_INT_31,
O => DATA16_0_SQMUXA);
II_hrdata_0HAKL31HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(15),
I2 => HRDATA(31),
O => n_ahbso_hrdata(31));
II_hrdata_0HAKL30HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(14),
I2 => HRDATA(30),
O => n_ahbso_hrdata(30));
II_hrdata_0HAKL29HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(13),
I2 => HRDATA(29),
O => n_ahbso_hrdata(29));
II_hrdata_0HAKL28HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(12),
I2 => HRDATA(28),
O => n_ahbso_hrdata(28));
II_hrdata_0HAKL27HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(11),
I2 => HRDATA(27),
O => n_ahbso_hrdata(27));
II_hrdata_0HAKL26HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(10),
I2 => HRDATA(26),
O => n_ahbso_hrdata(26));
II_hrdata_0HAKL25HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(9),
I2 => HRDATA(25),
O => n_ahbso_hrdata(25));
II_hrdata_0HAKL24HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(8),
I2 => HRDATA(24),
O => n_ahbso_hrdata(24));
II_hrdata_0HAKL23HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(7),
I2 => HRDATA(23),
O => n_ahbso_hrdata(23));
II_hrdata_0HAKL22HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(6),
I2 => HRDATA(22),
O => n_ahbso_hrdata(22));
II_hrdata_0HAKL21HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(5),
I2 => HRDATA(21),
O => n_ahbso_hrdata(21));
II_hrdata_0HAKL20HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(4),
I2 => HRDATA(20),
O => n_ahbso_hrdata(20));
II_hrdata_0HAKL19HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(3),
I2 => HRDATA(19),
O => n_ahbso_hrdata(19));
II_hrdata_0HAKL18HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(2),
I2 => HRDATA(18),
O => n_ahbso_hrdata(18));
II_hrdata_0HAKL17HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(1),
I2 => HRDATA(17),
O => n_ahbso_hrdata(17));
II_hrdata_0HAKL16HAKR: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => D16MUX(0),
I1 => DATA16(0),
I2 => HRDATA(16),
O => n_ahbso_hrdata(16));
II_hrdata_0HAKL15HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(15),
I2 => HRDATA(31),
O => n_ahbso_hrdata(15));
II_hrdata_0HAKL14HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(14),
I2 => HRDATA(30),
O => n_ahbso_hrdata(14));
II_hrdata_0HAKL13HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(13),
I2 => HRDATA(29),
O => n_ahbso_hrdata(13));
II_hrdata_0HAKL12HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(12),
I2 => HRDATA(28),
O => n_ahbso_hrdata(12));
II_hrdata_0HAKL11HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(11),
I2 => HRDATA(27),
O => n_ahbso_hrdata(11));
II_hrdata_0HAKL10HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(10),
I2 => HRDATA(26),
O => n_ahbso_hrdata(10));
II_hrdata_0HAKL9HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(9),
I2 => HRDATA(25),
O => n_ahbso_hrdata(9));
II_hrdata_0HAKL8HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(8),
I2 => HRDATA(24),
O => n_ahbso_hrdata(8));
II_hrdata_0HAKL7HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(7),
I2 => HRDATA(23),
O => n_ahbso_hrdata(7));
II_hrdata_0HAKL6HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(6),
I2 => HRDATA(22),
O => n_ahbso_hrdata(6));
II_hrdata_0HAKL5HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(5),
I2 => HRDATA(21),
O => n_ahbso_hrdata(5));
II_hrdata_0HAKL4HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(4),
I2 => HRDATA(20),
O => n_ahbso_hrdata(4));
II_hrdata_0HAKL3HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(3),
I2 => HRDATA(19),
O => n_ahbso_hrdata(3));
II_hrdata_0HAKL2HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(2),
I2 => HRDATA(18),
O => n_ahbso_hrdata(2));
II_hrdata_0HAKL1HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(1),
I2 => HRDATA(17),
O => n_ahbso_hrdata(1));
II_hrdata_0HAKL0HAKR: LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => D16MUX(1),
I1 => HRDATA(0),
I2 => HRDATA(16),
O => n_ahbso_hrdata(0));
II_ctrl_v_bdrive_1_iv_0_a0_0: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => PRSTATE_1_INT_28,
I1 => SETBDRIVE,
O => BDRIVE_1_IV_0_A4_0);
II_ctrl_hwrite6: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => CHANGE_INT_69,
I1 => PRHREADY_INT_48,
O => N_662_INT_60);
II_ctrl_regsd24: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_apbi_paddr(2),
I1 => n_apbi_paddr(3),
O => N_APBO_PRDATA_28_INT_11);
II_ctrl_bus16en: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ROMWIDTH(0),
I1 => ROMWIDTH(1),
O => BUS16EN_INT_72);
II_ctrl_v_ssrstate23_1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WS_1_INT_17,
I1 => WS_2_INT_18,
O => SSRSTATE23_1);
II_ctrl_un1_ahbsi: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
O => UN1_AHBSI_INT_68);
II_un1_r_ssrstate_2: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_0_INT_20,
I1 => SSRSTATE_3_INT_23,
O => SSRSTATE_2_I_INT_55);
II_ctrl_un17_bus16en: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => SIZE_0_INT_25,
I1 => SIZE_1_INT_26,
O => UN17_BUS16EN);
II_un1_r_ssrstate_1: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => SSRSTATE_2_INT_22,
I1 => SSRSTATE_4_INT_24,
O => N_668);
II_r_haddrHAKL1HAKR: FDSE port map (
Q => N_SRO_ADDRESS_1_INT_37,
D => n_ahbsi_haddr(1),
C => clk,
S => PRHREADY_0_SQMUXA,
CE => HMBSEL_0_SQMUXA);
II_r_prstateHAKL5HAKR: FDS port map (
Q => PRSTATE_5_INT_32,
D => PRSTATES_I,
C => clk,
S => RST_I);
II_r_prstateHAKL4HAKR: FDS port map (
Q => PRSTATE_4_INT_31,
D => N_342,
C => clk,
S => N_341);
II_r_prstateHAKL3HAKR: FDR port map (
Q => PRSTATE_3_INT_30,
D => PRSTATEC,
C => clk,
R => RST_I);
II_r_prstateHAKL2HAKR: FDR port map (
Q => PRSTATE_2_INT_29,
D => PRSTATEC_0,
C => clk,
R => RST_I);
II_r_prstateHAKL1HAKR: FDR port map (
Q => PRSTATE_1_INT_28,
D => N_337_I,
C => clk,
R => RST_I);
II_r_prstateHAKL0HAKR: FDR port map (
Q => PRSTATE_0_INT_27,
D => PRSTATEC_1,
C => clk,
R => RST_I);
II_r_ssrstateHAKL1HAKR: FDR port map (
Q => SSRSTATE_1_INT_21,
D => ssrstatec,
C => clk,
R => RST_I);
II_r_ssrstateHAKL0HAKR: FDR port map (
Q => SSRSTATE_0_INT_20,
D => SSRSTATEC_0,
C => clk,
R => RST_I);
II_rbdriveHAKL28HAKR: FDR port map (
Q => n_sro_vbdrive(28),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL29HAKR: FDR port map (
Q => n_sro_vbdrive(29),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL30HAKR: FDR port map (
Q => n_sro_vbdrive(30),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL31HAKR: FDR port map (
Q => n_sro_vbdrive(31),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL13HAKR: FDR port map (
Q => n_sro_vbdrive(13),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL14HAKR: FDR port map (
Q => n_sro_vbdrive(14),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL15HAKR: FDR port map (
Q => n_sro_vbdrive(15),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL16HAKR: FDR port map (
Q => n_sro_vbdrive(16),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL17HAKR: FDR port map (
Q => n_sro_vbdrive(17),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL18HAKR: FDR port map (
Q => n_sro_vbdrive(18),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL19HAKR: FDR port map (
Q => n_sro_vbdrive(19),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL20HAKR: FDR port map (
Q => n_sro_vbdrive(20),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL21HAKR: FDR port map (
Q => n_sro_vbdrive(21),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL22HAKR: FDR port map (
Q => n_sro_vbdrive(22),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL23HAKR: FDR port map (
Q => n_sro_vbdrive(23),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL24HAKR: FDR port map (
Q => n_sro_vbdrive(24),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL25HAKR: FDR port map (
Q => n_sro_vbdrive(25),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL26HAKR: FDR port map (
Q => n_sro_vbdrive(26),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL27HAKR: FDR port map (
Q => n_sro_vbdrive(27),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL0HAKR: FDR port map (
Q => n_sro_vbdrive(0),
D => RBDRIVEC_18,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL1HAKR: FDR port map (
Q => n_sro_vbdrive(1),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL2HAKR: FDR port map (
Q => n_sro_vbdrive(2),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL3HAKR: FDR port map (
Q => n_sro_vbdrive(3),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL4HAKR: FDR port map (
Q => n_sro_vbdrive(4),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL5HAKR: FDR port map (
Q => n_sro_vbdrive(5),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL6HAKR: FDR port map (
Q => n_sro_vbdrive(6),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL7HAKR: FDR port map (
Q => n_sro_vbdrive(7),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL8HAKR: FDR port map (
Q => n_sro_vbdrive(8),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL9HAKR: FDR port map (
Q => n_sro_vbdrive(9),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL10HAKR: FDR port map (
Q => n_sro_vbdrive(10),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL11HAKR: FDR port map (
Q => n_sro_vbdrive(11),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_rbdriveHAKL12HAKR: FDR port map (
Q => n_sro_vbdrive(12),
D => RBDRIVEC,
C => clk,
R => BDRIVE_1_IV_0_A1);
II_r_d16muxHAKL0HAKR: FDR port map (
Q => D16MUX(0),
D => D16MUXC,
C => clk,
R => WS_2_INT_18);
II_r_d16muxHAKL1HAKR: FDR port map (
Q => D16MUX(1),
D => D16MUXC_0,
C => clk,
R => PRSTATE_2_INT_29);
II_r_acount_sHAKL9HAKR: XORCY port map (
LI => ACOUNT_QXU(9),
CI => ACOUNT_CRY(8),
O => ACOUNT_S(9));
II_r_acount_sHAKL8HAKR: XORCY port map (
LI => ACOUNT_QXU(8),
CI => ACOUNT_CRY(7),
O => ACOUNT_S(8));
II_r_acount_cryHAKL8HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(7),
S => ACOUNT_QXU(8),
LO => ACOUNT_CRY(8));
II_r_acount_sHAKL7HAKR: XORCY port map (
LI => ACOUNT_QXU(7),
CI => ACOUNT_CRY(6),
O => ACOUNT_S(7));
II_r_acount_cryHAKL7HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(6),
S => ACOUNT_QXU(7),
LO => ACOUNT_CRY(7));
II_r_acount_sHAKL6HAKR: XORCY port map (
LI => ACOUNT_QXU(6),
CI => ACOUNT_CRY(5),
O => ACOUNT_S(6));
II_r_acount_cryHAKL6HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(5),
S => ACOUNT_QXU(6),
LO => ACOUNT_CRY(6));
II_r_acount_sHAKL5HAKR: XORCY port map (
LI => ACOUNT_QXU(5),
CI => ACOUNT_CRY(4),
O => ACOUNT_S(5));
II_r_acount_cryHAKL5HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(4),
S => ACOUNT_QXU(5),
LO => ACOUNT_CRY(5));
II_r_acount_sHAKL4HAKR: XORCY port map (
LI => ACOUNT_QXU(4),
CI => ACOUNT_CRY(3),
O => ACOUNT_S(4));
II_r_acount_cryHAKL4HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(3),
S => ACOUNT_QXU(4),
LO => ACOUNT_CRY(4));
II_r_acount_sHAKL3HAKR: XORCY port map (
LI => ACOUNT_QXU(3),
CI => ACOUNT_CRY(2),
O => ACOUNT_S(3));
II_r_acount_cryHAKL3HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(2),
S => ACOUNT_QXU(3),
LO => ACOUNT_CRY(3));
II_r_acount_sHAKL2HAKR: XORCY port map (
LI => ACOUNT_QXU(2),
CI => ACOUNT_CRY(1),
O => ACOUNT_S(2));
II_r_acount_cryHAKL2HAKR: MUXCY_L port map (
DI => NN_10,
CI => ACOUNT_CRY(1),
S => ACOUNT_QXU(2),
LO => ACOUNT_CRY(2));
II_r_acount_sHAKL1HAKR: XORCY port map (
LI => ACOUNT_QXU(1),
CI => N_SRO_ADDRESS_2_INT_38,
O => ACOUNT_S(1));
II_r_acount_cryHAKL1HAKR: MUXCY_L port map (
DI => NN_10,
CI => N_SRO_ADDRESS_2_INT_38,
S => ACOUNT_QXU(1),
LO => ACOUNT_CRY(1));
II_r_hsel: FDRE port map (
Q => HSEL_INT_58,
D => hsel_4,
C => clk,
R => RST_I,
CE => n_ahbsi_hready);
II_r_mcfg1_ioen: FDRE port map (
Q => IOEN,
D => IOEN_1,
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwrite: FDRE port map (
Q => ROMWRITE,
D => ROMWRITE_1,
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL3HAKR: FDRE port map (
Q => IOWS_3_INT_6,
D => IOWS_1(3),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL2HAKR: FDRE port map (
Q => IOWS(2),
D => IOWS_1(2),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL1HAKR: FDRE port map (
Q => IOWS(1),
D => IOWS_1(1),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_iowsHAKL0HAKR: FDRE port map (
Q => IOWS_0_INT_5,
D => IOWS_1(0),
C => clk,
R => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL3HAKR: FDSE port map (
Q => ROMRWS_3_INT_10,
D => N_627_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL2HAKR: FDSE port map (
Q => ROMRWS(2),
D => N_628_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL1HAKR: FDSE port map (
Q => ROMRWS(1),
D => N_629_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romrwsHAKL0HAKR: FDSE port map (
Q => ROMRWS_0_INT_9,
D => N_630_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL3HAKR: FDSE port map (
Q => ROMWWS_3_INT_8,
D => N_623_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL2HAKR: FDSE port map (
Q => ROMWWS(2),
D => N_624_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL1HAKR: FDSE port map (
Q => ROMWWS(1),
D => N_625_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_mcfg1_romwwsHAKL0HAKR: FDSE port map (
Q => ROMWWS_0_INT_7,
D => N_626_I,
C => clk,
S => RST_I,
CE => BEXCEN_1_SQMUXA_I);
II_r_writen: FDSE port map (
Q => n_sro_writen,
D => N_635_I,
C => clk,
S => RST_I,
CE => WRITEN_2_SQMUXA);
II_r_loadcount: FDS port map (
Q => loadcount,
D => loadcount_7,
C => clk,
S => RST_I);
II_r_setbdrive: FDRE port map (
Q => SETBDRIVE,
D => SSRSTATE_1_INT_21,
C => clk,
R => RST_I,
CE => SSRSTATE_3);
II_r_ssrhready: FDS port map (
Q => SSRHREADY_INT_51,
D => ssrhready_8,
C => clk,
S => RST_I);
II_r_prhready: FDS port map (
Q => PRHREADY_INT_48,
D => PRHREADY_6,
C => clk,
S => RST_I);
II_r_romsn: FDSE port map (
Q => N_SRO_ROMSN_0_INT_12,
D => ROMSN_1,
C => clk,
S => RST_I,
CE => N_599_I);
II_r_hready: FDS port map (
Q => n_ahbso_hready,
D => hready_2,
C => clk,
S => RST_I);
II_GND: GND port map (
G => NN_10);
II_VCC: VCC port map (
P => NN_11);
iows_0 <= IOWS_0_INT_5;
iows_3 <= IOWS_3_INT_6;
romwws_0 <= ROMWWS_0_INT_7;
romwws_3 <= ROMWWS_3_INT_8;
romrws_0 <= ROMRWS_0_INT_9;
romrws_3 <= ROMRWS_3_INT_10;
n_apbo_prdata_28 <= N_APBO_PRDATA_28_INT_11;
n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_12;
prstate_fast(2) <= PRSTATE_FAST_2_INT_13;
hmbsel_4(1) <= HMBSEL_4_1_INT_14;
n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_15;
ws(0) <= WS_0_INT_16;
ws(1) <= WS_1_INT_17;
ws(2) <= WS_2_INT_18;
ws(3) <= WS_3_INT_19;
ssrstate(0) <= SSRSTATE_0_INT_20;
ssrstate(1) <= SSRSTATE_1_INT_21;
ssrstate(2) <= SSRSTATE_2_INT_22;
ssrstate(3) <= SSRSTATE_3_INT_23;
ssrstate(4) <= SSRSTATE_4_INT_24;
size(0) <= SIZE_0_INT_25;
size(1) <= SIZE_1_INT_26;
prstate(0) <= PRSTATE_0_INT_27;
prstate(1) <= PRSTATE_1_INT_28;
prstate(2) <= PRSTATE_2_INT_29;
prstate(3) <= PRSTATE_3_INT_30;
prstate(4) <= PRSTATE_4_INT_31;
prstate(5) <= PRSTATE_5_INT_32;
hmbsel(0) <= HMBSEL_0_INT_33;
hmbsel(1) <= HMBSEL_1_INT_34;
hmbsel(2) <= HMBSEL_2_INT_35;
n_sro_address(0) <= N_SRO_ADDRESS_0_INT_36;
n_sro_address(1) <= N_SRO_ADDRESS_1_INT_37;
n_sro_address(2) <= N_SRO_ADDRESS_2_INT_38;
n_sro_address(3) <= N_SRO_ADDRESS_3_INT_39;
n_sro_address(4) <= N_SRO_ADDRESS_4_INT_40;
n_sro_address(5) <= N_SRO_ADDRESS_5_INT_41;
n_sro_address(6) <= N_SRO_ADDRESS_6_INT_42;
n_sro_address(7) <= N_SRO_ADDRESS_7_INT_43;
n_sro_address(8) <= N_SRO_ADDRESS_8_INT_44;
n_sro_address(9) <= N_SRO_ADDRESS_9_INT_45;
n_sro_address(10) <= N_SRO_ADDRESS_10_INT_46;
n_sro_address(11) <= N_SRO_ADDRESS_11_INT_47;
prhready <= PRHREADY_INT_48;
ws_0_sqmuxa_c <= WS_0_SQMUXA_C_INT_49;
ws_0_sqmuxa_0_c <= WS_0_SQMUXA_0_C_INT_50;
ssrhready <= SSRHREADY_INT_51;
ws_1_sqmuxa <= WS_1_SQMUXA_INT_52;
ws_3_sqmuxa_1 <= WS_3_SQMUXA_1_INT_53;
ws_2_sqmuxa_3_0_2 <= WS_2_SQMUXA_3_0_2_INT_54;
ssrstate_2_i <= SSRSTATE_2_I_INT_55;
ws_2_sqmuxa_3_d <= WS_2_SQMUXA_3_D_INT_56;
ws_0_sqmuxa_1 <= WS_0_SQMUXA_1_INT_57;
hsel <= HSEL_INT_58;
prstate_2_rep1 <= PRSTATE_2_REP1_INT_59;
N_662 <= N_662_INT_60;
ssrstate_6_sqmuxa <= SSRSTATE_6_SQMUXA_INT_61;
ssrhready_2_sqmuxa_0_0 <= SSRHREADY_2_SQMUXA_0_0_INT_62;
change_1_sqmuxa_N_3 <= CHANGE_1_SQMUXA_N_3_INT_63;
ssrstate6_xx_mm_m3 <= SSRSTATE6_XX_MM_M3_INT_64;
ssrstate6_1_d_0_L1 <= SSRSTATE6_1_D_0_L1_INT_65;
N_656 <= N_656_INT_66;
hsel_5 <= HSEL_5_INT_67;
un1_ahbsi <= UN1_AHBSI_INT_68;
change <= CHANGE_INT_69;
n_sro_iosn <= N_SRO_IOSN_INT_70;
N_371 <= N_371_INT_71;
bus16en <= BUS16EN_INT_72;
d16muxc_0_4 <= D16MUXC_0_4_INT_73;
end beh;
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture beh of ssrctrl_unisim is
signal WRP_R_HMBSEL : std_logic_vector (2 downto 0);
signal WRP_R_WS : std_logic_vector (3 downto 0);
signal WRP_R_SIZE : std_logic_vector (1 downto 0);
signal WRP_R_PRSTATE : std_logic_vector (5 downto 0);
signal WRP_R_SSRSTATE : std_logic_vector (4 downto 0);
signal WRP_R_MCFG1_ROMRWS : std_logic_vector (3 downto 0);
signal WRP_R_MCFG1_ROMWWS : std_logic_vector (3 downto 0);
signal WRP_R_MCFG1_IOWS : std_logic_vector (3 downto 0);
signal WRP_CTRL_V_SSRSTATE_1 : std_logic_vector (4 to 4);
signal WRP_CTRL_V_SSRSTATE_1_M1 : std_logic_vector (4 downto 3);
signal WRP_CTRL_V_WS_1 : std_logic_vector (3 downto 0);
signal WRP_CTRL_V_HMBSEL_4 : std_logic_vector (1 to 1);
signal WRP_NONAME_CNST : std_logic_vector (0 to 0);
signal WRP_CTRL_HSIZE_1 : std_logic_vector (1 to 1);
signal WRP_HADDR : std_logic_vector (1 to 1);
signal WRP_UN1_V_HSEL_1 : std_logic_vector (0 to 0);
signal WRP_CTRL_V_BWN_1_0_O3 : std_logic_vector (0 to 0);
signal WRP_V_PRSTATE_1_I_O4_S : std_logic_vector (2 to 2);
signal WRP_R_PRSTATE_FAST : std_logic_vector (2 to 2);
signal N_SRO_ADDRESS_0_INT_172 : std_logic ;
signal N_SRO_ADDRESS_1_INT_173 : std_logic ;
signal N_SRO_IOSN_INT_259 : std_logic ;
signal N_SRO_ROMSN_0_INT_260 : std_logic ;
signal WRP_R_PRHREADY : std_logic ;
signal WRP_R_CHANGE : std_logic ;
signal WRP_CTRL_V_HSEL_5 : std_logic ;
signal WRP_R_HSEL : std_logic ;
signal WRP_CTRL_V_LOADCOUNT_7 : std_logic ;
signal WRP_R_LOADCOUNT : std_logic ;
signal WRP_CTRL_V_SSRHREADY_8 : std_logic ;
signal WRP_R_SSRHREADY : std_logic ;
signal WRP_CTRL_V_HREADY_2 : std_logic ;
signal N_574_I : std_logic ;
signal WRP_CTRL_BUS16EN : std_logic ;
signal WRP_CTRL_V_HSEL_4 : std_logic ;
signal WRP_CTRL_UN7_BUS16EN : std_logic ;
signal WRP_V_D16MUX_0_SQMUXA : std_logic ;
signal N_593 : std_logic ;
signal N_597 : std_logic ;
signal N_596 : std_logic ;
signal WRP_V_SSRSTATE_2_SQMUXA_1 : std_logic ;
signal WRP_V_SSRSTATE_6_SQMUXA : std_logic ;
signal WRP_V_SSRSTATE_1_SQMUXA_1 : std_logic ;
signal WRP_UN1_R_SSRSTATE_2_I : std_logic ;
signal WRP_V_WS_0_SQMUXA_1 : std_logic ;
signal WRP_V_BWN_0_SQMUXA_1 : std_logic ;
signal WRP_V_WS_1_SQMUXA : std_logic ;
signal N_646 : std_logic ;
signal WRP_V_WS_3_SQMUXA_1 : std_logic ;
signal N_662 : std_logic ;
signal WRP_V_LOADCOUNT_1_SQMUXA : std_logic ;
signal N_319_1 : std_logic ;
signal WRP_CTRL_UN1_AHBSI : std_logic ;
signal N_622 : std_logic ;
signal WRP_UN1_V_SSRSTATE_2_SQMUXA_I : std_logic ;
signal N_365 : std_logic ;
signal N_371 : std_logic ;
signal N_656 : std_logic ;
signal WRP_UN1_V_CHANGE_1_SQMUXA_0 : std_logic ;
signal G0_25 : std_logic ;
signal WRP_CTRL_V_CHANGE_3_F0 : std_logic ;
signal WRP_UN1_V_BWN_1_SQMUXA_2_D : std_logic ;
signal WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4 : std_logic ;
signal SSRSTATE17_2_0_M6_I_A3_A2 : std_logic ;
signal SSRSTATE6_XX_MM_M3 : std_logic ;
signal WRP_V_CHANGE_1_SQMUXA_N_3 : std_logic ;
signal WRP_CTRL_V_CHANGE_3_F1_D_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_D : std_logic ;
signal WRP_V_WS_0_SQMUXA_C : std_logic ;
signal WRP_V_WS_0_SQMUXA_0_C : std_logic ;
signal G0_30 : std_logic ;
signal D_M2_0_A2_0 : std_logic ;
signal N_618_I : std_logic ;
signal WRP_R_SSRSTATEC : std_logic ;
signal WRP_R_D16MUXC_0_4 : std_logic ;
signal WRP_V_WS_4_SQMUXA_0 : std_logic ;
signal D_M1_E_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_0 : std_logic ;
signal WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0 : std_logic ;
signal WRP_UN1_V_SSRSTATE17_2_0_M6_I_1 : std_logic ;
signal WRP_V_SSRHREADY_2_SQMUXA_0_0 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_0_2 : std_logic ;
signal WRP_V_WS_2_SQMUXA_3_0_4 : std_logic ;
signal WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2 : std_logic ;
signal WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1 : std_logic ;
signal SSRSTATE6_1_D_0_L1 : std_logic ;
signal HSEL_1_0_L3 : std_logic ;
signal SSRHREADY_8_F0_L5 : std_logic ;
signal SSRHREADY_8_F0_L8 : std_logic ;
signal G0_I : std_logic ;
signal N_5 : std_logic ;
signal G0_23 : std_logic ;
signal N_14 : std_logic ;
signal N_19 : std_logic ;
signal G0_34 : std_logic ;
signal G0_29 : std_logic ;
signal G0_28 : std_logic ;
signal G0_31 : std_logic ;
signal G2_1_0 : std_logic ;
signal G0_44 : std_logic ;
signal G0_I_M2_1 : std_logic ;
signal G0_14 : std_logic ;
signal G0_7_0 : std_logic ;
signal G0_1_0 : std_logic ;
signal G3 : std_logic ;
signal N_4 : std_logic ;
signal N_17 : std_logic ;
signal G0_5_0 : std_logic ;
signal G0_11 : std_logic ;
signal G0_I_A3_0 : std_logic ;
signal G0_51 : std_logic ;
signal G0_8_1 : std_logic ;
signal G0_56 : std_logic ;
signal G0_I_M2_2 : std_logic ;
signal N_9 : std_logic ;
signal G0_8 : std_logic ;
signal G0_I_M2_L1 : std_logic ;
signal G0_54_L1 : std_logic ;
signal G0_57_1 : std_logic ;
signal G0_34_L1_0 : std_logic ;
signal G0_34_L6 : std_logic ;
signal G0_34_L10 : std_logic ;
signal G0_55_L1 : std_logic ;
signal G0_55_L5 : std_logic ;
signal G0_55_L7 : std_logic ;
signal G0_19_L1 : std_logic ;
signal G0_52_X0 : std_logic ;
signal G0_52_X1 : std_logic ;
signal G0_50_X : std_logic ;
signal WS_2_SQMUXA_3_0_X : std_logic ;
signal D_M1_E_L1 : std_logic ;
signal G0_57_1_L5 : std_logic ;
signal G0_57_1_L7 : std_logic ;
signal G0_55_L5_L1 : std_logic ;
signal G0_55_L7_L1 : std_logic ;
signal G0_36_L1 : std_logic ;
signal G0_48_L1 : std_logic ;
signal G0_34_L10_L1 : std_logic ;
signal G0_34_L10_L3 : std_logic ;
signal G0_57_1_L7_L4 : std_logic ;
signal G0_57_1_L7_L6 : std_logic ;
signal G0_57_1_L7_L8 : std_logic ;
signal WRP_R_PRSTATE_2_REP1 : std_logic ;
signal D_M1_E_L1_0 : std_logic ;
signal D_M1_E_L3 : std_logic ;
signal G0_I_M2_0_L1 : std_logic ;
signal G0_I_M2_0_L3 : std_logic ;
signal G0_I_M2_0_L5 : std_logic ;
signal G3_1 : std_logic ;
signal G0_0_L1 : std_logic ;
signal G0_0_L3 : std_logic ;
signal G0_0_L5 : std_logic ;
signal G0_0_L7 : std_logic ;
signal G0_0_L9 : std_logic ;
signal G0_57_1_L7_L6_RN_0 : std_logic ;
signal G0_57_1_L7_L6_SN : std_logic ;
signal G0_55_L7_L1_RN_0 : std_logic ;
signal G0_55_L7_L1_SN : std_logic ;
signal G0_52X : std_logic ;
signal G0_52X_0 : std_logic ;
signal G2_0_1 : std_logic ;
signal G0_46_L1 : std_logic ;
signal G0_46_L3 : std_logic ;
signal G0_46_L5 : std_logic ;
signal G0_46_L7 : std_logic ;
signal NN_1 : std_logic ;
signal N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268 : std_logic ;
signal N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272 : std_logic ;
signal NN_2 : std_logic ;
component ssrctrl_unisim_netlist
port(
n_sro_vbdrive : out std_logic_vector(31 downto 0);
n_ahbso_hrdata : out std_logic_vector(31 downto 0);
iows_0 : out std_logic;
iows_3 : out std_logic;
romwws_0 : out std_logic;
romwws_3 : out std_logic;
romrws_0 : out std_logic;
romrws_3 : out std_logic;
NoName_cnst : in std_logic_vector(0 downto 0);
n_sri_bwidth : in std_logic_vector(1 downto 0);
n_apbi_pwdata_19 : in std_logic;
n_apbi_pwdata_11 : in std_logic;
n_apbi_pwdata_9 : in std_logic;
n_apbi_pwdata_8 : in std_logic;
n_apbi_pwdata_23 : in std_logic;
n_apbi_pwdata_22 : in std_logic;
n_apbi_pwdata_21 : in std_logic;
n_apbi_pwdata_20 : in std_logic;
n_apbi_pwdata_3 : in std_logic;
n_apbi_pwdata_2 : in std_logic;
n_apbi_pwdata_1 : in std_logic;
n_apbi_pwdata_0 : in std_logic;
n_apbi_pwdata_7 : in std_logic;
n_apbi_pwdata_6 : in std_logic;
n_apbi_pwdata_5 : in std_logic;
n_apbi_pwdata_4 : in std_logic;
n_apbi_psel : in std_logic_vector(0 downto 0);
n_apbi_paddr : in std_logic_vector(5 downto 2);
n_apbo_prdata_0 : out std_logic;
n_apbo_prdata_4 : out std_logic;
n_apbo_prdata_20 : out std_logic;
n_apbo_prdata_23 : out std_logic;
n_apbo_prdata_22 : out std_logic;
n_apbo_prdata_21 : out std_logic;
n_apbo_prdata_19 : out std_logic;
n_apbo_prdata_7 : out std_logic;
n_apbo_prdata_6 : out std_logic;
n_apbo_prdata_5 : out std_logic;
n_apbo_prdata_3 : out std_logic;
n_apbo_prdata_2 : out std_logic;
n_apbo_prdata_1 : out std_logic;
n_apbo_prdata_11 : out std_logic;
n_apbo_prdata_9 : out std_logic;
n_apbo_prdata_8 : out std_logic;
n_apbo_prdata_28 : out std_logic;
n_sro_romsn : out std_logic_vector(0 downto 0);
n_ahbsi_hsel : in std_logic_vector(0 downto 0);
prstate_fast : out std_logic_vector(2 downto 2);
n_ahbsi_htrans : in std_logic_vector(1 downto 0);
ssrstate_1_m1 : inout std_logic_vector(4 downto 3);
hsel_1 : in std_logic_vector(0 downto 0);
hmbsel_4 : out std_logic_vector(1 downto 1);
n_sro_bdrive : out std_logic_vector(3 downto 3);
ws_1_0 : in std_logic;
ws_1_3 : in std_logic;
ws : out std_logic_vector(3 downto 0);
ssrstate_1_2 : in std_logic;
n_ahbsi_haddr : in std_logic_vector(31 downto 0);
n_ahbsi_hmbsel : in std_logic_vector(2 downto 0);
n_sri_data : in std_logic_vector(31 downto 0);
ssrstate : out std_logic_vector(4 downto 0);
n_ahbsi_hwdata : in std_logic_vector(31 downto 0);
n_ahbsi_hsize : in std_logic_vector(1 downto 0);
size : out std_logic_vector(1 downto 0);
n_sro_data : out std_logic_vector(31 downto 0);
n_sro_ramsn : out std_logic_vector(0 downto 0);
n_sro_wrn : out std_logic_vector(3 downto 0);
haddr_0 : in std_logic;
bwn_1_0_o3_0 : in std_logic;
hsize_1 : in std_logic_vector(1 downto 1);
prstate_1_i_o4_s : in std_logic_vector(2 downto 2);
prstate : out std_logic_vector(5 downto 0);
hmbsel : out std_logic_vector(2 downto 0);
n_sro_address : out std_logic_vector(31 downto 0);
hready_2 : in std_logic;
n_ahbso_hready : out std_logic;
ssrhready_8 : in std_logic;
loadcount : out std_logic;
n_sro_writen : out std_logic;
ssrstatec : in std_logic;
prhready : out std_logic;
d_m2_0_a2_0 : in std_logic;
ssrstate17_2_0_m6_i_a3_a2 : out std_logic;
N_319_1 : out std_logic;
ws_0_sqmuxa_c : out std_logic;
N_365 : in std_logic;
ws_0_sqmuxa_0_c : out std_logic;
ws_2_sqmuxa_3_0_4 : out std_logic;
change_1_sqmuxa_0 : in std_logic;
d16mux_0_sqmuxa : in std_logic;
ssrstate_2_sqmuxa_1 : in std_logic;
un7_bus16en : in std_logic;
N_646 : in std_logic;
loadcount_1_sqmuxa : in std_logic;
ssrstate_1_sqmuxa_1_0_m3_0_1 : out std_logic;
n_apbi_penable : in std_logic;
n_apbi_pwrite : in std_logic;
d_m1_e_0_0 : in std_logic;
hsel_1_0_L3 : out std_logic;
ssrhready_8_f0_L8 : out std_logic;
ssrstate_1_sqmuxa_1 : in std_logic;
ssrhready : out std_logic;
ssrhready_8_f0_L5 : out std_logic;
ssrstate17_1_xx_mm_N_4 : in std_logic;
ws_1_sqmuxa : out std_logic;
ws_4_sqmuxa_0 : in std_logic;
ws_2_sqmuxa_0 : in std_logic;
ssrstate17_2_0_m6_i_1 : out std_logic;
ws_2_sqmuxa_3_0_x : out std_logic;
ws_3_sqmuxa_1 : out std_logic;
ws_2_sqmuxa_3_0_2 : out std_logic;
ssrstate_2_i : out std_logic;
ws_2_sqmuxa_3_d : out std_logic;
ws_0_sqmuxa_1 : out std_logic;
g0_30 : in std_logic;
hsel_4 : in std_logic;
n_ahbsi_hready : in std_logic;
hsel : out std_logic;
g0_25 : in std_logic;
bwn_0_sqmuxa_1 : in std_logic;
prstate_2_rep1 : out std_logic;
N_662 : out std_logic;
ssrstate_6_sqmuxa : out std_logic;
g0_52_x1 : in std_logic;
g0_52_x0 : in std_logic;
ssrhready_2_sqmuxa_0_0 : out std_logic;
change_1_sqmuxa_N_3 : out std_logic;
ssrstate6_xx_mm_m3 : out std_logic;
ssrstate6_1_d_0_L1 : out std_logic;
N_656 : out std_logic;
hsel_5 : out std_logic;
change_3_f0 : in std_logic;
un1_ahbsi : out std_logic;
change : out std_logic;
n_ahbsi_hwrite : in std_logic;
N_574_i : in std_logic;
n_sro_iosn : out std_logic;
N_618_i : in std_logic;
clk : in std_logic;
n_sro_oen : out std_logic;
rst : in std_logic;
bwn_1_sqmuxa_2_d : in std_logic;
bwn_1_sqmuxa_2_d_0_2 : in std_logic;
ssrstate_2_sqmuxa_i : in std_logic;
g0_23 : in std_logic;
N_371 : out std_logic;
loadcount_7 : in std_logic;
bus16en : out std_logic;
d16muxc_0_4 : out std_logic;
change_3_f1_d_0_0 : in std_logic;
g0_1_0 : in std_logic;
g0_44 : in std_logic );
end component;
begin
II_g0_46: LUT4_L
generic map(
INIT => X"B000"
)
port map (
I0 => N_4,
I1 => N_17,
I2 => G0_46_L7,
I3 => G3,
LO => WRP_CTRL_V_HREADY_2);
II_g0_45: LUT4_L
generic map(
INIT => X"0B00"
)
port map (
I0 => N_4,
I1 => N_17,
I2 => SSRHREADY_8_F0_L8,
I3 => G3,
LO => WRP_CTRL_V_SSRHREADY_8);
II_g0_35: LUT4_L
generic map(
INIT => X"00B1"
)
port map (
I0 => N_622,
I1 => G0_34,
I2 => G0_29,
I3 => WRP_V_SSRSTATE_2_SQMUXA_1,
LO => WRP_R_SSRSTATEC);
II_g0_57: LUT4_L
generic map(
INIT => X"FA44"
)
port map (
I0 => N_371,
I1 => G0_56,
I2 => G0_I_M2_2,
I3 => G0_57_1,
LO => WRP_CTRL_V_WS_1(0));
II_g0_i_m2_0: LUT4_L
generic map(
INIT => X"B1E4"
)
port map (
I0 => N_5,
I1 => G0_I_M2_0_L3,
I2 => G0_I_M2_0_L5,
I3 => WRP_R_WS(3),
LO => WRP_CTRL_V_WS_1(3));
II_g0_i_m2: LUT4_L
generic map(
INIT => X"D8CC"
)
port map (
I0 => N_622,
I1 => G0_I_M2_L1,
I2 => WRP_CTRL_V_SSRSTATE_1_M1(4),
I3 => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
LO => WRP_CTRL_V_SSRSTATE_1(4));
II_g0_5: LUT4_L
generic map(
INIT => X"37FF"
)
port map (
I0 => WRP_CTRL_HSIZE_1(1),
I1 => WRP_CTRL_V_BWN_1_0_O3(0),
I2 => WRP_HADDR(1),
I3 => WRP_UN1_V_BWN_1_SQMUXA_2_D,
LO => N_618_I);
II_g0_46_L1: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_R_SSRHREADY,
I2 => WRP_R_SSRSTATE(3),
O => G0_46_L1);
II_g0_46_L3: LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_CHANGE,
O => G0_46_L3);
II_g0_46_L5: LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => G0_44,
I1 => G0_46_L1,
I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_46_L5);
II_g0_46_L7: LUT4_L
generic map(
INIT => X"1033"
)
port map (
I0 => G0_46_L3,
I1 => G0_46_L5,
I2 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
I3 => WRP_V_PRSTATE_1_I_O4_S(2),
LO => G0_46_L7);
II_g2_0: LUT4
generic map(
INIT => X"E0EA"
)
port map (
I0 => SSRHREADY_8_F0_L5,
I1 => G2_0_1,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(2),
O => N_4);
II_g2_0_1: LUT3
generic map(
INIT => X"20"
)
port map (
I0 => G0_48_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HSEL_5,
O => G2_0_1);
II_g0_52_x1x: LUT4
generic map(
INIT => X"35F5"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_hsel(0),
O => G0_52X_0);
II_g0_52_x0x: LUT2
generic map(
INIT => X"D"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hready,
O => G0_52X);
II_g0_55_L7_L1: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => G0_55_L7_L1_RN_0,
I1 => G0_55_L7_L1_SN,
I2 => n_ahbsi_htrans(1),
O => G0_55_L7_L1);
II_g0_55_L7_L1_sn: LUT4
generic map(
INIT => X"8D88"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => WRP_R_HSEL,
O => G0_55_L7_L1_SN);
II_g0_55_L7_L1_rn: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HSEL,
O => G0_55_L7_L1_RN_0);
II_g0_57_1_L7_L6: LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => G0_57_1_L7_L6_RN_0,
I1 => G0_57_1_L7_L6_SN,
I2 => n_ahbsi_htrans(1),
O => G0_57_1_L7_L6);
II_g0_57_1_L7_L6_sn: LUT4
generic map(
INIT => X"8D88"
)
port map (
I0 => n_ahbsi_hready,
I1 => n_ahbsi_hsel(0),
I2 => n_ahbsi_htrans(0),
I3 => WRP_R_HSEL,
O => G0_57_1_L7_L6_SN);
II_g0_57_1_L7_L6_rn: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HSEL,
O => G0_57_1_L7_L6_RN_0);
II_g0_0_L1: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rst,
I1 => WRP_R_PRSTATE_2_REP1,
O => G0_0_L1);
II_g0_0_L3: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => G0_0_L3);
II_g0_0_L5: LUT4
generic map(
INIT => X"55DF"
)
port map (
I0 => G0_0_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HSEL_5,
I3 => WRP_R_D16MUXC_0_4,
O => G0_0_L5);
II_g0_0_L7: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
O => G0_0_L7);
II_g0_0_L9: LUT4
generic map(
INIT => X"7F33"
)
port map (
I0 => G0_0_L3,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => SSRSTATE6_XX_MM_M3,
O => G0_0_L9);
II_g0_0: LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => G0_0_L5,
I1 => G0_0_L7,
I2 => G0_0_L9,
I3 => WRP_V_LOADCOUNT_1_SQMUXA,
O => WRP_UN1_V_BWN_1_SQMUXA_2_D);
II_g3: LUT4
generic map(
INIT => X"DFCC"
)
port map (
I0 => G3_1,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => SSRSTATE6_XX_MM_M3,
O => G3);
II_g3_1: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_V_CHANGE_1_SQMUXA_N_3,
I1 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => G3_1);
II_g0_i_m2_0_L1: LUT3
generic map(
INIT => X"01"
)
port map (
I0 => WRP_R_WS(0),
I1 => WRP_R_WS(1),
I2 => WRP_R_WS(2),
O => G0_I_M2_0_L1);
II_g0_i_m2_0_L3: LUT4
generic map(
INIT => X"0A2A"
)
port map (
I0 => G0_I_M2_0_L1,
I1 => G0_30,
I2 => WRP_V_WS_0_SQMUXA_1,
I3 => WRP_V_WS_3_SQMUXA_1,
O => G0_I_M2_0_L3);
II_g0_i_m2_0_L5: LUT4
generic map(
INIT => X"1555"
)
port map (
I0 => D_M1_E_L1_0,
I1 => D_M1_E_L3,
I2 => WRP_V_WS_2_SQMUXA_3_0_2,
I3 => WRP_V_WS_2_SQMUXA_3_D,
O => G0_I_M2_0_L5);
II_d_m1_e_L1_0: LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => N_365,
I1 => D_M1_E_L1,
I2 => WRP_R_MCFG1_ROMRWS(3),
O => D_M1_E_L1_0);
II_d_m1_e_L3: LUT4_L
generic map(
INIT => X"0F2F"
)
port map (
I0 => WRP_UN1_R_SSRSTATE_2_I,
I1 => G0_30,
I2 => WRP_V_WS_0_SQMUXA_1,
I3 => WRP_V_WS_3_SQMUXA_1,
LO => D_M1_E_L3);
II_g0_57_1_L7_L4: LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => SSRSTATE6_1_D_0_L1,
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => WRP_R_SSRSTATE(1),
O => G0_57_1_L7_L4);
II_g0_57_1_L7_L8: LUT4_L
generic map(
INIT => X"4C40"
)
port map (
I0 => G0_57_1_L7_L4,
I1 => G0_57_1_L7_L6,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(2),
LO => G0_57_1_L7_L8);
II_g0_57_1_L7: LUT4_L
generic map(
INIT => X"4F5F"
)
port map (
I0 => N_656,
I1 => G0_57_1_L7_L8,
I2 => rst,
I3 => SSRSTATE6_XX_MM_M3,
LO => G0_57_1_L7);
II_g0_34_L10_L1: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
I3 => WRP_R_SSRSTATE(1),
O => G0_34_L10_L1);
II_g0_34_L10_L3: LUT2
generic map(
INIT => X"7"
)
port map (
I0 => G0_34_L10_L1,
I1 => WRP_CTRL_V_HSEL_5,
O => G0_34_L10_L3);
II_g0_34_L10: LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => G0_34_L10_L3,
I1 => WRP_CTRL_V_HMBSEL_4(1),
I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
I3 => WRP_V_SSRSTATE_6_SQMUXA,
O => G0_34_L10);
II_g0_48_L1: LUT3
generic map(
INIT => X"40"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
O => G0_48_L1);
II_g0_48: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_48_L1,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_CTRL_V_HSEL_5,
O => WRP_V_LOADCOUNT_1_SQMUXA);
II_g0_36_L1: LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_HSEL,
I2 => WRP_R_PRSTATE(5),
O => G0_36_L1);
II_g0_36: LUT4
generic map(
INIT => X"2220"
)
port map (
I0 => G0_I_M2_1,
I1 => G0_36_L1,
I2 => WRP_CTRL_V_HSEL_5,
I3 => WRP_R_CHANGE,
O => WRP_V_PRSTATE_1_I_O4_S(2));
II_g0_55_L7: LUT4_L
generic map(
INIT => X"4CFC"
)
port map (
I0 => G0_55_L1,
I1 => G0_55_L5,
I2 => G0_55_L7_L1,
I3 => WRP_CTRL_V_HMBSEL_4(1),
LO => G0_55_L7);
II_g0_55_L5_L1: LUT4
generic map(
INIT => X"35FF"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_htrans(0),
O => G0_55_L5_L1);
II_g0_55_L5: LUT4
generic map(
INIT => X"51FF"
)
port map (
I0 => G0_55_L5_L1,
I1 => n_ahbsi_hready,
I2 => WRP_CTRL_V_HSEL_4,
I3 => WRP_R_SSRSTATE(2),
O => G0_55_L5);
II_g0_57_1_L5: LUT3
generic map(
INIT => X"70"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_2_SQMUXA_3_D,
O => G0_57_1_L5);
II_g0_57_1: LUT4_L
generic map(
INIT => X"1D55"
)
port map (
I0 => N_365,
I1 => G0_57_1_L5,
I2 => G0_57_1_L7,
I3 => WRP_V_WS_2_SQMUXA_3_0_4,
LO => G0_57_1);
II_d_m1_e_L1: LUT4
generic map(
INIT => X"087F"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_R_MCFG1_IOWS(3),
I3 => WRP_R_MCFG1_ROMWWS(3),
O => D_M1_E_L1);
II_g0_i_o4: LUT4_L
generic map(
INIT => X"FDF5"
)
port map (
I0 => N_365,
I1 => WS_2_SQMUXA_3_0_X,
I2 => WRP_V_WS_1_SQMUXA,
I3 => WRP_V_WS_2_SQMUXA_3_0_4,
LO => N_5);
II_g3_2: LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => G0_50_X,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hsel(0),
I3 => n_ahbsi_htrans(1),
O => N_19);
II_g0_50_x: LUT3_L
generic map(
INIT => X"80"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_PRSTATE(5),
I2 => WRP_R_SSRSTATE(4),
LO => G0_50_X);
II_g0_52: MUXF5 port map (
I0 => G0_52X,
I1 => G0_52X_0,
S => n_ahbsi_htrans(1),
O => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4);
II_g0_52_x1: LUT4
generic map(
INIT => X"35F5"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => n_ahbsi_hsel(0),
O => G0_52_X1);
II_g0_52_x0: LUT2
generic map(
INIT => X"D"
)
port map (
I0 => D_M1_E_0_0,
I1 => n_ahbsi_hready,
O => G0_52_X0);
II_g1_1: LUT4
generic map(
INIT => X"0105"
)
port map (
I0 => SSRSTATE17_2_0_M6_I_A3_A2,
I1 => n_ahbsi_htrans(1),
I2 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
I3 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
O => N_14);
II_g0_19_L1: LUT4_L
generic map(
INIT => X"0001"
)
port map (
I0 => G0_28,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
LO => G0_19_L1);
II_g0_19: LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => G0_19_L1,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
I3 => WRP_V_SSRSTATE_6_SQMUXA,
O => N_622);
II_g0_55_L1: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => n_ahbsi_hwrite,
I3 => WRP_R_SSRSTATE(1),
O => G0_55_L1);
II_g0_55: LUT4
generic map(
INIT => X"0F0D"
)
port map (
I0 => G0_55_L7,
I1 => WRP_R_LOADCOUNT,
I2 => WRP_R_SSRSTATE(3),
I3 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => WRP_CTRL_V_LOADCOUNT_7);
II_g0_34_L1_0: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_V_WS_0_SQMUXA_0_C,
O => G0_34_L1_0);
II_g0_34_L6: LUT4
generic map(
INIT => X"A2AA"
)
port map (
I0 => G0_34_L1_0,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_SSRSTATE(0),
I3 => WRP_V_WS_0_SQMUXA_C,
O => G0_34_L6);
II_g0_34: LUT4_L
generic map(
INIT => X"51F3"
)
port map (
I0 => G0_34_L6,
I1 => G0_34_L10,
I2 => WRP_NONAME_CNST(0),
I3 => WRP_R_SSRSTATE(1),
LO => G0_34);
II_g0_54_L1: LUT4_L
generic map(
INIT => X"0400"
)
port map (
I0 => n_ahbsi_htrans(0),
I1 => n_ahbsi_htrans(1),
I2 => WRP_CTRL_UN1_AHBSI,
I3 => WRP_CTRL_V_HSEL_5,
LO => G0_54_L1);
II_g0_54: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_54_L1,
I1 => n_ahbsi_hwrite,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_R_SSRSTATE(1),
O => WRP_CTRL_V_SSRSTATE_1_M1(3));
II_g0_i_m2_L1: LUT3
generic map(
INIT => X"75"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
I2 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_I_M2_L1);
II_g0_56: LUT4
generic map(
INIT => X"CC5A"
)
port map (
I0 => N_9,
I1 => WRP_R_MCFG1_ROMRWS(0),
I2 => WRP_R_WS(0),
I3 => WRP_V_WS_1_SQMUXA,
O => G0_56);
II_g1_3: LUT3_L
generic map(
INIT => X"37"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_3_SQMUXA_1,
LO => N_9);
II_g0_30: LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => N_14,
I1 => N_19,
I2 => G0_8,
I3 => WRP_R_SSRSTATE(4),
O => G0_30);
II_g0_16: LUT4
generic map(
INIT => X"337F"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_V_WS_2_SQMUXA_0,
I3 => WRP_V_WS_4_SQMUXA_0,
O => N_365);
II_g0_8: LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => n_ahbsi_hready,
I1 => WRP_R_HMBSEL(1),
I2 => WRP_R_HSEL,
I3 => WRP_R_PRSTATE(5),
O => G0_8);
II_g0_i_m2_2: LUT4
generic map(
INIT => X"F780"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => rst,
I2 => WRP_R_MCFG1_IOWS(0),
I3 => WRP_R_MCFG1_ROMWWS(0),
O => G0_I_M2_2);
II_g0_7: LUT3
generic map(
INIT => X"54"
)
port map (
I0 => N_SRO_IOSN_INT_259,
I1 => WRP_R_PRSTATE(4),
I2 => WRP_R_PRSTATE_2_REP1,
O => WRP_V_WS_2_SQMUXA_0);
II_g0_6: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => N_SRO_ROMSN_0_INT_260,
I1 => WRP_R_PRSTATE_FAST(2),
O => WRP_V_WS_4_SQMUXA_0);
II_g0_53: LUT4
generic map(
INIT => X"1050"
)
port map (
I0 => G0_51,
I1 => WRP_CTRL_V_HSEL_4,
I2 => WRP_R_SSRSTATE(4),
I3 => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0,
O => WRP_V_SSRSTATE_1_SQMUXA_1);
II_g0_51: LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => G0_8_1,
I1 => n_ahbsi_hready,
I2 => WRP_R_HMBSEL(1),
I3 => WRP_R_HSEL,
O => G0_51);
II_g0_50: LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => n_ahbsi_hmbsel(1),
I1 => n_ahbsi_hready,
I2 => WRP_R_PRSTATE(5),
I3 => WRP_R_SSRSTATE(4),
O => WRP_V_SSRSTATE_1_SQMUXA_1_XX_MM_A1_0);
II_g0_8_1: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_PRSTATE(5),
I1 => WRP_R_SSRSTATE(4),
O => G0_8_1);
II_g0_4: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_HMBSEL(1),
I1 => WRP_R_HSEL,
O => D_M1_E_0_0);
II_g0_3: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => n_ahbsi_hsel(0),
I1 => n_ahbsi_htrans(1),
O => WRP_CTRL_V_HSEL_4);
II_g0_i_0: LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => G0_I_A3_0,
I1 => rst,
I2 => WRP_R_PRSTATE(2),
I3 => WRP_V_BWN_0_SQMUXA_1,
O => WRP_CTRL_V_BWN_1_0_O3(0));
II_g0_2: LUT4
generic map(
INIT => X"C4CC"
)
port map (
I0 => WRP_CTRL_V_HMBSEL_4(1),
I1 => SSRSTATE6_XX_MM_M3,
I2 => WRP_V_CHANGE_1_SQMUXA_N_3,
I3 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
O => N_646);
II_g0_i_a3_0: LUT4_L
generic map(
INIT => X"5D7F"
)
port map (
I0 => N_319_1,
I1 => N_662,
I2 => n_ahbsi_haddr(0),
I3 => N_SRO_ADDRESS_0_INT_172,
LO => G0_I_A3_0);
II_g0: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662,
I1 => n_ahbsi_haddr(1),
I2 => N_SRO_ADDRESS_1_INT_173,
O => WRP_HADDR(1));
II_g0_i: LUT4
generic map(
INIT => X"F3A2"
)
port map (
I0 => G0_11,
I1 => n_ahbsi_htrans(0),
I2 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
I3 => WRP_R_D16MUXC_0_4,
O => G0_I);
II_g0_47: LUT4
generic map(
INIT => X"202A"
)
port map (
I0 => rst,
I1 => WRP_R_D16MUXC_0_4,
I2 => WRP_R_PRSTATE(1),
I3 => WRP_R_PRSTATE_2_REP1,
O => WRP_V_BWN_0_SQMUXA_1);
II_g0_38: LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => N_662,
I1 => n_ahbsi_hsize(1),
I2 => WRP_R_SIZE(1),
O => WRP_CTRL_HSIZE_1(1));
II_g0_11: LUT2_L
generic map(
INIT => X"4"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
LO => G0_11);
II_g0_44: LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => G0_5_0,
I1 => WRP_CTRL_UN7_BUS16EN,
I2 => WRP_R_PRSTATE(0),
I3 => WRP_V_D16MUX_0_SQMUXA,
O => G0_44);
II_g0_43: LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => N_SRO_ADDRESS_1_INT_173,
I1 => WRP_CTRL_BUS16EN,
I2 => WRP_R_SIZE(0),
I3 => WRP_R_SIZE(1),
O => WRP_CTRL_UN7_BUS16EN);
II_g0_41: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => N_17,
I1 => WRP_R_CHANGE,
O => G0_1_0);
II_g0_5_0: LUT2
generic map(
INIT => X"E"
)
port map (
I0 => WRP_R_PRHREADY,
I1 => WRP_R_PRSTATE(5),
O => G0_5_0);
II_g0_40: LUT2
generic map(
INIT => X"4"
)
port map (
I0 => WRP_CTRL_UN1_AHBSI,
I1 => WRP_CTRL_V_HSEL_5,
O => N_17);
II_g0_39: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => WRP_R_D16MUXC_0_4,
I1 => WRP_R_PRSTATE(3),
O => WRP_V_D16MUX_0_SQMUXA);
II_g0_18: LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => G0_7_0,
I1 => WRP_CTRL_V_HMBSEL_4(1),
I2 => WRP_R_CHANGE,
O => WRP_CTRL_V_CHANGE_3_F1_D_0_0);
II_g0_17: LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => G0_I_M2_1,
I1 => WRP_CTRL_V_HSEL_5,
I2 => WRP_R_CHANGE,
I3 => WRP_R_HSEL,
O => WRP_UN1_V_HSEL_1(0));
II_g0_7_0: LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(2),
I3 => WRP_R_SSRSTATE(4),
O => G0_7_0);
II_g0_15: LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => WRP_R_CHANGE,
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(2),
I3 => WRP_R_SSRSTATE(4),
O => WRP_CTRL_V_CHANGE_3_F0);
II_g0_i_m2_1: LUT4
generic map(
INIT => X"3353"
)
port map (
I0 => HSEL_1_0_L3,
I1 => G0_14,
I2 => n_ahbsi_hready,
I3 => WRP_R_CHANGE,
O => G0_I_M2_1);
II_g0_14: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_HMBSEL(0),
I1 => WRP_R_HMBSEL(2),
O => G0_14);
II_g0_33: LUT4
generic map(
INIT => X"085D"
)
port map (
I0 => G0_31,
I1 => G2_1_0,
I2 => WRP_R_SSRSTATE(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
O => WRP_UN1_V_CHANGE_1_SQMUXA_0);
II_g0_32: LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => G0_28,
I1 => WRP_CTRL_UN1_AHBSI,
I2 => WRP_CTRL_V_HMBSEL_4(1),
I3 => WRP_V_CHANGE_1_SQMUXA_N_3,
O => WRP_NONAME_CNST(0));
II_g0_31: LUT4
generic map(
INIT => X"FFAB"
)
port map (
I0 => G0_28,
I1 => n_ahbsi_htrans(0),
I2 => n_ahbsi_htrans(1),
I3 => WRP_R_SSRSTATE(0),
O => G0_31);
II_g2_1_0: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(0),
I1 => WRP_R_SSRSTATE(2),
O => G2_1_0);
II_g0_29: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => n_ahbsi_hwrite,
I1 => WRP_V_SSRSTATE_1_SQMUXA_1,
O => G0_29);
II_g0_28: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(1),
I1 => WRP_R_SSRSTATE(2),
O => G0_28);
II_g0_27: LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
O => WRP_V_SSRSTATE_2_SQMUXA_1);
II_g0_25: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => N_365,
I1 => WRP_V_WS_1_SQMUXA,
O => G0_25);
II_g0_23: LUT3
generic map(
INIT => X"37"
)
port map (
I0 => G0_30,
I1 => WRP_V_WS_0_SQMUXA_1,
I2 => WRP_V_WS_3_SQMUXA_1,
O => G0_23);
II_g0_12: LUT2
generic map(
INIT => X"1"
)
port map (
I0 => WRP_R_SSRSTATE(0),
I1 => WRP_R_SSRSTATE(2),
O => D_M2_0_A2_0);
II_g0_10: LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rst,
I1 => WRP_R_SSRSTATE(3),
O => WRP_UN1_V_SSRSTATE_2_SQMUXA_I);
II_g0_1: LUT4
generic map(
INIT => X"FFD5"
)
port map (
I0 => G0_I,
I1 => rst,
I2 => WRP_R_PRSTATE(2),
I3 => WRP_V_LOADCOUNT_1_SQMUXA,
O => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2);
II_N_574_i: LUT4_L
generic map(
INIT => X"5545"
)
port map (
I0 => N_593,
I1 => N_596,
I2 => D_M1_E_0_0,
I3 => n_ahbsi_hready,
LO => N_574_I);
II_N_574_i_a3_0: LUT4_L
generic map(
INIT => X"4000"
)
port map (
I0 => N_597,
I1 => n_ahbsi_hmbsel(1),
I2 => n_ahbsi_hready,
I3 => WRP_CTRL_V_HSEL_4,
LO => N_593);
II_N_574_i_o3_0: LUT4
generic map(
INIT => X"135F"
)
port map (
I0 => n_ahbsi_htrans(1),
I1 => WRP_R_PRSTATE(5),
I2 => WRP_R_SSRSTATE(1),
I3 => WRP_R_SSRSTATE(4),
O => N_596);
II_N_574_i_o3: LUT3
generic map(
INIT => X"13"
)
port map (
I0 => WRP_R_PRSTATE(5),
I1 => WRP_R_SSRSTATE(1),
I2 => WRP_R_SSRSTATE(4),
O => N_597);
II_wrp: ssrctrl_unisim_netlist port map (
n_sro_vbdrive(0) => n_sro_vbdrive(0),
n_sro_vbdrive(1) => n_sro_vbdrive(1),
n_sro_vbdrive(2) => n_sro_vbdrive(2),
n_sro_vbdrive(3) => n_sro_vbdrive(3),
n_sro_vbdrive(4) => n_sro_vbdrive(4),
n_sro_vbdrive(5) => n_sro_vbdrive(5),
n_sro_vbdrive(6) => n_sro_vbdrive(6),
n_sro_vbdrive(7) => n_sro_vbdrive(7),
n_sro_vbdrive(8) => n_sro_vbdrive(8),
n_sro_vbdrive(9) => n_sro_vbdrive(9),
n_sro_vbdrive(10) => n_sro_vbdrive(10),
n_sro_vbdrive(11) => n_sro_vbdrive(11),
n_sro_vbdrive(12) => n_sro_vbdrive(12),
n_sro_vbdrive(13) => n_sro_vbdrive(13),
n_sro_vbdrive(14) => n_sro_vbdrive(14),
n_sro_vbdrive(15) => n_sro_vbdrive(15),
n_sro_vbdrive(16) => n_sro_vbdrive(16),
n_sro_vbdrive(17) => n_sro_vbdrive(17),
n_sro_vbdrive(18) => n_sro_vbdrive(18),
n_sro_vbdrive(19) => n_sro_vbdrive(19),
n_sro_vbdrive(20) => n_sro_vbdrive(20),
n_sro_vbdrive(21) => n_sro_vbdrive(21),
n_sro_vbdrive(22) => n_sro_vbdrive(22),
n_sro_vbdrive(23) => n_sro_vbdrive(23),
n_sro_vbdrive(24) => n_sro_vbdrive(24),
n_sro_vbdrive(25) => n_sro_vbdrive(25),
n_sro_vbdrive(26) => n_sro_vbdrive(26),
n_sro_vbdrive(27) => n_sro_vbdrive(27),
n_sro_vbdrive(28) => n_sro_vbdrive(28),
n_sro_vbdrive(29) => n_sro_vbdrive(29),
n_sro_vbdrive(30) => n_sro_vbdrive(30),
n_sro_vbdrive(31) => n_sro_vbdrive(31),
n_ahbso_hrdata(0) => n_ahbso_hrdata(0),
n_ahbso_hrdata(1) => n_ahbso_hrdata(1),
n_ahbso_hrdata(2) => n_ahbso_hrdata(2),
n_ahbso_hrdata(3) => n_ahbso_hrdata(3),
n_ahbso_hrdata(4) => n_ahbso_hrdata(4),
n_ahbso_hrdata(5) => n_ahbso_hrdata(5),
n_ahbso_hrdata(6) => n_ahbso_hrdata(6),
n_ahbso_hrdata(7) => n_ahbso_hrdata(7),
n_ahbso_hrdata(8) => n_ahbso_hrdata(8),
n_ahbso_hrdata(9) => n_ahbso_hrdata(9),
n_ahbso_hrdata(10) => n_ahbso_hrdata(10),
n_ahbso_hrdata(11) => n_ahbso_hrdata(11),
n_ahbso_hrdata(12) => n_ahbso_hrdata(12),
n_ahbso_hrdata(13) => n_ahbso_hrdata(13),
n_ahbso_hrdata(14) => n_ahbso_hrdata(14),
n_ahbso_hrdata(15) => n_ahbso_hrdata(15),
n_ahbso_hrdata(16) => n_ahbso_hrdata(16),
n_ahbso_hrdata(17) => n_ahbso_hrdata(17),
n_ahbso_hrdata(18) => n_ahbso_hrdata(18),
n_ahbso_hrdata(19) => n_ahbso_hrdata(19),
n_ahbso_hrdata(20) => n_ahbso_hrdata(20),
n_ahbso_hrdata(21) => n_ahbso_hrdata(21),
n_ahbso_hrdata(22) => n_ahbso_hrdata(22),
n_ahbso_hrdata(23) => n_ahbso_hrdata(23),
n_ahbso_hrdata(24) => n_ahbso_hrdata(24),
n_ahbso_hrdata(25) => n_ahbso_hrdata(25),
n_ahbso_hrdata(26) => n_ahbso_hrdata(26),
n_ahbso_hrdata(27) => n_ahbso_hrdata(27),
n_ahbso_hrdata(28) => n_ahbso_hrdata(28),
n_ahbso_hrdata(29) => n_ahbso_hrdata(29),
n_ahbso_hrdata(30) => n_ahbso_hrdata(30),
n_ahbso_hrdata(31) => n_ahbso_hrdata(31),
iows_0 => WRP_R_MCFG1_IOWS(0),
iows_3 => WRP_R_MCFG1_IOWS(3),
romwws_0 => WRP_R_MCFG1_ROMWWS(0),
romwws_3 => WRP_R_MCFG1_ROMWWS(3),
romrws_0 => WRP_R_MCFG1_ROMRWS(0),
romrws_3 => WRP_R_MCFG1_ROMRWS(3),
NoName_cnst(0) => WRP_NONAME_CNST(0),
n_sri_bwidth(0) => n_sri_bwidth(0),
n_sri_bwidth(1) => n_sri_bwidth(1),
n_apbi_pwdata_19 => n_apbi_pwdata(19),
n_apbi_pwdata_11 => n_apbi_pwdata(11),
n_apbi_pwdata_9 => n_apbi_pwdata(9),
n_apbi_pwdata_8 => n_apbi_pwdata(8),
n_apbi_pwdata_23 => n_apbi_pwdata(23),
n_apbi_pwdata_22 => n_apbi_pwdata(22),
n_apbi_pwdata_21 => n_apbi_pwdata(21),
n_apbi_pwdata_20 => n_apbi_pwdata(20),
n_apbi_pwdata_3 => n_apbi_pwdata(3),
n_apbi_pwdata_2 => n_apbi_pwdata(2),
n_apbi_pwdata_1 => n_apbi_pwdata(1),
n_apbi_pwdata_0 => n_apbi_pwdata(0),
n_apbi_pwdata_7 => n_apbi_pwdata(7),
n_apbi_pwdata_6 => n_apbi_pwdata(6),
n_apbi_pwdata_5 => n_apbi_pwdata(5),
n_apbi_pwdata_4 => n_apbi_pwdata(4),
n_apbi_psel(0) => n_apbi_psel(0),
n_apbi_paddr(2) => n_apbi_paddr(2),
n_apbi_paddr(3) => n_apbi_paddr(3),
n_apbi_paddr(4) => n_apbi_paddr(4),
n_apbi_paddr(5) => n_apbi_paddr(5),
n_apbo_prdata_0 => n_apbo_prdata(0),
n_apbo_prdata_4 => n_apbo_prdata(4),
n_apbo_prdata_20 => n_apbo_prdata(20),
n_apbo_prdata_23 => n_apbo_prdata(23),
n_apbo_prdata_22 => n_apbo_prdata(22),
n_apbo_prdata_21 => n_apbo_prdata(21),
n_apbo_prdata_19 => n_apbo_prdata(19),
n_apbo_prdata_7 => n_apbo_prdata(7),
n_apbo_prdata_6 => n_apbo_prdata(6),
n_apbo_prdata_5 => n_apbo_prdata(5),
n_apbo_prdata_3 => n_apbo_prdata(3),
n_apbo_prdata_2 => n_apbo_prdata(2),
n_apbo_prdata_1 => n_apbo_prdata(1),
n_apbo_prdata_11 => n_apbo_prdata(11),
n_apbo_prdata_9 => n_apbo_prdata(9),
n_apbo_prdata_8 => n_apbo_prdata(8),
n_apbo_prdata_28 => n_apbo_prdata(28),
n_sro_romsn(0) => N_SRO_ROMSN_0_INT_260,
n_ahbsi_hsel(0) => n_ahbsi_hsel(0),
prstate_fast(2) => WRP_R_PRSTATE_FAST(2),
n_ahbsi_htrans(0) => n_ahbsi_htrans(0),
n_ahbsi_htrans(1) => n_ahbsi_htrans(1),
ssrstate_1_m1(3) => WRP_CTRL_V_SSRSTATE_1_M1(3),
ssrstate_1_m1(4) => WRP_CTRL_V_SSRSTATE_1_M1(4),
hsel_1(0) => WRP_UN1_V_HSEL_1(0),
hmbsel_4(1) => WRP_CTRL_V_HMBSEL_4(1),
n_sro_bdrive(3) => N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272,
ws_1_0 => WRP_CTRL_V_WS_1(0),
ws_1_3 => WRP_CTRL_V_WS_1(3),
ws(0) => WRP_R_WS(0),
ws(1) => WRP_R_WS(1),
ws(2) => WRP_R_WS(2),
ws(3) => WRP_R_WS(3),
ssrstate_1_2 => WRP_CTRL_V_SSRSTATE_1(4),
n_ahbsi_haddr(0) => n_ahbsi_haddr(0),
n_ahbsi_haddr(1) => n_ahbsi_haddr(1),
n_ahbsi_haddr(2) => n_ahbsi_haddr(2),
n_ahbsi_haddr(3) => n_ahbsi_haddr(3),
n_ahbsi_haddr(4) => n_ahbsi_haddr(4),
n_ahbsi_haddr(5) => n_ahbsi_haddr(5),
n_ahbsi_haddr(6) => n_ahbsi_haddr(6),
n_ahbsi_haddr(7) => n_ahbsi_haddr(7),
n_ahbsi_haddr(8) => n_ahbsi_haddr(8),
n_ahbsi_haddr(9) => n_ahbsi_haddr(9),
n_ahbsi_haddr(10) => n_ahbsi_haddr(10),
n_ahbsi_haddr(11) => n_ahbsi_haddr(11),
n_ahbsi_haddr(12) => n_ahbsi_haddr(12),
n_ahbsi_haddr(13) => n_ahbsi_haddr(13),
n_ahbsi_haddr(14) => n_ahbsi_haddr(14),
n_ahbsi_haddr(15) => n_ahbsi_haddr(15),
n_ahbsi_haddr(16) => n_ahbsi_haddr(16),
n_ahbsi_haddr(17) => n_ahbsi_haddr(17),
n_ahbsi_haddr(18) => n_ahbsi_haddr(18),
n_ahbsi_haddr(19) => n_ahbsi_haddr(19),
n_ahbsi_haddr(20) => n_ahbsi_haddr(20),
n_ahbsi_haddr(21) => n_ahbsi_haddr(21),
n_ahbsi_haddr(22) => n_ahbsi_haddr(22),
n_ahbsi_haddr(23) => n_ahbsi_haddr(23),
n_ahbsi_haddr(24) => n_ahbsi_haddr(24),
n_ahbsi_haddr(25) => n_ahbsi_haddr(25),
n_ahbsi_haddr(26) => n_ahbsi_haddr(26),
n_ahbsi_haddr(27) => n_ahbsi_haddr(27),
n_ahbsi_haddr(28) => n_ahbsi_haddr(28),
n_ahbsi_haddr(29) => n_ahbsi_haddr(29),
n_ahbsi_haddr(30) => n_ahbsi_haddr(30),
n_ahbsi_haddr(31) => n_ahbsi_haddr(31),
n_ahbsi_hmbsel(0) => n_ahbsi_hmbsel(0),
n_ahbsi_hmbsel(1) => n_ahbsi_hmbsel(1),
n_ahbsi_hmbsel(2) => n_ahbsi_hmbsel(2),
n_sri_data(0) => n_sri_data(0),
n_sri_data(1) => n_sri_data(1),
n_sri_data(2) => n_sri_data(2),
n_sri_data(3) => n_sri_data(3),
n_sri_data(4) => n_sri_data(4),
n_sri_data(5) => n_sri_data(5),
n_sri_data(6) => n_sri_data(6),
n_sri_data(7) => n_sri_data(7),
n_sri_data(8) => n_sri_data(8),
n_sri_data(9) => n_sri_data(9),
n_sri_data(10) => n_sri_data(10),
n_sri_data(11) => n_sri_data(11),
n_sri_data(12) => n_sri_data(12),
n_sri_data(13) => n_sri_data(13),
n_sri_data(14) => n_sri_data(14),
n_sri_data(15) => n_sri_data(15),
n_sri_data(16) => n_sri_data(16),
n_sri_data(17) => n_sri_data(17),
n_sri_data(18) => n_sri_data(18),
n_sri_data(19) => n_sri_data(19),
n_sri_data(20) => n_sri_data(20),
n_sri_data(21) => n_sri_data(21),
n_sri_data(22) => n_sri_data(22),
n_sri_data(23) => n_sri_data(23),
n_sri_data(24) => n_sri_data(24),
n_sri_data(25) => n_sri_data(25),
n_sri_data(26) => n_sri_data(26),
n_sri_data(27) => n_sri_data(27),
n_sri_data(28) => n_sri_data(28),
n_sri_data(29) => n_sri_data(29),
n_sri_data(30) => n_sri_data(30),
n_sri_data(31) => n_sri_data(31),
ssrstate(0) => WRP_R_SSRSTATE(0),
ssrstate(1) => WRP_R_SSRSTATE(1),
ssrstate(2) => WRP_R_SSRSTATE(2),
ssrstate(3) => WRP_R_SSRSTATE(3),
ssrstate(4) => WRP_R_SSRSTATE(4),
n_ahbsi_hwdata(0) => n_ahbsi_hwdata(0),
n_ahbsi_hwdata(1) => n_ahbsi_hwdata(1),
n_ahbsi_hwdata(2) => n_ahbsi_hwdata(2),
n_ahbsi_hwdata(3) => n_ahbsi_hwdata(3),
n_ahbsi_hwdata(4) => n_ahbsi_hwdata(4),
n_ahbsi_hwdata(5) => n_ahbsi_hwdata(5),
n_ahbsi_hwdata(6) => n_ahbsi_hwdata(6),
n_ahbsi_hwdata(7) => n_ahbsi_hwdata(7),
n_ahbsi_hwdata(8) => n_ahbsi_hwdata(8),
n_ahbsi_hwdata(9) => n_ahbsi_hwdata(9),
n_ahbsi_hwdata(10) => n_ahbsi_hwdata(10),
n_ahbsi_hwdata(11) => n_ahbsi_hwdata(11),
n_ahbsi_hwdata(12) => n_ahbsi_hwdata(12),
n_ahbsi_hwdata(13) => n_ahbsi_hwdata(13),
n_ahbsi_hwdata(14) => n_ahbsi_hwdata(14),
n_ahbsi_hwdata(15) => n_ahbsi_hwdata(15),
n_ahbsi_hwdata(16) => n_ahbsi_hwdata(16),
n_ahbsi_hwdata(17) => n_ahbsi_hwdata(17),
n_ahbsi_hwdata(18) => n_ahbsi_hwdata(18),
n_ahbsi_hwdata(19) => n_ahbsi_hwdata(19),
n_ahbsi_hwdata(20) => n_ahbsi_hwdata(20),
n_ahbsi_hwdata(21) => n_ahbsi_hwdata(21),
n_ahbsi_hwdata(22) => n_ahbsi_hwdata(22),
n_ahbsi_hwdata(23) => n_ahbsi_hwdata(23),
n_ahbsi_hwdata(24) => n_ahbsi_hwdata(24),
n_ahbsi_hwdata(25) => n_ahbsi_hwdata(25),
n_ahbsi_hwdata(26) => n_ahbsi_hwdata(26),
n_ahbsi_hwdata(27) => n_ahbsi_hwdata(27),
n_ahbsi_hwdata(28) => n_ahbsi_hwdata(28),
n_ahbsi_hwdata(29) => n_ahbsi_hwdata(29),
n_ahbsi_hwdata(30) => n_ahbsi_hwdata(30),
n_ahbsi_hwdata(31) => n_ahbsi_hwdata(31),
n_ahbsi_hsize(0) => n_ahbsi_hsize(0),
n_ahbsi_hsize(1) => n_ahbsi_hsize(1),
size(0) => WRP_R_SIZE(0),
size(1) => WRP_R_SIZE(1),
n_sro_data(0) => n_sro_data(0),
n_sro_data(1) => n_sro_data(1),
n_sro_data(2) => n_sro_data(2),
n_sro_data(3) => n_sro_data(3),
n_sro_data(4) => n_sro_data(4),
n_sro_data(5) => n_sro_data(5),
n_sro_data(6) => n_sro_data(6),
n_sro_data(7) => n_sro_data(7),
n_sro_data(8) => n_sro_data(8),
n_sro_data(9) => n_sro_data(9),
n_sro_data(10) => n_sro_data(10),
n_sro_data(11) => n_sro_data(11),
n_sro_data(12) => n_sro_data(12),
n_sro_data(13) => n_sro_data(13),
n_sro_data(14) => n_sro_data(14),
n_sro_data(15) => n_sro_data(15),
n_sro_data(16) => n_sro_data(16),
n_sro_data(17) => n_sro_data(17),
n_sro_data(18) => n_sro_data(18),
n_sro_data(19) => n_sro_data(19),
n_sro_data(20) => n_sro_data(20),
n_sro_data(21) => n_sro_data(21),
n_sro_data(22) => n_sro_data(22),
n_sro_data(23) => n_sro_data(23),
n_sro_data(24) => n_sro_data(24),
n_sro_data(25) => n_sro_data(25),
n_sro_data(26) => n_sro_data(26),
n_sro_data(27) => n_sro_data(27),
n_sro_data(28) => n_sro_data(28),
n_sro_data(29) => n_sro_data(29),
n_sro_data(30) => n_sro_data(30),
n_sro_data(31) => n_sro_data(31),
n_sro_ramsn(0) => n_sro_ramsn(0),
n_sro_wrn(0) => n_sro_wrn(0),
n_sro_wrn(1) => n_sro_wrn(1),
n_sro_wrn(2) => n_sro_wrn(2),
n_sro_wrn(3) => n_sro_wrn(3),
haddr_0 => WRP_HADDR(1),
bwn_1_0_o3_0 => WRP_CTRL_V_BWN_1_0_O3(0),
hsize_1(1) => WRP_CTRL_HSIZE_1(1),
prstate_1_i_o4_s(2) => WRP_V_PRSTATE_1_I_O4_S(2),
prstate(0) => WRP_R_PRSTATE(0),
prstate(1) => WRP_R_PRSTATE(1),
prstate(2) => WRP_R_PRSTATE(2),
prstate(3) => WRP_R_PRSTATE(3),
prstate(4) => WRP_R_PRSTATE(4),
prstate(5) => WRP_R_PRSTATE(5),
hmbsel(0) => WRP_R_HMBSEL(0),
hmbsel(1) => WRP_R_HMBSEL(1),
hmbsel(2) => WRP_R_HMBSEL(2),
n_sro_address(0) => N_SRO_ADDRESS_0_INT_172,
n_sro_address(1) => N_SRO_ADDRESS_1_INT_173,
n_sro_address(2) => n_sro_address(2),
n_sro_address(3) => n_sro_address(3),
n_sro_address(4) => n_sro_address(4),
n_sro_address(5) => n_sro_address(5),
n_sro_address(6) => n_sro_address(6),
n_sro_address(7) => n_sro_address(7),
n_sro_address(8) => n_sro_address(8),
n_sro_address(9) => n_sro_address(9),
n_sro_address(10) => n_sro_address(10),
n_sro_address(11) => n_sro_address(11),
n_sro_address(12) => n_sro_address(12),
n_sro_address(13) => n_sro_address(13),
n_sro_address(14) => n_sro_address(14),
n_sro_address(15) => n_sro_address(15),
n_sro_address(16) => n_sro_address(16),
n_sro_address(17) => n_sro_address(17),
n_sro_address(18) => n_sro_address(18),
n_sro_address(19) => n_sro_address(19),
n_sro_address(20) => n_sro_address(20),
n_sro_address(21) => n_sro_address(21),
n_sro_address(22) => n_sro_address(22),
n_sro_address(23) => n_sro_address(23),
n_sro_address(24) => n_sro_address(24),
n_sro_address(25) => n_sro_address(25),
n_sro_address(26) => n_sro_address(26),
n_sro_address(27) => n_sro_address(27),
n_sro_address(28) => n_sro_address(28),
n_sro_address(29) => n_sro_address(29),
n_sro_address(30) => n_sro_address(30),
n_sro_address(31) => n_sro_address(31),
hready_2 => WRP_CTRL_V_HREADY_2,
n_ahbso_hready => n_ahbso_hready,
ssrhready_8 => WRP_CTRL_V_SSRHREADY_8,
loadcount => WRP_R_LOADCOUNT,
n_sro_writen => n_sro_writen,
ssrstatec => WRP_R_SSRSTATEC,
prhready => WRP_R_PRHREADY,
d_m2_0_a2_0 => D_M2_0_A2_0,
ssrstate17_2_0_m6_i_a3_a2 => SSRSTATE17_2_0_M6_I_A3_A2,
N_319_1 => N_319_1,
ws_0_sqmuxa_c => WRP_V_WS_0_SQMUXA_C,
N_365 => N_365,
ws_0_sqmuxa_0_c => WRP_V_WS_0_SQMUXA_0_C,
ws_2_sqmuxa_3_0_4 => WRP_V_WS_2_SQMUXA_3_0_4,
change_1_sqmuxa_0 => WRP_UN1_V_CHANGE_1_SQMUXA_0,
d16mux_0_sqmuxa => WRP_V_D16MUX_0_SQMUXA,
ssrstate_2_sqmuxa_1 => WRP_V_SSRSTATE_2_SQMUXA_1,
un7_bus16en => WRP_CTRL_UN7_BUS16EN,
N_646 => N_646,
loadcount_1_sqmuxa => WRP_V_LOADCOUNT_1_SQMUXA,
ssrstate_1_sqmuxa_1_0_m3_0_1 => WRP_UN1_V_SSRSTATE_1_SQMUXA_1_0_M3_0_1,
n_apbi_penable => n_apbi_penable,
n_apbi_pwrite => n_apbi_pwrite,
d_m1_e_0_0 => D_M1_E_0_0,
hsel_1_0_L3 => HSEL_1_0_L3,
ssrhready_8_f0_L8 => SSRHREADY_8_F0_L8,
ssrstate_1_sqmuxa_1 => WRP_V_SSRSTATE_1_SQMUXA_1,
ssrhready => WRP_R_SSRHREADY,
ssrhready_8_f0_L5 => SSRHREADY_8_F0_L5,
ssrstate17_1_xx_mm_N_4 => WRP_CTRL_UN1_V_SSRSTATE17_1_XX_MM_N_4,
ws_1_sqmuxa => WRP_V_WS_1_SQMUXA,
ws_4_sqmuxa_0 => WRP_V_WS_4_SQMUXA_0,
ws_2_sqmuxa_0 => WRP_V_WS_2_SQMUXA_0,
ssrstate17_2_0_m6_i_1 => WRP_UN1_V_SSRSTATE17_2_0_M6_I_1,
ws_2_sqmuxa_3_0_x => WS_2_SQMUXA_3_0_X,
ws_3_sqmuxa_1 => WRP_V_WS_3_SQMUXA_1,
ws_2_sqmuxa_3_0_2 => WRP_V_WS_2_SQMUXA_3_0_2,
ssrstate_2_i => WRP_UN1_R_SSRSTATE_2_I,
ws_2_sqmuxa_3_d => WRP_V_WS_2_SQMUXA_3_D,
ws_0_sqmuxa_1 => WRP_V_WS_0_SQMUXA_1,
g0_30 => G0_30,
hsel_4 => WRP_CTRL_V_HSEL_4,
n_ahbsi_hready => n_ahbsi_hready,
hsel => WRP_R_HSEL,
g0_25 => G0_25,
bwn_0_sqmuxa_1 => WRP_V_BWN_0_SQMUXA_1,
prstate_2_rep1 => WRP_R_PRSTATE_2_REP1,
N_662 => N_662,
ssrstate_6_sqmuxa => WRP_V_SSRSTATE_6_SQMUXA,
g0_52_x1 => G0_52_X1,
g0_52_x0 => G0_52_X0,
ssrhready_2_sqmuxa_0_0 => WRP_V_SSRHREADY_2_SQMUXA_0_0,
change_1_sqmuxa_N_3 => WRP_V_CHANGE_1_SQMUXA_N_3,
ssrstate6_xx_mm_m3 => SSRSTATE6_XX_MM_M3,
ssrstate6_1_d_0_L1 => SSRSTATE6_1_D_0_L1,
N_656 => N_656,
hsel_5 => WRP_CTRL_V_HSEL_5,
change_3_f0 => WRP_CTRL_V_CHANGE_3_F0,
un1_ahbsi => WRP_CTRL_UN1_AHBSI,
change => WRP_R_CHANGE,
n_ahbsi_hwrite => n_ahbsi_hwrite,
N_574_i => N_574_I,
n_sro_iosn => N_SRO_IOSN_INT_259,
N_618_i => N_618_I,
clk => clk,
n_sro_oen => N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268,
rst => rst,
bwn_1_sqmuxa_2_d => WRP_UN1_V_BWN_1_SQMUXA_2_D,
bwn_1_sqmuxa_2_d_0_2 => WRP_UN1_V_BWN_1_SQMUXA_2_D_0_2,
ssrstate_2_sqmuxa_i => WRP_UN1_V_SSRSTATE_2_SQMUXA_I,
g0_23 => G0_23,
N_371 => N_371,
loadcount_7 => WRP_CTRL_V_LOADCOUNT_7,
bus16en => WRP_CTRL_BUS16EN,
d16muxc_0_4 => WRP_R_D16MUXC_0_4,
change_3_f1_d_0_0 => WRP_CTRL_V_CHANGE_3_F1_D_0_0,
g0_1_0 => G0_1_0,
g0_44 => G0_44);
II_GND: GND port map (
G => NN_2);
II_VCC: VCC port map (
P => NN_1);
n_ahbso_hresp(0) <= NN_2;
n_ahbso_hresp(1) <= NN_2;
n_ahbso_hsplit(0) <= NN_2;
n_ahbso_hsplit(1) <= NN_2;
n_ahbso_hsplit(2) <= NN_2;
n_ahbso_hsplit(3) <= NN_2;
n_ahbso_hsplit(4) <= NN_2;
n_ahbso_hsplit(5) <= NN_2;
n_ahbso_hsplit(6) <= NN_2;
n_ahbso_hsplit(7) <= NN_2;
n_ahbso_hsplit(8) <= NN_2;
n_ahbso_hsplit(9) <= NN_2;
n_ahbso_hsplit(10) <= NN_2;
n_ahbso_hsplit(11) <= NN_2;
n_ahbso_hsplit(12) <= NN_2;
n_ahbso_hsplit(13) <= NN_2;
n_ahbso_hsplit(14) <= NN_2;
n_ahbso_hsplit(15) <= NN_2;
n_ahbso_hcache <= NN_1;
n_ahbso_hirq(0) <= NN_2;
n_ahbso_hirq(1) <= NN_2;
n_ahbso_hirq(2) <= NN_2;
n_ahbso_hirq(3) <= NN_2;
n_ahbso_hirq(4) <= NN_2;
n_ahbso_hirq(5) <= NN_2;
n_ahbso_hirq(6) <= NN_2;
n_ahbso_hirq(7) <= NN_2;
n_ahbso_hirq(8) <= NN_2;
n_ahbso_hirq(9) <= NN_2;
n_ahbso_hirq(10) <= NN_2;
n_ahbso_hirq(11) <= NN_2;
n_ahbso_hirq(12) <= NN_2;
n_ahbso_hirq(13) <= NN_2;
n_ahbso_hirq(14) <= NN_2;
n_ahbso_hirq(15) <= NN_2;
n_ahbso_hirq(16) <= NN_2;
n_ahbso_hirq(17) <= NN_2;
n_ahbso_hirq(18) <= NN_2;
n_ahbso_hirq(19) <= NN_2;
n_ahbso_hirq(20) <= NN_2;
n_ahbso_hirq(21) <= NN_2;
n_ahbso_hirq(22) <= NN_2;
n_ahbso_hirq(23) <= NN_2;
n_ahbso_hirq(24) <= NN_2;
n_ahbso_hirq(25) <= NN_2;
n_ahbso_hirq(26) <= NN_2;
n_ahbso_hirq(27) <= NN_2;
n_ahbso_hirq(28) <= NN_2;
n_ahbso_hirq(29) <= NN_2;
n_ahbso_hirq(30) <= NN_2;
n_ahbso_hirq(31) <= NN_2;
n_apbo_prdata(10) <= NN_2;
n_apbo_prdata(12) <= NN_2;
n_apbo_prdata(13) <= NN_2;
n_apbo_prdata(14) <= NN_2;
n_apbo_prdata(15) <= NN_2;
n_apbo_prdata(16) <= NN_2;
n_apbo_prdata(17) <= NN_2;
n_apbo_prdata(18) <= NN_2;
n_apbo_prdata(24) <= NN_2;
n_apbo_prdata(25) <= NN_2;
n_apbo_prdata(26) <= NN_2;
n_apbo_prdata(27) <= NN_2;
n_apbo_prdata(29) <= NN_2;
n_apbo_prdata(30) <= NN_2;
n_apbo_prdata(31) <= NN_2;
n_apbo_pirq(0) <= NN_2;
n_apbo_pirq(1) <= NN_2;
n_apbo_pirq(2) <= NN_2;
n_apbo_pirq(3) <= NN_2;
n_apbo_pirq(4) <= NN_2;
n_apbo_pirq(5) <= NN_2;
n_apbo_pirq(6) <= NN_2;
n_apbo_pirq(7) <= NN_2;
n_apbo_pirq(8) <= NN_2;
n_apbo_pirq(9) <= NN_2;
n_apbo_pirq(10) <= NN_2;
n_apbo_pirq(11) <= NN_2;
n_apbo_pirq(12) <= NN_2;
n_apbo_pirq(13) <= NN_2;
n_apbo_pirq(14) <= NN_2;
n_apbo_pirq(15) <= NN_2;
n_apbo_pirq(16) <= NN_2;
n_apbo_pirq(17) <= NN_2;
n_apbo_pirq(18) <= NN_2;
n_apbo_pirq(19) <= NN_2;
n_apbo_pirq(20) <= NN_2;
n_apbo_pirq(21) <= NN_2;
n_apbo_pirq(22) <= NN_2;
n_apbo_pirq(23) <= NN_2;
n_apbo_pirq(24) <= NN_2;
n_apbo_pirq(25) <= NN_2;
n_apbo_pirq(26) <= NN_2;
n_apbo_pirq(27) <= NN_2;
n_apbo_pirq(28) <= NN_2;
n_apbo_pirq(29) <= NN_2;
n_apbo_pirq(30) <= NN_2;
n_apbo_pirq(31) <= NN_2;
n_sro_address(0) <= N_SRO_ADDRESS_0_INT_172;
n_sro_address(1) <= N_SRO_ADDRESS_1_INT_173;
n_sro_sddata(0) <= NN_2;
n_sro_sddata(1) <= NN_2;
n_sro_sddata(2) <= NN_2;
n_sro_sddata(3) <= NN_2;
n_sro_sddata(4) <= NN_2;
n_sro_sddata(5) <= NN_2;
n_sro_sddata(6) <= NN_2;
n_sro_sddata(7) <= NN_2;
n_sro_sddata(8) <= NN_2;
n_sro_sddata(9) <= NN_2;
n_sro_sddata(10) <= NN_2;
n_sro_sddata(11) <= NN_2;
n_sro_sddata(12) <= NN_2;
n_sro_sddata(13) <= NN_2;
n_sro_sddata(14) <= NN_2;
n_sro_sddata(15) <= NN_2;
n_sro_sddata(16) <= NN_2;
n_sro_sddata(17) <= NN_2;
n_sro_sddata(18) <= NN_2;
n_sro_sddata(19) <= NN_2;
n_sro_sddata(20) <= NN_2;
n_sro_sddata(21) <= NN_2;
n_sro_sddata(22) <= NN_2;
n_sro_sddata(23) <= NN_2;
n_sro_sddata(24) <= NN_2;
n_sro_sddata(25) <= NN_2;
n_sro_sddata(26) <= NN_2;
n_sro_sddata(27) <= NN_2;
n_sro_sddata(28) <= NN_2;
n_sro_sddata(29) <= NN_2;
n_sro_sddata(30) <= NN_2;
n_sro_sddata(31) <= NN_2;
n_sro_sddata(32) <= NN_2;
n_sro_sddata(33) <= NN_2;
n_sro_sddata(34) <= NN_2;
n_sro_sddata(35) <= NN_2;
n_sro_sddata(36) <= NN_2;
n_sro_sddata(37) <= NN_2;
n_sro_sddata(38) <= NN_2;
n_sro_sddata(39) <= NN_2;
n_sro_sddata(40) <= NN_2;
n_sro_sddata(41) <= NN_2;
n_sro_sddata(42) <= NN_2;
n_sro_sddata(43) <= NN_2;
n_sro_sddata(44) <= NN_2;
n_sro_sddata(45) <= NN_2;
n_sro_sddata(46) <= NN_2;
n_sro_sddata(47) <= NN_2;
n_sro_sddata(48) <= NN_2;
n_sro_sddata(49) <= NN_2;
n_sro_sddata(50) <= NN_2;
n_sro_sddata(51) <= NN_2;
n_sro_sddata(52) <= NN_2;
n_sro_sddata(53) <= NN_2;
n_sro_sddata(54) <= NN_2;
n_sro_sddata(55) <= NN_2;
n_sro_sddata(56) <= NN_2;
n_sro_sddata(57) <= NN_2;
n_sro_sddata(58) <= NN_2;
n_sro_sddata(59) <= NN_2;
n_sro_sddata(60) <= NN_2;
n_sro_sddata(61) <= NN_2;
n_sro_sddata(62) <= NN_2;
n_sro_sddata(63) <= NN_2;
n_sro_ramsn(1) <= NN_1;
n_sro_ramsn(2) <= NN_1;
n_sro_ramsn(3) <= NN_1;
n_sro_ramsn(4) <= NN_1;
n_sro_ramsn(5) <= NN_1;
n_sro_ramsn(6) <= NN_1;
n_sro_ramsn(7) <= NN_1;
n_sro_ramoen(0) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(1) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(2) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(3) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(4) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(5) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(6) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramoen(7) <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_ramn <= NN_2;
n_sro_romn <= NN_2;
n_sro_mben(0) <= NN_2;
n_sro_mben(1) <= NN_2;
n_sro_mben(2) <= NN_2;
n_sro_mben(3) <= NN_2;
n_sro_iosn <= N_SRO_IOSN_INT_259;
n_sro_romsn(0) <= N_SRO_ROMSN_0_INT_260;
n_sro_romsn(1) <= NN_1;
n_sro_romsn(2) <= NN_1;
n_sro_romsn(3) <= NN_1;
n_sro_romsn(4) <= NN_1;
n_sro_romsn(5) <= NN_1;
n_sro_romsn(6) <= NN_1;
n_sro_romsn(7) <= NN_1;
n_sro_oen <= N_SRO_OEN_INT_245_INT_246_INT_247_INT_248_INT_249_INT_250_INT_251_INT_252_INT_268;
n_sro_bdrive(0) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(1) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(2) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_bdrive(3) <= N_SRO_BDRIVE_3_INT_269_INT_270_INT_271_INT_272;
n_sro_svbdrive(0) <= NN_2;
n_sro_svbdrive(1) <= NN_2;
n_sro_svbdrive(2) <= NN_2;
n_sro_svbdrive(3) <= NN_2;
n_sro_svbdrive(4) <= NN_2;
n_sro_svbdrive(5) <= NN_2;
n_sro_svbdrive(6) <= NN_2;
n_sro_svbdrive(7) <= NN_2;
n_sro_svbdrive(8) <= NN_2;
n_sro_svbdrive(9) <= NN_2;
n_sro_svbdrive(10) <= NN_2;
n_sro_svbdrive(11) <= NN_2;
n_sro_svbdrive(12) <= NN_2;
n_sro_svbdrive(13) <= NN_2;
n_sro_svbdrive(14) <= NN_2;
n_sro_svbdrive(15) <= NN_2;
n_sro_svbdrive(16) <= NN_2;
n_sro_svbdrive(17) <= NN_2;
n_sro_svbdrive(18) <= NN_2;
n_sro_svbdrive(19) <= NN_2;
n_sro_svbdrive(20) <= NN_2;
n_sro_svbdrive(21) <= NN_2;
n_sro_svbdrive(22) <= NN_2;
n_sro_svbdrive(23) <= NN_2;
n_sro_svbdrive(24) <= NN_2;
n_sro_svbdrive(25) <= NN_2;
n_sro_svbdrive(26) <= NN_2;
n_sro_svbdrive(27) <= NN_2;
n_sro_svbdrive(28) <= NN_2;
n_sro_svbdrive(29) <= NN_2;
n_sro_svbdrive(30) <= NN_2;
n_sro_svbdrive(31) <= NN_2;
n_sro_svbdrive(32) <= NN_2;
n_sro_svbdrive(33) <= NN_2;
n_sro_svbdrive(34) <= NN_2;
n_sro_svbdrive(35) <= NN_2;
n_sro_svbdrive(36) <= NN_2;
n_sro_svbdrive(37) <= NN_2;
n_sro_svbdrive(38) <= NN_2;
n_sro_svbdrive(39) <= NN_2;
n_sro_svbdrive(40) <= NN_2;
n_sro_svbdrive(41) <= NN_2;
n_sro_svbdrive(42) <= NN_2;
n_sro_svbdrive(43) <= NN_2;
n_sro_svbdrive(44) <= NN_2;
n_sro_svbdrive(45) <= NN_2;
n_sro_svbdrive(46) <= NN_2;
n_sro_svbdrive(47) <= NN_2;
n_sro_svbdrive(48) <= NN_2;
n_sro_svbdrive(49) <= NN_2;
n_sro_svbdrive(50) <= NN_2;
n_sro_svbdrive(51) <= NN_2;
n_sro_svbdrive(52) <= NN_2;
n_sro_svbdrive(53) <= NN_2;
n_sro_svbdrive(54) <= NN_2;
n_sro_svbdrive(55) <= NN_2;
n_sro_svbdrive(56) <= NN_2;
n_sro_svbdrive(57) <= NN_2;
n_sro_svbdrive(58) <= NN_2;
n_sro_svbdrive(59) <= NN_2;
n_sro_svbdrive(60) <= NN_2;
n_sro_svbdrive(61) <= NN_2;
n_sro_svbdrive(62) <= NN_2;
n_sro_svbdrive(63) <= NN_2;
n_sro_read <= NN_2;
n_sro_sa(0) <= NN_2;
n_sro_sa(1) <= NN_2;
n_sro_sa(2) <= NN_2;
n_sro_sa(3) <= NN_2;
n_sro_sa(4) <= NN_2;
n_sro_sa(5) <= NN_2;
n_sro_sa(6) <= NN_2;
n_sro_sa(7) <= NN_2;
n_sro_sa(8) <= NN_2;
n_sro_sa(9) <= NN_2;
n_sro_sa(10) <= NN_2;
n_sro_sa(11) <= NN_2;
n_sro_sa(12) <= NN_2;
n_sro_sa(13) <= NN_2;
n_sro_sa(14) <= NN_2;
n_sro_cb(0) <= NN_2;
n_sro_cb(1) <= NN_2;
n_sro_cb(2) <= NN_2;
n_sro_cb(3) <= NN_2;
n_sro_cb(4) <= NN_2;
n_sro_cb(5) <= NN_2;
n_sro_cb(6) <= NN_2;
n_sro_cb(7) <= NN_2;
n_sro_scb(0) <= NN_2;
n_sro_scb(1) <= NN_2;
n_sro_scb(2) <= NN_2;
n_sro_scb(3) <= NN_2;
n_sro_scb(4) <= NN_2;
n_sro_scb(5) <= NN_2;
n_sro_scb(6) <= NN_2;
n_sro_scb(7) <= NN_2;
n_sro_vcdrive(0) <= NN_2;
n_sro_vcdrive(1) <= NN_2;
n_sro_vcdrive(2) <= NN_2;
n_sro_vcdrive(3) <= NN_2;
n_sro_vcdrive(4) <= NN_2;
n_sro_vcdrive(5) <= NN_2;
n_sro_vcdrive(6) <= NN_2;
n_sro_vcdrive(7) <= NN_2;
n_sro_svcdrive(0) <= NN_2;
n_sro_svcdrive(1) <= NN_2;
n_sro_svcdrive(2) <= NN_2;
n_sro_svcdrive(3) <= NN_2;
n_sro_svcdrive(4) <= NN_2;
n_sro_svcdrive(5) <= NN_2;
n_sro_svcdrive(6) <= NN_2;
n_sro_svcdrive(7) <= NN_2;
n_sro_ce <= NN_2;
end beh;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------
-- File : ../rtl/dummy_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from dummy_ctrl_regs_wb_slave.wb
-- Created : Fri May 13 11:28:38 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dummy_ctrl_regs_wb_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy_ctrl_regs_wb_slave is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Ports for PASS_THROUGH field: 'IRQ' in reg: 'DUMMY_1'
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_1_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Dummy register 2' in reg: 'DUMMY_2'
dummy_reg_2_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register 3' in reg: 'DUMMY_3'
dummy_reg_3_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Dummy register for LED control' in reg: 'DUMMY_LED'
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end dummy_ctrl_regs_wb_slave;
architecture syn of dummy_ctrl_regs_wb_slave is
signal dummy_reg_2_int : std_logic_vector(31 downto 0);
signal dummy_reg_3_int : std_logic_vector(31 downto 0);
signal dummy_reg_led_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dummy_reg_1_wr_o <= '0';
dummy_reg_2_int <= "00000000000000000000000000000000";
dummy_reg_3_int <= "00000000000000000000000000000000";
dummy_reg_led_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dummy_reg_1_wr_o <= '0';
ack_in_progress <= '0';
else
dummy_reg_1_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
dummy_reg_1_wr_o <= '1';
else
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
dummy_reg_2_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_2_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
dummy_reg_3_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_3_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
dummy_reg_led_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= dummy_reg_led_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- IRQ
-- pass-through field: IRQ in register: DUMMY_1
dummy_reg_1_o <= wrdata_reg(31 downto 0);
-- Dummy register 2
dummy_reg_2_o <= dummy_reg_2_int;
-- Dummy register 3
dummy_reg_3_o <= dummy_reg_3_int;
-- Dummy register for LED control
dummy_reg_led_o <= dummy_reg_led_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
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