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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2843.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity UNITS is
end UNITS;
ENTITY c13s09b00x00p99n01i02843ent IS
END c13s09b00x00p99n01i02843ent;
ARCHITECTURE c13s09b00x00p99n01i02843arch OF c13s09b00x00p99n01i02843ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02843 - Reserved word UNITS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02843arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2843.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity UNITS is
end UNITS;
ENTITY c13s09b00x00p99n01i02843ent IS
END c13s09b00x00p99n01i02843ent;
ARCHITECTURE c13s09b00x00p99n01i02843arch OF c13s09b00x00p99n01i02843ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02843 - Reserved word UNITS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02843arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2843.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity UNITS is
end UNITS;
ENTITY c13s09b00x00p99n01i02843ent IS
END c13s09b00x00p99n01i02843ent;
ARCHITECTURE c13s09b00x00p99n01i02843arch OF c13s09b00x00p99n01i02843ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02843 - Reserved word UNITS can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02843arch;
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
-- Company: Fachhochschule Dortmund
-- Engineer: Mysara Ibrahim
--
-- Create Date: 27/06/2017 10:20:32 AM
-- Design Name: Decoder for Convolutional Codes example project
-- Module Name: decoder - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity decoder is
port (EncIN : in std_logic_vector(n-1 downto 0);
Dec_clk : in std_logic;
DecOUT : out std_logic_vector(6 downto 0));
end decoder;
architecture Behavioral of decoder is
-- Signals declaration
signal clk : integer;
signal BmuAdder1, BmuAdder2, BmuAdder3, BmuAdder4 : integer;
signal BmuAdder5, BmuAdder6, BmuAdder7, BmuAdder8 : integer;
signal BmuAdder9, BmuAdder10, BmuAdder11, BmuAdder12 : integer;
signal BmuAdder13, BmuAdder14, BmuAdder15, BmuAdder16 : integer;
signal selectx1, selectx2, selectx3, selectx4 : bit;
signal selectx5, selectx6, selectx7, selectx8 : bit;
signal OUP1_1, OUP1_5, OUP5_3, OUP5_7, OUP3_2, OUP3_6, OUP7_4, OUP7_8 : integer;
signal OUP2_1, OUP2_5, OUP6_3, OUP6_7, OUP4_2, OUP4_6, OUP8_4, OUP8_8 : integer;
signal PMX1, PMX2, PMX3, PMX4, PMX5, PMX6, PMX7, PMX8 : integer;
signal path1, path2, path3, path4, path5, path6, path7, path8 : integer;
signal surv_path, index1 : integer;
-- Components declaration
component MyBMU
port (INP : in std_logic_vector (n-1 downto 0);
BMU_clk : in std_logic;
Index : out integer;
OUP1, OUP2, OUP3, OUP4, OUP5, OUP6, OUP7, OUP8, OUP9, OUP10,
OUP11, OUP12, OUP13, OUP14, OUP15, OUP16 : out integer := 0);
end component;
component MyADDER
port (INP1, INP2, INP3, INP4, INP5, INP6, INP7, INP8, INP9, INP10,
INP11, INP12, INP13, INP14, INP15, INP16 : in integer;
ADDer_clk : in std_logic;
ADDer_count : in integer;
OUP1_1, OUP1_5, OUP5_3, OUP5_7, OUP3_2, OUP3_6, OUP7_4, OUP7_8, OUP2_1,
OUP2_5, OUP6_3, OUP6_7, OUP4_2, OUP4_6, OUP8_4, OUP8_8 : out integer :=0);
end component;
component MyComparator
port (IN1 : in integer;
IN2 : in integer;
Bigger : out integer := 0;
Comp_clk : in std_logic;
Comp_count : in integer;
selectionIndex : out bit := '0');
end component;
component surviv_path
port (path1, path2, path3, path4, path5, path6, path7, path8 : in integer;
index : in integer;
surv_path : out integer := 0);
end component;
component MyTraceBack
port (index : in integer;
surv_path : in integer;
selectionIndex1, selectionIndex2, selectionIndex3, selectionIndex4 : in bit;
selectionIndex5, selectionIndex6, selectionIndex7, selectionIndex8 : in bit;
Decoded_out : out std_logic_vector(6 downto 0) := (others => '0'));
end component;
begin
MyBMU1 : MyBMU port map(EncIN, Dec_clk, index1,
BmuAdder1, BmuAdder2, BmuAdder3, BmuAdder4,
BmuAdder5, BmuAdder6, BmuAdder7, BmuAdder8,
BmuAdder9, BmuAdder10, BmuAdder11, BmuAdder12,
BmuAdder13, BmuAdder14, BmuAdder15, BmuAdder16);
MyADDER1 : MyADDER port map(BmuAdder1, BmuAdder2, BmuAdder3, BmuAdder4,
BmuAdder5, BmuAdder6, BmuAdder7, BmuAdder8,
BmuAdder9, BmuAdder10, BmuAdder11, BmuAdder12,
BmuAdder13, BmuAdder14, BmuAdder15, BmuAdder16,
Dec_clk, index1,
OUP1_1, OUP1_5, OUP5_3, OUP5_7, OUP3_2, OUP3_6, OUP7_4, OUP7_8,
OUP2_1, OUP2_5, OUP6_3, OUP6_7, OUP4_2, OUP4_6, OUP8_4, OUP8_8);
comp1 : MyComparator port map(OUP1_1, OUP2_1, PMX1, Dec_clk, index1, selectx1);
comp2 : MyComparator port map(OUP3_2, OUP4_2, PMX2, Dec_clk, index1, selectx2);
comp3 : MyComparator port map(OUP5_3, OUP6_3, PMX3, Dec_clk, index1, selectx3);
comp4 : MyComparator port map(OUP7_4, OUP8_4, PMX4, Dec_clk, index1, selectx4);
comp5 : MyComparator port map(OUP1_5, OUP2_5, PMX5, Dec_clk, index1, selectx5);
comp6 : MyComparator port map(OUP3_6, OUP4_6, PMX6, Dec_clk, index1, selectx6);
comp7 : MyComparator port map(OUP5_7, OUP6_7, PMX7, Dec_clk, index1, selectx7);
comp8 : MyComparator port map(OUP7_8, OUP8_8, PMX8, Dec_clk, index1, selectx8);
surv : surviv_path port map(PMX1, PMX2, PMX3, PMX4, PMX5, PMX6, PMX7, PMX8, index1, surv_path);
resultbts : MyTraceBack port map( index1, surv_path,
selectx1, selectx2, selectx3, selectx4,
selectx5, selectx6, selectx7, selectx8,
DecOUT);
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity MF_stratix_pll is
generic(
operation_mode : string := "normal";
qualify_conf_done: string := "off";
compensate_clock: string := "clk0";
pll_type : string := "auto";
scan_chain : string := "long";
clk0_multiply_by: integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift: integer := 0;
clk0_time_delay : integer := 0;
clk0_duty_cycle : integer := 50;
clk1_multiply_by: integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift: integer := 0;
clk1_time_delay : integer := 0;
clk1_duty_cycle : integer := 50;
clk2_multiply_by: integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift: integer := 0;
clk2_time_delay : integer := 0;
clk2_duty_cycle : integer := 50;
clk3_multiply_by: integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift: integer := 0;
clk3_time_delay : integer := 0;
clk3_duty_cycle : integer := 50;
clk4_multiply_by: integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift: integer := 0;
clk4_time_delay : integer := 0;
clk4_duty_cycle : integer := 50;
clk5_multiply_by: integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift: integer := 0;
clk5_time_delay : integer := 0;
clk5_duty_cycle : integer := 50;
extclk0_multiply_by: integer := 1;
extclk0_divide_by: integer := 1;
extclk0_phase_shift: integer := 0;
extclk0_time_delay: integer := 0;
extclk0_duty_cycle: integer := 50;
extclk1_multiply_by: integer := 1;
extclk1_divide_by: integer := 1;
extclk1_phase_shift: integer := 0;
extclk1_time_delay: integer := 0;
extclk1_duty_cycle: integer := 50;
extclk2_multiply_by: integer := 1;
extclk2_divide_by: integer := 1;
extclk2_phase_shift: integer := 0;
extclk2_time_delay: integer := 0;
extclk2_duty_cycle: integer := 50;
extclk3_multiply_by: integer := 1;
extclk3_divide_by: integer := 1;
extclk3_phase_shift: integer := 0;
extclk3_time_delay: integer := 0;
extclk3_duty_cycle: integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency: integer := 10000;
inclk1_input_frequency: integer := 10000;
gate_lock_signal: string := "no";
gate_lock_counter: integer := 1;
valid_lock_multiplier: integer := 5;
invalid_lock_multiplier: integer := 5;
switch_over_on_lossclk: string := "off";
switch_over_on_gated_lock: string := "off";
switch_over_counter: integer := 1;
enable_switch_over_counter: string := "off";
feedback_source : string := "extclk0";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
spread_frequency: integer := 0;
common_rx_tx : string := "off";
rx_outclock_resource: string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current: integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
pll_compensation_delay: integer := 0;
simulation_type : string := "timing";
down_spread : string := "0.0";
clk0_phase_shift_num: integer := 0;
clk1_phase_shift_num: integer := 0;
clk2_phase_shift_num: integer := 0;
family_name : string := "Stratix";
skip_vco : string := "off";
clk0_use_even_counter_mode: string := "off";
clk1_use_even_counter_mode: string := "off";
clk2_use_even_counter_mode: string := "off";
clk3_use_even_counter_mode: string := "off";
clk4_use_even_counter_mode: string := "off";
clk5_use_even_counter_mode: string := "off";
extclk0_use_even_counter_mode: string := "off";
extclk1_use_even_counter_mode: string := "off";
extclk2_use_even_counter_mode: string := "off";
extclk3_use_even_counter_mode: string := "off";
clk0_use_even_counter_value: string := "off";
clk1_use_even_counter_value: string := "off";
clk2_use_even_counter_value: string := "off";
clk3_use_even_counter_value: string := "off";
clk4_use_even_counter_value: string := "off";
clk5_use_even_counter_value: string := "off";
extclk0_use_even_counter_value: string := "off";
extclk1_use_even_counter_value: string := "off";
extclk2_use_even_counter_value: string := "off";
extclk3_use_even_counter_value: string := "off";
scan_chain_mif_file: string := "";
EGPP_SCAN_CHAIN : integer := 289;
GPP_SCAN_CHAIN : integer := 193;
TRST : integer := 5000;
TRSTCLK : integer := 5000
);
port(
inclk : in vl_logic_vector(1 downto 0);
fbin : in vl_logic;
ena : in vl_logic;
clkswitch : in vl_logic;
areset : in vl_logic;
pfdena : in vl_logic;
clkena : in vl_logic_vector(5 downto 0);
extclkena : in vl_logic_vector(3 downto 0);
scanclk : in vl_logic;
scanaclr : in vl_logic;
scandata : in vl_logic;
clk : out vl_logic_vector(5 downto 0);
extclk : out vl_logic_vector(3 downto 0);
clkbad : out vl_logic_vector(1 downto 0);
activeclock : out vl_logic;
locked : out vl_logic;
clkloss : out vl_logic;
scandataout : out vl_logic;
comparator : in vl_logic;
enable0 : out vl_logic;
enable1 : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of qualify_conf_done : constant is 1;
attribute mti_svvh_generic_type of compensate_clock : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of scan_chain : constant is 1;
attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk0_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk1_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk2_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk3_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk4_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk4_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk5_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk5_time_delay : constant is 1;
attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk0_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk1_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk2_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of extclk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of extclk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of extclk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of extclk3_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of primary_clock : constant is 1;
attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1;
attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1;
attribute mti_svvh_generic_type of gate_lock_signal : constant is 1;
attribute mti_svvh_generic_type of gate_lock_counter : constant is 1;
attribute mti_svvh_generic_type of valid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of invalid_lock_multiplier : constant is 1;
attribute mti_svvh_generic_type of switch_over_on_lossclk : constant is 1;
attribute mti_svvh_generic_type of switch_over_on_gated_lock : constant is 1;
attribute mti_svvh_generic_type of switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of feedback_source : constant is 1;
attribute mti_svvh_generic_type of bandwidth : constant is 1;
attribute mti_svvh_generic_type of bandwidth_type : constant is 1;
attribute mti_svvh_generic_type of spread_frequency : constant is 1;
attribute mti_svvh_generic_type of common_rx_tx : constant is 1;
attribute mti_svvh_generic_type of rx_outclock_resource : constant is 1;
attribute mti_svvh_generic_type of use_vco_bypass : constant is 1;
attribute mti_svvh_generic_type of use_dc_coupling : constant is 1;
attribute mti_svvh_generic_type of pfd_min : constant is 1;
attribute mti_svvh_generic_type of pfd_max : constant is 1;
attribute mti_svvh_generic_type of vco_min : constant is 1;
attribute mti_svvh_generic_type of vco_max : constant is 1;
attribute mti_svvh_generic_type of vco_center : constant is 1;
attribute mti_svvh_generic_type of m_initial : constant is 1;
attribute mti_svvh_generic_type of m : constant is 1;
attribute mti_svvh_generic_type of n : constant is 1;
attribute mti_svvh_generic_type of m2 : constant is 1;
attribute mti_svvh_generic_type of n2 : constant is 1;
attribute mti_svvh_generic_type of ss : constant is 1;
attribute mti_svvh_generic_type of l0_high : constant is 1;
attribute mti_svvh_generic_type of l0_low : constant is 1;
attribute mti_svvh_generic_type of l0_initial : constant is 1;
attribute mti_svvh_generic_type of l0_mode : constant is 1;
attribute mti_svvh_generic_type of l0_ph : constant is 1;
attribute mti_svvh_generic_type of l0_time_delay : constant is 1;
attribute mti_svvh_generic_type of l1_high : constant is 1;
attribute mti_svvh_generic_type of l1_low : constant is 1;
attribute mti_svvh_generic_type of l1_initial : constant is 1;
attribute mti_svvh_generic_type of l1_mode : constant is 1;
attribute mti_svvh_generic_type of l1_ph : constant is 1;
attribute mti_svvh_generic_type of l1_time_delay : constant is 1;
attribute mti_svvh_generic_type of g0_high : constant is 1;
attribute mti_svvh_generic_type of g0_low : constant is 1;
attribute mti_svvh_generic_type of g0_initial : constant is 1;
attribute mti_svvh_generic_type of g0_mode : constant is 1;
attribute mti_svvh_generic_type of g0_ph : constant is 1;
attribute mti_svvh_generic_type of g0_time_delay : constant is 1;
attribute mti_svvh_generic_type of g1_high : constant is 1;
attribute mti_svvh_generic_type of g1_low : constant is 1;
attribute mti_svvh_generic_type of g1_initial : constant is 1;
attribute mti_svvh_generic_type of g1_mode : constant is 1;
attribute mti_svvh_generic_type of g1_ph : constant is 1;
attribute mti_svvh_generic_type of g1_time_delay : constant is 1;
attribute mti_svvh_generic_type of g2_high : constant is 1;
attribute mti_svvh_generic_type of g2_low : constant is 1;
attribute mti_svvh_generic_type of g2_initial : constant is 1;
attribute mti_svvh_generic_type of g2_mode : constant is 1;
attribute mti_svvh_generic_type of g2_ph : constant is 1;
attribute mti_svvh_generic_type of g2_time_delay : constant is 1;
attribute mti_svvh_generic_type of g3_high : constant is 1;
attribute mti_svvh_generic_type of g3_low : constant is 1;
attribute mti_svvh_generic_type of g3_initial : constant is 1;
attribute mti_svvh_generic_type of g3_mode : constant is 1;
attribute mti_svvh_generic_type of g3_ph : constant is 1;
attribute mti_svvh_generic_type of g3_time_delay : constant is 1;
attribute mti_svvh_generic_type of e0_high : constant is 1;
attribute mti_svvh_generic_type of e0_low : constant is 1;
attribute mti_svvh_generic_type of e0_initial : constant is 1;
attribute mti_svvh_generic_type of e0_mode : constant is 1;
attribute mti_svvh_generic_type of e0_ph : constant is 1;
attribute mti_svvh_generic_type of e0_time_delay : constant is 1;
attribute mti_svvh_generic_type of e1_high : constant is 1;
attribute mti_svvh_generic_type of e1_low : constant is 1;
attribute mti_svvh_generic_type of e1_initial : constant is 1;
attribute mti_svvh_generic_type of e1_mode : constant is 1;
attribute mti_svvh_generic_type of e1_ph : constant is 1;
attribute mti_svvh_generic_type of e1_time_delay : constant is 1;
attribute mti_svvh_generic_type of e2_high : constant is 1;
attribute mti_svvh_generic_type of e2_low : constant is 1;
attribute mti_svvh_generic_type of e2_initial : constant is 1;
attribute mti_svvh_generic_type of e2_mode : constant is 1;
attribute mti_svvh_generic_type of e2_ph : constant is 1;
attribute mti_svvh_generic_type of e2_time_delay : constant is 1;
attribute mti_svvh_generic_type of e3_high : constant is 1;
attribute mti_svvh_generic_type of e3_low : constant is 1;
attribute mti_svvh_generic_type of e3_initial : constant is 1;
attribute mti_svvh_generic_type of e3_mode : constant is 1;
attribute mti_svvh_generic_type of e3_ph : constant is 1;
attribute mti_svvh_generic_type of e3_time_delay : constant is 1;
attribute mti_svvh_generic_type of m_ph : constant is 1;
attribute mti_svvh_generic_type of m_time_delay : constant is 1;
attribute mti_svvh_generic_type of n_time_delay : constant is 1;
attribute mti_svvh_generic_type of extclk0_counter : constant is 1;
attribute mti_svvh_generic_type of extclk1_counter : constant is 1;
attribute mti_svvh_generic_type of extclk2_counter : constant is 1;
attribute mti_svvh_generic_type of extclk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk0_counter : constant is 1;
attribute mti_svvh_generic_type of clk1_counter : constant is 1;
attribute mti_svvh_generic_type of clk2_counter : constant is 1;
attribute mti_svvh_generic_type of clk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk4_counter : constant is 1;
attribute mti_svvh_generic_type of clk5_counter : constant is 1;
attribute mti_svvh_generic_type of enable0_counter : constant is 1;
attribute mti_svvh_generic_type of enable1_counter : constant is 1;
attribute mti_svvh_generic_type of charge_pump_current : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c : constant is 1;
attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1;
attribute mti_svvh_generic_type of simulation_type : constant is 1;
attribute mti_svvh_generic_type of down_spread : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of family_name : constant is 1;
attribute mti_svvh_generic_type of skip_vco : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of extclk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of extclk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1;
attribute mti_svvh_generic_type of EGPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of TRST : constant is 1;
attribute mti_svvh_generic_type of TRSTCLK : constant is 1;
end MF_stratix_pll;
|
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_palette.vhd,v 1.10 2016/11/09 10:47:01 fbelavenuto Exp $
--
-- Palette
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vdp18_palette is
port (
reset_i : in boolean;
clock_i : in std_logic;
we_i : in std_logic;
addr_wr_i : in std_logic_vector(0 to 3);
data_i : in std_logic_vector(0 to 15);
addr_rd_i : in std_logic_vector(0 to 3);
data_o : out std_logic_vector(0 to 15)
);
end entity;
architecture Memory of vdp18_palette is
type ram_t is array (natural range 15 downto 0) of std_logic_vector(15 downto 0);
signal ram_q : ram_t;
signal read_addr_q : unsigned(3 downto 0);
begin
process (reset_i, clock_i)
begin
if reset_i then
ram_q <= (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
elsif rising_edge(clock_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_wr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_rd_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end architecture; |
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 :INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:10 10/29/2009
-- Design Name:
-- Module Name: m_calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity m_calc is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector (15 downto 0);
t : in std_logic_vector (15 downto 0);
n_cons : in std_logic_vector (15 downto 0);
m : out std_logic_vector (15 downto 0);
mult_valid : in std_logic; -- indica que los datos de entrada son validos
m_valid : out std_logic); -- la m calculada es valida
end m_calc;
architecture Behavioral of m_calc is
signal sum_res, next_sum_res : std_logic_vector(15 downto 0);
signal mult_valid_1, mult_valid_2 : std_logic; --delay del valido a lo largo del calculo
signal mult : std_logic_vector(31 downto 0);
begin
mult <= sum_res * n_cons;
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1') then
sum_res <= (others => '0');
mult_valid_1 <= '0';
mult_valid_2 <= '0';
else
sum_res <= next_sum_res;
mult_valid_1 <= mult_valid;
mult_valid_2 <= mult_valid_1;
end if;
end if;
end process;
process(ab, t, mult_valid_2)
begin
m <= mult(15 downto 0);
next_sum_res <= ab+t;
m_valid <= mult_valid_2;
end process;
end Behavioral;
|
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity cache is
port
(
CLK : in std_logic;
AI : in std_logic_vector(5 downto 0);
DI : in std_logic_vector(31 downto 0);
WE : in std_logic := '1';
AO : in std_logic_vector(5 downto 0);
DO : out std_logic_vector(31 downto 0);
CACHE : in std_logic
);
end cache;
architecture rtl of cache is
signal CACHE_ACTIVE : std_logic := '0';
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to 127) of word_t;
shared variable ram : memory_t;
begin
process(CLK)
begin
if rising_edge(CLK) then
if CACHE = '1' then
CACHE_ACTIVE <= not CACHE_ACTIVE;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
ram(to_integer(unsigned(CACHE_ACTIVE & AI))) := DI;
end if;
end if;
end process;
process(CLK)
begin
if rising_edge(CLK) then
DO <= ram(to_integer(unsigned(not CACHE_ACTIVE & AO)));
end if;
end process;
end rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOF.VHD ***
--*** ***
--*** Function: Cast Long to IEEE754 Single ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltof IS
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castltof;
ARCHITECTURE rtl OF hcc_castltof IS
signal fit : STD_LOGIC;
signal xvector : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
xvector(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
xvector(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
core: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>'0',aazip=>'0',
cc=>cc);
END rtl;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerArray is array (0 to 9) of integer;
variable myArray : integerArray;
begin -- process p
for i in myArray'range loop
myArray(i) := i;
end loop; -- i
for i in myArray'range loop
assert myArray(i) = i report "TEST FAILED myArray(i) = " &
integer'image(myArray(i)) & " - was supposed to be " &
integer'image(i) severity FAILURE;
end loop; -- i
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerArray is array (0 to 9) of integer;
variable myArray : integerArray;
begin -- process p
for i in myArray'range loop
myArray(i) := i;
end loop; -- i
for i in myArray'range loop
assert myArray(i) = i report "TEST FAILED myArray(i) = " &
integer'image(myArray(i)) & " - was supposed to be " &
integer'image(i) severity FAILURE;
end loop; -- i
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
p: process
type integerArray is array (0 to 9) of integer;
variable myArray : integerArray;
begin -- process p
for i in myArray'range loop
myArray(i) := i;
end loop; -- i
for i in myArray'range loop
assert myArray(i) = i report "TEST FAILED myArray(i) = " &
integer'image(myArray(i)) & " - was supposed to be " &
integer'image(i) severity FAILURE;
end loop; -- i
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity attr16 is
end entity;
architecture test of attr16 is
type int_vec_2d is array (natural range <>, natural range <>) of integer;
signal s1, s2 : integer_vector(1 to 5) := (others => 0);
signal s3, s4 : int_vec_2d(1 to 2, 5 to 5) := (others => (others => 0));
begin
check: process is
begin
assert s1'range(1)'low = 1;
assert s1'range(1)'right = 5;
assert s3'range(1)'left = 1;
assert s3'range(2)'left = 5;
assert s3'range(2)'right = 5;
wait;
end process;
end architecture;
|
entity \t\\est\ is end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit_mb
-- File: greth_gbit_mb.vhd
-- Author: Marko Isomaki
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and dual AHB master interfaces
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
gmiimode : integer range 0 to 1 := 0;
mdiochain : integer range 0 to 1 := 0; -- Not supported: Leave at zero
iotest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type;
mdchain_ui : in greth_mdiochain_down_type; -- Set to greth_mdiochain_down_first
mdchain_uo : out greth_mdiochain_up_type; -- Leave open
mdchain_di : out greth_mdiochain_down_type; -- Leave open
mdchain_do : in greth_mdiochain_up_type -- Assign to greth_mdiochain_up_last
);
end entity;
architecture rtl of greth_gbit_mb is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal ehwdata : std_logic_vector(31 downto 0);
signal ehrdata : std_logic_vector(31 downto 0);
signal mdio_o,mdio_oe : std_ulogic;
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
gmiimode => gmiimode,
mdiochain => mdiochain,
iotest => iotest
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi2.hgrant(ehindex),
ehready => ahbmi2.hready,
ehresp => ahbmi2.hresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ahbmo2.hbusreq,
ehlock => ahbmo2.hlock,
ehtrans => ahbmo2.htrans,
ehaddr => ahbmo2.haddr,
ehwrite => ahbmo2.hwrite,
ehsize => ahbmo2.hsize,
ehburst => ahbmo2.hburst,
ehprot => ahbmo2.hprot,
ehwdata => ehwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => ethi.gtx_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd,
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd,
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
--cfg
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable,
speed => etho.speed,
gbit => etho.gbit,
-- mdio sharing
mdiochain_first => mdchain_ui.first,
mdiochain_ticki => mdchain_ui.tick,
mdiochain_datai => mdchain_ui.mdio_i,
mdiochain_locko => mdchain_uo.lock,
mdiochain_ticko => mdchain_di.tick,
mdiochain_i => mdchain_di.mdio_i,
mdiochain_locki => mdchain_do.lock,
mdiochain_o => mdchain_do.mdio_o,
mdiochain_oe => mdchain_do.mdio_oe
);
etho.tx_clk <= '0'; -- driven in rgmii component
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
ehrdata <= ahbreadword(ahbmi2.hrdata);
ahbmo2.hwdata <= ahbdrivedata(ehwdata);
ahbmo2.hconfig <= ehconfig;
ahbmo2.hindex <= ehindex;
ahbmo2.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
etho.mdio_o <= mdio_o;
etho.mdio_oe <= mdio_oe;
mdchain_di.first <= '0';
mdchain_uo.mdio_o <= mdio_o;
mdchain_uo.mdio_oe <= mdio_oe;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen, custombits => memtest_vlen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, ahbmi.testin
);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, testen => scanen, custombits => memtest_vlen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, ahbmi.testin
);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft, testen => scanen, custombits => memtest_vlen)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata, open, ahbmi.testin
);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft, testen => scanen, custombits => memtest_vlen)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata, open, ahbmi.testin
);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen, 0, memtest_vlen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), ahbmi.testin
);
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, scanen, 0, memtest_vlen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), ahbmi.testin
);
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft, scanen, 0, memtest_vlen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16), open, ahbmi.testin
);
r1 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft, scanen, 0, memtest_vlen) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0), open, ahbmi.testin
);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100/1000 Mbit Ethernet MAC rev " &
tost(REVISION) & tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz*edcl) & " kbyte " & tost(fifosize) & " txfifo, " &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic ( MultiplierIsShiftAdd: boolean:=true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc: std_logic;
constant c_trigger: std_logic:='0';
begin
--Control logic of the multiplication algorithm
ShiftAdd: if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER,sr_recalc,r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2*BIT_WIDTH-1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B,RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <='0';
elsif rising_edge(clk) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1';-- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(clk) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
P_Multiply: process(TRIGGER,A,B)
variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
variable v_en: std_logic:='0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic ( MultiplierIsShiftAdd: boolean:=true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc: std_logic;
constant c_trigger: std_logic:='0';
begin
--Control logic of the multiplication algorithm
ShiftAdd: if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER,sr_recalc,r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2*BIT_WIDTH-1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B,RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <='0';
elsif rising_edge(clk) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1';-- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(clk) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
P_Multiply: process(TRIGGER,A,B)
variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
variable v_en: std_logic:='0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic ( MultiplierIsShiftAdd: boolean:=true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc: std_logic;
constant c_trigger: std_logic:='0';
begin
--Control logic of the multiplication algorithm
ShiftAdd: if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER,sr_recalc,r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2*BIT_WIDTH-1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B,RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <='0';
elsif rising_edge(clk) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1';-- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(clk) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
P_Multiply: process(TRIGGER,A,B)
variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
variable v_en: std_logic:='0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic ( MultiplierIsShiftAdd: boolean:=true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc: std_logic;
constant c_trigger: std_logic:='0';
begin
--Control logic of the multiplication algorithm
ShiftAdd: if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER,sr_recalc,r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2*BIT_WIDTH-1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B,RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <='0';
elsif rising_edge(clk) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1';-- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(clk) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
P_Multiply: process(TRIGGER,A,B)
variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
variable v_en: std_logic:='0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:17:25 02/11/2015
-- Design Name:
-- Module Name: aaatop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
-- LED example, by Jerome Cornet
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Aaatop is
Port (
CLK,reset : in STD_LOGIC;
tx : inout std_logic;
rx : in std_logic;
ARDUINO_RESET : out STD_LOGIC;
DUO_SW1 : in STD_LOGIC;
-- DUO_LED : out std_logic;
sram_addr : out std_logic_vector(20 downto 0);
sram_data : inout std_logic_vector(7 downto 0);
sram_ce : out std_logic;
sram_we : out std_logic;
sram_oe : out std_logic;
SD_MISO : in std_logic;
SD_MOSI : out std_logic;
SD_SCK : out std_logic;
SD_nCS : out std_logic;
SW_LEFT : in STD_LOGIC;
SW_UP : in STD_LOGIC;
SW_DOWN : in STD_LOGIC;
SW_RIGHT : in STD_LOGIC;
LED1 : inout STD_LOGIC;
LED2 : inout STD_LOGIC;
LED3 : inout STD_LOGIC;
LED4 : inout STD_LOGIC;
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC;
VGA_BLUE : out std_logic_vector(3 downto 0);
VGA_GREEN : out std_logic_vector(3 downto 0);
VGA_RED : out std_logic_vector(3 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (21 downto 0)
-- Arduino : inout STD_LOGIC_VECTOR (53 downto 0)
);
end Aaatop;
architecture Behavioral of Aaatop is
signal CLOCK_40MHZ : std_logic;
signal CTS : std_logic := '1';
signal PIN3 : std_logic;
signal LED1P : std_logic;
signal LED2N : std_logic;
signal LED3N : std_logic;
signal PIN4 : std_logic;
signal RTS : std_logic;
signal vramaddr : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal vramdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal clock, video_on, pixel_tick: std_logic;
signal rgb_reg, rgb_next: std_logic_vector(2 downto 0);
signal hsync, vsync: std_logic;
signal rgb: std_logic_vector(2 downto 0);
signal buttons: std_logic_vector(3 downto 0);
signal leds: std_logic_vector(3 downto 0);
begin
CTS <= '1';
-- PIN3 <= not Arduino(40); -- por
-- PIN3 <= reset; -- por
PIN3 <= '1'; -- por
-- Arduino(38) <= Arduino(40);
-- Arduino(42) <= Arduino(44);
-- Arduino(46) <= Arduino(48);
-- Arduino(50) <= Arduino(52);
-- Arduino(38) <= LED1;
-- Arduino(42) <= LED2N;
-- Arduino(46) <= LED3N;
-- Arduino(50) <= '0';
-- sram_addr <= (others => '0');
-- sram_ce <= '0';
-- sram_we <= '0';
-- sram_oe <= '0';
drigmorn1_top0: ENTITY work.drigmorn1_top
PORT map(
sram_addr => sram_addr,
sram_data => sram_data,
sram_ce => sram_ce,
sram_we => sram_we,
sram_oe => sram_oe,
vramaddr => vramaddr,
vramdata => vramdata,
spi_cs => SD_nCS,
spi_clk => SD_SCK,
spi_mosi => SD_MOSI,
spi_miso => SD_MISO,
buttons => buttons,
leds => leds,
CLOCK_40MHZ => CLOCK_40MHZ,
CTS => CTS,
PIN3 => PIN3,
RXD => RX,
LED1 => LED1P,
LED2N => LED2N,
LED3N => LED3N,
PIN4 => PIN4,
RTS => RTS,
TXD => TX
);
dcm0: entity work.clk32to40
port map
(-- Clock in ports
CLK_IN1 => clk,
-- Clock out ports
CLK_OUT1 => CLOCK_40MHZ,
CLK_OUT2 => clock
);
-- VGA signals
vga_sync_unit: entity work.vga_sync
port map(
clock => clock,
reset => reset,
hsync => hsync,
vsync => vsync,
video_on => video_on,
pixel_tick => pixel_tick,
pixel_x => pixel_x,
pixel_y => pixel_y
);
-- font generator
font_gen_unit: entity work.font_generator
port map(
clock => pixel_tick,
vramaddr => vramaddr,
vramdata => vramdata,
video_on => video_on,
pixel_x => pixel_x,
pixel_y => pixel_y,
rgb_text => rgb_next
);
ARDUINO_RESET <= not(DUO_SW1);
buttons <= sw_left & sw_right & sw_up & sw_down;
led1 <= leds(0);
led2 <= leds(1);
led3 <= leds(2);
led4 <= leds(3);
-- rgb buffer
process(clock)
begin
if clock'event and clock = '1' then
if pixel_tick = '1' then
rgb_reg <= rgb_next;
end if;
end if;
end process;
rgb <= rgb_reg;
vga_hsync <= hsync;
vga_vsync <= vsync;
vga_blue <= (others => rgb(0));--blue
vga_green <= (others => rgb(1));--green
vga_red <= (others => rgb(2));--red
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity flip_flop_jk is
port( J,K: in std_logic := '1';
Reset: in std_logic := '0';
Clock_enable: in std_logic := '1';
Clock: in std_logic;
Output: out std_logic);
end flip_flop_jk;
architecture Behavioral of flip_flop_jk is
signal temp: std_logic;
begin
process (Clock)
begin
if rising_edge(Clock) then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral; |
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of MAX6682_tb is
for behavior
for DUT : MAX6682
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:25:06 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_g8_0_0 -prefix
-- system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0_rgb888_to_g8 is
port (
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb888_to_g8_0_0_rgb888_to_g8;
architecture STRUCTURE of system_rgb888_to_g8_0_0_rgb888_to_g8 is
signal \_carry__0_i_1_n_0\ : STD_LOGIC;
signal \_carry__0_i_2_n_0\ : STD_LOGIC;
signal \_carry__0_i_3_n_0\ : STD_LOGIC;
signal \_carry__0_i_4_n_0\ : STD_LOGIC;
signal \_carry__0_n_0\ : STD_LOGIC;
signal \_carry__0_n_1\ : STD_LOGIC;
signal \_carry__0_n_2\ : STD_LOGIC;
signal \_carry__0_n_3\ : STD_LOGIC;
signal \_carry__1_i_1_n_0\ : STD_LOGIC;
signal \_carry__1_n_2\ : STD_LOGIC;
signal \_carry_i_1_n_0\ : STD_LOGIC;
signal \_carry_i_2_n_0\ : STD_LOGIC;
signal \_carry_i_3_n_0\ : STD_LOGIC;
signal \_carry_i_4_n_0\ : STD_LOGIC;
signal \_carry_i_5_n_0\ : STD_LOGIC;
signal \_carry_n_0\ : STD_LOGIC;
signal \_carry_n_1\ : STD_LOGIC;
signal \_carry_n_2\ : STD_LOGIC;
signal \_carry_n_3\ : STD_LOGIC;
signal g810_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g81__120_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_0\ : STD_LOGIC;
signal \g81__120_carry__0_n_1\ : STD_LOGIC;
signal \g81__120_carry__0_n_2\ : STD_LOGIC;
signal \g81__120_carry__0_n_3\ : STD_LOGIC;
signal \g81__120_carry__0_n_4\ : STD_LOGIC;
signal \g81__120_carry__0_n_5\ : STD_LOGIC;
signal \g81__120_carry__0_n_6\ : STD_LOGIC;
signal \g81__120_carry__0_n_7\ : STD_LOGIC;
signal \g81__120_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_0\ : STD_LOGIC;
signal \g81__120_carry__1_n_1\ : STD_LOGIC;
signal \g81__120_carry__1_n_2\ : STD_LOGIC;
signal \g81__120_carry__1_n_3\ : STD_LOGIC;
signal \g81__120_carry__1_n_4\ : STD_LOGIC;
signal \g81__120_carry__1_n_5\ : STD_LOGIC;
signal \g81__120_carry__1_n_6\ : STD_LOGIC;
signal \g81__120_carry__1_n_7\ : STD_LOGIC;
signal \g81__120_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry__2_n_1\ : STD_LOGIC;
signal \g81__120_carry__2_n_3\ : STD_LOGIC;
signal \g81__120_carry__2_n_6\ : STD_LOGIC;
signal \g81__120_carry__2_n_7\ : STD_LOGIC;
signal \g81__120_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__120_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_0\ : STD_LOGIC;
signal \g81__120_carry_n_1\ : STD_LOGIC;
signal \g81__120_carry_n_2\ : STD_LOGIC;
signal \g81__120_carry_n_3\ : STD_LOGIC;
signal \g81__120_carry_n_4\ : STD_LOGIC;
signal \g81__120_carry_n_5\ : STD_LOGIC;
signal \g81__120_carry_n_6\ : STD_LOGIC;
signal \g81__149_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_0\ : STD_LOGIC;
signal \g81__149_carry__0_n_1\ : STD_LOGIC;
signal \g81__149_carry__0_n_2\ : STD_LOGIC;
signal \g81__149_carry__0_n_3\ : STD_LOGIC;
signal \g81__149_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_0\ : STD_LOGIC;
signal \g81__149_carry__1_n_1\ : STD_LOGIC;
signal \g81__149_carry__1_n_2\ : STD_LOGIC;
signal \g81__149_carry__1_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_0\ : STD_LOGIC;
signal \g81__149_carry__2_n_1\ : STD_LOGIC;
signal \g81__149_carry__2_n_2\ : STD_LOGIC;
signal \g81__149_carry__2_n_3\ : STD_LOGIC;
signal \g81__149_carry__2_n_4\ : STD_LOGIC;
signal \g81__149_carry__2_n_5\ : STD_LOGIC;
signal \g81__149_carry__2_n_6\ : STD_LOGIC;
signal \g81__149_carry__2_n_7\ : STD_LOGIC;
signal \g81__149_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_0\ : STD_LOGIC;
signal \g81__149_carry__3_n_1\ : STD_LOGIC;
signal \g81__149_carry__3_n_2\ : STD_LOGIC;
signal \g81__149_carry__3_n_3\ : STD_LOGIC;
signal \g81__149_carry__3_n_4\ : STD_LOGIC;
signal \g81__149_carry__3_n_5\ : STD_LOGIC;
signal \g81__149_carry__3_n_6\ : STD_LOGIC;
signal \g81__149_carry__3_n_7\ : STD_LOGIC;
signal \g81__149_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_0\ : STD_LOGIC;
signal \g81__149_carry__4_n_2\ : STD_LOGIC;
signal \g81__149_carry__4_n_3\ : STD_LOGIC;
signal \g81__149_carry__4_n_5\ : STD_LOGIC;
signal \g81__149_carry__4_n_6\ : STD_LOGIC;
signal \g81__149_carry__4_n_7\ : STD_LOGIC;
signal \g81__149_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__149_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_0\ : STD_LOGIC;
signal \g81__149_carry_n_1\ : STD_LOGIC;
signal \g81__149_carry_n_2\ : STD_LOGIC;
signal \g81__149_carry_n_3\ : STD_LOGIC;
signal \g81__206_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_0\ : STD_LOGIC;
signal \g81__206_carry__0_n_1\ : STD_LOGIC;
signal \g81__206_carry__0_n_2\ : STD_LOGIC;
signal \g81__206_carry__0_n_3\ : STD_LOGIC;
signal \g81__206_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_0\ : STD_LOGIC;
signal \g81__206_carry__1_n_1\ : STD_LOGIC;
signal \g81__206_carry__1_n_2\ : STD_LOGIC;
signal \g81__206_carry__1_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_0\ : STD_LOGIC;
signal \g81__206_carry__2_n_1\ : STD_LOGIC;
signal \g81__206_carry__2_n_2\ : STD_LOGIC;
signal \g81__206_carry__2_n_3\ : STD_LOGIC;
signal \g81__206_carry__2_n_4\ : STD_LOGIC;
signal \g81__206_carry__2_n_5\ : STD_LOGIC;
signal \g81__206_carry__2_n_6\ : STD_LOGIC;
signal \g81__206_carry__2_n_7\ : STD_LOGIC;
signal \g81__206_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_0\ : STD_LOGIC;
signal \g81__206_carry__3_n_1\ : STD_LOGIC;
signal \g81__206_carry__3_n_2\ : STD_LOGIC;
signal \g81__206_carry__3_n_3\ : STD_LOGIC;
signal \g81__206_carry__3_n_4\ : STD_LOGIC;
signal \g81__206_carry__3_n_5\ : STD_LOGIC;
signal \g81__206_carry__3_n_6\ : STD_LOGIC;
signal \g81__206_carry__3_n_7\ : STD_LOGIC;
signal \g81__206_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_0\ : STD_LOGIC;
signal \g81__206_carry__4_n_2\ : STD_LOGIC;
signal \g81__206_carry__4_n_3\ : STD_LOGIC;
signal \g81__206_carry__4_n_5\ : STD_LOGIC;
signal \g81__206_carry__4_n_6\ : STD_LOGIC;
signal \g81__206_carry__4_n_7\ : STD_LOGIC;
signal \g81__206_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__206_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_0\ : STD_LOGIC;
signal \g81__206_carry_n_1\ : STD_LOGIC;
signal \g81__206_carry_n_2\ : STD_LOGIC;
signal \g81__206_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_0\ : STD_LOGIC;
signal \g81__22_carry__0_n_1\ : STD_LOGIC;
signal \g81__22_carry__0_n_2\ : STD_LOGIC;
signal \g81__22_carry__0_n_3\ : STD_LOGIC;
signal \g81__22_carry__0_n_4\ : STD_LOGIC;
signal \g81__22_carry__0_n_5\ : STD_LOGIC;
signal \g81__22_carry__0_n_6\ : STD_LOGIC;
signal \g81__22_carry__0_n_7\ : STD_LOGIC;
signal \g81__22_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_0\ : STD_LOGIC;
signal \g81__22_carry__1_n_1\ : STD_LOGIC;
signal \g81__22_carry__1_n_2\ : STD_LOGIC;
signal \g81__22_carry__1_n_3\ : STD_LOGIC;
signal \g81__22_carry__1_n_4\ : STD_LOGIC;
signal \g81__22_carry__1_n_5\ : STD_LOGIC;
signal \g81__22_carry__1_n_6\ : STD_LOGIC;
signal \g81__22_carry__1_n_7\ : STD_LOGIC;
signal \g81__22_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry__2_n_1\ : STD_LOGIC;
signal \g81__22_carry__2_n_3\ : STD_LOGIC;
signal \g81__22_carry__2_n_6\ : STD_LOGIC;
signal \g81__22_carry__2_n_7\ : STD_LOGIC;
signal \g81__22_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__22_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_0\ : STD_LOGIC;
signal \g81__22_carry_n_1\ : STD_LOGIC;
signal \g81__22_carry_n_2\ : STD_LOGIC;
signal \g81__22_carry_n_3\ : STD_LOGIC;
signal \g81__22_carry_n_4\ : STD_LOGIC;
signal \g81__22_carry_n_5\ : STD_LOGIC;
signal \g81__22_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_0\ : STD_LOGIC;
signal \g81__261_carry__0_n_1\ : STD_LOGIC;
signal \g81__261_carry__0_n_2\ : STD_LOGIC;
signal \g81__261_carry__0_n_3\ : STD_LOGIC;
signal \g81__261_carry__0_n_4\ : STD_LOGIC;
signal \g81__261_carry__0_n_5\ : STD_LOGIC;
signal \g81__261_carry__0_n_6\ : STD_LOGIC;
signal \g81__261_carry__0_n_7\ : STD_LOGIC;
signal \g81__261_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_0\ : STD_LOGIC;
signal \g81__261_carry__1_n_1\ : STD_LOGIC;
signal \g81__261_carry__1_n_2\ : STD_LOGIC;
signal \g81__261_carry__1_n_3\ : STD_LOGIC;
signal \g81__261_carry__1_n_4\ : STD_LOGIC;
signal \g81__261_carry__1_n_5\ : STD_LOGIC;
signal \g81__261_carry__1_n_6\ : STD_LOGIC;
signal \g81__261_carry__1_n_7\ : STD_LOGIC;
signal \g81__261_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry__2_n_1\ : STD_LOGIC;
signal \g81__261_carry__2_n_3\ : STD_LOGIC;
signal \g81__261_carry__2_n_6\ : STD_LOGIC;
signal \g81__261_carry__2_n_7\ : STD_LOGIC;
signal \g81__261_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__261_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_0\ : STD_LOGIC;
signal \g81__261_carry_n_1\ : STD_LOGIC;
signal \g81__261_carry_n_2\ : STD_LOGIC;
signal \g81__261_carry_n_3\ : STD_LOGIC;
signal \g81__261_carry_n_4\ : STD_LOGIC;
signal \g81__261_carry_n_5\ : STD_LOGIC;
signal \g81__261_carry_n_6\ : STD_LOGIC;
signal \g81__261_carry_n_7\ : STD_LOGIC;
signal \g81__301_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_0\ : STD_LOGIC;
signal \g81__301_carry__0_n_1\ : STD_LOGIC;
signal \g81__301_carry__0_n_2\ : STD_LOGIC;
signal \g81__301_carry__0_n_3\ : STD_LOGIC;
signal \g81__301_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_0\ : STD_LOGIC;
signal \g81__301_carry__1_n_1\ : STD_LOGIC;
signal \g81__301_carry__1_n_2\ : STD_LOGIC;
signal \g81__301_carry__1_n_3\ : STD_LOGIC;
signal \g81__301_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_0\ : STD_LOGIC;
signal \g81__301_carry__2_n_1\ : STD_LOGIC;
signal \g81__301_carry__2_n_2\ : STD_LOGIC;
signal \g81__301_carry__2_n_3\ : STD_LOGIC;
signal \g81__301_carry__3_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_0\ : STD_LOGIC;
signal \g81__301_carry__3_n_1\ : STD_LOGIC;
signal \g81__301_carry__3_n_2\ : STD_LOGIC;
signal \g81__301_carry__3_n_3\ : STD_LOGIC;
signal \g81__301_carry__4_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_0\ : STD_LOGIC;
signal \g81__301_carry__4_n_1\ : STD_LOGIC;
signal \g81__301_carry__4_n_2\ : STD_LOGIC;
signal \g81__301_carry__4_n_3\ : STD_LOGIC;
signal \g81__301_carry__5_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_i_8_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_0\ : STD_LOGIC;
signal \g81__301_carry__5_n_1\ : STD_LOGIC;
signal \g81__301_carry__5_n_2\ : STD_LOGIC;
signal \g81__301_carry__5_n_3\ : STD_LOGIC;
signal \g81__301_carry__6_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry__6_n_1\ : STD_LOGIC;
signal \g81__301_carry__6_n_2\ : STD_LOGIC;
signal \g81__301_carry__6_n_3\ : STD_LOGIC;
signal \g81__301_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__301_carry_i_7_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_0\ : STD_LOGIC;
signal \g81__301_carry_n_1\ : STD_LOGIC;
signal \g81__301_carry_n_2\ : STD_LOGIC;
signal \g81__301_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry__0_n_1\ : STD_LOGIC;
signal \g81__347_carry__0_n_2\ : STD_LOGIC;
signal \g81__347_carry__0_n_3\ : STD_LOGIC;
signal \g81__347_carry__0_n_4\ : STD_LOGIC;
signal \g81__347_carry__0_n_5\ : STD_LOGIC;
signal \g81__347_carry__0_n_6\ : STD_LOGIC;
signal \g81__347_carry__0_n_7\ : STD_LOGIC;
signal \g81__347_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__347_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_0\ : STD_LOGIC;
signal \g81__347_carry_n_1\ : STD_LOGIC;
signal \g81__347_carry_n_2\ : STD_LOGIC;
signal \g81__347_carry_n_3\ : STD_LOGIC;
signal \g81__347_carry_n_4\ : STD_LOGIC;
signal \g81__347_carry_n_5\ : STD_LOGIC;
signal \g81__347_carry_n_6\ : STD_LOGIC;
signal \g81__347_carry_n_7\ : STD_LOGIC;
signal \g81__53_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_0\ : STD_LOGIC;
signal \g81__53_carry__0_n_1\ : STD_LOGIC;
signal \g81__53_carry__0_n_2\ : STD_LOGIC;
signal \g81__53_carry__0_n_3\ : STD_LOGIC;
signal \g81__53_carry__0_n_4\ : STD_LOGIC;
signal \g81__53_carry__0_n_5\ : STD_LOGIC;
signal \g81__53_carry__0_n_6\ : STD_LOGIC;
signal \g81__53_carry__0_n_7\ : STD_LOGIC;
signal \g81__53_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_0\ : STD_LOGIC;
signal \g81__53_carry__1_n_1\ : STD_LOGIC;
signal \g81__53_carry__1_n_2\ : STD_LOGIC;
signal \g81__53_carry__1_n_3\ : STD_LOGIC;
signal \g81__53_carry__1_n_4\ : STD_LOGIC;
signal \g81__53_carry__1_n_5\ : STD_LOGIC;
signal \g81__53_carry__1_n_6\ : STD_LOGIC;
signal \g81__53_carry__1_n_7\ : STD_LOGIC;
signal \g81__53_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry__2_n_1\ : STD_LOGIC;
signal \g81__53_carry__2_n_3\ : STD_LOGIC;
signal \g81__53_carry__2_n_6\ : STD_LOGIC;
signal \g81__53_carry__2_n_7\ : STD_LOGIC;
signal \g81__53_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__53_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_0\ : STD_LOGIC;
signal \g81__53_carry_n_1\ : STD_LOGIC;
signal \g81__53_carry_n_2\ : STD_LOGIC;
signal \g81__53_carry_n_3\ : STD_LOGIC;
signal \g81__53_carry_n_4\ : STD_LOGIC;
signal \g81__53_carry_n_5\ : STD_LOGIC;
signal \g81__53_carry_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_0\ : STD_LOGIC;
signal \g81__92_carry__0_n_1\ : STD_LOGIC;
signal \g81__92_carry__0_n_2\ : STD_LOGIC;
signal \g81__92_carry__0_n_3\ : STD_LOGIC;
signal \g81__92_carry__0_n_4\ : STD_LOGIC;
signal \g81__92_carry__0_n_5\ : STD_LOGIC;
signal \g81__92_carry__0_n_6\ : STD_LOGIC;
signal \g81__92_carry__0_n_7\ : STD_LOGIC;
signal \g81__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_0\ : STD_LOGIC;
signal \g81__92_carry__1_n_1\ : STD_LOGIC;
signal \g81__92_carry__1_n_2\ : STD_LOGIC;
signal \g81__92_carry__1_n_3\ : STD_LOGIC;
signal \g81__92_carry__1_n_4\ : STD_LOGIC;
signal \g81__92_carry__1_n_5\ : STD_LOGIC;
signal \g81__92_carry__1_n_6\ : STD_LOGIC;
signal \g81__92_carry__1_n_7\ : STD_LOGIC;
signal \g81__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry__2_n_1\ : STD_LOGIC;
signal \g81__92_carry__2_n_3\ : STD_LOGIC;
signal \g81__92_carry__2_n_6\ : STD_LOGIC;
signal \g81__92_carry__2_n_7\ : STD_LOGIC;
signal \g81__92_carry_i_1_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_2_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_3_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_4_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_5_n_0\ : STD_LOGIC;
signal \g81__92_carry_i_6_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_0\ : STD_LOGIC;
signal \g81__92_carry_n_1\ : STD_LOGIC;
signal \g81__92_carry_n_2\ : STD_LOGIC;
signal \g81__92_carry_n_3\ : STD_LOGIC;
signal \g81__92_carry_n_4\ : STD_LOGIC;
signal \g81__92_carry_n_5\ : STD_LOGIC;
signal \g81__92_carry_n_6\ : STD_LOGIC;
signal \g81_carry__0_i_10_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_11_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_12_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_13_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_14_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_15_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__0_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_0\ : STD_LOGIC;
signal \g81_carry__0_n_1\ : STD_LOGIC;
signal \g81_carry__0_n_2\ : STD_LOGIC;
signal \g81_carry__0_n_3\ : STD_LOGIC;
signal \g81_carry__0_n_4\ : STD_LOGIC;
signal \g81_carry__0_n_5\ : STD_LOGIC;
signal \g81_carry__0_n_6\ : STD_LOGIC;
signal \g81_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_4_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_5_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_6_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_7_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_8_n_0\ : STD_LOGIC;
signal \g81_carry__1_i_9_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_0\ : STD_LOGIC;
signal \g81_carry__1_n_1\ : STD_LOGIC;
signal \g81_carry__1_n_2\ : STD_LOGIC;
signal \g81_carry__1_n_3\ : STD_LOGIC;
signal \g81_carry__1_n_4\ : STD_LOGIC;
signal \g81_carry__1_n_5\ : STD_LOGIC;
signal \g81_carry__1_n_6\ : STD_LOGIC;
signal \g81_carry__1_n_7\ : STD_LOGIC;
signal \g81_carry__2_i_1_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_2_n_0\ : STD_LOGIC;
signal \g81_carry__2_i_3_n_0\ : STD_LOGIC;
signal \g81_carry__2_n_1\ : STD_LOGIC;
signal \g81_carry__2_n_3\ : STD_LOGIC;
signal \g81_carry__2_n_6\ : STD_LOGIC;
signal \g81_carry__2_n_7\ : STD_LOGIC;
signal g81_carry_i_1_n_0 : STD_LOGIC;
signal g81_carry_i_2_n_0 : STD_LOGIC;
signal g81_carry_i_3_n_0 : STD_LOGIC;
signal g81_carry_i_4_n_0 : STD_LOGIC;
signal g81_carry_i_5_n_0 : STD_LOGIC;
signal g81_carry_i_6_n_0 : STD_LOGIC;
signal g81_carry_i_7_n_0 : STD_LOGIC;
signal g81_carry_n_0 : STD_LOGIC;
signal g81_carry_n_1 : STD_LOGIC;
signal g81_carry_n_2 : STD_LOGIC;
signal g81_carry_n_3 : STD_LOGIC;
signal g81_carry_n_7 : STD_LOGIC;
signal g83 : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \g83__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_0\ : STD_LOGIC;
signal \g83__0_carry__0_n_1\ : STD_LOGIC;
signal \g83__0_carry__0_n_2\ : STD_LOGIC;
signal \g83__0_carry__0_n_3\ : STD_LOGIC;
signal \g83__0_carry__0_n_4\ : STD_LOGIC;
signal \g83__0_carry__0_n_5\ : STD_LOGIC;
signal \g83__0_carry__0_n_6\ : STD_LOGIC;
signal \g83__0_carry__0_n_7\ : STD_LOGIC;
signal \g83__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry__1_n_2\ : STD_LOGIC;
signal \g83__0_carry__1_n_7\ : STD_LOGIC;
signal \g83__0_carry_i_1_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_2_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_3_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_4_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_5_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_6_n_0\ : STD_LOGIC;
signal \g83__0_carry_i_7_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_0\ : STD_LOGIC;
signal \g83__0_carry_n_1\ : STD_LOGIC;
signal \g83__0_carry_n_2\ : STD_LOGIC;
signal \g83__0_carry_n_3\ : STD_LOGIC;
signal \g83__0_carry_n_4\ : STD_LOGIC;
signal \g83__0_carry_n_5\ : STD_LOGIC;
signal \g83__0_carry_n_6\ : STD_LOGIC;
signal \g83__0_carry_n_7\ : STD_LOGIC;
signal g84 : STD_LOGIC;
signal \g84_carry__0_i_1_n_0\ : STD_LOGIC;
signal \g84_carry__0_i_2_n_0\ : STD_LOGIC;
signal g84_carry_i_1_n_0 : STD_LOGIC;
signal g84_carry_i_2_n_0 : STD_LOGIC;
signal g84_carry_i_3_n_0 : STD_LOGIC;
signal g84_carry_i_4_n_0 : STD_LOGIC;
signal g84_carry_i_5_n_0 : STD_LOGIC;
signal g84_carry_i_6_n_0 : STD_LOGIC;
signal g84_carry_i_7_n_0 : STD_LOGIC;
signal g84_carry_i_8_n_0 : STD_LOGIC;
signal g84_carry_n_0 : STD_LOGIC;
signal g84_carry_n_1 : STD_LOGIC;
signal g84_carry_n_2 : STD_LOGIC;
signal g84_carry_n_3 : STD_LOGIC;
signal \NLW__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__120_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__120_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__149_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__149_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__149_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__206_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__206_carry__4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_g81__206_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__22_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__22_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__22_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__261_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__261_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__301_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__301_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__301_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g81__347_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_g81__53_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__53_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__53_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g81__92_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81__92_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_g81_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_g81_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g81_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_g83__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g83__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_g84_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_g84_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_g84_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute HLUTNM : string;
attribute HLUTNM of \g81__120_carry__1_i_1\ : label is "lutpair7";
attribute HLUTNM of \g81__149_carry__0_i_1\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_2\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__0_i_5\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__0_i_6\ : label is "lutpair8";
attribute HLUTNM of \g81__149_carry__0_i_7\ : label is "lutpair27";
attribute HLUTNM of \g81__149_carry__1_i_1\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_2\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_3\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__1_i_4\ : label is "lutpair9";
attribute HLUTNM of \g81__149_carry__1_i_5\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__1_i_6\ : label is "lutpair12";
attribute HLUTNM of \g81__149_carry__1_i_7\ : label is "lutpair11";
attribute HLUTNM of \g81__149_carry__1_i_8\ : label is "lutpair10";
attribute HLUTNM of \g81__149_carry__2_i_1\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_2\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_3\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__2_i_4\ : label is "lutpair13";
attribute HLUTNM of \g81__149_carry__2_i_5\ : label is "lutpair17";
attribute HLUTNM of \g81__149_carry__2_i_6\ : label is "lutpair16";
attribute HLUTNM of \g81__149_carry__2_i_7\ : label is "lutpair15";
attribute HLUTNM of \g81__149_carry__2_i_8\ : label is "lutpair14";
attribute HLUTNM of \g81__149_carry__3_i_1\ : label is "lutpair17";
attribute HLUTNM of \g81__206_carry__0_i_1\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_2\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__0_i_5\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__0_i_6\ : label is "lutpair18";
attribute HLUTNM of \g81__206_carry__0_i_7\ : label is "lutpair28";
attribute HLUTNM of \g81__206_carry__1_i_1\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_2\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_3\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__1_i_4\ : label is "lutpair19";
attribute HLUTNM of \g81__206_carry__1_i_5\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__1_i_6\ : label is "lutpair22";
attribute HLUTNM of \g81__206_carry__1_i_7\ : label is "lutpair21";
attribute HLUTNM of \g81__206_carry__1_i_8\ : label is "lutpair20";
attribute HLUTNM of \g81__206_carry__2_i_1\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__2_i_4\ : label is "lutpair23";
attribute HLUTNM of \g81__206_carry__2_i_6\ : label is "lutpair29";
attribute HLUTNM of \g81__206_carry__3_i_1\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_3\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__3_i_6\ : label is "lutpair25";
attribute HLUTNM of \g81__206_carry__3_i_8\ : label is "lutpair24";
attribute HLUTNM of \g81__206_carry__4_i_2\ : label is "lutpair26";
attribute HLUTNM of \g81__206_carry__4_i_6\ : label is "lutpair26";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \g81_carry__0_i_10\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_11\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \g81_carry__0_i_12\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \g81_carry__0_i_13\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_14\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \g81_carry__0_i_15\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__0_i_9\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \g81_carry__1_i_9\ : label is "soft_lutpair3";
attribute HLUTNM of \g81_carry__2_i_2\ : label is "lutpair7";
attribute HLUTNM of \g83__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \g83__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \g83__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \g83__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \g83__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \g83__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \g83__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \g83__0_carry_i_7\ : label is "lutpair0";
begin
\_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \_carry_n_0\,
CO(2) => \_carry_n_1\,
CO(1) => \_carry_n_2\,
CO(0) => \_carry_n_3\,
CYINIT => \_carry_i_1_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(4 downto 1),
S(3) => \_carry_i_2_n_0\,
S(2) => \_carry_i_3_n_0\,
S(1) => \_carry_i_4_n_0\,
S(0) => \_carry_i_5_n_0\
);
\_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \_carry_n_0\,
CO(3) => \_carry__0_n_0\,
CO(2) => \_carry__0_n_1\,
CO(1) => \_carry__0_n_2\,
CO(0) => \_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => g83(8 downto 5),
S(3) => \_carry__0_i_1_n_0\,
S(2) => \_carry__0_i_2_n_0\,
S(1) => \_carry__0_i_3_n_0\,
S(0) => \_carry__0_i_4_n_0\
);
\_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
O => \_carry__0_i_1_n_0\
);
\_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_4\,
O => \_carry__0_i_2_n_0\
);
\_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
O => \_carry__0_i_3_n_0\
);
\_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_6\,
O => \_carry__0_i_4_n_0\
);
\_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \_carry__0_n_0\,
CO(3 downto 2) => \NLW__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \_carry__1_n_2\,
CO(0) => \NLW__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => g83(9),
S(3 downto 1) => B"001",
S(0) => \_carry__1_i_1_n_0\
);
\_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_2\,
O => \_carry__1_i_1_n_0\
);
\_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
O => \_carry_i_1_n_0\
);
\_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
O => \_carry_i_2_n_0\
);
\_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_4\,
O => \_carry_i_3_n_0\
);
\_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
O => \_carry_i_4_n_0\
);
\_carry_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_6\,
O => \_carry_i_5_n_0\
);
\g81__120_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__120_carry_n_0\,
CO(2) => \g81__120_carry_n_1\,
CO(1) => \g81__120_carry_n_2\,
CO(0) => \g81__120_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__120_carry_i_1_n_0\,
DI(1) => \g81__120_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__120_carry_n_4\,
O(2) => \g81__120_carry_n_5\,
O(1) => \g81__120_carry_n_6\,
O(0) => \NLW_g81__120_carry_O_UNCONNECTED\(0),
S(3) => \g81__120_carry_i_3_n_0\,
S(2) => \g81__120_carry_i_4_n_0\,
S(1) => \g81__120_carry_i_5_n_0\,
S(0) => \g81__120_carry_i_6_n_0\
);
\g81__120_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry_n_0\,
CO(3) => \g81__120_carry__0_n_0\,
CO(2) => \g81__120_carry__0_n_1\,
CO(1) => \g81__120_carry__0_n_2\,
CO(0) => \g81__120_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__120_carry__0_n_4\,
O(2) => \g81__120_carry__0_n_5\,
O(1) => \g81__120_carry__0_n_6\,
O(0) => \g81__120_carry__0_n_7\,
S(3) => \g81__120_carry__0_i_1_n_0\,
S(2) => \g81__120_carry__0_i_2_n_0\,
S(1) => \g81__120_carry__0_i_3_n_0\,
S(0) => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__120_carry__0_i_1_n_0\
);
\g81__120_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__120_carry__0_i_2_n_0\
);
\g81__120_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__120_carry__0_i_3_n_0\
);
\g81__120_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__120_carry__0_i_4_n_0\
);
\g81__120_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__0_n_0\,
CO(3) => \g81__120_carry__1_n_0\,
CO(2) => \g81__120_carry__1_n_1\,
CO(1) => \g81__120_carry__1_n_2\,
CO(0) => \g81__120_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__120_carry__1_n_4\,
O(2) => \g81__120_carry__1_n_5\,
O(1) => \g81__120_carry__1_n_6\,
O(0) => \g81__120_carry__1_n_7\,
S(3) => \g81__120_carry__1_i_1_n_0\,
S(2) => \g81__120_carry__1_i_2_n_0\,
S(1) => \g81__120_carry__1_i_3_n_0\,
S(0) => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"369C"
)
port map (
I0 => g84,
I1 => \g81_carry__1_i_1_n_0\,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__120_carry__1_i_1_n_0\
);
\g81__120_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_2_n_0\
);
\g81__120_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__120_carry__1_i_3_n_0\
);
\g81__120_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__120_carry__1_i_4_n_0\
);
\g81__120_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__120_carry__1_n_0\,
CO(3) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__120_carry__2_n_1\,
CO(1) => \NLW_g81__120_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__120_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__120_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__120_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__120_carry__2_n_6\,
O(0) => \g81__120_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__120_carry__2_i_1_n_0\
);
\g81__120_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__120_carry__2_i_2_n_0\
);
\g81__120_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__120_carry_i_1_n_0\
);
\g81__120_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__120_carry_i_2_n_0\
);
\g81__120_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__120_carry_i_3_n_0\
);
\g81__120_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__120_carry_i_4_n_0\
);
\g81__120_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__120_carry_i_5_n_0\
);
\g81__120_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__120_carry_i_6_n_0\
);
\g81__149_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__149_carry_n_0\,
CO(2) => \g81__149_carry_n_1\,
CO(1) => \g81__149_carry_n_2\,
CO(0) => \g81__149_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry_i_1_n_0\,
DI(2) => \g81__149_carry_i_2_n_0\,
DI(1) => \g81__149_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__149_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry_i_4_n_0\,
S(2) => \g81__149_carry_i_5_n_0\,
S(1) => \g81__149_carry_i_6_n_0\,
S(0) => \g81__149_carry_i_7_n_0\
);
\g81__149_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry_n_0\,
CO(3) => \g81__149_carry__0_n_0\,
CO(2) => \g81__149_carry__0_n_1\,
CO(1) => \g81__149_carry__0_n_2\,
CO(0) => \g81__149_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__0_i_1_n_0\,
DI(2) => \g81__149_carry__0_i_2_n_0\,
DI(1) => \g81__149_carry__0_i_3_n_0\,
DI(0) => \g81__149_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__0_i_5_n_0\,
S(2) => \g81__149_carry__0_i_6_n_0\,
S(1) => \g81__149_carry__0_i_7_n_0\,
S(0) => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
O => \g81__149_carry__0_i_1_n_0\
);
\g81__149_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
O => \g81__149_carry__0_i_2_n_0\
);
\g81__149_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_6\,
I1 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_3_n_0\
);
\g81__149_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
O => \g81__149_carry__0_i_4_n_0\
);
\g81__149_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
I3 => \g81__149_carry__0_i_1_n_0\,
O => \g81__149_carry__0_i_5_n_0\
);
\g81__149_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__22_carry__0_n_6\,
I2 => \g81_carry__1_n_4\,
I3 => \g81__149_carry__0_i_2_n_0\,
O => \g81__149_carry__0_i_6_n_0\
);
\g81__149_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__22_carry__0_n_7\,
I1 => \g81_carry__1_n_5\,
I2 => \g81_carry__1_n_6\,
I3 => \g81__22_carry_n_4\,
O => \g81__149_carry__0_i_7_n_0\
);
\g81__149_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__1_n_7\,
I1 => \g81__22_carry_n_5\,
I2 => \g81__22_carry_n_4\,
I3 => \g81_carry__1_n_6\,
O => \g81__149_carry__0_i_8_n_0\
);
\g81__149_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__0_n_0\,
CO(3) => \g81__149_carry__1_n_0\,
CO(2) => \g81__149_carry__1_n_1\,
CO(1) => \g81__149_carry__1_n_2\,
CO(0) => \g81__149_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__1_i_1_n_0\,
DI(2) => \g81__149_carry__1_i_2_n_0\,
DI(1) => \g81__149_carry__1_i_3_n_0\,
DI(0) => \g81__149_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__149_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__149_carry__1_i_5_n_0\,
S(2) => \g81__149_carry__1_i_6_n_0\,
S(1) => \g81__149_carry__1_i_7_n_0\,
S(0) => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__1_i_1_n_0\
);
\g81__149_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
O => \g81__149_carry__1_i_2_n_0\
);
\g81__149_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
O => \g81__149_carry__1_i_3_n_0\
);
\g81__149_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__22_carry__0_n_5\,
I2 => \g81_carry__2_n_7\,
O => \g81__149_carry__1_i_4_n_0\
);
\g81__149_carry__1_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_1_n_0\,
O => \g81__149_carry__1_i_5_n_0\
);
\g81__149_carry__1_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry_n_4\,
I1 => \g81__22_carry__1_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__1_i_2_n_0\,
O => \g81__149_carry__1_i_6_n_0\
);
\g81__149_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_5\,
I1 => \g81__22_carry__1_n_7\,
I2 => \g81_carry__2_n_1\,
I3 => \g81__149_carry__1_i_3_n_0\,
O => \g81__149_carry__1_i_7_n_0\
);
\g81__149_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__53_carry_n_6\,
I1 => \g81__22_carry__0_n_4\,
I2 => \g81_carry__2_n_6\,
I3 => \g81__149_carry__1_i_4_n_0\,
O => \g81__149_carry__1_i_8_n_0\
);
\g81__149_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__1_n_0\,
CO(3) => \g81__149_carry__2_n_0\,
CO(2) => \g81__149_carry__2_n_1\,
CO(1) => \g81__149_carry__2_n_2\,
CO(0) => \g81__149_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__149_carry__2_i_1_n_0\,
DI(2) => \g81__149_carry__2_i_2_n_0\,
DI(1) => \g81__149_carry__2_i_3_n_0\,
DI(0) => \g81__149_carry__2_i_4_n_0\,
O(3) => \g81__149_carry__2_n_4\,
O(2) => \g81__149_carry__2_n_5\,
O(1) => \g81__149_carry__2_n_6\,
O(0) => \g81__149_carry__2_n_7\,
S(3) => \g81__149_carry__2_i_5_n_0\,
S(2) => \g81__149_carry__2_i_6_n_0\,
S(1) => \g81__149_carry__2_i_7_n_0\,
S(0) => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_1_n_0\
);
\g81__149_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_2_n_0\
);
\g81__149_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_3_n_0\
);
\g81__149_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__0_n_7\,
I1 => \g81__22_carry__1_n_5\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__2_i_4_n_0\
);
\g81__149_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_1_n_0\,
O => \g81__149_carry__2_i_5_n_0\
);
\g81__149_carry__2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_4\,
I1 => \g81__22_carry__2_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_2_n_0\,
O => \g81__149_carry__2_i_6_n_0\
);
\g81__149_carry__2_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_5\,
I1 => \g81__22_carry__2_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_3_n_0\,
O => \g81__149_carry__2_i_7_n_0\
);
\g81__149_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__53_carry__0_n_6\,
I1 => \g81__22_carry__1_n_4\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__149_carry__2_i_4_n_0\,
O => \g81__149_carry__2_i_8_n_0\
);
\g81__149_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__2_n_0\,
CO(3) => \g81__149_carry__3_n_0\,
CO(2) => \g81__149_carry__3_n_1\,
CO(1) => \g81__149_carry__3_n_2\,
CO(0) => \g81__149_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__2_i_2_n_0\,
DI(2) => \g81_carry__2_i_2_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81__149_carry__3_i_1_n_0\,
O(3) => \g81__149_carry__3_n_4\,
O(2) => \g81__149_carry__3_n_5\,
O(1) => \g81__149_carry__3_n_6\,
O(0) => \g81__149_carry__3_n_7\,
S(3) => \g81__149_carry__3_i_2_n_0\,
S(2) => \g81__149_carry__3_i_3_n_0\,
S(1) => \g81__149_carry__3_i_4_n_0\,
S(0) => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__3_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"888E"
)
port map (
I0 => \g81__53_carry__1_n_7\,
I1 => \g81__22_carry__2_n_1\,
I2 => \_carry__1_n_2\,
I3 => g84,
O => \g81__149_carry__3_i_1_n_0\
);
\g81__149_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_7\,
O => \g81__149_carry__3_i_2_n_0\
);
\g81__149_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_4\,
O => \g81__149_carry__3_i_3_n_0\
);
\g81__149_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__1_n_5\,
O => \g81__149_carry__3_i_4_n_0\
);
\g81__149_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__149_carry__3_i_1_n_0\,
I1 => \g81__53_carry__1_n_6\,
O => \g81__149_carry__3_i_5_n_0\
);
\g81__149_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__149_carry__3_n_0\,
CO(3) => \g81__149_carry__4_n_0\,
CO(2) => \NLW_g81__149_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__149_carry__4_n_2\,
CO(0) => \g81__149_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__149_carry__4_i_1_n_0\,
DI(1) => \g81_carry__2_i_2_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3) => \NLW_g81__149_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__149_carry__4_n_5\,
O(1) => \g81__149_carry__4_n_6\,
O(0) => \g81__149_carry__4_n_7\,
S(3 downto 2) => B"10",
S(1) => \g81__149_carry__4_i_2_n_0\,
S(0) => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__149_carry__4_i_1_n_0\
);
\g81__149_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_1\,
O => \g81__149_carry__4_i_2_n_0\
);
\g81__149_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => \g81__53_carry__2_n_6\,
O => \g81__149_carry__4_i_3_n_0\
);
\g81__149_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
O => \g81__149_carry_i_1_n_0\
);
\g81__149_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
O => \g81__149_carry_i_2_n_0\
);
\g81__149_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_3_n_0\
);
\g81__149_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_4\,
I1 => \g81__22_carry_n_6\,
I2 => \g81__22_carry_n_5\,
I3 => \g81_carry__1_n_7\,
O => \g81__149_carry_i_4_n_0\
);
\g81__149_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_5\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__22_carry_n_6\,
I3 => \g81_carry__0_n_4\,
O => \g81__149_carry_i_5_n_0\
);
\g81__149_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g81_carry__0_n_5\,
O => \g81__149_carry_i_6_n_0\
);
\g81__149_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81_carry__0_n_6\,
I1 => \g83__0_carry_n_7\,
O => \g81__149_carry_i_7_n_0\
);
\g81__206_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__206_carry_n_0\,
CO(2) => \g81__206_carry_n_1\,
CO(1) => \g81__206_carry_n_2\,
CO(0) => \g81__206_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry_i_1_n_0\,
DI(2) => \g81__206_carry_i_2_n_0\,
DI(1) => \g81__206_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__206_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry_i_4_n_0\,
S(2) => \g81__206_carry_i_5_n_0\,
S(1) => \g81__206_carry_i_6_n_0\,
S(0) => \g81__206_carry_i_7_n_0\
);
\g81__206_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry_n_0\,
CO(3) => \g81__206_carry__0_n_0\,
CO(2) => \g81__206_carry__0_n_1\,
CO(1) => \g81__206_carry__0_n_2\,
CO(0) => \g81__206_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__0_i_1_n_0\,
DI(2) => \g81__206_carry__0_i_2_n_0\,
DI(1) => \g81__206_carry__0_i_3_n_0\,
DI(0) => \g81__206_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__0_i_5_n_0\,
S(2) => \g81__206_carry__0_i_6_n_0\,
S(1) => \g81__206_carry__0_i_7_n_0\,
S(0) => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
O => \g81__206_carry__0_i_1_n_0\
);
\g81__206_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
O => \g81__206_carry__0_i_2_n_0\
);
\g81__206_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_4\,
I1 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_3_n_0\
);
\g81__206_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
O => \g81__206_carry__0_i_4_n_0\
);
\g81__206_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
I3 => \g81__206_carry__0_i_1_n_0\,
O => \g81__206_carry__0_i_5_n_0\
);
\g81__206_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__3_n_5\,
I1 => \g83__0_carry_n_7\,
I2 => \g81__92_carry__0_n_6\,
I3 => \g81__206_carry__0_i_2_n_0\,
O => \g81__206_carry__0_i_6_n_0\
);
\g81__206_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__149_carry__3_n_6\,
I1 => \g81__92_carry__0_n_7\,
I2 => \g81__92_carry_n_4\,
I3 => \g81__149_carry__3_n_7\,
O => \g81__206_carry__0_i_7_n_0\
);
\g81__206_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_5\,
I1 => \g81__149_carry__2_n_4\,
I2 => \g81__149_carry__3_n_7\,
I3 => \g81__92_carry_n_4\,
O => \g81__206_carry__0_i_8_n_0\
);
\g81__206_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__0_n_0\,
CO(3) => \g81__206_carry__1_n_0\,
CO(2) => \g81__206_carry__1_n_1\,
CO(1) => \g81__206_carry__1_n_2\,
CO(0) => \g81__206_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__1_i_1_n_0\,
DI(2) => \g81__206_carry__1_i_2_n_0\,
DI(1) => \g81__206_carry__1_i_3_n_0\,
DI(0) => \g81__206_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__206_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__206_carry__1_i_5_n_0\,
S(2) => \g81__206_carry__1_i_6_n_0\,
S(1) => \g81__206_carry__1_i_7_n_0\,
S(0) => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
O => \g81__206_carry__1_i_1_n_0\
);
\g81__206_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
O => \g81__206_carry__1_i_2_n_0\
);
\g81__206_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
O => \g81__206_carry__1_i_3_n_0\
);
\g81__206_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__3_n_4\,
I1 => \g81_carry__0_i_11_n_0\,
I2 => \g81__92_carry__0_n_5\,
O => \g81__206_carry__1_i_4_n_0\
);
\g81__206_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
I3 => \g81__206_carry__1_i_1_n_0\,
O => \g81__206_carry__1_i_5_n_0\
);
\g81__206_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_5\,
I1 => \g81__120_carry_n_4\,
I2 => \g81__92_carry__1_n_6\,
I3 => \g81__206_carry__1_i_2_n_0\,
O => \g81__206_carry__1_i_6_n_0\
);
\g81__206_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_6\,
I1 => \g81__120_carry_n_5\,
I2 => \g81__92_carry__1_n_7\,
I3 => \g81__206_carry__1_i_3_n_0\,
O => \g81__206_carry__1_i_7_n_0\
);
\g81__206_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g81__149_carry__4_n_7\,
I1 => \g81__120_carry_n_6\,
I2 => \g81__92_carry__0_n_4\,
I3 => \g81__206_carry__1_i_4_n_0\,
O => \g81__206_carry__1_i_8_n_0\
);
\g81__206_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__1_n_0\,
CO(3) => \g81__206_carry__2_n_0\,
CO(2) => \g81__206_carry__2_n_1\,
CO(1) => \g81__206_carry__2_n_2\,
CO(0) => \g81__206_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_i_1_n_0\,
DI(2) => \g81__206_carry__2_i_2_n_0\,
DI(1) => \g81__206_carry__2_i_3_n_0\,
DI(0) => \g81__206_carry__2_i_4_n_0\,
O(3) => \g81__206_carry__2_n_4\,
O(2) => \g81__206_carry__2_n_5\,
O(1) => \g81__206_carry__2_n_6\,
O(0) => \g81__206_carry__2_n_7\,
S(3) => \g81__206_carry__2_i_5_n_0\,
S(2) => \g81__206_carry__2_i_6_n_0\,
S(1) => \g81__206_carry__2_i_7_n_0\,
S(0) => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
O => \g81__206_carry__2_i_1_n_0\
);
\g81__206_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry__2_n_7\,
I1 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_2_n_0\
);
\g81__206_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__0_n_6\,
I3 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_3_n_0\
);
\g81__206_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \g81__149_carry__4_n_0\,
I1 => \g81__120_carry__0_n_7\,
I2 => \g81__92_carry__1_n_5\,
O => \g81__206_carry__2_i_4_n_0\
);
\g81__206_carry__2_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_1_n_0\,
I1 => \g81__120_carry__1_n_7\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__2_i_5_n_0\
);
\g81__206_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"9666"
)
port map (
I0 => \g81__120_carry__0_n_4\,
I1 => \g81__92_carry__2_n_6\,
I2 => \g81__92_carry__2_n_7\,
I3 => \g81__120_carry__0_n_5\,
O => \g81__206_carry__2_i_6_n_0\
);
\g81__206_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"888E77717771888E"
)
port map (
I0 => \g81__92_carry__1_n_4\,
I1 => \g81__120_carry__0_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
I4 => \g81__120_carry__0_n_5\,
I5 => \g81__92_carry__2_n_7\,
O => \g81__206_carry__2_i_7_n_0\
);
\g81__206_carry__2_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"99966669"
)
port map (
I0 => \g81__206_carry__2_i_4_n_0\,
I1 => \g81__120_carry__0_n_6\,
I2 => \_carry__1_n_2\,
I3 => g84,
I4 => \g81__92_carry__1_n_4\,
O => \g81__206_carry__2_i_8_n_0\
);
\g81__206_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__2_n_0\,
CO(3) => \g81__206_carry__3_n_0\,
CO(2) => \g81__206_carry__3_n_1\,
CO(1) => \g81__206_carry__3_n_2\,
CO(0) => \g81__206_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_i_1_n_0\,
DI(2) => \g81__206_carry__3_i_2_n_0\,
DI(1) => \g81__206_carry__3_i_3_n_0\,
DI(0) => \g81__206_carry__3_i_4_n_0\,
O(3) => \g81__206_carry__3_n_4\,
O(2) => \g81__206_carry__3_n_5\,
O(1) => \g81__206_carry__3_n_6\,
O(0) => \g81__206_carry__3_n_7\,
S(3) => \g81__206_carry__3_i_5_n_0\,
S(2) => \g81__206_carry__3_i_6_n_0\,
S(1) => \g81__206_carry__3_i_7_n_0\,
S(0) => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_1_n_0\
);
\g81__206_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__3_i_2_n_0\
);
\g81__206_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__3_i_3_n_0\
);
\g81__206_carry__3_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F110"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__120_carry__1_n_7\,
I3 => \g81__92_carry__2_n_1\,
O => \g81__206_carry__3_i_4_n_0\
);
\g81__206_carry__3_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_1_n_0\,
I1 => \g81__120_carry__2_n_7\,
O => \g81__206_carry__3_i_5_n_0\
);
\g81__206_carry__3_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__1_n_4\,
O => \g81__206_carry__3_i_6_n_0\
);
\g81__206_carry__3_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__3_i_3_n_0\,
I1 => \g81__120_carry__1_n_5\,
O => \g81__206_carry__3_i_7_n_0\
);
\g81__206_carry__3_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"56AAAAA9"
)
port map (
I0 => \g81__120_carry__1_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
I3 => \g81__92_carry__2_n_1\,
I4 => \g81__120_carry__1_n_7\,
O => \g81__206_carry__3_i_8_n_0\
);
\g81__206_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__206_carry__3_n_0\,
CO(3) => \g81__206_carry__4_n_0\,
CO(2) => \NLW_g81__206_carry__4_CO_UNCONNECTED\(2),
CO(1) => \g81__206_carry__4_n_2\,
CO(0) => \g81__206_carry__4_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__206_carry__4_i_1_n_0\,
DI(1) => \g81__206_carry__4_i_2_n_0\,
DI(0) => \g81__206_carry__4_i_3_n_0\,
O(3) => \NLW_g81__206_carry__4_O_UNCONNECTED\(3),
O(2) => \g81__206_carry__4_n_5\,
O(1) => \g81__206_carry__4_n_6\,
O(0) => \g81__206_carry__4_n_7\,
S(3) => '1',
S(2) => \g81__206_carry__4_i_4_n_0\,
S(1) => \g81__206_carry__4_i_5_n_0\,
S(0) => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_1_n_0\
);
\g81__206_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \g81__120_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__206_carry__4_i_2_n_0\
);
\g81__206_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_3_n_0\
);
\g81__206_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
O => \g81__206_carry__4_i_4_n_0\
);
\g81__206_carry__4_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g81__206_carry__4_i_2_n_0\,
I1 => \g81__120_carry__2_n_1\,
O => \g81__206_carry__4_i_5_n_0\
);
\g81__206_carry__4_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__120_carry__2_n_6\,
O => \g81__206_carry__4_i_6_n_0\
);
\g81__206_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
O => \g81__206_carry_i_1_n_0\
);
\g81__206_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
O => \g81__206_carry_i_2_n_0\
);
\g81__206_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_3_n_0\
);
\g81__206_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g81__92_carry_n_6\,
I1 => \g81__149_carry__2_n_5\,
I2 => \g81__149_carry__2_n_4\,
I3 => \g81__92_carry_n_5\,
O => \g81__206_carry_i_4_n_0\
);
\g81__206_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => g81_carry_n_7,
I1 => \g81__149_carry__2_n_6\,
I2 => \g81__149_carry__2_n_5\,
I3 => \g81__92_carry_n_6\,
O => \g81__206_carry_i_5_n_0\
);
\g81__206_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
I2 => \g81__149_carry__2_n_6\,
I3 => g81_carry_n_7,
O => \g81__206_carry_i_6_n_0\
);
\g81__206_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__149_carry__2_n_7\,
O => \g81__206_carry_i_7_n_0\
);
\g81__22_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__22_carry_n_0\,
CO(2) => \g81__22_carry_n_1\,
CO(1) => \g81__22_carry_n_2\,
CO(0) => \g81__22_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__22_carry_i_1_n_0\,
DI(1) => \g81__22_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__22_carry_n_4\,
O(2) => \g81__22_carry_n_5\,
O(1) => \g81__22_carry_n_6\,
O(0) => \NLW_g81__22_carry_O_UNCONNECTED\(0),
S(3) => \g81__22_carry_i_3_n_0\,
S(2) => \g81__22_carry_i_4_n_0\,
S(1) => \g81__22_carry_i_5_n_0\,
S(0) => \g81__22_carry_i_6_n_0\
);
\g81__22_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry_n_0\,
CO(3) => \g81__22_carry__0_n_0\,
CO(2) => \g81__22_carry__0_n_1\,
CO(1) => \g81__22_carry__0_n_2\,
CO(0) => \g81__22_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__22_carry__0_n_4\,
O(2) => \g81__22_carry__0_n_5\,
O(1) => \g81__22_carry__0_n_6\,
O(0) => \g81__22_carry__0_n_7\,
S(3) => \g81__22_carry__0_i_1_n_0\,
S(2) => \g81__22_carry__0_i_2_n_0\,
S(1) => \g81__22_carry__0_i_3_n_0\,
S(0) => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__22_carry__0_i_1_n_0\
);
\g81__22_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__22_carry__0_i_2_n_0\
);
\g81__22_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__22_carry__0_i_3_n_0\
);
\g81__22_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__22_carry__0_i_4_n_0\
);
\g81__22_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__0_n_0\,
CO(3) => \g81__22_carry__1_n_0\,
CO(2) => \g81__22_carry__1_n_1\,
CO(1) => \g81__22_carry__1_n_2\,
CO(0) => \g81__22_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__22_carry__1_n_4\,
O(2) => \g81__22_carry__1_n_5\,
O(1) => \g81__22_carry__1_n_6\,
O(0) => \g81__22_carry__1_n_7\,
S(3) => \g81__22_carry__1_i_1_n_0\,
S(2) => \g81__22_carry__1_i_2_n_0\,
S(1) => \g81__22_carry__1_i_3_n_0\,
S(0) => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__22_carry__1_i_1_n_0\
);
\g81__22_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_2_n_0\
);
\g81__22_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__22_carry__1_i_3_n_0\
);
\g81__22_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__22_carry__1_i_4_n_0\
);
\g81__22_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__22_carry__1_n_0\,
CO(3) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__22_carry__2_n_1\,
CO(1) => \NLW_g81__22_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__22_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__22_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__22_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__22_carry__2_n_6\,
O(0) => \g81__22_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__22_carry__2_i_1_n_0\
);
\g81__22_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__22_carry__2_i_2_n_0\
);
\g81__22_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__22_carry_i_1_n_0\
);
\g81__22_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__22_carry_i_2_n_0\
);
\g81__22_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__22_carry_i_3_n_0\
);
\g81__22_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__22_carry_i_4_n_0\
);
\g81__22_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__22_carry_i_5_n_0\
);
\g81__22_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__22_carry_i_6_n_0\
);
\g81__261_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__261_carry_n_0\,
CO(2) => \g81__261_carry_n_1\,
CO(1) => \g81__261_carry_n_2\,
CO(0) => \g81__261_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__2_n_6\,
DI(2) => \g81__206_carry__2_n_7\,
DI(1 downto 0) => B"01",
O(3) => \g81__261_carry_n_4\,
O(2) => \g81__261_carry_n_5\,
O(1) => \g81__261_carry_n_6\,
O(0) => \g81__261_carry_n_7\,
S(3) => \g81__261_carry_i_1_n_0\,
S(2) => \g81__261_carry_i_2_n_0\,
S(1) => \g81__261_carry_i_3_n_0\,
S(0) => \g81__261_carry_i_4_n_0\
);
\g81__261_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry_n_0\,
CO(3) => \g81__261_carry__0_n_0\,
CO(2) => \g81__261_carry__0_n_1\,
CO(1) => \g81__261_carry__0_n_2\,
CO(0) => \g81__261_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__3_n_6\,
DI(2) => \g81__206_carry__3_n_7\,
DI(1) => \g81__206_carry__2_n_4\,
DI(0) => \g81__206_carry__2_n_5\,
O(3) => \g81__261_carry__0_n_4\,
O(2) => \g81__261_carry__0_n_5\,
O(1) => \g81__261_carry__0_n_6\,
O(0) => \g81__261_carry__0_n_7\,
S(3) => \g81__261_carry__0_i_1_n_0\,
S(2) => \g81__261_carry__0_i_2_n_0\,
S(1) => \g81__261_carry__0_i_3_n_0\,
S(0) => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__206_carry__3_n_4\,
O => \g81__261_carry__0_i_1_n_0\
);
\g81__261_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__206_carry__3_n_5\,
O => \g81__261_carry__0_i_2_n_0\
);
\g81__261_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__206_carry__3_n_6\,
O => \g81__261_carry__0_i_3_n_0\
);
\g81__261_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__206_carry__3_n_7\,
O => \g81__261_carry__0_i_4_n_0\
);
\g81__261_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__0_n_0\,
CO(3) => \g81__261_carry__1_n_0\,
CO(2) => \g81__261_carry__1_n_1\,
CO(1) => \g81__261_carry__1_n_2\,
CO(0) => \g81__261_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__206_carry__4_n_6\,
DI(2) => \g81__206_carry__4_n_7\,
DI(1) => \g81__206_carry__3_n_4\,
DI(0) => \g81__206_carry__3_n_5\,
O(3) => \g81__261_carry__1_n_4\,
O(2) => \g81__261_carry__1_n_5\,
O(1) => \g81__261_carry__1_n_6\,
O(0) => \g81__261_carry__1_n_7\,
S(3) => \g81__261_carry__1_i_1_n_0\,
S(2) => \g81__261_carry__1_i_2_n_0\,
S(1) => \g81__261_carry__1_i_3_n_0\,
S(0) => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_6\,
I1 => \g81__206_carry__4_n_0\,
O => \g81__261_carry__1_i_1_n_0\
);
\g81__261_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__4_n_7\,
I1 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__1_i_2_n_0\
);
\g81__261_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__206_carry__4_n_6\,
O => \g81__261_carry__1_i_3_n_0\
);
\g81__261_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__206_carry__4_n_7\,
O => \g81__261_carry__1_i_4_n_0\
);
\g81__261_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__261_carry__1_n_0\,
CO(3) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__261_carry__2_n_1\,
CO(1) => \NLW_g81__261_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__261_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__206_carry__4_n_0\,
DI(0) => \g81__206_carry__4_n_5\,
O(3 downto 2) => \NLW_g81__261_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__261_carry__2_n_6\,
O(0) => \g81__261_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \g81__261_carry__2_i_1_n_0\,
S(0) => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => \g81__206_carry__4_n_0\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__261_carry__2_i_1_n_0\
);
\g81__261_carry__2_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__4_n_5\,
O => \g81__261_carry__2_i_2_n_0\
);
\g81__261_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__206_carry__2_n_4\,
O => \g81__261_carry_i_1_n_0\
);
\g81__261_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__206_carry__2_n_5\,
O => \g81__261_carry_i_2_n_0\
);
\g81__261_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__261_carry_i_3_n_0\
);
\g81__261_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__261_carry_i_4_n_0\
);
\g81__301_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__301_carry_n_0\,
CO(2) => \g81__301_carry_n_1\,
CO(1) => \g81__301_carry_n_2\,
CO(0) => \g81__301_carry_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry_i_1_n_0\,
DI(2) => \g81__301_carry_i_2_n_0\,
DI(1) => \g81__301_carry_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_g81__301_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry_i_4_n_0\,
S(2) => \g81__301_carry_i_5_n_0\,
S(1) => \g81__301_carry_i_6_n_0\,
S(0) => \g81__301_carry_i_7_n_0\
);
\g81__301_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry_n_0\,
CO(3) => \g81__301_carry__0_n_0\,
CO(2) => \g81__301_carry__0_n_1\,
CO(1) => \g81__301_carry__0_n_2\,
CO(0) => \g81__301_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__0_i_1_n_0\,
DI(2) => \g81__301_carry__0_i_2_n_0\,
DI(1) => \g81__301_carry__0_i_3_n_0\,
DI(0) => \g81__301_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__0_i_5_n_0\,
S(2) => \g81__301_carry__0_i_6_n_0\,
S(1) => \g81__301_carry__0_i_7_n_0\,
S(0) => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_5\,
I1 => g84,
I2 => g83(6),
I3 => \g83__0_carry__0_n_5\,
O => \g81__301_carry__0_i_1_n_0\
);
\g81__301_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_6\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
O => \g81__301_carry__0_i_2_n_0\
);
\g81__301_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_7\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
O => \g81__301_carry__0_i_3_n_0\
);
\g81__301_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_4\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
O => \g81__301_carry__0_i_4_n_0\
);
\g81__301_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
I3 => \g81__261_carry__0_n_5\,
I4 => \g81__261_carry__0_n_4\,
I5 => \g81_carry__1_i_9_n_0\,
O => \g81__301_carry__0_i_5_n_0\
);
\g81__301_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
I3 => \g81__261_carry__0_n_6\,
I4 => \g81__261_carry__0_n_5\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__301_carry__0_i_6_n_0\
);
\g81__301_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
I3 => \g81__261_carry__0_n_7\,
I4 => \g81__261_carry__0_n_6\,
I5 => \g81_carry__0_i_14_n_0\,
O => \g81__301_carry__0_i_7_n_0\
);
\g81__301_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => \g81__261_carry_n_4\,
I2 => \g81__261_carry__0_n_7\,
I3 => \g83__0_carry__0_n_7\,
I4 => g83(4),
I5 => g84,
O => \g81__301_carry__0_i_8_n_0\
);
\g81__301_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__0_n_0\,
CO(3) => \g81__301_carry__1_n_0\,
CO(2) => \g81__301_carry__1_n_1\,
CO(1) => \g81__301_carry__1_n_2\,
CO(0) => \g81__301_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__1_i_1_n_0\,
DI(2) => \g81__301_carry__1_i_2_n_0\,
DI(1) => \g81__301_carry__1_i_3_n_0\,
DI(0) => \g81__301_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__1_i_5_n_0\,
S(2) => \g81__301_carry__1_i_6_n_0\,
S(1) => \g81__301_carry__1_i_7_n_0\,
S(0) => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__1_i_1_n_0\
);
\g81__301_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_6\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__301_carry__1_i_2_n_0\
);
\g81__301_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__1_n_7\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__301_carry__1_i_3_n_0\
);
\g81__301_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry__0_n_4\,
I1 => g84,
I2 => g83(7),
I3 => \g83__0_carry__0_n_4\,
O => \g81__301_carry__1_i_4_n_0\
);
\g81__301_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_5\,
I1 => \g81__261_carry__1_n_4\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_5_n_0\
);
\g81__301_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"50AF30CF50AFCF30"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => \g81__261_carry__1_n_6\,
I3 => \g81__261_carry__1_n_5\,
I4 => g84,
I5 => \_carry__1_n_2\,
O => \g81__301_carry__1_i_6_n_0\
);
\g81__301_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => g83(8),
I2 => g84,
I3 => \g81__261_carry__1_n_7\,
I4 => \g81__261_carry__1_n_6\,
I5 => \g81__301_carry__1_i_9_n_0\,
O => \g81__301_carry__1_i_7_n_0\
);
\g81__301_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"B44BB44BB4B44B4B"
)
port map (
I0 => \g81_carry__1_i_9_n_0\,
I1 => \g81__261_carry__0_n_4\,
I2 => \g81__261_carry__1_n_7\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__301_carry__1_i_8_n_0\
);
\g81__301_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__1_n_2\,
I1 => g83(9),
I2 => g84,
O => \g81__301_carry__1_i_9_n_0\
);
\g81__301_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__1_n_0\,
CO(3) => \g81__301_carry__2_n_0\,
CO(2) => \g81__301_carry__2_n_1\,
CO(1) => \g81__301_carry__2_n_2\,
CO(0) => \g81__301_carry__2_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__2_i_1_n_0\,
DI(2) => \g81__301_carry__2_i_2_n_0\,
DI(1) => \g81__301_carry__2_i_3_n_0\,
DI(0) => \g81__301_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__2_i_5_n_0\,
S(2) => \g81__301_carry__2_i_6_n_0\,
S(1) => \g81__301_carry__2_i_7_n_0\,
S(0) => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__2_i_1_n_0\
);
\g81__301_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_2_n_0\
);
\g81__301_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_3_n_0\
);
\g81__301_carry__2_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \_carry__1_n_2\,
I2 => g84,
O => \g81__301_carry__2_i_4_n_0\
);
\g81__301_carry__2_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_5_n_0\
);
\g81__301_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6663"
)
port map (
I0 => \g81__261_carry__2_n_6\,
I1 => \g81__261_carry__2_n_1\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_6_n_0\
);
\g81__301_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__2_n_7\,
I1 => \g81__261_carry__2_n_6\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_7_n_0\
);
\g81__301_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"999C"
)
port map (
I0 => \g81__261_carry__1_n_4\,
I1 => \g81__261_carry__2_n_7\,
I2 => g84,
I3 => \_carry__1_n_2\,
O => \g81__301_carry__2_i_8_n_0\
);
\g81__301_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__2_n_0\,
CO(3) => \g81__301_carry__3_n_0\,
CO(2) => \g81__301_carry__3_n_1\,
CO(1) => \g81__301_carry__3_n_2\,
CO(0) => \g81__301_carry__3_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__3_i_1_n_0\,
DI(2) => \g81__301_carry__3_i_2_n_0\,
DI(1) => \g81__301_carry__3_i_3_n_0\,
DI(0) => \g81__301_carry__3_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__3_i_5_n_0\,
S(2) => \g81__301_carry__3_i_6_n_0\,
S(1) => \g81__301_carry__3_i_7_n_0\,
S(0) => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__3_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_1_n_0\
);
\g81__301_carry__3_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_2_n_0\
);
\g81__301_carry__3_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_3_n_0\
);
\g81__301_carry__3_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__3_i_4_n_0\
);
\g81__301_carry__3_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_5_n_0\
);
\g81__301_carry__3_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_6_n_0\
);
\g81__301_carry__3_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_7_n_0\
);
\g81__301_carry__3_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__3_i_8_n_0\
);
\g81__301_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__3_n_0\,
CO(3) => \g81__301_carry__4_n_0\,
CO(2) => \g81__301_carry__4_n_1\,
CO(1) => \g81__301_carry__4_n_2\,
CO(0) => \g81__301_carry__4_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__4_i_1_n_0\,
DI(2) => \g81__301_carry__4_i_2_n_0\,
DI(1) => \g81__301_carry__4_i_3_n_0\,
DI(0) => \g81__301_carry__4_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__4_i_5_n_0\,
S(2) => \g81__301_carry__4_i_6_n_0\,
S(1) => \g81__301_carry__4_i_7_n_0\,
S(0) => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__4_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_1_n_0\
);
\g81__301_carry__4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_2_n_0\
);
\g81__301_carry__4_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_3_n_0\
);
\g81__301_carry__4_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__4_i_4_n_0\
);
\g81__301_carry__4_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_5_n_0\
);
\g81__301_carry__4_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_6_n_0\
);
\g81__301_carry__4_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_7_n_0\
);
\g81__301_carry__4_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__4_i_8_n_0\
);
\g81__301_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__4_n_0\,
CO(3) => \g81__301_carry__5_n_0\,
CO(2) => \g81__301_carry__5_n_1\,
CO(1) => \g81__301_carry__5_n_2\,
CO(0) => \g81__301_carry__5_n_3\,
CYINIT => '0',
DI(3) => \g81__301_carry__5_i_1_n_0\,
DI(2) => \g81__301_carry__5_i_2_n_0\,
DI(1) => \g81__301_carry__5_i_3_n_0\,
DI(0) => \g81__301_carry__5_i_4_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \g81__301_carry__5_i_5_n_0\,
S(2) => \g81__301_carry__5_i_6_n_0\,
S(1) => \g81__301_carry__5_i_7_n_0\,
S(0) => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__5_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_1_n_0\
);
\g81__301_carry__5_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_2_n_0\
);
\g81__301_carry__5_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_3_n_0\
);
\g81__301_carry__5_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__5_i_4_n_0\
);
\g81__301_carry__5_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_5_n_0\
);
\g81__301_carry__5_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_6_n_0\
);
\g81__301_carry__5_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_7_n_0\
);
\g81__301_carry__5_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__5_i_8_n_0\
);
\g81__301_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \g81__301_carry__5_n_0\,
CO(3) => \NLW_g81__301_carry__6_CO_UNCONNECTED\(3),
CO(2) => \g81__301_carry__6_n_1\,
CO(1) => \g81__301_carry__6_n_2\,
CO(0) => \g81__301_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \g81__301_carry__6_i_1_n_0\,
DI(1) => \g81__301_carry__6_i_2_n_0\,
DI(0) => \g81__301_carry__6_i_3_n_0\,
O(3 downto 0) => \NLW_g81__301_carry__6_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \g81__301_carry__6_i_4_n_0\,
S(1) => \g81__301_carry__6_i_5_n_0\,
S(0) => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry__6_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_1_n_0\
);
\g81__301_carry__6_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_2_n_0\
);
\g81__301_carry__6_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \_carry__1_n_2\,
I1 => g84,
I2 => \g81__261_carry__2_n_1\,
O => \g81__301_carry__6_i_3_n_0\
);
\g81__301_carry__6_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_4_n_0\
);
\g81__301_carry__6_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_5_n_0\
);
\g81__301_carry__6_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \g81__261_carry__2_n_1\,
I1 => g84,
I2 => \_carry__1_n_2\,
O => \g81__301_carry__6_i_6_n_0\
);
\g81__301_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"028A"
)
port map (
I0 => \g81__261_carry_n_5\,
I1 => g84,
I2 => g83(2),
I3 => \g83__0_carry_n_5\,
O => \g81__301_carry_i_1_n_0\
);
\g81__301_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABEF"
)
port map (
I0 => \g81__261_carry_n_6\,
I1 => g84,
I2 => g83(1),
I3 => \g83__0_carry_n_6\,
O => \g81__301_carry_i_2_n_0\
);
\g81__301_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g81__261_carry_n_7\,
I1 => \g83__0_carry_n_7\,
O => \g81__301_carry_i_3_n_0\
);
\g81__301_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ACFF53005300ACFF"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
I3 => \g81__261_carry_n_5\,
I4 => \g81__261_carry_n_4\,
I5 => \g81_carry__0_i_9_n_0\,
O => \g81__301_carry_i_4_n_0\
);
\g81__301_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DD22DD22D2DD2D2"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => \g81__261_carry_n_6\,
I2 => \g81__261_carry_n_5\,
I3 => \g83__0_carry_n_5\,
I4 => g83(2),
I5 => g84,
O => \g81__301_carry_i_5_n_0\
);
\g81__301_carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22DD22DD2D22D2D"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
I2 => \g81__261_carry_n_6\,
I3 => \g83__0_carry_n_6\,
I4 => g83(1),
I5 => g84,
O => \g81__301_carry_i_6_n_0\
);
\g81__301_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g81__261_carry_n_7\,
O => \g81__301_carry_i_7_n_0\
);
\g81__347_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__347_carry_n_0\,
CO(2) => \g81__347_carry_n_1\,
CO(1) => \g81__347_carry_n_2\,
CO(0) => \g81__347_carry_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \g81__347_carry_n_4\,
O(2) => \g81__347_carry_n_5\,
O(1) => \g81__347_carry_n_6\,
O(0) => \g81__347_carry_n_7\,
S(3) => \g81__347_carry_i_1_n_0\,
S(2) => \g81__347_carry_i_2_n_0\,
S(1) => \g81__347_carry_i_3_n_0\,
S(0) => \g81__347_carry_i_4_n_0\
);
\g81__347_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__347_carry_n_0\,
CO(3) => \NLW_g81__347_carry__0_CO_UNCONNECTED\(3),
CO(2) => \g81__347_carry__0_n_1\,
CO(1) => \g81__347_carry__0_n_2\,
CO(0) => \g81__347_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \g81__347_carry__0_n_4\,
O(2) => \g81__347_carry__0_n_5\,
O(1) => \g81__347_carry__0_n_6\,
O(0) => \g81__347_carry__0_n_7\,
S(3) => \g81__347_carry__0_i_1_n_0\,
S(2) => \g81__347_carry__0_i_2_n_0\,
S(1) => \g81__347_carry__0_i_3_n_0\,
S(0) => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_4\,
O => \g81__347_carry__0_i_1_n_0\
);
\g81__347_carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_5\,
O => \g81__347_carry__0_i_2_n_0\
);
\g81__347_carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_6\,
O => \g81__347_carry__0_i_3_n_0\
);
\g81__347_carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__3_n_7\,
O => \g81__347_carry__0_i_4_n_0\
);
\g81__347_carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_4\,
O => \g81__347_carry_i_1_n_0\
);
\g81__347_carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_5\,
O => \g81__347_carry_i_2_n_0\
);
\g81__347_carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \g81__206_carry__2_n_6\,
O => \g81__347_carry_i_3_n_0\
);
\g81__347_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \g81__206_carry__2_n_7\,
O => \g81__347_carry_i_4_n_0\
);
\g81__53_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__53_carry_n_0\,
CO(2) => \g81__53_carry_n_1\,
CO(1) => \g81__53_carry_n_2\,
CO(0) => \g81__53_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__53_carry_i_1_n_0\,
DI(1) => \g81__53_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__53_carry_n_4\,
O(2) => \g81__53_carry_n_5\,
O(1) => \g81__53_carry_n_6\,
O(0) => \NLW_g81__53_carry_O_UNCONNECTED\(0),
S(3) => \g81__53_carry_i_3_n_0\,
S(2) => \g81__53_carry_i_4_n_0\,
S(1) => \g81__53_carry_i_5_n_0\,
S(0) => \g81__53_carry_i_6_n_0\
);
\g81__53_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry_n_0\,
CO(3) => \g81__53_carry__0_n_0\,
CO(2) => \g81__53_carry__0_n_1\,
CO(1) => \g81__53_carry__0_n_2\,
CO(0) => \g81__53_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__53_carry__0_n_4\,
O(2) => \g81__53_carry__0_n_5\,
O(1) => \g81__53_carry__0_n_6\,
O(0) => \g81__53_carry__0_n_7\,
S(3) => \g81__53_carry__0_i_1_n_0\,
S(2) => \g81__53_carry__0_i_2_n_0\,
S(1) => \g81__53_carry__0_i_3_n_0\,
S(0) => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__53_carry__0_i_1_n_0\
);
\g81__53_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__53_carry__0_i_2_n_0\
);
\g81__53_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__53_carry__0_i_3_n_0\
);
\g81__53_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__53_carry__0_i_4_n_0\
);
\g81__53_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__0_n_0\,
CO(3) => \g81__53_carry__1_n_0\,
CO(2) => \g81__53_carry__1_n_1\,
CO(1) => \g81__53_carry__1_n_2\,
CO(0) => \g81__53_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__53_carry__1_n_4\,
O(2) => \g81__53_carry__1_n_5\,
O(1) => \g81__53_carry__1_n_6\,
O(0) => \g81__53_carry__1_n_7\,
S(3) => \g81__53_carry__1_i_1_n_0\,
S(2) => \g81__53_carry__1_i_2_n_0\,
S(1) => \g81__53_carry__1_i_3_n_0\,
S(0) => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__53_carry__1_i_1_n_0\
);
\g81__53_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_2_n_0\
);
\g81__53_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__53_carry__1_i_3_n_0\
);
\g81__53_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__53_carry__1_i_4_n_0\
);
\g81__53_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__53_carry__1_n_0\,
CO(3) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__53_carry__2_n_1\,
CO(1) => \NLW_g81__53_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__53_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__53_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__53_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__53_carry__2_n_6\,
O(0) => \g81__53_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__53_carry__2_i_1_n_0\
);
\g81__53_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__53_carry__2_i_2_n_0\
);
\g81__53_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__53_carry_i_1_n_0\
);
\g81__53_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__53_carry_i_2_n_0\
);
\g81__53_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__53_carry_i_3_n_0\
);
\g81__53_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__53_carry_i_4_n_0\
);
\g81__53_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__53_carry_i_5_n_0\
);
\g81__53_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__53_carry_i_6_n_0\
);
\g81__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g81__92_carry_n_0\,
CO(2) => \g81__92_carry_n_1\,
CO(1) => \g81__92_carry_n_2\,
CO(0) => \g81__92_carry_n_3\,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => \g81__92_carry_i_1_n_0\,
DI(1) => \g81__92_carry_i_2_n_0\,
DI(0) => '0',
O(3) => \g81__92_carry_n_4\,
O(2) => \g81__92_carry_n_5\,
O(1) => \g81__92_carry_n_6\,
O(0) => \NLW_g81__92_carry_O_UNCONNECTED\(0),
S(3) => \g81__92_carry_i_3_n_0\,
S(2) => \g81__92_carry_i_4_n_0\,
S(1) => \g81__92_carry_i_5_n_0\,
S(0) => \g81__92_carry_i_6_n_0\
);
\g81__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry_n_0\,
CO(3) => \g81__92_carry__0_n_0\,
CO(2) => \g81__92_carry__0_n_1\,
CO(1) => \g81__92_carry__0_n_2\,
CO(0) => \g81__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81__92_carry__0_n_4\,
O(2) => \g81__92_carry__0_n_5\,
O(1) => \g81__92_carry__0_n_6\,
O(0) => \g81__92_carry__0_n_7\,
S(3) => \g81__92_carry__0_i_1_n_0\,
S(2) => \g81__92_carry__0_i_2_n_0\,
S(1) => \g81__92_carry__0_i_3_n_0\,
S(0) => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81__92_carry__0_i_1_n_0\
);
\g81__92_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81__92_carry__0_i_2_n_0\
);
\g81__92_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81__92_carry__0_i_3_n_0\
);
\g81__92_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81__92_carry__0_i_4_n_0\
);
\g81__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__0_n_0\,
CO(3) => \g81__92_carry__1_n_0\,
CO(2) => \g81__92_carry__1_n_1\,
CO(1) => \g81__92_carry__1_n_2\,
CO(0) => \g81__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81__92_carry__1_n_4\,
O(2) => \g81__92_carry__1_n_5\,
O(1) => \g81__92_carry__1_n_6\,
O(0) => \g81__92_carry__1_n_7\,
S(3) => \g81__92_carry__1_i_1_n_0\,
S(2) => \g81__92_carry__1_i_2_n_0\,
S(1) => \g81__92_carry__1_i_3_n_0\,
S(0) => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81__92_carry__1_i_1_n_0\
);
\g81__92_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_2_n_0\
);
\g81__92_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81__92_carry__1_i_3_n_0\
);
\g81__92_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81__92_carry__1_i_4_n_0\
);
\g81__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81__92_carry__1_n_0\,
CO(3) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81__92_carry__2_n_1\,
CO(1) => \NLW_g81__92_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81__92_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81__92_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81__92_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81__92_carry__2_n_6\,
O(0) => \g81__92_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81__92_carry__2_i_1_n_0\
);
\g81__92_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81__92_carry__2_i_2_n_0\
);
\g81__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81__92_carry_i_1_n_0\
);
\g81__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81__92_carry_i_2_n_0\
);
\g81__92_carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => \g81__92_carry_i_3_n_0\
);
\g81__92_carry_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81__92_carry_i_4_n_0\
);
\g81__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => \g81__92_carry_i_5_n_0\
);
\g81__92_carry_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81__92_carry_i_6_n_0\
);
g81_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g81_carry_n_0,
CO(2) => g81_carry_n_1,
CO(1) => g81_carry_n_2,
CO(0) => g81_carry_n_3,
CYINIT => '0',
DI(3) => g81_carry_i_1_n_0,
DI(2) => g81_carry_i_2_n_0,
DI(1) => g81_carry_i_3_n_0,
DI(0) => '0',
O(3 downto 1) => NLW_g81_carry_O_UNCONNECTED(3 downto 1),
O(0) => g81_carry_n_7,
S(3) => g81_carry_i_4_n_0,
S(2) => g81_carry_i_5_n_0,
S(1) => g81_carry_i_6_n_0,
S(0) => g81_carry_i_7_n_0
);
\g81_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g81_carry_n_0,
CO(3) => \g81_carry__0_n_0\,
CO(2) => \g81_carry__0_n_1\,
CO(1) => \g81_carry__0_n_2\,
CO(0) => \g81_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__0_i_1_n_0\,
DI(2) => \g81_carry__0_i_2_n_0\,
DI(1) => \g81_carry__0_i_3_n_0\,
DI(0) => \g81_carry__0_i_4_n_0\,
O(3) => \g81_carry__0_n_4\,
O(2) => \g81_carry__0_n_5\,
O(1) => \g81_carry__0_n_6\,
O(0) => \NLW_g81_carry__0_O_UNCONNECTED\(0),
S(3) => \g81_carry__0_i_5_n_0\,
S(2) => \g81_carry__0_i_6_n_0\,
S(1) => \g81_carry__0_i_7_n_0\,
S(0) => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_9_n_0\,
I1 => g84,
I2 => g83(5),
I3 => \g83__0_carry__0_n_6\,
I4 => g83(7),
I5 => \g83__0_carry__0_n_4\,
O => \g81_carry__0_i_1_n_0\
);
\g81_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => \g81_carry__0_i_10_n_0\
);
\g81_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => \g81_carry__0_i_11_n_0\
);
\g81_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => g83(6),
I2 => g84,
O => \g81_carry__0_i_12_n_0\
);
\g81_carry__0_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => g83(4),
I2 => g84,
O => \g81_carry__0_i_13_n_0\
);
\g81_carry__0_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_6\,
I1 => g83(5),
I2 => g84,
O => \g81_carry__0_i_14_n_0\
);
\g81_carry__0_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => \g81_carry__0_i_15_n_0\
);
\g81_carry__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_10_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => g83(6),
I5 => \g83__0_carry__0_n_5\,
O => \g81_carry__0_i_2_n_0\
);
\g81_carry__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEBAECA8BA32A820"
)
port map (
I0 => \g81_carry__0_i_11_n_0\,
I1 => g84,
I2 => g83(3),
I3 => \g83__0_carry_n_4\,
I4 => g83(5),
I5 => \g83__0_carry__0_n_6\,
O => \g81_carry__0_i_3_n_0\
);
\g81_carry__0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C33CC33CA5A55A5A"
)
port map (
I0 => g83(5),
I1 => \g83__0_carry__0_n_6\,
I2 => \g81_carry__0_i_11_n_0\,
I3 => \g83__0_carry_n_4\,
I4 => g83(3),
I5 => g84,
O => \g81_carry__0_i_4_n_0\
);
\g81_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_1_n_0\,
I1 => \g81_carry__0_i_12_n_0\,
I2 => \g81_carry__0_i_13_n_0\,
I3 => \g83__0_carry__1_n_7\,
I4 => g83(8),
I5 => g84,
O => \g81_carry__0_i_5_n_0\
);
\g81_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__0_i_2_n_0\,
I1 => \g81_carry__0_i_14_n_0\,
I2 => \g81_carry__0_i_9_n_0\,
I3 => \g83__0_carry__0_n_4\,
I4 => g83(7),
I5 => g84,
O => \g81_carry__0_i_6_n_0\
);
\g81_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"569AA965A965569A"
)
port map (
I0 => \g81_carry__0_i_3_n_0\,
I1 => g84,
I2 => g83(4),
I3 => \g83__0_carry__0_n_7\,
I4 => \g81_carry__0_i_10_n_0\,
I5 => \g81_carry__0_i_12_n_0\,
O => \g81_carry__0_i_7_n_0\
);
\g81_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"99666666A55A5A5A"
)
port map (
I0 => \g81_carry__0_i_15_n_0\,
I1 => \g83__0_carry__0_n_6\,
I2 => g83(5),
I3 => \g81_carry__0_i_10_n_0\,
I4 => \g83__0_carry_n_7\,
I5 => g84,
O => \g81_carry__0_i_8_n_0\
);
\g81_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => \g81_carry__0_i_9_n_0\
);
\g81_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__0_n_0\,
CO(3) => \g81_carry__1_n_0\,
CO(2) => \g81_carry__1_n_1\,
CO(1) => \g81_carry__1_n_2\,
CO(0) => \g81_carry__1_n_3\,
CYINIT => '0',
DI(3) => \g81_carry__1_i_1_n_0\,
DI(2) => \g81_carry__1_i_2_n_0\,
DI(1) => \g81_carry__1_i_3_n_0\,
DI(0) => \g81_carry__1_i_4_n_0\,
O(3) => \g81_carry__1_n_4\,
O(2) => \g81_carry__1_n_5\,
O(1) => \g81_carry__1_n_6\,
O(0) => \g81_carry__1_n_7\,
S(3) => \g81_carry__1_i_5_n_0\,
S(2) => \g81_carry__1_i_6_n_0\,
S(1) => \g81_carry__1_i_7_n_0\,
S(0) => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(7),
I1 => \g83__0_carry__0_n_4\,
I2 => g84,
I3 => g83(9),
I4 => \g83__0_carry__1_n_2\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_1_n_0\
);
\g81_carry__1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CAC00A00CFCA0F0A"
)
port map (
I0 => g83(6),
I1 => \g83__0_carry__0_n_5\,
I2 => g84,
I3 => g83(8),
I4 => \g83__0_carry__1_n_7\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_2_n_0\
);
\g81_carry__1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(5),
I2 => \g83__0_carry__0_n_6\,
I3 => \g81_carry__1_i_9_n_0\,
I4 => g83(9),
I5 => \g83__0_carry__1_n_2\,
O => \g81_carry__1_i_3_n_0\
);
\g81_carry__1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE4EEA0F544E400"
)
port map (
I0 => g84,
I1 => g83(4),
I2 => \g83__0_carry__0_n_7\,
I3 => \g81_carry__0_i_12_n_0\,
I4 => g83(8),
I5 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_4_n_0\
);
\g81_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__1_i_1_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
O => \g81_carry__1_i_5_n_0\
);
\g81_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
I4 => \g81_carry__1_i_9_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_6_n_0\
);
\g81_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"A965569A9A5665A9"
)
port map (
I0 => \g81_carry__1_i_3_n_0\,
I1 => g84,
I2 => g83(8),
I3 => \g83__0_carry__1_n_7\,
I4 => \g81_carry__0_i_12_n_0\,
I5 => \_carry__1_n_2\,
O => \g81_carry__1_i_7_n_0\
);
\g81_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996699669699696"
)
port map (
I0 => \g81_carry__1_i_4_n_0\,
I1 => \g81_carry__1_i_9_n_0\,
I2 => \g81_carry__0_i_14_n_0\,
I3 => \g83__0_carry__1_n_2\,
I4 => g83(9),
I5 => g84,
O => \g81_carry__1_i_8_n_0\
);
\g81_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry__0_n_4\,
I1 => g83(7),
I2 => g84,
O => \g81_carry__1_i_9_n_0\
);
\g81_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \g81_carry__1_n_0\,
CO(3) => \NLW_g81_carry__2_CO_UNCONNECTED\(3),
CO(2) => \g81_carry__2_n_1\,
CO(1) => \NLW_g81_carry__2_CO_UNCONNECTED\(1),
CO(0) => \g81_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \g81_carry__2_i_1_n_0\,
DI(0) => \g81_carry__2_i_2_n_0\,
O(3 downto 2) => \NLW_g81_carry__2_O_UNCONNECTED\(3 downto 2),
O(1) => \g81_carry__2_n_6\,
O(0) => \g81_carry__2_n_7\,
S(3 downto 1) => B"010",
S(0) => \g81_carry__2_i_3_n_0\
);
\g81_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_1_n_0\
);
\g81_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => g84,
I1 => \_carry__1_n_2\,
O => \g81_carry__2_i_2_n_0\
);
\g81_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"569A"
)
port map (
I0 => \g81_carry__2_i_2_n_0\,
I1 => g84,
I2 => g83(9),
I3 => \g83__0_carry__1_n_2\,
O => \g81_carry__2_i_3_n_0\
);
g81_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_1_n_0
);
g81_carry_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_4\,
I1 => g83(3),
I2 => g84,
O => g81_carry_i_2_n_0
);
g81_carry_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => g83(2),
I2 => g84,
O => g81_carry_i_3_n_0
);
g81_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"99A5995A66A5665A"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_5\,
I2 => g83(2),
I3 => g84,
I4 => g83(4),
I5 => \g83__0_carry__0_n_7\,
O => g81_carry_i_4_n_0
);
g81_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"353AC5CA"
)
port map (
I0 => g83(3),
I1 => \g83__0_carry_n_4\,
I2 => g84,
I3 => g83(1),
I4 => \g83__0_carry_n_6\,
O => g81_carry_i_5_n_0
);
g81_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"35CA"
)
port map (
I0 => g83(2),
I1 => \g83__0_carry_n_5\,
I2 => g84,
I3 => \g83__0_carry_n_7\,
O => g81_carry_i_6_n_0
);
g81_carry_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \g83__0_carry_n_6\,
I1 => g83(1),
I2 => g84,
O => g81_carry_i_7_n_0
);
\g83__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g83__0_carry_n_0\,
CO(2) => \g83__0_carry_n_1\,
CO(1) => \g83__0_carry_n_2\,
CO(0) => \g83__0_carry_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry_i_1_n_0\,
DI(2) => \g83__0_carry_i_2_n_0\,
DI(1) => \g83__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \g83__0_carry_n_4\,
O(2) => \g83__0_carry_n_5\,
O(1) => \g83__0_carry_n_6\,
O(0) => \g83__0_carry_n_7\,
S(3) => \g83__0_carry_i_4_n_0\,
S(2) => \g83__0_carry_i_5_n_0\,
S(1) => \g83__0_carry_i_6_n_0\,
S(0) => \g83__0_carry_i_7_n_0\
);
\g83__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry_n_0\,
CO(3) => \g83__0_carry__0_n_0\,
CO(2) => \g83__0_carry__0_n_1\,
CO(1) => \g83__0_carry__0_n_2\,
CO(0) => \g83__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \g83__0_carry__0_i_1_n_0\,
DI(2) => \g83__0_carry__0_i_2_n_0\,
DI(1) => \g83__0_carry__0_i_3_n_0\,
DI(0) => \g83__0_carry__0_i_4_n_0\,
O(3) => \g83__0_carry__0_n_4\,
O(2) => \g83__0_carry__0_n_5\,
O(1) => \g83__0_carry__0_n_6\,
O(0) => \g83__0_carry__0_n_7\,
S(3) => \g83__0_carry__0_i_5_n_0\,
S(2) => \g83__0_carry__0_i_6_n_0\,
S(1) => \g83__0_carry__0_i_7_n_0\,
S(0) => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
O => \g83__0_carry__0_i_1_n_0\
);
\g83__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
O => \g83__0_carry__0_i_2_n_0\
);
\g83__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
O => \g83__0_carry__0_i_3_n_0\
);
\g83__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
O => \g83__0_carry__0_i_4_n_0\
);
\g83__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \g83__0_carry__0_i_1_n_0\,
I1 => rgb888(7),
I2 => rgb888(15),
I3 => rgb888(23),
O => \g83__0_carry__0_i_5_n_0\
);
\g83__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(14),
I1 => rgb888(6),
I2 => rgb888(22),
I3 => \g83__0_carry__0_i_2_n_0\,
O => \g83__0_carry__0_i_6_n_0\
);
\g83__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(13),
I1 => rgb888(5),
I2 => rgb888(21),
I3 => \g83__0_carry__0_i_3_n_0\,
O => \g83__0_carry__0_i_7_n_0\
);
\g83__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(12),
I1 => rgb888(4),
I2 => rgb888(20),
I3 => \g83__0_carry__0_i_4_n_0\,
O => \g83__0_carry__0_i_8_n_0\
);
\g83__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \g83__0_carry__0_n_0\,
CO(3 downto 2) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \g83__0_carry__1_n_2\,
CO(0) => \NLW_g83__0_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_g83__0_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \g83__0_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(15),
I1 => rgb888(7),
I2 => rgb888(23),
O => \g83__0_carry__1_i_1_n_0\
);
\g83__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
O => \g83__0_carry_i_1_n_0\
);
\g83__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
O => \g83__0_carry_i_2_n_0\
);
\g83__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_3_n_0\
);
\g83__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(11),
I1 => rgb888(3),
I2 => rgb888(19),
I3 => \g83__0_carry_i_1_n_0\,
O => \g83__0_carry_i_4_n_0\
);
\g83__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(10),
I1 => rgb888(2),
I2 => rgb888(18),
I3 => \g83__0_carry_i_2_n_0\,
O => \g83__0_carry_i_5_n_0\
);
\g83__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(1),
I2 => rgb888(17),
I3 => \g83__0_carry_i_3_n_0\,
O => \g83__0_carry_i_6_n_0\
);
\g83__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(0),
I2 => rgb888(16),
O => \g83__0_carry_i_7_n_0\
);
g84_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => g84_carry_n_0,
CO(2) => g84_carry_n_1,
CO(1) => g84_carry_n_2,
CO(0) => g84_carry_n_3,
CYINIT => '1',
DI(3) => g84_carry_i_1_n_0,
DI(2) => g84_carry_i_2_n_0,
DI(1) => g84_carry_i_3_n_0,
DI(0) => g84_carry_i_4_n_0,
O(3 downto 0) => NLW_g84_carry_O_UNCONNECTED(3 downto 0),
S(3) => g84_carry_i_5_n_0,
S(2) => g84_carry_i_6_n_0,
S(1) => g84_carry_i_7_n_0,
S(0) => g84_carry_i_8_n_0
);
\g84_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => g84_carry_n_0,
CO(3 downto 1) => \NLW_g84_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => g84,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \g84_carry__0_i_1_n_0\,
O(3 downto 0) => \NLW_g84_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \g84_carry__0_i_2_n_0\
);
\g84_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_1_n_0\
);
\g84_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__1_n_7\,
I1 => \g83__0_carry__1_n_2\,
O => \g84_carry__0_i_2_n_0\
);
g84_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_1_n_0
);
g84_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_2_n_0
);
g84_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_3_n_0
);
g84_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_4_n_0
);
g84_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_5\,
I1 => \g83__0_carry__0_n_4\,
O => g84_carry_i_5_n_0
);
g84_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry__0_n_7\,
I1 => \g83__0_carry__0_n_6\,
O => g84_carry_i_6_n_0
);
g84_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_5\,
I1 => \g83__0_carry_n_4\,
O => g84_carry_i_7_n_0
);
g84_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \g83__0_carry_n_7\,
I1 => \g83__0_carry_n_6\,
O => g84_carry_i_8_n_0
);
\g8[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_7\,
O => g810_in(0)
);
\g8[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_6\,
O => g810_in(1)
);
\g8[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_5\,
O => g810_in(2)
);
\g8[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__2_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry_n_4\,
O => g810_in(3)
);
\g8[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_7\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_7\,
O => g810_in(4)
);
\g8[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_6\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_6\,
O => g810_in(5)
);
\g8[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_5\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_5\,
O => g810_in(6)
);
\g8[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABABABB8A8A8A88"
)
port map (
I0 => \g81__206_carry__3_n_4\,
I1 => \g81__301_carry__6_n_1\,
I2 => \g81__261_carry__2_n_1\,
I3 => g84,
I4 => \_carry__1_n_2\,
I5 => \g81__347_carry__0_n_4\,
O => g810_in(7)
);
\g8_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(0),
Q => g8(0),
R => '0'
);
\g8_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(1),
Q => g8(1),
R => '0'
);
\g8_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(2),
Q => g8(2),
R => '0'
);
\g8_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(3),
Q => g8(3),
R => '0'
);
\g8_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(4),
Q => g8(4),
R => '0'
);
\g8_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(5),
Q => g8(5),
R => '0'
);
\g8_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(6),
Q => g8(6),
R => '0'
);
\g8_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => g810_in(7),
Q => g8(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_g8_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_g8_0_0 : entity is "system_rgb888_to_g8_0_0,rgb888_to_g8,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_g8_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_g8_0_0 : entity is "rgb888_to_g8,Vivado 2016.4";
end system_rgb888_to_g8_0_0;
architecture STRUCTURE of system_rgb888_to_g8_0_0 is
begin
U0: entity work.system_rgb888_to_g8_0_0_rgb888_to_g8
port map (
clk => clk,
g8(7 downto 0) => g8(7 downto 0),
rgb888(23 downto 0) => rgb888(23 downto 0)
);
end STRUCTURE;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect key_block
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`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
--
-- File: PkgZmodADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodScpeController IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodADC is
-- Zmod Scope variants identifier
constant kZmodScope1410_105 : integer := 0; -- Zmod Scpe 1410 - 105 (AD9648)
constant kZmodScope1010_40 : integer := 1; -- Zmod Scpe 1010 - 40 (AD9204)
constant kZmodScope1010_125 : integer := 2; -- Zmod Scpe 1010 - 125 (AD9608)
constant kZmodScope1210_40 : integer := 3; -- Zmod Scpe 1210 - 40 (AD9231)
constant kZmodScope1210_125 : integer := 4; -- Zmod Scpe 1210 - 125 (AD9628)
constant kZmodScope1410_40 : integer := 5; -- Zmod Scpe 1410 - 40 (AD9251)
constant kZmodScope1410_125 : integer := 6; -- Zmod Scpe 1410 - 125 (AD9648)
--Timing parameters
constant kSysClkPeriod : time := 10ns; -- System Clock Period
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
constant kTdcoMax : time := 4.4 ns;
-- Relay Set and Reset signals in simulation. In real life, this constant should be equal to 3ms.
constant kRelayConfigTime : time := 3us;
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified in AD9648
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 16; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9648. The maximum frequency is 25MHz.
type ADC_SPI_Commands_t is array (19 downto 0) of std_logic_vector(23 downto 0);
type ADC_SPI_Readback_t is array (19 downto 0) of std_logic_vector(7 downto 0);
constant kAD96xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"003A02", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"001680", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"000500", --8 Device index: none
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD96xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"80", --9 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"00", --8 Device index: none
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Cmd : ADC_SPI_Commands_t := (x"000500", --19 Device index: none
x"000800", --18 Power modes: Normal operation
x"000502", --17 Device index: B
x"000800", --16 Power modes: Normal operation
x"000501", --15 Device index: A
x"010002", --14 Sync control : continuous | sync enable | 0
x"001781", --13 Output Delay; DCO delay enabled; 1.12ns
x"001511", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"002A00", --11 Overrange control: output disable
x"000B03", --10 Clck Divide: 4
x"000500", --9 Device index: none
x"001680", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"001421", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"000803", --6 Power modes: digital reset
x"000502", --5 Device index: B
x"001431", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"000803", --3 Power modes: digital reset
x"000501", --2 Device index: A
x"000100", --1 Chip ID: read chip ID
x"00003C" --0 SPI Port Config: soft reset
);
constant kAD92xx_SPI_Rdbck : ADC_SPI_Readback_t:= (x"00", --19 Device index: none
x"00", --18 Power modes: Normal operation
x"02", --17 Device index: B
x"00", --16 Power modes: Normal operation
x"01", --15 Device index: A
x"02", --14 Sync control : continuous | sync enable | 0
x"81", --13 Output Delay; DCO delay enabled; 1.12ns
x"11", --12 Output adjust: CMOS drive strength 01 - 2X [DCO | DOUT]
x"00", --11 Overrange control: output disable
x"03", --10 Clck Divide: 4
x"00", --9 Device index: none
x"80", --8 Clock Phase control: DCO inverted, Input clock divider phase adjust 0
x"21", --7 Output mode: CMOS | interleave | enable B | output not invert | 2's Complement
x"03", --6 Power modes: digital reset
x"02", --5 Device index: B
x"31", --4 Output mode: CMOS | interleave | disable A | output not invert | 2's Complement
x"03", --3 Power modes: digital reset
x"01", --2 Device index: A
x"88", --1 Chip ID expected value:88
x"18" --0 SPI Port Config: soft reset
);
constant kSetTrsfReg : std_logic_vector(23 downto 0) := x"00FF01";
--ADC Register addresses
constant kDevIndex : std_logic_vector(12 downto 0) := "00000" & x"05";
constant kPwrModes : std_logic_vector(12 downto 0) := "00000" & x"08";
constant kSyncCtrll : std_logic_vector(12 downto 0) := "00000" & x"3A";
constant kOutDly : std_logic_vector(12 downto 0) := "00000" & x"17";
constant kOutAdj : std_logic_vector(12 downto 0) := "00000" & x"15";
constant kOvrrCtrl : std_logic_vector(12 downto 0) := "00000" & x"2A";
constant kClkPhCtrl : std_logic_vector(12 downto 0) := "00000" & x"16";
constant kClkDiv : std_logic_vector(12 downto 0) := "00000" & x"0B";
constant kOutMode : std_logic_vector(12 downto 0) := "00000" & x"14";
constant kChipID : std_logic_vector(12 downto 0) := "00000" & x"01";
constant kSPI_PortCfg : std_logic_vector(12 downto 0) := "00000" & x"01";
--ID Register value for supported Zmods
constant AD9648_ID : std_logic_vector(7 downto 0) := x"88";
constant AD9204_ID : std_logic_vector(7 downto 0) := x"25";
constant AD9608_ID : std_logic_vector(7 downto 0) := x"9C";
constant AD9231_ID : std_logic_vector(7 downto 0) := x"24";
constant AD9628_ID : std_logic_vector(7 downto 0) := x"89";
constant AD9251_ID : std_logic_vector(7 downto 0) := x"23";
constant AD9648_Grade : std_logic_vector(7 downto 0) := x"40";
constant AD9204_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9608_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9231_Grade : std_logic_vector(7 downto 0) := x"10";
constant AD9628_Grade : std_logic_vector(7 downto 0) := x"50";
constant AD9251_Grade : std_logic_vector(7 downto 0) := x"10";
-- number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 3;
-- command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (x"800200", -- read chip grade
x"800100", -- read chip ID
x"00003C", -- write SPI Port Config
x"000000" -- dummy
);
-- number of commands expected to be returned and loaded in the RX command FIFO of
-- the CommandFIFO module by the AD9648_SPI_Module in the tb_TestConfigADC test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
type CalibCoef_t is record
LgMultCoef : std_logic_vector (17 downto 0);
LgAddCoef : std_logic_vector (17 downto 0);
HgMultCoef : std_logic_vector (17 downto 0);
HgAddCoef : std_logic_vector (17 downto 0);
end record;
type RelayConfig_t is record
CouplingConfig : std_logic;
GainConfig : std_logic;
end record;
constant kCmdWrTotal_AD9648 : integer := 19;
constant kCmdWrTotal_AD9204 : integer := 19;
constant kCmdWrTotal_AD9608 : integer := 19;
constant kCmdWrTotal_AD9231 : integer := 19;
constant kCmdWrTotal_AD9628 : integer := 19;
constant kCmdWrTotal_AD9251 : integer := 19;
constant kCmdReadID_Index : integer := 1; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
constant kCmdClkDivIndex : integer := 10; --Clock Divide command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 290ms (with a clock frequency of 100MHz) to allow the ADC's
-- transition from power down to normal operation (ConfigADC.vhd).
-- 290ms value is computed from:
-- https://www.analog.com/media/en/technical-documentation/data-sheets/ad9648.pdf page 40,
-- "The pseudo code sequence for a digital reset":
-- 2.9e6 sample clock cycles @ 10MHz minimum sampling clock frequency (for ZmodScope) = 290ms
constant kCountResetResume : unsigned := to_unsigned (28999999, 25);
-- Smaller version of the kCountResetResume, used only for simulation purposes.
-- (999 + 1) clock cycles @ 100MHz frequency means 10us.
constant kCountResetResumeSim : unsigned := to_unsigned (999, 25);
-- Constant used to measure 4ms (with a clock frequency of 100MHz) that allows to
-- determine the timin intervals for the relay drive signals (ConfigRelays.vhd)
constant kCount4ms : unsigned := to_unsigned (399999, 24);
-- Smaller version of the kCount4ms, used only for simulation purposes.
-- (399 + 1) clock cycles @ 100MHz frequency means 4us.
constant kCount4msSim : unsigned := to_unsigned (399, 24);
-- Constant used to measure 5ms with a clock frequency of 100MHz
-- Used to determine the ADC calibration timeout condition (tb_TestConfigADC.vhd and tb_TestTop.vhd)
constant kCount5ms : integer := 500000;
-- Constant used to measure 291ms (with a clock frequency of 100MHz) that determines a
-- timeout condition on the ADC's SPI interface (ConfigADC.vhd)
-- This value has to be larger than kCountResetResume, otherwise false timeouts on the ADC
-- SPI interface will occur (i.e. after an ADC soft reset is performed).
constant kCfgTimeout : unsigned := to_unsigned (29099999, 25);
type FsmStatesADC_t is (StStart, StCheckCmdCnt, StWriteSoftReset, StWaitDoneRst, StReadPortConfig,
StCheckResetDone, StReadID, StWaitDoneID, StWriteControlReg, StWaitDoneWriteReg,
StWaitDoneReadReg, StReadControlReg, StResetTimer, StWaitRecover, StInitDone, StIdle,
StError, StExtSPI_RdCmd, StExtSPI_WrCmd, StWaitDoneExtWrReg,
StWaitDoneExtRdReg, StRegExtRxData, StSetTrsfReg, StWaitDoneTrsfReg, StReadTrsfReg, StWaitDoneTrsfRegRd);
type FsmStatesRelays_t is (StStart, StConfigCouplingCh1, StConfigCouplingCh1Rst, StConfigCouplingCh2,
StConfigCouplingCh2Rst, StConfigGainCh1, StConfigGainCh1Rst, StConfigGainCh2,
StConfigGainCh2Rst, StPushInitDone, StWaitRdy, StIdle, StError, StWaitAckCouplingCh1,
StChangeCouplingCh1, StWaitAckCouplingCh2, StChangeCouplingCh2, StWaitAckGainCh1,
StChangeGainCh1, StWaitAckGainCh2, StChangeGainCh2, StRstCfgPulse);
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
constant kRangeLg : real := 26.25;
constant kRangeHg : real := 1.086;
constant kRangeIdealLg : real := 25.0;
constant kRangeIdealHg : real := 1.0;
-- Function used to determine the Chip ID based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_ID(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Chip grade based on the ZmodIC parameter
-- that identifies the Zmod.
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector;
-- Function used to determine the Clock devide ratio field of register 0x0B
-- based on the kADC_ClkDiv generic
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector;
-- The initiaization command list is different depending on which Zmod is targeted.
-- The SelCmdList function is used to select the appropriate command list based on
-- the ZmodIC parameter.
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t;
-- The initiaization command readback list is different depending on which Zmod is
-- targeted. The SelCmdList function is used to select the appropriate command list
-- based on the ZmodIC parameter.
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t;
-- The OverwriteClkDiv function is used to overwrite the Clock divide ratio field of commad list
-- (CmdList) sent as parameter based on ADC_ClkDiv. It is important to note that the "write
-- Clock Divide register" (address 0x0B) command shares the same position (kCmdClkDivIndex) in
-- the command list for the currently supported Zmods.
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t;
-- The OverWriteID_ClkDiv function is used to overwrite the ADC chip ID field of the
-- command readback list (RdbkList) based on the ZmodIC parameter.
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t;
-- The SelCmdWrListLength function is used to detrmine the command list
-- length based on the ZmodIC parameter.
function SelCmdWrListLength(ZmodIC:integer)
return integer;
-- Function used to determine the ADC resolution (kADC_Width) based on the ZmodIC parameter.
-- Used in the top level test bench.
function SelADC_Width(ZmodIC:integer)
return integer;
-- Function used to compute the IDDR sampling clock phase as a function of the sampling
-- period. This is necessary so the clock phase is always an integer multiple of
-- (45 degrees/output clock division factor) of the MMCM which generates it.
function IDDR_ClockPhase(SamplingPeriod:real)
return real;
end PkgZmodADC;
package body PkgZmodADC is
function SelADC_ID(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return AD9648_ID;
when kZmodScope1010_40 =>
return AD9204_ID;
when kZmodScope1010_125 =>
return AD9608_ID;
when kZmodScope1210_40 =>
return AD9231_ID;
when kZmodScope1210_125 =>
return AD9628_ID;
when kZmodScope1410_40 =>
return AD9251_ID;
when kZmodScope1410_125 =>
return AD9648_ID;
when others =>
return x"00";
end case;
end function;
function SelADC_Grade(ZmodIC:integer)
return std_logic_vector is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return AD9648_Grade;
when kZmodScope1010_40 =>
return AD9204_Grade;
when kZmodScope1010_125 =>
return AD9608_Grade;
when kZmodScope1210_40 =>
return AD9231_Grade;
when kZmodScope1210_125 =>
return AD9628_Grade;
when kZmodScope1410_40 =>
return AD9251_Grade;
when kZmodScope1410_125 =>
return AD9648_Grade;
when others =>
return x"00";
end case;
end function;
function DetClkDiv(ADC_ClkDiv:integer)
return std_logic_vector is
begin
if (ADC_ClkDiv = 1) then
return x"00";
elsif (ADC_ClkDiv = 2) then
return x"01";
elsif (ADC_ClkDiv = 3) then
return x"02";
elsif (ADC_ClkDiv = 4) then
return x"03";
elsif (ADC_ClkDiv = 5) then
return x"04";
elsif (ADC_ClkDiv = 6) then
return x"05";
elsif (ADC_ClkDiv = 7) then
return x"06";
elsif (ADC_ClkDiv = 8) then
return x"07";
else
return x"00";
end if;
end function;
function SelCmdList(ZmodIC:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := kAD96xx_SPI_Cmd;
begin
case ZmodIC is
when kZmodScope1410_105 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1010_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1010_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1210_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1210_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when kZmodScope1410_40 =>
CmdListV := kAD92xx_SPI_Cmd;
return CmdListV;
when kZmodScope1410_125 =>
CmdListV := kAD96xx_SPI_Cmd;
return CmdListV;
when others =>
CmdListV := (others => (others => '0'));
return CmdListV;
end case;
end function;
function SelRdbkList(ZmodIC:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := kAD96xx_SPI_Rdbck;
begin
case ZmodIC is
when kZmodScope1410_105 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1010_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1010_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1210_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1210_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1410_40 =>
RdbkListV := kAD92xx_SPI_Rdbck;
return RdbkListV;
when kZmodScope1410_125 =>
RdbkListV := kAD96xx_SPI_Rdbck;
return RdbkListV;
when others =>
RdbkListV := (others => (others => '0'));
return RdbkListV;
end case;
end function;
function OverwriteClkDiv(CmdList:ADC_SPI_Commands_t; ADC_ClkDiv:integer)
return ADC_SPI_Commands_t is
variable CmdListV : ADC_SPI_Commands_t := CmdList;
begin
CmdListV(kCmdClkDivIndex) := CmdList(kCmdClkDivIndex)(23 downto 8) & DetClkDiv(ADC_ClkDiv);
return CmdListV;
end function;
function OverWriteID_ClkDiv(ZmodIC:integer; RdbkList:ADC_SPI_Readback_t; ADC_ClkDiv:integer)
return ADC_SPI_Readback_t is
variable RdbkListV : ADC_SPI_Readback_t := RdbkList;
begin
RdbkListV(kCmdClkDivIndex) := DetClkDiv(ADC_ClkDiv);
case ZmodIC is
when kZmodScope1410_105 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when kZmodScope1010_40 =>
RdbkListV(kCmdReadID_Index) := AD9204_ID;
return RdbkListV;
when kZmodScope1010_125 =>
RdbkListV(kCmdReadID_Index) := AD9608_ID;
return RdbkListV;
when kZmodScope1210_40 =>
RdbkListV(kCmdReadID_Index) := AD9231_ID;
return RdbkListV;
when kZmodScope1210_125 =>
RdbkListV(kCmdReadID_Index) := AD9628_ID;
return RdbkListV;
when kZmodScope1410_40 =>
RdbkListV(kCmdReadID_Index) := AD9251_ID;
return RdbkListV;
when kZmodScope1410_125 =>
RdbkListV(kCmdReadID_Index) := AD9648_ID;
return RdbkListV;
when others =>
RdbkListV(kCmdReadID_Index) := x"00";
return RdbkListV;
end case;
end function;
function SelCmdWrListLength(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return kCmdWrTotal_AD9648;
when kZmodScope1010_40 =>
return kCmdWrTotal_AD9204;
when kZmodScope1010_125 =>
return kCmdWrTotal_AD9608;
when kZmodScope1210_40 =>
return kCmdWrTotal_AD9231;
when kZmodScope1210_125 =>
return kCmdWrTotal_AD9628;
when kZmodScope1410_40 =>
return kCmdWrTotal_AD9251;
when kZmodScope1410_125 =>
return kCmdWrTotal_AD9648;
when others =>
return 0;
end case;
end function;
function SelADC_Width(ZmodIC:integer)
return integer is
begin
case ZmodIC is
when kZmodScope1410_105 =>
return 14;
when kZmodScope1010_40 =>
return 10;
when kZmodScope1010_125 =>
return 10;
when kZmodScope1210_40 =>
return 12;
when kZmodScope1210_125 =>
return 12;
when kZmodScope1410_40 =>
return 14;
when kZmodScope1410_125 =>
return 14;
when others =>
return 14;
end case;
end function;
function IDDR_ClockPhase(SamplingPeriod:real)
return real is
begin
--400MHz to 200MHz
if ((SamplingPeriod > 2.5) and (SamplingPeriod <= 5.0)) then
return 120.0;
--200MHz to 111MHz
elsif ((SamplingPeriod > 5.0) and (SamplingPeriod <= 9.0)) then
return 127.5;
--111MHz to 100MHz
elsif ((SamplingPeriod > 9.0) and (SamplingPeriod <= 10.0)) then
return 120.0;
--100MHz to 50MHz
elsif ((SamplingPeriod > 10.0) and (SamplingPeriod <= 20.0)) then
return 123.75;
--50MHz to 25MHz
elsif ((SamplingPeriod > 20.0) and (SamplingPeriod <= 40.0)) then
return 125.625;
--25MHz to 12.5MHz
elsif ((SamplingPeriod > 40.0) and (SamplingPeriod <= 80.0)) then
return 125.625;
--12.5MHz to 10MHz
elsif (SamplingPeriod > 80.0) then
return 125.859375;
--Out of specifications;
else
return 1.0;
end if;
end function;
end PkgZmodADC; |
-- $Id: $
-- File name: tristate.vhd
-- Created: 4/8/2012
-- Author: John Wyant
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Runs the tristate for the bidirectional wires between the usb
-- and intercept and between the computer and interceptor.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
entity tristate is
port ( lock, interceptorOutput : in std_logic;
interceptorInput : out std_logic;
dataLine : inout std_logic);
end tristate;
architecture behavioral of tristate is
begin
-- output to bus logic
dataLine <= interceptorOutput when lock = '1'
else 'Z';
-- input from bus logic
interceptorInput <= '1' when (dataLine = '1' and lock = '0') or lock = '1'
else '0';
end architecture; |
-- Automatically generated: write_netlist -preliminary -vhdl -component reconflogic-cmp.vhd
component MyReconfigLogic
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0);
I2C_Busy_i : in std_logic;
I2C_DataIn_o : out std_logic_vector(7 downto 0);
I2C_DataOut_i : in std_logic_vector(7 downto 0);
I2C_Divider800_o : out std_logic_vector(15 downto 0);
I2C_ErrAckParam_o : out std_logic;
I2C_Error_i : in std_logic;
I2C_F100_400_n_o : out std_logic;
I2C_FIFOEmpty_i : in std_logic;
I2C_FIFOFull_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(3 downto 0);
I2C_ReceiveSend_n_o : out std_logic;
I2C_StartProcess_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
ReconfModuleIRQs_o : out std_logic_vector(4 downto 0);
SPI_CPHA_o : out std_logic;
SPI_CPOL_o : out std_logic;
SPI_DataIn_o : out std_logic_vector(7 downto 0);
SPI_DataOut_i : in std_logic_vector(7 downto 0);
SPI_FIFOEmpty_i : in std_logic;
SPI_FIFOFull_i : in std_logic;
SPI_LSBFE_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0);
SPI_Transmission_i : in std_logic;
SPI_Write_o : out std_logic;
ReconfModuleIn_i : in std_logic_vector(7 downto 0);
ReconfModuleOut_o : out std_logic_vector(7 downto 0);
I2C_Errors_i : in std_logic_vector(7 downto 0);
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgIntfDOut_o : out std_logic_vector(15 downto 0);
ParamIntfDOut_o : out std_logic_vector(15 downto 0)
);
end component;
|
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`protect end_protected
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ed_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ed_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:07 wig Exp $
-- $Date: 2004/04/06 10:50:07 $
-- $Log: inst_ed_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:07 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ed_e
--
architecture rtl of inst_ed_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eda_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eda_e
cgs_ramclk : out std_ulogic;
nreset : out std_ulogic;
nreset_s : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_eda_e
);
end component;
-- ---------
component inst_edb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_edb_e
acg_systime_init : in std_ulogic_vector(30 downto 0);
cgu_scani : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
cgu_scano : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio0_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio1_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ifu_gpio2_wkup : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nreset : in std_ulogic;
nreset_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_edb_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal acg_systime_init : std_ulogic_vector(30 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal cgs_ramclk : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal gpio_int : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal itm_scani : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_scano : std_ulogic_vector(70 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal vclkl27 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
acg_systime_init <= p_mix_acg_systime_init_30_0_gi; -- __I_I_BUS_PORT
p_mix_cgs_ramclk_go <= cgs_ramclk; -- __I_O_BIT_PORT
gpio_int(2 downto 0) <= p_mix_gpio_int_2_0_gi(2 downto 0); -- __I_I_SLICE_PORT
itm_scani(0) <= p_mix_itm_scani_0_0_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_nreset_go <= nreset; -- __I_O_BIT_PORT
p_mix_nreset_s_go <= nreset_s; -- __I_O_BIT_PORT
p_mix_tmi_scano_0_0_go <= tmi_scano(0); -- __I_O_SLICE_PORT -- __W_SINGLE_BIT_SLICE
p_mix_vclkl27_go <= vclkl27; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eda
inst_eda: inst_eda_e
port map (
cgs_ramclk => cgs_ramclk, -- ClockSignalsESDRAMInterface
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eda
-- Generated Instance Port Map for inst_edb
inst_edb: inst_edb_e
port map (
acg_systime_init => acg_systime_init, -- ADPinterfaceScan
cgu_scani => itm_scani(0),
cgu_scano => tmi_scano(0),
ifu_gpio0_wkup => gpio_int(0), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio1_wkup => gpio_int(1), -- GPIOWakeUPSignalsInterruptinputs
ifu_gpio2_wkup => gpio_int(2), -- GPIOWakeUPSignalsInterruptinputs
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_edb
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
use work.average_calculator_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity average_calculator is
generic(
UNSIGNED_2COMP_opt : boolean := false; --default
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
ROUND_STYLE_opt : T_round_style := fixed_truncate; --default
ROUND_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
MAX_ERROR_PCT_opt : real_exc := real'low; --exception: value not set
S : positive --compulsory
);
port(
input : in sulv_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out std_ulogic_vector; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture average_calculator1 of average_calculator is
constant P : positive := input'length(1);
constant NORM_IN_HIGH : integer := input(1)'high-SULV_NEW_ZERO;
constant NORM_IN_LOW : integer := input(1)'low-SULV_NEW_ZERO;
/* constant CHECKS : integer := average_calculator_CHECKS();*/
constant INTER_HIGH : integer := average_calculator_IH(S,
P,
NORM_IN_HIGH);
constant INTER_LOW : integer := average_calculator_IL(ROUND_TO_BIT_opt,
NORM_IN_LOW);
constant NORM_OUT_HIGH : integer := average_calculator_OH(UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant NORM_OUT_LOW : integer := average_calculator_OL(UNSIGNED_2COMP_opt,
ROUND_STYLE_opt,
ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt,
S,
P,
NORM_IN_HIGH,
NORM_IN_LOW);
constant OUT_HIGH : integer := NORM_OUT_HIGH + SULV_NEW_ZERO;
constant OUT_LOW : integer := NORM_OUT_LOW + SULV_NEW_ZERO;
signal aux_input_s : u_sfixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
signal aux_input_u : u_ufixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW);
signal aux_output_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW);
/*================================================================================================*/
/*================================================================================================*/
begin
average_calculator_selection:
if UNSIGNED_2COMP_opt generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_u(i) <= to_ufixed(input(i), aux_input_u(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= std_ulogic_vector(aux_output_u);
average_calculator_u1:
entity work.average_calculator_u
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_u,
valid_input => valid_input,
start => start,
output => aux_output_u,
valid_output => valid_output
);
end;
else generate
begin
generate_input:
for i in 1 to P generate
begin
aux_input_s(i) <= to_sfixed(input(i), aux_input_s(i));
end;
end generate;
output(OUT_HIGH downto OUT_LOW)
<= std_ulogic_vector(aux_output_s);
average_calculator_s1:
entity work.average_calculator_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
ROUND_STYLE_opt => ROUND_STYLE_opt,
ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
S => S
)
port map(
clk => clk,
input => aux_input_s,
valid_input => valid_input,
start => start,
output => aux_output_s,
valid_output => valid_output
);
end;
end generate;
end architecture; |
-- file: SysPLL_k7.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____60.000
-- CLK_OUT1____15.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_k7 is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_k7;
architecture xilinx of SysPLL_k7 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_k7,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN1_P,
IB => CLK_IN1_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 10,
CLKFBOUT_MULT_F => 51.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 17.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 68,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
CLK_OUT2 <= clkout1;
end xilinx;
|
-- file: SysPLL_k7.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____60.000
-- CLK_OUT1____15.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_k7 is
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_k7;
architecture xilinx of SysPLL_k7 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_k7,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN1_P,
IB => CLK_IN1_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 10,
CLKFBOUT_MULT_F => 51.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 17.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 68,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
CLK_OUT2 <= clkout1;
end xilinx;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY overflowTest IS
END overflowTest;
ARCHITECTURE behavior OF overflowTest IS
COMPONENT overflow
PORT(
entrada1 : IN std_logic_vector(2 downto 0);
entrada2 : IN std_logic_vector(2 downto 0);
cin : IN std_logic;
saida1 : IN std_logic_vector(2 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal entrada1 : std_logic_vector(2 downto 0) := (others => '0');
signal entrada2 : std_logic_vector(2 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal saida1 : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: overflow PORT MAP (
entrada1 => entrada1,
entrada2 => entrada2,
cin => cin,
saida1 => saida1,
cout => cout
);
-- Clock process definitions
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
saida1 <= entrada1;
wait for <clock>_period*10;
entada2 <= "111";
saida1 <= entrada2;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dma_ctrl is
generic(
DWIDTH : natural; -- 8
RD_CYCLE : natural; -- 1
RD_DELAY : natural; -- 1
RAM_AWIDTH : natural
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector(DWIDTH - 1 downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector(DWIDTH - 1 downto 0)
);
end entity;
architecture behave of dma_ctrl is
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
signal length_reg : std_logic_vector(15 downto 0);
signal start_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal start_raddr_reg : std_logic_vector(23 downto 0);
signal start_raddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wstep_reg : std_logic_vector(7 downto 0);
signal rstep_reg : std_logic_vector(7 downto 0);
signal busy_buf : std_logic;
signal cycle_cnt : std_logic_vector(7 downto 0);
signal cnt : std_logic_vector(15 downto 0);
signal rden_buf : std_logic;
-- signal raddr_buf : std_logic_vector(23 downto 0);
signal raddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wren_buf : std_logic;
signal waddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal rd_start : std_logic;
signal wr_start : std_logic;
signal rd_ctrl : std_logic_vector(1 downto 0);
signal wr_ctrl : std_logic_vector(1 downto 0);
begin
-- DMA Status
process(clk, reset)
begin
if reset = '1' then
length_reg <= (others => '0');
start_waddr_reg <= (others => '0');
start_raddr_reg <= (others => '0');
wstep_reg <= (others => '0');
rstep_reg <= (others => '0');
elsif rising_edge(clk) then
if start = '1' then
length_reg <= length;
start_waddr_reg <= start_waddr;
start_raddr_reg <= start_raddr;
wstep_reg <= wstep;
rstep_reg <= rstep;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
busy_buf <= '0';
elsif rising_edge(clk) then
if start = '1' then
busy_buf <= '1';
elsif cnt = length_reg and cycle_cnt = RD_CYCLE - 1 then
busy_buf <= '0';
end if;
end if;
end process;
busy <= busy_buf;
process(clk, reset)
begin
if reset = '1' then
cycle_cnt <= (others => '0');
elsif rising_edge(clk) then
if busy_buf = '1' and ena = '1' then
if cycle_cnt = RD_CYCLE - 1 then
cycle_cnt <= (others => '0');
else
cycle_cnt <= cycle_cnt + 1;
end if;
else
cycle_cnt <= (others => '0');
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
cnt <= X"0000";
elsif rising_edge(clk) then
if start = '1' then
cnt <= X"0001";
elsif busy_buf = '1' and ena = '1' and cycle_cnt = RD_CYCLE - 1 then
cnt <= cnt + 1;
end if;
end if;
end process;
-- Read Ctrl
process(clk, reset)
begin
if reset = '1' then
rden_buf <= '0';
elsif rising_edge(clk) then
if busy_buf = '1' and ena = '1' and cycle_cnt = RD_CYCLE - 1 and cnt < length_reg then
rden_buf <= '1';
else
rden_buf <= '0';
end if;
end if;
end process;
-- process(clk, reset)
-- begin
-- if reset = '1' then
-- raddr_buf <= (others => '0');
-- elsif rising_edge(clk) then
-- if rd_start = '1' then
-- raddr_buf <= start_raddr_reg;
-- elsif rden_buf = '1' then
-- raddr_buf <= raddr_buf + rstep_reg;
-- end if;
-- end if;
-- end process;
process(clk, reset)
begin
if reset = '1' then
raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if rd_start = '1' then
raddr_buf <= start_raddr_reg;
elsif rden_buf = '1' then
raddr_buf <= raddr_buf + rstep_reg;
end if;
end if;
end process;
raddr <= raddr_buf;
-- Write Ctrl
u_wr_ctrl : shiftreg
generic map(
width => 2,
depth => RD_DELAY + RD_CYCLE -- 100M RD_DELAY ??? a4a881d4
)
port map(
clk => clk,
ce => '1',
D => rd_ctrl,
Q => wr_ctrl,
S => open
);
rd_ctrl(0) <= rden_buf;
rd_ctrl(1) <= rd_start;
wren_buf <= wr_ctrl(0);
wr_start <= wr_ctrl(1);
process(clk, reset)
begin
if reset = '1' then
waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if wr_start = '1' then
waddr_buf <= start_waddr_reg;
elsif wren_buf = '1' then
waddr_buf <= waddr_buf + wstep_reg;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
rd_start <= start;
wren <= wr_start or wren_buf;
end if;
end process;
waddr <= waddr_buf;
wdata <= rdata;
end behave;
|
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
entity signal12 is
end entity;
architecture test of signal12 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
signal a : bit_vector(7 downto 0);
signal b : byte_vec(1 to 3);
begin
assign: b <= (others => a);
process is
begin
a <= X"01";
wait for 1 ns;
assert b(1) = X"01";
assert b(2) = X"01";
assert b(3) = X"01";
a <= X"f0";
wait for 1 ns;
assert b(1) = X"f0";
assert b(2) = X"f0";
assert b(3) = X"f0";
wait;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY distortion_component_tb IS
END distortion_component_tb;
--1111110010011001
--1111101110100100
--1111101110000100
--1111110000111111
--1111110110111000
--1111111110110000
--0000000111001111
--0000001110111000
--0000010100010001
--0000010110010101
--0000010100100000
ARCHITECTURE behavior OF distortion_component_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT distort --'distortion_component' is the name of the module needed to be tested.
--just copy and paste the input and output ports of your module as such.
PORT(
data_in : in std_logic_vector(15 downto 0); -- 16-bit data stream input
dist_en : in std_logic; -- 1-bit distortion enable signal
clipping_value: in std_logic_vector(15 downto 0); -- 16-bit input clipping threshold
clk : in std_logic;
reset : in std_logic;
data_out: out std_logic_vector(15 downto 0) -- 16-bit data stream output (either clipped or not)
);
END COMPONENT;
--declare inputs and initialize them
signal data_in : std_logic_vector(15 downto 0) := "0000000000000000";
signal dist_en : std_logic := '1';
signal clipping_value : std_logic_vector(15 downto 0) := "0000001111101000"; -- Clipped at 1000
signal clk : std_logic := '0';
signal reset : std_logic := '1';
--declare outputs and initialize them
signal data_out: std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 1 ns;
BEGIN
uut: distort PORT MAP (
clk => clk,
reset => reset,
data_in => data_in,
dist_en => dist_en,
clipping_value => clipping_value,
data_out => data_out
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 0.5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 0.5 ns signal is '1'.
end process;
stim_proc: process
begin
wait for 10 ns;
data_in <="1111110010011001";
wait for 10 ns;
data_in <="1111101110100100";
wait for 10 ns;
data_in <="1111101110000100";
wait for 10 ns;
data_in <="0111110000111111";
wait for 10 ns;
data_in <="1111110110111000";
wait for 10 ns;
data_in <="1111111110110000";
wait for 10 ns;
data_in <="1111110000111111";
wait for 10 ns;
data_in <="0000000111001111";
wait for 10 ns;
data_in <="0000001110111000";
wait for 10 ns;
data_in <="0000010100010001";
wait for 10 ns;
data_in <="0000010110010101";
wait for 10 ns;
data_in <="0000010100100000";
wait for 10 ns;
report "Test bench Complete";
wait;
end process stim_proc;
END behavior; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p03n01i00003ent IS
END c04s01b00x00p03n01i00003ent;
ARCHITECTURE c04s01b00x00p03n01i00003arch OF c04s01b00x00p03n01i00003ent IS
type t1 (l,m,n); -- Error: missing 'is'
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p03n01i00003 - The reserved word 'is' is missing in the type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p03n01i00003arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p03n01i00003ent IS
END c04s01b00x00p03n01i00003ent;
ARCHITECTURE c04s01b00x00p03n01i00003arch OF c04s01b00x00p03n01i00003ent IS
type t1 (l,m,n); -- Error: missing 'is'
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p03n01i00003 - The reserved word 'is' is missing in the type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p03n01i00003arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s01b00x00p03n01i00003ent IS
END c04s01b00x00p03n01i00003ent;
ARCHITECTURE c04s01b00x00p03n01i00003arch OF c04s01b00x00p03n01i00003ent IS
type t1 (l,m,n); -- Error: missing 'is'
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s01b00x00p03n01i00003 - The reserved word 'is' is missing in the type declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s01b00x00p03n01i00003arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant use_eth_data_output_delay : integer := 0;
constant use_eth_input_delay_clk : integer := 0;
constant use_gtx_clk : integer := 0;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal leds : std_logic_vector(3 downto 0); -- I/O port
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
end generate;
noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
erx_clk0 : if (use_eth_input_delay_clk /= 0) generate
delay_rgmii_rx_clk : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_clk,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_clk,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 10 -- (See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
end generate;
ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
DATA_RATE => "DDR",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0,
pirq => 15, use90degtxclk => 0)
port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erx_clk1 : if (use_eth_input_delay_clk = 0) generate
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
end generate;
erx_clk2 : if (use_eth_input_delay_clk /= 0) generate
erxc_pad : inpad generic map (tech => padtech)
port map (erx_clk, rgmii_pad.rx_clk);
erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk);
end generate;
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
gtx_clk0 : if (use_gtx_clk = 0) generate
-- Use MIG PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
gtx_clk1 : if (use_gtx_clk = 1) generate
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 3)
port map (clk125, rgmiii.gtx_clk);
end generate;
gtx_clk2 : if (use_gtx_clk = 2) generate
-- Use Separate PLL
-- Add to UCF (only if there is no BUFG left):
-- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE;
-- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE;
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen0 : clkgen -- clock generator
generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open);
clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll);
rgmiii.gtx_clk <= clk_125_bufg;
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
-- MIPS I CPU - General Purpose Register --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpr is
port(
clk_i : in std_logic;
hld_i : in std_logic;
rs_a : in std_logic_vector(4 downto 0);
rt_a : in std_logic_vector(4 downto 0);
rd_a : in std_logic_vector(4 downto 0);
rd_we : in std_logic;
rd_i : in std_logic_vector(31 downto 0);
rs_o : out std_logic_vector(31 downto 0);
rt_o : out std_logic_vector(31 downto 0)
);
end gpr;
architecture rtl of gpr is
type gpr_t is array (0 to 31) of std_logic_vector(31 downto 0);
signal gpr : gpr_t := (others => (others => '0'));
attribute RAM_STYLE : string;
attribute RAM_STYLE of gpr: signal is "BLOCK";
begin
reg : process(clk_i)
begin
if rising_edge(clk_i) then
if (hld_i = '0') then
-- Save data only if it's register address is not zero.
-- Keeps register $0 zero.
if (rd_we = '1') and (rd_a /= "00000") then
gpr( to_integer(unsigned(rd_a)) ) <= rd_i;
end if;
rs_o <= gpr( to_integer(unsigned(rs_a)) );
rt_o <= gpr( to_integer(unsigned(rt_a)) );
end if;
end if;
end process;
end rtl; |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
end block;
a <= b;
BLOCK_LABEL : block is
begin
end block;
a <= b;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc268.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00268ent IS
END c03s01b03x00p02n01i00268ent;
ARCHITECTURE c03s01b03x00p02n01i00268arch OF c03s01b03x00p02n01i00268ent IS
type UPLE is range 1 to 8
units
single;
double; -- Failure_here
-- SYNTAX ERROR: MORE THAN ONE BASE UNIT DECLARATION
triple = 3 single;
quadruple = 2 double;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p02n01i00268 - Only one base type declaration allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00268arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc268.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00268ent IS
END c03s01b03x00p02n01i00268ent;
ARCHITECTURE c03s01b03x00p02n01i00268arch OF c03s01b03x00p02n01i00268ent IS
type UPLE is range 1 to 8
units
single;
double; -- Failure_here
-- SYNTAX ERROR: MORE THAN ONE BASE UNIT DECLARATION
triple = 3 single;
quadruple = 2 double;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p02n01i00268 - Only one base type declaration allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00268arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc268.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p02n01i00268ent IS
END c03s01b03x00p02n01i00268ent;
ARCHITECTURE c03s01b03x00p02n01i00268arch OF c03s01b03x00p02n01i00268ent IS
type UPLE is range 1 to 8
units
single;
double; -- Failure_here
-- SYNTAX ERROR: MORE THAN ONE BASE UNIT DECLARATION
triple = 3 single;
quadruple = 2 double;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p02n01i00268 - Only one base type declaration allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p02n01i00268arch;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A0123712
--
-- Create Date: 09:13:49 10/13/2015
-- Design Name:
-- Module Name: Shift_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implementation of a 8 bit shift register
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Shift_Register is
Port ( Clk : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Clr : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (0 to 7));
end Shift_Register;
architecture Behavioral of Shift_Register is
--Embedded signal
--signal Reg : BIT_VECTOR (0 to 7);
signal Reg : STD_LOGIC_VECTOR (0 to 7);
signal AnB : STD_LOGIC;
--frequency devider
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 1; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
signal ClkOut : STD_LOGIC;
signal ret : STD_LOGIC;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de 1 Hz
process (Clr, Clk)
begin
if Clr = '0' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
-- Describe the shift-right register
AnB <= A and B;
shift_reg: process(Clk, Clr, ClkOut)
begin
if (Clr = '0') then
Reg <= (others => '0');
elsif (rising_edge(Clk) and ClkOut='1') then
Reg <= (AnB & Reg(0 to 6));
end if;
end process shift_reg;
Q <= Reg;
-- Describe the shift-left register
-- AnB <= A and B;
-- shift_reg: process(Clk, Clr, ClkOut)
-- begin
-- if (Clr = '0') then
-- Reg <= (others => '0');
-- elsif (rising_edge(Clk) and ClkOut='1') then
-- Reg <= (Reg(1 to 7) & AnB);
--
-- end if;
-- end process shift_reg;
-- Q <= Reg;
-- Describe the shift-left-rigth register
--
-- shift_reg: process(Clk, Clr, ClkOut, ret)
-- begin
-- if (Clr = '0') then
-- Reg <= (others => '0');
-- Reg(0) <= '1';
-- ret <= '0';
-- elsif (rising_edge(Clk) and ClkOut='1') then
-- if ret = '1' then
-- Reg <= (Reg(1 to 7) & '0');
-- --Reg <= Reg sll 1;
-- else
-- Reg <= ('0' & Reg(0 to 6));
-- --Reg <= Reg srl 1;
-- end if;
-- if Reg = "00000010" then
-- ret <= '1';
-- end if;
-- if Reg = "01000000" then
-- ret <= '0';
-- end if;
-- end if;
-- end process shift_reg;
-- --Q <= To_StdLogicVector(Reg);
-- Q<= Reg;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01601ent IS
END c08s11b00x00p03n01i01601ent;
ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable counter : integer := 0;
BEGIN
L1 :
for i in boolean loop
L2 :
for j in 1 to 3 loop
exit L2 ;
p := 5 ;
end loop L2 ;
counter := counter + 1 ;
end loop L1 ;
assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***PASSED TEST: c08s11b00x00p03n01i01601"
severity NOTE;
assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01601arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01601ent IS
END c08s11b00x00p03n01i01601ent;
ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable counter : integer := 0;
BEGIN
L1 :
for i in boolean loop
L2 :
for j in 1 to 3 loop
exit L2 ;
p := 5 ;
end loop L2 ;
counter := counter + 1 ;
end loop L1 ;
assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***PASSED TEST: c08s11b00x00p03n01i01601"
severity NOTE;
assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01601arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01601ent IS
END c08s11b00x00p03n01i01601ent;
ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
variable counter : integer := 0;
BEGIN
L1 :
for i in boolean loop
L2 :
for j in 1 to 3 loop
exit L2 ;
p := 5 ;
end loop L2 ;
counter := counter + 1 ;
end loop L1 ;
assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***PASSED TEST: c08s11b00x00p03n01i01601"
severity NOTE;
assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1)))
report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01601arch;
|
-- file : test_fb2.vhdl
-- created by Yann Guidon / ygdes.com
-- version 2010/06/05
library work;
use work.fb_ghdl.all;
entity test_fb2 is
end test_fb2;
architecture test of test_fb2 is
begin
process
variable i,j:integer;
begin
-- affiche un carre cyan
for j in (fby/2)-100 to (fby/2)+100 loop
for i in (fbx/2)-100 to (fbx/2)+100 loop
pixel(j,i) := 16#FFFF#;
end loop;
end loop;
wait;
end process;
end test;
|
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|
-- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (ufixed(l), ufixed(r));
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report float_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector (to_sulv (arg));
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report float_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
|
-- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (ufixed(l), ufixed(r));
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report float_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector (to_sulv (arg));
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report float_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
|
-- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (ufixed(l), ufixed(r));
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report float_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector (to_sulv (arg));
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report float_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
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