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-- This VHDL was converted from Verilog using the
-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity subtract is
port (
a : in unsigned(3 downto 0);
b : in unsigned(3 downto 0);
out_sig : out unsigned(3 downto 0)
);
end entity;
architecture test of subtract is
begin
out_sig <= (a + not b) + 1;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi;
architecture behave of contact_discovery_results_out_m_axi is
component contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_write;
component contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_read;
component contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_results_out_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_results_out_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_results_out_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi_reg_slice;
architecture behave of contact_discovery_results_out_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_results_out_m_axi_fifo;
architecture behave of contact_discovery_results_out_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_results_out_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_results_out_m_axi_decoder;
architecture behav of contact_discovery_results_out_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_results_out_m_axi_throttl;
architecture behav of contact_discovery_results_out_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_read;
architecture behave of contact_discovery_results_out_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_write;
architecture behave of contact_discovery_results_out_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi;
architecture behave of contact_discovery_results_out_m_axi is
component contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_write;
component contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_read;
component contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_results_out_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_results_out_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_results_out_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi_reg_slice;
architecture behave of contact_discovery_results_out_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_results_out_m_axi_fifo;
architecture behave of contact_discovery_results_out_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_results_out_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_results_out_m_axi_decoder;
architecture behav of contact_discovery_results_out_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_results_out_m_axi_throttl;
architecture behav of contact_discovery_results_out_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_read;
architecture behave of contact_discovery_results_out_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_write;
architecture behave of contact_discovery_results_out_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi;
architecture behave of contact_discovery_results_out_m_axi is
component contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 1;
MAX_WRITE_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_write;
component contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 1;
MAX_READ_BURST_LENGTH : INTEGER := 1;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component contact_discovery_results_out_m_axi_read;
component contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component contact_discovery_results_out_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : contact_discovery_results_out_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : contact_discovery_results_out_m_axi_write
generic map (
NUM_WRITE_OUTSTANDING => NUM_WRITE_OUTSTANDING,
MAX_WRITE_BURST_LENGTH => MAX_WRITE_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : contact_discovery_results_out_m_axi_read
generic map (
NUM_READ_OUTSTANDING => NUM_READ_OUTSTANDING,
MAX_READ_BURST_LENGTH => MAX_READ_BURST_LENGTH,
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
-- system signals
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
-- slave side
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
-- master side
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end entity contact_discovery_results_out_m_axi_reg_slice;
architecture behave of contact_discovery_results_out_m_axi_reg_slice is
constant ZERO : STD_LOGIC_VECTOR(1 downto 0) := "10";
constant ONE : STD_LOGIC_VECTOR(1 downto 0) := "11";
constant TWO : STD_LOGIC_VECTOR(1 downto 0) := "01";
signal data_p1 : STD_LOGIC_VECTOR(N-1 downto 0);
signal data_p2 : STD_LOGIC_VECTOR(N-1 downto 0);
signal load_p1 : STD_LOGIC;
signal load_p2 : STD_LOGIC;
signal load_p1_from_p2 : STD_LOGIC;
signal s_ready_t : STD_LOGIC;
signal state : STD_LOGIC_VECTOR(1 downto 0);
signal next_st : STD_LOGIC_VECTOR(1 downto 0);
begin
s_ready <= s_ready_t;
m_data <= data_p1;
m_valid <= state(0);
load_p1 <= '1' when (state = ZERO and s_valid = '1') or
(state = ONE and s_valid = '1' and m_ready = '1') or
(state = TWO and m_ready = '1')
else '0';
load_p2 <= s_valid and s_ready_t;
load_p1_from_p2 <= '1' when state = TWO else '0';
data_p1_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p1 = '1') then
if (load_p1_from_p2 = '1') then
data_p1 <= data_p2;
else
data_p1 <= s_data;
end if;
end if;
end if;
end process;
data_p2_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (load_p2 = '1') then
data_p2 <= s_data;
end if;
end if;
end process;
s_ready_t_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
s_ready_t <= '0';
elsif (state = ZERO) then
s_ready_t <= '1';
elsif (state = ONE and next_st = TWO) then
s_ready_t <= '0';
elsif (state = TWO and next_st = ONE) then
s_ready_t <= '1';
end if;
end if;
end process;
state_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if (reset = '1') then
state <= ZERO;
else
state <= next_st;
end if;
end if;
end process;
next_st_proc : process (state, s_valid, s_ready_t, m_ready)
begin
case state is
when ZERO =>
if (s_valid = '1' and s_ready_t = '1') then
next_st <= ONE;
else
next_st <= ZERO;
end if;
when ONE =>
if (s_valid = '0' and m_ready = '1') then
next_st <= ZERO;
elsif (s_valid = '1' and m_ready = '0') then
next_st <= TWO;
else
next_st <= ONE;
end if;
when TWO =>
if (m_ready = '1') then
next_st <= ONE;
else
next_st <= TWO;
end if;
when others =>
next_st <= ZERO;
end case;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity contact_discovery_results_out_m_axi_fifo;
architecture behave of contact_discovery_results_out_m_axi_fifo is
signal push, pop, data_vld, full_cond : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
depth_nlt2 : if DEPTH >= 2 generate
full_cond <= '1' when push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' else '0';
end generate;
depth_lt2 : if DEPTH < 2 generate
full_cond <= '1' when push = '1' and pop = '0' else '0';
end generate;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if pop = '1' then
full_n_tmp <= '1';
elsif full_cond = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of contact_discovery_results_out_m_axi_buffer is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
signal q_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal usedw : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal q_tmp : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal show_ahead : std_logic := '0';
signal dout_buf : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal dout_valid : std_logic := '0';
attribute ram_style: string;
attribute ram_style of mem: signal is MEM_STYLE;
begin
if_full_n <= full_n;
if_empty_n <= dout_valid;
if_dout <= dout_buf;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_valid or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
elsif sclk_en = '1' then
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
elsif sclk_en = '1' then
raddr <= rnext;
end if;
end if;
end process;
-- usedw
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
usedw <= (others => '0');
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
usedw <= usedw + 1;
elsif push = '0' and pop = '1' then
usedw <= usedw - 1;
end if;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
if usedw = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif sclk_en = '1' then
if push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if usedw = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end if;
end process;
-- mem
process (clk) begin
if clk'event and clk = '1' then
if push = '1' then
mem(to_integer(waddr)) <= if_din;
end if;
end if;
end process;
-- q_buf
process (clk) begin
if clk'event and clk = '1' then
q_buf <= mem(to_integer(rnext));
end if;
end process;
-- q_tmp
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
q_tmp <= (others => '0');
elsif sclk_en = '1' then
if push = '1' then
q_tmp <= if_din;
end if;
end if;
end if;
end process;
-- show_ahead
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
show_ahead <= '0';
elsif sclk_en = '1' then
if push = '1' and (usedw = 0 or (usedw = 1 and pop = '1')) then
show_ahead <= '1';
else
show_ahead <= '0';
end if;
end if;
end if;
end process;
-- dout_buf
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_buf <= (others => '0');
elsif sclk_en = '1' then
if pop = '1' then
if show_ahead = '1' then
dout_buf <= q_tmp;
else
dout_buf <= q_buf;
end if;
end if;
end if;
end if;
end process;
-- dout_valid
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_valid <= '0';
elsif sclk_en = '1' then
if pop = '1' then
dout_valid <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity contact_discovery_results_out_m_axi_decoder;
architecture behav of contact_discovery_results_out_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
if (not(din = 0)) then
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity contact_discovery_results_out_m_axi_throttl;
architecture behav of contact_discovery_results_out_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_read is
generic (
NUM_READ_OUTSTANDING : INTEGER := 2;
MAX_READ_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_read;
architecture behave of contact_discovery_results_out_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant NUM_READ_WIDTH : INTEGER := log2(MAX_READ_BURST_LENGTH);
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_rreq_valid : STD_LOGIC;
signal rs2f_rreq_ack : STD_LOGIC;
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal ar2r_ardata : UNSIGNED(1 downto 0);
signal fifo_rctl_r : STD_LOGIC;
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 2 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal rs_rrsp_rdata : UNSIGNED(USER_DW + 1 downto 0);
signal rdata_data_pack : UNSIGNED(USER_DW + 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal ar2r_rdata : UNSIGNED(1 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal tmp_last : STD_LOGIC;
signal need_rlast : STD_LOGIC;
signal fifo_rctl_ready : STD_LOGIC;
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_ack_t : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
rs_rreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW+ 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rreq_data),
s_valid => rreq_valid,
s_ready => rreq_ack,
UNSIGNED(m_data)=> rs2f_rreq_data,
m_valid => rs2f_rreq_valid,
m_ready => rs2f_rreq_ack);
fifo_rreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_rreq_ack,
wrreq => rs2f_rreq_valid,
data => rs2f_rreq_data,
empty_n => fifo_rreq_valid,
rdreq => fifo_rreq_read,
q => fifo_rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_READ_BURST_LENGTH) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_sect else '0';
ar2r_ardata <= "10" when last_sect else "00";
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_READ_BURST_LENGTH) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_READ_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_READ_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' and fifo_rctl_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= RESIZE(sect_len_buf(NUM_READ_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_READ_BURST_LENGTH-1, 8);
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_rctl_r <= '1' when next_loop else '0';
ar2r_ardata <= "10" when last_loop else "00";
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => BUS_DATA_WIDTH + 3,
DEPTH => NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_READ_OUTSTANDING * MAX_READ_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => RREADY,
if_write_ce => '1',
if_write => RVALID,
if_din => STD_LOGIC_VECTOR(fifo_rresp_rdata),
if_empty_n => beat_valid,
if_read_ce => '1',
if_read => next_beat,
UNSIGNED(if_dout) => data_pack);
rs_rdata : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_DW + 2)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(rs_rrsp_rdata),
s_valid => rdata_valid_t,
s_ready => rdata_ack_t,
UNSIGNED(m_data) => rdata_data_pack,
m_valid => rdata_valid,
m_ready => rdata_ack);
fifo_rctl : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_READ_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_READ_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_rlast,
full_n => fifo_rctl_ready,
rdreq => tmp_last,
wrreq => fifo_rctl_r,
q => ar2r_rdata,
data => ar2r_ardata);
fifo_rresp_rdata <= (RLAST & RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
tmp_last <= data_pack(BUS_DATA_WIDTH + 2) and beat_valid;
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rs_rrsp_rdata <= resp_buf & data_buf(USER_DW - 1 downto 0);
rrsp <= rdata_data_pack(USER_DW + 1 downto USER_DW);
rdata_data <= rdata_data_pack(USER_DW - 1 downto 0);
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack_t = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity contact_discovery_results_out_m_axi_write is
generic (
NUM_WRITE_OUTSTANDING : INTEGER := 2;
MAX_WRITE_BURST_LENGTH : INTEGER := 16;
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity contact_discovery_results_out_m_axi_write;
architecture behave of contact_discovery_results_out_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
constant NUM_WRITE_WIDTH : INTEGER := log2(MAX_WRITE_BURST_LENGTH);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal rs2f_wreq_valid : STD_LOGIC;
signal rs2f_wreq_ack : STD_LOGIC;
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal aw2b_awdata : UNSIGNED(1 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal aw2b_bdata : UNSIGNED(1 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : STD_LOGIC;
signal last_resp : STD_LOGIC;
signal invalid_event : STD_LOGIC;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component contact_discovery_results_out_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component contact_discovery_results_out_m_axi_fifo;
component contact_discovery_results_out_m_axi_reg_slice is
generic (
N : INTEGER := 8);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
s_data : in STD_LOGIC_VECTOR(N-1 downto 0);
s_valid : in STD_LOGIC;
s_ready : out STD_LOGIC;
m_data : out STD_LOGIC_VECTOR(N-1 downto 0);
m_valid : out STD_LOGIC;
m_ready : in STD_LOGIC);
end component contact_discovery_results_out_m_axi_reg_slice;
component contact_discovery_results_out_m_axi_buffer is
generic (
MEM_STYLE : STRING := "block";
DATA_WIDTH : NATURAL := 32;
ADDR_WIDTH : NATURAL := 5;
DEPTH : NATURAL := 32
);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
if_full_n : out STD_LOGIC;
if_write_ce : in STD_LOGIC;
if_write : in STD_LOGIC;
if_din : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : out STD_LOGIC;
if_read_ce : in STD_LOGIC;
if_read : in STD_LOGIC;
if_dout : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_buffer;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
rs_wreq : contact_discovery_results_out_m_axi_reg_slice
generic map (
N => USER_AW + 32)
port map (
sclk => ACLK,
reset => ARESET,
s_data => STD_LOGIC_VECTOR(wreq_data),
s_valid => wreq_valid,
s_ready => wreq_ack,
UNSIGNED(m_data)=> rs2f_wreq_data,
m_valid => rs2f_wreq_valid,
m_ready => rs2f_wreq_ack);
fifo_wreq : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
full_n => rs2f_wreq_ack,
wrreq => rs2f_wreq_valid,
data => rs2f_wreq_data,
empty_n => fifo_wreq_valid,
rdreq => fifo_wreq_read,
q => fifo_wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
must_one_burst : if (BUS_DATA_BYTES >= 4096/MAX_WRITE_BURST_LENGTH) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_burst_ready = '1' and fifo_resp_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_sect else '0';
aw2b_awdata <= '1' & invalid_len_event when last_sect else '0' & invalid_len_event;
fifo_burst_w <= '1' when invalid_len_event = '0' and next_sect else '0';
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 4096/MAX_WRITE_BURST_LENGTH) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(11 - NUM_WRITE_WIDTH - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto NUM_WRITE_WIDTH));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= RESIZE(sect_len_buf(NUM_WRITE_WIDTH-1 downto 0), 8) when last_loop else
TO_UNSIGNED(MAX_WRITE_BURST_LENGTH-1, 8);
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop else '0';
aw2b_awdata <= '1' & invalid_len_event_2 when last_loop and last_sect_buf = '1' else '0' & invalid_len_event_2;
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
fifo_burst_w <= '1' when invalid_len_event_2 = '0' and next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
buff_wdata : contact_discovery_results_out_m_axi_buffer
generic map (
DATA_WIDTH => USER_DW + USER_DW/8,
DEPTH => NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH,
ADDR_WIDTH => log2(NUM_WRITE_OUTSTANDING * MAX_WRITE_BURST_LENGTH))
port map (
clk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
if_full_n => wdata_ack,
if_write_ce => '1',
if_write => wdata_valid,
if_din => STD_LOGIC_VECTOR(fifo_wdata_wstrb),
if_empty_n => data_valid,
if_read_ce => '1',
if_read => next_data,
UNSIGNED(if_dout) => data_pack);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component contact_discovery_results_out_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component contact_discovery_results_out_m_axi_decoder;
begin
-- Instantiation
fifo_burst : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : contact_discovery_results_out_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => NUM_WRITE_OUTSTANDING-1,
DEPTH_BITS => log2(NUM_WRITE_OUTSTANDING-1))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => next_resp,
wrreq => fifo_resp_w,
q => aw2b_bdata,
data => aw2b_awdata);
fifo_resp_to_user : contact_discovery_results_out_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
last_resp <= aw2b_bdata(1);
invalid_event <= aw2b_bdata(0);
resp_match <= '1' when (next_resp = '1' and (last_resp = '1' or invalid_event = '1')) and need_wrsp = '1' else '0';
next_resp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
next_resp <= '0';
elsif ACLK_EN = '1' then
next_resp <= (BVALID and resp_ready) or (invalid_event and need_wrsp and (not next_resp));
end if;
end if;
end process next_resp_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and next_resp = '0') then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp = '1') then
bresp_tmp <= BRESP;
elsif (next_resp = '1' and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:24:15 07/31/2014
-- Design Name:
-- Module Name: C:/Documents and Settings/paulmoon/Desktop/SENG440/huffman/huffman_testbench.vhd
-- Project Name: huffman
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: huffman_decoder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY huffman_testbench IS
END huffman_testbench;
ARCHITECTURE behavior OF huffman_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT huffman_decoder
PORT(
clock : IN std_logic;
encoded_string : IN std_logic_vector(0 to 43);
encoding : IN string(1 to 6);
output_string : OUT string(32 downto 1)
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal encoded_string : std_logic_vector(0 to 43) := (others => '0');
signal encoding : string(1 to 6) := (others => '0');
--Outputs
signal output_string : string(32 downto 1);
-- Clock period definitions
constant clock_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: huffman_decoder PORT MAP (
clock => clock,
encoded_string => encoded_string,
encoding => encoding,
output_string => output_string
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
encoded_string <= "01011011101111001111101101110110100111011110";
encoding <= "dbecfa";
wait for 100 ns;
wait for clock_period*10;
-- output_string <= "00000000000000000000000000000000";
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Instruction_Memory_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Instruction_Memory_tb IS
END ENTITY;
ARCHITECTURE Instruction_Memory_tb_ARCH OF Instruction_Memory_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Instruction_Memory_tb_synth_inst:ENTITY work.Instruction_Memory_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 1;
NRP : integer := 1;
AW : integer := 11;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_FIRST)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1)-1 downto DW*0);
end rtl;
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
port (
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
data : in std_logic_vector(23 downto 0) := (others => '0'); -- data.wire
height : out std_logic_vector(15 downto 0); -- height.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
write : in std_logic := '0'; -- write.wire
width : out std_logic_vector(15 downto 0); -- width.wire
sop : in std_logic := '0'; -- sop.wire
enble : out std_logic_vector(0 downto 0); -- enble.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
color : out std_logic_vector(2 downto 0); -- color.wire
vertex_col : out std_logic_vector(15 downto 0); -- vertex_col.wire
vertex_row : out std_logic_vector(15 downto 0) -- vertex_row.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_decoder_GNASZZCDAR is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNASZZCDAR;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GN7UJNSI7B is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7UJNSI7B;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
component alt_dspbuilder_cast_GNZ5LMFB5D is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNZ5LMFB5D;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GNXAOKDYKC is
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_port_GNXAOKDYKC;
component alt_dspbuilder_delay_GNWON5MXYC is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNWON5MXYC;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNFEQ57IEX is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNFEQ57IEX;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_cast_GNGABHQUMP is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNGABHQUMP;
signal decoder11sclrgnd_output_wire : std_logic; -- Decoder11sclrGND:output -> Decoder11:sclr
signal decoder11enavcc_output_wire : std_logic; -- Decoder11enaVCC:output -> Decoder11:ena
signal decoder10sclrgnd_output_wire : std_logic; -- Decoder10sclrGND:output -> Decoder10:sclr
signal decoder10enavcc_output_wire : std_logic; -- Decoder10enaVCC:output -> Decoder10:ena
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal decoder9sclrgnd_output_wire : std_logic; -- Decoder9sclrGND:output -> Decoder9:sclr
signal decoder9enavcc_output_wire : std_logic; -- Decoder9enaVCC:output -> Decoder9:ena
signal decoder8sclrgnd_output_wire : std_logic; -- Decoder8sclrGND:output -> Decoder8:sclr
signal decoder8enavcc_output_wire : std_logic; -- Decoder8enaVCC:output -> Decoder8:ena
signal decoder7sclrgnd_output_wire : std_logic; -- Decoder7sclrGND:output -> Decoder7:sclr
signal decoder7enavcc_output_wire : std_logic; -- Decoder7enaVCC:output -> Decoder7:ena
signal decoder6sclrgnd_output_wire : std_logic; -- Decoder6sclrGND:output -> Decoder6:sclr
signal decoder6enavcc_output_wire : std_logic; -- Decoder6enaVCC:output -> Decoder6:ena
signal decoder5sclrgnd_output_wire : std_logic; -- Decoder5sclrGND:output -> Decoder5:sclr
signal decoder5enavcc_output_wire : std_logic; -- Decoder5enaVCC:output -> Decoder5:ena
signal decoder4sclrgnd_output_wire : std_logic; -- Decoder4sclrGND:output -> Decoder4:sclr
signal decoder4enavcc_output_wire : std_logic; -- Decoder4enaVCC:output -> Decoder4:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay9sclrgnd_output_wire : std_logic; -- Delay9sclrGND:output -> Delay9:sclr
signal delay8sclrgnd_output_wire : std_logic; -- Delay8sclrGND:output -> Delay8:sclr
signal delay7sclrgnd_output_wire : std_logic; -- Delay7sclrGND:output -> Delay7:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay12sclrgnd_output_wire : std_logic; -- Delay12sclrGND:output -> Delay12:sclr
signal delay10sclrgnd_output_wire : std_logic; -- Delay10sclrGND:output -> Delay10:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal delay11sclrgnd_output_wire : std_logic; -- Delay11sclrGND:output -> Delay11:sclr
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input, Bus_Conversion8:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> [Decoder10:data, Decoder2:data, Decoder4:data, Decoder6:data, Decoder8:data, Decoder:data]
signal bus_conversion4_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion4:output -> Delay1:input
signal bus_conversion8_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion8:output -> Delay10:input
signal delay10_output_wire : std_logic_vector(15 downto 0); -- Delay10:output -> Delay11:input
signal delay1_output_wire : std_logic_vector(15 downto 0); -- Delay1:output -> Delay2:input
signal bus_conversion5_output_wire : std_logic_vector(2 downto 0); -- Bus_Conversion5:output -> Delay3:input
signal delay3_output_wire : std_logic_vector(2 downto 0); -- Delay3:output -> Delay12:input
signal bus_conversion1_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion1:output -> Delay4:input
signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> Delay5:input
signal bus_conversion2_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion2:output -> Delay6:input
signal delay6_output_wire : std_logic_vector(15 downto 0); -- Delay6:output -> Delay7:input
signal bus_conversion3_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion3:output -> Delay8:input
signal delay8_output_wire : std_logic_vector(15 downto 0); -- Delay8:output -> Delay9:input
signal data_0_output_wire : std_logic_vector(23 downto 0); -- data_0:output -> [Decoder11:data, Decoder1:data, Decoder3:data, Decoder5:data, Decoder7:data, Decoder9:data]
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator1:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator1:data1, Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1, Logical_Bit_Operator6:data1, Logical_Bit_Operator8:data1]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay4:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator11:data0, Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator7:data0, Logical_Bit_Operator9:data0]
signal decoder9_dec_wire : std_logic; -- Decoder9:dec -> Logical_Bit_Operator10:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Delay2:ena
signal decoder11_dec_wire : std_logic; -- Decoder11:dec -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Delay12:ena
signal decoder10_dec_wire : std_logic; -- Decoder10:dec -> Logical_Bit_Operator12:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Delay3:ena
signal decoder8_dec_wire : std_logic; -- Decoder8:dec -> Logical_Bit_Operator2:data0
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay1:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay5:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay6:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay7:ena
signal decoder4_dec_wire : std_logic; -- Decoder4:dec -> Logical_Bit_Operator6:data0
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Delay8:ena
signal decoder5_dec_wire : std_logic; -- Decoder5:dec -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Delay9:ena
signal decoder6_dec_wire : std_logic; -- Decoder6:dec -> Logical_Bit_Operator8:data0
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Delay10:ena
signal decoder7_dec_wire : std_logic; -- Decoder7:dec -> Logical_Bit_Operator9:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Delay11:ena
signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> enble_0:input
signal delay7_output_wire : std_logic_vector(15 downto 0); -- Delay7:output -> vertex_col_0:input
signal delay9_output_wire : std_logic_vector(15 downto 0); -- Delay9:output -> vertex_row_0:input
signal delay11_output_wire : std_logic_vector(15 downto 0); -- Delay11:output -> width_0:input
signal delay2_output_wire : std_logic_vector(15 downto 0); -- Delay2:output -> height_0:input
signal delay12_output_wire : std_logic_vector(2 downto 0); -- Delay12:output -> color_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder10:aclr, Decoder11:aclr, Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder4:aclr, Decoder5:aclr, Decoder6:aclr, Decoder7:aclr, Decoder8:aclr, Decoder9:aclr, Decoder:aclr, Delay10:aclr, Delay11:aclr, Delay12:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay7:aclr, Delay8:aclr, Delay9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder10:clock, Decoder11:clock, Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder4:clock, Decoder5:clock, Decoder6:clock, Decoder7:clock, Decoder8:clock, Decoder9:clock, Decoder:clock, Delay10:clock, Delay11:clock, Delay12:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay7:clock, Delay8:clock, Delay9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
decoder11 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder11_dec_wire, -- dec.wire
sclr => decoder11sclrgnd_output_wire, -- sclr.wire
ena => decoder11enavcc_output_wire -- ena.wire
);
decoder11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder11sclrgnd_output_wire -- output.wire
);
decoder11enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder11enavcc_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
decoder10 : component alt_dspbuilder_decoder_GNASZZCDAR
generic map (
decode => "110",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder10_dec_wire, -- dec.wire
sclr => decoder10sclrgnd_output_wire, -- sclr.wire
ena => decoder10enavcc_output_wire -- ena.wire
);
decoder10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder10sclrgnd_output_wire -- output.wire
);
decoder10enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder10enavcc_output_wire -- output.wire
);
vertex_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay9_output_wire, -- input.wire
output => vertex_row -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder5_dec_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => decoder4_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
vertex_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay7_output_wire, -- input.wire
output => vertex_col -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay2_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder7_dec_wire -- data1.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => decoder6_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder8_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNBHXAVAPH
generic map (
decode => "010",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay11_output_wire, -- input.wire
output => width -- output.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => decoder10_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder11_dec_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder9_dec_wire -- data1.wire
);
decoder9 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder9_dec_wire, -- dec.wire
sclr => decoder9sclrgnd_output_wire, -- sclr.wire
ena => decoder9enavcc_output_wire -- ena.wire
);
decoder9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder9sclrgnd_output_wire -- output.wire
);
decoder9enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder9enavcc_output_wire -- output.wire
);
decoder8 : component alt_dspbuilder_decoder_GN7UJNSI7B
generic map (
decode => "101",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder8_dec_wire, -- dec.wire
sclr => decoder8sclrgnd_output_wire, -- sclr.wire
ena => decoder8enavcc_output_wire -- ena.wire
);
decoder8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder8sclrgnd_output_wire -- output.wire
);
decoder8enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder8enavcc_output_wire -- output.wire
);
decoder7 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder7_dec_wire, -- dec.wire
sclr => decoder7sclrgnd_output_wire, -- sclr.wire
ena => decoder7enavcc_output_wire -- ena.wire
);
decoder7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder7sclrgnd_output_wire -- output.wire
);
decoder7enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder7enavcc_output_wire -- output.wire
);
decoder6 : component alt_dspbuilder_decoder_GN7W55JURN
generic map (
decode => "100",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder6_dec_wire, -- dec.wire
sclr => decoder6sclrgnd_output_wire, -- sclr.wire
ena => decoder6enavcc_output_wire -- ena.wire
);
decoder6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder6sclrgnd_output_wire -- output.wire
);
decoder6enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder6enavcc_output_wire -- output.wire
);
decoder5 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder5_dec_wire, -- dec.wire
sclr => decoder5sclrgnd_output_wire, -- sclr.wire
ena => decoder5enavcc_output_wire -- ena.wire
);
decoder5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder5sclrgnd_output_wire -- output.wire
);
decoder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder5enavcc_output_wire -- output.wire
);
decoder4 : component alt_dspbuilder_decoder_GNBT6YIKS3
generic map (
decode => "011",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder4_dec_wire, -- dec.wire
sclr => decoder4sclrgnd_output_wire, -- sclr.wire
ena => decoder4enavcc_output_wire -- ena.wire
);
decoder4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder4sclrgnd_output_wire -- output.wire
);
decoder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder4enavcc_output_wire -- output.wire
);
bus_conversion1 : component alt_dspbuilder_cast_GNZ5LMFB5D
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
enble_0 : component alt_dspbuilder_port_GNXAOKDYKC
port map (
input => delay5_output_wire, -- input.wire
output => enble -- output.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
delay6 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNFEQ57IEX
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "000",
width => 3
)
port map (
input => bus_conversion5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator12_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay9 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay9_output_wire, -- output.wire
sclr => delay9sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator7_result_wire -- ena.wire
);
delay9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay9sclrgnd_output_wire -- output.wire
);
delay8 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay8_output_wire, -- output.wire
sclr => delay8sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator6_result_wire -- ena.wire
);
delay8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay8sclrgnd_output_wire -- output.wire
);
delay7 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay7_output_wire, -- output.wire
sclr => delay7sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay7sclrgnd_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
color_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => delay12_output_wire, -- input.wire
output => color -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator10_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay12 : component alt_dspbuilder_delay_GNFEQ57IEX
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "000",
width => 3
)
port map (
input => delay3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay12_output_wire, -- output.wire
sclr => delay12sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator11_result_wire -- ena.wire
);
delay12sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay12sclrgnd_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
delay10 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay10_output_wire, -- output.wire
sclr => delay10sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator8_result_wire -- ena.wire
);
delay10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay10sclrgnd_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNQPHUITBS
generic map (
decode => "001",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
delay11 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay10_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay11_output_wire, -- output.wire
sclr => delay11sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator9_result_wire -- ena.wire
);
delay11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay11sclrgnd_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNGABHQUMP
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
port (
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
data : in std_logic_vector(23 downto 0) := (others => '0'); -- data.wire
height : out std_logic_vector(15 downto 0); -- height.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
write : in std_logic := '0'; -- write.wire
width : out std_logic_vector(15 downto 0); -- width.wire
sop : in std_logic := '0'; -- sop.wire
enble : out std_logic_vector(0 downto 0); -- enble.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
color : out std_logic_vector(2 downto 0); -- color.wire
vertex_col : out std_logic_vector(15 downto 0); -- vertex_col.wire
vertex_row : out std_logic_vector(15 downto 0) -- vertex_row.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_decoder_GNASZZCDAR is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNASZZCDAR;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_decoder_GN7UJNSI7B is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7UJNSI7B;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
component alt_dspbuilder_cast_GNZ5LMFB5D is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNZ5LMFB5D;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GNXAOKDYKC is
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_port_GNXAOKDYKC;
component alt_dspbuilder_delay_GNWON5MXYC is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNWON5MXYC;
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNFEQ57IEX is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNFEQ57IEX;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_cast_GNGABHQUMP is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNGABHQUMP;
signal decoder11sclrgnd_output_wire : std_logic; -- Decoder11sclrGND:output -> Decoder11:sclr
signal decoder11enavcc_output_wire : std_logic; -- Decoder11enaVCC:output -> Decoder11:ena
signal decoder10sclrgnd_output_wire : std_logic; -- Decoder10sclrGND:output -> Decoder10:sclr
signal decoder10enavcc_output_wire : std_logic; -- Decoder10enaVCC:output -> Decoder10:ena
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal decoder9sclrgnd_output_wire : std_logic; -- Decoder9sclrGND:output -> Decoder9:sclr
signal decoder9enavcc_output_wire : std_logic; -- Decoder9enaVCC:output -> Decoder9:ena
signal decoder8sclrgnd_output_wire : std_logic; -- Decoder8sclrGND:output -> Decoder8:sclr
signal decoder8enavcc_output_wire : std_logic; -- Decoder8enaVCC:output -> Decoder8:ena
signal decoder7sclrgnd_output_wire : std_logic; -- Decoder7sclrGND:output -> Decoder7:sclr
signal decoder7enavcc_output_wire : std_logic; -- Decoder7enaVCC:output -> Decoder7:ena
signal decoder6sclrgnd_output_wire : std_logic; -- Decoder6sclrGND:output -> Decoder6:sclr
signal decoder6enavcc_output_wire : std_logic; -- Decoder6enaVCC:output -> Decoder6:ena
signal decoder5sclrgnd_output_wire : std_logic; -- Decoder5sclrGND:output -> Decoder5:sclr
signal decoder5enavcc_output_wire : std_logic; -- Decoder5enaVCC:output -> Decoder5:ena
signal decoder4sclrgnd_output_wire : std_logic; -- Decoder4sclrGND:output -> Decoder4:sclr
signal decoder4enavcc_output_wire : std_logic; -- Decoder4enaVCC:output -> Decoder4:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay9sclrgnd_output_wire : std_logic; -- Delay9sclrGND:output -> Delay9:sclr
signal delay8sclrgnd_output_wire : std_logic; -- Delay8sclrGND:output -> Delay8:sclr
signal delay7sclrgnd_output_wire : std_logic; -- Delay7sclrGND:output -> Delay7:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay12sclrgnd_output_wire : std_logic; -- Delay12sclrGND:output -> Delay12:sclr
signal delay10sclrgnd_output_wire : std_logic; -- Delay10sclrGND:output -> Delay10:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal delay11sclrgnd_output_wire : std_logic; -- Delay11sclrGND:output -> Delay11:sclr
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Bus_Conversion4:input, Bus_Conversion5:input, Bus_Conversion8:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> [Decoder10:data, Decoder2:data, Decoder4:data, Decoder6:data, Decoder8:data, Decoder:data]
signal bus_conversion4_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion4:output -> Delay1:input
signal bus_conversion8_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion8:output -> Delay10:input
signal delay10_output_wire : std_logic_vector(15 downto 0); -- Delay10:output -> Delay11:input
signal delay1_output_wire : std_logic_vector(15 downto 0); -- Delay1:output -> Delay2:input
signal bus_conversion5_output_wire : std_logic_vector(2 downto 0); -- Bus_Conversion5:output -> Delay3:input
signal delay3_output_wire : std_logic_vector(2 downto 0); -- Delay3:output -> Delay12:input
signal bus_conversion1_output_wire : std_logic_vector(0 downto 0); -- Bus_Conversion1:output -> Delay4:input
signal delay4_output_wire : std_logic_vector(0 downto 0); -- Delay4:output -> Delay5:input
signal bus_conversion2_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion2:output -> Delay6:input
signal delay6_output_wire : std_logic_vector(15 downto 0); -- Delay6:output -> Delay7:input
signal bus_conversion3_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion3:output -> Delay8:input
signal delay8_output_wire : std_logic_vector(15 downto 0); -- Delay8:output -> Delay9:input
signal data_0_output_wire : std_logic_vector(23 downto 0); -- data_0:output -> [Decoder11:data, Decoder1:data, Decoder3:data, Decoder5:data, Decoder7:data, Decoder9:data]
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator1:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator1:data1, Logical_Bit_Operator2:data1, Logical_Bit_Operator4:data1, Logical_Bit_Operator6:data1, Logical_Bit_Operator8:data1]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay4:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator11:data0, Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator7:data0, Logical_Bit_Operator9:data0]
signal decoder9_dec_wire : std_logic; -- Decoder9:dec -> Logical_Bit_Operator10:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Delay2:ena
signal decoder11_dec_wire : std_logic; -- Decoder11:dec -> Logical_Bit_Operator11:data1
signal logical_bit_operator11_result_wire : std_logic; -- Logical_Bit_Operator11:result -> Delay12:ena
signal decoder10_dec_wire : std_logic; -- Decoder10:dec -> Logical_Bit_Operator12:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Delay3:ena
signal decoder8_dec_wire : std_logic; -- Decoder8:dec -> Logical_Bit_Operator2:data0
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay1:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay5:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay6:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay7:ena
signal decoder4_dec_wire : std_logic; -- Decoder4:dec -> Logical_Bit_Operator6:data0
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Delay8:ena
signal decoder5_dec_wire : std_logic; -- Decoder5:dec -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Delay9:ena
signal decoder6_dec_wire : std_logic; -- Decoder6:dec -> Logical_Bit_Operator8:data0
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Delay10:ena
signal decoder7_dec_wire : std_logic; -- Decoder7:dec -> Logical_Bit_Operator9:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Delay11:ena
signal delay5_output_wire : std_logic_vector(0 downto 0); -- Delay5:output -> enble_0:input
signal delay7_output_wire : std_logic_vector(15 downto 0); -- Delay7:output -> vertex_col_0:input
signal delay9_output_wire : std_logic_vector(15 downto 0); -- Delay9:output -> vertex_row_0:input
signal delay11_output_wire : std_logic_vector(15 downto 0); -- Delay11:output -> width_0:input
signal delay2_output_wire : std_logic_vector(15 downto 0); -- Delay2:output -> height_0:input
signal delay12_output_wire : std_logic_vector(2 downto 0); -- Delay12:output -> color_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder10:aclr, Decoder11:aclr, Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder4:aclr, Decoder5:aclr, Decoder6:aclr, Decoder7:aclr, Decoder8:aclr, Decoder9:aclr, Decoder:aclr, Delay10:aclr, Delay11:aclr, Delay12:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay7:aclr, Delay8:aclr, Delay9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder10:clock, Decoder11:clock, Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder4:clock, Decoder5:clock, Decoder6:clock, Decoder7:clock, Decoder8:clock, Decoder9:clock, Decoder:clock, Delay10:clock, Delay11:clock, Delay12:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay7:clock, Delay8:clock, Delay9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
decoder11 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder11_dec_wire, -- dec.wire
sclr => decoder11sclrgnd_output_wire, -- sclr.wire
ena => decoder11enavcc_output_wire -- ena.wire
);
decoder11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder11sclrgnd_output_wire -- output.wire
);
decoder11enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder11enavcc_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
decoder10 : component alt_dspbuilder_decoder_GNASZZCDAR
generic map (
decode => "110",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder10_dec_wire, -- dec.wire
sclr => decoder10sclrgnd_output_wire, -- sclr.wire
ena => decoder10enavcc_output_wire -- ena.wire
);
decoder10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder10sclrgnd_output_wire -- output.wire
);
decoder10enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder10enavcc_output_wire -- output.wire
);
vertex_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay9_output_wire, -- input.wire
output => vertex_row -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder5_dec_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => decoder4_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
vertex_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay7_output_wire, -- input.wire
output => vertex_col -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay2_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder7_dec_wire -- data1.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => decoder6_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => decoder8_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNBHXAVAPH
generic map (
decode => "010",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay11_output_wire, -- input.wire
output => width -- output.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => decoder10_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator11 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator11_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder11_dec_wire -- data1.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder9_dec_wire -- data1.wire
);
decoder9 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder9_dec_wire, -- dec.wire
sclr => decoder9sclrgnd_output_wire, -- sclr.wire
ena => decoder9enavcc_output_wire -- ena.wire
);
decoder9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder9sclrgnd_output_wire -- output.wire
);
decoder9enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder9enavcc_output_wire -- output.wire
);
decoder8 : component alt_dspbuilder_decoder_GN7UJNSI7B
generic map (
decode => "101",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder8_dec_wire, -- dec.wire
sclr => decoder8sclrgnd_output_wire, -- sclr.wire
ena => decoder8enavcc_output_wire -- ena.wire
);
decoder8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder8sclrgnd_output_wire -- output.wire
);
decoder8enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder8enavcc_output_wire -- output.wire
);
decoder7 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder7_dec_wire, -- dec.wire
sclr => decoder7sclrgnd_output_wire, -- sclr.wire
ena => decoder7enavcc_output_wire -- ena.wire
);
decoder7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder7sclrgnd_output_wire -- output.wire
);
decoder7enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder7enavcc_output_wire -- output.wire
);
decoder6 : component alt_dspbuilder_decoder_GN7W55JURN
generic map (
decode => "100",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder6_dec_wire, -- dec.wire
sclr => decoder6sclrgnd_output_wire, -- sclr.wire
ena => decoder6enavcc_output_wire -- ena.wire
);
decoder6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder6sclrgnd_output_wire -- output.wire
);
decoder6enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder6enavcc_output_wire -- output.wire
);
decoder5 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder5_dec_wire, -- dec.wire
sclr => decoder5sclrgnd_output_wire, -- sclr.wire
ena => decoder5enavcc_output_wire -- ena.wire
);
decoder5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder5sclrgnd_output_wire -- output.wire
);
decoder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder5enavcc_output_wire -- output.wire
);
decoder4 : component alt_dspbuilder_decoder_GNBT6YIKS3
generic map (
decode => "011",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder4_dec_wire, -- dec.wire
sclr => decoder4sclrgnd_output_wire, -- sclr.wire
ena => decoder4enavcc_output_wire -- ena.wire
);
decoder4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder4sclrgnd_output_wire -- output.wire
);
decoder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder4enavcc_output_wire -- output.wire
);
bus_conversion1 : component alt_dspbuilder_cast_GNZ5LMFB5D
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
enble_0 : component alt_dspbuilder_port_GNXAOKDYKC
port map (
input => delay5_output_wire, -- input.wire
output => enble -- output.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
delay6 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNUECIBFDH
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0",
width => 1
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNFEQ57IEX
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "000",
width => 3
)
port map (
input => bus_conversion5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator12_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay9 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay9_output_wire, -- output.wire
sclr => delay9sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator7_result_wire -- ena.wire
);
delay9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay9sclrgnd_output_wire -- output.wire
);
delay8 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay8_output_wire, -- output.wire
sclr => delay8sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator6_result_wire -- ena.wire
);
delay8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay8sclrgnd_output_wire -- output.wire
);
delay7 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay7_output_wire, -- output.wire
sclr => delay7sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay7sclrgnd_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
color_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => delay12_output_wire, -- input.wire
output => color -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator10_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay12 : component alt_dspbuilder_delay_GNFEQ57IEX
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "000",
width => 3
)
port map (
input => delay3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay12_output_wire, -- output.wire
sclr => delay12sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator11_result_wire -- ena.wire
);
delay12sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay12sclrgnd_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
delay10 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay10_output_wire, -- output.wire
sclr => delay10sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator8_result_wire -- ena.wire
);
delay10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay10sclrgnd_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNQPHUITBS
generic map (
decode => "001",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
delay11 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay10_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay11_output_wire, -- output.wire
sclr => delay11sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator9_result_wire -- ena.wire
);
delay11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay11sclrgnd_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNGABHQUMP
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_FRAME_PARAMETER
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
|
entity t1 is
port(
A,B,C : in bit;
D : out bit
);
end t1;
architecture rtl of t1 is
begin
D<='1' when A='1' and B='1' and C='1' else '0';
end rtl;
entity test is
port(
A,B,C : in bit_vector(7 downto 0);
D : out bit_vector(7 downto 0)
);
end test;
architecture rtl of test is
begin
ADD_GEN: for I in 0 to 7 generate
L: if I=0 generate--failure is here
U0: entity work.t1
port map(A(I),B(I),'0',D(I));
end generate L;
U: if I>0 generate
UX: entity work.t1
port map(A(I),B(I),C(I-1),D(I));
end generate U;
end generate ADD_GEN;
end rtl;
entity issue111 is
end entity;
architecture test of issue111 is
signal A, B, C : bit_vector(7 downto 0);
signal D : bit_vector(7 downto 0);
begin
uut: entity work.test
port map (
A => A,
B => B,
C => C,
D => D );
process is
begin
wait for 1 ns;
assert D = X"00";
A <= X"ff";
wait for 1 ns;
assert D = X"00";
B <= X"0f";
C <= X"0c";
wait for 1 ns;
assert D = X"08";
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2155.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02155ent IS
END c07s02b04x00p21n01i02155ent;
ARCHITECTURE c07s02b04x00p21n01i02155arch OF c07s02b04x00p21n01i02155ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_1 is integer_v (1 to 1);
SUBTYPE integer_null is integer_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : integer_1;
variable l_operand : integer_null;
variable r_operand : integer := 123;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=123)
report "***PASSED TEST: c07s02b04x00p21n01i02155"
severity NOTE;
assert (result(1)=123)
report "***FAILED TEST: c07s02b04x00p21n01i02155 - Concatenation of null and INTEGER element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2155.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02155ent IS
END c07s02b04x00p21n01i02155ent;
ARCHITECTURE c07s02b04x00p21n01i02155arch OF c07s02b04x00p21n01i02155ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_1 is integer_v (1 to 1);
SUBTYPE integer_null is integer_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : integer_1;
variable l_operand : integer_null;
variable r_operand : integer := 123;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=123)
report "***PASSED TEST: c07s02b04x00p21n01i02155"
severity NOTE;
assert (result(1)=123)
report "***FAILED TEST: c07s02b04x00p21n01i02155 - Concatenation of null and INTEGER element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02155arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2155.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02155ent IS
END c07s02b04x00p21n01i02155ent;
ARCHITECTURE c07s02b04x00p21n01i02155arch OF c07s02b04x00p21n01i02155ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_1 is integer_v (1 to 1);
SUBTYPE integer_null is integer_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : integer_1;
variable l_operand : integer_null;
variable r_operand : integer := 123;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result(1)=123)
report "***PASSED TEST: c07s02b04x00p21n01i02155"
severity NOTE;
assert (result(1)=123)
report "***FAILED TEST: c07s02b04x00p21n01i02155 - Concatenation of null and INTEGER element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02155arch;
|
library ieee; context c1, c1a, c1b;
library ieee; context con1; context con2; context con3;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1951.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n05i01951ent IS
END c07s02b01x00p01n05i01951ent;
ARCHITECTURE c07s02b01x00p01n05i01951arch OF c07s02b01x00p01n05i01951ent IS
BEGIN
TESTING: PROCESS
constant C1 : BIT_VECTOR(1 to 4) := "0110";
constant C2 : BIT_VECTOR := not C1;
constant C3 : BIT_VECTOR(1 TO 4) := not C1;
BEGIN
assert C1(1) = '0';
assert C2(0) = '1';
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n05i01951 - Value is outside the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n05i01951arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1951.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n05i01951ent IS
END c07s02b01x00p01n05i01951ent;
ARCHITECTURE c07s02b01x00p01n05i01951arch OF c07s02b01x00p01n05i01951ent IS
BEGIN
TESTING: PROCESS
constant C1 : BIT_VECTOR(1 to 4) := "0110";
constant C2 : BIT_VECTOR := not C1;
constant C3 : BIT_VECTOR(1 TO 4) := not C1;
BEGIN
assert C1(1) = '0';
assert C2(0) = '1';
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n05i01951 - Value is outside the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n05i01951arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1951.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n05i01951ent IS
END c07s02b01x00p01n05i01951ent;
ARCHITECTURE c07s02b01x00p01n05i01951arch OF c07s02b01x00p01n05i01951ent IS
BEGIN
TESTING: PROCESS
constant C1 : BIT_VECTOR(1 to 4) := "0110";
constant C2 : BIT_VECTOR := not C1;
constant C3 : BIT_VECTOR(1 TO 4) := not C1;
BEGIN
assert C1(1) = '0';
assert C2(0) = '1';
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n05i01951 - Value is outside the range."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n05i01951arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: Math extension package.
--
-- Description:
-- -------------------------------------
-- This package provides additional math functions.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
package math is
-- figurate numbers
function squareNumber(N : natural) return natural;
function cubicNumber(N : natural) return natural;
function triangularNumber(N : natural) return natural;
-- coefficients
-- binomial coefficient (N choose K)
function binomialCoefficient(N : positive; K : positive) return positive;
-- greatest common divisor (gcd)
function greatestCommonDivisor(N1 : positive; N2 : positive) return positive;
-- least common multiple (lcm)
function leastCommonMultiple(N1 : positive; N2 : positive) return positive;
end package;
package body math is
-- figurate numbers
function squareNumber(N : natural) return natural is
begin
return N*N;
end function;
function cubicNumber(N : natural) return natural is
begin
return N*N*N;
end function;
function triangularNumber(N : natural) return natural is
variable T : natural;
begin
return (N * (N + 1) / 2);
end function;
-- coefficients
function binomialCoefficient(N : positive; K : positive) return positive is
variable Result : positive;
begin
Result := 1;
for i in 1 to K loop
Result := Result * (((N + 1) - i) / i);
end loop;
return Result;
end function;
-- greatest common divisor (gcd)
function greatestCommonDivisor(N1 : positive; N2 : positive) return positive is
variable M1 : positive;
variable M2 : natural;
variable Remainer : natural;
begin
M1 := imax(N1, N2);
M2 := imin(N1, N2);
while M2 /= 0 loop
Remainer := M1 mod M2;
M1 := M2;
M2 := Remainer;
end loop;
return M1;
end function;
-- least common multiple (lcm)
function leastCommonMultiple(N1 : positive; N2 : positive) return positive is
begin
return ((N1 * N2) / greatestCommonDivisor(N1, N2));
end function;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- time base
i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (STATE_INIT, STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES, STATE_READ_PARTICLE_SIZE, STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE, STATE_NEEDED_BURSTS, STATE_NEEDED_BURSTS_2,
STATE_NEEDED_READS_1, STATE_NEEDED_READS_2, STATE_READ_OBSERVATION_ADDRESS,
STATE_READ_REF_DATA_ADDRESS, STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1, STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3, STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5, STATE_LOAD_OBSERVATION,
STATE_LOAD_BURST_DECISION, STATE_LOAD_BURST, STATE_LOAD_READ_DECISION,
STATE_LOAD_READ, STATE_WRITE_TO_RAM,
STATE_LOAD_OBSERVATION_DATA_DECISION, STATE_LOAD_OBSERVATION_DATA_DECISION_2,
STATE_LOAD_OBSERVATION_DATA_DECISION_3,
STATE_LIKELIHOOD, STATE_LIKELIHOOD_DONE, STATE_WRITE_LIKELIHOOD,
STATE_SEND_MESSAGE, STATE_SEND_MEASUREMENT_1, STATE_SEND_MEASUREMENT_2 );
-- current state
signal state : t_state := STATE_INIT;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer := 128;
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_TASK_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_TASK_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_TASK_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= STATE_READ_PARTICLE_ADDRESS;
-- CHANGE BACK (2 of 6) !!!
--state <= STATE_NEEDED_BURSTS;
end if;
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= STATE_NEEDED_BURSTS_2;
when STATE_NEEDED_BURSTS_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= STATE_NEEDED_READS_1;
when STATE_NEEDED_READS_1 =>
--! calculate number of reads (1 of 2)
-- change this back
-- old
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= STATE_NEEDED_READS_2;
when STATE_NEEDED_READS_2 =>
--! calculate number of reads (2 of 2)
number_of_reads_remember <= number_of_reads_remember / 4;
state <= STATE_READ_OBSERVATION_ADDRESS;
when STATE_READ_OBSERVATION_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_REF_DATA_ADDRESS;
end if;
-- -- CHANGE BACK (3 of 6) !!!
-- observation_array_start_address <= "00100000000000000000000000000000";
-- state <= STATE_READ_REF_DATA_ADDRESS;
when STATE_READ_REF_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
state <= STATE_WAIT_FOR_MESSAGE;
end if;
-- -- CHANGE BACK (4 of 6) !!!
-- -- ref data address = 10000040
-- reference_data_address <= "00010000000000000000000001000000";
-- state <= STATE_WAIT_FOR_MESSAGE;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
time_start <= TO_INTEGER(SIGNED(i_timebase));
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
temp <= message2 * block_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= STATE_LOAD_OBSERVATION;
when STATE_LOAD_OBSERVATION =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= STATE_LOAD_BURST_DECISION;
when STATE_LOAD_BURST_DECISION =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= STATE_LOAD_BURST;
number_of_bursts <= number_of_bursts - 1;
else
state <= STATE_LOAD_READ_DECISION;
end if;
when STATE_LOAD_BURST =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= STATE_LOAD_BURST_DECISION;
end if;
when STATE_LOAD_READ_DECISION =>
--! decision if a read into local ram is needed
if (number_of_reads > 0) then
state <= STATE_LOAD_READ;
number_of_reads <= number_of_reads - 1;
elsif (second_run = '1') then
state <= STATE_LIKELIHOOD;
else
second_run <= '1';
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_LOAD_READ =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
state <= STATE_WRITE_TO_RAM;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= STATE_LOAD_READ_DECISION;
when STATE_LOAD_OBSERVATION_DATA_DECISION =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_2;
when STATE_LOAD_OBSERVATION_DATA_DECISION_2 =>
--! decide, if there is another observation to be handled, else post semaphore
o_RAMWEImportance <= '0';
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION_3;
when STATE_LOAD_OBSERVATION_DATA_DECISION_3 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= STATE_LOAD_BURST_DECISION;
else
time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
when STATE_LIKELIHOOD =>
--! start and run likelihood user process
init <= '0';
enable <= '1';
observation_loaded <= '1';
state <= STATE_LIKELIHOOD_DONE;
when STATE_LIKELIHOOD_DONE =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
if (finished = '1') then
enable <= '0';
init <= '1';
state <= STATE_WRITE_LIKELIHOOD;
remaining_observations <= remaining_observations - 1;
end if;
when STATE_WRITE_LIKELIHOOD =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address, STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= STATE_LOAD_OBSERVATION_DATA_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
-- when STATE_SEND_MEASUREMENT_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
--
-- state <= STATE_WAIT_FOR_MESSAGE;
-- end if;
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
package pkg is
type type_t is (a,b,c,d);
function type_t_image(data : type_t) return string;
end package;
package body pkg is
function type_t_image(data : type_t) return string is
begin
return type_t'image(data);
end;
end;
use work.pkg.all;
entity bug is
end entity;
architecture arch of bug is
begin
main : process
begin
assert type_t_image(a) = "a";
assert type_t_image(b) = "b";
assert type_t_image(c) = "c";
assert type_t_image(d) = "d";
report "Success";
wait;
end process;
end;
|
package pkg is
type type_t is (a,b,c,d);
function type_t_image(data : type_t) return string;
end package;
package body pkg is
function type_t_image(data : type_t) return string is
begin
return type_t'image(data);
end;
end;
use work.pkg.all;
entity bug is
end entity;
architecture arch of bug is
begin
main : process
begin
assert type_t_image(a) = "a";
assert type_t_image(b) = "b";
assert type_t_image(c) = "c";
assert type_t_image(d) = "d";
report "Success";
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
m : out std_logic);
end mux;
architecture behavioral of mux is
begin
process(a,b,c,d,s) begin
case s is
when "00" => m <= a;
when "01" => m <= b;
when "10" => m <= c;
when others => m <= d;
end case;
end process;
end behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mux2 is
port ( a, b, sel : in bit;
z : out bit );
end entity mux2;
--------------------------------------------------
architecture behavioral of mux2 is
constant prop_delay : time := 2 ns;
begin
slick_mux : process is
begin
case sel is
when '0' =>
z <= a after prop_delay;
wait on sel, a;
when '1' =>
z <= b after prop_delay;
wait on sel, b;
end case;
end process slick_mux;
end architecture behavioral;
|
-- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT half adder
-- Michael Lancaster <[email protected]>
-- 4 October 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity smt_half_adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC);
end smt_half_adder;
architecture Behavioral of smt_half_adder is
begin
S <= A xor B;
Cout <= A and B;
end Behavioral;
|
-------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: full_axi.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller when configured in a full AXI4 mode.
-- The rd_chnl and wr_chnl modules are instantiated.
-- The ECC AXI-Lite register module is instantiated, if enabled.
-- When single port BRAM mode is selected, the arbitration logic
-- is instantiated (and connected to each wr_chnl & rd_chnl).
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter and mappings on instantiated modules.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE & BRAM data sizes based on 128-bit ECC configuration.
-- Plus XST clean-up.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
use work.lite_ecc_reg;
use work.sng_port_arb;
use work.wr_chnl;
use work.rd_chnl;
------------------------------------------------------------------------------
entity full_axi is
generic (
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- TBD
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity full_axi;
-------------------------------------------------------------------------------
architecture implementation of full_axi is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal AXI Signals
signal S_AXI_AWREADY_i : std_logic := '0';
signal S_AXI_ARREADY_i : std_logic := '0';
-- Internal BRAM Signals
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_En_A_i : std_logic := '0';
signal BRAM_En_B_i : std_logic := '0';
signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- Internal ECC Signals
signal Enable_ECC : std_logic := '0';
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Wr_BRAM_Addr_En : std_logic := '0';
signal Rd_BRAM_Addr_En : std_logic := '0';
-- Internal Arbitration Signals
signal Arb2AW_Active : std_logic := '0';
signal AW2Arb_Busy : std_logic := '0';
signal AW2Arb_Active_Clr : std_logic := '0';
signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0');
signal Arb2AR_Active : std_logic := '0';
signal AR2Arb_Active_Clr : std_logic := '0';
signal WrChnl_BRAM_Addr_Rst : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal WrChnl_BRAM_Addr_Inc : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal RdChnl_BRAM_Addr_Inc : std_logic := '0';
signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** BRAM Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: ADDR_SNG_PORT
-- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl
-- Only one write or read will be active at a time.
-- Ensure that ecah channel address is driven to '0' when not in use.
---------------------------------------------------------------------------
ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate
signal sng_bram_addr_rst : std_logic := '0';
signal sng_bram_addr_ld_en : std_logic := '0';
signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal sng_bram_addr_inc : std_logic := '0';
begin
-- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i;
-- Insert mux on address counter control signals
sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst;
sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En;
sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld;
sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc;
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (sng_bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (sng_bram_addr_ld_en = '1') then
bram_addr_int <= sng_bram_addr_ld;
elsif (sng_bram_addr_inc = '1') then
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
BRAM_Addr_B <= (others => '0');
BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i;
-- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i;
BRAM_En_B <= '0';
BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A
BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0');
-- v1.03a
-- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared).
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
end generate ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: ADDR_DUAL_PORT
-- Purpose: Assign each BRAM address when in a dual port controller
-- configuration.
---------------------------------------------------------------------------
ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate
begin
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
BRAM_En_A <= BRAM_En_A_i;
BRAM_En_B <= BRAM_En_B_i;
BRAM_WE_A <= BRAM_WE_A_i;
BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B
end generate ADDR_DUAL_PORT;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
GEN_NO_REGS: if (C_ECC = 0) generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
Enable_ECC <= '0';
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
-- For future implementation.
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- TBD
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- Add AXI-Lite ECC Register Ports
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
-- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) ,
-- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC_i
);
BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En;
-- v1.03a
-- Add coverage tags for Wr_CE_Failing_We.
-- No testing on forcing errors with RMW and AXI write transfers.
--coverage off
CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We;
Sl_CE <= Wr_Sl_CE or Rd_Sl_CE;
Sl_UE <= Wr_Sl_UE or Rd_Sl_UE;
--coverage on
-------------------------------------------------------------------
-- Generate: GEN_32
-- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit.
-------------------------------------------------------------------
GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectECC <= '0' & FaultInjectECC_i;
end generate GEN_32;
-------------------------------------------------------------------
-- Generate: GEN_NON_32
-- Purpose: Data widths match at 8-bits for ECC on 64-bit data.
-- And 9-bits for 128-bit data.
-------------------------------------------------------------------
GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate
begin
FaultInjectECC <= FaultInjectECC_i;
end generate GEN_NON_32;
end generate GEN_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_ARB
-- Purpose: Generate arbitration module when AXI4 is configured in
-- single port mode.
---------------------------------------------------------------------------
GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_SNG_PORT : entity work.sng_port_arb
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY ,
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr
);
end generate GEN_ARB;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL
-- Purpose: Dual mode. AWREADY and ARREADY are generated from each
-- wr_chnl and rd_chnl module.
---------------------------------------------------------------------------
GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
S_AXI_AWREADY <= S_AXI_AWREADY_i;
S_AXI_ARREADY <= S_AXI_ARREADY_i;
Arb2AW_Active <= '0';
Arb2AR_Active <= '0';
end generate GEN_DUAL;
---------------------------------------------------------------------------
-- Instance: I_WR_CHNL
--
-- Description:
-- BRAM controller write channel logic. Controls AXI bus handshaking and
-- data flow on the write address (AW), write data (W) and
-- write response (B) channels.
--
-- BRAM signals are marked as output from Wr Chnl for future implementation
-- of merging Wr/Rd channel outputs to a single port of the BRAM module.
--
---------------------------------------------------------------------------
I_WR_CHNL : entity work.wr_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_AWID => S_AXI_AWID ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWLEN => S_AXI_AWLEN ,
AXI_AWSIZE => S_AXI_AWSIZE ,
AXI_AWBURST => S_AXI_AWBURST ,
AXI_AWLOCK => S_AXI_AWLOCK ,
AXI_AWCACHE => S_AXI_AWCACHE ,
AXI_AWPROT => S_AXI_AWPROT ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_i ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WLAST => S_AXI_WLAST ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BID => S_AXI_BID ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
-- Arb Ports
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst ,
Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Wr_BRAM_Addr_En ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => Wr_CE_Failing_We ,
Sl_CE => Wr_Sl_CE ,
Sl_UE => Wr_Sl_UE ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC ,
BRAM_En => BRAM_En_A_i ,
-- BRAM_WE => BRAM_WE_A ,
-- 4/13
BRAM_WE => BRAM_WE_A_i ,
BRAM_WrData => BRAM_WrData_A ,
BRAM_RdData => BRAM_RdData_A ,
BRAM_Addr => BRAM_Addr_A_i
);
---------------------------------------------------------------------------
-- Instance: I_RD_CHNL
--
-- Description:
-- BRAM controller read channel logic. Controls all handshaking and data
-- flow on read address (AR) and read data (R) AXI channels.
--
-- BRAM signals are marked as Rd Chnl signals for future implementation
-- of merging Rd/Wr BRAM signals to a single BRAM port.
--
---------------------------------------------------------------------------
I_RD_CHNL : entity work.rd_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_ARID => S_AXI_ARID ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARLEN => S_AXI_ARLEN ,
AXI_ARSIZE => S_AXI_ARSIZE ,
AXI_ARBURST => S_AXI_ARBURST ,
AXI_ARLOCK => S_AXI_ARLOCK ,
AXI_ARCACHE => S_AXI_ARCACHE ,
AXI_ARPROT => S_AXI_ARPROT ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_i ,
AXI_RID => S_AXI_RID ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Arb Ports
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr ,
Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Rd_BRAM_Addr_En ,
CE_Failing_We => Rd_CE_Failing_We ,
Sl_CE => Rd_Sl_CE ,
Sl_UE => Rd_Sl_UE ,
BRAM_En => BRAM_En_B_i ,
BRAM_Addr => BRAM_Addr_B_i ,
BRAM_RdData => BRAM_RdData_i
);
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_maxcode;
architecture augh of p_jinfo_ac_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_maxcode;
architecture augh of p_jinfo_ac_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity UC_receptor is
port(
CLOCK, RESET, LIGA, CD : in std_logic;
DTR, enable_recepcao : out std_logic;
dep_estado : out std_logic_vector(1 downto 0)
);
end UC_receptor;
architecture estados of UC_receptor is
type tipo_estado is (INICIAL, LIGADO, RECEBENDO);
signal estado : tipo_estado;
begin
process (LIGA, RESET, CLOCK, estado)
begin
if RESET = '1'then
estado <= INICIAL;
elsif (clock'event and clock='1') then
case estado is
when INICIAL =>
if LIGA = '1' then
estado <= LIGADO;
end if;
when LIGADO =>
if LIGA = '1' and CD = '1' then
estado <= RECEBENDO;
elsif LIGA = '0' then
estado <= INICIAL;
end if;
when RECEBENDO =>
if LIGA = '0' then
estado <= INICIAL;
elsif CD = '0' then
estado <= LIGADO;
end if;
end case;
end if;
end process;
process (estado)
begin
case estado is
when INICIAL =>
dep_estado <= "00";
DTR <= '0';
enable_recepcao <= '0';
when LIGADO =>
dep_estado <= "01";
DTR <= '1';
enable_recepcao <='0';
when RECEBENDO =>
dep_estado <= "10";
DTR <= '1';
enable_recepcao <= '1';
end case;
end process;
end estados;
|
library verilog;
use verilog.vl_types.all;
entity SeqSideEightBitAdder_vlg_check_tst is
port(
HEX0 : in vl_logic_vector(6 downto 0);
HEX1 : in vl_logic_vector(6 downto 0);
LEDR : in vl_logic_vector(8 downto 0);
sampler_rx : in vl_logic
);
end SeqSideEightBitAdder_vlg_check_tst;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dilate is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dilate;
architecture rtl of dilate is
component dilate_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
di00_reg_m00 : in std_logic_vector(7 downto 0);
di01_reg_m01 : in std_logic_vector(7 downto 0);
di02_reg_m02 : in std_logic_vector(7 downto 0);
di10_reg_m10 : in std_logic_vector(7 downto 0);
di11_reg_m11 : in std_logic_vector(7 downto 0);
di12_reg_m12 : in std_logic_vector(7 downto 0);
di20_reg_m20 : in std_logic_vector(7 downto 0);
di21_reg_m21 : in std_logic_vector(7 downto 0);
di22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component dilate_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_value : out std_logic_vector(15 downto 0);
di00_reg_m00 : out std_logic_vector(7 downto 0);
di01_reg_m01 : out std_logic_vector(7 downto 0);
di02_reg_m02 : out std_logic_vector(7 downto 0);
di10_reg_m10 : out std_logic_vector(7 downto 0);
di11_reg_m11 : out std_logic_vector(7 downto 0);
di12_reg_m12 : out std_logic_vector(7 downto 0);
di20_reg_m20 : out std_logic_vector(7 downto 0);
di21_reg_m21 : out std_logic_vector(7 downto 0);
di22_reg_m22 : out std_logic_vector(7 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_value : std_logic_vector (15 downto 0);
signal di00_reg_m00 : std_logic_vector (7 downto 0);
signal di01_reg_m01 : std_logic_vector (7 downto 0);
signal di02_reg_m02 : std_logic_vector (7 downto 0);
signal di10_reg_m10 : std_logic_vector (7 downto 0);
signal di11_reg_m11 : std_logic_vector (7 downto 0);
signal di12_reg_m12 : std_logic_vector (7 downto 0);
signal di20_reg_m20 : std_logic_vector (7 downto 0);
signal di21_reg_m21 : std_logic_vector (7 downto 0);
signal di22_reg_m22 : std_logic_vector (7 downto 0);
begin
dilate_process_inst : dilate_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
di00_reg_m00 => di00_reg_m00,
di01_reg_m01 => di01_reg_m01,
di02_reg_m02 => di02_reg_m02,
di10_reg_m10 => di10_reg_m10,
di11_reg_m11 => di11_reg_m11,
di12_reg_m12 => di12_reg_m12,
di20_reg_m20 => di20_reg_m20,
di21_reg_m21 => di21_reg_m21,
di22_reg_m22 => di22_reg_m22,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
dilate_slave_inst : dilate_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_value => widthimg_reg_value,
di00_reg_m00 => di00_reg_m00,
di01_reg_m01 => di01_reg_m01,
di02_reg_m02 => di02_reg_m02,
di10_reg_m10 => di10_reg_m10,
di11_reg_m11 => di11_reg_m11,
di12_reg_m12 => di12_reg_m12,
di20_reg_m20 => di20_reg_m20,
di21_reg_m21 => di21_reg_m21,
di22_reg_m22 => di22_reg_m22,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_69x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_69x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(69-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(69-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_69x512_hf_top_wrapper;
architecture xilinx of fifo_69x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_69x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_69x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
use work.pico_cpu.all;
entity PicoCPUTestBench is
end PicoCPUTestBench;
architecture Bench of PicoCPUTestBench is
--Component declaration for ALU
signal clk: std_logic:= '0';
signal rst: std_logic:= '0';
signal IO: std_logic_vector(CPU_Bitwidth-1 downto 0):= (others => 'Z');
begin
--Component instantiation of ALU
PicoCPU_comp: PicoCPU
generic map (Mem_preload_file => "code.txt")
port map (rst, clk, IO => IO);
CLOCK_GEN:process
begin
clk <= '0';
wait for clock_period/2;
clk <= '1';
wait for clock_period/2;
end process;
RST_GEN:process
begin
rst <= '1';
wait for 0.5*clock_period;
rst <= '0';
wait;
end process;
IO <= "00000000000000000000000000000001" after 36.5 ns;
end Bench;
|
------------------------------------------------------------------------------
-- qmfir.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: qmfir.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri Feb 25 13:30:06 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library interrupt_control_v2_01_a;
use interrupt_control_v2_01_a.interrupt_control;
library wrpfifo_v5_00_a;
use wrpfifo_v5_00_a.wrpfifo_top;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
-- C_MEM2_BASEADDR -- User memory space 2 base address
-- C_MEM2_HIGHADDR -- User memory space 2 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- IP2INTC_Irpt -- Interrupt output to processor
------------------------------------------------------------------------------
entity qmfir is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM1_HIGHADDR : std_logic_vector := X"00000000";
C_MEM2_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM2_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
IP2INTC_Irpt : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH";
end entity qmfir;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of qmfir is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant WFF_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant WFF_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF";
constant WFF_DAT_BASEADDR : std_logic_vector := C_BASEADDR or X"00000300";
constant WFF_DAT_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address
ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address
ZERO_ADDR_PAD & WFF_REG_BASEADDR, -- write pfifo register space base address
ZERO_ADDR_PAD & WFF_REG_HIGHADDR, -- write pfifo register space high address
ZERO_ADDR_PAD & WFF_DAT_BASEADDR, -- write pfifo data space base address
ZERO_ADDR_PAD & WFF_DAT_HIGHADDR, -- write pfifo data space high address
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR, -- user logic memory space 0 high address
ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
ZERO_ADDR_PAD & C_MEM1_HIGHADDR, -- user logic memory space 1 high address
ZERO_ADDR_PAD & C_MEM2_BASEADDR, -- user logic memory space 2 base address
ZERO_ADDR_PAD & C_MEM2_HIGHADDR -- user logic memory space 2 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant INTR_NUM_CE : integer := 16;
constant WFF_NUM_REG_CE : integer := 4;
constant WFF_NUM_DAT_CE : integer := 1;
constant USER_NUM_MEM : integer := 3;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => INTR_NUM_CE, -- number of ce for interrupt control space
2 => WFF_NUM_REG_CE, -- number of ce for write pfifo register space
3 => WFF_NUM_DAT_CE, -- number of ce for write pfifo data space
4 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
5 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable)
6 => 1 -- number of ce for user logic memory space 2 (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Number of device level interrupts
------------------------------------------
constant INTR_NUM_IPIF_IRPT_SRC : integer := 4;
------------------------------------------
-- Capture mode for each IP interrupt (generated by user logic)
-- 1 = pass through (non-inverting)
-- 2 = pass through (inverting)
-- 3 = registered level (non-inverting)
-- 4 = registered level (inverting)
-- 5 = positive edge detect
-- 6 = negative edge detect
------------------------------------------
constant USER_NUM_INTR : integer := 1;
constant USER_INTR_CAPTURE_MODE : integer := 1;
constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_INTR_CAPTURE_MODE
);
------------------------------------------
-- Device priority encoder feature inclusion/omission
-- true = include priority encoder
-- false = omit priority encoder
------------------------------------------
constant INTR_INCLUDE_DEV_PENCODER : boolean := true;
------------------------------------------
-- Device ISC feature inclusion/omission
-- true = include device ISC
-- false = omit device ISC
------------------------------------------
constant INTR_INCLUDE_DEV_ISC : boolean := true;
------------------------------------------
-- Write FIFO desired depth specified as a Log2(x) value (2 to 14)
------------------------------------------
constant USER_WRFIFO_DEPTH : integer := 512;
constant WFF_FIFO_DEPTH_LOG2X : integer := log2(USER_WRFIFO_DEPTH);
------------------------------------------
-- Write FIFO packet mode feature inclusion/omision
-- true = include packet mode features
-- false = omit packet mode features
------------------------------------------
constant WFF_INCLUDE_PACKET_MODE : boolean := true;
------------------------------------------
-- Write FIFO vacancy calculation inclusion/omision
-- true = include vacancy calculation
-- false = omit vacancy calculation
------------------------------------------
constant WFF_INCLUDE_VACANCY : boolean := true;
------------------------------------------
-- Write FIFO enable for host bus data burst support
-- true = support host bus data bursting
-- false = do not support host bus data bursting
------------------------------------------
constant WFF_SUPPORT_BURST : boolean := (C_SPLB_SUPPORT_BURSTS /= 0);
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant INTR_CS_INDEX : integer := 1;
constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
constant WFF_REG_CS_INDEX : integer := 2;
constant WFF_REG_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, WFF_REG_CS_INDEX);
constant WFF_DAT_CS_INDEX : integer := 3;
constant WFF_DAT_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, WFF_DAT_CS_INDEX);
constant USER_MEM0_CS_INDEX : integer := 4;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1);
signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal intr_IP2Bus_WrAck : std_logic;
signal intr_IP2Bus_RdAck : std_logic;
signal intr_IP2Bus_Error : std_logic;
signal wff_WFIFO2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal wff_WFIFO2IP_RdAck : std_logic;
signal wff_WFIFO2IP_AlmostEmpty : std_logic;
signal wff_WFIFO2IP_Empty : std_logic;
signal wff_WFIFO2IP_Occupancy : std_logic_vector(0 to WFF_FIFO_DEPTH_LOG2X);
signal wff_FIFO2IRPT_DeadLock : std_logic;
signal wff_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal wff_IP2Bus_WrAck : std_logic;
signal wff_IP2Bus_RdAck : std_logic;
signal wff_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1);
signal user_IP2WFIFO_RdReq : std_logic;
signal user_IP2WFIFO_RdMark : std_logic;
signal user_IP2WFIFO_RdRelease : std_logic;
signal user_IP2WFIFO_RdRestore : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4;
C_NUM_MEM : integer := 3;
C_NUM_INTR : integer := 1;
C_WRFIFO_DEPTH : integer := 512
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1);
IP2WFIFO_RdReq : out std_logic;
IP2WFIFO_RdMark : out std_logic;
IP2WFIFO_RdRelease : out std_logic;
IP2WFIFO_RdRestore : out std_logic;
WFIFO2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
WFIFO2IP_RdAck : in std_logic;
WFIFO2IP_AlmostEmpty : in std_logic;
WFIFO2IP_Empty : in std_logic;
WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH))
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate interrupt_control
------------------------------------------
INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
generic map
(
C_NUM_CE => INTR_NUM_CE,
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts,
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr_IP2Bus_Data,
Intr2Bus_WrAck => intr_IP2Bus_WrAck,
Intr2Bus_RdAck => intr_IP2Bus_RdAck,
Intr2Bus_Error => intr_IP2Bus_Error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
intr_IPIF_Reg_Interrupts(0) <= '0';
intr_IPIF_Reg_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(0) <= '0';
intr_IPIF_Lvl_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(2) <= '0';
intr_IPIF_Lvl_Interrupts(3) <= wff_FIFO2IRPT_DeadLock;
------------------------------------------
-- instantiate wrpfifo_top
------------------------------------------
WRPFIFO_TOP_I : entity wrpfifo_v5_00_a.wrpfifo_top
generic map
(
C_OPB_PROTOCOL => false,
C_MIR_ENABLE => false,
C_BLOCK_ID => 0,
C_NUM_REG_CE => WFF_NUM_REG_CE,
C_FIFO_DEPTH_LOG2X => WFF_FIFO_DEPTH_LOG2X,
C_FIFO_WIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_PACKET_MODE => WFF_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => WFF_INCLUDE_VACANCY,
C_SUPPORT_BURST => WFF_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
Bus_rst => ipif_Bus2IP_Reset,
Bus_clk => ipif_Bus2IP_Clk,
Bus_Burst => '0',
Bus_BE => ipif_Bus2IP_BE,
Bus2FIFO_Reg_RdCE => ipif_Bus2IP_RdCE(WFF_REG_CE_INDEX to WFF_REG_CE_INDEX+WFF_NUM_REG_CE-1),
Bus2FIFO_Data_RdCE => ipif_Bus2IP_RdCE(WFF_DAT_CE_INDEX),
Bus2FIFO_Reg_WrCE => ipif_Bus2IP_WrCE(WFF_REG_CE_INDEX to WFF_REG_CE_INDEX+WFF_NUM_REG_CE-1),
Bus2FIFO_Data_WrCE => ipif_Bus2IP_WrCE(WFF_DAT_CE_INDEX),
Bus_DBus => ipif_Bus2IP_Data,
BAWR_Push => '0',
IP2WFIFO_RdReq => user_IP2WFIFO_RdReq,
IP2WFIFO_RdMark => user_IP2WFIFO_RdMark,
IP2WFIFO_RdRestore => user_IP2WFIFO_RdRestore,
IP2WFIFO_RdRelease => user_IP2WFIFO_RdRelease,
WFIFO2IP_Data => wff_WFIFO2IP_Data,
WFIFO2IP_RdAck => wff_WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => wff_WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => wff_WFIFO2IP_Empty,
WFIFO2IP_Occupancy => wff_WFIFO2IP_Occupancy,
WFIFO2DMA_AlmostFull => open,
WFIFO2DMA_Full => open,
WFIFO2DMA_Vacancy => open,
FIFO2IRPT_DeadLock => wff_FIFO2IRPT_DeadLock,
FIFO2Bus_DBus => wff_IP2Bus_Data,
FIFO2Bus_WrAck => wff_IP2Bus_WrAck,
FIFO2Bus_RdAck => wff_IP2Bus_RdAck,
FIFO2Bus_Error => wff_IP2Bus_Error,
FIFO2Bus_Retry => open,
FIFO2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_MEM => USER_NUM_MEM,
C_NUM_INTR => USER_NUM_INTR,
C_WRFIFO_DEPTH => USER_WRFIFO_DEPTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
IP2WFIFO_RdReq => user_IP2WFIFO_RdReq,
IP2WFIFO_RdMark => user_IP2WFIFO_RdMark,
IP2WFIFO_RdRelease => user_IP2WFIFO_RdRelease,
IP2WFIFO_RdRestore => user_IP2WFIFO_RdRestore,
WFIFO2IP_Data => wff_WFIFO2IP_Data,
WFIFO2IP_RdAck => wff_WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => wff_WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => wff_WFIFO2IP_Empty,
WFIFO2IP_Occupancy => wff_WFIFO2IP_Occupancy
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data, wff_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0100000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
when "0010000" => ipif_IP2Bus_Data <= wff_IP2Bus_Data;
when "0001000" => ipif_IP2Bus_Data <= wff_IP2Bus_Data;
when "0000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck or wff_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck or wff_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error or wff_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
------------------------------------------------------------------------------
-- qmfir.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: qmfir.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri Feb 25 13:30:06 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library interrupt_control_v2_01_a;
use interrupt_control_v2_01_a.interrupt_control;
library wrpfifo_v5_00_a;
use wrpfifo_v5_00_a.wrpfifo_top;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
-- C_MEM2_BASEADDR -- User memory space 2 base address
-- C_MEM2_HIGHADDR -- User memory space 2 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- IP2INTC_Irpt -- Interrupt output to processor
------------------------------------------------------------------------------
entity qmfir is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM1_HIGHADDR : std_logic_vector := X"00000000";
C_MEM2_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM2_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
IP2INTC_Irpt : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH";
end entity qmfir;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of qmfir is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant WFF_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant WFF_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"000002FF";
constant WFF_DAT_BASEADDR : std_logic_vector := C_BASEADDR or X"00000300";
constant WFF_DAT_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address
ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address
ZERO_ADDR_PAD & WFF_REG_BASEADDR, -- write pfifo register space base address
ZERO_ADDR_PAD & WFF_REG_HIGHADDR, -- write pfifo register space high address
ZERO_ADDR_PAD & WFF_DAT_BASEADDR, -- write pfifo data space base address
ZERO_ADDR_PAD & WFF_DAT_HIGHADDR, -- write pfifo data space high address
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR, -- user logic memory space 0 high address
ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
ZERO_ADDR_PAD & C_MEM1_HIGHADDR, -- user logic memory space 1 high address
ZERO_ADDR_PAD & C_MEM2_BASEADDR, -- user logic memory space 2 base address
ZERO_ADDR_PAD & C_MEM2_HIGHADDR -- user logic memory space 2 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant INTR_NUM_CE : integer := 16;
constant WFF_NUM_REG_CE : integer := 4;
constant WFF_NUM_DAT_CE : integer := 1;
constant USER_NUM_MEM : integer := 3;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => INTR_NUM_CE, -- number of ce for interrupt control space
2 => WFF_NUM_REG_CE, -- number of ce for write pfifo register space
3 => WFF_NUM_DAT_CE, -- number of ce for write pfifo data space
4 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
5 => 1, -- number of ce for user logic memory space 1 (always 1 chip enable)
6 => 1 -- number of ce for user logic memory space 2 (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Number of device level interrupts
------------------------------------------
constant INTR_NUM_IPIF_IRPT_SRC : integer := 4;
------------------------------------------
-- Capture mode for each IP interrupt (generated by user logic)
-- 1 = pass through (non-inverting)
-- 2 = pass through (inverting)
-- 3 = registered level (non-inverting)
-- 4 = registered level (inverting)
-- 5 = positive edge detect
-- 6 = negative edge detect
------------------------------------------
constant USER_NUM_INTR : integer := 1;
constant USER_INTR_CAPTURE_MODE : integer := 1;
constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_INTR_CAPTURE_MODE
);
------------------------------------------
-- Device priority encoder feature inclusion/omission
-- true = include priority encoder
-- false = omit priority encoder
------------------------------------------
constant INTR_INCLUDE_DEV_PENCODER : boolean := true;
------------------------------------------
-- Device ISC feature inclusion/omission
-- true = include device ISC
-- false = omit device ISC
------------------------------------------
constant INTR_INCLUDE_DEV_ISC : boolean := true;
------------------------------------------
-- Write FIFO desired depth specified as a Log2(x) value (2 to 14)
------------------------------------------
constant USER_WRFIFO_DEPTH : integer := 512;
constant WFF_FIFO_DEPTH_LOG2X : integer := log2(USER_WRFIFO_DEPTH);
------------------------------------------
-- Write FIFO packet mode feature inclusion/omision
-- true = include packet mode features
-- false = omit packet mode features
------------------------------------------
constant WFF_INCLUDE_PACKET_MODE : boolean := true;
------------------------------------------
-- Write FIFO vacancy calculation inclusion/omision
-- true = include vacancy calculation
-- false = omit vacancy calculation
------------------------------------------
constant WFF_INCLUDE_VACANCY : boolean := true;
------------------------------------------
-- Write FIFO enable for host bus data burst support
-- true = support host bus data bursting
-- false = do not support host bus data bursting
------------------------------------------
constant WFF_SUPPORT_BURST : boolean := (C_SPLB_SUPPORT_BURSTS /= 0);
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant INTR_CS_INDEX : integer := 1;
constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
constant WFF_REG_CS_INDEX : integer := 2;
constant WFF_REG_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, WFF_REG_CS_INDEX);
constant WFF_DAT_CS_INDEX : integer := 3;
constant WFF_DAT_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, WFF_DAT_CS_INDEX);
constant USER_MEM0_CS_INDEX : integer := 4;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1);
signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal intr_IP2Bus_WrAck : std_logic;
signal intr_IP2Bus_RdAck : std_logic;
signal intr_IP2Bus_Error : std_logic;
signal wff_WFIFO2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal wff_WFIFO2IP_RdAck : std_logic;
signal wff_WFIFO2IP_AlmostEmpty : std_logic;
signal wff_WFIFO2IP_Empty : std_logic;
signal wff_WFIFO2IP_Occupancy : std_logic_vector(0 to WFF_FIFO_DEPTH_LOG2X);
signal wff_FIFO2IRPT_DeadLock : std_logic;
signal wff_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal wff_IP2Bus_WrAck : std_logic;
signal wff_IP2Bus_RdAck : std_logic;
signal wff_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1);
signal user_IP2WFIFO_RdReq : std_logic;
signal user_IP2WFIFO_RdMark : std_logic;
signal user_IP2WFIFO_RdRelease : std_logic;
signal user_IP2WFIFO_RdRestore : std_logic;
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4;
C_NUM_MEM : integer := 3;
C_NUM_INTR : integer := 1;
C_WRFIFO_DEPTH : integer := 512
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1);
IP2WFIFO_RdReq : out std_logic;
IP2WFIFO_RdMark : out std_logic;
IP2WFIFO_RdRelease : out std_logic;
IP2WFIFO_RdRestore : out std_logic;
WFIFO2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
WFIFO2IP_RdAck : in std_logic;
WFIFO2IP_AlmostEmpty : in std_logic;
WFIFO2IP_Empty : in std_logic;
WFIFO2IP_Occupancy : in std_logic_vector(0 to log2(C_WRFIFO_DEPTH))
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate interrupt_control
------------------------------------------
INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
generic map
(
C_NUM_CE => INTR_NUM_CE,
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts,
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr_IP2Bus_Data,
Intr2Bus_WrAck => intr_IP2Bus_WrAck,
Intr2Bus_RdAck => intr_IP2Bus_RdAck,
Intr2Bus_Error => intr_IP2Bus_Error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
intr_IPIF_Reg_Interrupts(0) <= '0';
intr_IPIF_Reg_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(0) <= '0';
intr_IPIF_Lvl_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(2) <= '0';
intr_IPIF_Lvl_Interrupts(3) <= wff_FIFO2IRPT_DeadLock;
------------------------------------------
-- instantiate wrpfifo_top
------------------------------------------
WRPFIFO_TOP_I : entity wrpfifo_v5_00_a.wrpfifo_top
generic map
(
C_OPB_PROTOCOL => false,
C_MIR_ENABLE => false,
C_BLOCK_ID => 0,
C_NUM_REG_CE => WFF_NUM_REG_CE,
C_FIFO_DEPTH_LOG2X => WFF_FIFO_DEPTH_LOG2X,
C_FIFO_WIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_PACKET_MODE => WFF_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => WFF_INCLUDE_VACANCY,
C_SUPPORT_BURST => WFF_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
Bus_rst => ipif_Bus2IP_Reset,
Bus_clk => ipif_Bus2IP_Clk,
Bus_Burst => '0',
Bus_BE => ipif_Bus2IP_BE,
Bus2FIFO_Reg_RdCE => ipif_Bus2IP_RdCE(WFF_REG_CE_INDEX to WFF_REG_CE_INDEX+WFF_NUM_REG_CE-1),
Bus2FIFO_Data_RdCE => ipif_Bus2IP_RdCE(WFF_DAT_CE_INDEX),
Bus2FIFO_Reg_WrCE => ipif_Bus2IP_WrCE(WFF_REG_CE_INDEX to WFF_REG_CE_INDEX+WFF_NUM_REG_CE-1),
Bus2FIFO_Data_WrCE => ipif_Bus2IP_WrCE(WFF_DAT_CE_INDEX),
Bus_DBus => ipif_Bus2IP_Data,
BAWR_Push => '0',
IP2WFIFO_RdReq => user_IP2WFIFO_RdReq,
IP2WFIFO_RdMark => user_IP2WFIFO_RdMark,
IP2WFIFO_RdRestore => user_IP2WFIFO_RdRestore,
IP2WFIFO_RdRelease => user_IP2WFIFO_RdRelease,
WFIFO2IP_Data => wff_WFIFO2IP_Data,
WFIFO2IP_RdAck => wff_WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => wff_WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => wff_WFIFO2IP_Empty,
WFIFO2IP_Occupancy => wff_WFIFO2IP_Occupancy,
WFIFO2DMA_AlmostFull => open,
WFIFO2DMA_Full => open,
WFIFO2DMA_Vacancy => open,
FIFO2IRPT_DeadLock => wff_FIFO2IRPT_DeadLock,
FIFO2Bus_DBus => wff_IP2Bus_Data,
FIFO2Bus_WrAck => wff_IP2Bus_WrAck,
FIFO2Bus_RdAck => wff_IP2Bus_RdAck,
FIFO2Bus_Error => wff_IP2Bus_Error,
FIFO2Bus_Retry => open,
FIFO2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_MEM => USER_NUM_MEM,
C_NUM_INTR => USER_NUM_INTR,
C_WRFIFO_DEPTH => USER_WRFIFO_DEPTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
IP2WFIFO_RdReq => user_IP2WFIFO_RdReq,
IP2WFIFO_RdMark => user_IP2WFIFO_RdMark,
IP2WFIFO_RdRelease => user_IP2WFIFO_RdRelease,
IP2WFIFO_RdRestore => user_IP2WFIFO_RdRestore,
WFIFO2IP_Data => wff_WFIFO2IP_Data,
WFIFO2IP_RdAck => wff_WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty => wff_WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty => wff_WFIFO2IP_Empty,
WFIFO2IP_Occupancy => wff_WFIFO2IP_Occupancy
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data, wff_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1000000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0100000" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
when "0010000" => ipif_IP2Bus_Data <= wff_IP2Bus_Data;
when "0001000" => ipif_IP2Bus_Data <= wff_IP2Bus_Data;
when "0000100" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0000010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0000001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck or wff_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck or wff_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error or wff_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package breakout_config is
type control_signal_out is (go_up, go_down, go_left, go_right, pause, end_game, launch, none);
constant SCREEN_Y_BEGIN : integer := 64;
constant SCREEN_Y_END : integer := 80;
constant SCREEN_BRICK_BEGIN : integer := 116;
constant SCREEN_BRICK_END : integer := 164;
constant PADDLE_WIDTH : integer := 48;
constant BALL_WIDTH : integer := 8;
constant BALL_HEIGHT : integer := 6;
constant SCREEN_PADDLE_BEGIN : integer := 450;
constant SCREEN_PADDLE_END : integer := 456;
constant SCREEN_X_BEGIN : integer := 32;
constant SCREEN_X_END : integer := 608;
end breakout_config;
|
-- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector(DWIDTH - 1 downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector(DWIDTH - 1 downto 0); -- dob delay = 2 clk compared with rdb
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector(AWIDTH -1 downto 0)
);
end fifo_async;
architecture fast_read of fifo_async is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal wea_sync : std_logic := '0';
signal wp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clka)
begin
if reset = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
wp <= (others => '0');
elsif full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ASYNCWRITE_wea_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clka,
sync_clk => clkb,
async_wren => wea,
trigger => '1',
sync_wren => wea_sync,
over => open,
flag => open
);
WritePointorCtrl_sync : process(reset,clkb)
begin
if reset = '1' then
wp_sync <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
wp_sync <= (others => '0');
elsif full_flag = '0' and wea_sync = '1' then
wp_sync <= wp_sync + 1;
end if;
end if;
end process;
ReadPointorCtrl : process(reset,clkb)
begin
if reset = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
rp <= (others => '0');
elsif empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clkb)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clkb) then
if clr = '1' then
empty_flag <= '1';
elsif (wp_sync = rp) and (wea_sync = '1') then
empty_flag <= '0';
elsif (wp_sync = rp + 1) and (rdb = '1'and wea_sync = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clkb)
begin
if reset = '1' then
full_flag <= '0';
elsif rising_edge(clkb) then
if clr = '1' then
full_flag <= '0';
elsif (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
full_flag <= '1';
elsif (wp_sync = rp) and (rdb = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp_sync - rp;
end fast_read;
---------------------------------------------------------------------------------
architecture fast_write of fifo_async is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal rdb_sync : std_logic := '0';
signal rp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clka)
begin
if reset = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
wp <= (others => '0');
elsif full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ReadPointorCtrl : process(reset,clkb)
begin
if reset = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
if clr = '1' then
rp <= (others => '0');
elsif empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
ASYNCWRITE_rdb_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clkb,
sync_clk => clka,
async_wren => rdb,
trigger => '1',
sync_wren => rdb_sync,
over => open,
flag => open
);
ReadPointorCtrl_sync : process(reset,clka)
begin
if reset = '1' then
rp_sync <= (others => '0');
elsif rising_edge(clka) then
if clr = '1' then
rp_sync <= (others => '0');
elsif empty_flag = '0' and rdb_sync = '1' then
rp_sync <= rp_sync + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clka)
begin
if reset = '1' then
empty_flag <= '1';
elsif rising_edge(clka) then
if clr = '1' then
empty_flag <= '1';
elsif (wp = rp_sync) and (wea = '1') then
empty_flag <= '0';
elsif (wp = rp_sync + 1) and (rdb_sync = '1'and wea = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clka)
begin
if reset = '1' then
full_flag <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
if clr = '1' then
full_flag <= '0';
elsif (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
full_flag <= '1';
elsif (wp = rp_sync) and (rdb_sync = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp - rp_sync;
end fast_write;
|
architecture Struct of TbdAudioCodecAvalon is
component Audio is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
audio_clk_clk : out std_logic; -- clk
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck : in std_logic := 'X'; -- adclrck
i2s_bclk : in std_logic := 'X'; -- bclk
i2s_dacdat : out std_logic; -- dacdat
i2s_daclrck : in std_logic := 'X'; -- daclrck
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic -- SCLK
);
end component Audio;
begin -- architecture Struct
u0 : component Audio
port map (
reset_reset_n => KEY(0), -- reset.reset_n
clk_clk => CLOCK_50, -- clk.clk
audio_clk_clk => AUD_XCK, -- audio_clk.clk
i2s_adcdat => AUD_ADCDAT, -- i2s.adcdat
i2s_adclrck => AUD_ADCLRCK, -- .adclrck
i2s_bclk => AUD_BCLK, -- .bclk
i2s_dacdat => AUD_DACDAT, -- .dacdat
i2s_daclrck => AUD_DACLRCK, -- .daclrck
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK -- .SCLK
);
end architecture Struct;
|
entity should_fold is
generic ( X : boolean );
end entity;
architecture test of should_fold is
begin
g: if not X generate -- Error if not constant folded
assert X;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity ieee5 is
end entity;
library ieee;
use ieee.math_real.all;
architecture test of ieee5 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
begin
s1: entity work.should_fold
generic map ( approx(sign(6.8), 1.0) );
s2: entity work.should_fold
generic map ( approx(ceil(5.7), 6.0) );
s3: entity work.should_fold
generic map ( approx(floor(0.6), 0.0) );
s4: entity work.should_fold
generic map ( approx(round(0.5), 1.0) );
s5: entity work.should_fold
generic map ( approx(round(6.4999), 6.0) );
s6: entity work.should_fold
generic map ( approx(trunc(0.999), 0.0) );
s7: entity work.should_fold
generic map ( approx(4.6 mod 2.7, 1.9) );
s8: entity work.should_fold
generic map ( approx(sin(MATH_PI), 0.0) );
s9: entity work.should_fold
generic map ( approx(cos(1.15251), 0.406195) );
s10: entity work.should_fold
generic map ( approx(arctan(0.5), 0.463648) );
end architecture;
|
entity should_fold is
generic ( X : boolean );
end entity;
architecture test of should_fold is
begin
g: if not X generate -- Error if not constant folded
assert X;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity ieee5 is
end entity;
library ieee;
use ieee.math_real.all;
architecture test of ieee5 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
begin
s1: entity work.should_fold
generic map ( approx(sign(6.8), 1.0) );
s2: entity work.should_fold
generic map ( approx(ceil(5.7), 6.0) );
s3: entity work.should_fold
generic map ( approx(floor(0.6), 0.0) );
s4: entity work.should_fold
generic map ( approx(round(0.5), 1.0) );
s5: entity work.should_fold
generic map ( approx(round(6.4999), 6.0) );
s6: entity work.should_fold
generic map ( approx(trunc(0.999), 0.0) );
s7: entity work.should_fold
generic map ( approx(4.6 mod 2.7, 1.9) );
s8: entity work.should_fold
generic map ( approx(sin(MATH_PI), 0.0) );
s9: entity work.should_fold
generic map ( approx(cos(1.15251), 0.406195) );
s10: entity work.should_fold
generic map ( approx(arctan(0.5), 0.463648) );
end architecture;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity gamma_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/gamma_output.pgm"; --! Output file of test
gamma: real := 0.5; --! Amount of contrast adjustment
c_factor: real := 1.0 --! Amount of contrast adjustment
);
end entity;
--======================================================================================--
architecture structural of gamma_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 3
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
pixel_from_file: out std_logic_vector((wordsize-1) downto 0);
pixel_to_file: in std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
component lookup_table is
generic (
wordsize: integer := const_wordsize;
lut: array_pixel := create_gamma_lut(2**const_wordsize, gamma, c_factor)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
pixel_i: in std_logic_vector((wordsize-1) downto 0);
pixel_o: out std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: lookup_table
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity gamma_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/gamma_output.pgm"; --! Output file of test
gamma: real := 0.5; --! Amount of contrast adjustment
c_factor: real := 1.0 --! Amount of contrast adjustment
);
end entity;
--======================================================================================--
architecture structural of gamma_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 3
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
pixel_from_file: out std_logic_vector((wordsize-1) downto 0);
pixel_to_file: in std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
component lookup_table is
generic (
wordsize: integer := const_wordsize;
lut: array_pixel := create_gamma_lut(2**const_wordsize, gamma, c_factor)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
pixel_i: in std_logic_vector((wordsize-1) downto 0);
pixel_o: out std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: lookup_table
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tx_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo_tx_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo_tx_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
-- NEED RESULT: ARCH00677: Attributes inherited by aliases passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00677
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.4 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00677)
-- ENT00677_Test_Bench(ARCH00677_Test_Bench)
--
-- REVISION HISTORY:
--
-- 1-SEP-1987 - initial revision
-- 17-JUN-1988 - (KLM) added wait at end of process
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00677 of E00000 is
signal s : string ( 1 to 3 ) ;
attribute at : boolean ;
attribute at of s : signal is true ;
alias al_s : string ( 2 to 4) is s ;
begin
process
subtype st is integer range al_s'range ;
begin
test_report ( "ARCH00677" ,
"Attributes inherited by aliases" ,
st'left = 2 and al_s'at ) ;
wait;
end process ;
end ARCH00677 ;
--
entity ENT00677_Test_Bench is
end ENT00677_Test_Bench ;
architecture ARCH00677_Test_Bench of ENT00677_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00677 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00677_Test_Bench ;
--
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForwardingUnit is
Port ( EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0);
ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0));
end ForwardingUnit;
architecture Behavioral of ForwardingUnit is
begin
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RS,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RS then
AnticipaA<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RS and MEM_WB_RD=ID_EX_RS then
AnticipaA<="01";
else
AnticipaA<="00";
end if;
end process;
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RT,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RT then
AnticipaB<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RT and MEM_WB_RD=ID_EX_RT then
AnticipaB<="01";
else
AnticipaB<="00";
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ForwardingUnit is
Port ( EX_MEM_ESCREG : in STD_LOGIC;
MEM_WB_ESCREG : in STD_LOGIC;
AnticipaA : out STD_LOGIC_VECTOR (1 downto 0);
AnticipaB : out STD_LOGIC_VECTOR (1 downto 0);
ID_EX_RS : in STD_LOGIC_VECTOR (4 downto 0);
ID_EX_RT : in STD_LOGIC_VECTOR (4 downto 0);
EX_MEM_RD : in STD_LOGIC_VECTOR (4 downto 0);
MEM_WB_RD : in STD_LOGIC_VECTOR (4 downto 0));
end ForwardingUnit;
architecture Behavioral of ForwardingUnit is
begin
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RS,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RS then
AnticipaA<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RS and MEM_WB_RD=ID_EX_RS then
AnticipaA<="01";
else
AnticipaA<="00";
end if;
end process;
process (EX_MEM_ESCREG,EX_MEM_RD,ID_EX_RT,MEM_WB_ESCREG,MEM_WB_RD)
begin
if EX_MEM_ESCREG='1' and EX_MEM_RD/="00000" and EX_MEM_RD=ID_EX_RT then
AnticipaB<="10";
elsif MEM_WB_ESCREG='1' and MEM_WB_RD/="00000" and EX_MEM_RD/=ID_EX_RT and MEM_WB_RD=ID_EX_RT then
AnticipaB<="01";
else
AnticipaB<="00";
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00039ent IS
END c04s03b01x01p02n01i00039ent;
ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
constant C1 : Boolean := 10 = 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = true )
report "***PASSED TEST: c04s03b01x01p02n01i00039"
severity NOTE;
assert ( C1 = true )
report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00039arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00039ent IS
END c04s03b01x01p02n01i00039ent;
ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
constant C1 : Boolean := 10 = 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = true )
report "***PASSED TEST: c04s03b01x01p02n01i00039"
severity NOTE;
assert ( C1 = true )
report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00039arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00039ent IS
END c04s03b01x01p02n01i00039ent;
ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
constant C1 : Boolean := 10 = 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( C1 = true )
report "***PASSED TEST: c04s03b01x01p02n01i00039"
severity NOTE;
assert ( C1 = true )
report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00039arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1277.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01277ent IS
END c08s04b00x00p04n01i01277ent;
ARCHITECTURE c08s04b00x00p04n01i01277arch OF c08s04b00x00p04n01i01277ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1**2 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01277 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01277arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1277.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01277ent IS
END c08s04b00x00p04n01i01277ent;
ARCHITECTURE c08s04b00x00p04n01i01277arch OF c08s04b00x00p04n01i01277ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1**2 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01277 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01277arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1277.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01277ent IS
END c08s04b00x00p04n01i01277ent;
ARCHITECTURE c08s04b00x00p04n01i01277arch OF c08s04b00x00p04n01i01277ent IS
signal S1 : integer ;
BEGIN
TESTING: PROCESS
BEGIN
S1**2 <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01277 - Simple expressions are not allowed on the left-hand side of a signal assignment."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01277arch;
|
entity vhdl2008 is
end entity;
architecture test of vhdl2008 is
begin
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
x := 5 when x; -- Error
x := 1 when x < 1 else false; -- Error
end process;
-- Changes to locally static rules
process is
type r is record
k : bit;
end record;
constant c : bit_vector(1 to 3) := "101";
constant d : r := ( k => '1' );
variable x : bit;
variable y : r;
variable i : integer;
begin
case x is
when c(1) => null; -- OK
when d.k => null; -- OK
when c(i) => null; -- Error
when others => null;
end case;
end process;
-- 'SUBTYPE attribute
process is
variable x : integer;
begin
x := baz'subtype(4); -- Error
report to_string(x'subtype); -- Error
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : eth_filter
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Filter block for ethernet frames
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.block_bus_pkg.all;
use work.mem_bus_pkg.all;
entity eth_filter is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"13" );
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req;
io_resp : out t_io_resp;
-- interface to free block system
alloc_req : out std_logic;
alloc_resp : in t_alloc_resp;
used_req : out t_used_req;
used_resp : in std_logic;
-- interface to memory
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
----
eth_clock : in std_logic;
eth_reset : in std_logic;
eth_rx_data : in std_logic_vector(7 downto 0);
eth_rx_sof : in std_logic;
eth_rx_eof : in std_logic;
eth_rx_valid : in std_logic );
end entity;
architecture gideon of eth_filter is
-- signals in the sys_clock domain
type t_mac is array(0 to 5) of std_logic_vector(7 downto 0);
signal my_mac : t_mac := (others => (others => '0'));
type t_mac_16 is array(0 to 2) of std_logic_vector(15 downto 0);
signal my_mac_16 : t_mac_16 := (others => (others => '0'));
signal eth_rx_enable : std_logic;
signal clear : std_logic;
signal rx_enable : std_logic;
signal promiscuous : std_logic;
signal rd_next : std_logic;
signal rd_dout : std_logic_vector(17 downto 0);
signal rd_valid : std_logic;
type t_receive_state is (idle, odd, even, len, ovfl);
signal receive_state : t_receive_state;
type t_state is (idle, get_block, drop, copy, valid_packet, pushing, ram_write);
signal state : t_state;
signal address_valid : std_logic;
signal start_addr : unsigned(25 downto 0);
signal mac_idx : integer range 0 to 3;
signal for_me : std_logic;
signal block_id : unsigned(7 downto 0);
-- memory signals
signal mem_addr : unsigned(25 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_req : std_logic;
-- signals in eth_clock domain
signal eth_wr_din : std_logic_vector(17 downto 0);
signal eth_wr_en : std_logic;
signal eth_wr_full : std_logic;
signal eth_length : unsigned(11 downto 0);
signal crc_ok : std_logic;
signal toggle : std_logic;
begin
-- 18 wide fifo; 16 data bits and 2 control bits
-- 00 = packet data
-- 01 = overflow detected => drop
-- 10 = packet with CRC error => drop
-- 11 = packet OK!
i_fifo: entity work.async_fifo_ft
generic map (
--g_fast => true,
g_data_width => 18,
g_depth_bits => 9
)
port map (
wr_clock => eth_clock,
wr_reset => eth_reset,
wr_en => eth_wr_en,
wr_din => eth_wr_din,
wr_full => eth_wr_full,
rd_clock => clock,
rd_reset => clear,
rd_next => rd_next,
rd_dout => rd_dout,
rd_valid => rd_valid
);
clear <= reset or not rx_enable;
process(eth_clock)
begin
if rising_edge(eth_clock) then
eth_wr_en <= '0';
case receive_state is
when idle =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_length <= to_unsigned(1, eth_length'length);
if eth_rx_sof = '1' and eth_rx_valid = '1' then
receive_state <= odd;
end if;
when odd =>
eth_wr_din(15 downto 8) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_wr_full = '1' then
receive_state <= ovfl;
else
eth_wr_en <= '1';
crc_ok <= eth_rx_data(0);
if eth_rx_eof = '1' then
receive_state <= len;
else
receive_state <= even;
end if;
end if;
end if;
when even =>
eth_wr_din(7 downto 0) <= eth_rx_data;
eth_wr_din(17 downto 16) <= "00";
if eth_rx_valid = '1' then
eth_length <= eth_length + 1;
if eth_rx_eof = '1' then
receive_state <= len;
crc_ok <= eth_rx_data(0);
else
receive_state <= odd;
end if;
end if;
when len =>
if eth_wr_full = '0' then
eth_wr_din <= (others => '0');
eth_wr_din(17) <= '1';
eth_wr_din(16) <= crc_ok;
eth_wr_din(eth_length'range) <= std_logic_vector(eth_length);
eth_wr_en <= '1';
receive_state <= idle;
else
receive_state <= ovfl;
end if;
when ovfl =>
if eth_wr_full = '0' then
eth_wr_din(17 downto 16) <= "01";
eth_wr_en <= '1';
receive_state <= idle;
end if;
end case;
if eth_reset = '1' or eth_rx_enable = '0' then
receive_state <= idle;
crc_ok <= '0';
end if;
end if;
end process;
i_sync_enable: entity work.level_synchronizer
port map (
clock => eth_clock,
reset => eth_reset,
input => rx_enable,
input_c => eth_rx_enable
);
process(clock)
alias local_addr : unsigned(3 downto 0) is io_req.address(3 downto 0);
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write = '1' then
io_resp.ack <= '1';
case local_addr is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5" =>
my_mac(to_integer(local_addr)) <= io_req.data;
when X"7" =>
promiscuous <= io_req.data(0);
when X"8" =>
rx_enable <= io_req.data(0);
when others =>
null;
end case;
end if;
if io_req.read = '1' then
io_resp.ack <= '1';
case local_addr is
when others =>
null;
end case;
end if;
if reset = '1' then
promiscuous <= '0';
rx_enable <= '0';
end if;
end if;
end process;
-- condense to do 16 bit compares with data from fifo
my_mac_16(0) <= my_mac(1) & my_mac(0);
my_mac_16(1) <= my_mac(3) & my_mac(2);
my_mac_16(2) <= my_mac(5) & my_mac(4);
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
mac_idx <= 0;
toggle <= '0';
for_me <= '1';
if rx_enable = '0' then
address_valid <= '0';
end if;
if rd_valid = '1' then -- packet data available!
if rd_dout(17 downto 16) = "00" then
if rx_enable = '0' then
state <= drop;
elsif address_valid = '1' then
mem_addr <= start_addr;
state <= copy;
else
alloc_req <= '1';
state <= get_block;
end if;
else
state <= drop; -- resyncronize
end if;
end if;
when get_block =>
if alloc_resp.done = '1' then
alloc_req <= '0';
block_id <= alloc_resp.id;
if alloc_resp.error = '1' then
state <= drop;
else
start_addr <= alloc_resp.address;
mem_addr <= alloc_resp.address;
address_valid <= '1';
state <= copy;
end if;
end if;
when drop =>
if (rd_valid = '1' and rd_dout(17 downto 16) /= "00") or (rx_enable = '0') then
state <= idle;
end if;
when copy =>
if rx_enable = '0' then
state <= idle;
elsif rd_valid = '1' then
if mac_idx /= 3 then
if rd_dout(15 downto 0) /= X"FFFF" and rd_dout(15 downto 0) /= my_mac_16(mac_idx) then
for_me <= '0';
end if;
mac_idx <= mac_idx + 1;
end if;
toggle <= not toggle;
if toggle = '0' then
mem_data(31 downto 16) <= rd_dout(15 downto 0);
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= ram_write;
end if;
else
mem_data(15 downto 0) <= rd_dout(15 downto 0);
end if;
case rd_dout(17 downto 16) is
when "01" =>
-- overflow detected
write_req <= '0';
state <= idle;
when "10" =>
-- packet with bad CRC
write_req <= '0';
state <= idle;
when "11" =>
-- correct packet!
used_req.bytes <= unsigned(rd_dout(used_req.bytes'range)) - 5; -- snoop FF and CRC
if for_me = '1' or promiscuous = '1' then
write_req <= '1';
state <= valid_packet;
else
state <= idle;
end if;
when others =>
null;
end case;
end if;
when ram_write =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
mem_addr <= mem_addr + 4;
state <= copy;
end if;
when valid_packet =>
if mem_resp.rack_tag = g_mem_tag then
write_req <= '0';
if for_me = '1' or promiscuous = '1' then
address_valid <= '0';
used_req.request <= '1';
used_req.id <= block_id;
state <= pushing;
else
state <= idle;
end if;
end if;
when pushing =>
if used_resp = '1' then
used_req.request <= '0';
state <= idle;
end if;
end case;
if reset = '1' then
alloc_req <= '0';
used_req <= c_used_req_init;
state <= idle;
address_valid <= '0';
write_req <= '0';
end if;
end if;
end process;
mem_req.request <= write_req;
mem_req.data <= mem_data;
mem_req.address <= mem_addr;
mem_req.read_writen <= '0';
mem_req.byte_en <= (others => '1');
mem_req.tag <= g_mem_tag;
process(state)
begin
case state is
when drop =>
rd_next <= '1';
when copy =>
rd_next <= '1'; -- do something here with memory
when others =>
rd_next <= '0';
end case;
end process;
end architecture;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiv_atom_pack.all;
package stratixiv_components is
--
-- stratixiv_jtag
--
COMPONENT stratixiv_jtag
generic (
lpm_type : string := "stratixiv_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixiv_crcblock
--
COMPONENT stratixiv_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiv_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiv_lcell_comb
--
COMPONENT stratixiv_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiv_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixiv_routing_wire
--
COMPONENT stratixiv_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixiv_lvds_transmitter
--
COMPONENT stratixiv_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- STRATIXIV
tx_output_path_delay_engineering_bits : Integer := -1; -- STRATIXIV
enable_dpaclk_to_lvdsout : string := "off"; -- STRATIXIV
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiv_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- STRATIXIV
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- STRATIXIV
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- STRATIXIV
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- stratixiv_rublock
--
COMPONENT stratixiv_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiv_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiv_ram_block
--
COMPONENT stratixiv_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiv_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_ff
--
COMPONENT stratixiv_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiv_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- stratixiv_clkselect
--
COMPONENT stratixiv_clkselect
generic (
lpm_type : STRING := "stratixiv_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiv_clkena
--
COMPONENT stratixiv_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiv_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiv_mlab_cell
--
COMPONENT stratixiv_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiv_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_io_ibuf
--
COMPONENT stratixiv_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiv_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_obuf
--
COMPONENT stratixiv_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiv_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_ddio_in
--
COMPONENT stratixiv_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiv_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_ddio_oe
--
COMPONENT stratixiv_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiv_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_ddio_out
--
COMPONENT stratixiv_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiv_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_termination
--
COMPONENT stratixiv_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiv_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- stratixiv_termination_logic
--
COMPONENT stratixiv_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiv_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- stratixiv_dll
--
COMPONENT stratixiv_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiv_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dll_offset_ctrl
--
COMPONENT stratixiv_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiv_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_dqs_delay_chain
--
COMPONENT stratixiv_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_enable
--
COMPONENT stratixiv_dqs_enable
GENERIC (
lpm_type : string := "stratixiv_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_enable_ctrl
--
COMPONENT stratixiv_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_delay_chain
--
COMPONENT stratixiv_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiv_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_clock_divider
--
COMPONENT stratixiv_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_output_phase_alignment
--
COMPONENT stratixiv_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiv_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_input_phase_alignment
--
COMPONENT stratixiv_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiv_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_half_rate_input
--
COMPONENT stratixiv_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiv_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_io_config
--
COMPONENT stratixiv_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_dqs_config
--
COMPONENT stratixiv_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiv_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_mac_mult
--
COMPONENT stratixiv_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_mac_out
--
COMPONENT stratixiv_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiv_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_io_pad
--
COMPONENT stratixiv_io_pad
GENERIC (
lpm_type : string := "stratixiv_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- stratixiv_pll
--
COMPONENT stratixiv_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiv_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "STRATIXIV";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- stratixiv_asmiblock
--
COMPONENT stratixiv_asmiblock
generic (
lpm_type : string := "stratixiv_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- stratixiv_lvds_receiver
--
COMPONENT stratixiv_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiv_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiv_pseudo_diff_out
--
COMPONENT stratixiv_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiv_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiv_bias_block
--
COMPONENT stratixiv_bias_block
GENERIC (
lpm_type : string := "stratixiv_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- stratixiv_tsdblock
--
COMPONENT stratixiv_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiv_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
END COMPONENT;
end stratixiv_components;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:45 01/24/2015
-- Design Name:
-- Module Name: /home/james/devroot/learnfpga/analogue/vhdl/analogue_tb.vhd
-- Project Name: analogue
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: analogue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY analogue_tb IS
END analogue_tb;
ARCHITECTURE behavior OF analogue_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT analogue
PORT(
clk50 : IN std_logic;
sw : IN std_logic_vector(3 downto 0);
leds : OUT std_logic_vector(7 downto 0);
ad_dout : IN std_logic;
ad_din : OUT std_logic;
ad_cs : OUT std_logic;
ad_sclk : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk50 : std_logic := '0';
signal sw : std_logic_vector(3 downto 0) := (others => '0');
signal ad_dout : std_logic := '1';
--Outputs
signal leds : std_logic_vector(7 downto 0);
signal ad_din : std_logic;
signal ad_cs : std_logic;
signal ad_sclk : std_logic;
-- Clock period definitions
constant clk50_period : time := 10 ns;
constant ad_sclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: analogue PORT MAP (
clk50 => clk50,
sw => sw,
leds => leds,
ad_dout => ad_dout,
ad_din => ad_din,
ad_cs => ad_cs,
ad_sclk => ad_sclk
);
-- Clock process definitions
clk50_process :process
begin
clk50 <= '0';
wait for clk50_period/2;
clk50 <= '1';
wait for clk50_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk50_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1118.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01118ent IS
END c06s05b00x00p03n01i01118ent;
ARCHITECTURE c06s05b00x00p03n01i01118arch OF c06s05b00x00p03n01i01118ent IS
type idx is range 1 to 10;
type aray1 is array (idx) of bit;
type aray2 is array (idx range <>) of aray1;
BEGIN
TESTING: PROCESS
variable v1 : aray1; -- default is all '0'
BEGIN
--
-- Try slices of aggregates
--
v1 := "1111111111";
v1 := aray1'(others => '0')(idx); -- slice is the whole aggr
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01118 - Slice of an aggregate as a value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01118arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1118.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01118ent IS
END c06s05b00x00p03n01i01118ent;
ARCHITECTURE c06s05b00x00p03n01i01118arch OF c06s05b00x00p03n01i01118ent IS
type idx is range 1 to 10;
type aray1 is array (idx) of bit;
type aray2 is array (idx range <>) of aray1;
BEGIN
TESTING: PROCESS
variable v1 : aray1; -- default is all '0'
BEGIN
--
-- Try slices of aggregates
--
v1 := "1111111111";
v1 := aray1'(others => '0')(idx); -- slice is the whole aggr
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01118 - Slice of an aggregate as a value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01118arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1118.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p03n01i01118ent IS
END c06s05b00x00p03n01i01118ent;
ARCHITECTURE c06s05b00x00p03n01i01118arch OF c06s05b00x00p03n01i01118ent IS
type idx is range 1 to 10;
type aray1 is array (idx) of bit;
type aray2 is array (idx range <>) of aray1;
BEGIN
TESTING: PROCESS
variable v1 : aray1; -- default is all '0'
BEGIN
--
-- Try slices of aggregates
--
v1 := "1111111111";
v1 := aray1'(others => '0')(idx); -- slice is the whole aggr
assert FALSE
report "***FAILED TEST: c06s05b00x00p03n01i01118 - Slice of an aggregate as a value failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p03n01i01118arch;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_noqueue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 6/16/10 v4_03
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32
-- Master AXI Stream Data Width
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel Control --
desc_flush : in std_logic ; --
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
-- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active = '1')then
curdesc_tdata <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
curdesc_tvalid <= '1';
writing_lsb <= '1';
writing_msb <= '0';
-- On ready write MSB address
elsif(writing_lsb = '1' and ftch_tready = '1')then
curdesc_tdata <= msb_curdesc;
curdesc_tvalid <= '1';
writing_lsb <= '0';
writing_msb <= '1';
-- On MSB write and ready then clear all
elsif(writing_msb = '1' and ftch_tready = '1')then
curdesc_tdata <= (others => '0');
curdesc_tvalid <= '0';
writing_lsb <= '0';
writing_msb <= '0';
end if;
end if;
end process WRITE_CURDESC_PROCESS;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
TVALID_TDATA_MUX : process(writing_curdesc,
writing_nxtdesc,
ftch_active,
curdesc_tvalid,
curdesc_tdata,
m_axis_mm2s_tvalid,
m_axis_mm2s_tdata,
m_axis_mm2s_tlast)
begin
-- Select current descriptor to drive out (Queue or Channel Port)
if(writing_curdesc = '1')then
ftch_tvalid <= curdesc_tvalid;
ftch_tdata <= curdesc_tdata;
ftch_tlast <= '0';
-- Deassert tvalid when capturing next descriptor pointer
elsif(writing_nxtdesc = '1')then
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
-- Otherwise drive data from Datamover out (Queue or Channel Port)
elsif(ftch_active = '1')then
ftch_tvalid <= m_axis_mm2s_tvalid;
ftch_tdata <= m_axis_mm2s_tdata;
ftch_tlast <= m_axis_mm2s_tlast;
else
ftch_tvalid <= '0';
ftch_tdata <= (others => '0');
ftch_tlast <= '0';
end if;
end process TVALID_TDATA_MUX;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
m_axis_ftch_tdata <= ftch_tdata;
m_axis_ftch_tlast <= ftch_tlast;
m_axis_ftch_tvalid <= ftch_tvalid;
ftch_tready <= m_axis_ftch_tready;
m_axis_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_971;
architecture augh of cmp_971 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_971 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_971;
architecture augh of cmp_971 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal notA : std_logic;
signal notB : std_logic;
signal notC : std_logic;
signal notD : std_logic;
begin
G0 : NOR3
port map
(
I1 => notA,
I2 => notB,
I3 => D,
O => s1
);
G1 : OR3
port map
(
I1 => B,
I2 => notC,
I3 => notD,
O => s2
);
G2 : NAND2
port map
(
I1 => A,
I2 => notD,
O => s3
);
G3 : AND2
port map
(
I1 => A,
I2 => notD,
O => s4
);
G4 : NOR4
port map
(
I1=>s1,
I2=>s2,
I3=>s3,
I4=>s4,
O=> s5
);
O <= s5;
notA <= not A;
notB <= not B;
notC <= not C;
notD <= not D;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;
signal s4 : std_logic;
signal s5 : std_logic;
signal notA : std_logic;
signal notB : std_logic;
signal notC : std_logic;
signal notD : std_logic;
begin
G0 : NOR3
port map
(
I1 => notA,
I2 => notB,
I3 => D,
O => s1
);
G1 : OR3
port map
(
I1 => B,
I2 => notC,
I3 => notD,
O => s2
);
G2 : NAND2
port map
(
I1 => A,
I2 => notD,
O => s3
);
G3 : AND2
port map
(
I1 => A,
I2 => notD,
O => s4
);
G4 : NOR4
port map
(
I1=>s1,
I2=>s2,
I3=>s3,
I4=>s4,
O=> s5
);
O <= s5;
notA <= not A;
notB <= not B;
notC <= not C;
notD <= not D;
end behavior;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- mi_pipe_arch.vhd: MI Pipe - wrapper to generic pipe
-- Copyright (C) 2010 CESNET
-- Author(s): Vaclav Bartos <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_pipe_arch.vhd 14019 2010-06-11 12:51:48Z washek $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-- ----------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION --
-- ----------------------------------------------------------------------------
architecture mi_pipe_arch of MI_PIPE is
signal in_data : std_logic_vector(DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 1 downto 0);
signal out_data : std_logic_vector(DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 1 downto 0);
signal in_req : std_logic;
signal in_dst_rdy : std_logic;
signal out_src_rdy : std_logic;
signal out_dst_rdy : std_logic;
signal OUT_RD_aux : std_logic;
signal OUT_WR_aux : std_logic;
begin
in_data <= IN_WR & IN_RD & IN_BE & IN_ADDR & IN_DWR;
OUT_DWR <= out_data(DATA_WIDTH-1 downto 0);
OUT_ADDR <= out_data(DATA_WIDTH+ADDR_WIDTH-1 downto DATA_WIDTH);
OUT_BE <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8-1 downto DATA_WIDTH+ADDR_WIDTH);
OUT_RD_aux <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8) and out_src_rdy;
OUT_WR_aux <= out_data(DATA_WIDTH+ADDR_WIDTH+DATA_WIDTH/8+1) and out_src_rdy;
OUT_RD <= OUT_RD_aux;
OUT_WR <= OUT_WR_aux;
in_req <= IN_RD or IN_WR;
out_dst_rdy <= ((not (OUT_RD_aux or OUT_WR_aux)) or OUT_ARDY);
PIPE: entity work.PIPE
generic map(
DATA_WIDTH => DATA_WIDTH + ADDR_WIDTH + DATA_WIDTH/8 + 2,
USE_OUTREG => USE_OUTREG,
FAKE_PIPE => FAKE_PIPE
)
port map(
CLK => CLK,
RESET => RESET,
IN_DATA => in_data,
IN_SRC_RDY => in_req,
IN_DST_RDY => in_dst_rdy,
OUT_DATA => out_data,
OUT_SRC_RDY => out_src_rdy,
OUT_DST_RDY => out_dst_rdy
);
IN_ARDY <= in_dst_rdy and in_req;
NOT_FAKE: if (FAKE_PIPE = false) generate
in_drdp: process(CLK)
begin
if (CLK'event and CLK = '1') then
IN_DRD <= OUT_DRD;
end if;
end process;
in_drdyp: process(RESET, CLK)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then
IN_DRDY <= '0';
else
IN_DRDY <= OUT_DRDY;
end if;
end if;
end process;
end generate;
FAKE: if (FAKE_PIPE = true) generate
IN_DRD <= OUT_DRD;
IN_DRDY <= OUT_DRDY;
end generate;
end mi_pipe_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- dummy entity
entity ent is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ent;
architecture beh of ent is
signal result : std_logic_vector(n downto 0);
begin
fooProc : process is
variable baz : natural := 4711;
begin
-- without else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
end if;
-- with else
if (3 = 3) then
baz := 3;
elsif (4 = 4) then
baz := 4;
elsif (5 = 5) then
baz := 5;
elsif (6 = 6) then
baz := 6;
else
baz := 100000;
end if;
end process fooProc;
end beh;
|
component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
xck_clk : out std_logic -- clk
);
end component Platform;
u0 : component Platform
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hex0_2_export => CONNECTED_TO_hex0_2_export, -- hex0_2.export
hex3_5_export => CONNECTED_TO_hex3_5_export, -- hex3_5.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
i2c_SDAT => CONNECTED_TO_i2c_SDAT, -- i2c.SDAT
i2c_SCLK => CONNECTED_TO_i2c_SCLK, -- .SCLK
keys_export => CONNECTED_TO_keys_export, -- keys.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
switches_export => CONNECTED_TO_switches_export, -- switches.export
xck_clk => CONNECTED_TO_xck_clk -- xck.clk
);
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
-- number of bits in the RAMB16_S18
constant ramb16_size : integer := 16384;
-- determine shape of memory
constant block_size : integer := ramb16_size / WIDTH;
constant block_bits : integer := f_log2(block_size);
constant num_blocks : integer := (SIZE + block_size - 1) / block_size;
type RAMBlDOut_Type is array(0 to num_blocks - 1) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
begin
RAM_Inst:for i in 0 to num_blocks - 1 generate
Ram : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map(
DO => RAMBlDOut(i),
ADDR => address(block_bits - 1 downto 0),
DI => din,
DIP => "11",
EN => ce,
SSR => '0',
CLK => cp2,
WE => '0'
);
end generate;
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto block_bits)));
end RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
-- number of bits in the RAMB16_S18
constant ramb16_size : integer := 16384;
-- determine shape of memory
constant block_size : integer := ramb16_size / WIDTH;
constant block_bits : integer := f_log2(block_size);
constant num_blocks : integer := (SIZE + block_size - 1) / block_size;
type RAMBlDOut_Type is array(0 to num_blocks - 1) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
begin
RAM_Inst:for i in 0 to num_blocks - 1 generate
Ram : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map(
DO => RAMBlDOut(i),
ADDR => address(block_bits - 1 downto 0),
DI => din,
DIP => "11",
EN => ce,
SSR => '0',
CLK => cp2,
WE => '0'
);
end generate;
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto block_bits)));
end RTL;
|
entity main is
end entity main ;
architecture arch of main is
-- type t is range -1 to 10;
-- type t is integer;
signal s1 : integer;
signal s2 : integer;
signal s : integer;
begin
s <= s1 + s2;
main: process(s)
begin
report integer'image(s);
end process;
end;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : ila_icon.vhd
-- /___/ /\ Timestamp : Mon Jan 20 14:27:06 CET 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ila_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END ila_icon;
ARCHITECTURE ila_icon_a OF ila_icon IS
BEGIN
END ila_icon_a;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : ila_icon.vhd
-- /___/ /\ Timestamp : Mon Jan 20 14:27:06 CET 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ila_icon IS
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END ila_icon;
ARCHITECTURE ila_icon_a OF ila_icon IS
BEGIN
END ila_icon_a;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
-- synthesis translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use std.textio.all;
--library work;
--use work.AESL_components.all;
package AESL_sim_components is
-- simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER);
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING);
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING);
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING);
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN);
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING;
function esl_conv_lv (str : string; base : integer; len : integer) return STD_LOGIC_VECTOR;
end package;
package body AESL_sim_components is
--simulation routines
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING;
token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
procedure esl_assign_lv (signal LHS : out STD_LOGIC_VECTOR;
variable RHS : in STRING) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
for i in 1 to bitwidth loop
if RHS(i) = '1' then
LHS(bitwidth - i) <= '1';
elsif RHS(i) = '0' then
LHS(bitwidth - i) <= '0';
else
LHS(bitwidth - i) <= 'X';
end if;
end loop;
end procedure;
procedure esl_assign_l (signal LHS : out STD_LOGIC;
variable RHS : in STRING) is
begin
if RHS(1) = '1' then
LHS <= '1';
elsif RHS(1) = '0' then
LHS <= '0';
else
LHS <= 'X';
end if;
end procedure;
procedure esl_compare_l (signal LHS: in STD_LOGIC;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
begin
if dontcare then
isok := true;
elsif RHS(1) = '1' then
if LHS = '1' then
isok := true;
else
isok := false;
end if;
elsif RHS(1) = '0' then
if LHS = '0' then
isok := true;
else
isok := false;
end if;
else
isok := true;
end if;
end procedure;
procedure esl_compare_lv (signal LHS: in STD_LOGIC_VECTOR;
variable RHS: in STRING;
variable dontcare: in BOOLEAN;
variable isok: out BOOLEAN) is
variable i : INTEGER;
variable bitwidth : INTEGER;
begin
bitwidth := LHS'length;
if dontcare then
isok := true;
else
isok := true;
loop_compare: for i in 1 to bitwidth loop
if RHS(i) = '1' then
if LHS(bitwidth - i) /= '1' then
isok := false;
exit loop_compare;
end if;
elsif RHS(i) = '0' then
if LHS(bitwidth - i) /= '0' then
isok := false;
exit loop_compare;
end if;
end if;
end loop;
end if;
end procedure;
function esl_conv_string (lv : STD_LOGIC_VECTOR) return STRING is
variable ret : STRING (1 to lv'length);
variable i: INTEGER;
begin
for i in 1 to lv'length loop
if lv(lv'length - i) = '1' then
ret(i) := '1';
elsif lv(lv'length - i) = '0' then
ret(i) := '0';
else
ret(i) := 'X';
end if;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant LEN : integer := (lv'length + 3)/4;
variable ret : STRING (1 to LEN);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(LEN * 4 - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := (others => '0');
normal_lv(lv'length - 1 downto 0) := lv;
for i in 0 to LEN - 1 loop
tmp_lv := normal_lv(LEN * 4 - 1 - i * 4 downto LEN * 4 - 4 - i * 4);
case tmp_lv is
when "0000" => ret(i + 1) := '0';
when "0001" => ret(i + 1) := '1';
when "0010" => ret(i + 1) := '2';
when "0011" => ret(i + 1) := '3';
when "0100" => ret(i + 1) := '4';
when "0101" => ret(i + 1) := '5';
when "0110" => ret(i + 1) := '6';
when "0111" => ret(i + 1) := '7';
when "1000" => ret(i + 1) := '8';
when "1001" => ret(i + 1) := '9';
when "1010" => ret(i + 1) := 'a';
when "1011" => ret(i + 1) := 'b';
when "1100" => ret(i + 1) := 'c';
when "1101" => ret(i + 1) := 'd';
when "1110" => ret(i + 1) := 'e';
when "1111" => ret(i + 1) := 'f';
when others => ret(i + 1) := '0';
end case;
end loop;
return ret;
end function;
function esl_conv_lv (str : STRING; base : integer; len : integer) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(len - 1 downto 0);
variable val : integer := 0;
variable pos : boolean := true;
variable i : integer;
begin
loop_main: for i in 1 to str'length loop
if str(i) = ' ' or str(i) = HT or str(i) = CR or str(i) = LF then
exit loop_main;
elsif str(i) = '-' then
pos := false;
else
case base is
when 10 =>
if '0' <= str(i) and str(i) <= '9' then
val := val*10 + character'pos(str(i)) - character'pos('0');
else
val := val*10;
end if;
when others =>
val := 0;
end case;
end if;
end loop;
if pos = false then
val := val * (-1);
end if;
ret := conv_std_logic_vector(val, len);
return ret;
end function;
end package body;
-- synthesis translate_on
-- 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity fifo_cc_got_tempgot_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_cc_got_tempgot_tb is
-- component generics
constant D_BITS : positive := 8;
constant MIN_DEPTH : positive := 8;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
constant ISPEC : string := "C C Cccccpppp pppp c ccc pp Cppppp ppp rp RpC";
constant OSPEC : string := "ggg gggggggg ggg G G";
-- Sequence Generator
constant GEN : bit_vector := "100110001";
constant ORG : std_logic_vector := "00000001";
-- Clock Control
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic_vector(0 to 7) := (others => '0');
begin
clk <= not clk after 5 ns when done /= (done'range => '1') else '0';
genTests: for c in 0 to 7 generate
constant DATA_REG : boolean := c mod 2 > 0;
constant STATE_REG : boolean := c mod 4 > 1;
constant OUTPUT_REG : boolean := c mod 8 > 3;
signal put : std_logic;
signal putx : std_logic;
signal di : std_logic_vector(D_BITS-1 downto 0);
signal ful : std_logic;
signal commit : std_logic;
signal rollback : std_logic;
signal got : std_logic;
signal gotx : std_logic;
signal do : std_logic_vector(D_BITS-1 downto 0);
signal dox : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
begin
putx <= put and not ful;
geni : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => putx,
mask => di
);
process
begin
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
for i in ISPEC'range loop
put <= '0';
commit <= '0';
rollback <= '0';
case ISPEC(i) is
when ' ' =>
wait until rising_edge(clk);
when 'p' =>
put <= '1';
wait until rising_edge(clk) and ful = '0';
when 'c' =>
commit <= '1';
wait until rising_edge(clk);
when 'C' =>
put <= '1';
commit <= '1';
wait until rising_edge(clk) and ful = '0';
when 'r' =>
rollback <= '1';
wait until rising_edge(clk);
when 'R' =>
put <= '1';
rollback <= '1';
wait until rising_edge(clk) and ful = '0';
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
put <= '0';
commit <= '0';
wait;
end process;
DUT : entity PoC.fifo_cc_got_tempgot
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
DATA_REG => DATA_REG,
STATE_REG => STATE_REG,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
rst => rst,
clk => clk,
put => put,
din => di,
full => ful,
estate_wr => open,
commit => commit,
rollback => rollback,
got => got,
dout => do,
valid => vld,
fstate_rd => open
);
process
begin
for i in OSPEC'range loop
case OSPEC(i) is
when ' ' =>
got <= '0';
wait until rising_edge(clk);
when 'g' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do = dox report "Test #"&integer'image(c)&": Output Mismatch." severity error;
when 'G' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do /= dox report "Output Mismatch." severity error;
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
done(c) <= '1';
report "Test #"&integer'image(c)&" completed." severity note;
wait;
end process;
gotx <= got and vld;
geno : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => gotx,
mask => dox
);
end generate;
end tb;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: Testbench for a FIFO with Common Clock (cc) and Pipelined Interface
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
entity fifo_cc_got_tempgot_tb is
end entity;
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
architecture tb of fifo_cc_got_tempgot_tb is
-- component generics
constant D_BITS : positive := 8;
constant MIN_DEPTH : positive := 8;
constant ESTATE_WR_BITS : natural := 2;
constant FSTATE_RD_BITS : natural := 2;
constant ISPEC : string := "C C Cccccpppp pppp c ccc pp Cppppp ppp rp RpC";
constant OSPEC : string := "ggg gggggggg ggg G G";
-- Sequence Generator
constant GEN : bit_vector := "100110001";
constant ORG : std_logic_vector := "00000001";
-- Clock Control
signal rst : std_logic;
signal clk : std_logic := '0';
signal done : std_logic_vector(0 to 7) := (others => '0');
begin
clk <= not clk after 5 ns when done /= (done'range => '1') else '0';
genTests: for c in 0 to 7 generate
constant DATA_REG : boolean := c mod 2 > 0;
constant STATE_REG : boolean := c mod 4 > 1;
constant OUTPUT_REG : boolean := c mod 8 > 3;
signal put : std_logic;
signal putx : std_logic;
signal di : std_logic_vector(D_BITS-1 downto 0);
signal ful : std_logic;
signal commit : std_logic;
signal rollback : std_logic;
signal got : std_logic;
signal gotx : std_logic;
signal do : std_logic_vector(D_BITS-1 downto 0);
signal dox : std_logic_vector(D_BITS-1 downto 0);
signal vld : std_logic;
begin
putx <= put and not ful;
geni : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => putx,
mask => di
);
process
begin
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
for i in ISPEC'range loop
put <= '0';
commit <= '0';
rollback <= '0';
case ISPEC(i) is
when ' ' =>
wait until rising_edge(clk);
when 'p' =>
put <= '1';
wait until rising_edge(clk) and ful = '0';
when 'c' =>
commit <= '1';
wait until rising_edge(clk);
when 'C' =>
put <= '1';
commit <= '1';
wait until rising_edge(clk) and ful = '0';
when 'r' =>
rollback <= '1';
wait until rising_edge(clk);
when 'R' =>
put <= '1';
rollback <= '1';
wait until rising_edge(clk) and ful = '0';
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
put <= '0';
commit <= '0';
wait;
end process;
DUT : entity PoC.fifo_cc_got_tempgot
generic map (
D_BITS => D_BITS,
MIN_DEPTH => MIN_DEPTH,
DATA_REG => DATA_REG,
STATE_REG => STATE_REG,
OUTPUT_REG => OUTPUT_REG,
ESTATE_WR_BITS => ESTATE_WR_BITS,
FSTATE_RD_BITS => FSTATE_RD_BITS
)
port map (
rst => rst,
clk => clk,
put => put,
din => di,
full => ful,
estate_wr => open,
commit => commit,
rollback => rollback,
got => got,
dout => do,
valid => vld,
fstate_rd => open
);
process
begin
for i in OSPEC'range loop
case OSPEC(i) is
when ' ' =>
got <= '0';
wait until rising_edge(clk);
when 'g' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do = dox report "Test #"&integer'image(c)&": Output Mismatch." severity error;
when 'G' =>
got <= '1';
wait until rising_edge(clk) and vld = '1';
assert do /= dox report "Output Mismatch." severity error;
when others =>
report "Illegal ISPEC." severity failure;
end case;
end loop;
done(c) <= '1';
report "Test #"&integer'image(c)&" completed." severity note;
wait;
end process;
gotx <= got and vld;
geno : entity PoC.comm_scramble
generic map (
GEN => GEN,
BITS => D_BITS
)
port map (
clk => clk,
set => rst,
din => ORG,
step => gotx,
mask => dox
);
end generate;
end tb;
|
-- This is valid
architecture RTL of ENTITY1 is
begin
end architecture RTL;
-- This is not valid
architecture ENTITY1 of entity1 is
begin
end architecture ENTITY1;
-- This is valid
architecture BLUE of ENTITY1 is
begin
end architecture BLUE;
-- This is not valid
architecture CDC of ENTITY1 is
begin
end architecture CDC;
|
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: FMD2030_5-06A-B.vhd
-- Creation Date: 22:26:31 18/04/05
-- Description:
-- ALU, A & B registers
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-13
-- Initial Release
--
--
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
library work;
use work.Gates_package.all;
use work.Buses_package.all;
use work.PH;
use work.FLL;
ENTITY ABALU IS
port
(
-- Inputs
LAMP_TEST : IN STD_LOGIC; -- 04A
SALS : IN SALS_Bus; -- 01C
MANUAL_STORE : IN STD_LOGIC; -- 03D
RECYCLE_RST : IN STD_LOGIC; -- 04A
S_REG_3 : IN STD_LOGIC; -- 07B
SERV_IN_SIG,STAT_IN_SIG,OPNL_IN,ADDR_IN : IN STD_LOGIC; -- 08D
T_REQUEST : IN STD_LOGIC; -- 10B
A_BUS, B_BUS : IN STD_LOGIC_VECTOR(0 to 8); -- 8 is P
MAN_STOR_OR_DSPLY : IN STD_LOGIC; -- 03D
MACH_RST_SET_LCH : IN STD_LOGIC; -- 04B
S_REG_0 : IN STD_LOGIC; -- 07B
CTRL : IN CTRL_REG; -- 01C
DIAG_SW : IN STD_LOGIC; -- 04A
S_REG_RST : IN STD_LOGIC; -- 07B
GT_Z_BUS_TO_S_REG : IN STD_LOGIC; -- 07B
ROS_SCAN : IN STD_LOGIC; -- 03C
GT_SWS_TO_WX_PWR : IN STD_LOGIC; -- 04A
RST_LOAD : IN STD_LOGIC; -- 03C
SYSTEM_RST_PRIORITY_LCH : IN STD_LOGIC; -- 03A
-- Outputs
IND_A,IND_B,IND_ALU : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
A_REG_PC,B_REG_PC : OUT STD_LOGIC; -- 11A,07A,13A
OPNL_IN_LCHD,STATUS_IN_LCHD,Z0_BUS_0,SERV_IN_LCHD,ADDR_IN_LCHD : OUT STD_LOGIC; -- 02A
CARRY_1_LCHD : OUT STD_LOGIC; -- 05A
CARRY_0_LATCHED : OUT STD_LOGIC; -- 01B,02A
CARRY_0 : OUT STD_LOGIC; -- 07B
ALU_CHK : OUT STD_LOGIC; -- 03C,01A,07A
NTRUE,COMPLEMENT : OUT STD_LOGIC; -- 03B
P_CONNECT : OUT STD_LOGIC; -- 02A
P_CTRL_N : OUT STD_LOGIC; -- 02A,03A
N_CTRL_N : OUT STD_LOGIC; -- 04A
N_CTRL_LM : OUT STD_LOGIC; -- 02A
P_Z_BUS,N_Z_BUS : OUT STD_LOGIC_VECTOR(0 to 8); -- 8 is P
Z_HI_0,Z_LO_0,Z_0,Z_BUS_LO_DIGIT_PARITY : OUT STD_LOGIC;
MACH_RST_2A,MACH_RST_2B,MACH_RST_2C : OUT STD_LOGIC;
ODD : OUT STD_LOGIC; -- 04A
ALU_CHK_LCH : OUT STD_LOGIC; -- 01B,08D
GT_CARRY_TO_S3 : OUT STD_LOGIC; -- 07B
INTRODUCE_ALU_CHK : OUT STD_LOGIC; -- 04A
DECIMAL : OUT STD_LOGIC; -- 02A
-- Debug
DBG_P_ALU_A_IN, DBG_P_ALU_B_IN, DBG_P_ALU_CARRY, DBG_P_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DBG_N_ALU_A_IN, DBG_N_ALU_B_IN, DBG_N_ALU_CARRY, DBG_N_ALU_SUMS : OUT STD_LOGIC_VECTOR(0 to 7);
DEBUG : OUT STD_LOGIC;
-- Clocks
T1,T2,T3,T4 : IN STD_LOGIC;
P1 : IN STD_LOGIC;
Clk : IN STD_LOGIC -- 50MHz
);
END ABALU;
ARCHITECTURE FMD OF ABALU IS
alias CC : STD_LOGIC_VECTOR(0 to 2) is CTRL.CTRL_CC;
alias CV : STD_LOGIC_VECTOR(0 to 1) is CTRL.CTRL_CV;
alias CROSSED : STD_LOGIC is CTRL.CROSSED;
alias STRAIGHT : STD_LOGIC is CTRL.STRAIGHT;
alias GT_A_LO : STD_LOGIC is CTRL.GT_A_REG_LO;
alias GT_A_HI : STD_LOGIC is CTRL.GT_A_REG_HI;
alias GT_B_REG_LO : STD_LOGIC is CTRL.GT_B_REG_LO;
alias GT_B_REG_HI : STD_LOGIC is CTRL.GT_B_REG_HI;
signal P_CARRY_IN_7,N_CARRY_IN_7 : STD_LOGIC;
signal P_Z_ALU_BUS,N_Z_ALU_BUS : STD_LOGIC_VECTOR(0 to 7);
signal A_REG,B_REG : STD_LOGIC_VECTOR(0 to 8); -- 8 is P
signal CARRY_S3,INSERT_CARRY,INSERT_0_CARRY : STD_LOGIC;
signal NOT_S3 : STD_LOGIC;
signal HEX,sDECIMAL : STD_LOGIC;
-- signal N_CONNECT : std_logic;
-- signal P_CTRL_LM : STD_LOGIC;
signal P_ALU_A_IN,N_ALU_A_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_ALU_B_IN,N_ALU_B_IN : STD_LOGIC_VECTOR(0 to 7);
signal P_SUMS,N_SUMS,P_CARRY,N_CARRY : STD_LOGIC_VECTOR(0 to 7);
signal HSEL,LSEL : STD_LOGIC_VECTOR(0 to 2);
signal sINTRODUCE_ALU_CHK : STD_LOGIC;
signal sODD,EVEN : STD_LOGIC;
signal DIAG_TEST_BIT : STD_LOGIC;
signal sNTRUE : STD_LOGIC;
signal sP_Z_BUS,sN_Z_BUS : STD_LOGIC_VECTOR(0 to 8);
signal sALU_CHK_LCH : STD_LOGIC;
signal sZ_HI_0, sZ_LO_0, sZ_0 : STD_LOGIC;
signal sMACH_RST_2, sMACH_RST_2A : STD_LOGIC;
signal sGT_CARRY_TO_S3 : STD_LOGIC;
signal SI_LCH_Set,STI_LCH_Set,Z0C1C0_LCH,PC7_LCH_Set,PC7_LCH_Reset,
NC7_LCH_Set,A_LCH_L,B_LCH_L,NS3_LCH_Set,NS3_LCH_Reset,EVEN_LCH_Set,EVEN_LCH_Reset,AC_LCH_Set,AC_LCH_Reset : STD_LOGIC;
signal sCARRY_0_LATCHED, sALU_CHK : STD_LOGIC; -- Debug
BEGIN
-- Fig 5-06A
-- A REGISTER, B REGISTER INDICATORS
IND_A <= "111111111" when LAMP_TEST='1' else A_REG;
IND_B <= "111111111" when LAMP_TEST='1' else B_REG;
A_REG_PC <= EvenParity(A_REG); -- AB2H2
B_REG_PC <= EvenParity(B_REG); -- AB2J2
-- IMMED STAT REG
SI_LCH_Set <= SERV_IN_SIG and not T_REQUEST;
SI_LCH: entity PH port map(SI_LCH_Set,T3,SERV_IN_LCHD); -- AB2D6
STI_LCH_Set <= STAT_IN_SIG and not T_REQUEST;
STI_LCH: entity PH port map(STI_LCH_Set,T3,STATUS_IN_LCHD); -- AB2D6
OI_LCH: entity PH port map(OPNL_IN,T3,OPNL_IN_LCHD); -- AB2D6
AI_LCH: entity PH port map(ADDR_IN,T3,ADDR_IN_LCHD); -- AB2D6
Z0C1C0_LCH <= T4 or RECYCLE_RST;
Z0_LCH: entity PH port map(sZ_0,Z0C1C0_LCH,Z0_BUS_0); -- AB2D6
C1_LCH: entity PH port map(P_CARRY(1),Z0C1C0_LCH,CARRY_1_LCHD); -- AB2D6
C0_LCH: entity PH port map(P_CARRY(0),Z0C1C0_LCH,sCARRY_0_LATCHED); -- AB2D6
CARRY_0_LATCHED <= sCARRY_0_LATCHED;
-- ALU INDICATORS
IND_ALU <= "111111111" when LAMP_TEST='1' else sP_Z_BUS;
-- CARRY IN LATCHES
CARRY_S3 <= '1' when CC="110" else '0'; -- AB2E7
INSERT_CARRY <= '1' when (CC="001") or (CC="101") else '0'; -- AB2E6
INSERT_0_CARRY <= '1' when (CC="000") or (CC="010") or (CC="011") or (CC="100") or (CC="111") else '0'; -- AB2E7
PC7_LCH_Set <= (S_REG_3 and CARRY_S3 and P1) or (P1 and INSERT_CARRY);
PC7_LCH_Reset <= MANUAL_STORE or T1 or RECYCLE_RST;
PC7_LCH: entity FLL port map(PC7_LCH_Set,PC7_LCH_Reset,P_CARRY_IN_7); -- AB2F3,AB2E4
NC7_LCH_Set <= (NOT_S3 and CARRY_S3 and P1) or (P1 and INSERT_0_CARRY) or RECYCLE_RST or MANUAL_STORE;
NC7_LCH: entity FLL port map(NC7_LCH_Set,T1,N_CARRY_IN_7); -- AB2F3,AB2E4
-- ALU CHECK
sALU_CHK <= '1' when (P_Z_ALU_BUS xor N_Z_ALU_BUS)/="11111111" or (P_SUMS(0) = N_SUMS(0)) or (P_SUMS(4) = N_SUMS(4)) or (P_CARRY(0) = N_CARRY(0)) else '0'; -- AB2D3,AB2D4,AB2E4
ALU_CHK <= sALU_CHK;
-- Fig 5-06B
-- A REG and B REG
A_LCH_L <= MAN_STOR_OR_DSPLY or MACH_RST_SET_LCH or T1;
A_LCH: PHV9 port map(not A_BUS,A_LCH_L,A_REG); -- AB1J5,AB1K7
B_LCH_L <= MACH_RST_SET_LCH or T1 or MANUAL_STORE;
B_LCH: PHV9 port map(B_BUS,B_LCH_L,B_REG); -- AB1J5,AB1L5
-- ALU B entry
sNTRUE <= '1' when (CV(0)='1' and S_REG_0='0') or CV="00" else '0'; -- AB2K7
NTRUE <= sNTRUE;
COMPLEMENT <= '1' when (CV(0)='1' and S_REG_0='1') or CV="01" else '0'; -- AB2L7
HEX <= '1' when CV(0)='0' or CV(1)='0' else '0'; -- AB2J7
sDECIMAL <= '1' when CV="11" else '0'; -- AB2H7
DECIMAL <= sDECIMAL;
HSEL <= GT_B_REG_HI & sDECIMAL & sNTRUE;
with HSEL select P_ALU_B_IN(0 to 3) <=
B_REG(0 to 3) + "0110" when "111", -- Spec A1
B_REG(0 to 3) when "101", -- Spec A2
not B_REG(0 to 3) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
LSEL <= GT_B_REG_LO & sDECIMAL & sNTRUE;
with LSEL select P_ALU_B_IN(4 to 7) <=
B_REG(4 to 7) + "0110" when "111", -- Spec A1
B_REG(4 to 7) when "101", -- Spec A2
not B_REG(4 to 7) when "100"|"110", -- Spec A3
"0110" when "011", -- Spec A4 ???
"1111" when "000"|"010", -- Spec A5
"0000" when others
;
N_ALU_B_IN <= not P_ALU_B_IN;
-- ALU A entry
P_ALU_A_IN(0 to 3) <=
((0 to 3 => not CROSSED) or A_REG(4 to 7)) and
((0 to 3 => not STRAIGHT) or A_REG(0 to 3)) and
(0 to 3 => GT_A_HI);
P_ALU_A_IN(4 to 7) <=
((4 to 7 => not CROSSED) or A_REG(0 to 3)) and
((4 to 7 => not STRAIGHT) or A_REG(4 to 7)) and
(4 to 7 => GT_A_LO);
N_ALU_A_IN(0 to 3) <=
not(((0 to 3 => GT_A_HI and STRAIGHT) and A_REG(0 to 3)) or
((0 to 3 => GT_A_HI and CROSSED) and A_REG(4 to 7))); -- ?? GT_A_HI is missing in MDM
N_ALU_A_IN(4 to 7) <=
not(((4 to 7 => GT_A_LO and STRAIGHT) and A_REG(4 to 7)) or
((4 to 7 => GT_A_LO and CROSSED) and A_REG(0 to 3)));
-- ALU
P_CONNECT <= '1' when (CC(0)='0' and CC(1)='1') or (CC(1)='1' and CC(2)='1') else '0'; -- AB2D7,AB2F7 CC=01X or CC=X11 i.e. 010 011 111
-- N_CONNECT <= '1' when (CC(0)/='0' or CC(1)/='1') and (CC(1)/='1' or CC(2)/='1') else '0'; -- AB2G7 i.e. 000 001 100 101 110www.typeupsidedown.
P_CTRL_N <= '1' when CC(1)='0' or CC(0)='1' else '0'; -- AB2D7,AB2F7 CC=X0X or 1XX ie. 000 001 100 101 110 111
N_CTRL_N <= '1' when CC(0)/='1' and CC(1)/='0' else '0'; -- AB2G7 CC=1XX nor CC=X0X ==> CC\=1XX and CC\=X0X i.e. 010 or 011
N_CTRL_LM <= '1' when CC/="010" else '0'; -- AB2G7
-- P_CTRL_LM <= '1' when CC="010" else '0'; -- AB2H7
-- CC functions
-- 000 Add, Carry in 0, Ignore Carry out
-- 001 Add, Carry in 1, Ignore Carry out
-- 010 And, Ignore Carry out
-- 011 Or, Ignore Carry out
-- 100 Add, Carry in 0, Set S3 to 1 on Carry out
-- 101 Add, Carry in 1, Set S3 to 1 on Carry out
-- 110 Add, Carry in from S3, Set S3 to 1 on Carry out
-- 111 Xor, Ignore Carry out
-- ALU P
with CC select P_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
P_ALU_A_IN and P_ALU_B_IN when "010",
P_ALU_A_IN or P_ALU_B_IN when "011",
P_ALU_A_IN xor P_ALU_B_IN when "111",
P_ALU_A_IN xor P_ALU_B_IN xor P_CARRY(1 to 7) & P_CARRY_IN_7 when others;
with CC select P_CARRY <=
"00000000" when "010"|"011"|"111",
(P_ALU_A_IN and P_ALU_B_IN) or
(P_ALU_A_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) or
(P_ALU_B_IN and P_CARRY(1 to 7) & P_CARRY_IN_7) when others; -- Ripple carry
CARRY_0 <= P_CARRY(0);
sINTRODUCE_ALU_CHK <= DIAG_SW and sALU_CHK_LCH; -- AE3H5,AB3F6,AB3F7
INTRODUCE_ALU_CHK <= sINTRODUCE_ALU_CHK;
-- ALU N
with CC select N_SUMS <= -- AB2J6,AB2H6,AB2G6,AB2F6,AB2J5,AB2H5,AB2G5,AB2F5
(N_ALU_A_IN or N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "010",
(N_ALU_A_IN and N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "011",
(N_ALU_A_IN xnor N_ALU_B_IN) or (0 to 7 => sINTRODUCE_ALU_CHK) when "111",
(N_ALU_A_IN xor N_ALU_B_IN xor N_CARRY(1 to 7) & N_CARRY_IN_7) or (0 to 7 => sINTRODUCE_ALU_CHK) when others;
with CC select N_CARRY <=
"11111111" and (0 to 7 => not sINTRODUCE_ALU_CHK) when "010"|"011"|"111",
((N_ALU_A_IN and N_ALU_B_IN) or
(N_ALU_A_IN and N_CARRY(1 to 7) & N_CARRY_IN_7) or
(N_ALU_B_IN and N_CARRY(1 to 7) & N_CARRY_IN_7)) and (0 to 7 => not sINTRODUCE_ALU_CHK) when others;
-- Debug
DBG_P_ALU_A_IN <= P_ALU_A_IN;
DBG_P_ALU_B_IN <= P_ALU_B_IN;
DBG_P_ALU_CARRY <= P_CARRY;
DBG_P_ALU_SUMS <= P_SUMS;
DBG_N_ALU_A_IN <= N_ALU_A_IN;
DBG_N_ALU_B_IN <= N_ALU_B_IN;
DBG_N_ALU_CARRY <= N_CARRY;
DBG_N_ALU_SUMS <= N_SUMS;
sGT_CARRY_TO_S3 <= '1' when CC="100" or CC="101" or CC="110" else '0'; -- AB2E6
GT_CARRY_TO_S3 <= sGT_CARRY_TO_S3;
-- Debug
NOT_S3 <= not S_REG_3;
-- NS3_LCH_Set <= (N_CARRY(0) and T4 and sGT_CARRY_TO_S3) or S_REG_RST;
-- NS3_LCH_Reset <= (sGT_CARRY_TO_S3 and T4 and P_CARRY(0)) or (GT_Z_BUS_TO_S_REG and sP_Z_BUS(3));
-- NS3_LCH: FLE port map(NS3_LCH_Set,NS3_LCH_Reset,clk,NOT_S3); -- AB2E3
-- Temp Debug
P_Z_ALU_BUS(0 to 3) <= ((0 => sODD and HEX, 1 to 3 => HEX) and P_SUMS(0 to 3)) or
((0 to 3 => P_CARRY(0) and sDECIMAL) and P_SUMS(0 to 3)) or
((0 to 3 => N_CARRY(0) and sDECIMAL) and (P_SUMS(0 to 3) - "0110"));
N_Z_ALU_BUS(0 to 3) <= ((0 to 3 => HEX) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and P_CARRY(0)) and N_SUMS(0 to 3)) or
((0 to 3 => sDECIMAL and N_CARRY(0)) and (N_SUMS(0 to 3) + "0110"));
P_Z_ALU_BUS(4 to 7) <= ((4 => sODD and HEX, 5 to 7 => HEX) and P_SUMS(4 to 7)) or
((4 to 7 => P_CARRY(4) and sDECIMAL) and P_SUMS(4 to 7)) or
((4 to 7 => N_CARRY(4) and sDECIMAL) and (P_SUMS(4 to 7) - "0110"));
N_Z_ALU_BUS(4 to 7) <= ((4 to 7 => HEX) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and P_CARRY(4)) and N_SUMS(4 to 7)) or
((4 to 7 => sDECIMAL and N_CARRY(4)) and (N_SUMS(4 to 7) + "0110"));
sP_Z_BUS <= P_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN); -- AB3C4
-- Note N_Z parity is not inverted, so is the same as P_Z
-- This may force a parity error when INTRODUCE_ALU_CHK is active,
-- depending on the value of P_Z. This parity error into R is required
-- for Diag B73 to work
sN_Z_BUS <= N_Z_ALU_BUS & EvenParity(P_Z_ALU_BUS & EVEN);
P_Z_BUS <= sP_Z_BUS;
N_Z_BUS <= sN_Z_BUS;
Z_BUS_LO_DIGIT_PARITY <= EvenParity(P_Z_ALU_BUS(4 to 7)); -- AB3C4
sZ_HI_0 <= '1' when sP_Z_BUS(0 to 3)="0000" else '0'; -- AB2E5
Z_HI_0 <= sZ_HI_0;
sZ_LO_0 <= '1' when sP_Z_BUS(4 to 7)="0000" else '0'; -- AB2E5
Z_LO_0 <= sZ_LO_0;
sZ_0 <= sZ_HI_0 and sZ_LO_0; -- AB2D5
Z_0 <= sZ_0;
sMACH_RST_2 <= sZ_0 and RECYCLE_RST; -- AB3C5
MACH_RST_2A_DELAY: AR port map(D=>sMACH_RST_2,Clk=>Clk,Q=>sMACH_RST_2A);
MACH_RST_2A <= sMACH_RST_2A;
MACH_RST_2B <= sMACH_RST_2A;
MACH_RST_2C <= sMACH_RST_2A;
DIAG_TEST_BIT <= '1' when SALS.SALS_CK="1000" and SALS.SALS_AK='1' else '0'; -- AB3E7
EVEN_LCH_Set <= T2 and DIAG_TEST_BIT and not sALU_CHK_LCH;
EVEN_LCH_Reset <= (T2 and sALU_CHK_LCH) or RST_LOAD or SYSTEM_RST_PRIORITY_LCH or RECYCLE_RST; -- ?? *not* SYSTEM_RST_PRIORITY_LCH ??
EVEN_LCH: entity FLL port map(EVEN_LCH_Set,EVEN_LCH_Reset,EVEN); -- AB3E5,AB3G2
sODD <= not EVEN;
ODD <= sODD;
AC_LCH_Set <= EVEN and DIAG_TEST_BIT and T1;
AC_LCH_Reset <= RECYCLE_RST or RST_LOAD or (ROS_SCAN and GT_SWS_TO_WX_PWR);
AC_LCH: entity FLL port map(AC_LCH_Set,AC_LCH_Reset,sALU_CHK_LCH); -- AG3G7,AB3G2
ALU_CHK_LCH <= sALU_CHK_LCH;
-- Debug
DEBUG <= '1' when NC7_LCH_Set='1' else '0';
END FMD;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNH6PQLQQ2 is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0000000000110010";
width : positive := 16);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNH6PQLQQ2 is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 16,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0000000000110010")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- $Id: snespad_ctrl.vhd,v 1.3 2005-09-15 17:28:17 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/gamepads/
--
-- The project homepage is located at:
-- http://www.opencores.org/projects.cgi/web/gamepads/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity snespad_ctrl is
generic (
reset_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
clk_en_o : out boolean;
-- Control Interface ------------------------------------------------------
shift_buttons_o : out boolean;
save_buttons_o : out boolean;
-- Pad Interface ----------------------------------------------------------
pad_clk_o : out std_logic;
pad_latch_o : out std_logic
);
end snespad_ctrl;
use work.snespad_pack.all;
architecture rtl of snespad_ctrl is
subtype clocks_per_6us_t is natural range 0 to clocks_per_6us_g;
type state_t is (IDLE,
IDLE2,
LATCH,
READ_PAD);
signal pad_latch_q,
pad_latch_s : std_logic;
signal pad_clk_q,
pad_clk_s : std_logic;
signal num_buttons_read_q : num_buttons_read_t;
signal clocks_per_6us_q : clocks_per_6us_t;
signal state_q,
state_s : state_t;
signal clk_en_s : boolean;
signal shift_buttons_s : boolean;
begin
-- pragma translate_off
-----------------------------------------------------------------------------
-- Check generics
-----------------------------------------------------------------------------
assert (reset_level_g = 0) or (reset_level_g = 1)
report "reset_level_g must be either 0 or 1!"
severity failure;
assert clocks_per_6us_g > 1
report "clocks_per_6us_g must be at least 2!"
severity failure;
-- pragma translate_on
seq: process (reset_i, clk_i)
begin
if reset_i = reset_level_g then
pad_latch_q <= '1';
pad_clk_q <= '1';
num_buttons_read_q <= num_buttons_c-1;
clocks_per_6us_q <= 0;
state_q <= IDLE;
elsif clk_i'event and clk_i = '1' then
if clk_en_s then
clocks_per_6us_q <= 0;
else
clocks_per_6us_q <= clocks_per_6us_q + 1;
end if;
if clk_en_s and shift_buttons_s then
if num_buttons_read_q = 0 then
num_buttons_read_q <= num_buttons_c-1;
else
num_buttons_read_q <= num_buttons_read_q - 1;
end if;
end if;
if clk_en_s then
state_q <= state_s;
end if;
pad_clk_q <= pad_clk_s;
pad_latch_q <= pad_latch_s;
end if;
end process;
clk_en_s <= clocks_per_6us_q = clocks_per_6us_g-1;
fsm: process (state_q,
num_buttons_read_q)
begin
-- default assignments
pad_clk_s <= '1';
pad_latch_s <= '1';
shift_buttons_s <= false;
save_buttons_o <= false;
state_s <= IDLE;
case state_q is
when IDLE =>
save_buttons_o <= true;
state_s <= IDLE2;
when IDLE2 =>
state_s <= LATCH;
when LATCH =>
pad_latch_s <= '0';
state_s <= READ_PAD;
when READ_PAD =>
pad_latch_s <= '0';
-- set clock low
-- pad data will be read at end of 6us cycle
pad_clk_s <= '0';
shift_buttons_s <= true;
if num_buttons_read_q = 0 then
-- return to IDLE after last button bit has been read
state_s <= IDLE;
else
state_s <= LATCH;
end if;
when others =>
null;
end case;
end process fsm;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
clk_en_o <= clk_en_s;
shift_buttons_o <= shift_buttons_s;
pad_clk_o <= pad_clk_q;
pad_latch_o <= pad_latch_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2005/07/03 21:36:00 arniml
-- removed obsolete state CLOCK
--
-- Revision 1.1 2004/10/05 17:01:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:27 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_0;
architecture stub of zqynq_lab_1_design_axi_bram_ctrl_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_bram_ctrl,Vivado 2017.2";
begin
end;
|
entity ieee7 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.fixed_pkg.all;
architecture test of ieee7 is
begin
main: process is
variable x, y, z : ufixed(7 downto -3) := (others => '0');
begin
z := to_ufixed(0, 7, -3);
assert x + y = z;
x := to_ufixed(5, 7, -3);
y := to_ufixed(6, 7, -3);
z := to_ufixed(11, 7, -3);
assert x + y = z;
assert to_string(z) = "00001011.000" report to_string(z);
x := to_ufixed(7, 7, -3);
y := to_ufixed(2, 7, -3);
z := to_ufixed(3.5, 7, -3);
assert x / y = z;
assert to_string(z) = "00000011.100" report to_string(z);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port (
a, b : in std_logic_vector(31 downto 0);
control : in std_logic_vector(2 downto 0);
output : out std_logic_vector(31 downto 0);
zero : out std_logic);
end alu;
architecture behave of alu is
begin
end behave;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for concatenation of function call results.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity concat_func is
port(in_word : in std_logic_vector(7 downto 0);
out_word : out std_logic_vector(7 downto 0));
end entity concat_func;
architecture test of concat_func is
begin
process(in_word)
variable tmp : unsigned(7 downto 0);
variable int : integer;
begin
tmp := unsigned(in_word);
int := to_integer(tmp);
out_word <= in_word(7 downto 6) & std_logic_vector(to_unsigned(int, 3)) & std_logic_vector(resize(tmp, 3));
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for concatenation of function call results.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity concat_func is
port(in_word : in std_logic_vector(7 downto 0);
out_word : out std_logic_vector(7 downto 0));
end entity concat_func;
architecture test of concat_func is
begin
process(in_word)
variable tmp : unsigned(7 downto 0);
variable int : integer;
begin
tmp := unsigned(in_word);
int := to_integer(tmp);
out_word <= in_word(7 downto 6) & std_logic_vector(to_unsigned(int, 3)) & std_logic_vector(resize(tmp, 3));
end process;
end architecture test;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 3;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 0;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library nvc;
use nvc.sim_pkg.ieee_warnings;
package body NUMERIC_BIT is
-- null range array constants
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := not ieee_warnings;
-- =========================Local Subprograms =================================
function MAXIMUM (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAXIMUM;
function MINIMUM (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MINIMUM;
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNSIGNED; C : BIT) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNSIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : SIGNED; C : BIT) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(L_LEFT downto 0) is R;
variable RESULT : SIGNED(L_LEFT downto 0);
variable CBIT : BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNSIGNED; XQUOT, XREMAIN : out UNSIGNED) is
variable TEMP : UNSIGNED(NUM'length downto 0);
variable QUOT : UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0);
alias DENOM : UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_BIT.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_BIT.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
---------------- Local Subprograms - Relational Operators --------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : SIGNED(0 to L'length-1);
variable INTERN_R : SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- ====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT : SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : SIGNED) return SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : SIGNED(ARG_LEFT downto 0);
variable CBIT : BIT := '1';
begin
if ARG'length < 1 then return NAS;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.4
function "+" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end function "+";
-- Id: A.5
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.10
function "-" (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end function "-";
-- Id: A.11
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNSIGNED) return UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
variable RESULT : UNSIGNED((L'length+R'length-1) downto 0) := (others => '0');
variable ADVAL : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : SIGNED) return SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : SIGNED(L_LEFT downto 0);
variable XR : SIGNED(R_LEFT downto 0);
variable RESULT : SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL : SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : SIGNED; R : INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
QNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
RNEG := true;
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNSIGNED) return UNSIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : SIGNED) return SIGNED is
variable FQUOT : UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNSIGNED(R'length-1 downto 0);
variable XNUM : UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
if L(L'left) = '1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'left) = '1' then
XDENOM := UNSIGNED(-R);
RNEG := true;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : SIGNED; R : INTEGER) return SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : SIGNED) return SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function ">";
-- Id: C.5
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function ">";
-- Id: C.6
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function "<";
-- Id: C.11
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function "<";
-- Id: C.12
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'length), R);
end function "<=";
-- Id: C.17
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "<=";
-- Id: C.18
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'length), R);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'length), R);
end function ">=";
-- Id: C.23
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'length));
end function ">=";
-- Id: C.24
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'length), R);
end function "=";
-- Id: C.29
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length));
end function "=";
-- Id: C.30
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNSIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : SIGNED) return BOOLEAN is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'length), R));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN is
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'length), R));
end function "/=";
-- Id: C.35
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'length)));
end function "/=";
-- Id: C.36
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN is
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'length)));
end function "/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNSIGNED; COUNT : NATURAL) return UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : SIGNED; COUNT : NATURAL) return SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : SIGNED) return INTEGER is
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
if ARG(ARG'left) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED is
variable RESULT : UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER;
SIZE : NATURAL) return SIGNED is
variable RESULT : SIGNED(SIZE-1 downto 0);
variable B_VAL : BIT := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : SIGNED; NEW_SIZE : NATURAL) return SIGNED is
alias INVEC : SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNSIGNED; NEW_SIZE : NATURAL) return UNSIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNSIGNED) return UNSIGNED is
variable RESULT : UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : SIGNED) return SIGNED is
variable RESULT : SIGNED(L'length-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end function "xnor";
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
end package body NUMERIC_BIT;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : ElectronFpga_core.vhd
-- /___/ /\ Timestamp : 28/07/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: ElectronFpga_core
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ElectronFpga_core is
generic (
IncludeICEDebugger : boolean := false;
IncludeABRRegs : boolean := false;
IncludeJafaMode7 : boolean := false
);
port (
-- Clocks
clk_16M00 : in std_logic;
clk_24M00 : in std_logic; -- for Jafa Mode7
clk_32M00 : in std_logic; -- for Jafa Mode7
clk_33M33 : in std_logic;
clk_40M00 : in std_logic;
-- Hard reset (active low)
hard_reset_n : in std_logic;
-- Keyboard
ps2_clk : in std_logic;
ps2_data : in std_logic;
-- Video
video_red : out std_logic_vector (3 downto 0);
video_green : out std_logic_vector (3 downto 0);
video_blue : out std_logic_vector (3 downto 0);
video_vsync : out std_logic;
video_hsync : out std_logic;
-- Audio
audio_l : out std_logic;
audio_r : out std_logic;
-- External memory (e.g. SRAM and/or FLASH)
-- 512KB logical address space
ext_nOE : out std_logic;
ext_nWE : out std_logic;
ext_nCS : out std_logic;
ext_A : out std_logic_vector (18 downto 0);
ext_Dout : in std_logic_vector (7 downto 0);
ext_Din : out std_logic_vector (7 downto 0);
-- SD Card
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
-- KeyBoard LEDs (active high)
caps_led : out std_logic;
motor_led : out std_logic;
-- Casette Port
cassette_in : in std_logic;
cassette_out : out std_logic;
-- Format of Video
-- 00 - sRGB - interlaced
-- 01 - sRGB - non interlaced
-- 10 - SVGA - 50Hz
-- 11 - SVGA - 60Hz
vid_mode : in std_logic_vector(1 downto 0);
-- Test outputs
test : out std_logic_vector(7 downto 0);
-- ICE T65 Deubgger 57600 baud serial
avr_RxD : in std_logic;
avr_TxD : out std_logic;
cpu_addr : out std_logic_vector(15 downto 0)
);
end;
architecture behavioral of ElectronFpga_core is
signal RSTn : std_logic;
signal cpu_R_W_n : std_logic;
signal cpu_a : std_logic_vector (23 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal ROM_n : std_logic;
signal ula_data : std_logic_vector (7 downto 0);
signal ula_enable : std_logic;
signal key_break : std_logic;
signal key_turbo : std_logic_vector(1 downto 0);
signal sound : std_logic;
signal kbd_data : std_logic_vector(3 downto 0);
signal cpu_clken : std_logic;
signal cpu_clken_r : std_logic;
signal rom_latch : std_logic_vector(3 downto 0);
signal ext_enable : std_logic;
signal abr_enable : std_logic;
signal abr_lo_bank_lock : std_logic;
signal abr_hi_bank_lock : std_logic;
signal video_vsync_int : std_logic;
signal video_hsync_int : std_logic;
signal video_red_int : std_logic_vector(3 downto 0);
signal video_green_int : std_logic_vector(3 downto 0);
signal video_blue_int : std_logic_vector(3 downto 0);
begin
video_vsync <= video_vsync_int;
video_hsync <= video_hsync_int;
video_red <= video_red_int;
video_green <= video_green_int;
video_blue <= video_blue_int;
GenDebug: if IncludeICEDebugger generate
signal cpu_clken1 : std_logic;
begin
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => true,
UseAlanDCore => false
)
port map (
clock_avr => clk_24M00,
busmon_clk => clk_16M00,
busmon_clken => cpu_clken1,
cpu_clk => clk_16M00,
cpu_clken => cpu_clken,
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
Sync => open,
Addr => cpu_a(15 downto 0),
R_W_n => cpu_R_W_n,
Din => cpu_din,
Dout => cpu_dout,
SO_n => '1',
Res_n => RSTn,
Rdy => '1',
trig => "00",
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => '0',
sw_reset_avr => not hard_reset_n,
led_bkpt => open,
led_trig0 => open,
led_trig1 => open,
tmosi => open,
tdin => open,
tcclk => open
);
process(clk_16M00)
begin
if rising_edge(clk_16M00) then
cpu_clken1 <= cpu_clken;
end if;
end process;
end generate;
GenNoDebugCore: if not IncludeICEDebugger generate
T65core : entity work.T65
port map (
Mode => "00",
Abort_n => '1',
SO_n => '1',
Res_n => RSTn,
Enable => cpu_clken,
Clk => clk_16M00,
Rdy => '1',
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
R_W_n => cpu_R_W_n,
Sync => open,
A => cpu_a,
DI => cpu_din,
DO => cpu_dout
);
avr_TxD <= avr_RxD;
end generate;
ula : entity work.ElectronULA
generic map (
IncludeMMC => true,
Include32KRAM => false,
IncludeVGA => true,
IncludeJafaMode7 => IncludeJafaMode7,
LimitROMSpeed => false,
LimitIOSpeed => false
)
port map (
clk_16M00 => clk_16M00,
clk_24M00 => clk_24M00,
clk_32M00 => clk_32M00,
clk_33M33 => clk_33M33,
clk_40M00 => clk_40M00,
-- CPU Interface
addr => cpu_a(15 downto 0),
data_in => cpu_dout,
data_out => ula_data,
data_en => ula_enable,
R_W_n => cpu_R_W_n,
RST_n => RSTn,
IRQ_n => cpu_IRQ_n,
NMI_n => cpu_NMI_n,
-- Rom Enable
ROM_n => ROM_n,
-- Video
red => video_red_int,
green => video_green_int,
blue => video_blue_int,
vsync => video_vsync_int,
hsync => video_hsync_int,
-- Audio
sound => sound,
-- SD Card
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
-- Casette
casIn => cassette_in,
casOut => cassette_out,
-- Keyboard
kbd => kbd_data,
-- MISC
caps => caps_led,
motor => motor_led,
rom_latch => rom_latch,
mode_init => vid_mode,
-- Clock Generation
cpu_clken_out => cpu_clken,
turbo => key_turbo
);
input : entity work.keyboard port map(
clk => clk_16M00,
rst_n => hard_reset_n, -- to avoid a loop when break pressed!
ps2_clk => ps2_clk,
ps2_data => ps2_data,
col => kbd_data,
row => cpu_a(13 downto 0),
break => key_break,
turbo => key_turbo
);
cpu_NMI_n <= '1';
RSTn <= hard_reset_n and key_break;
audio_l <= sound;
audio_r <= sound;
ext_enable <= '1' when
-- ROM accrss
ROM_n = '0' or
-- Non screen main memory access (0000-2FFF)
cpu_a(15 downto 13) = "000" or cpu_a(15 downto 12) = "0010" or
-- Sideways RAM Access
(cpu_a(15 downto 14) = "10" and rom_latch(3 downto 1) /= "100") else '0';
cpu_din <= ext_Dout when ext_enable = '1' else
ula_data when ula_enable = '1' else
x"F1";
-- Pipeline external memory interface
-- External addresses 00000-3FFFF are routed to FLASH 80000-DFFFFF
-- External addresses 40000-7FFFF are routed to SRAM
-- Note: the bottom 32K of CPU address space is mapped to SRAM, 20K of this is overlaid by the ULA
process(clk_16M00,hard_reset_n)
begin
if hard_reset_n = '0' then
ext_A <= (others => '0');
ext_Din <= (others => '0');
ext_nWE <= '1';
ext_nOE <= '1';
elsif rising_edge(clk_16M00) then
-- delayed cpu_clken for use as an external write signal
cpu_clken_r <= cpu_clken;
if cpu_a(15) = '0' then
-- exteral main memory access
ext_A <= "1" & "000" & cpu_a(14 downto 0);
elsif cpu_a(15 downto 14) = "11" then
-- The OS rom image lives in slot 8 as on the Elk this is where the
-- keyboard appears, which keeps the external memory image down to 256KB.
ext_A <= "0" & "1000" & cpu_a(13 downto 0);
elsif cpu_a(15 downto 14) = "10" and rom_latch(3 downto 2) = "00" then
-- Slots 0..3 are mapped to SRAM
ext_A <= "1" & rom_latch & cpu_a(13 downto 0);
elsif cpu_a(15 downto 14) = "10" and rom_latch(3 downto 0) = "0100" and cpu_a(13 downto 8) >= "110110" then
-- Slots 4 (MMFS) has B600 onwards as writeable for private workspace so mapped to SRAM
ext_A <= "1" & rom_latch & cpu_a(13 downto 0);
else
-- everyting else is ROM
ext_A <= "0" & rom_latch & cpu_a(13 downto 0);
end if;
ext_Din <= cpu_dout;
if cpu_R_W_n = '1' or ext_enable = '0' or cpu_clken_r = '0' then
-- Default is disable WE, except in a few cases
ext_nWE <= '1';
elsif cpu_a(15) = '0' then
-- exteral main memory access
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 2) = "00" and rom_latch(0) = '0' and abr_lo_bank_lock = '0' then
-- Slots 0,2 are write protected with FCDC/FCDD
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 2) = "00" and rom_latch(0) = '1' and abr_hi_bank_lock = '0' then
-- Slots 1,3 are write protected with FCDE/FCDF
ext_nWE <= '0';
elsif cpu_a(14) = '0' and rom_latch(3 downto 0) = "0100" and cpu_a(13 downto 8) >= "110110" then
-- Slots 4 (MMFS) has B600 onwards as writeable for private workspace
ext_nWE <= '0';
else
-- Other slots are read only
ext_nWE <= '1';
end if;
-- Could make this more restrictive
if cpu_R_W_n = '1' and ext_enable = '1' then
ext_nOE <= '0';
else
ext_nOE <= '1';
end if;
end if;
end process;
-- Always enabled
ext_nCS <= '0';
--------------------------------------------------------
-- ABR Lock Registers
--------------------------------------------------------
ABRIncluded: if IncludeABRRegs generate
abr_enable <= '1' when cpu_a(15 downto 2) & "00" = x"fcdc" else '0';
process(clk_16M00, RSTn)
begin
if RSTn = '0' then
abr_lo_bank_lock <= '1';
abr_hi_bank_lock <= '1';
elsif rising_edge(clk_16M00) then
if cpu_clken = '1' then
if abr_enable = '1' and cpu_R_W_n = '0' then
if cpu_a(1) = '0' then
abr_lo_bank_lock <= cpu_a(0);
else
abr_hi_bank_lock <= cpu_a(0);
end if;
end if;
end if;
end if;
end process;
end generate;
ABRExcluded: if not IncludeABRRegs generate
abr_lo_bank_lock <= '1';
abr_hi_bank_lock <= '1';
end generate;
cpu_addr <= cpu_a(15 downto 0);
test <= video_vsync_int & video_hsync_int & video_blue_int(3) & video_green_int(3) & video_red_int(3) & "00" & cpu_IRQ_n;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatch is
port(SW : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(2 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDG : out std_logic_vector(8 downto 7));
end BasicWatch;
architecture Shell of BasicWatch is
begin
system_core : entity work.BasicWatchCore(RTL)
port map(reset => SW(0),
clk => CLOCK_50,
mode => not KEY(1),
hSet => not KEY(2),
mSet => not KEY(0),
hTens => HEX7,
hUnits => HEX6,
mTens => HEX5,
mUnits => HEX4,
sTens => HEX3,
sUnits => HEX2,
sTick => LEDG(8),
ledOut => LEDG(7));
end Shell;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- N TO 16 BITS Adaptateur
-- valeurs possibles entrée 8,16,32
-- tester avec 1, 2, 4 avec le code en 8to16, devrait fonctionner ou presque ...
-- ALtera libray used for 32 to 16 bits scfifo component
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
use ieee.math_real.all;
entity flowto16 is
generic (
INPUT_SIZE : integer;
FIFO_DEPTH : integer := 32
);
port (
rst_n : in std_logic;
clk : in std_logic;
in_data : in std_logic_vector(INPUT_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector(15 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end flowto16;
architecture rtl of flowto16 is
-- signaux pour inf a 16bits
constant CPT_MAX : integer := 16/INPUT_SIZE;
type state_t is (Initial, WaitSd);
signal state : state_t := Initial;
signal tmp8bits : std_logic_vector(7 downto 0) := (others=>'0');
-- signaux pour fonctionnement 32 to 16
type state_32t is (Initial, SendLSB, DumpLastMSB, DumpLastLSB, SyncSignal);
signal state_32b : state_32t := Initial;
signal tmp16bits : std_logic_vector(15 downto 0) := (others=>'0');
signal fifo_empty_s : std_logic := '0';
signal databuf : std_logic_vector(31 downto 0) := (others=>'0');
signal aclr_s : std_logic := '0';
signal rdreq_s : std_logic := '0';
signal usedw_s : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH))))-1 downto 0) := (others=>'0');
signal fifo_empty_r : std_logic :='0';
begin
label_16bits : if (INPUT_SIZE=16) generate
out_fv <= in_fv;
out_dv <= in_dv;
out_data <= in_data;
end generate label_16bits;
label_32bits : if (INPUT_SIZE=32) generate
aclr_s <= not(rst_n);
with state_32b select
rdreq_s <= not(fifo_empty_s) when Initial,
'0' when SendLSB ,
'0' when others;
FIFO : component scfifo
generic map(
intended_device_family => "Cyclone III",
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => 32,
lpm_widthu => integer(ceil(log2(real(FIFO_DEPTH)))),
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
port map
(
data => in_data,
rdreq => rdreq_s,
clock => clk,
wrreq => in_dv,
aclr => aclr_s ,
q => databuf,
empty => fifo_empty_s,
usedw => usedw_s,
full => open
);
process(clk, rst_n)
begin
if (rst_n = '0') then
state_32b <= Initial;
out_fv <= '0';
out_dv <='0';
out_data <= (others=>'0');
tmp16bits <= (others=>'0');
fifo_empty_r <= '1';
-- rdreq_s <= '0';
elsif rising_edge(clk) then
-- out_fv <= in_fv;
out_dv <='0';
fifo_empty_r <= fifo_empty_s;
case state_32b is
when Initial =>
if (in_fv = '1') then
out_fv <='1';
end if;
if( fifo_empty_r = '0' ) then
out_data <= databuf(31 downto 16);
out_dv <='1';
tmp16bits <= databuf(15 downto 0);
state_32b <= SendLSB;
end if;
when SendLSB =>
out_data <= tmp16bits ;
out_dv <='1';
state_32b <= Initial;
-- Dernière donnée : cas particulier
if(fifo_empty_s = '1') then
state_32b <= DumpLastMSB;
end if;
when DumpLastMSB =>
out_dv <='1';
out_data <= databuf(31 downto 16);
state_32b <= DumpLastLSB;
when DumpLastLSB =>
out_dv <='1';
out_data <= databuf(15 downto 0);
state_32b <= SyncSignal;
when SyncSignal =>
if (in_fv = '0') then
out_fv <='0';
out_dv <='0';
end if;
state_32b <= Initial;
end case;
end if;
end process;
end generate label_32bits;
-- Fonctionnement 8 TO 16bits
label_8bits : if INPUT_SIZE = 8 generate
process(clk,rst_n)
begin
if (rst_n = '0') then
state <= Initial;
out_fv <= '0';
out_dv <='0';
out_data <= (others=>'0');
tmp8bits <= (others=>'0');
elsif rising_edge(clk) then
out_fv <= in_fv;
out_dv <='0';
case state is
when Initial =>
if (in_dv ='1' and in_fv='1') then
out_dv <='0';
tmp8bits <= in_data;
state <= WaitSd;
end if;
when WaitSd =>
if (in_dv ='1' and in_fv='1') then
out_data <= tmp8bits & in_data;
out_dv <='1';
state <= Initial;
end if;
end case;
end if;
end process;
end generate label_8bits;
-- Fonctionnement non verifie pour INPUT_SIZE < 8
-- label_inf8bits : if INPUT_SIZE < 8 generate
-- process(clk,rst_n)
-- variable cpt : integer range 0 to CPT_MAX := 0;
-- begin
-- if (rst_n = '0') then
-- state <= Initial;
-- out_fv <= '0';
-- out_dv <='0';
-- out_data <= (others=>'0');
-- tmp <= (others=>'0');
-- cpt = 0;
-- elsif rising_edge(clk) then
-- out_fv <= in_fv;
-- out_dv <='0';
-- case state is
-- when Initial =>
-- if in_dv ='1' then
-- tmp (INPUT_SIZE-1 downto 0) <= in_data;
-- tmp sll INPUT_SIZE;
-- cpt = cpt + 1;
-- if (cpt = CPT_MAX) then
-- state <= WaitSd;
-- cpt = 0;
-- end if;
-- end if;
-- when WaitSd =>
-- if in_dv ='1' then
-- out_data <= tmp ;
-- out_dv <='1';
-- state <= Initial;
-- end if;
-- end case;
-- end if;
-- end process;
-- end generate label_inf8bits;
end rtl;
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