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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type t_reg_type is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
end record;
constant TRES : t_reg_type := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
hsel => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0'
);
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tr, trin : t_reg_type;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : t_reg_type;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable bphit1, bphit2 : std_ulogic;
variable vh : hclk_reg_type;
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata;
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
-- check for AHB watchpoints
bphit1 := '0'; bphit2 := '0';
if TRACEN and ((ahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit1 := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit2 := '1'; end if;
if (bphit1 or bphit2) = '1' then
if ((tr.enable and not r.act) = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.bphit := tr.break; end if;
end if;
end if;
-- generate AHB buffer inputs
vabufi.write := "0000";
if TRACEN then
if (tr.enable = '1') and (r.act = '0') then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := bphit1 or bphit2;
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi2.hwdata(31 downto 0);
else
vabufi.data(63 downto 32) := ahbmi.hrdata(31 downto 0);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := tr.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0);
end if;
-- write trace buffer
if (tr.enable and not r.act) = '1' then
if (tr.ahbactive and ahbsi2.hready) = '1' then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- save AHB transfer parameters
if (ahbsi2.hready = '1' ) then
tv.haddr := ahbsi2.haddr; tv.hwrite := ahbsi2.hwrite; tv.htrans := ahbsi2.htrans;
tv.hsize := ahbsi2.hsize; tv.hburst := ahbsi2.hburst;
tv.hmaster := ahbsi2.hmaster; tv.hmastlock := ahbsi2.hmastlock;
end if;
if tr.hsel = '1' then tv.hwdata := ahbsi2.hwdata(31 downto 0); end if;
if ahbsi2.hready = '1' then
tv.hsel := ahbsi2.hsel(hindex);
tv.ahbactive := ahbsi2.htrans(1);
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if tstop = '0' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := ahbsi2.hwdata(0);
v.be(index) := ahbsi2.hwdata(1);
v.bw(index) := ahbsi2.hwdata(2);
v.bs(index) := ahbsi2.hwdata(3);
v.bx(index) := ahbsi2.hwdata(4);
v.bz(index) := ahbsi2.hwdata(5);
v.reset(index) := ahbsi2.hwdata(9);
v.halt(index) := ahbsi2.hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := ahbsi2.hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := ahbsi2.hwdata(NCPU-1 downto 0);
v.ss := ahbsi2.hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(2 downto 0) := tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := ahbsi2.hwdata((TBUFABITS+ 15) downto 16);
tv.break := ahbsi2.hwdata(2);
tv.dcnten := ahbsi2.hwdata(1);
tv.enable := ahbsi2.hwdata(0);
else
tv.delaycnt := tr.delaycnt; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := ahbsi2.hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg1.read := ahbsi2.hwdata(1);
tv.tbreg1.write := ahbsi2.hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg2.read := ahbsi2.hwdata(1);
tv.tbreg2.write := ahbsi2.hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not (tr.enable and not r.act);
case tr.haddr(3 downto 2) is
when "00" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "01" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "10" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when others =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := ahbsi2.hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0';
tv.hsel := '0'; tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
end if;
vabufi.enable := vabufi.enable and not ahbsi.scanen;
vabufi.diag := ahbsi.testen & "000";
rin <= v; trin <= tv; tbi <= vabufi;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmastlock, hclken, ahbsi2.hmastlock);
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
gen3 : for i in ahbsi.haddr'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
gen4 : for i in ahbsi.htrans'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
-- gen5 : for i in ahbsi.hwdata'range generate
gen5 : for i in 0 to 31 generate
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
gen6 : for i in ahbsi.hsize'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsize(i), hclken, ahbsi2.hsize(i));
end generate;
gen7 : for i in ahbsi.hburst'range generate
ag7 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hburst(i), hclken, ahbsi2.hburst(i));
end generate;
gen8 : for i in ahbsi.hmaster'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmaster(i), hclken, ahbsi2.hmaster(i));
end generate;
gen9 : for i in ahbsi.hsel'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen10 : for i in hrdata2x'range generate
ag10 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, testen => testen) port map (cpuclk, tbi, tbo);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
end;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity TEST is
end TEST;
architecture BEH of TEST is
component gianni is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
nw, clk : in std_logic;
res : out std_logic_vector(31 downto 0);
ready : out std_logic
);
end component;
signal op : std_logic_vector(1 downto 0);
signal din : std_logic_vector(31 downto 0);
signal nw, clk : std_logic;
signal res : std_logic_vector(31 downto 0);
signal ready : std_logic;
begin
DUT: gianni port map (op, din, nw, clk, res, ready);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
nw <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 101 ns, '0' after 111 ns,
'1' after 161 ns, '0' after 171 ns;
op <= "01" after 11 ns, -- OP "01" aka OR
"10" after 61 ns, -- OP "10" aka SLT
"00" after 111 ns, -- OP "00" aka ADD
"11" after 171 ns; -- OP "11" aka MUL
din <= conv_std_logic_vector(5, 32) after 11 ns, conv_std_logic_vector(3, 32) after 21 ns,
conv_std_logic_vector(2, 32) after 61 ns, conv_std_logic_vector(7, 32) after 71 ns,
conv_std_logic_vector(4, 32) after 111 ns, conv_std_logic_vector(9, 32) after 121 ns,
conv_std_logic_vector(1, 32) after 171 ns, conv_std_logic_vector(10, 32) after 181 ns;
end BEH;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity TEST is
end TEST;
architecture BEH of TEST is
component gianni is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
nw, clk : in std_logic;
res : out std_logic_vector(31 downto 0);
ready : out std_logic
);
end component;
signal op : std_logic_vector(1 downto 0);
signal din : std_logic_vector(31 downto 0);
signal nw, clk : std_logic;
signal res : std_logic_vector(31 downto 0);
signal ready : std_logic;
begin
DUT: gianni port map (op, din, nw, clk, res, ready);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
nw <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 101 ns, '0' after 111 ns,
'1' after 161 ns, '0' after 171 ns;
op <= "01" after 11 ns, -- OP "01" aka OR
"10" after 61 ns, -- OP "10" aka SLT
"00" after 111 ns, -- OP "00" aka ADD
"11" after 171 ns; -- OP "11" aka MUL
din <= conv_std_logic_vector(5, 32) after 11 ns, conv_std_logic_vector(3, 32) after 21 ns,
conv_std_logic_vector(2, 32) after 61 ns, conv_std_logic_vector(7, 32) after 71 ns,
conv_std_logic_vector(4, 32) after 111 ns, conv_std_logic_vector(9, 32) after 121 ns,
conv_std_logic_vector(1, 32) after 171 ns, conv_std_logic_vector(10, 32) after 181 ns;
end BEH;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:57:22 07/29/2015
-- Design Name:
-- Module Name: CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is
Port ( RST : in STD_LOGIC;
CLK : in STD_LOGIC;
ABUS : out STD_LOGIC_VECTOR (15 downto 0);
DBUS : inout STD_LOGIC_VECTOR (15 downto 0);
nMREQ : out STD_LOGIC;
nRD : out STD_LOGIC;
nWR : out STD_LOGIC;
nBHE : out STD_LOGIC;
nBLE : out STD_LOGIC;
s1 : out STD_LOGIC;
s2 : out STD_LOGIC;
s3 : out STD_LOGIC;
s4 : out STD_LOGIC;
s5 : out STD_LOGIC;
s7 : out STD_LOGIC;
i : out STD_LOGIC_VECTOR(15 downto 0)
);
end CPU;
architecture Behavioral of CPU is
component clock is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
t : out STD_LOGIC_VECTOR (4 downto 0)
);
end component;
component fetch is
port (
irnew : in STD_LOGIC_VECTOR (15 downto 0); --·Ã´æÄ£¿éÊäÈëµÄIR
pcnew : in STD_LOGIC_VECTOR (15 downto 0); --»Øдģ¿é£¬¸üÂPC
clk : in STD_LOGIC; --½ÚÅÄ
pcupdate : in STD_LOGIC; --¸æËßÒª¸üÐÂPCÁË
reset : in STD_LOGIC; --¸´Î»
t0 : in STD_LOGIC;
t1 : in STD_LOGIC;
irout : out STD_LOGIC_VECTOR (15 downto 0); --Êä³öµÄIR
pcout : out STD_LOGIC_VECTOR (15 downto 0);
irrep : out STD_LOGIC
);
end component;
component ALU is
port (
-- ʵÏÖ×¼±¸ºÍÔËË㹦ÄÜ
enable_t : in std_logic; -- ×¼±¸ºÍÔËË㹦ÜʹÄÜÐź?
ir : in std_logic_vector(15 downto 0); --16λµÄIRÐźÅ
-- Ïò·Ã´æ¿ØÖÆÄ£¿éÊä³ö
sig_reg7aluout : out std_logic_vector ( 15 downto 0 ); -- ÔÝ´æÆ÷Êä³ö¶Ë¿Ú
sig_reg7addrout : out std_logic_vector ( 15 downto 0 ); -- 8λµØÖ·Êä³ö¶Ë¿Ú
--reg7_out : out std_logic_vector ( 7 downto 0 );
-- ʵÏÖ»Øд¹¦ÄÜ
enable_wb : in std_logic ; -- »Øд¹¦ÄÜʹÄÜ
reg_wb : in std_logic_vector (7 downto 0 ); -- »Øд½ÓÊն˿Ú
-- ½øλ±êÖ¾
cy : out std_logic
);
end component;
component control is
port (
IRreq :in STD_LOGIC; --irʹÄÜ
IR:out STD_LOGIC_VECTOR (15 downto 0); --¶Ôȡָģ¿éÊä³öir
PCout: in STD_LOGIC_VECTOR (15 downto 0); --½ÓÊÕÈ¡Ö¸Ö¸Áî
ALUOUT : in STD_LOGIC_VECTOR (7 downto 0); --ÔËËãÄ£¿é
Addr : in STD_LOGIC_VECTOR (15 downto 0); --ÔËËãÄ£¿é
ABUS : out STD_LOGIC_VECTOR (15 downto 0); --¶ÔÖ÷´æÊä³öµØÖ·
DBUS : inout STD_LOGIC_VECTOR (15 downto 0); --Êý¾Ý×ÜÏß
--¸øÖ÷´æ·¢
nWR : out STD_LOGIC; --дÖ÷´æʹÄÜ
nRD : out STD_LOGIC; --¶ÁÖ÷´æʹÄÜ
nMREQ : out STD_LOGIC; --Ö÷´æƬѡÐźÅ
nBHE : out STD_LOGIC; --Ö÷´æ¸ß°Ëλ¿ØÖÆÐźÅ
nBLE : out STD_LOGIC; --Ö÷´æµÍ°Ëλ¿ØÖÆÐźÅ
--ÔËËãÄ£¿é/ȡָģ¿é¸ø³ö£¬Òª²»Òª·ÃÄÚ´æ
nMWR : in STD_LOGIC; --ALUдÊýʹÄÜ
nMRD : in STD_LOGIC; --ALUÈ¡ÊýʹÄÜ
--À´×Դ洢ģ¿é
data : out STD_LOGIC_VECTOR (7 downto 0) --¶Ô´æ´¢¿ØÖÆÊä³öÈ¡µ½µÄÊý¾Ý¡£
);
end component;
component save is
port (
t : in STD_LOGIC;
ALUOUT : in std_logic_vector(7 downto 0); --- ALUÊä³öµÄÖµ
data : in std_logic_vector(7 downto 0); --- ½ÓÊÕÇøÊôµÄʱºò·Ã´æ¿ØÖƵÄÊý¾Ý
nMWR : out std_logic;
IR : in STD_LOGIC_VECTOR (15 downto 0);
nMRD : out STD_LOGIC;
Rtemp : out std_logic_vector(7 downto 0)
);
end component;
component write_back is
port (
PCin:in std_logic_vector(15 downto 0); --½ÓÊÕȡָģ¿é´«³öµÄPC£¬ÓÃÓÚ0ÌøתºÍÖ±½ÓÌøת
t : in STD_LOGIC; -- »ØдʹÄÜ
Rtemp : in STD_LOGIC_VECTOR (7 downto 0); -- ½ÓÊÕÀ´×Ô´æ´¢¹ÜÀíÄ£¿éµÄ¼Ä´æÆ÷
IR : in STD_LOGIC_VECTOR (15 downto 0); -- ½ÓÊÕȡָģ¿é´«³öµÄIR
--z:in STD_LOGIC; --½ÓÊÕALU´«³öµÄz
cy:in STD_LOGIC; --½ÓÊÕALU´«³öµÄ½øλ
Rupdate : out STD_LOGIC; -- ¼Ä´æÆ÷»ØдʹÄÜÐźÅ
Rdata : out STD_LOGIC_VECTOR (7 downto 0); -- ALU Êä³öµÄ¼Ä´æÆ÷»ØдÊý¾Ý
PCupdate : out STD_LOGIC; -- PC »ØдʹÄÜÐͺÅ
PCnew : out STD_LOGIC_VECTOR (15 downto 0) --Êä³öPC»ØдµÄÖµ
);
end component;
signal t : STD_LOGIC_VECTOR(4 downto 0); --Õý³£½ÚÅÄ
signal IR_C_F : STD_LOGIC_VECTOR(15 downto 0); -- ȡָģ¿éÈ¡³öµÄir
signal PCout_F_CW : STD_LOGIC_VECTOR(15 downto 0); -- PC ËÍÍù·Ã´æ¿ØÖÆÈ¡Ö¸£¬ËÍ»Øдģ¿é
signal PCnew_W_F : STD_LOGIC_VECTOR(15 downto 0); -- ÌøתµÄʱºòÒª¸üеÄPC
signal PCupdate_W_F : STD_LOGIC; -- Ìøת¸üÐÂPCʹÄÜÐźÅ
signal irout_F_ASW : STD_LOGIC_VECTOR(15 downto 0); --ȡָģ¿éÈ¡µ½µÄIr,»áËÍÍùALU ´æ´¢ ºÍ»Øд
signal irreq_F_C : STD_LOGIC; -- È¡Ö¸ËÍÍù·Ã´æ¿ØÖÆ£¬¸æËßҪȡָÁîÁË
signal ALUOUT_A_CS : STD_LOGIC_VECTOR(15 downto 0); ---ALU ËÍÍùÆäËûÄ£¿éµÄaluout
signal Addr_A_C : STD_LOGIC_VECTOR(15 downto 0); --- ALU ËÍÍù·Ã´æµÄaddr
signal Rupdate_W_A : STD_LOGIC; ---»Øдģ¿éËÍÍùALUµÄ¸ü¸Ä¼Ä´æÆ÷ʹÄÜÐźÅ
signal Rdata_W_A : STD_LOGIC_VECTOR(7 downto 0); ----»Øдģ¿éÊä³öµÄÒª¸üеļĴæÆ÷µÄÖµ
signal data_C_S : STD_LOGIC_VECTOR(7 downto 0); -- È¡ÊýµÄʱºòʹÓÃ
signal nMWR_S_C : STD_LOGIC; --дÊýʹÄÜ
signal nMRD_S_C : STD_LOGIC; --¶ÁÊýʹÄÜ
signal Rtemp_S_W : STD_LOGIC_VECTOR(7 downto 0); -- ´æ´¢Ä£¿éÏò»Øдģ¿é
signal cy_A_W : STD_LOGIC; --½øλ
begin
u1: clock port map(CLK, RST, t);
u2: fetch port map(IR_C_F, PCnew_W_F, CLK , PCupdate_W_F, RST, t(0), t(1), irout_F_ASW, PCout_F_CW, irreq_F_C);
u3: ALU port map(t(2), irout_F_ASW, ALUOUT_A_CS, Addr_A_C, Rupdate_W_A, Rdata_W_A, cy_A_W);
u4: control port map(irreq_F_C, IR_C_F, PCout_F_CW, ALUOUT_A_CS(7 downto 0), Addr_A_C, ABUS, DBUS, nWR, nRD, nMREQ, nBHE, nBLE, nMWR_S_C, nMRD_S_C , data_C_S);
u5: save port map(t(3), ALUOUT_A_CS(7 downto 0), data_C_S, nMWR_S_C, irout_F_ASW, nMRD_S_C, Rtemp_S_W);
u6: write_back port map(PCout_F_CW, t(4), Rtemp_S_W, irout_F_ASW, cy_A_W, Rupdate_W_A, Rdata_W_A, PCupdate_W_F, PCnew_W_F);
s1 <= t(0);
s2 <= t(1);
s3 <= t(2);
s4 <= t(3);
s5 <= t(4);
s7 <= Rupdate_W_A;
i <= IR_C_F;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : WR_FLASH_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- *********************************************************************
-- Copyright 2008, Cypress Semiconductor Corporation.
--
-- This software is owned by Cypress Semiconductor Corporation (Cypress)
-- and is protected by United States copyright laws and international
-- treaty provisions. Therefore, you must treat this software like any
-- other copyrighted material (e.g., book, or musical recording), with
-- the exception that one copy may be made for personal use or
-- evaluation. Reproduction, modification, translation, compilation, or
-- representation of this software in any other form (e.g., paper,
-- magnetic, optical, silicon, etc.) is prohibited without the express
-- written permission of Cypress.
--
-- Disclaimer: Cypress makes no warranty of any kind, express or
-- implied, with regard to this material, including, but not limited to,
-- the implied warranties of merchantability and fitness for a particular
-- purpose. Cypress reserves the right to make changes without further
-- notice to the materials described herein. Cypress does not assume any
-- liability arising out of the application or use of any product or
-- circuit described herein. Cypress' products described herein are not
-- authorized for use as components in life-support devices.
--
-- This software is protected by and subject to worldwide patent
-- coverage, including U.S. and foreign patents. Use may be limited by
-- and subject to the Cypress Software License Agreement.
--
-- *********************************************************************
-- Author : $Author: fwi $ @ cypress.com
-- Department : MPD_BE
-- Date : $Date: 2011-01-11 13:22:13 +0100 (di, 11 jan 2011) $
-- Revision : $Revision: 712 $
-- *********************************************************************
-- Description
--
-- *********************************************************************
-------------------
-- LIBRARY USAGE --
-------------------
--common:
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--xilinx:
---------
--Library XilinxCoreLib;
library unisim;
use unisim.vcomponents.all;
-----------------------
-- ENTITY DEFINITION --
-----------------------
entity iserdes_mux is
generic(
DATAWIDTH : integer;
NROF_CONN : integer
);
port(
CLOCK : in std_logic;
RESET : in std_logic;
CLKDIV : in std_logic;
-- select comes from the bitalign/wordalign statemachine and is aligned to CLOCK
SEL : in std_logic_vector(15 downto 0);
-- from/to ISERDES
IODELAY_ISERDES_RESET : out std_logic_vector(NROF_CONN-1 downto 0);
IODELAY_INC : out std_logic_vector(NROF_CONN-1 downto 0);
IODELAY_CE : out std_logic_vector(NROF_CONN-1 downto 0);
ISERDES_BITSLIP : out std_logic_vector(NROF_CONN-1 downto 0);
ISERDES_DATA : in std_logic_vector((DATAWIDTH*NROF_CONN)-1 downto 0);
-- made as a one dimensional array, multidimensional arrays parameterisable with generics do not exist in VHDL
--from/to sync
SYNC_RESET : in std_logic;
SYNC_INC : in std_logic;
SYNC_CE : in std_logic;
SYNC_BITSLIP : in std_logic;
SYNC_DATA : out std_logic_vector(DATAWIDTH-1 downto 0)
);
end iserdes_mux;
architecture rtl of iserdes_mux is
begin
muxgen: if (NROF_CONN > 1) generate
multiplexer: process(RESET, CLKDIV)
variable index : integer range 0 to (NROF_CONN-1);
begin
if (RESET = '1') then
IODELAY_ISERDES_RESET <= (others => '0');
IODELAY_INC <= (others => '0');
IODELAY_CE <= (others => '0');
ISERDES_BITSLIP <= (others => '0');
SYNC_DATA <= (others => '0');
elsif (CLKDIV'event and CLKDIV = '1') then
index := TO_INTEGER(UNSIGNED(SEL));
IODELAY_ISERDES_RESET(index) <= SYNC_RESET;
IODELAY_INC(index) <= SYNC_INC;
IODELAY_CE(index) <= SYNC_CE;
SYNC_DATA <= ISERDES_DATA(((index+1)*DATAWIDTH)-1 downto (index*DATAWIDTH));
ISERDES_BITSLIP(index) <= SYNC_BITSLIP;
end if;
end process multiplexer;
end generate;
nomuxgen: if (NROF_CONN = 1) generate
multiplexer: process(RESET, CLKDIV)
variable index : integer range 0 to (NROF_CONN-1);
begin
if (RESET = '1') then
IODELAY_ISERDES_RESET <= (others => '0');
IODELAY_INC <= (others => '0');
IODELAY_CE <= (others => '0');
ISERDES_BITSLIP <= (others => '0');
SYNC_DATA <= (others => '0');
elsif (CLKDIV'event and CLKDIV = '1') then
IODELAY_ISERDES_RESET(0) <= SYNC_RESET;
IODELAY_INC(0) <= SYNC_INC;
IODELAY_CE(0) <= SYNC_CE;
ISERDES_BITSLIP(0) <= SYNC_BITSLIP;
SYNC_DATA <= ISERDES_DATA;
end if;
end process multiplexer;
end generate;
end rtl;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- P A R T N A M E
-- (<name>.vhd)
--
-- Structural
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
ENTITY <name> is
-------------------------------------------------------------------------------
port (
);
end <name>;
-------------------------------------------------------------------------------
ARCHITECTURE structural of <name> is
-------------------------------------------------------------------------------
----------------------------------------------
-- constants
----------------------------------------------
----------------------------------------------
-- signals
----------------------------------------------
--------------------------------------------------------------------------------
begin -- architecture structural
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
INSTANCE_A : entity work.test234
-------------------------------------------------------------------------------
port map (
);
end structural;
|
-- NEED RESULT: ARCH00146.P1: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P2: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P3: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P4: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P5: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P6: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P7: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P8: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P9: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P10: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P11: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P12: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P13: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P14: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P15: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P16: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146.P17: Multi inertial transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00146: One inertial transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00146
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00146(ARCH00146)
-- ENT00146_Test_Bench(ARCH00146_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00146 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00146 ;
--
architecture ARCH00146 of ENT00146 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00146" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00146 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00146_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00146_Test_Bench ;
--
architecture ARCH00146_Test_Bench of ENT00146_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_bit_vector : inout st_bit_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_int1_vector : inout st_int1_vector
; s_st_time_vector : inout st_time_vector
; s_st_phys1_vector : inout st_phys1_vector
; s_st_real_vector : inout st_real_vector
; s_st_real1_vector : inout st_real1_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
; s_st_arr1_vector : inout st_arr1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00146 ( ARCH00146 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_bit_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_int1_vector
, s_st_time_vector
, s_st_phys1_vector
, s_st_real_vector
, s_st_real1_vector
, s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
, s_st_arr1_vector
, s_st_arr2_vector
, s_st_arr3_vector
) ;
end block L1 ;
end ARCH00146_Test_Bench ;
|
--------------------------------------------------------------------------------
-- KBD ENC
-- Anders Nilsson
-- 16-feb-2016
-- Version 1.1
-- KBD is copied from VGA_LAB and modified for our computer
-- library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- basic IEEE library
use IEEE.NUMERIC_STD.ALL; -- IEEE library for the unsigned type
-- and various arithmetic operations
-- entity
entity KBD_ENC is
port ( clk : in std_logic; -- system clock (100 MHz)
rst : in std_logic; -- reset signal
PS2KeyboardCLK : in std_logic; -- USB keyboard PS2 clock
PS2KeyboardData : in std_logic; -- USB keyboard PS2 data
input : out std_logic); -- input flag
end KBD_ENC;
-- architecture
architecture behavioral of KBD_ENC is
signal PS2Clk : std_logic; -- Synchronized PS2 clock
signal PS2Data : std_logic; -- Synchronized PS2 data
signal PS2Clk_Q1, PS2Clk_Q2 : std_logic; -- PS2 clock one pulse flip flop
signal PS2Clk_op : std_logic; -- PS2 clock one pulse
signal PS2Data_sr : std_logic_vector(10 downto 0);-- PS2 data shift register
signal PS2BitCounter : unsigned(3 downto 0); -- PS2 bit counter
signal make_Q : std_logic; -- make one pulselse flip flop
signal make_op : std_logic; -- make one pulse
type state_type is (IDLE, MAKE, BREAK); -- declare state types for PS2
signal PS2state : state_type; -- PS2 state
signal ScanCode : std_logic_vector(7 downto 0); -- scan code
signal BC11 : std_logic;
begin
-- Synchronize PS2-KBD signals
process(clk)
begin
if rising_edge(clk) then
PS2Clk <= PS2KeyboardCLK;
PS2Data <= PS2KeyboardData;
end if;
end process;
-- Generate one cycle pulse from PS2 clock, negative edge
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
PS2Clk_Q1 <= '1';
PS2Clk_Q2 <= '0';
else
PS2Clk_Q1 <= PS2Clk;
PS2Clk_Q2 <= not PS2Clk_Q1;
end if;
end if;
end process;
PS2Clk_op <= (not PS2Clk_Q1) and (not PS2Clk_Q2);
-- PS2 data shift register
-- ***********************************
-- * *
-- * VHDL for : *
-- * PS2_data_shift_reg *
-- * *
-- ***********************************
process(clk)
begin
if rising_edge(clk) then
if PS2Clk_op = '1' then
PS2Data_sr <= to_stdlogicvector(to_bitvector(PS2Data_sr) srl 1);
PS2Data_sr(10) <= PS2Data;
PS2Data_sr <= PS2Data & PS2Data_sr(10 downto 1);
end if;
end if;
end process;
ScanCode <= PS2Data_sr(8 downto 1);
-- PS2 bit counter
-- The purpose of the PS2 bit counter is to tell the PS2 state machine when to change state
-- ***********************************
-- * *
-- * VHDL for : *
-- * PS2_bit_Counter *
-- * *
-- ***********************************
process(clk)
begin
if rising_edge(clk) then
if PS2Clk_op = '1' then
if PS2BitCounter = "1010" then
PS2BitCounter <= "0000";
BC11 <= '1';
else
PS2BitCounter <= PS2BitCounter + 1;
BC11 <= '0';
end if;
else
BC11 <= '0';
end if;
end if;
end process;
-- PS2 state
-- Either MAKE or BREAK state is identified from the scancode
-- Only single character scan codes are identified
-- The behavior of multiple character scan codes is undefined
-- ***********************************
-- * *
-- * VHDL for : *
-- * PS2_State *
-- * *
-- ***********************************
process(clk)
begin
if rising_edge(clk) then
if PS2State = IDLE then
if BC11 = '1' and ScanCode /= "11110000" then
PS2State <= MAKE;
end if;
if BC11 = '1' and ScanCode = "11110000" then
PS2State <= BREAK;
end if;
end if;
-- Checks for a spacebar press and
-- gives a 1 on the input signal until it is released
if ScanCode = x"29" then
if PS2State = MAKE then
input <= '1';
elsif PS2State = BREAK then
input <= '0';
end if;
end if;
if PS2State = MAKE then
PS2State <= IDLE;
end if;
if PS2State = BREAK then
if BC11 = '1' then
PS2State <= IDLE;
end if;
end if;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc411.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00411ent IS
END c03s02b01x01p19n01i00411ent;
ARCHITECTURE c03s02b01x01p19n01i00411arch OF c03s02b01x01p19n01i00411ent IS
constant C1 : real := 3.0;
function complex_scalar(s : real) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real;
signal S2 : real;
signal S3 : real := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00411"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00411 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00411arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc411.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00411ent IS
END c03s02b01x01p19n01i00411ent;
ARCHITECTURE c03s02b01x01p19n01i00411arch OF c03s02b01x01p19n01i00411ent IS
constant C1 : real := 3.0;
function complex_scalar(s : real) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real;
signal S2 : real;
signal S3 : real := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00411"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00411 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00411arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc411.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00411ent IS
END c03s02b01x01p19n01i00411ent;
ARCHITECTURE c03s02b01x01p19n01i00411arch OF c03s02b01x01p19n01i00411ent IS
constant C1 : real := 3.0;
function complex_scalar(s : real) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return real is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : real;
signal S2 : real;
signal S3 : real := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00411"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00411 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00411arch;
|
-----------------------------------------------------------------------------------------
-- baud rate generator for uart
--
-- this module has been changed to receive the baud rate dividing counter from registers.
-- the two registers should be calculated as follows:
-- first register:
-- baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
-- second register:
-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baudGen is
port ( clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
-- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
ce16 : out std_logic); -- baud rate multiplyed by 16
end baudGen;
architecture Behavioral of baudGen is
signal counter : std_logic_vector(15 downto 0);
begin
-- baud divider counter
-- clock divider output
process (clr, clk)
begin
if (clr = '1') then
counter <= (others => '0');
ce16 <= '0';
elsif (rising_edge(clk)) then
if (counter >= baudLimit) then
counter <= counter - baudLimit;
ce16 <= '1';
else
counter <= counter + baudFreq;
ce16 <= '0';
end if;
end if;
end process;
end Behavioral;
|
-----------------------------------------------------------------------------------------
-- baud rate generator for uart
--
-- this module has been changed to receive the baud rate dividing counter from registers.
-- the two registers should be calculated as follows:
-- first register:
-- baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
-- second register:
-- baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baudGen is
port ( clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
-- baudFreq = 16 * baudRate / gcd(clkFreq, 16 * baudRate)
baudFreq : in std_logic_vector(11 downto 0); -- baud rate setting registers - see header description
-- baudLimit = clkFreq / gcd(clkFreq, 16 * baudRate) - baudFreq
baudLimit : in std_logic_vector(15 downto 0); -- baud rate setting registers - see header description
ce16 : out std_logic); -- baud rate multiplyed by 16
end baudGen;
architecture Behavioral of baudGen is
signal counter : std_logic_vector(15 downto 0);
begin
-- baud divider counter
-- clock divider output
process (clr, clk)
begin
if (clr = '1') then
counter <= (others => '0');
ce16 <= '0';
elsif (rising_edge(clk)) then
if (counter >= baudLimit) then
counter <= counter - baudLimit;
ce16 <= '1';
else
counter <= counter + baudFreq;
ce16 <= '0';
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity heartbeat is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
heartbeat_out : out std_logic := '0';
avalon_regs_read : in std_logic := '0'; -- avalon_master.read
avalon_regs_write : in std_logic := '0'; -- .write
avalon_regs_waitrequest : out std_logic := '0'; -- .waitrequest
avalon_regs_address : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
avalon_regs_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
avalon_regs_readdata : out std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avalon_regs_readdatavalid : out std_logic := '0' -- .readdatavalid
);
end entity heartbeat;
architecture rtl of heartbeat is
signal heartbeat_counter : unsigned(31 downto 0) := (others => '0');
signal heartbeat_counter_logic : std_logic_vector(31 downto 0) := (others => '0');
signal heartbeat_divider : unsigned(4 downto 0) := to_unsigned(27,5); --initial division is 2^27 = 0.86Hz
signal heartbeat_divider_16 : std_logic_vector(15 downto 0) := (others => '0');
signal heartbeat_divider_int : integer range 31 downto 0 := 27;
signal heartbeat_force_flag : std_logic := '0';
signal heartbeat_force_value : std_logic := '0';
begin
heartbeat_divider_16 <= std_logic_vector(resize(heartbeat_divider,16));
heartbeat_divider_int <= to_integer(heartbeat_divider);
heartbeat_counter_logic <= std_logic_vector(heartbeat_counter);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_regs_readdatavalid <= '0';
if avalon_regs_read = '1' then
avalon_regs_readdatavalid <= '1';
case avalon_regs_address(7 downto 0) is
when X"00" =>
avalon_regs_readdata <= heartbeat_divider_16;
when X"04" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(15 downto 0));
when X"06" =>
avalon_regs_readdata <= std_logic_vector(heartbeat_counter(31 downto 16));
when others =>
avalon_regs_readdata <= X"0000";
end case;
end if;
end if;
end process;
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
if avalon_regs_write= '1' then
case avalon_regs_address(7 downto 0) is
when X"00" =>
heartbeat_divider <= unsigned(avalon_regs_writedata(4 downto 0));
heartbeat_force_value <= avalon_regs_writedata(6);
heartbeat_force_flag <= avalon_regs_writedata(7);
when others =>
null;
end case;
end if;
end if;
end process;
--Avalon regs interface is only regs, so always ready to write.
avalon_regs_waitrequest <= '0';
--Counter
heartbeat_counter <= heartbeat_counter + 1 when rising_edge(clock);
--Heartbeat selector
process (clock)
begin
if rising_edge(clock) then
if heartbeat_force_flag = '1' then
heartbeat_out <= heartbeat_force_value;
else
case heartbeat_divider_int is
when 21 =>
heartbeat_out <= heartbeat_counter_logic(20); -- 54 Hz
when 22 =>
heartbeat_out <= heartbeat_counter_logic(21); -- 28 Hz
when 23 =>
heartbeat_out <= heartbeat_counter_logic(22); -- 14 Hz
when 24 =>
heartbeat_out <= heartbeat_counter_logic(23); -- 7 Hz
when 25 =>
heartbeat_out <= heartbeat_counter_logic(24); --3.2 Hz
when 26 =>
heartbeat_out <= heartbeat_counter_logic(25); --1.6 Hz
when 27 =>
heartbeat_out <= heartbeat_counter_logic(26); --0.8 Hz
when 28 =>
heartbeat_out <= heartbeat_counter_logic(27);
when 29 =>
heartbeat_out <= heartbeat_counter_logic(28);
when 30 =>
heartbeat_out <= heartbeat_counter_logic(29);
when 31 =>
heartbeat_out <= heartbeat_counter_logic(30);
when others =>
heartbeat_out <= heartbeat_counter_logic(26);
end case;
end if;
end if;
end process;
end architecture rtl; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1750.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p21n01i01750ent IS
generic (g1: integer := 12);
port (
input1: in bit ;
input2: in bit ;
clk : in boolean;
output: out bit);
END c09s05b00x00p21n01i01750ent;
ARCHITECTURE c09s05b00x00p21n01i01750arch OF c09s05b00x00p21n01i01750ent IS
type boolvec is array (positive range <>) of boolean;
function F (BB: boolvec) return boolean is
begin
return TRUE;
end;
signal i : F boolean bus;
signal k : boolean ;
BEGIN
i <= transport k; -- Failure_here
-- i is a guarded target while the statement is not a guarded assignment
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p21n01i01750 - Ungarded signal can not assign to a guarded signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p21n01i01750arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1750.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p21n01i01750ent IS
generic (g1: integer := 12);
port (
input1: in bit ;
input2: in bit ;
clk : in boolean;
output: out bit);
END c09s05b00x00p21n01i01750ent;
ARCHITECTURE c09s05b00x00p21n01i01750arch OF c09s05b00x00p21n01i01750ent IS
type boolvec is array (positive range <>) of boolean;
function F (BB: boolvec) return boolean is
begin
return TRUE;
end;
signal i : F boolean bus;
signal k : boolean ;
BEGIN
i <= transport k; -- Failure_here
-- i is a guarded target while the statement is not a guarded assignment
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p21n01i01750 - Ungarded signal can not assign to a guarded signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p21n01i01750arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1750.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b00x00p21n01i01750ent IS
generic (g1: integer := 12);
port (
input1: in bit ;
input2: in bit ;
clk : in boolean;
output: out bit);
END c09s05b00x00p21n01i01750ent;
ARCHITECTURE c09s05b00x00p21n01i01750arch OF c09s05b00x00p21n01i01750ent IS
type boolvec is array (positive range <>) of boolean;
function F (BB: boolvec) return boolean is
begin
return TRUE;
end;
signal i : F boolean bus;
signal k : boolean ;
BEGIN
i <= transport k; -- Failure_here
-- i is a guarded target while the statement is not a guarded assignment
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b00x00p21n01i01750 - Ungarded signal can not assign to a guarded signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b00x00p21n01i01750arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_10_2 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_10_2;
ARCHITECTURE sys_router_10_2_arch OF sys_router_10_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_10_2_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_router_10_2_arch: ARCHITECTURE IS "router_struct,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_router_10_2_arch : ARCHITECTURE IS "sys_router_10_2,router_struct,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 2,
ADDR_Y => 0,
N_INST => true,
S_INST => false,
E_INST => false,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_VIN => '0',
S_ROUT => '0',
E_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
E_VIN => '0',
E_ROUT => '0',
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_10_2_arch;
|
----------------------------------------------------------------------------------
-- Engineer: Longofono
--
-- Create Date: 11/27/2017 09:05:36 AM
-- Module Name: tb_regfile - Behavioral
-- Description:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity tb_regfile is
-- Port ( );
end tb_regfile;
architecture Behavioral of tb_regfile is
-- Component declarations
component regfile is
port(
clk: in std_logic;
rst: in std_logic;
read_addr_1: in std_logic_vector(4 downto 0); -- Register source read_data_1
read_addr_2: in std_logic_vector(4 downto 0); -- Register source read_data_2
write_addr: in std_logic_vector(4 downto 0); -- Write dest write_data
write_data: in doubleword; -- Data to be written
halt: in std_logic; -- Control, do nothing on high
write_en: in std_logic; -- write_data is valid
read_data_1: out doubleword; -- Data from read_addr_1
read_data_2: out doubleword; -- Data from read_addr_2
write_error: out std_logic; -- Writing to constant, HW exception
debug_out: out regfile_arr -- Copy of regfile contents for debugger
);
end component;
-- Signals and constants
constant t_per: time := 1 ns;
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal ra1: std_logic_vector(4 downto 0) := "00000";
signal ra2: std_logic_vector(4 downto 0) := "00000";
signal wa: std_logic_vector(4 downto 0) := "00000";
signal halt: std_logic := '0';
signal write_en: std_logic := '0';
signal rd1: doubleword;
signal rd2:doubleword;
signal wd: doubleword := (others => '0');
signal write_error: std_logic;
signal debug: regfile_arr;
begin
-- Instantiation
myReg: regfile
port map(
clk => clk,
rst => rst,
read_addr_1 => ra1,
read_addr_2 => ra2,
write_addr => wa,
write_data => wd,
halt => halt,
write_en => write_en,
read_data_1 => rd1,
read_data_2 => rd2,
write_error => write_error,
debug_out => debug
);
-- Clock generation
tiktok: process
begin
clk <= '0';
wait for t_per/2;
clk <= '1';
wait for t_per/2;
end process;
main: process
begin
-- Settling
wait for t_per;
-- Test error condition
wd <= (others => '1');
wa <= "00000";
write_en <= '1';
rst <= '0';
wait for t_per;
-- Test simple write and read (RAW test)
ra1 <= "00001";
ra2 <= "00010";
wa <= "00001";
write_en <= '1';
wd <= (others => '1');
wait for t_per;
-- Test write to all valid writeable registers
for I in 1 to 32 loop
wa <= std_logic_vector(to_unsigned(I, 5));
wd <= (others => '1');
write_en <= '1';
wait for t_per;
end loop;
-- Test reset
rst <= '1';
wa <= "00001";
wait for t_per;
-- Test halt
rst <= '0';
halt <= '1';
wa <= "00001";
wd <= (others => '1');
wait for t_per;
-- Test resume
halt <= '0';
wa <= "00001";
wd <= (others => '1');
wait for t_per;
wait;
end process;
end Behavioral;
|
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F92N91ec5pdpt+qcFZLDczLg
`protect end_protected
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_15.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_15
-- Source Path: hdl_ofdm_tx/ifft/TWDLROM_3_15
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY TWDLROM_3_15 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_vld : OUT std_logic
);
END TWDLROM_3_15;
ARCHITECTURE rtl OF TWDLROM_3_15 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE addr_cast : unsigned(3 DOWNTO 0);
VARIABLE c : unsigned(1 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt;
Radix22TwdlMapping_phase_next <= Radix22TwdlMapping_phase;
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
c := unsigned'(Radix22TwdlMapping_cnt(0) & Radix22TwdlMapping_cnt(1));
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4) sll 1;
ELSE
addr_cast := resize(c, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (addr_cast sll 1) + addr_cast;
END IF;
IF dout_2_vld = '1' THEN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000004#, 2);
END IF;
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_15_re_tmp <= twdlIn_re;
twdl_3_15_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_15_re <= std_logic_vector(twdl_3_15_re_tmp);
twdl_3_15_im <= std_logic_vector(twdl_3_15_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_15_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_15_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
package assert_after_missing_type is
end package;
package body assert_after_missing_type is
procedure proc(var : type_t) is
begin
end;
procedure calling_proc is
begin
proc(1); -- Error (used to cause SIGABRT)
end;
end package body;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: moore_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity moore_t is
end entity;
architecture arch_moore_t of moore_t is
component moore is
port (d, clk, reset: in std_logic;
z: out std_logic);
end component moore;
signal data: std_logic_vector(0 to 9) := "1100010110";
signal clk, r, d, z: std_logic := '0';
signal clk_t: std_logic := '0';
for all:moore use entity work.moore(arch_moore);
begin
m : moore port map (d, clk, r, z);
clk <= not clk after 50 ns;
clk_t <= not clk_t after 40 ns;
process (clk_t)
variable i : natural := 0;
begin
if clk_t = '1' and clk_t'event then
d <= data(i);
i := i + 1;
end if;
end process;
end architecture arch_moore_t;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Alessandro Salvato
--
-- Create Date: 12:09:40 05/18/2017
-- Design Name:
-- Module Name: ControlUnit_FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.myTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ControlUnit_FSM is
--trs iofk
generic (
MICROCODE_MEM_LENGHT : integer := 19;
CW_SIZE : integer := 13; --ciao emanuele
--questa riga essere bastarda
ALU_nWIRE_OP : integer := 2); --malvagita al massimo
-- non ne parliamo proprio
--cena
port (
Clk : in std_logic;
Rst : in std_logic;
OPCODE : in std_logic_vector(OP_CODE_SIZE - 1 downto 0);
FUNC : in std_logic_vector(FUNC_SIZE - 1 downto 0);
EN1 : out std_logic;
RF1 : out std_logic;
RF2 : out std_logic; --sono felice
-- che rumore fa la happiness
--terza riga di commento
WF1 : out std_logic; --NO
EN2 : out std_logic;
S1 : out std_logic;
S2 : out std_logic;
EN3 : out std_logic;
RM : out std_logic;
WM : out std_logic; -- write in of memory enable
S3 : out std_logic;
ALU : out std_logic_vector(ALU_nWIRE_OP -1 downto 0) ); -- ma se io scrivo qui?
--e poi qui?
--ALESSANDRO
end ControlUnit_FSM;
architecture Behavioral of ControlUnit_FSM is
type State is (RESET, DECODE, EXEC_I, EXEC_R, MEMORY_I, WB, WAIT1, WAIT2);
signal CurrentState, NextState : State;
signal cw : std_logic_vector(CW_SIZE-1 downto 0);
begin
state_process: process(clk, rst)
begin
if(rst='0') then --asyncronous reset
CurrentState <= RESET;
elsif(clk = '1') then
CurrentState <= NextState;
end if;
end process;
combinational_process: process(CurrentState)
begin
case CurrentState is
WHEN RESET => cw <= (others => '0');
NextState <= DECODE;
WHEN DECODE =>
cw(CW_SIZE-5 downto 0) <= (others => '0');
if(OPCODE = RTYPE) then
NextState <= EXEC_R;
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1101";
else
case OPCODE is
when ITYPE_ADDI1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0101";
NextState <= EXEC_I;
when ITYPE_SUBI1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0101";
NextState <= EXEC_I;
when ITYPE_ANDI1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0101";
NextState <= EXEC_I;
when ITYPE_ORI1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0101";
NextState <= EXEC_I;
when ITYPE_ADDI2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when ITYPE_SUBI2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when ITYPE_ANDI2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when ITYPE_ORI2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when ITYPE_MOV =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when ITYPE_S_REG1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0001";
NextState <= EXEC_I;
when ITYPE_S_REG2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0001";
NextState <= EXEC_I;
when ITYPE_S_MEM2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1101";
NextState <= EXEC_I;
when ITYPE_L_MEM1 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "0101";
NextState <= EXEC_I;
when ITYPE_L_MEM2 =>
cw(CW_SIZE-1 downto CW_SIZE-4) <= "1001";
NextState <= EXEC_I;
when others => NextState <= WAIT2;
cw <= (others => '0');
end case;
end if;
WHEN EXEC_I => case OPCODE is
when ITYPE_ADDI1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when ITYPE_SUBI1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "011";
NextState <= WB;
when ITYPE_ANDI1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "101";
NextState <= WB;
when ITYPE_ORI1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "111";
NextState <= WB;
when ITYPE_ADDI2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when ITYPE_SUBI2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "011";
NextState <= WB;
when ITYPE_ANDI2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "101";
NextState <= WB;
when ITYPE_ORI2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "111";
NextState <= WB;
when ITYPE_MOV =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when ITYPE_S_REG1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when ITYPE_S_REG2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when ITYPE_S_MEM2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= MEMORY_I;
when ITYPE_L_MEM1 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "00";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= MEMORY_I;
when ITYPE_L_MEM2 =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "11";
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= MEMORY_I;
when others => cw <= (others => '0');
NextState <= WAIT1;
end case;
WHEN EXEC_R =>
cw(CW_SIZE-5 downto CW_SIZE-6) <= "10"; --control signals for muxs
case FUNC is
when RTYPE_ADD =>
cw(CW_SIZE-7 downto CW_SIZE-9) <= "001";
NextState <= WB;
when RTYPE_SUB =>
cw(CW_SIZE-7 downto CW_SIZE-9) <= "011";
NextState <= WB;
when RTYPE_AND =>
cw(CW_SIZE-7 downto CW_SIZE-9) <= "101";
NextState <= WB;
when RTYPE_OR =>
cw(CW_SIZE-7 downto CW_SIZE-9) <= "111";
NextState <= WB;
-- when NOP =>
-- cw(CW_SIZE-7 downto CW_SIZE-9) <= "000";
-- NextState <= WB;
-- --alu output register disabled
when others =>
cw(CW_SIZE-7 downto CW_SIZE-9) <= "000";
NextState <= WAIT1;
--same behaviour NOP
end case;
WHEN MEMORY_I =>
cw(CW_SIZE-1 downto CW_SIZE-2) <= (others => '0');
cw(CW_SIZE-4 downto CW_SIZE-9) <= (others => '0');
case OPCODE is
when ITYPE_S_MEM2 =>
cw(CW_SIZE-10 downto CW_SIZE-13) <= "0110";
cw(CW_SIZE-3) <= '0';
NextState <= DECODE;
when ITYPE_L_MEM1 =>
cw(CW_SIZE-10 downto CW_SIZE-13) <= "1010";
cw(CW_SIZE-3) <= '1';
NextState <= DECODE;
when ITYPE_L_MEM2 =>
cw(CW_SIZE-10 downto CW_SIZE-13) <= "1010";
cw(CW_SIZE-3) <= '1';
NextState <= DECODE;
when others =>
cw(CW_SIZE-10 downto CW_SIZE-13) <= "0000";
cw(CW_SIZE-3) <= '0';
NextState <= DECODE;
end case;
WHEN WB =>
cw(CW_SIZE-10 downto CW_SIZE-13) <= "0001";
cw(CW_SIZE-3) <= '1';
cw(CW_SIZE-1 downto CW_SIZE-2) <= (others => '0');
cw(CW_SIZE-4 downto CW_SIZE-9) <= (others => '0');
NextState <= DECODE;
WHEN WAIT2 =>
NextState <= WAIT1;
WHEN WAIT1 =>
NextState <= DECODE;
WHEN OTHERS =>
cw <= (others => '0');
NextState <= DECODE;
end case;
end process;
RF1 <= cw(CW_SIZE-1);
RF2 <= cw(CW_SIZE-2);
WF1 <= cw(CW_SIZE-3);
EN1 <= cw(CW_SIZE-4);
S1 <= cw(CW_SIZE-5);
S2 <= cw(CW_SIZE-6);
ALU(1) <= cw(CW_SIZE-7);
ALU(0) <= cw(CW_SIZE-8);
EN2 <= cw(CW_SIZE-9);
RM <= cw(CW_SIZE-10);
WM <= cw(CW_SIZE-11);
EN3 <= cw(CW_SIZE-12);
S3 <= cw(CW_SIZE-13);
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1488_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1488_hot;
architecture behaviour of s1488_hot is
constant s000000: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant s001110: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant s011000: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant s010000: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant s010100: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant s110011: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant s010011: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant s000100: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant s100011: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant s010110: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant s010111: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant s000111: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant s101011: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant s001111: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant s111100: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant s101100: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant s001100: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant s010001: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant s011011: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant s110110: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant s011111: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant s101110: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant s010101: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant s111110: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant s000011: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant s111010: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant s011010: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant s111011: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant s100000: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant s101000: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant s110000: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant s011110: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant s010010: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant s001010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant s000010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant s111000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant s100100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant s001000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant s001011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant s110100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant s100110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant s011101: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant s000110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant s110010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant s011100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant s101010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant s100010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant s100111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-11----") then next_state <= s000000; output <= "0100011010010010111";
elsif std_match(input, "0-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0100011010010010111";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "0000000011000100000";
elsif std_match(input, "--00----") then next_state <= s000000; output <= "0000000010000110000";
elsif std_match(input, "--10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "00------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0010100010001110000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---0---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000001010001010000";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "0010100010001110000";
end if;
when s011000 =>
if std_match(input, "0-10-010") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000010000000000101";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000010000000000100";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000011000011011101";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "0000000000001111101";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "0000000000001111100";
elsif std_match(input, "0-00-000") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "0000010001001101101";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "0000010001001101100";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "0-----01") then next_state <= s000000; output <= "0000001100111010011";
elsif std_match(input, "0-----11") then next_state <= s000000; output <= "0000001100111010010";
elsif std_match(input, "1-----11") then next_state <= s010100; output <= "0000001100111010010";
elsif std_match(input, "1-----01") then next_state <= s010100; output <= "0000001100111010011";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "0000010001001101101";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "0000010001001101100";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "0000010001001101001";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "0000010001001101000";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000011000011011101";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "0000000000001111101";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "0000000000001111100";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "0000000000001111001";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "0000000000001111000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000010000000000001";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000010000000000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000010000000000100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000010000000000101";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000001010001010000";
end if;
when s010011 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0000001010000110011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0000001010000110111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010000110111";
end if;
when s000100 =>
if std_match(input, "11---01-") then next_state <= s100011; output <= "0000001010001010000";
elsif std_match(input, "01---01-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "01---11-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10----1-") then next_state <= s010111; output <= "0000001010001010000";
elsif std_match(input, "00----1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0-----0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000001010001010000";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000001000011011001";
end if;
when s110011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s000111; output <= "0000001010001010000";
end if;
when s000111 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000001000011011110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000001000011011010";
end if;
when s101011 =>
if std_match(input, "1-------") then next_state <= s001111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s001111 =>
if std_match(input, "1----0--") then next_state <= s000100; output <= "0001000000101011011";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "0001000000101011111";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000101011111";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001000000101011011";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0100001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "0000010001001101000";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "0000000000001111000";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000010000000000000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010010010111";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "0000010001001101000";
end if;
when s111100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "1-------") then next_state <= s100011; output <= "0000001110001010000";
end if;
when s101100 =>
if std_match(input, "1-------") then next_state <= s010110; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010111 =>
if std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000110010010";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000000110010110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110010010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000110010110";
end if;
when s001100 =>
if std_match(input, "1----0--") then next_state <= s010001; output <= "0000001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010001 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011110111";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "0000001000011110111";
elsif std_match(input, "1----0--") then next_state <= s110110; output <= "0000001000011110011";
end if;
when s110110 =>
if std_match(input, "1-------") then next_state <= s011111; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110111111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110111110";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110111010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110111011";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110111010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110111011";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110111110";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110111111";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010101 =>
if std_match(input, "1----1--") then next_state <= s111110; output <= "0000001000001111101";
elsif std_match(input, "1----0--") then next_state <= s111110; output <= "0000001000001111001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000001111101";
end if;
when s111110 =>
if std_match(input, "00--1-0-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "01--1-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-0-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "1000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "10--1--1") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "10--1--0") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--1-11") then next_state <= s111010; output <= "1000001010001010000";
elsif std_match(input, "11--0-11") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-10") then next_state <= s011010; output <= "1000001010001010000";
elsif std_match(input, "11--0-10") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "11--1-01") then next_state <= s000011; output <= "0000001010001010000";
elsif std_match(input, "11--0-0-") then next_state <= s000011; output <= "0000001010001010000";
end if;
when s000011 =>
if std_match(input, "1----0-1") then next_state <= s001110; output <= "0000001010010010011";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "0000001010010110011";
elsif std_match(input, "1----1--") then next_state <= s001110; output <= "0000001010010010111";
elsif std_match(input, "0----0-1") then next_state <= s000000; output <= "0000001010010010011";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000001010010010011";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010010010011";
end if;
when s100000 =>
if std_match(input, "00--1---") then next_state <= s000000; output <= "0000101010001010000";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "11--1---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000101010001010000";
elsif std_match(input, "11--0---") then next_state <= s101000; output <= "0000001110001010000";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000001110001010000";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000001010001010000";
end if;
when s101000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010000110011";
elsif std_match(input, "1-------") then next_state <= s010010; output <= "0000001010000110011";
end if;
when s010010 =>
if std_match(input, "1---0---") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0---0---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0---1---") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000001010001010000";
end if;
when s011110 =>
if std_match(input, "0-00-00-") then next_state <= s000000; output <= "0000000000001111000";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "0000000000001111001";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000010000000000001";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000010000000000000";
elsif std_match(input, "0--0-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0--1-1--") then next_state <= s000000; output <= "0000001010010010111";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000011000011011001";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "0000010001001101000";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "0000010001001101001";
elsif std_match(input, "1-0--1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "0000000000001111000";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "0000000000001111001";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "0000010001001101001";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "0000010001001101000";
elsif std_match(input, "1-10-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000010000000000001";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000010000000000000";
elsif std_match(input, "1-11-1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000011000011011001";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0001001010001010000";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001010 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000001010100010001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
end if;
when s111000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000001010001010000";
elsif std_match(input, "1---00--") then next_state <= s001000; output <= "0000001010001010000";
elsif std_match(input, "1---1---") then next_state <= s001000; output <= "0000001010001010000";
end if;
when s001000 =>
if std_match(input, "1----0--") then next_state <= s100100; output <= "0000001000011011001";
elsif std_match(input, "1----1--") then next_state <= s100100; output <= "0000001000011011101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011101";
end if;
when s100100 =>
if std_match(input, "1-------") then next_state <= s001011; output <= "0001001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
end if;
when s001011 =>
if std_match(input, "1----0--") then next_state <= s110100; output <= "0000001000011011010";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000001000011011110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001000011011010";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001000011011110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0001001010001010000";
end if;
when s011011 =>
if std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000011010111";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000011010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000011010010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000011010011";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000001000011010010";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000001000011010011";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000001000011010110";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000001000011010111";
end if;
when s100110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011101; output <= "0000001010001010000";
end if;
when s011101 =>
if std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110011000";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011001";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000000110011101";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000000110011100";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000000110011101";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000000110011100";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000110011000";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011001";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001000001111001";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "0000001000001111001";
end if;
when s000110 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0001001010001010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0100001010001010000";
elsif std_match(input, "1---01--") then next_state <= s011000; output <= "0100001010001010000";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0001001010001010000";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0100001010001010000";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0001001010001010000";
end if;
when s011010 =>
if std_match(input, "1----1--") then next_state <= s100000; output <= "0000001010010010111";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000001010100010001";
elsif std_match(input, "1----01-") then next_state <= s110010; output <= "0000001010100010000";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001010100010001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001010100010000";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000001010010010111";
end if;
when s110010 =>
if std_match(input, "1----00-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000001010001010000";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s011100 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000001000111010111";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000001000111010110";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000001000111010011";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000001000111010010";
elsif std_match(input, "1----10-") then next_state <= s101010; output <= "0000001000111010110";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000001000111010111";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000001000111010011";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000001000111010010";
end if;
when s101010 =>
if std_match(input, "1-------") then next_state <= s111010; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s100010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
elsif std_match(input, "1-------") then next_state <= s011010; output <= "0000001010001010000";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "0000001010010110011";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000001010010110011";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010101010010010111";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0010101010010010111";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000001010001010000";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000001010001010000";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000001000011010010";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
-- ======================================================================
-- AES Counter mode testbench
-- Copyright (C) 2020 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use std.env.all;
entity tb_ctraes is
end entity tb_ctraes;
architecture sim of tb_ctraes is
constant C_NONCE_WIDTH : natural range 64 to 96 := 96;
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_start : std_logic := '0';
signal s_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1) := (others => '0');
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptin : std_logic;
signal s_dataout : std_logic_vector(0 to 127);
signal s_validout : std_logic := '0';
signal s_acceptout : std_logic := '0';
procedure cryptData(datain : in std_logic_vector(0 to 127);
key : in std_logic_vector(0 to 127);
iv : in std_logic_vector(0 to 127);
start : in boolean;
final : in boolean;
dataout : out std_logic_vector(0 to 127);
bytelen : in integer) is
begin
report "VHPIDIRECT cryptData" severity failure;
end procedure;
attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
variable v_data : std_logic_vector(0 to 127);
begin
for i in 0 to 15 loop
for y in 0 to 7 loop
v_data((i*8)+y) := datain((i*8)+7-y);
end loop;
end loop;
return v_data;
end function;
begin
i_ctraes : entity work.ctraes
generic map (
NONCE_WIDTH => C_NONCE_WIDTH
)
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
nonce_i => s_nonce,
key_i => s_key,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptin,
data_o => s_dataout,
valid_o => s_validout,
accept_i => s_acceptout
);
s_clk <= not(s_clk) after 10 ns;
s_reset <= '1' after 100 ns;
process is
variable v_key : std_logic_vector(0 to 127);
variable v_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1);
variable v_datain : std_logic_vector(0 to 127);
variable v_dataout : std_logic_vector(0 to 127);
variable v_random : RandomPType;
begin
v_random.InitSeed(v_random'instance_name);
wait until s_reset = '1' and rising_edge(s_clk);
-- ENCRYPTION TESTs
report "Test CTR-AES encryption";
s_start <= '1';
v_nonce := v_random.RandSlv(s_nonce'length);
v_key := v_random.RandSlv(128);
for i in 0 to 31 loop
v_datain := v_random.RandSlv(128);
s_validin <= '1';
s_key <= v_key;
s_nonce <= v_nonce;
s_datain <= v_datain;
cryptData(swap(v_datain), swap(v_key), swap(v_nonce & 32x"0"), i = 0, i = 31, v_dataout, v_datain'length/8);
wait until s_acceptin = '1' and rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
wait until s_validout = '1' and rising_edge(s_clk);
s_acceptout <= '1';
assert s_dataout = swap(v_dataout)
report "Encryption error: Expected 0x" & to_hstring(swap(v_dataout)) & ", got 0x" & to_hstring(s_dataout)
severity failure;
wait until rising_edge(s_clk);
s_acceptout <= '0';
end loop;
-- Watchdog
wait for 100 ns;
report "Simulation finished without errors";
finish(0);
end process;
end architecture sim;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc327.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00327ent IS
END c03s02b01x00p04n01i00327ent;
ARCHITECTURE c03s02b01x00p04n01i00327arch OF c03s02b01x00p04n01i00327ent IS
-- Failure_here: bad index format; need ranges, not constants.
type er1 is array(5,2) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00327 - The index constraint in the constrained array definition is invalid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00327arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc327.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00327ent IS
END c03s02b01x00p04n01i00327ent;
ARCHITECTURE c03s02b01x00p04n01i00327arch OF c03s02b01x00p04n01i00327ent IS
-- Failure_here: bad index format; need ranges, not constants.
type er1 is array(5,2) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00327 - The index constraint in the constrained array definition is invalid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00327arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc327.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p04n01i00327ent IS
END c03s02b01x00p04n01i00327ent;
ARCHITECTURE c03s02b01x00p04n01i00327arch OF c03s02b01x00p04n01i00327ent IS
-- Failure_here: bad index format; need ranges, not constants.
type er1 is array(5,2) of integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x00p04n01i00327 - The index constraint in the constrained array definition is invalid."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p04n01i00327arch;
|
package issue_pkg is
type t_one_two is (one, two);
end package issue_pkg;
|
package issue_pkg is
type t_one_two is (one, two);
end package issue_pkg;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:16 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_sim_netlist.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
\s_axi_arready[0]\ : out STD_LOGIC;
aa_mi_arvalid : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_axi.read_cnt_reg[5]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
mi_arready_2 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC;
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_araddr[30]\ : in STD_LOGIC;
\s_axi_araddr[28]\ : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
\m_payload_i_reg[34]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \^gen_axi.s_axi_rid_i_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.s_axi_rlast_i_i_6_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_target_hot_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_valid_i_reg_0\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[16]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair6";
begin
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_axi.s_axi_rid_i_reg[11]\(0) <= \^gen_axi.s_axi_rid_i_reg[11]\(0);
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) <= \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0);
\gen_no_arbiter.m_valid_i_reg_0\ <= \^gen_no_arbiter.m_valid_i_reg_0\;
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => mi_arready_2,
I3 => p_15_in,
O => E(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \gen_axi.read_cnt_reg[5]\,
I1 => p_15_in,
I2 => \gen_axi.s_axi_rlast_i_i_6_n_0\,
I3 => \^m_axi_arqos[7]\(44),
I4 => \^m_axi_arqos[7]\(45),
I5 => \^m_axi_arqos[7]\(47),
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^m_axi_arqos[7]\(49),
I1 => p_15_in,
I2 => \^m_axi_arqos[7]\(48),
I3 => \^m_axi_arqos[7]\(46),
I4 => \^m_axi_arqos[7]\(51),
I5 => \^m_axi_arqos[7]\(50),
O => \gen_axi.s_axi_rlast_i_i_6_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\,
I1 => \m_payload_i_reg[34]\,
I2 => r_issuing_cnt(0),
I3 => r_issuing_cnt(1),
I4 => r_issuing_cnt(2),
I5 => r_issuing_cnt(3),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(3),
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(1),
I3 => r_issuing_cnt(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \m_payload_i_reg[34]\,
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(4),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I1 => \m_payload_i_reg[34]_0\,
I2 => r_issuing_cnt(4),
I3 => r_issuing_cnt(5),
I4 => r_issuing_cnt(6),
I5 => r_issuing_cnt(7),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => r_issuing_cnt(7),
I1 => r_issuing_cnt(6),
I2 => r_issuing_cnt(5),
I3 => r_issuing_cnt(4),
I4 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => aa_mi_artarget_hot(1),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080808080808080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
I2 => m_axi_arready(1),
I3 => s_axi_rready(0),
I4 => m_valid_i_reg,
I5 => Q(0),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => mi_arready_2,
I1 => \^gen_axi.s_axi_rid_i_reg[11]\(0),
I2 => \^aa_mi_arvalid\,
O => \^gen_no_arbiter.m_valid_i_reg_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[7]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[7]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[7]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[7]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[7]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[7]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[7]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[7]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[7]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[7]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[7]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[7]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[7]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[7]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[7]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[7]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[7]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[7]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[7]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[7]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[7]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[7]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[7]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[7]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[7]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[7]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[7]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[7]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[7]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[7]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[7]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[7]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[7]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[7]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[7]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[7]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[7]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[7]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[7]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[7]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[7]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[7]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[7]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[7]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[7]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[7]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[7]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[7]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[7]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[7]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[7]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[7]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[7]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[7]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[7]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[7]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[7]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[7]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[7]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[7]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[7]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[7]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[7]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[7]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[7]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[7]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[7]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[7]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[7]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \s_axi_arqos[3]\(33),
I1 => \s_axi_arqos[3]\(36),
I2 => \s_axi_araddr[30]\,
I3 => \s_axi_araddr[28]\,
I4 => \s_axi_araddr[25]\,
O => \^gen_no_arbiter.m_target_hot_i_reg[0]_0\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_artarget_hot(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => aa_mi_artarget_hot(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^gen_axi.s_axi_rid_i_reg[11]\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000002A"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0\,
I4 => \^gen_no_arbiter.m_valid_i_reg_0\,
I5 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFEFFFEFFFFF"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I1 => \^aa_mi_arvalid\,
I2 => s_axi_arvalid(0),
I3 => \^s_axi_arready[0]\,
I4 => \chosen_reg[0]\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\,
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^s_axi_arready[0]\,
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(1),
O => m_axi_arvalid(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
aa_mi_awtarget_hot : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].w_issuing_cnt_reg[9]\ : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
st_aa_awtarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 7 downto 0 );
\chosen_reg[1]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[0]\ : in STD_LOGIC;
mi_awready_2 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC;
\s_axi_awaddr[20]\ : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^aa_mi_awtarget_hot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \^gen_master_slots[1].w_issuing_cnt_reg[9]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal \^st_aa_awtarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[9]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_4\ : label is "soft_lutpair12";
begin
aa_mi_awtarget_hot(2 downto 0) <= \^aa_mi_awtarget_hot\(2 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
\gen_master_slots[1].w_issuing_cnt_reg[9]\ <= \^gen_master_slots[1].w_issuing_cnt_reg[9]\;
\m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\;
ss_aa_awready <= \^ss_aa_awready\;
st_aa_awtarget_hot(0) <= \^st_aa_awtarget_hot\(0);
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(2),
I3 => mi_awready_2,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \chosen_reg[0]\,
I2 => m_axi_awready(0),
I3 => \^aa_mi_awtarget_hot\(0),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\,
I1 => w_issuing_cnt(3),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(2),
I4 => w_issuing_cnt(1),
I5 => \chosen_reg[0]\,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(3),
I1 => w_issuing_cnt(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(0),
I3 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \chosen_reg[0]\,
I1 => m_axi_awready(0),
I2 => \^aa_mi_awtarget_hot\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(1),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA55555554"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\,
I1 => w_issuing_cnt(7),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(6),
I4 => w_issuing_cnt(5),
I5 => \chosen_reg[1]\,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => w_issuing_cnt(7),
I1 => w_issuing_cnt(4),
I2 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_ready_d(1),
I1 => \^aa_sa_awvalid\,
I2 => \^aa_mi_awtarget_hot\(1),
I3 => m_axi_awready(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => m_valid_i_reg,
I1 => s_axi_bready(0),
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_sa_awvalid\,
I5 => m_ready_d(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA95555555"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \chosen_reg[1]\,
I2 => m_axi_awready(1),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^gen_master_slots[1].w_issuing_cnt_reg[9]\,
I5 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[1].w_issuing_cnt[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => m_ready_d(1),
O => \^gen_master_slots[1].w_issuing_cnt_reg[9]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\,
I1 => \s_axi_awaddr[26]\,
I2 => \s_axi_awaddr[20]\,
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
O => \^st_aa_awtarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(31),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(39),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => Q(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => Q(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => Q(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => Q(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => Q(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => Q(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => Q(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => Q(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => Q(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => Q(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => Q(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => Q(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => Q(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => Q(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => Q(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => Q(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => Q(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => Q(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => Q(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => Q(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => Q(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => Q(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => Q(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => Q(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => Q(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => Q(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => Q(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => Q(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => Q(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => Q(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => Q(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => Q(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => Q(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => Q(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => Q(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => Q(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => Q(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => Q(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => Q(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => Q(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => Q(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => Q(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => Q(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => Q(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => Q(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => Q(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => Q(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => Q(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => Q(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => Q(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => Q(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => Q(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => Q(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => Q(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => Q(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => Q(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => Q(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => Q(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => Q(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => Q(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => Q(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => Q(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => Q(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => Q(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => Q(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => Q(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => Q(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => Q(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => Q(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => \^st_aa_awtarget_hot\(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(0),
O => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => m_valid_i,
I2 => aresetn_d,
I3 => \^aa_mi_awtarget_hot\(1),
O => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0\,
Q => \^aa_mi_awtarget_hot\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg_0,
Q => \^aa_mi_awtarget_hot\(2),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F2"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I2 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => m_ready_d(0),
I4 => \^m_ready_d_reg[1]\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^ss_aa_awready\,
I1 => m_ready_d_0(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg,
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(0),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^aa_mi_awtarget_hot\(1),
I1 => m_ready_d(1),
I2 => \^aa_sa_awvalid\,
O => m_axi_awvalid(1)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555554FFFFFFFF"
)
port map (
I0 => \^m_ready_d_reg[1]\,
I1 => m_ready_d(0),
I2 => \^aa_mi_awtarget_hot\(2),
I3 => \^aa_mi_awtarget_hot\(1),
I4 => \^aa_mi_awtarget_hot\(0),
I5 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_mi_awtarget_hot\(2),
I2 => \^aa_mi_awtarget_hot\(1),
I3 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000777"
)
port map (
I0 => m_axi_awready(1),
I1 => \^aa_mi_awtarget_hot\(1),
I2 => mi_awready_2,
I3 => \^aa_mi_awtarget_hot\(2),
I4 => \m_ready_d[1]_i_4_n_0\,
I5 => m_ready_d(1),
O => \^m_ready_d_reg[1]\
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_axi_awready(0),
I1 => \^aa_mi_awtarget_hot\(0),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
\chosen_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : out STD_LOGIC;
aresetn_d : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ : in STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_5\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \chosen[0]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1__0_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1__0_n_0\ : STD_LOGIC;
signal \^chosen_reg[0]_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_master_slots[0].w_issuing_cnt_reg[1]\ : STD_LOGIC;
signal \^gen_master_slots[2].w_issuing_cnt_reg[16]\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_6_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \chosen[2]_i_1__0\ : label is "soft_lutpair112";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_6\ : label is "soft_lutpair111";
begin
SR(0) <= \^sr\(0);
\chosen_reg[0]_0\ <= \^chosen_reg[0]_0\;
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[1]\;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ <= \^gen_master_slots[2].w_issuing_cnt_reg[16]\;
m_valid_i <= \^m_valid_i\;
\chosen[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^chosen_reg[0]_0\,
O => \chosen[0]_i_1__0_n_0\
);
\chosen[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1__0_n_0\
);
\chosen[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \chosen[2]_i_1__0_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1__0_n_0\,
Q => \^chosen_reg[0]_0\,
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1__0_n_0\,
Q => \^chosen_reg[1]_0\,
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1__0_n_0\,
Q => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
R => \^sr\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^chosen_reg[0]_0\,
I1 => p_80_out,
I2 => s_axi_bready(0),
O => \^gen_master_slots[0].w_issuing_cnt_reg[1]\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[1]_0\,
I2 => p_60_out,
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F7F00"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => s_axi_bready(0),
I3 => \m_ready_d_reg[1]_5\,
I4 => w_issuing_cnt(4),
O => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A956"
)
port map (
I0 => Q(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFF1100E"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFE00000000FFFF"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AAAAAAAA999A"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \m_ready_d_reg[1]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_4\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_3\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_2\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \m_ready_d_reg[1]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \m_ready_d_reg[1]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00AAAA80AA80AA80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^chosen_reg[0]_0\,
I2 => p_80_out,
I3 => m_valid_i_reg,
I4 => p_38_out,
I5 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"1FFF1000"
)
port map (
I0 => \s_axi_awaddr[26]\(0),
I1 => st_aa_awtarget_hot(0),
I2 => \^m_valid_i\,
I3 => aresetn_d,
I4 => aa_mi_awtarget_hot(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F022"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \s_axi_awaddr[26]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF40FFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0\,
I1 => Q(3),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => aa_sa_awvalid,
I4 => s_axi_awvalid(0),
I5 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => \^gen_master_slots[0].w_issuing_cnt_reg[1]\,
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(0),
I4 => w_issuing_cnt(3),
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEFEFAAEAEA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => st_aa_awtarget_hot(0),
I3 => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
I4 => \s_axi_awaddr[26]\(0),
I5 => \gen_master_slots[2].w_issuing_cnt_reg[16]_1\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1_n_0\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEE00000FEE"
)
port map (
I0 => p_60_out,
I1 => p_38_out,
I2 => \^chosen_reg[0]_0\,
I3 => p_80_out,
I4 => \last_rr_hot[2]_i_6_n_0\,
I5 => s_axi_bready(0),
O => need_arbitration
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_38_out,
I1 => p_60_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_80_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_60_out,
I1 => p_3_in,
I2 => p_80_out,
I3 => p_38_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_80_out,
I1 => p_4_in,
I2 => p_38_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_60_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot[2]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
O => \last_rr_hot[2]_i_6_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1_n_0\,
Q => p_3_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1_n_0\,
Q => p_4_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^gen_master_slots[2].w_issuing_cnt_reg[16]\,
I1 => p_38_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_60_out,
I4 => p_80_out,
I5 => \^chosen_reg[0]_0\,
O => s_axi_bvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.accept_cnt_reg[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]_0\ : out STD_LOGIC;
\m_payload_i_reg[34]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
cmd_push_3 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_3\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_4\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_5\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5 is
signal \chosen[0]_i_1_n_0\ : STD_LOGIC;
signal \chosen[1]_i_1_n_0\ : STD_LOGIC;
signal \chosen[2]_i_1_n_0\ : STD_LOGIC;
signal \^chosen_reg[1]_0\ : STD_LOGIC;
signal \^gen_multi_thread.accept_cnt_reg[2]\ : STD_LOGIC;
signal \i__carry_i_10_n_0\ : STD_LOGIC;
signal \i__carry_i_11_n_0\ : STD_LOGIC;
signal \i__carry_i_12_n_0\ : STD_LOGIC;
signal \i__carry_i_13_n_0\ : STD_LOGIC;
signal \i__carry_i_14_n_0\ : STD_LOGIC;
signal \i__carry_i_15_n_0\ : STD_LOGIC;
signal \i__carry_i_16_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_9_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_1__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[34]\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rid[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \chosen[0]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \chosen[2]_i_1\ : label is "soft_lutpair79";
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_2\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \s_axi_rid[11]_INST_0_i_3\ : label is "soft_lutpair78";
begin
\chosen_reg[1]_0\ <= \^chosen_reg[1]_0\;
\gen_multi_thread.accept_cnt_reg[2]\ <= \^gen_multi_thread.accept_cnt_reg[2]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i_reg[34]\ <= \^m_payload_i_reg[34]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\chosen[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(0),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[0]_0\,
O => \chosen[0]_i_1_n_0\
);
\chosen[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(1),
I1 => need_arbitration,
I2 => \^chosen_reg[1]_0\,
O => \chosen[1]_i_1_n_0\
);
\chosen[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => next_rr_hot(2),
I1 => need_arbitration,
I2 => \^m_payload_i_reg[34]\,
O => \chosen[2]_i_1_n_0\
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[0]_i_1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[1]_i_1_n_0\,
Q => \^chosen_reg[1]_0\,
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \chosen[2]_i_1_n_0\,
Q => \^m_payload_i_reg[34]\,
R => SR(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A659"
)
port map (
I0 => Q(0),
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFF4400B"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[2]\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => Q(1),
I3 => Q(2),
I4 => \^gen_multi_thread.accept_cnt_reg[2]\,
I5 => \gen_no_arbiter.s_ready_i_reg[0]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAA9A99"
)
port map (
I0 => Q(3),
I1 => Q(0),
I2 => \^gen_multi_thread.accept_cnt_reg[2]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]\,
I4 => Q(1),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_0,
I1 => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_5\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_4\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => cmd_push_3,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\,
I2 => CO(0),
I3 => \^gen_multi_thread.accept_cnt_reg[2]\,
O => E(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_3\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5955"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_2\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \^gen_multi_thread.accept_cnt_reg[2]\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8880000"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => s_axi_rready(0),
O => \^gen_multi_thread.accept_cnt_reg[2]\
);
\i__carry_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(9),
I2 => \m_payload_i_reg[46]_0\(22),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(22),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_10_n_0\
);
\i__carry_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(5),
I2 => \m_payload_i_reg[46]_0\(18),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(18),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_11_n_0\
);
\i__carry_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(17),
I2 => \m_payload_i_reg[46]_1\(4),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]_0\(17),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_12_n_0\
);
\i__carry_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(19),
I2 => \m_payload_i_reg[46]_1\(6),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(19),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_13_n_0\
);
\i__carry_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(2),
I2 => \m_payload_i_reg[46]_0\(15),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(15),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_14_n_0\
);
\i__carry_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(14),
I2 => \m_payload_i_reg[46]_1\(1),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(14),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_15_n_0\
);
\i__carry_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(3),
I2 => \m_payload_i_reg[46]_0\(16),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(16),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_16_n_0\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0)
);
\i__carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(11),
I2 => \m_payload_i_reg[46]\(24),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(24),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \i__carry_i_5_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(23),
I2 => \m_payload_i_reg[46]_1\(10),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(23),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_6_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(25),
I2 => \m_payload_i_reg[46]_1\(12),
I3 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I4 => \m_payload_i_reg[46]\(25),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_7_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(8),
I2 => \m_payload_i_reg[46]_0\(21),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(21),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_8_n_0\
);
\i__carry_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB0BBB0B0000BB0B"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(7),
I2 => \m_payload_i_reg[46]_0\(20),
I3 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I4 => \m_payload_i_reg[46]\(20),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => \i__carry_i_9_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF57AA00"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[0]_i_1__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F5F7A0A0"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_3_in,
O => \last_rr_hot[1]_i_1__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDF8888"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(2),
I2 => next_rr_hot(1),
I3 => next_rr_hot(0),
I4 => p_4_in,
O => \last_rr_hot[2]_i_1__0_n_0\
);
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBABBBABBBAB88"
)
port map (
I0 => s_axi_rready(0),
I1 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I2 => \^m_payload_i_reg[0]_0\,
I3 => p_74_out,
I4 => p_54_out,
I5 => p_32_out,
O => need_arbitration
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA20222020"
)
port map (
I0 => p_32_out,
I1 => p_54_out,
I2 => \last_rr_hot_reg_n_0_[0]\,
I3 => p_74_out,
I4 => p_4_in,
I5 => p_3_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0A0A0008"
)
port map (
I0 => p_54_out,
I1 => p_3_in,
I2 => p_74_out,
I3 => p_32_out,
I4 => p_4_in,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(1)
);
\last_rr_hot[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A8A8A8A88888A88"
)
port map (
I0 => p_74_out,
I1 => p_4_in,
I2 => p_32_out,
I3 => \last_rr_hot_reg_n_0_[0]\,
I4 => p_54_out,
I5 => p_3_in,
O => next_rr_hot(0)
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[0]_i_1__0_n_0\,
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[1]_i_1__0_n_0\,
Q => p_3_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \last_rr_hot[2]_i_1__0_n_0\,
Q => p_4_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B3"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_74_out,
I2 => s_axi_rready(0),
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_rready(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
O => \m_payload_i_reg[34]_0\(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \i__carry_i_7_n_0\,
O => S(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \i__carry_i_10_n_0\,
O => S(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \i__carry_i_13_n_0\,
O => S(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \i__carry_i_16_n_0\,
O => S(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I3 => \i__carry_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \i__carry_i_7_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_8_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I3 => \i__carry_i_9_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \i__carry_i_10_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_11_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I3 => \i__carry_i_12_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \i__carry_i_13_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \i__carry_i_14_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I3 => \i__carry_i_15_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \i__carry_i_16_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(0),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(5),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(6),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(7),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(8),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(9),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(10),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(11),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(1),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(2),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(3),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F2A2A2A002A2A2A"
)
port map (
I0 => \m_payload_i_reg[46]\(4),
I1 => \^m_payload_i_reg[34]\,
I2 => p_32_out,
I3 => \^chosen_reg[1]_0\,
I4 => p_54_out,
I5 => \m_payload_i_reg[46]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(14),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(1),
I4 => \m_payload_i_reg[46]_0\(14),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(0)
);
\s_axi_rid[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(24),
I2 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I3 => \m_payload_i_reg[46]\(24),
I4 => \m_payload_i_reg[46]_1\(11),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(10)
);
\s_axi_rid[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(25),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(12),
I4 => \m_payload_i_reg[46]_0\(25),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(11)
);
\s_axi_rid[11]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_1_n_0\
);
\s_axi_rid[11]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^chosen_reg[1]_0\,
I1 => p_54_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_32_out,
O => \s_axi_rid[11]_INST_0_i_2_n_0\
);
\s_axi_rid[11]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8FFF"
)
port map (
I0 => \^m_payload_i_reg[34]\,
I1 => p_32_out,
I2 => \^chosen_reg[1]_0\,
I3 => p_54_out,
O => \s_axi_rid[11]_INST_0_i_3_n_0\
);
\s_axi_rid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(15),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(15),
I4 => \m_payload_i_reg[46]_1\(2),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(1)
);
\s_axi_rid[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(16),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(16),
I4 => \m_payload_i_reg[46]_1\(3),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(2)
);
\s_axi_rid[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I1 => \m_payload_i_reg[46]_0\(17),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(4),
I4 => \m_payload_i_reg[46]\(17),
I5 => \s_axi_rid[11]_INST_0_i_1_n_0\,
O => s_axi_rid(3)
);
\s_axi_rid[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(18),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(18),
I4 => \m_payload_i_reg[46]_1\(5),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(4)
);
\s_axi_rid[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(19),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(6),
I4 => \m_payload_i_reg[46]_0\(19),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(5)
);
\s_axi_rid[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(20),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(20),
I4 => \m_payload_i_reg[46]_1\(7),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(6)
);
\s_axi_rid[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(21),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(21),
I4 => \m_payload_i_reg[46]_1\(8),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(7)
);
\s_axi_rid[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(22),
I2 => \s_axi_rid[11]_INST_0_i_3_n_0\,
I3 => \m_payload_i_reg[46]_0\(22),
I4 => \m_payload_i_reg[46]_1\(9),
I5 => \s_axi_rid[11]_INST_0_i_2_n_0\,
O => s_axi_rid(8)
);
\s_axi_rid[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[46]\(23),
I2 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[46]_1\(10),
I4 => \m_payload_i_reg[46]_0\(23),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => s_axi_rid(9)
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_rid[11]_INST_0_i_2_n_0\,
I1 => \m_payload_i_reg[46]_1\(0),
I2 => \m_payload_i_reg[46]\(13),
I3 => \s_axi_rid[11]_INST_0_i_1_n_0\,
I4 => \m_payload_i_reg[46]_0\(13),
I5 => \s_axi_rid[11]_INST_0_i_3_n_0\,
O => \^s_axi_rlast\(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FEAEAEA00EAEAEA"
)
port map (
I0 => \m_payload_i_reg[46]\(12),
I1 => p_32_out,
I2 => \^m_payload_i_reg[34]\,
I3 => p_54_out,
I4 => \^chosen_reg[1]_0\,
I5 => \m_payload_i_reg[46]_0\(12),
O => s_axi_rresp(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => p_54_out,
I1 => \^chosen_reg[1]_0\,
I2 => p_32_out,
I3 => \^m_payload_i_reg[34]\,
I4 => \^m_payload_i_reg[0]_0\,
I5 => p_74_out,
O => s_axi_rvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_2 : out STD_LOGIC;
p_14_in : out STD_LOGIC;
p_21_in : out STD_LOGIC;
p_15_in : out STD_LOGIC;
p_17_in : out STD_LOGIC;
\gen_axi.write_cs_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_2 : out STD_LOGIC;
\gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : in STD_LOGIC;
mi_rready_2 : in STD_LOGIC;
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
mi_bready_2 : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.write_cs_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_arready_2\ : STD_LOGIC;
signal \^mi_awready_2\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_14_in\ : STD_LOGIC;
signal \^p_15_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal \^p_21_in\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair15";
begin
\gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\;
\gen_axi.write_cs_reg[1]_0\(0) <= \^gen_axi.write_cs_reg[1]_0\(0);
mi_arready_2 <= \^mi_arready_2\;
mi_awready_2 <= \^mi_awready_2\;
p_14_in <= \^p_14_in\;
p_15_in <= \^p_15_in\;
p_17_in <= \^p_17_in\;
p_21_in <= \^p_21_in\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \^p_15_in\,
I3 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9FFA900"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \^p_15_in\,
I4 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9FFFFAAA90000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg\(0),
I3 => \gen_axi.read_cnt_reg__0\(1),
I4 => \^p_15_in\,
I5 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FACAFAFACACACACA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_15_in\,
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt[4]_i_2_n_0\,
I5 => \gen_axi.read_cnt_reg__0\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg\(0),
I2 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3CAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^p_15_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE2E22E2"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \^p_15_in\,
I2 => \gen_axi.read_cnt[7]_i_3_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(5),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B874B8"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \^p_15_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I3 => \gen_axi.read_cnt[7]_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg__0\(5),
I5 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \gen_axi.read_cnt_reg\(0),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(4),
I4 => \gen_axi.read_cnt_reg__0\(3),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FF80FF80FF80"
)
port map (
I0 => \^mi_arready_2\,
I1 => \gen_no_arbiter.m_target_hot_i_reg[2]\(0),
I2 => aa_mi_arvalid,
I3 => \^p_15_in\,
I4 => mi_rready_2,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_15_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_2\,
I1 => \^p_15_in\,
I2 => mi_rready_2,
I3 => \^gen_axi.s_axi_arready_i_reg_0\,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
O => \^gen_axi.s_axi_arready_i_reg_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_2\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7F70F000F0F"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_reg\,
I1 => aa_mi_awtarget_hot(0),
I2 => write_cs(0),
I3 => mi_bready_2,
I4 => \^gen_axi.write_cs_reg[1]_0\(0),
I5 => \^mi_awready_2\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_2\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => write_cs(0),
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => \^mi_awready_2\,
I3 => aa_mi_awtarget_hot(0),
I4 => aa_sa_awvalid,
I5 => m_ready_d(0),
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => Q(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => Q(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => Q(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => Q(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => Q(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => Q(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => Q(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => Q(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => Q(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => Q(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => Q(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => Q(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFA888"
)
port map (
I0 => \storage_data1_reg[0]\,
I1 => write_cs(0),
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => mi_bready_2,
I4 => \^p_21_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_21_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBA8888888A"
)
port map (
I0 => s_axi_rlast_i0,
I1 => E(0),
I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I5 => \^p_17_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \gen_axi.read_cnt_reg__0\(5),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^p_15_in\,
I1 => mi_rready_2,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(1),
I3 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF0202"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
I4 => \^p_14_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_14_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0252"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => \^gen_axi.write_cs_reg[1]_0\(0),
I2 => write_cs(0),
I3 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF10FA10"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => mi_bready_2,
I2 => \^gen_axi.write_cs_reg[1]_0\(0),
I3 => write_cs(0),
I4 => \storage_data1_reg[0]\,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^gen_axi.write_cs_reg[1]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
ss_wr_awvalid : out STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair141";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"111F"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \gen_multi_thread.accept_cnt_reg[3]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030000000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000EC00000000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(0),
I4 => ss_aa_awready,
I5 => aresetn_d,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_aa_awready,
I1 => \^m_ready_d\(0),
I2 => ss_wr_awready,
I3 => \^m_ready_d\(1),
O => s_axi_awready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[0]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]_1\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 : entity is "axi_crossbar_v2_1_14_splitter";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEEEEEC"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(0),
I2 => aa_mi_awtarget_hot(2),
I3 => aa_mi_awtarget_hot(1),
I4 => aa_mi_awtarget_hot(0),
I5 => \m_ready_d_reg[0]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => aa_sa_awvalid,
I1 => \^m_ready_d\(1),
I2 => aresetn_d,
I3 => \m_ready_d_reg[0]_0\,
I4 => \gen_no_arbiter.m_target_hot_i_reg[1]\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => \storage_data1_reg[0]\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
\storage_data1_reg[1]_0\ : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\ is
signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC;
signal \^gen_rep[0].fifoaddr_reg[0]\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_rep[0].fifoaddr_reg[0]\ <= \^gen_rep[0].fifoaddr_reg[0]\;
push <= \^push\;
s_ready_i_reg <= \^s_ready_i_reg\;
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \FSM_onehot_state[3]_i_6_n_0\,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => m_avalid,
O => \^gen_rep[0].fifoaddr_reg[0]\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F035FF35"
)
port map (
I0 => m_axi_wready(0),
I1 => p_14_in,
I2 => \storage_data1_reg[1]_0\,
I3 => \storage_data1_reg[0]\,
I4 => m_axi_wready(1),
O => \FSM_onehot_state[3]_i_6_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg\,
O => \^push\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0DFFFFFFDDFFFF"
)
port map (
I0 => out0(1),
I1 => \^gen_rep[0].fifoaddr_reg[0]\,
I2 => s_ready_i_reg_0,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => out0(0),
O => \^s_ready_i_reg\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F011FFFFF0110000"
)
port map (
I0 => st_aa_awtarget_enc(0),
I1 => st_aa_awtarget_hot(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => \storage_data1_reg[1]_0\,
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_2\ : STD_LOGIC;
signal \s_axi_bid[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bid[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 35 downto 24 );
begin
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_2 <= \^mi_bready_2\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => w_issuing_cnt(0),
I1 => s_axi_bready(0),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(8),
Q => st_mr_bid(32),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(9),
Q => st_mr_bid(33),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(10),
Q => Q(4),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(11),
Q => st_mr_bid(35),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(0),
Q => st_mr_bid(24),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(1),
Q => Q(0),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(2),
Q => Q(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(3),
Q => Q(2),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(4),
Q => st_mr_bid(28),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(5),
Q => Q(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(6),
Q => st_mr_bid(30),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in\,
D => D(7),
Q => st_mr_bid(31),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_21_in,
I1 => \^mi_bready_2\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
O => \m_valid_i_i_1__1_n_0\
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => S(0)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(0),
I3 => \s_axi_bid[6]_INST_0_i_1_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2),
I5 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\s_axi_bid[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(0),
I1 => st_mr_bid(24),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(6)
);
\s_axi_bid[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(6),
I1 => st_mr_bid(35),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(13),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bid[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(1),
I1 => st_mr_bid(28),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[6]_INST_0_i_1_n_0\,
O => s_axi_bid(2)
);
\s_axi_bid[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(2),
I1 => st_mr_bid(30),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(9),
O => \s_axi_bid[6]_INST_0_i_1_n_0\
);
\s_axi_bid[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[7]_INST_0_i_1_n_0\,
O => s_axi_bid(3)
);
\s_axi_bid[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(3),
I1 => st_mr_bid(31),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(10),
O => \s_axi_bid[7]_INST_0_i_1_n_0\
);
\s_axi_bid[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_bid[8]_INST_0_i_1_n_0\,
O => s_axi_bid(4)
);
\s_axi_bid[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5303030F53F3F3F"
)
port map (
I0 => st_mr_bid(32),
I1 => \m_payload_i_reg[13]_0\(11),
I2 => m_valid_i_reg_1,
I3 => \^m_payload_i_reg[2]_0\,
I4 => chosen(0),
I5 => \m_payload_i_reg[13]_0\(4),
O => \s_axi_bid[8]_INST_0_i_1_n_0\
);
\s_axi_bid[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(5)
);
\s_axi_bid[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0003555FFFF3555"
)
port map (
I0 => \m_payload_i_reg[13]_0\(5),
I1 => st_mr_bid(33),
I2 => \^m_payload_i_reg[2]_0\,
I3 => chosen(0),
I4 => m_valid_i_reg_1,
I5 => \m_payload_i_reg[13]_0\(12),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_21_in,
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^mi_bready_2\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\ is
signal \^gen_multi_thread.accept_cnt_reg[3]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal st_mr_bid : STD_LOGIC_VECTOR ( 22 downto 13 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 4 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi_bid[11]_INST_0_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair44";
begin
\gen_multi_thread.accept_cnt_reg[3]\ <= \^gen_multi_thread.accept_cnt_reg[3]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ <= \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\;
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000700000000"
)
port map (
I0 => \^gen_multi_thread.accept_cnt_reg[3]\,
I1 => s_axi_bready(0),
I2 => Q(2),
I3 => Q(1),
I4 => Q(0),
I5 => Q(3),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => st_mr_bmesg(3),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(12),
Q => st_mr_bid(22),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => st_mr_bmesg(4),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => st_mr_bid(13),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => st_mr_bid(14),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => st_mr_bid(15),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(1),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => st_mr_bid(17),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(3),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \^m_payload_i_reg[0]_0\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
\s_axi_bid[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
O => s_axi_bid(4)
);
\s_axi_bid[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(4),
I1 => st_mr_bid(22),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(9),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\
);
\s_axi_bid[11]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => chosen(0),
O => \^gen_multi_thread.accept_cnt_reg[3]\
);
\s_axi_bid[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
O => s_axi_bid(0)
);
\s_axi_bid[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(0),
I1 => st_mr_bid(13),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(5),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\
);
\s_axi_bid[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
O => s_axi_bid(1)
);
\s_axi_bid[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(14),
I1 => \m_payload_i_reg[12]_0\(1),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(6),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\
);
\s_axi_bid[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
O => s_axi_bid(2)
);
\s_axi_bid[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0535353FF535353"
)
port map (
I0 => st_mr_bid(15),
I1 => \m_payload_i_reg[12]_0\(2),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(7),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\
);
\s_axi_bid[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
O => s_axi_bid(3)
);
\s_axi_bid[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0353535FF353535"
)
port map (
I0 => \m_payload_i_reg[12]_0\(3),
I1 => st_mr_bid(17),
I2 => \^gen_multi_thread.accept_cnt_reg[3]\,
I3 => p_38_out,
I4 => chosen(1),
I5 => \m_payload_i_reg[12]_0\(8),
O => \^gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FBFBFBF3F808080"
)
port map (
I0 => st_mr_bmesg(3),
I1 => chosen(0),
I2 => \^m_payload_i_reg[0]_0\,
I3 => chosen(1),
I4 => p_38_out,
I5 => \m_payload_i_reg[1]_0\(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CCCFAAAFAAAFAAA"
)
port map (
I0 => \m_payload_i_reg[1]_0\(1),
I1 => st_mr_bmesg(4),
I2 => chosen(1),
I3 => p_38_out,
I4 => \^m_payload_i_reg[0]_0\,
I5 => chosen(0),
O => s_axi_bresp(1)
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => chosen(0),
I4 => \aresetn_d_reg[1]_1\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__0_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\ is
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \m_payload_i[13]_i_1__1_n_0\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => chosen(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => s_axi_bready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => chosen(0),
I3 => s_axi_bready(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair69";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"955555552AAAAAAA"
)
port map (
I0 => \gen_axi.s_axi_arready_i_reg\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I5 => r_issuing_cnt(0),
O => \gen_master_slots[2].r_issuing_cnt_reg[16]\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FF2020000F202"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\,
I2 => st_aa_artarget_hot(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I4 => st_aa_artarget_hot(1),
I5 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_17_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF70FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => chosen_0(0),
I2 => \^m_valid_i_reg_0\,
I3 => p_15_in,
I4 => \^skid_buffer_reg[34]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => p_15_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => s_axi_rready(0),
I3 => chosen_0(0),
I4 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_17_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\ is
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 25 downto 0 );
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 68 downto 35 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_6\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__3\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_valid_i_i_1__3\ : label is "soft_lutpair45";
begin
\gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
I1 => \^s_ready_i_reg_0\,
I2 => chosen_0(0),
I3 => s_axi_rready(0),
O => \^gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_master_slots[1].r_issuing_cnt[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => chosen_0(0),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(0),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(1),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(2),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3),
I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
O => p_1_in_0
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(67),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(68),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF2AFFFF"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_rready(0),
I2 => chosen_0(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[1]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(50),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(5),
O => s_axi_rdata(5)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(51),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(6),
O => s_axi_rdata(6)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(52),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(7),
O => s_axi_rdata(7)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(53),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(8),
O => s_axi_rdata(8)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(54),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(9),
O => s_axi_rdata(9)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(55),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(10),
O => s_axi_rdata(10)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(56),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(11),
O => s_axi_rdata(11)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(39),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(0),
O => s_axi_rdata(0)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(59),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(12),
O => s_axi_rdata(12)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(61),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(13),
O => s_axi_rdata(13)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(62),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(14),
O => s_axi_rdata(14)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(63),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(15),
O => s_axi_rdata(15)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(64),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(16),
O => s_axi_rdata(16)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(66),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(17),
O => s_axi_rdata(17)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(67),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(18),
O => s_axi_rdata(18)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(40),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(1),
O => s_axi_rdata(1)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(68),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(19),
O => s_axi_rdata(19)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(41),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(2),
O => s_axi_rdata(2)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(43),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(3),
O => s_axi_rdata(3)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A3F3F3F2A000000"
)
port map (
I0 => st_mr_rmesg(45),
I1 => chosen_0(1),
I2 => p_32_out,
I3 => chosen_0(0),
I4 => \^s_ready_i_reg_0\,
I5 => \m_payload_i_reg[32]_0\(4),
O => s_axi_rdata(4)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFFACCCACCCACCC"
)
port map (
I0 => st_mr_rmesg(35),
I1 => \m_payload_i_reg[32]_0\(20),
I2 => \^s_ready_i_reg_0\,
I3 => chosen_0(0),
I4 => p_32_out,
I5 => chosen_0(1),
O => s_axi_rresp(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F4F4F"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[1]\,
I2 => \^s_ready_i_reg_0\,
I3 => s_axi_rready(0),
I4 => chosen_0(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\ is
signal \^gen_master_slots[0].r_issuing_cnt_reg[0]\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair39";
begin
\gen_master_slots[0].r_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]\;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => s_axi_rready(0),
I2 => \^m_valid_i_reg_0\,
I3 => chosen_0(0),
O => \^gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(2),
I3 => Q(3),
I4 => \^gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4CFFFF"
)
port map (
I0 => chosen_0(0),
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_rready(0),
I3 => m_axi_rvalid(0),
I4 => \^m_axi_rready[0]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F4FF44FF"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[0]\,
I2 => chosen_0(0),
I3 => \^m_valid_i_reg_0\,
I4 => s_axi_rready(0),
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[2]_0\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_artarget_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC;
\s_axi_araddr[25]_0\ : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\s_axi_araddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
p_74_out : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_54_out : in STD_LOGIC;
p_32_out : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_0\ : in STD_LOGIC_VECTOR ( 25 downto 0 );
\m_payload_i_reg[46]_1\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_0\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_1\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_20\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_21\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_22\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_23\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_24\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_25\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_26\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_27\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_28\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_29\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_30\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_31\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_32\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_33\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_34\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_35\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_36\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_37\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_38\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_39\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_40\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_41\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_42\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_43\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_44\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_45\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_46\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_47\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_48\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_49\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_50\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_51\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_6\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_7\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_8\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_artarget_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1__0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_24__0\ : label is "soft_lutpair99";
begin
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\;
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ <= \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\;
m_valid_i <= \^m_valid_i\;
st_aa_artarget_hot(0) <= \^st_aa_artarget_hot\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I3 => \s_axi_araddr[31]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_araddr[31]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I3 => \s_axi_araddr[31]\(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I5 => \s_axi_araddr[31]\(6),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I3 => \s_axi_araddr[31]\(5),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I3 => \s_axi_araddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I5 => \s_axi_araddr[31]\(1),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I1 => \s_axi_araddr[31]\(7),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(6),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
I4 => \s_axi_araddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_araddr[31]\(5),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
I2 => \s_axi_araddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I5 => \s_axi_araddr[31]\(4),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I1 => \s_axi_araddr[31]\(9),
I2 => \s_axi_araddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
I4 => \s_axi_araddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(8),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
I4 => \s_axi_araddr[31]\(7),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
I4 => \s_axi_araddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I1 => \s_axi_araddr[31]\(0),
I2 => \s_axi_araddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I1 => \s_axi_araddr[31]\(10),
I2 => \s_axi_araddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_araddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I1 => \s_axi_araddr[31]\(6),
I2 => \s_axi_araddr[31]\(7),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I4 => \s_axi_araddr[31]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I1 => \s_axi_araddr[31]\(3),
I2 => \s_axi_araddr[31]\(4),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I4 => \s_axi_araddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I1 => \s_axi_araddr[31]\(1),
I2 => \s_axi_araddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_araddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_1\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.arbiter_resp_inst_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_5
port map (
CO(0) => p_8_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_0\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_1\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_2\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\,
SR(0) => SR(0),
aclk => aclk,
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_multi_thread.accept_cnt_reg[2]\ => \gen_multi_thread.accept_cnt_reg[2]_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_27\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_31\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_35\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_8\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_7\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_43\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_6\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_47\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.arbiter_resp_inst_n_5\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => \gen_multi_thread.arbiter_resp_inst_n_51\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]_1\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_2\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_3\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_4\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_5\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[0]_0\ => chosen(0),
\m_payload_i_reg[34]\ => chosen(2),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[46]\(25 downto 0) => \m_payload_i_reg[46]\(25 downto 0),
\m_payload_i_reg[46]_0\(25 downto 0) => \m_payload_i_reg[46]_0\(25 downto 0),
\m_payload_i_reg[46]_1\(12 downto 0) => \m_payload_i_reg[46]_1\(12 downto 0),
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid(0) => s_axi_rvalid(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0088888888"
)
port map (
I0 => aid_match_00,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8FFFFFFFF"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_artarget_hot\(0),
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF55FF55CF55FF55"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"3B080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I4 => aid_match_10,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_artarget_hot\(0),
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_20,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_artarget_hot\(0),
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_4\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
I4 => aid_match_00,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0A0A0A3A0A0A0A"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => aid_match_30,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => aid_match_10,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(57),
I2 => active_cnt(56),
I3 => active_cnt(58),
I4 => active_cnt(59),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(33),
I2 => active_cnt(32),
I3 => active_cnt(34),
I4 => active_cnt(35),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_artarget_hot\(0),
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(35),
I1 => active_cnt(34),
I2 => active_cnt(32),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_8\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545FFFFFFEFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I5 => aid_match_40,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_artarget_hot\(0),
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_7\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FF77F077FF77"
)
port map (
I0 => aid_match_50,
I1 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABFFFFFFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0\,
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => active_cnt(27),
I4 => active_cnt(26),
I5 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_artarget_hot\(0),
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_6\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA800000000"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => aid_match_60,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => active_cnt(51),
I2 => active_cnt(50),
I3 => active_cnt(48),
I4 => active_cnt(49),
I5 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_artarget_hot\(0),
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(59),
I1 => active_cnt(58),
I2 => active_cnt(56),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_5\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \s_axi_araddr[31]\(17),
I1 => \s_axi_araddr[31]\(20),
I2 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\,
I3 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\,
I4 => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\,
O => \^st_aa_artarget_hot\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_araddr[31]\(13),
I1 => \s_axi_araddr[31]\(22),
I2 => \s_axi_araddr[31]\(15),
I3 => \s_axi_araddr[31]\(12),
I4 => \s_axi_araddr[31]\(14),
I5 => \s_axi_araddr[31]\(26),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(25),
I1 => \s_axi_araddr[31]\(27),
I2 => \s_axi_araddr[31]\(23),
I3 => \s_axi_araddr[31]\(24),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_araddr[31]\(18),
I1 => \s_axi_araddr[31]\(19),
I2 => \s_axi_araddr[31]\(16),
I3 => \s_axi_araddr[31]\(21),
O => \^gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \s_axi_araddr[25]_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF5555CFFF5555"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_1\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_artarget_hot\(0),
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F40"
)
port map (
I0 => \s_axi_araddr[25]_0\,
I1 => \^m_valid_i\,
I2 => aresetn_d,
I3 => \gen_no_arbiter.m_target_hot_i_reg[2]_0\(0),
O => \gen_no_arbiter.m_target_hot_i_reg[2]\
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDDDFFFD"
)
port map (
I0 => aid_match_30,
I1 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(25),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"88880008"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(49),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_50,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I2 => \s_axi_araddr[25]\(0),
I3 => active_target(41),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(8),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I4 => aid_match_10,
I5 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010FF1010"
)
port map (
I0 => active_target(16),
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I2 => aid_match_20,
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => active_cnt(3),
I4 => active_cnt(2),
I5 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(48),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F1000000"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[25]\(0),
I2 => active_target(32),
I3 => aid_match_40,
I4 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I5 => \^st_aa_artarget_hot\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0\,
I2 => active_target(49),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(17),
O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F007F7F7F7F7F7F"
)
port map (
I0 => active_target(33),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0\,
I4 => aid_match_50,
I5 => active_target(41),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0\,
I4 => aid_match_30,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0\,
I1 => aid_match_10,
I2 => active_target(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0\,
I4 => aid_match_00,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(3),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
I3 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000002F2"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
I2 => \^st_aa_artarget_hot\(0),
I3 => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I5 => \gen_no_arbiter.m_valid_i_reg\,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000E00"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \s_axi_araddr[25]\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000111F"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0\,
I1 => active_target(9),
I2 => active_target(1),
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0\,
I4 => \s_axi_araddr[25]\(0),
I5 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEEEF"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0\,
I3 => active_target(56),
I4 => \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFAAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I5 => \s_axi_araddr[25]_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F7F700F7F7F7F7"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(57),
I3 => active_target(17),
I4 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => aid_match_70,
I1 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0\,
I2 => active_target(56),
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0\,
I4 => aid_match_20,
I5 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_48\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_49\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_50\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_51\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_28\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_29\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_30\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_31\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_24\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_25\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_26\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_27\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_20\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_21\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_22\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_23\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_44\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_45\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_46\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_47\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_40\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_41\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_42\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_43\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_36\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_37\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_38\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_39\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.arbiter_resp_inst_n_32\,
S(2) => \gen_multi_thread.arbiter_resp_inst_n_33\,
S(1) => \gen_multi_thread.arbiter_resp_inst_n_34\,
S(0) => \gen_multi_thread.arbiter_resp_inst_n_35\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
m_valid_i : out STD_LOGIC;
\gen_master_slots[0].w_issuing_cnt_reg[1]\ : out STD_LOGIC;
chosen : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
p_80_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[10]\ : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ : in STD_LOGIC;
\s_axi_awaddr[31]\ : in STD_LOGIC_VECTOR ( 27 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_38_out : in STD_LOGIC;
p_60_out : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst_n_10\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_11\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_12\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_13\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_14\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_15\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_16\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_17\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_2\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_3\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_4\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst_n_9\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_i_1_n_0 : STD_LOGIC;
signal p_10_out_carry_i_3_n_0 : STD_LOGIC;
signal p_10_out_carry_i_4_n_0 : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_i_1_n_0 : STD_LOGIC;
signal p_12_out_carry_i_3_n_0 : STD_LOGIC;
signal p_12_out_carry_i_4_n_0 : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_i_1_n_0 : STD_LOGIC;
signal p_14_out_carry_i_3_n_0 : STD_LOGIC;
signal p_14_out_carry_i_4_n_0 : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_i_1_n_0 : STD_LOGIC;
signal p_2_out_carry_i_3_n_0 : STD_LOGIC;
signal p_2_out_carry_i_4_n_0 : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_i_1_n_0 : STD_LOGIC;
signal p_4_out_carry_i_3_n_0 : STD_LOGIC;
signal p_4_out_carry_i_4_n_0 : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_i_1_n_0 : STD_LOGIC;
signal p_6_out_carry_i_3_n_0 : STD_LOGIC;
signal p_6_out_carry_i_4_n_0 : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_i_1_n_0 : STD_LOGIC;
signal p_8_out_carry_i_3_n_0 : STD_LOGIC;
signal p_8_out_carry_i_4_n_0 : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal \^st_aa_awtarget_enc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_12\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_8__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_9__0\ : label is "soft_lutpair140";
begin
D(0) <= \^d\(0);
Q(2 downto 0) <= \^q\(2 downto 0);
SR(0) <= \^sr\(0);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\;
st_aa_awtarget_enc(0) <= \^st_aa_awtarget_enc\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^q\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^q\(2),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(1),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(9),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I3 => \s_axi_awaddr[31]\(10),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awaddr[31]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(6),
I1 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
I2 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
I3 => \s_axi_awaddr[31]\(8),
I4 => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
I5 => \s_axi_awaddr[31]\(7),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(3),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I3 => \s_axi_awaddr[31]\(4),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awaddr[31]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awaddr[31]\(0),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I3 => \s_axi_awaddr[31]\(2),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I5 => \s_axi_awaddr[31]\(1),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(9),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(7),
I3 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awaddr[31]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I1 => \s_axi_awaddr[31]\(10),
I2 => \s_axi_awaddr[31]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
I4 => \s_axi_awaddr[31]\(6),
I5 => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(11),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I4 => \s_axi_awaddr[31]\(10),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
I1 => \s_axi_awaddr[31]\(6),
I2 => \s_axi_awaddr[31]\(8),
I3 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
I4 => \s_axi_awaddr[31]\(7),
I5 => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I1 => \s_axi_awaddr[31]\(3),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(4),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I1 => \s_axi_awaddr[31]\(0),
I2 => \s_axi_awaddr[31]\(1),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I4 => \s_axi_awaddr[31]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I1 => \s_axi_awaddr[31]\(9),
I2 => \s_axi_awaddr[31]\(10),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I4 => \s_axi_awaddr[31]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
I1 => \s_axi_awaddr[31]\(7),
I2 => \s_axi_awaddr[31]\(6),
I3 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
I4 => \s_axi_awaddr[31]\(8),
I5 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I1 => \s_axi_awaddr[31]\(4),
I2 => \s_axi_awaddr[31]\(5),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I4 => \s_axi_awaddr[31]\(3),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I1 => \s_axi_awaddr[31]\(1),
I2 => \s_axi_awaddr[31]\(2),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I4 => \s_axi_awaddr[31]\(0),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_4\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_3\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_17\,
D => \gen_multi_thread.arbiter_resp_inst_n_2\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
CO(0) => p_0_out,
D(2) => \gen_multi_thread.arbiter_resp_inst_n_2\,
D(1) => \gen_multi_thread.arbiter_resp_inst_n_3\,
D(0) => \gen_multi_thread.arbiter_resp_inst_n_4\,
E(0) => \gen_multi_thread.arbiter_resp_inst_n_9\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
SR(0) => \^sr\(0),
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[0]_0\ => chosen(0),
\chosen_reg[1]_0\ => chosen(1),
cmd_push_0 => cmd_push_0,
cmd_push_3 => cmd_push_3,
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_master_slots[0].w_issuing_cnt_reg[1]\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].w_issuing_cnt_reg[10]\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => chosen(2),
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].w_issuing_cnt_reg[16]\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1\ => \gen_master_slots[2].w_issuing_cnt_reg[16]_0\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst_n_17\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst_n_16\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\(0) => p_14_out,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.arbiter_resp_inst_n_15\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\ => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\ => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.arbiter_resp_inst_n_14\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\ => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\ => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.arbiter_resp_inst_n_13\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\ => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.arbiter_resp_inst_n_12\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1\ => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\ => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.arbiter_resp_inst_n_11\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.arbiter_resp_inst_n_10\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\ => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\ => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
\m_ready_d_reg[1]_0\ => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
\m_ready_d_reg[1]_1\ => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
\m_ready_d_reg[1]_2\ => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
\m_ready_d_reg[1]_3\ => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
\m_ready_d_reg[1]_4\ => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
\m_ready_d_reg[1]_5\ => \m_ready_d_reg[1]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[26]\(0) => \^st_aa_awtarget_enc\(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(0),
I2 => active_cnt(1),
I3 => cmd_push_0,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(3),
I1 => active_cnt(2),
I2 => cmd_push_0,
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_16\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(6),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(7),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(8),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0500050035300500"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_40,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => aid_match_50,
O => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(8),
I2 => active_cnt(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(11),
I1 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFFBBF0BBFFBB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_10,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0\,
I1 => active_cnt(8),
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_15\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08083B08"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I1 => active_cnt(16),
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(16),
I2 => active_cnt(17),
I3 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(19),
I1 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_14\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDDFFDDF0DDFFDD"
)
port map (
I0 => aid_match_20,
I1 => \m_ready_d_reg[1]\,
I2 => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AA9"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(24),
I2 => active_cnt(25),
I3 => cmd_push_3,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => active_cnt(27),
I1 => active_cnt(26),
I2 => cmd_push_3,
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_13\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"004400440F440044"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => aid_match_30,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFFF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
I4 => aid_match_20,
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_10,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_30,
I1 => active_cnt(26),
I2 => active_cnt(27),
I3 => active_cnt(25),
I4 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I1 => active_cnt(32),
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(32),
I2 => active_cnt(33),
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(35),
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_12\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAFAFAFAFACAFAF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_00,
I1 => active_cnt(2),
I2 => active_cnt(3),
I3 => active_cnt(1),
I4 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0001"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I1 => active_cnt(40),
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(40),
I2 => active_cnt(41),
I3 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(43),
I1 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
I2 => active_cnt(41),
I3 => active_cnt(40),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_11\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAFFFFFACAFFCF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => aid_match_50,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I1 => active_cnt(48),
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(48),
I2 => active_cnt(49),
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(51),
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
I2 => active_cnt(49),
I3 => active_cnt(48),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(51),
I1 => active_cnt(50),
I2 => active_cnt(48),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_10\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555557"
)
port map (
I0 => aid_match_60,
I1 => active_cnt(49),
I2 => active_cnt(48),
I3 => active_cnt(50),
I4 => active_cnt(51),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => active_cnt(48),
I5 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I1 => active_cnt(56),
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(56),
I2 => active_cnt(57),
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAA6"
)
port map (
I0 => active_cnt(59),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.arbiter_resp_inst_n_9\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awaddr[31]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\,
I1 => \s_axi_awaddr[31]\(17),
I2 => \s_axi_awaddr[31]\(20),
O => \^st_aa_awtarget_enc\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\,
I2 => \s_axi_awaddr[31]\(19),
I3 => \s_axi_awaddr[31]\(15),
I4 => \s_axi_awaddr[31]\(12),
I5 => \s_axi_awaddr[31]\(23),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \s_axi_awaddr[31]\(14),
I1 => \s_axi_awaddr[31]\(25),
I2 => \s_axi_awaddr[31]\(21),
I3 => \s_axi_awaddr[31]\(22),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \s_axi_awaddr[31]\(24),
I1 => \s_axi_awaddr[31]\(27),
I2 => \s_axi_awaddr[31]\(13),
I3 => \s_axi_awaddr[31]\(26),
I4 => \s_axi_awaddr[31]\(18),
I5 => \s_axi_awaddr[31]\(16),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^st_aa_awtarget_enc\(0),
I1 => st_aa_awtarget_hot(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0000FFEF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF0001"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0\,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => active_cnt(58),
I3 => active_cnt(59),
I4 => active_cnt(57),
I5 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => aid_match_70,
I1 => active_cnt(58),
I2 => active_cnt(59),
I3 => active_cnt(57),
I4 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^st_aa_awtarget_enc\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(57),
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F100"
)
port map (
I0 => active_target(41),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(40),
I3 => aid_match_50,
I4 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"22220002"
)
port map (
I0 => aid_match_20,
I1 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I2 => active_target(17),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(56),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(8),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I1 => aid_match_00,
I2 => active_target(1),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44440004"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I1 => aid_match_30,
I2 => active_target(25),
I3 => st_aa_awtarget_hot(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => active_target(32),
I1 => aid_match_40,
I2 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I3 => active_target(8),
I4 => aid_match_10,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFB00FBFB"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I1 => aid_match_50,
I2 => active_target(40),
I3 => active_target(24),
I4 => aid_match_30,
I5 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0404040404FF0404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(16),
I3 => active_target(0),
I4 => aid_match_00,
I5 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
I5 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0\,
I1 => aid_match_20,
I2 => active_target(17),
I3 => aid_match_00,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0\,
I5 => active_target(1),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => aid_match_40,
I1 => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0\,
I2 => active_target(33),
I3 => aid_match_70,
I4 => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0\,
I5 => active_target(57),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDF00DFDFDFDFDF"
)
port map (
I0 => active_target(41),
I1 => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0\,
I2 => aid_match_50,
I3 => aid_match_10,
I4 => \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0\,
I5 => active_target(9),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080FF8080808080"
)
port map (
I0 => aid_match_60,
I1 => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0\,
I2 => active_target(49),
I3 => aid_match_30,
I4 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0\,
I5 => active_target(25),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(1),
I2 => \gen_multi_thread.accept_cnt_reg\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000DDD0"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004040400"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0\,
I4 => active_target(48),
I5 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEE0EEEE"
)
port map (
I0 => st_aa_awtarget_hot(0),
I1 => \^st_aa_awtarget_enc\(0),
I2 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(32),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(33),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => active_target(48),
I1 => st_aa_awtarget_hot(0),
I2 => active_target(49),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => \i__carry_i_4_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_1_n_0\,
S(2) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0),
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_10_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0),
S(1) => p_10_out_carry_i_3_n_0,
S(0) => p_10_out_carry_i_4_n_0
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_10_out_carry_i_1_n_0
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_10_out_carry_i_3_n_0
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_10_out_carry_i_4_n_0
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_12_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0),
S(1) => p_12_out_carry_i_3_n_0,
S(0) => p_12_out_carry_i_4_n_0
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_12_out_carry_i_1_n_0
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_12_out_carry_i_3_n_0
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_12_out_carry_i_4_n_0
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_14_out_carry_i_1_n_0,
S(2) => S(0),
S(1) => p_14_out_carry_i_3_n_0,
S(0) => p_14_out_carry_i_4_n_0
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_14_out_carry_i_1_n_0
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_14_out_carry_i_3_n_0
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_14_out_carry_i_4_n_0
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_2_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0),
S(1) => p_2_out_carry_i_3_n_0,
S(0) => p_2_out_carry_i_4_n_0
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_2_out_carry_i_1_n_0
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_2_out_carry_i_3_n_0
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_2_out_carry_i_4_n_0
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_4_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0),
S(1) => p_4_out_carry_i_3_n_0,
S(0) => p_4_out_carry_i_4_n_0
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_4_out_carry_i_1_n_0
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_4_out_carry_i_3_n_0
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_4_out_carry_i_4_n_0
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_6_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0),
S(1) => p_6_out_carry_i_3_n_0,
S(0) => p_6_out_carry_i_4_n_0
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_6_out_carry_i_1_n_0
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_6_out_carry_i_3_n_0
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_6_out_carry_i_4_n_0
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => p_8_out_carry_i_1_n_0,
S(2) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0),
S(1) => p_8_out_carry_i_3_n_0,
S(0) => p_8_out_carry_i_4_n_0
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I3 => \m_payload_i_reg[11]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
I5 => \m_payload_i_reg[13]\,
O => p_8_out_carry_i_1_n_0
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I3 => \m_payload_i_reg[5]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
I5 => \m_payload_i_reg[7]\,
O => p_8_out_carry_i_3_n_0
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000066006600000"
)
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I3 => \m_payload_i_reg[2]\,
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
I5 => \m_payload_i_reg[4]\,
O => p_8_out_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
s_ready_i_reg_0 : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_1\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_2\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_3\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[0]\ : STD_LOGIC;
signal \storage_data1_reg_n_0_[1]\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair142";
begin
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\/FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"40440000"
)
port map (
I0 => p_9_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_0_in8_in,
O => \/FSM_onehot_state[0]_i_1_n_0\
);
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\/FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002A22"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => m_ready_d(0),
I3 => s_axi_awvalid(0),
I4 => p_9_in,
O => \/FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(0),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I5 => fifoaddr(2),
O => p_0_in5_out
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \/FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => \gen_axi.write_cs_reg[1]_0\(0),
I3 => s_axi_wlast(0),
I4 => s_axi_wvalid(0),
I5 => m_avalid,
O => \gen_axi.write_cs_reg[1]\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C133DDFF3ECC2200"
)
port map (
I0 => p_0_in8_in,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \^s_ready_i_reg_0\,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFD5402A"
)
port map (
I0 => fifoaddr(0),
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFF77710000888"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
I2 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_rep[0].fifoaddr_reg[0]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
load_s1 => load_s1,
m_avalid => m_avalid,
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_ready_d(0) => m_ready_d(0),
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_14_in => p_14_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
s_ready_i_reg_0 => \^s_ready_i_reg_0\,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
\storage_data1_reg[0]\ => \storage_data1_reg_n_0_[0]\,
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
\storage_data1_reg[1]_0\ => \storage_data1_reg_n_0_[1]\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \storage_data1_reg_n_0_[0]\,
I1 => \storage_data1_reg_n_0_[1]\,
I2 => m_avalid,
I3 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A8A008A0A800080"
)
port map (
I0 => m_avalid,
I1 => m_axi_wready(1),
I2 => \storage_data1_reg_n_0_[0]\,
I3 => \storage_data1_reg_n_0_[1]\,
I4 => p_14_in,
I5 => m_axi_wready(0),
O => s_axi_wready(0)
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFAAAAAAAA"
)
port map (
I0 => s_ready_i_i_2_n_0,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_2\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => fifoaddr(2),
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => areset_d1,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^s_ready_i_reg_0\,
R => SR(0)
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(0),
I3 => load_s1,
I4 => \storage_data1_reg_n_0_[0]\,
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888FFC88888"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \gen_srls[0].gen_rep[1].srl_nx1_n_3\,
I2 => p_0_in8_in,
I3 => p_9_in,
I4 => s_axi_awvalid(0),
I5 => m_ready_d(0),
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => \storage_data1_reg_n_0_[0]\,
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_1\,
Q => \storage_data1_reg_n_0_[1]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_80_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_74_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8\
port map (
D(13 downto 0) => D(13 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_80_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9\
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
chosen_0(0) => chosen_0(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_74_out,
p_1_in => p_1_in,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_60_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_54_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 25 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen : in STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[12]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_38_out : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[32]\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
p_32_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6\
port map (
D(13 downto 0) => D(13 downto 0),
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
chosen(1 downto 0) => chosen(1 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_multi_thread.accept_cnt_reg[3]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\(6 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_60_out,
\m_payload_i_reg[12]_0\(9 downto 0) => \m_payload_i_reg[12]\(9 downto 0),
\m_payload_i_reg[1]_0\(1 downto 0) => \m_payload_i_reg[1]\(1 downto 0),
p_1_in => \^p_1_in\,
p_38_out => p_38_out,
s_axi_bid(4 downto 0) => s_axi_bid(4 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7\
port map (
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
chosen_0(1 downto 0) => chosen_0(1 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].r_issuing_cnt_reg[11]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[32]_0\(20 downto 0) => \m_payload_i_reg[32]\(20 downto 0),
p_1_in => \^p_1_in\,
p_32_out => p_32_out,
s_axi_rdata(19 downto 0) => s_axi_rdata(19 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0),
s_ready_i_reg_0 => p_54_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_38_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_2 : out STD_LOGIC;
p_32_out : out STD_LOGIC;
mi_rready_2 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 6 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ : out STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : out STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_21_in : in STD_LOGIC;
chosen : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[13]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_artarget_hot : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
p_15_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
chosen_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_17_in : in STD_LOGIC;
\gen_axi.s_axi_arready_i_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(4 downto 0) => Q(4 downto 0),
S(0) => S(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
chosen(0) => chosen(0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_no_arbiter.m_target_hot_i_reg[2]\,
\m_payload_i_reg[13]_0\(13 downto 0) => \m_payload_i_reg[13]\(13 downto 0),
\m_payload_i_reg[2]_0\ => p_38_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
m_valid_i_reg_1 => m_valid_i_reg_0,
mi_bready_2 => mi_bready_2,
p_1_in => p_1_in,
p_21_in => p_21_in,
s_axi_bid(6 downto 0) => s_axi_bid(6 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg,
w_issuing_cnt(0) => w_issuing_cnt(0)
);
r_pipe: entity work.\zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
chosen_0(0) => chosen_0(0),
\gen_axi.s_axi_arready_i_reg\ => \gen_axi.s_axi_arready_i_reg\,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_valid_i_reg_0 => p_32_out,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
r_issuing_cnt(0) => r_issuing_cnt(0),
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_2,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.write_cs_reg[1]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
st_aa_awtarget_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_14_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zynq_design_1_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(0) => D(0),
SR(0) => SR(0),
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_axi.write_cs_reg[1]\,
\gen_axi.write_cs_reg[1]_0\(0) => \gen_axi.write_cs_reg[1]_0\(0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(0),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[7]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
aresetn : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 56 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 2 to 2 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_2 : STD_LOGIC;
signal addr_arbiter_ar_n_3 : STD_LOGIC;
signal addr_arbiter_ar_n_4 : STD_LOGIC;
signal addr_arbiter_ar_n_5 : STD_LOGIC;
signal addr_arbiter_ar_n_6 : STD_LOGIC;
signal addr_arbiter_ar_n_7 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_11 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_15 : STD_LOGIC;
signal addr_arbiter_aw_n_16 : STD_LOGIC;
signal addr_arbiter_aw_n_2 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_21 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_8 : STD_LOGIC;
signal addr_arbiter_aw_n_9 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_12\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_75\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_76\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_13\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_19\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_20\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_21\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_22\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_23\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_24\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_25\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_26\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_27\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_28\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_29\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_30\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_31\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_45\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_1\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\ : STD_LOGIC;
signal \^m_axi_arqos[7]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_3 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_2 : STD_LOGIC;
signal mi_arready_2 : STD_LOGIC;
signal mi_awready_2 : STD_LOGIC;
signal mi_bready_2 : STD_LOGIC;
signal mi_rready_2 : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_21_in : STD_LOGIC;
signal p_24_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_32_out : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_54_out : STD_LOGIC;
signal p_56_out : STD_LOGIC;
signal p_60_out : STD_LOGIC;
signal p_74_out : STD_LOGIC;
signal p_76_out : STD_LOGIC;
signal p_80_out : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 34 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 35 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 69 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 16 downto 0 );
signal write_cs : STD_LOGIC_VECTOR ( 1 to 1 );
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[7]\(68 downto 0) <= \^m_axi_arqos[7]\(68 downto 0);
addr_arbiter_ar: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
D(2) => addr_arbiter_ar_n_2,
D(1) => addr_arbiter_ar_n_3,
D(0) => addr_arbiter_ar_n_4,
E(0) => s_axi_rvalid_i,
Q(0) => p_56_out,
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.s_axi_rid_i_reg[11]\(0) => aa_mi_artarget_hot(2),
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_5,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_6,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_7,
\gen_master_slots[1].r_issuing_cnt_reg[8]\(0) => addr_arbiter_ar_n_85,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_82,
\gen_no_arbiter.m_target_hot_i_reg[0]_0\(0) => st_aa_artarget_hot(0),
\gen_no_arbiter.m_valid_i_reg_0\ => addr_arbiter_ar_n_80,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_81,
\m_axi_arqos[7]\(68 downto 0) => \^m_axi_arqos[7]\(68 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
\m_payload_i_reg[34]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\m_payload_i_reg[34]_0\ => \gen_master_slots[1].reg_slice_mi_n_27\,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_75\,
mi_arready_2 => mi_arready_2,
p_15_in => p_15_in,
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\s_axi_araddr[25]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\s_axi_araddr[28]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\s_axi_araddr[30]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\s_axi_arqos[3]\(68 downto 12) => \s_axi_arqos[3]\(56 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready\(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
s_axi_rready(0) => s_axi_rready(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
addr_arbiter_aw: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
D(2) => addr_arbiter_aw_n_7,
D(1) => addr_arbiter_aw_n_8,
D(0) => addr_arbiter_aw_n_9,
E(0) => addr_arbiter_aw_n_15,
Q(68 downto 0) => \^q\(68 downto 0),
SR(0) => reset,
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
aresetn_d_reg_0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\chosen_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\chosen_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => addr_arbiter_aw_n_16,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_12,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_13,
\gen_master_slots[1].w_issuing_cnt_reg[9]\ => addr_arbiter_aw_n_10,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => addr_arbiter_aw_n_14,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\ => addr_arbiter_aw_n_20,
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_2,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_3,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_21,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_awready_2 => mi_awready_2,
\s_axi_awaddr[20]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\s_axi_awaddr[26]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\s_axi_awqos[3]\(68 downto 12) => D(56 downto 0),
\s_axi_awqos[3]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
ss_aa_awready => ss_aa_awready,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(11 downto 0) => p_24_in(11 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_7\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[7]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[7]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[2]\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_10,
m_ready_d(0) => m_ready_d_3(1),
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_14,
mi_arready_2 => mi_arready_2,
mi_awready_2 => mi_awready_2,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_14_in => p_14_in,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_21_in => p_21_in,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_20_in(11 downto 0),
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_4,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_3,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_84,
D => addr_arbiter_ar_n_2,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \r_pipe/p_1_in_0\,
Q(3 downto 0) => r_issuing_cnt(3 downto 0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(0),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_76_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_1_in => p_1_in,
p_74_out => p_74_out,
p_80_out => p_80_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_13,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_12,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_16,
D => addr_arbiter_aw_n_11,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_6,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_5,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_ar_n_85,
D => addr_arbiter_ar_n_7,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
D(13 downto 2) => m_axi_bid(23 downto 12),
D(1 downto 0) => m_axi_bresp(3 downto 2),
Q(3 downto 0) => w_issuing_cnt(11 downto 8),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[2].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[2].reg_slice_mi_n_5\,
chosen(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 1),
chosen_0(1 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 1),
\gen_master_slots[1].r_issuing_cnt_reg[11]\ => \gen_master_slots[1].reg_slice_mi_n_75\,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_27\,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(6) => st_mr_bid(23),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(5 downto 2) => st_mr_bid(21 downto 18),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => st_mr_bid(16),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => st_mr_bid(12),
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25 downto 14) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13) => p_56_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12) => st_mr_rmesg(36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11) => st_mr_rmesg(69),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10) => st_mr_rmesg(65),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9) => st_mr_rmesg(60),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8 downto 7) => st_mr_rmesg(58 downto 57),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6 downto 3) => st_mr_rmesg(49 downto 46),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2) => st_mr_rmesg(44),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1) => st_mr_rmesg(42),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => st_mr_rmesg(38),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
\m_payload_i_reg[12]\(9) => st_mr_bid(34),
\m_payload_i_reg[12]\(8) => st_mr_bid(29),
\m_payload_i_reg[12]\(7 downto 5) => st_mr_bid(27 downto 25),
\m_payload_i_reg[12]\(4) => st_mr_bid(10),
\m_payload_i_reg[12]\(3) => st_mr_bid(5),
\m_payload_i_reg[12]\(2 downto 0) => st_mr_bid(3 downto 1),
\m_payload_i_reg[1]\(1 downto 0) => st_mr_bmesg(1 downto 0),
\m_payload_i_reg[32]\(20) => st_mr_rmesg(0),
\m_payload_i_reg[32]\(19 downto 17) => st_mr_rmesg(33 downto 31),
\m_payload_i_reg[32]\(16 downto 13) => st_mr_rmesg(29 downto 26),
\m_payload_i_reg[32]\(12) => st_mr_rmesg(24),
\m_payload_i_reg[32]\(11 downto 5) => st_mr_rmesg(21 downto 15),
\m_payload_i_reg[32]\(4) => st_mr_rmesg(10),
\m_payload_i_reg[32]\(3) => st_mr_rmesg(8),
\m_payload_i_reg[32]\(2 downto 0) => st_mr_rmesg(6 downto 4),
p_1_in => p_1_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
p_54_out => p_54_out,
p_60_out => p_60_out,
s_axi_bid(4) => s_axi_bid(10),
s_axi_bid(3) => s_axi_bid(5),
s_axi_bid(2 downto 0) => s_axi_bid(3 downto 1),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_rdata(19 downto 17) => s_axi_rdata(30 downto 28),
s_axi_rdata(16 downto 13) => s_axi_rdata(26 downto 23),
s_axi_rdata(12) => s_axi_rdata(21),
s_axi_rdata(11 downto 5) => s_axi_rdata(18 downto 12),
s_axi_rdata(4) => s_axi_rdata(7),
s_axi_rdata(3) => s_axi_rdata(5),
s_axi_rdata(2 downto 0) => s_axi_rdata(3 downto 1),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_8,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_7,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => addr_arbiter_aw_n_15,
D => addr_arbiter_aw_n_9,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[2].reg_slice_mi_n_45\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zynq_design_1_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(11 downto 0) => p_24_in(11 downto 0),
E(0) => \r_pipe/p_1_in\,
Q(4) => st_mr_bid(34),
Q(3) => st_mr_bid(29),
Q(2 downto 0) => st_mr_bid(27 downto 25),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_76\,
chosen(0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2),
chosen_0(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\gen_axi.s_axi_arready_i_reg\ => addr_arbiter_ar_n_80,
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_20_in(11 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_4\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_26\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_45\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(12 downto 1) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(0) => p_34_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_31\,
\m_payload_i_reg[13]\(13) => st_mr_bid(23),
\m_payload_i_reg[13]\(12 downto 9) => st_mr_bid(21 downto 18),
\m_payload_i_reg[13]\(8) => st_mr_bid(16),
\m_payload_i_reg[13]\(7 downto 6) => st_mr_bid(12 downto 11),
\m_payload_i_reg[13]\(5 downto 2) => st_mr_bid(9 downto 6),
\m_payload_i_reg[13]\(1) => st_mr_bid(4),
\m_payload_i_reg[13]\(0) => st_mr_bid(0),
m_valid_i_reg => \gen_master_slots[2].reg_slice_mi_n_1\,
m_valid_i_reg_0 => \gen_master_slots[1].reg_slice_mi_n_6\,
mi_bready_2 => mi_bready_2,
mi_rready_2 => mi_rready_2,
p_15_in => p_15_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_21_in => p_21_in,
p_32_out => p_32_out,
p_38_out => p_38_out,
r_issuing_cnt(0) => r_issuing_cnt(16),
s_axi_bid(6) => s_axi_bid(11),
s_axi_bid(5 downto 2) => s_axi_bid(9 downto 6),
s_axi_bid(1) => s_axi_bid(4),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[2].reg_slice_mi_n_5\,
st_aa_artarget_hot(1 downto 0) => st_aa_artarget_hot(1 downto 0),
w_issuing_cnt(0) => w_issuing_cnt(16)
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
E(0) => \r_pipe/p_1_in_0\,
SR(0) => reset,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2 downto 0),
\gen_multi_thread.accept_cnt_reg[2]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3\,
\gen_no_arbiter.m_target_hot_i_reg[2]_0\(0) => aa_mi_artarget_hot(2),
\gen_no_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_81,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8\,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready\(0),
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[46]\(25 downto 14) => st_mr_rid(11 downto 0),
\m_payload_i_reg[46]\(13) => p_76_out,
\m_payload_i_reg[46]\(12) => st_mr_rmesg(1),
\m_payload_i_reg[46]\(11) => st_mr_rmesg(34),
\m_payload_i_reg[46]\(10) => st_mr_rmesg(30),
\m_payload_i_reg[46]\(9) => st_mr_rmesg(25),
\m_payload_i_reg[46]\(8 downto 7) => st_mr_rmesg(23 downto 22),
\m_payload_i_reg[46]\(6 downto 3) => st_mr_rmesg(14 downto 11),
\m_payload_i_reg[46]\(2) => st_mr_rmesg(9),
\m_payload_i_reg[46]\(1) => st_mr_rmesg(7),
\m_payload_i_reg[46]\(0) => st_mr_rmesg(3),
\m_payload_i_reg[46]_0\(25 downto 14) => st_mr_rid(23 downto 12),
\m_payload_i_reg[46]_0\(13) => p_56_out,
\m_payload_i_reg[46]_0\(12) => st_mr_rmesg(36),
\m_payload_i_reg[46]_0\(11) => st_mr_rmesg(69),
\m_payload_i_reg[46]_0\(10) => st_mr_rmesg(65),
\m_payload_i_reg[46]_0\(9) => st_mr_rmesg(60),
\m_payload_i_reg[46]_0\(8 downto 7) => st_mr_rmesg(58 downto 57),
\m_payload_i_reg[46]_0\(6 downto 3) => st_mr_rmesg(49 downto 46),
\m_payload_i_reg[46]_0\(2) => st_mr_rmesg(44),
\m_payload_i_reg[46]_0\(1) => st_mr_rmesg(42),
\m_payload_i_reg[46]_0\(0) => st_mr_rmesg(38),
\m_payload_i_reg[46]_1\(12 downto 1) => st_mr_rid(35 downto 24),
\m_payload_i_reg[46]_1\(0) => p_34_out,
m_valid_i => m_valid_i,
p_32_out => p_32_out,
p_54_out => p_54_out,
p_74_out => p_74_out,
\s_axi_araddr[25]\(0) => st_aa_artarget_hot(0),
\s_axi_araddr[25]_0\ => addr_arbiter_ar_n_82,
\s_axi_araddr[31]\(27 downto 12) => \s_axi_arqos[3]\(31 downto 16),
\s_axi_araddr[31]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_rdata(11) => s_axi_rdata(31),
s_axi_rdata(10) => s_axi_rdata(27),
s_axi_rdata(9) => s_axi_rdata(22),
s_axi_rdata(8 downto 7) => s_axi_rdata(20 downto 19),
s_axi_rdata(6 downto 3) => s_axi_rdata(11 downto 8),
s_axi_rdata(2) => s_axi_rdata(6),
s_axi_rdata(1) => s_axi_rdata(4),
s_axi_rdata(0) => s_axi_rdata(0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(0) => s_axi_rresp(1),
s_axi_rvalid(0) => s_axi_rvalid(0),
st_aa_artarget_hot(0) => st_aa_artarget_hot(1)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zynq_design_1_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
Q(2 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8 downto 6),
S(0) => \gen_master_slots[2].reg_slice_mi_n_20\,
SR(0) => reset,
aa_mi_awtarget_hot(0) => aa_mi_awtarget_hot(2),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
chosen(2 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_1\(2 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[1]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\gen_master_slots[1].w_issuing_cnt_reg[10]\ => \gen_master_slots[1].reg_slice_mi_n_5\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38\,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0\ => \gen_master_slots[2].reg_slice_mi_n_30\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_22\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_23\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_24\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_25\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_26\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(2 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8 downto 6),
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0\(0) => \gen_master_slots[2].reg_slice_mi_n_27\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10\,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11\,
\gen_no_arbiter.m_target_hot_i_reg[2]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6\,
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_20,
\m_payload_i_reg[11]\ => \gen_master_slots[2].reg_slice_mi_n_28\,
\m_payload_i_reg[12]\ => \gen_master_slots[1].reg_slice_mi_n_23\,
\m_payload_i_reg[13]\ => \gen_master_slots[2].reg_slice_mi_n_29\,
\m_payload_i_reg[2]\ => \gen_master_slots[2].reg_slice_mi_n_13\,
\m_payload_i_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_12\,
\m_payload_i_reg[4]\ => \gen_master_slots[1].reg_slice_mi_n_20\,
\m_payload_i_reg[5]\ => \gen_master_slots[1].reg_slice_mi_n_21\,
\m_payload_i_reg[6]\ => \gen_master_slots[2].reg_slice_mi_n_19\,
\m_payload_i_reg[7]\ => \gen_master_slots[1].reg_slice_mi_n_22\,
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]_0\ => addr_arbiter_aw_n_14,
m_valid_i => m_valid_i_2,
m_valid_i_reg => \gen_master_slots[1].reg_slice_mi_n_6\,
p_38_out => p_38_out,
p_60_out => p_60_out,
p_80_out => p_80_out,
\s_axi_awaddr[31]\(27 downto 12) => D(31 downto 16),
\s_axi_awaddr[31]\(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0),
w_issuing_cnt(4) => w_issuing_cnt(16),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_multi_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8\,
SR(0) => reset,
aclk => aclk,
\gen_axi.write_cs_reg[1]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3\,
\gen_axi.write_cs_reg[1]_0\(0) => write_cs(1),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
m_ready_d(0) => m_ready_d(1),
p_14_in => p_14_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
st_aa_awtarget_hot(0) => st_aa_awtarget_hot(0)
);
splitter_aw_mi: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_splitter_3
port map (
aa_mi_awtarget_hot(2 downto 0) => aa_mi_awtarget_hot(2 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_3,
m_ready_d(1 downto 0) => m_ready_d_3(1 downto 0),
\m_ready_d_reg[0]_0\ => addr_arbiter_aw_n_21,
\m_ready_d_reg[0]_1\ => addr_arbiter_aw_n_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b11";
attribute P_ONES : string;
attribute P_ONES of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 63 downto 32 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(63 downto 32);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(63 downto 32);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(3 downto 2);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(3 downto 2);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(7 downto 4);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(7 downto 4);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(1) <= \^m_axi_arlock\(1);
m_axi_arlock(0) <= \^m_axi_arlock\(1);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(5 downto 3);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(5 downto 3);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(7 downto 4);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(7 downto 4);
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(5 downto 3);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(5 downto 3);
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(63 downto 32);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(3 downto 2);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(3 downto 2);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(7 downto 4);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(7 downto 4);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(15 downto 8);
m_axi_awlock(1) <= \^m_axi_awlock\(1);
m_axi_awlock(0) <= \^m_axi_awlock\(1);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(5 downto 3);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(5 downto 3);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(7 downto 4);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(7 downto 4);
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(5 downto 3);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(5 downto 3);
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52 downto 49) => s_axi_awcache(3 downto 0),
D(48 downto 47) => s_axi_awburst(1 downto 0),
D(46 downto 44) => s_axi_awprot(2 downto 0),
D(43) => s_axi_awlock(0),
D(42 downto 40) => s_axi_awsize(2 downto 0),
D(39 downto 32) => s_axi_awlen(7 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
M_AXI_RREADY(1 downto 0) => m_axi_rready(1 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(7 downto 4),
Q(64 downto 61) => \^m_axi_awcache\(7 downto 4),
Q(60 downto 59) => \^m_axi_awburst\(3 downto 2),
Q(58 downto 56) => \^m_axi_awprot\(5 downto 3),
Q(55) => \^m_axi_awlock\(1),
Q(54 downto 52) => \^m_axi_awsize\(5 downto 3),
Q(51 downto 44) => \^m_axi_awlen\(15 downto 8),
Q(43 downto 12) => \^m_axi_awaddr\(63 downto 32),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[7]\(68 downto 65) => \^m_axi_arqos\(7 downto 4),
\m_axi_arqos[7]\(64 downto 61) => \^m_axi_arcache\(7 downto 4),
\m_axi_arqos[7]\(60 downto 59) => \^m_axi_arburst\(3 downto 2),
\m_axi_arqos[7]\(58 downto 56) => \^m_axi_arprot\(5 downto 3),
\m_axi_arqos[7]\(55) => \^m_axi_arlock\(1),
\m_axi_arqos[7]\(54 downto 52) => \^m_axi_arsize\(5 downto 3),
\m_axi_arqos[7]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[7]\(43 downto 12) => \^m_axi_araddr\(63 downto 32),
\m_axi_arqos[7]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
\s_axi_arqos[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(52 downto 49) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(48 downto 47) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(46 downto 44) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(43) => s_axi_arlock(0),
\s_axi_arqos[3]\(42 downto 40) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(39 downto 32) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_xbar_0 : entity is "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end zynq_design_1_xbar_0;
architecture STRUCTURE of zynq_design_1_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "64'b0000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "64'b1111111111111111111111111111111111111111111111111111111111111111";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "64'b0000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 2;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "2'b11";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "2'b11";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zynq_design_1_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(63 downto 0) => m_axi_araddr(63 downto 0),
m_axi_arburst(3 downto 0) => m_axi_arburst(3 downto 0),
m_axi_arcache(7 downto 0) => m_axi_arcache(7 downto 0),
m_axi_arid(23 downto 0) => m_axi_arid(23 downto 0),
m_axi_arlen(15 downto 0) => m_axi_arlen(15 downto 0),
m_axi_arlock(1 downto 0) => m_axi_arlock(1 downto 0),
m_axi_arprot(5 downto 0) => m_axi_arprot(5 downto 0),
m_axi_arqos(7 downto 0) => m_axi_arqos(7 downto 0),
m_axi_arready(1 downto 0) => m_axi_arready(1 downto 0),
m_axi_arregion(7 downto 0) => m_axi_arregion(7 downto 0),
m_axi_arsize(5 downto 0) => m_axi_arsize(5 downto 0),
m_axi_aruser(1 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(1 downto 0),
m_axi_arvalid(1 downto 0) => m_axi_arvalid(1 downto 0),
m_axi_awaddr(63 downto 0) => m_axi_awaddr(63 downto 0),
m_axi_awburst(3 downto 0) => m_axi_awburst(3 downto 0),
m_axi_awcache(7 downto 0) => m_axi_awcache(7 downto 0),
m_axi_awid(23 downto 0) => m_axi_awid(23 downto 0),
m_axi_awlen(15 downto 0) => m_axi_awlen(15 downto 0),
m_axi_awlock(1 downto 0) => m_axi_awlock(1 downto 0),
m_axi_awprot(5 downto 0) => m_axi_awprot(5 downto 0),
m_axi_awqos(7 downto 0) => m_axi_awqos(7 downto 0),
m_axi_awready(1 downto 0) => m_axi_awready(1 downto 0),
m_axi_awregion(7 downto 0) => m_axi_awregion(7 downto 0),
m_axi_awsize(5 downto 0) => m_axi_awsize(5 downto 0),
m_axi_awuser(1 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(1 downto 0),
m_axi_awvalid(1 downto 0) => m_axi_awvalid(1 downto 0),
m_axi_bid(23 downto 0) => m_axi_bid(23 downto 0),
m_axi_bready(1 downto 0) => m_axi_bready(1 downto 0),
m_axi_bresp(3 downto 0) => m_axi_bresp(3 downto 0),
m_axi_buser(1 downto 0) => B"00",
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_rdata(63 downto 0) => m_axi_rdata(63 downto 0),
m_axi_rid(23 downto 0) => m_axi_rid(23 downto 0),
m_axi_rlast(1 downto 0) => m_axi_rlast(1 downto 0),
m_axi_rready(1 downto 0) => m_axi_rready(1 downto 0),
m_axi_rresp(3 downto 0) => m_axi_rresp(3 downto 0),
m_axi_ruser(1 downto 0) => B"00",
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
m_axi_wdata(63 downto 0) => m_axi_wdata(63 downto 0),
m_axi_wid(23 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(23 downto 0),
m_axi_wlast(1 downto 0) => m_axi_wlast(1 downto 0),
m_axi_wready(1 downto 0) => m_axi_wready(1 downto 0),
m_axi_wstrb(7 downto 0) => m_axi_wstrb(7 downto 0),
m_axi_wuser(1 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(1 downto 0),
m_axi_wvalid(1 downto 0) => m_axi_wvalid(1 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- 8-Color 100x37 Textmode Video Controller --
--------------------------------------------------------------------------------
-- This controller features a 800x600@72Hz resolution Textmode VGA with 100 --
-- characters per line and 37 lines. One out of 8 different colors can be --
-- assigned to every single character and the character's background --
-- respectivly. --
-- You can replace the character set with your own with <chars.py>. It takes --
-- a <*.bdf> file and translates the character map into a <rom.vhd> --
-- (Replaces the original!). --
-- --
-- For information about colors and usage consult <stdio.h> and <stdio.c>. --
-- --
-- REFERENCES --
-- --
-- [1] VGA Display Adapter --
-- <http://javiervalcarce.es/wiki/VHDL_Macro:_VGA80x40> --
-- Copyright 2007 by Javier Valcarce García --
-- [2] BDF Console Font File --
-- <http://www.ibiblio.org/pub/Linux/X11/fonts/> --
-- [3] Z80 System On A Chip --
-- <http://www.opencores.org/?do=project&who=z80soc> --
-- [4] Yet Another VGA --
-- <http://www.opencores.org/?do=project&who=yavga> --
-- [5] Xilinx Spartan 3E Starter Kit Board User Guide --
-- <http://www.xilinx.com/support/documentation/ --
-- spartan-3e_board_and_kit_documentation.htm> --
-- [6] Display resolution calculator --
-- <http://www.epanorama.net/faq/vga2rgb/calc.html> --
-- --
-- [7] Chu Pong P., FPGA Prototyping By VHDL Examples, --
-- John Wiley & Sons Inc., Hoboken, New Jersy, 2008, --
-- ISBN: 978-0470185315 --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
package ivga is
component vga is
port(
si : in slave_in_t;
so : out slave_out_t;
VGA_RED : out std_logic;
VGA_GREEN : out std_logic;
VGA_BLUE : out std_logic;
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic
);
end component;
end ivga; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
LEN : positive := 32
);
port(
input_a : in unsigned(LEN-1 downto 0);
input_b : in unsigned(LEN-1 downto 0);
output : out unsigned(LEN-1 downto 0)
);
end bug;
architecture behav of bug is
begin
output <= minimum(input_a, input_b);
end architecture;
|
----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- transmitter.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes 32bit (one sample) and sends it out on the serial port.
-- End of transmission is signalled by taking back the busy flag.
-- Supports xon/xoff flow control.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
generic (
FREQ : integer;
RATE : integer
);
Port (
data : in STD_LOGIC_VECTOR (31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : in std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : in STD_LOGIC;
trxClock : IN std_logic;
reset : in std_logic;
tx : out STD_LOGIC;
busy: out std_logic
-- pause: out std_logic
);
end transmitter;
architecture Behavioral of transmitter is
type TX_STATES is (IDLE, SEND, POLL);
constant BITLENGTH : integer := FREQ / RATE;
signal dataBuffer : STD_LOGIC_VECTOR (31 downto 0);
signal disabledBuffer : std_logic_vector (3 downto 0);
signal txBuffer : std_logic_vector (9 downto 0) := "1000000000";
signal byte : std_logic_vector (7 downto 0);
signal counter : integer range 0 to BITLENGTH;
signal bits : integer range 0 to 10;
signal bytes : integer range 0 to 4;
signal state : TX_STATES;
signal paused, writeByte, byteDone, disabled : std_logic;
begin
-- pause <= paused;
tx <= txBuffer(0);
-- sends one byte
process(clock)
begin
if rising_edge(clock) then
if writeByte = '1' then
counter <= 0;
bits <= 0;
byteDone <= disabled;
txBuffer <= '1' & byte & "0";
elsif counter = BITLENGTH then
counter <= 0;
txBuffer <= '1' & txBuffer(9 downto 1);
if bits = 10 then
byteDone <= '1';
else
bits <= bits + 1;
end if;
elsif trxClock = '1' then
counter <= counter + 1;
end if;
end if;
end process;
-- control mechanism for sending a 32 bit word
process(clock, reset)
begin
if reset = '1' then
writeByte <= '0';
state <= IDLE;
dataBuffer <= (others => '0');
disabledBuffer <= (others => '0');
elsif rising_edge(clock) then
if (state /= IDLE) or (write = '1') or (paused = '1') then
busy <= '1';
else
busy <= '0';
end if;
case state is
-- when write is '1', data will be available with next cycle
when IDLE =>
if write = '1' then
dataBuffer <= data;
disabledBuffer <= disabledGroups;
state <= SEND;
bytes <= 0;
elsif id = '1' then
dataBuffer <= x"534c4131";
disabledBuffer <= "0000";
state <= SEND;
bytes <= 0;
end if;
when SEND =>
if bytes = 4 then
state <= IDLE;
else
bytes <= bytes + 1;
case bytes is
when 0 =>
byte <= dataBuffer(7 downto 0);
disabled <= disabledBuffer(0);
when 1 =>
byte <= dataBuffer(15 downto 8);
disabled <= disabledBuffer(1);
when 2 =>
byte <= dataBuffer(23 downto 16);
disabled <= disabledBuffer(2);
when others =>
byte <= dataBuffer(31 downto 24);
disabled <= disabledBuffer(3);
end case;
writeByte <= '1';
state <= POLL;
end if;
when POLL =>
writeByte <= '0';
if byteDone = '1' and writeByte = '0' and paused = '0' then
state <= SEND;
end if;
end case;
end if;
end process;
-- set paused mode according to xon/xoff commands
process(clock, reset)
begin
if reset = '1' then
paused <= '0';
elsif rising_edge(clock) then
if xon = '1' then
paused <= '0';
elsif xoff = '1' then
paused <= '1';
end if;
end if;
end process;
end Behavioral;
|
entity test is
file foo : bar open qux;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata_inf
-- File: ata_inf.vhd
-- Author: Erik Jagres, Gaisler Research
-- Description: ATA components and signals
------------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ata.all;
use gaisler.misc.all;
package ata_inf is
type slv_to_bm_type is record
prd_belec: std_logic;
en : std_logic;
dir : std_logic;
prdtb : std_logic_vector(31 downto 0);
end record;
constant SLV_TO_BM_RESET_VECTOR : slv_to_bm_type := ('0','0','0',(others=>'0'));
type bm_to_slv_type is record
err : std_logic;
done : std_logic;
cur_base : std_logic_vector(31 downto 0);
cur_cnt : std_logic_vector(15 downto 0);
end record;
constant BM_TO_SLV_RESET_VECTOR : bm_to_slv_type :=
('0','0',(others=>'0'),(others=>'0'));
type bm_to_ctrl_type is record
force_rdy : std_logic;
sel : std_logic;
ack : std_logic;
end record;
constant BM_TO_CTR_RESET_VECTOR : bm_to_ctrl_type := ('0','0','0');
type ctrl_to_bm_type is record
irq : std_logic;
ack : std_logic;
req : std_logic;
rx_empty : std_logic;
fifo_rdy : std_logic;
q : std_logic_vector(31 downto 0);
tip : std_logic;
rx_full : std_logic;
end record;
constant DMA_IN_RESET_VECTOR : ahb_dma_in_type :=
((others=>'0'),(others=>'0'),'0','0','0','0','0',"10");
type bmi_type is record
fr_mst : ahb_dma_out_type;
fr_slv : slv_to_bm_type;
fr_ctr : ctrl_to_bm_type;
end record;
type bmo_type is record
to_mst : ahb_dma_in_type;
to_slv : bm_to_slv_type;
to_ctr : bm_to_ctrl_type;
d : std_logic_vector(31 downto 0);
we : std_logic;
end record;
constant BMO_RESET_VECTOR : bmo_type :=
(DMA_IN_RESET_VECTOR,BM_TO_SLV_RESET_VECTOR,BM_TO_CTR_RESET_VECTOR,(others=>'0'),'0');
end ata_inf;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ata_inf
-- File: ata_inf.vhd
-- Author: Erik Jagres, Gaisler Research
-- Description: ATA components and signals
------------------------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.ata.all;
use gaisler.misc.all;
package ata_inf is
type slv_to_bm_type is record
prd_belec: std_logic;
en : std_logic;
dir : std_logic;
prdtb : std_logic_vector(31 downto 0);
end record;
constant SLV_TO_BM_RESET_VECTOR : slv_to_bm_type := ('0','0','0',(others=>'0'));
type bm_to_slv_type is record
err : std_logic;
done : std_logic;
cur_base : std_logic_vector(31 downto 0);
cur_cnt : std_logic_vector(15 downto 0);
end record;
constant BM_TO_SLV_RESET_VECTOR : bm_to_slv_type :=
('0','0',(others=>'0'),(others=>'0'));
type bm_to_ctrl_type is record
force_rdy : std_logic;
sel : std_logic;
ack : std_logic;
end record;
constant BM_TO_CTR_RESET_VECTOR : bm_to_ctrl_type := ('0','0','0');
type ctrl_to_bm_type is record
irq : std_logic;
ack : std_logic;
req : std_logic;
rx_empty : std_logic;
fifo_rdy : std_logic;
q : std_logic_vector(31 downto 0);
tip : std_logic;
rx_full : std_logic;
end record;
constant DMA_IN_RESET_VECTOR : ahb_dma_in_type :=
((others=>'0'),(others=>'0'),'0','0','0','0','0',"10");
type bmi_type is record
fr_mst : ahb_dma_out_type;
fr_slv : slv_to_bm_type;
fr_ctr : ctrl_to_bm_type;
end record;
type bmo_type is record
to_mst : ahb_dma_in_type;
to_slv : bm_to_slv_type;
to_ctr : bm_to_ctrl_type;
d : std_logic_vector(31 downto 0);
we : std_logic;
end record;
constant BMO_RESET_VECTOR : bmo_type :=
(DMA_IN_RESET_VECTOR,BM_TO_SLV_RESET_VECTOR,BM_TO_CTR_RESET_VECTOR,(others=>'0'),'0');
end ata_inf;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_tb IS
END ENTITY;
ARCHITECTURE RxTstFIFO2K_arch OF RxTstFIFO2K_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from RxTstFIFO2K_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of RxTstFIFO2K_synth
RxTstFIFO2K_synth_inst:RxTstFIFO2K_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_tb IS
END ENTITY;
ARCHITECTURE RxTstFIFO2K_arch OF RxTstFIFO2K_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from RxTstFIFO2K_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of RxTstFIFO2K_synth
RxTstFIFO2K_synth_inst:RxTstFIFO2K_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
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`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ixyOv8Pmp3S61di4DQ6x5jA6IQZ0VaPGFUSTXTTniEX8J/GPlhxRmszVLTBCjyCoPRPbr93iqRTQ
AZ7oFvQqgA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
mQ6ysyeEWGf76isegQ4+74xXTeIi4tkltnr0qsbqsrsP6dOX/fMWPSAoN4CkTpW2nS1DJ+cEMO9n
IvETV0bv19ngFn3J3bR+3VREvm5lYhGgvw73ucJdTtlPEI09kCV0TTxRV6UbDpTMcVeKTw0e4fur
C/y+uBFR750wd9EtTfE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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vrwi9X54QLsn7vH7IJhZTOdbVy4ihG6vrjkG/Q==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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qzPu5OEUKVv67GUQlu0=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cgWYPqfFogDbUrcMtbzX7tO8eOqiHJ5319TNcYTxFPi6743IsBD8KMmJXfNGImBA0pxiiGX0f6bi
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Nthz3bIthiEdI4I2rGlzJt/5Yr+OvHtNQ/O6Lw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_06 is
end entity inline_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of inline_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity logic_analyzer_32 is
generic (
g_big_endian : boolean;
g_timer_div : positive := 50 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(7 downto 0);
task : out std_logic_vector(3 downto 0);
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer_32;
architecture gideon of logic_analyzer_32 is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(15 downto 0);
signal ev_data_d : std_logic_vector(15 downto 0);
signal ev_wdata : std_logic_vector(31 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
type t_state is (idle, writing);
signal state : t_state;
signal sub, task_i : std_logic_vector(3 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= sub & task_i & ev_data;
case state is
when idle =>
if ev_dav='1' or ev_tick='1' then
if (ev_data_c /= ev_data_d) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
ev_data_d <= ev_data_c;
stamp <= (others => '0');
if enable_log = '1' then
state <= writing;
end if;
end if;
end if;
when writing =>
mem_req.data <= byte_swap(ev_wdata, g_big_endian);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
mem_req.request <= '0';
state <= idle;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
if g_big_endian then
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task_i;
when others =>
null;
end case;
else
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task_i;
when others =>
null;
end case;
end if;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "111" =>
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
when "110" =>
enable_log <= '0';
when "101" =>
task_i <= io_req.data(3 downto 0);
when "100" =>
sub <= io_req.data(3 downto 0);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
sub <= X"0";
task_i <= X"0";
enable_log <= '0';
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
task <= task_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity transmitter_tb is
end entity transmitter_tb;
architecture rtl of transmitter_tb is
component transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic
);
end component transmitter;
signal clk : std_logic;
signal rst : std_logic;
signal frequency : std_logic_vector(31 downto 0);
signal frequency_stb : std_logic;
signal frequency_ack : std_logic;
signal control : std_logic_vector(31 downto 0);
signal control_stb : std_logic;
signal control_ack : std_logic;
signal amplitude : std_logic_vector(31 downto 0);
signal amplitude_stb : std_logic;
signal amplitude_ack : std_logic;
signal rf : std_logic;
begin
process
begin
clk <= '0';
while True loop
wait for 5 ns;
clk <= not clk;
end loop;
wait;
end process;
process
begin
rst <= '0';
wait for 20 ns;
rst <= '1';
wait;
end process;
process
file stimulus: TEXT open read_mode is "stim.txt";
variable l : LINE;
variable x : integer;
begin
while not endfile(stimulus) loop
readline(stimulus, l);
read(l, x);
amplitude <= (others => '0');
amplitude(7 downto 0) <= std_logic_vector(to_signed(x, 8));
amplitude(23 downto 16) <= std_logic_vector(to_signed(x, 8));
wait until rising_edge(clk) and amplitude_ack = '1';
end loop;
wait;
end process;
frequency <= X"000FFFFF";
control <= X"00000000";
amplitude_stb <= '1';
frequency_stb <= '1';
control_stb <= '1';
uut : transmitter port map(
clk => clk,
rst => rst,
frequency => frequency,
frequency_stb => frequency_stb,
frequency_ack => frequency_ack,
control => control,
control_stb => control_stb,
control_ack => control_ack,
amplitude => amplitude,
amplitude_stb => amplitude_stb,
amplitude_ack => amplitude_ack,
rf => rf
);
end rtl;
|
-- NEED RESULT: ARCH00513: One or many instantiation labels may appear in an instantiation list of a configuration spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00513
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (1)
-- 5.2.1 (1)
-- 5.2.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00513(ARCH00513)
-- ENT00513_Test_Bench(ARCH00513_Test_Bench)
--
-- REVISION HISTORY:
--
-- 11-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00513 is
generic ( G : boolean ) ;
port ( P : in boolean ;
Q : out boolean := G) ;
end ENT00513 ;
architecture ARCH00513 of ENT00513 is
begin
process ( P )
variable First_Time : boolean := true ;
begin
if First_Time then
First_Time := false ;
else
Q <= transport Not P after 10 ns ;
end if ;
end process ;
end ARCH00513 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00513_Test_Bench is
end ENT00513_Test_Bench ;
architecture ARCH00513_Test_Bench of ENT00513_Test_Bench is
begin
L1:
block
component UUT generic ( G : boolean) ;
port ( P : in boolean ;
Q : out boolean ) ;
end component ;
signal S : boolean_vector ( 1 to 5 ) := (False,True,False,True,False) ;
alias S1 : boolean is S(1) ;
alias S2 : boolean is S(2) ;
alias S3 : boolean is S(3) ;
alias S4 : boolean is S(4) ;
alias S5 : boolean is S(5) ;
for CIS1 : UUT use entity WORK.ENT00513 ( ARCH00513 ) ;
for CIS2, CIS3, CIS4 : UUT use entity WORK.ENT00513 ( ARCH00513 ) ;
begin
S(1) <= transport True after 0 ns ;
CIS1 : UUT generic map (true) port map (s1, s2) ;
CIS2 : UUT generic map (false) port map (s2, s3) ;
CIS3 : UUT generic map (true) port map (s3, s4) ;
CIS4 : UUT generic map (false) port map (s4, s5) ;
Check_It :
process
begin
wait for 100 ns ;
test_report ( "ARCH00513" ,
"One or many instantiation labels may appear "&
"in an instantiation list of a configuration spec" ,
s1 and (Not s2) and s3 and (Not s4) and s5 ) ;
wait ;
end process Check_It ;
end block L1 ;
end ARCH00513_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2177.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02177ent IS
END c07s02b05x00p01n01i02177ent;
ARCHITECTURE c07s02b05x00p01n01i02177arch OF c07s02b05x00p01n01i02177ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := + p2;
BEGIN
assert NOT(a = 10 p1)
report "***PASSED TEST: c07s02b05x00p01n01i02177"
severity NOTE;
assert (a = 10 p1)
report "***FAILED TEST: c07s02b05x00p01n01i02177 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02177arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2177.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02177ent IS
END c07s02b05x00p01n01i02177ent;
ARCHITECTURE c07s02b05x00p01n01i02177arch OF c07s02b05x00p01n01i02177ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := + p2;
BEGIN
assert NOT(a = 10 p1)
report "***PASSED TEST: c07s02b05x00p01n01i02177"
severity NOTE;
assert (a = 10 p1)
report "***FAILED TEST: c07s02b05x00p01n01i02177 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02177arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2177.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02177ent IS
END c07s02b05x00p01n01i02177ent;
ARCHITECTURE c07s02b05x00p01n01i02177arch OF c07s02b05x00p01n01i02177ent IS
BEGIN
TESTING: PROCESS
type phys is range -10 to 100
units
p1;
p2 = 10 p1;
p3 = 5 p2;
end units;
constant a : phys := + p2;
BEGIN
assert NOT(a = 10 p1)
report "***PASSED TEST: c07s02b05x00p01n01i02177"
severity NOTE;
assert (a = 10 p1)
report "***FAILED TEST: c07s02b05x00p01n01i02177 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02177arch;
|
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is created from 2 Block RAMs of size 2048
-- words of 8-bits per word, giving a total frame memory capacity
-- of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The write clock (user-side
-- AxiStream clock) can be an equal or faster frequency than the
-- read clock (MAC-side AxiStream clock). The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library unimacro;
use unimacro.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end temac_10_100_1000_tx_client_fifo;
architecture RTL of temac_10_100_1000_tx_client_fifo is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
signal VCC : std_logic;
signal GND : std_logic_vector(0 downto 0);
signal GND_BUS : std_logic_vector(8 downto 0);
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_en_u : std_logic;
signal wr_en_u_bram : std_logic_vector(0 downto 0);
signal wr_en_l : std_logic;
signal wr_en_l_bram : std_logic_vector(0 downto 0);
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal frame_in_fifo : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_bram_u_unused : std_logic_vector(8 downto 0);
signal rd_bram_l_unused : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_u : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_l : std_logic_vector(8 downto 0);
signal rd_data_bram_u : std_logic_vector(7 downto 0);
signal rd_data_bram_l : std_logic_vector(7 downto 0);
signal rd_data_pipe_u : std_logic_vector(7 downto 0);
signal rd_data_pipe_l : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_eof_bram_u : std_logic_vector(0 downto 0);
signal rd_eof_bram_l : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_bram_u : std_logic;
signal rd_bram_u_reg : std_logic;
signal rd_addr_slv : std_logic_vector(10 downto 0);
signal wr_addr_slv : std_logic_vector(10 downto 0);
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0);
signal wr_frame_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0);
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0);
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0);
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0);
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0);
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
VCC <= '1';
GND <= (others => '0');
GND_BUS <= (others => '0');
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
-- The upper and lower signals are used to distinguish between the upper and
-- lower BRAMs.
wr_en_l <= wr_en and not(wr_addr(11));
wr_en_u <= wr_en and wr_addr(11);
wr_en_l_bram(0) <= wr_en_l;
wr_en_u_bram(0) <= wr_en_u;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = DATA_PRELOAD1_s and rd_nxt_state = FRAME_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : temac_10_100_1000_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
-- Which BRAM is read from is dependant on the upper bit of the address
-- space. This needs to be registered to give the correct timing.
rd_bram_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_bram_u <= '0' after dly;
rd_bram_u_reg <= '0' after dly;
else
if rd_addr_inc = '1' then
rd_bram_u <= rd_addr(11) after dly;
rd_bram_u_reg <= rd_bram_u after dly;
end if;
end if;
end if;
end process rd_bram_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_pipe_u <= rd_data_bram_u after dly;
rd_data_pipe_l <= rd_data_bram_l after dly;
if rd_bram_u_reg = '1' then
rd_data_pipe <= rd_data_pipe_u after dly;
else
rd_data_pipe <= rd_data_pipe_l after dly;
end if;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
if rd_bram_u = '1' then
rd_eof_pipe <= rd_eof_bram_u(0) after dly;
else
rd_eof_pipe <= rd_eof_bram_l(0) after dly;
end if;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
wr_addr_slv <= std_logic_vector(wr_addr(10 downto 0));
rd_addr_slv <= std_logic_vector(rd_addr(10 downto 0));
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_l(0) <= rd_eof_data_bram_l(8);
rd_data_bram_l <= rd_eof_data_bram_l(7 downto 0);
ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_l_bram,
WEB => GND
);
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_u(0) <= rd_eof_data_bram_u(8);
rd_data_bram_u <= rd_eof_data_bram_u(7 downto 0);
ramgen_u : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_u_unused,
DOB => rd_eof_data_bram_u,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_u_bram,
WEB => GND
);
end RTL;
|
--------------------------------------------------------------------------------
-- Title : Transmitter FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : temac_10_100_1000_tx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is a transmitter side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is created from 2 Block RAMs of size 2048
-- words of 8-bits per word, giving a total frame memory capacity
-- of 4096 bytes.
--
-- Valid frame data received from the user interface is written
-- into the Block RAM on the tx_fifo_aclkk. The FIFO will store
-- frames up to 4kbytes in length. If larger frames are written
-- to the FIFO, the AxiStream interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and the
-- overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO, the MAC
-- transmitter AxiStream interface will be driven to request frame
-- transmission by placing the first byte of the frame onto
-- tx_axis_mac_tdata and by asserting tx_axis_mac_tvalid. The MAC will later
-- respond by asserting tx_axis_mac_tready. At this point the remaining
-- frame data is read out of the FIFO subject to tx_axis_mac_tready.
-- Data is read out of the FIFO on the tx_mac_aclk.
--
-- If the generic FULL_DUPLEX_ONLY is set to false, the FIFO will
-- requeue and retransmit frames as requested by the MAC. Once a
-- frame has been transmitted by the FIFO it is stored until the
-- possible retransmit window for that frame has expired.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The write clock (user-side
-- AxiStream clock) can be an equal or faster frequency than the
-- read clock (MAC-side AxiStream clock). The minimum write clock
-- frequency is the read clock frequency divided by 2.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
--------------------------------------------------------------------------------
library unimacro;
use unimacro.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- Entity declaration for the Transmitter FIFO
--------------------------------------------------------------------------------
entity temac_10_100_1000_tx_client_fifo is
generic (
FULL_DUPLEX_ONLY : boolean := false);
port (
-- User-side (write-side) AxiStream interface
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
-- MAC-side (read-side) AxiStream interface
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (tx_user_aclk) interface
fifo_overflow : out std_logic;
fifo_status : out std_logic_vector(3 downto 0);
-- FIFO collision and retransmission requests from MAC
tx_collision : in std_logic;
tx_retransmit : in std_logic
);
end temac_10_100_1000_tx_client_fifo;
architecture RTL of temac_10_100_1000_tx_client_fifo is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component temac_10_100_1000_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
signal VCC : std_logic;
signal GND : std_logic_vector(0 downto 0);
signal GND_BUS : std_logic_vector(8 downto 0);
-- Encoded read state machine states.
type rd_state_typ is (IDLE_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
START_DATA1_s,
DATA_PRELOAD1_s,
DATA_PRELOAD2_s,
WAIT_HANDSHAKE_s,
FRAME_s,
HANDSHAKE_s,
FINISH_s,
DROP_ERR_s,
DROP_s,
RETRANSMIT_ERR_s,
RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states,
type wr_state_typ is (WAIT_s,
DATA_s,
EOF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array (0 to 1) of std_logic;
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_sof_int : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_eof_reg : std_logic;
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_en_u : std_logic;
signal wr_en_u_bram : std_logic_vector(0 downto 0);
signal wr_en_l : std_logic;
signal wr_en_l_bram : std_logic_vector(0 downto 0);
signal wr_ovflow_dst_rdy : std_logic;
signal tx_axis_fifo_tready_int_n : std_logic;
signal frame_in_fifo : std_logic;
signal rd_eof : std_logic;
signal rd_eof_pipe : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_bram_u_unused : std_logic_vector(8 downto 0);
signal rd_bram_l_unused : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_u : std_logic_vector(8 downto 0);
signal rd_eof_data_bram_l : std_logic_vector(8 downto 0);
signal rd_data_bram_u : std_logic_vector(7 downto 0);
signal rd_data_bram_l : std_logic_vector(7 downto 0);
signal rd_data_pipe_u : std_logic_vector(7 downto 0);
signal rd_data_pipe_l : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_eof_bram_u : std_logic_vector(0 downto 0);
signal rd_eof_bram_l : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_bram_u : std_logic;
signal rd_bram_u_reg : std_logic;
signal rd_addr_slv : std_logic_vector(10 downto 0);
signal wr_addr_slv : std_logic_vector(10 downto 0);
signal rd_tran_frame_tog : std_logic := '0';
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic := '0';
signal rd_retran_frame_tog : std_logic := '0';
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic := '0';
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : unsigned(8 downto 0);
signal wr_frame_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0);
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0);
signal rd_txfer_tog : std_logic := '0';
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic := '0';
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0);
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0);
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0);
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal tx_axis_mac_tdata_int_frame : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int_handshake : std_logic_vector(7 downto 0);
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int_finish : std_logic;
signal tx_axis_mac_tvalid_int_droperr : std_logic;
signal tx_axis_mac_tvalid_int_retransmiterr : std_logic;
signal tx_axis_mac_tlast_int_frame_handshake : std_logic;
signal tx_axis_mac_tlast_int_finish : std_logic;
signal tx_axis_mac_tlast_int_droperr : std_logic;
signal tx_axis_mac_tlast_int_retransmiterr : std_logic;
signal tx_axis_mac_tuser_int_droperr : std_logic;
signal tx_axis_mac_tuser_int_retransmit : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_mac_reset : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
------------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
------------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
------------------------------------------------------------------------------
-- Begin FIFO architecture
------------------------------------------------------------------------------
begin
VCC <= '1';
GND <= (others => '0');
GND_BUS <= (others => '0');
-- invert reset sense as architecture is optimised for active high resets
tx_fifo_reset <= not tx_fifo_resetn;
tx_mac_reset <= not tx_mac_resetn;
------------------------------------------------------------------------------
-- Write state machine and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are WAIT, DATA, EOF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinitorial.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe(0), wr_eof_pipe(1),
wr_eof_bram(0), wr_fifo_overflow)
begin
case wr_state is
when WAIT_s =>
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- Wait for the end of frame to be detected.
if wr_fifo_overflow = '1' and wr_eof_pipe(0) = '0'
and wr_eof_pipe(1) = '0' then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- If the start of frame is already in the pipe, a back-to-back frame
-- transmission has occured. Move straight back to frame state.
if wr_sof_pipe(1) = '1' and wr_eof_pipe(1) = '0' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- Wait until the end of frame is reached before clearing the overflow.
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- Decode output signals, combinatorial.
-- wr_en is used to enable the BRAM write and the address to increment.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
-- The upper and lower signals are used to distinguish between the upper and
-- lower BRAMs.
wr_en_l <= wr_en and not(wr_addr(11));
wr_en_u <= wr_en and wr_addr(11);
wr_en_l_bram(0) <= wr_en_l;
wr_en_u_bram(0) <= wr_en_u;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s
else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s
else '0';
-- Pause the AxiStream handshake when the FIFO is full.
tx_axis_fifo_tready_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s
else wr_fifo_full;
tx_axis_fifo_tready <= not tx_axis_fifo_tready_int_n;
-- Generate user overflow indicator.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
-- When in overflow and have captured ovflow EOF, set tx_axis_fifo_tready again.
p_ovflow_dst_rdy : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tlast = '1' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- EOF signals for use in overflow logic.
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Read state machine and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are IDLE, QUEUE1, QUEUE2, QUEUE3, QUEUE_ACK, WAIT_ACK, FRAME,
-- HANDSHAKE, FINISH, DROP_ERR, DROP, RETRANSMIT_ERR, RETRANSMIT.
-- Clock state to next state.
clock_rds_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_state <= IDLE_s after dly;
else
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
------------------------------------------------------------------------------
-- Full duplex-only state machine.
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rd_eof_reg, tx_axis_mac_tready)
begin
case rd_state is
when IDLE_s =>
-- If there is a frame in the FIFO, start to queue the new frame
-- to the output.
if frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= START_DATA1_s;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_PRELOAD1_s;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when FRAME_s =>
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
if tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
------------------------------------------------------------------------------
-- Full and half duplex state machine.
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Decode the next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof_reg, tx_axis_mac_tready,
rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- If a retransmit request is detected then prepare to retransmit.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- If there is a frame in the FIFO, then queue the new frame to
-- the output.
elsif frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= START_DATA1_s;
end if;
when START_DATA1_s =>
-- The pipeline is full and the frame output starts now.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD1_s =>
-- Await the tx_axis_mac_tready acknowledge before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= DATA_PRELOAD2_s;
else
rd_nxt_state <= DATA_PRELOAD1_s;
end if;
when DATA_PRELOAD2_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= WAIT_HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= DATA_PRELOAD2_s;
end if;
when WAIT_HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_HANDSHAKE_s;
end if;
when FRAME_s =>
-- If a collision-only request, then must drop the rest of the
-- current frame. If a collision and retransmit, then prepare
-- to retransmit the frame.
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_ERR_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
-- Read the frame out of the FIFO. If the MAC deasserts
-- tx_axis_mac_tready, stall in the handshake state. If the EOF
-- flag is encountered, move to the finish state.
elsif tx_axis_mac_tready = '0' then
rd_nxt_state <= HANDSHAKE_s;
elsif rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
else
rd_nxt_state <= FRAME_s;
end if;
when HANDSHAKE_s =>
-- Await tx_axis_mac_tready before continuing frame transmission.
-- If the EOF flag is encountered, move to the finish state.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '1' then
rd_nxt_state <= FINISH_s;
elsif tx_axis_mac_tready = '1' and rd_eof_reg = '0' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= HANDSHAKE_s;
end if;
when FINISH_s =>
-- Frame has finished. Assure that the MAC has accepted the final
-- byte by transitioning to idle only when tx_axis_mac_tready is high.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_ERR_s;
elsif tx_axis_mac_tready = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FINISH_s;
end if;
when DROP_ERR_s =>
-- FIFO is ready to drop the frame. Assure that the MAC has
-- accepted the final byte and err signal before dropping.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= DROP_s;
else
rd_nxt_state <= DROP_ERR_s;
end if;
when DROP_s =>
-- Wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_ERR_s =>
-- FIFO is ready to retransmit the frame. Assure that the MAC has
-- accepted the final byte and err signal before retransmitting.
if tx_axis_mac_tready = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= RETRANSMIT_ERR_s;
end if;
when RETRANSMIT_s =>
-- Reload the data pipeline from the start of the frame.
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- Combinatorially select tdata candidates.
tx_axis_mac_tdata_int_frame <= tx_axis_mac_tdata_int when rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s
else rd_data_pipe;
tx_axis_mac_tdata_int_handshake <= rd_data_pipe when rd_nxt_state = FINISH_s
else tx_axis_mac_tdata_int;
tx_axis_mac_tdata <= tx_axis_mac_tdata_int;
-- Decode output tdata based on current and next read state.
rd_data_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tdata_int <= rd_data_pipe after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_frame after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int_handshake after dly;
when others =>
tx_axis_mac_tdata_int <= tx_axis_mac_tdata_int after dly;
end case;
end if;
end if;
end process rd_data_decode_p;
-- Combinatorially select tvalid candidates.
tx_axis_mac_tvalid_int_finish <= '0' when rd_nxt_state = IDLE_s
else '1';
tx_axis_mac_tvalid_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tvalid_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tvalid based on current and next read state.
rd_dv_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tvalid <= '1' after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tvalid <= '1' after dly;
else
case rd_state is
when START_DATA1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when DATA_PRELOAD1_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tvalid <= '1' after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tvalid <= '1' after dly;
when FINISH_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tvalid <= tx_axis_mac_tvalid_int_retransmiterr after dly;
when others =>
tx_axis_mac_tvalid <= '0' after dly;
end case;
end if;
end if;
end process rd_dv_decode_p;
-- Combinatorially select tlast candidates.
tx_axis_mac_tlast_int_frame_handshake <= rd_eof_reg when rd_nxt_state = FINISH_s
else '0';
tx_axis_mac_tlast_int_finish <= '0' when rd_nxt_state = IDLE_s
else rd_eof_reg;
tx_axis_mac_tlast_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tlast_int_retransmiterr <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tlast based on current and next read state.
rd_last_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s then
tx_axis_mac_tlast <= rd_eof after dly;
elsif (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tlast <= '1' after dly;
else
case rd_state is
when DATA_PRELOAD1_s =>
tx_axis_mac_tlast <= rd_eof after dly;
when FRAME_s | DATA_PRELOAD2_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when HANDSHAKE_s | WAIT_HANDSHAKE_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_frame_handshake after dly;
when FINISH_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_finish after dly;
when DROP_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tlast <= tx_axis_mac_tlast_int_retransmiterr after dly;
when others =>
tx_axis_mac_tlast <= '0' after dly;
end case;
end if;
end if;
end process rd_last_decode_p;
-- Combinatorially select tuser candidates.
tx_axis_mac_tuser_int_droperr <= '0' when rd_nxt_state = DROP_s
else '1';
tx_axis_mac_tuser_int_retransmit <= '0' when rd_nxt_state = RETRANSMIT_s
else '1';
-- Decode output tuser based on current and next read state.
rd_user_decode_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if (rd_nxt_state = RETRANSMIT_ERR_s or rd_nxt_state = DROP_ERR_s)
then tx_axis_mac_tuser <= '1' after dly;
else
case rd_state is
when DROP_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_droperr after dly;
when RETRANSMIT_ERR_s =>
tx_axis_mac_tuser <= tx_axis_mac_tuser_int_retransmit after dly;
when others =>
tx_axis_mac_tuser <= '0' after dly;
end case;
end if;
end if;
end process rd_user_decode_p;
------------------------------------------------------------------------------
-- Decode full duplex-only control signals.
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when rd_nxt_state = HANDSHAKE_s else
'0' when rd_state = FINISH_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = DATA_PRELOAD1_s and rd_nxt_state = FRAME_s
else '0';
-- Unused for full duplex only.
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
------------------------------------------------------------------------------
-- Decode full and half duplex control signals.
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en <= '0' when rd_state = IDLE_s else
'0' when rd_nxt_state = DROP_ERR_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s or rd_nxt_state = DATA_PRELOAD2_s else
'0' when (rd_state = DATA_PRELOAD2_s and rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when (rd_state = FRAME_s and rd_nxt_state = HANDSHAKE_s) else
'0' when (rd_nxt_state = HANDSHAKE_s or rd_nxt_state = WAIT_HANDSHAKE_s) else
'0' when rd_state = FINISH_s else
'0' when rd_state = RETRANSMIT_ERR_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = DATA_PRELOAD1_s else '1';
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state /= FINISH_s and rd_nxt_state = FINISH_s
else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s
else '0';
-- Assertion indicates that the starting address must be reloaded to enable
-- the current frame to be retransmitted.
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state= WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than once per 64 clocks to
-- allow toggle to cross clock domain.
rd_transmit_frame <= '1' when rd_state = WAIT_HANDSHAKE_s and rd_nxt_state = FRAME_s
else '0';
-- Retransmit frame pulse must never be more frequent than once per 16 clocks
-- to allow toggle to cross clock domain.
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode; -- half duplex control signals
------------------------------------------------------------------------------
-- Frame count
-- We need to maintain a count of frames in the FIFO, so that we know when a
-- frame is available for transmission. The counter must be held on the write
-- clock domain as this is the faster clock if they differ.
------------------------------------------------------------------------------
-- A frame has been written to the FIFO.
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s
else '0';
-- Generate a toggle to indicate when a frame has been transmitted by the FIFO.
p_rd_trans_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read transmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_tran_frame_tog,
data_out => wr_tran_frame_sync
);
-- Edge-detect of the resynchronized transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_transmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
------------------------------------------------------------------------------
-- Full duplex-only frame count.
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock if they differ.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
------------------------------------------------------------------------------
-- Full and half duplex frame count.
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Generate a toggle to indicate when a frame has been retransmitted from
-- the FIFO.
p_rd_retran_tog : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end process;
-- Synchronize the read retransmit frame signal into the write clock domain.
resync_rd_tran_frame_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_retran_frame_tog,
data_out => wr_retran_frame_sync
);
-- Edge detect of the resynchronized read transmit frame signal.
p_delay_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
end if;
end process p_delay_wr_trans;
p_sync_wr_trans : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_retransmit_frame <= '0' after dly;
else
-- Edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- Count the number of frames in the FIFO. The counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is
-- transmitted. Need to keep the counter on the write clock as this is the
-- fastest clock if they differ. Logic assumes transmit and retransmit cannot
-- happen at same time.
p_wr_frames : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame)
and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- Generate a frame in FIFO signal for use in control logic.
p_wr_avail : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- Synchronize it back onto read domain for use in the read logic.
resync_wr_frame_in_fifo : temac_10_100_1000_sync_block
port map (
clk => tx_mac_aclk,
data_in => wr_frame_in_fifo,
data_out => frame_in_fifo
);
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when write enable signal has been asserted
wr_addr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- Store the start address in case the address must be reset.
wr_staddr_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
------------------------------------------------------------------------------
-- Half duplex-only read address counters.
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- Do not need to keep a start address, but the address is needed to
-- calculate FIFO occupancy.
rd_start_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
------------------------------------------------------------------------------
-- Full and half duplex read address counters
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Read address is incremented when read enable signal has been asserted.
rd_addr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_addr <= (others => '0') after dly;
else
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_start_addr <= (others => '0') after dly;
else
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 6 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1Gbps. Also if the end of frame has fully
-- been transmitted by the MAC then a collision cannot occur. This collision
-- expiration signal goes high at 768 cycles from the start of the frame.
-- This is inefficient for short frames, however it should be enough to
-- prevent the FIFO from locking up.
rd_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_col_window_expire <= '0' after dly;
else
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 7) = "110" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_col_window_pipe(0) <= rd_col_window_expire
and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end process;
rd_slot_time_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
-- Will not count until after the first frame is sent.
if tx_mac_reset = '1' then
rd_slot_timer <= "1111111111" after dly;
else
-- Reset counter.
if rd_transmit_frame = '1' then
rd_slot_timer <= (others => '0') after dly;
-- Do not allow counter to roll over, and
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-- Read address generation
rd_decaddr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_dec_addr <= (others => '0') after dly;
else
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
-- Which BRAM is read from is dependant on the upper bit of the address
-- space. This needs to be registered to give the correct timing.
rd_bram_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if tx_mac_reset = '1' then
rd_bram_u <= '0' after dly;
rd_bram_u_reg <= '0' after dly;
else
if rd_addr_inc = '1' then
rd_bram_u <= rd_addr(11) after dly;
rd_bram_u_reg <= rd_bram_u after dly;
end if;
end if;
end if;
end process rd_bram_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_data_pipe(0) <= tx_axis_fifo_tdata after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- Start of frame set when tvalid is asserted and previous frame has ended.
wr_sof_int <= tx_axis_fifo_tvalid and wr_eof_reg;
-- Set end of frame flag when tlast and tvalid are asserted together.
-- Reset to logic 1 to enable first frame's start of frame flag.
reg_eofreg_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if tx_fifo_reset = '1' then
wr_eof_reg <= '1';
else
if tx_axis_fifo_tvalid = '1' and tx_axis_fifo_tready_int_n = '0' then
wr_eof_reg <= tx_axis_fifo_tlast;
end if;
end if;
end if;
end process reg_eofreg_p;
-- Pipeline the start of frame flag when the pipe is enabled.
reg_sof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_sof_pipe(0) <= wr_sof_int after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
-- Pipeline the pipeline enable signal, which is derived from simultaneous
-- assertion of tvalid and tready.
reg_acc_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
if (tx_fifo_reset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= tx_axis_fifo_tvalid and (not tx_axis_fifo_tready_int_n) after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
-- Pipeline the end of frame flag when the pipe is enabled.
reg_eof_p : process(tx_fifo_aclk)
begin
if (tx_fifo_aclk'event and tx_fifo_aclk = '1') then
wr_eof_pipe(0) <= tx_axis_fifo_tvalid and tx_axis_fifo_tlast after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- Register data outputs from BRAM.
-- No resets to allow SRL16 target.
reg_dout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
rd_data_pipe_u <= rd_data_bram_u after dly;
rd_data_pipe_l <= rd_data_bram_l after dly;
if rd_bram_u_reg = '1' then
rd_data_pipe <= rd_data_pipe_u after dly;
else
rd_data_pipe <= rd_data_pipe_l after dly;
end if;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
if rd_en = '1' then
if rd_bram_u = '1' then
rd_eof_pipe <= rd_eof_bram_u(0) after dly;
else
rd_eof_pipe <= rd_eof_bram_l(0) after dly;
end if;
rd_eof <= rd_eof_pipe after dly;
rd_eof_reg <= rd_eof or rd_eof_pipe after dly;
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Half duplex-only drop and retransmission controls.
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- Register the collision without retransmit signal, which is a pulse that
-- causes the FIFO to drop the frame.
reg_col_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_drop_frame <= tx_collision and (not tx_retransmit) after dly;
end if;
end process reg_col_p;
-- Register the collision with retransmit signal, which is a pulse that
-- causes the FIFO to retransmit the frame.
reg_retr_p : process(tx_mac_aclk)
begin
if (tx_mac_aclk'event and tx_mac_aclk = '1') then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end process reg_retr_p;
end generate gen_hd_input;
------------------------------------------------------------------------------
-- FIFO full functionality
------------------------------------------------------------------------------
-- Full functionality is the difference between read and write addresses.
-- We cannot use gray code this time as the read address and read start
-- addresses jump by more than 1.
-- We generate an enable pulse for the read side every 16 read clocks. This
-- provides for the worst-case situation where the write clock is 20MHz and
-- read clock is 125MHz.
p_rd_16_pulse : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_16_count <= (others => '0') after dly;
else
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- Register the start address on the enable pulse.
p_rd_addr_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if tx_mac_reset = '1' then
rd_addr_txfer <= (others => '0') after dly;
else
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- Generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end process;
-- Synchronize the toggle to the write side.
resync_rd_txfer_tog : temac_10_100_1000_sync_block
port map (
clk => tx_fifo_aclk,
data_in => rd_txfer_tog,
data_out => wr_txfer_tog_sync
);
-- Delay the synchronized toggle by one cycle.
p_wr_tog_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end process;
-- Generate an enable pulse from the toggle. The address should have been
-- steady on the wr clock input for at least one clock.
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- Capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_full <= '0' after dly;
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- Memory overflow occurs when the FIFO is full and there are no frames
-- available in the FIFO for transmission. If the collision window has
-- expired and there are no frames in the FIFO and the FIFO is full, then the
-- FIFO is in an overflow state. We must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- In full duplex mode, the FIFO memory can only overflow if the FIFO goes
-- full but there is no frame available to be retranmsitted. Therefore,
-- prevent signal from being asserted when store_frame signal is high, as
-- frame count is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
else '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- In half duplex mode, register write collision window to give address
-- counter sufficient time to update. This will prevent the signal from
-- being asserted when the store_frame signal is high, as the frame count
-- is being updated.
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0'
and wr_col_window_expire = '1'
else '0';
-- Register rd_col_window signal.
-- This signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_fifo_status : process (tx_fifo_aclk)
begin
if tx_fifo_aclk'event and tx_fifo_aclk = '1' then
if tx_fifo_reset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
wr_addr_slv <= std_logic_vector(wr_addr(10 downto 0));
rd_addr_slv <= std_logic_vector(rd_addr(10 downto 0));
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram(0);
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_l(0) <= rd_eof_data_bram_l(8);
rd_data_bram_l <= rd_eof_data_bram_l(7 downto 0);
ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_l_bram,
WEB => GND
);
-- Block RAM for lower address space (rd_addr(11) = '0')
rd_eof_bram_u(0) <= rd_eof_data_bram_u(8);
rd_data_bram_u <= rd_eof_data_bram_u(7 downto 0);
ramgen_u : BRAM_TDP_MACRO
generic map (
DEVICE => "7SERIES",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_u_unused,
DOB => rd_eof_data_bram_u,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram,
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_u_bram,
WEB => GND
);
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien32_rom is
port(
addr: in std_logic_vector(9 downto 0);
data: out std_logic_vector(2 downto 0)
);
end alien32_rom;
architecture content of alien32_rom is
type rgb_array is array(0 to 31) of std_logic_vector(2 downto 0);
type rom_type is array(0 to 31) of rgb_array;
signal rgb_row: rgb_array;
constant ALIEN: rom_type :=
(
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000")
);
begin
rgb_row <= ALIEN(conv_integer(addr(9 downto 5)));
data <= rgb_row(conv_integer(addr(4 downto 0)));
end content;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien32_rom is
port(
addr: in std_logic_vector(9 downto 0);
data: out std_logic_vector(2 downto 0)
);
end alien32_rom;
architecture content of alien32_rom is
type rgb_array is array(0 to 31) of std_logic_vector(2 downto 0);
type rom_type is array(0 to 31) of rgb_array;
signal rgb_row: rgb_array;
constant ALIEN: rom_type :=
(
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "111", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "111", "000", "111", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "111", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "111", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000"),
("000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000", "000")
);
begin
rgb_row <= ALIEN(conv_integer(addr(9 downto 5)));
data <= rgb_row(conv_integer(addr(4 downto 0)));
end content;
|
library ieee;
use ieee.std_logic_1164.all;
entity Moore is port(
X, CLK, RST: in std_logic;
Z: out std_logic;
);
end Moore;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2012 by Peter Wendrich ([email protected])
-- All Rights Reserved.
--
-- http://www.syntiac.com/chameleon.html
--
-- -----------------------------------------------------------------------
--
-- Conway's Game of Life simulator for Chameleon
--
-- -----------------------------------------------------------------------
--
--
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
architecture rtl of chameleon2 is
constant reset_cycles : integer := 131071;
-- Game of life settings
constant life_columns : integer := 512;
constant life_rows : integer := 472;
-- Game signals
signal vga_life_background : std_logic := '0';
signal vga_life_pixel : std_logic := '0';
signal vga_life_menu : std_logic := '0';
signal vga_life_rules : std_logic := '0';
-- Clocks
signal sysclk : std_logic;
signal clk_150 : std_logic;
signal sd_clk_loc : std_logic;
signal clk_locked : std_logic;
signal ena_1mhz : std_logic;
signal ena_1khz : std_logic;
signal no_clock : std_logic;
signal reset_button_n : std_logic;
-- Global signals
signal reset : std_logic;
-- MUX
signal mux_clk_reg : std_logic := '0';
signal mux_reg : unsigned(3 downto 0) := (others => '1');
signal mux_d_reg : unsigned(3 downto 0) := (others => '1');
-- LEDs
signal led_green : std_logic;
signal led_red : std_logic;
-- IR
signal ir : std_logic := '1';
-- PS/2 Keyboard
signal ps2_keyboard_clk_in : std_logic;
signal ps2_keyboard_dat_in : std_logic;
signal ps2_keyboard_clk_out : std_logic;
signal ps2_keyboard_dat_out : std_logic;
signal keyboard_trigger : std_logic;
signal keyboard_scancode : unsigned(7 downto 0);
-- PS/2 Mouse
signal ps2_mouse_clk_in: std_logic;
signal ps2_mouse_dat_in: std_logic;
signal ps2_mouse_clk_out: std_logic;
signal ps2_mouse_dat_out: std_logic;
signal mouse_present : std_logic;
signal mouse_active : std_logic;
signal mouse_trigger : std_logic;
signal mouse_left_button : std_logic;
signal mouse_middle_button : std_logic;
signal mouse_right_button : std_logic;
signal mouse_delta_x : signed(8 downto 0);
signal mouse_delta_y : signed(8 downto 0);
signal cursor_x : signed(11 downto 0) := to_signed(320, 12);
signal cursor_y : signed(11 downto 0) := to_signed(240, 12);
-- VGA
signal end_of_pixel : std_logic;
signal end_of_line : std_logic;
signal end_of_frame : std_logic;
signal currentX : unsigned(11 downto 0);
signal currentY : unsigned(11 downto 0);
type stage_t is record
ena_pixel : std_logic;
hsync : std_logic;
vsync : std_logic;
x : unsigned(11 downto 0);
y : unsigned(11 downto 0);
r : unsigned(4 downto 0);
g : unsigned(4 downto 0);
b : unsigned(4 downto 0);
end record;
signal vga_master : stage_t;
signal red_reg : unsigned(4 downto 0) := (others => '0');
signal grn_reg : unsigned(4 downto 0) := (others => '0');
signal blu_reg : unsigned(4 downto 0) := (others => '0');
-- Docking station
signal docking_station : std_logic;
signal docking_keys : unsigned(63 downto 0);
signal docking_restore_n : std_logic;
signal docking_irq : std_logic;
signal irq_n : std_logic;
signal docking_joystick1 : unsigned(6 downto 0);
signal docking_joystick2 : unsigned(6 downto 0);
signal docking_joystick3 : unsigned(6 downto 0);
signal docking_joystick4 : unsigned(6 downto 0);
signal docking_amiga_reset_n : std_logic;
signal docking_amiga_scancode : unsigned(7 downto 0);
signal phi_cnt : unsigned(7 downto 0);
signal phi_end_1 : std_logic;
procedure drawtext(signal video : inout std_logic; x : signed; y : signed; xpos : integer; ypos : integer; t : string) is
variable ch : character;
variable pixels : unsigned(0 to 63);
begin
if (x >= xpos) and ((x - xpos) < 8*t'length)
and (y >= ypos) and ((y - ypos) < 8) then
pixels := (others => '0');
ch := t(1 + (to_integer(x-xpos) / 8));
case ch is
when ''' => pixels := X"0808000000000000";
when '.' => pixels := X"00000000000C0C00";
when '0' => pixels := X"1C22222A22221C00";
when '1' => pixels := X"0818080808081C00";
when '2' => pixels := X"1C22020408103E00";
when '3' => pixels := X"1C22020C02221C00";
when '4' => pixels := X"0C14243E04040E00";
when '5' => pixels := X"3E20203C02221C00";
when '6' => pixels := X"1C20203C22221C00";
when '7' => pixels := X"3E02040810101000";
when '8' => pixels := X"1C22221C22221C00";
when '9' => pixels := X"1C22221E02021C00";
when ':' => pixels := X"000C0C000C0C0000";
when 'A' => pixels := X"1C22223E22222200";
when 'B' => pixels := X"3C22223C22223C00";
when 'C' => pixels := X"1C22202020221C00";
when 'D' => pixels := X"3C22222222223C00";
when 'E' => pixels := X"3E20203C20203E00";
when 'F' => pixels := X"3E20203C20202000";
when 'G' => pixels := X"1C22202E22221C00";
when 'H' => pixels := X"2222223E22222200";
when 'I' => pixels := X"1C08080808081C00";
when 'L' => pixels := X"1010101010101E00";
when 'M' => pixels := X"4163554941414100";
when 'N' => pixels := X"22322A2A26222200";
when 'O' => pixels := X"1C22222222221C00";
when 'P' => pixels := X"1C12121C10101000";
when 'R' => pixels := X"3C22223C28242200";
when 'S' => pixels := X"1C22201C02221C00";
when 'T' => pixels := X"3E08080808080800";
when 'U' => pixels := X"2222222222221C00";
when 'V' => pixels := X"2222221414080800";
when 'W' => pixels := X"4141412A2A141400";
when 'Y' => pixels := X"2222140808080800";
when others =>
null;
end case;
video <= pixels(to_integer(y - ypos) * 8 + (to_integer(x - xpos) mod 8));
end if;
end procedure;
procedure box(signal video : inout std_logic; x : signed; y : signed; xpos : integer; ypos : integer; ison : boolean) is
begin
if (abs(x - xpos) < 5) and (abs(y - ypos) < 5) and ison then
video <= '1';
elsif (abs(x - xpos) = 5) and (abs(y - ypos) < 5) then
video <= '1';
elsif (abs(x - xpos) < 5) and (abs(y - ypos) = 5) then
video <= '1';
end if;
end procedure;
begin
-- -----------------------------------------------------------------------
-- Unused pins
-- -----------------------------------------------------------------------
iec_clk_out <= '0';
iec_atn_out <= '0';
iec_dat_out <= '0';
iec_srq_out <= '0';
irq_out <= '0';
nmi_out <= '0';
sigma_l <= '0';
sigma_r <= '0';
-- -----------------------------------------------------------------------
-- VGA sync
-- -----------------------------------------------------------------------
hsync_n <= not vga_master.hsync;
vsync_n <= not vga_master.vsync;
-- -----------------------------------------------------------------------
-- Clocks and PLL
-- -----------------------------------------------------------------------
pllInstance : entity work.pll50
port map (
inclk0 => clk50m,
c0 => sysclk,
c1 => open,
c2 => clk_150,
c3 => sd_clk_loc,
locked => clk_locked
);
ram_clk <= sd_clk_loc;
-- -----------------------------------------------------------------------
-- Phi 2
-- -----------------------------------------------------------------------
myPhi2: entity work.chameleon_phi_clock
port map (
clk => sysclk,
phi2_n => phi2_n,
-- no_clock is high when there are no phiIn changes detected.
-- This signal allows switching between real I/O and internal emulation.
no_clock => no_clock,
-- docking_station is high when there are no phiIn changes (no_clock) and
-- the phi signal is low. Without docking station phi is pulled up.
docking_station => docking_station
);
-- -----------------------------------------------------------------------
-- Reset
-- -----------------------------------------------------------------------
myReset : entity work.gen_reset
generic map (
resetCycles => reset_cycles
)
port map (
clk => sysclk,
enable => '1',
button => '0',
reset => reset
);
-- -----------------------------------------------------------------------
-- 1 Mhz and 1 Khz clocks
-- -----------------------------------------------------------------------
my1Mhz : entity work.chameleon_1mhz
generic map (
clk_ticks_per_usec => 100
)
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1mhz_2 => open
);
my1Khz : entity work.chameleon_1khz
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
ena_1khz => ena_1khz
);
-- -----------------------------------------------------------------------
-- Chameleon IO, docking station and cartridge port
-- -----------------------------------------------------------------------
chameleon2_io_blk : block
begin
chameleon2_io_inst : entity work.chameleon2_io
generic map (
enable_docking_station => true,
enable_cdtv_remote => true,
enable_c64_joykeyb => true,
enable_c64_4player => true
)
port map (
clk => sysclk,
ena_1mhz => ena_1mhz,
phi2_n => phi2_n,
dotclock_n => dotclk_n,
reset => reset,
ir_data => ir_data,
clock_ior => clock_ior,
clock_iow => clock_iow,
ioef => ioef,
romlh => romlh,
dma_out => dma_out,
game_out => game_out,
exrom_out => exrom_out,
ba_in => ba_in,
-- rw_in => rw_in,
rw_out => rw_out,
sa_dir => sa_dir,
sa_oe => sa_oe,
sa15_out => sa15_out,
low_a => low_a,
sd_dir => sd_dir,
sd_oe => sd_oe,
low_d => low_d,
no_clock => no_clock,
docking_station => docking_station,
phi_cnt => phi_cnt,
phi_end_1 => phi_end_1,
joystick1 => docking_joystick1,
joystick2 => docking_joystick2,
joystick3 => docking_joystick3,
joystick4 => docking_joystick4,
keys => docking_keys,
restore_key_n => docking_restore_n
);
flash_cs <= '1';
mmc_cs <= '1';
rtc_cs <= '0';
end block;
-- -----------------------------------------------------------------------
-- Docking station
-- -----------------------------------------------------------------------
-- myDockingStation : entity work.chameleon_docking_station
-- port map (
-- clk => sysclk,
--
-- docking_station => docking_station,
--
-- dotclock_n => dotclock_n,
-- io_ef_n => ioef_n,
-- rom_lh_n => romlh_n,
-- irq_q => docking_irq,
--
-- joystick1 => docking_joystick1,
-- joystick2 => docking_joystick2,
-- joystick3 => docking_joystick3,
-- joystick4 => docking_joystick4,
-- keys => docking_keys,
-- restore_key_n => docking_restore_n,
--
-- amiga_power_led => led_green,
-- amiga_drive_led => led_red,
-- amiga_reset_n => docking_amiga_reset_n,
-- amiga_scancode => docking_amiga_scancode
-- );
-- -----------------------------------------------------------------------
-- PS2IEC multiplexer
-- -----------------------------------------------------------------------
io_ps2iec_inst : entity work.chameleon2_io_ps2iec
port map (
clk => sysclk,
ps2iec_sel => ps2iec_sel,
ps2iec => ps2iec,
ps2_mouse_clk => ps2_mouse_clk_in,
ps2_mouse_dat => ps2_mouse_dat_in,
ps2_keyboard_clk => ps2_keyboard_clk_in,
ps2_keyboard_dat => ps2_keyboard_dat_in,
iec_clk => open, --iec_clk_in,
iec_srq => open, --iec_srq_in,
iec_atn => open, --iec_atn_in,
iec_dat => open --iec_dat_in
);
-- -----------------------------------------------------------------------
-- LED, PS2 and reset shiftregister
-- -----------------------------------------------------------------------
io_shiftreg_inst : entity work.chameleon2_io_shiftreg
port map (
clk => sysclk,
ser_out_clk => ser_out_clk,
ser_out_dat => ser_out_dat,
ser_out_rclk => ser_out_rclk,
reset_c64 => reset,
reset_iec => reset,
ps2_mouse_clk => ps2_mouse_clk_out,
ps2_mouse_dat => ps2_mouse_dat_out,
ps2_keyboard_clk => ps2_keyboard_clk_out,
ps2_keyboard_dat => ps2_keyboard_dat_out,
led_green => led_green,
led_red => led_red
);
-- -----------------------------------------------------------------------
-- Mouse controller
-- -----------------------------------------------------------------------
myMouse : entity work.io_ps2_mouse
generic map (
ticksPerUsec => 100
)
port map (
clk => sysclk,
reset => reset,
ps2_clk_in => ps2_mouse_clk_in,
ps2_dat_in => ps2_mouse_dat_in,
ps2_clk_out => ps2_mouse_clk_out,
ps2_dat_out => ps2_mouse_dat_out,
mousePresent => mouse_present,
trigger => mouse_trigger,
leftButton => mouse_left_button,
middleButton => mouse_middle_button,
rightButton => mouse_right_button,
deltaX => mouse_delta_x,
deltaY => mouse_delta_y
);
-- -----------------------------------------------------------------------
-- VGA timing configured for 640x480
-- -----------------------------------------------------------------------
myVgaMaster : entity work.video_vga_master
generic map (
clkDivBits => 4
)
port map (
clk => sysclk,
-- 100 Mhz / (3+1) = 25 Mhz
clkDiv => X"3",
hSync => vga_master.hsync,
vSync => vga_master.vsync,
endOfPixel => end_of_pixel,
endOfLine => end_of_line,
endOfFrame => open,
currentX => currentX,
currentY => currentY,
-- Setup 640x480@60hz needs ~25 Mhz
hSyncPol => '0',
vSyncPol => '0',
xSize => to_unsigned(800, 12),
ySize => to_unsigned(525, 12),
xSyncFr => to_unsigned(656, 12), -- Sync pulse 96
xSyncTo => to_unsigned(752, 12),
ySyncFr => to_unsigned(500, 12), -- Sync pulse 2
ySyncTo => to_unsigned(502, 12)
);
-- -----------------------------------------------------------------------
--
-- Reposition mouse cursor.
-- I like to move it, move it. You like to move it, move it.
-- We like to move it, move it. So just move it!
-- -----------------------------------------------------------------------
process(sysclk)
variable newX : signed(11 downto 0);
variable newY : signed(11 downto 0);
begin
if rising_edge(sysclk) then
--
-- Calculate new cursor coordinates
-- deltaY is subtracted as line count runs top to bottom on the screen.
newX := cursor_x + mouse_delta_x;
newY := cursor_y - mouse_delta_y;
--
-- Limit mouse cursor to screen
if newX > 639 then
newX := to_signed(639, 12);
end if;
if newX < 0 then
newX := to_signed(0, 12);
end if;
if newY > 479 then
newY := to_signed(479, 12);
end if;
if newY < 0 then
newY := to_signed(0, 12);
end if;
--
-- Update cursor location
if mouse_trigger = '1' then
cursor_x <= newX;
cursor_y <= newY;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Game of life
-- -----------------------------------------------------------------------
game_of_life: block
subtype line_t is unsigned(0 to life_columns-1);
type game_field_t is array(0 to life_rows-1) of line_t;
type game_mode_t is (
MODE_STOP, MODE_STEP, MODE_SLOW, MODE_MEDIUM, MODE_FAST, MODE_ULTRA, MODE_MAX);
type game_state_t is (
GAME_STOP, GAME_WAIT_TIMER,
GAME_FETCHB, GAME_FETCH0, GAME_FETCH1,
GAME_READ, GAME_WAIT, GAME_CALC);
signal game_timer : unsigned(9 downto 0) := (others => '0');
signal game_mode : game_mode_t := MODE_STOP;
signal game_state : game_state_t := GAME_STOP;
signal game_field : game_field_t := (others => (others => '0'));
signal game_vga_line : line_t := (others => '0');
signal game_buffer_top : line_t := (others => '0');
signal game_buffer_mid : line_t := (others => '0');
signal game_buffer_bot : line_t := (others => '0');
signal game_buffer_0 : line_t := (others => '0');
signal game_buffer_shift : std_logic := '0';
signal game_buffer_shift_dly : std_logic := '0';
signal game_buffer_store_0 : std_logic := '0';
signal game_buffer_store_0_dly : std_logic := '0';
signal game_buffer_cur_row : integer range 0 to life_rows-1 := 0;
signal game_buffer_next_row : integer range 0 to life_rows-1 := 0;
-- By default rules are "Conway's game of life". Born with 3 neighbours, stay alive with 2 or 3.
signal game_rules0 : unsigned(0 to 8) := "000100000";
signal game_rules1 : unsigned(0 to 8) := "001100000";
signal vga_line_empty : std_logic := '0';
signal vga_line_read : std_logic := '0';
signal vga_line_read2 : std_logic := '0';
-- Game field memory control. By restricting the access to the gamefield
-- by a memory interface, it allows Quartus to synthesize Block-RAM.
--
signal mem_we : std_logic := '0';
signal mem_row : integer range 0 to life_rows-1 := 0;
signal mem_d : line_t;
signal mem_q : line_t;
signal mem_mouse : std_logic := '0'; -- Set when mouse update is performed
signal run_x : std_logic;
signal run_y : std_logic;
signal run_column : integer range 0 to life_columns;
signal run_row : integer range 0 to life_rows;
signal mouse_row : integer range 0 to life_rows-1 := 0;
signal mem_mouse_dly : std_logic := '0';
signal mouse_left_button_dly : std_logic := '0';
begin
process(sysclk)
begin
if rising_edge(sysclk) then
if mem_we = '1' then
game_field(mem_row) <= mem_d;
-- else
end if;
mem_q <= game_field(mem_row);
end if;
end process;
process(sysclk)
variable cycle_available : boolean;
variable life_neighbours : integer range 0 to 8;
begin
if rising_edge(sysclk) then
mouse_left_button_dly <= mouse_left_button;
vga_line_read <= '0';
mem_we <= '0';
mem_mouse <= '0';
mem_mouse_dly <= mem_mouse;
cycle_available := true;
if mem_mouse_dly = '1' then
-- Update playfield after mouse click
cycle_available := false;
mem_we <= '1';
mem_row <= mouse_row;
mem_d <= mem_q;
-- Set or clear the pixel in the column that was clicked
if mouse_left_button = '1' then
-- Left mouse button sets the pixel under the mouse
mem_d(to_integer(cursor_x-4)) <= '1';
else
-- Right mouse button clears the pixel under to mouse
mem_d(to_integer(cursor_x-4)) <= '0';
end if;
elsif (mouse_trigger = '1') and ((mouse_left_button = '1') or (mouse_right_button = '1')) then
-- Mouse button is clicked
if (cursor_y > 3) and (cursor_y < (life_rows+4))
and (cursor_x > 3) and (cursor_x < (life_columns+4)) then
-- Click was inside the playfield. Perform fetch of the clicked row.
-- The number of the row is also stored in "mouse_row" as it needs to be written
-- back after update as the mouse might have be moved in the mean time.
cycle_available := false;
mem_row <= (to_integer(cursor_y)-4);
mouse_row <= (to_integer(cursor_y)-4);
mem_mouse <= '1';
end if;
elsif (vga_line_read = '0') and (vga_line_empty = '1') then
-- Read data for VGA display
cycle_available := false;
mem_row <= run_row;
vga_line_read <= '1';
end if;
-- Memory has 1 cycle delay after which all three line buffers
-- (game_buffer_top, game_buffer_mid and game_buffer_bot) shift
-- one position.
game_buffer_shift <= '0';
game_buffer_store_0 <= '0';
game_buffer_shift_dly <= game_buffer_shift;
game_buffer_store_0_dly <= game_buffer_store_0;
if game_buffer_shift = '1' then
game_buffer_cur_row <= game_buffer_next_row;
game_buffer_next_row <= mem_row;
end if;
if game_buffer_shift_dly = '1' then
game_buffer_top <= game_buffer_mid;
game_buffer_mid <= game_buffer_bot;
game_buffer_bot <= mem_q;
if game_buffer_store_0_dly = '1' then
-- Store line 0 as it will be overwritten and we need it
-- for calculating the last line (world is a torus)
game_buffer_0 <= mem_q;
elsif game_buffer_next_row = 0 then
-- Use line 0 stored earlier in the buffer.
-- The first is already changed in mem, but we need
-- the original version for calculating the last line
-- as the world is a torus.
game_buffer_bot <= game_buffer_0;
end if;
end if;
-- Game state-machine.
case game_state is
when GAME_STOP =>
game_timer <= (others => '0');
if game_mode /= MODE_STOP then
game_state <= GAME_WAIT_TIMER;
end if;
when GAME_WAIT_TIMER =>
-- Count the time for slower speeds. Useful for testing
-- new patterns as maximum speed is really really fast.
if ena_1khz = '1' then
game_timer <= game_timer + 1;
end if;
case game_mode is
when MODE_STOP =>
game_state <= GAME_STOP;
when MODE_STEP =>
if game_timer >= 500 then
game_state <= GAME_FETCHB;
end if;
when MODE_SLOW =>
if game_timer >= 200 then
game_state <= GAME_FETCHB;
end if;
when MODE_MEDIUM =>
if game_timer >= 50 then
game_state <= GAME_FETCHB;
end if;
when MODE_FAST =>
if game_timer >= 15 then
game_state <= GAME_FETCHB;
end if;
when MODE_ULTRA =>
if game_timer >= 5 then
game_state <= GAME_FETCHB;
end if;
when MODE_MAX =>
game_state <= GAME_FETCHB;
end case;
when GAME_FETCHB =>
if cycle_available then
-- Fetch bottom row. As the game world is a torus, the
-- new version of the top row depends on the bottom row.
mem_row <= life_rows-1;
game_buffer_shift <= '1';
game_state <= GAME_FETCH0;
end if;
when GAME_FETCH0 =>
if cycle_available then
mem_row <= 0;
game_buffer_shift <= '1';
game_buffer_store_0 <= '1';
game_state <= GAME_FETCH1;
end if;
when GAME_FETCH1 =>
if cycle_available then
mem_row <= 1;
game_buffer_shift <= '1';
game_state <= GAME_WAIT;
end if;
when GAME_READ =>
-- Perform a line read from memory until we reach
-- line 0, which was the line we started with.
if game_buffer_next_row = 0 then
game_state <= GAME_STOP;
elsif cycle_available then
mem_row <= game_buffer_next_row + 1;
if game_buffer_next_row = (life_rows-1) then
-- Reached end of game world. Wrap around to top.
mem_row <= 0;
end if;
game_buffer_shift <= '1';
game_state <= GAME_WAIT;
end if;
when GAME_WAIT =>
-- Wait for all memory operations to finish.
if (game_buffer_shift = '0') and (game_buffer_shift_dly = '0') then
game_state <= GAME_CALC;
end if;
when GAME_CALC =>
if cycle_available then
mem_we <= '1';
mem_row <= game_buffer_cur_row;
for i in 0 to life_columns - 1 loop
life_neighbours := 0;
--
-- Count neighbours
--
if game_buffer_top((i-1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_top(i) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_top((i+1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_mid((i-1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_mid((i+1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_bot((i-1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_bot(i) = '1' then
life_neighbours := life_neighbours + 1;
end if;
if game_buffer_bot((i+1) mod life_columns) = '1' then
life_neighbours := life_neighbours + 1;
end if;
--
-- Determine next state of the cell
--
if game_buffer_mid(i) = '0' then
mem_d(i) <= game_rules0(life_neighbours);
else
mem_d(i) <= game_rules1(life_neighbours);
end if;
end loop;
-- Uncomment next line to implement "Scroll-down-only" for testing memory accesses.
-- mem_d <= game_buffer_top;
game_state <= GAME_READ;
end if;
when others =>
null;
end case;
end if;
end process;
--
-- Handle clicking in speed selection menu
process(sysclk)
begin
if rising_edge(sysclk) then
if mouse_left_button = '1' then
if (cursor_y > 24) and (cursor_y < 40) then
if (cursor_x > (512+8)) and (cursor_x < (512+24)) then
game_mode <= MODE_STOP;
end if;
if (cursor_x > (512+24)) and (cursor_x < (512+40)) then
game_mode <= MODE_STEP;
end if;
if (cursor_x > (512+40)) and (cursor_x < (512+56)) then
game_mode <= MODE_SLOW;
end if;
if (cursor_x > (512+56)) and (cursor_x < (512+72)) then
game_mode <= MODE_MEDIUM;
end if;
if (cursor_x > (512+72)) and (cursor_x < (512+88)) then
game_mode <= MODE_FAST;
end if;
if (cursor_x > (512+88)) and (cursor_x < (512+104)) then
game_mode <= MODE_ULTRA;
end if;
if (cursor_x > (512+104)) and (cursor_x < (512+120)) then
game_mode <= MODE_MAX;
end if;
end if;
end if;
end if;
end process;
--
-- Draw speed selection menu
process(sysclk)
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vga_life_menu <= '0';
drawtext(vga_life_menu, x, y, 512+8, 16, "SPEED");
box(vga_life_menu, x, y, 512+1*16, 32, game_mode = MODE_STOP);
box(vga_life_menu, x, y, 512+2*16, 32, game_mode = MODE_STEP);
box(vga_life_menu, x, y, 512+3*16, 32, game_mode = MODE_SLOW);
box(vga_life_menu, x, y, 512+4*16, 32, game_mode = MODE_MEDIUM);
box(vga_life_menu, x, y, 512+5*16, 32, game_mode = MODE_FAST);
box(vga_life_menu, x, y, 512+6*16, 32, game_mode = MODE_ULTRA);
box(vga_life_menu, x, y, 512+7*16, 32, game_mode = MODE_MAX);
end if;
end process;
--
-- Draw rule selection menu
process(sysclk)
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
vga_life_rules <= '0';
drawtext(vga_life_rules, x, y, 512+8, 104, "RULES:");
drawtext(vga_life_rules, x, y, 512+8, 112, "BORN ALIVE");
drawtext(vga_life_rules, x, y, 512+44, 124 + 0*16, "0");
drawtext(vga_life_rules, x, y, 512+44, 124 + 1*16, "1");
drawtext(vga_life_rules, x, y, 512+44, 124 + 2*16, "2");
drawtext(vga_life_rules, x, y, 512+44, 124 + 3*16, "3");
drawtext(vga_life_rules, x, y, 512+44, 124 + 4*16, "4");
drawtext(vga_life_rules, x, y, 512+44, 124 + 5*16, "5");
drawtext(vga_life_rules, x, y, 512+44, 124 + 6*16, "6");
drawtext(vga_life_rules, x, y, 512+44, 124 + 7*16, "7");
drawtext(vga_life_rules, x, y, 512+44, 124 + 8*16, "8");
for r in 0 to 8 loop
box(vga_life_rules, x, y, 512+32, 128 + r*16, game_rules0(r) = '1');
box(vga_life_rules, x, y, 512+64, 128 + r*16, game_rules1(r) = '1');
end loop;
drawtext(vga_life_rules, x, y, 512+8, 416, "CONWAY'S GAME");
drawtext(vga_life_rules, x, y, 512+8, 424, " OF LIFE");
drawtext(vga_life_rules, x, y, 512+8, 440, "BY PW.SOFT.");
drawtext(vga_life_rules, x, y, 512+8, 448, "SYNTIAC.COM");
end if;
end process;
--
-- Handle clicking in rule selection menu
process(sysclk)
begin
if rising_edge(sysclk) then
if (mouse_left_button_dly = '0') and (mouse_left_button = '1') then
for r in 0 to 8 loop
if (cursor_x > 512+24) and (cursor_x < 512+40)
and (cursor_y > 120+r*16) and (cursor_y < 136+r*16) then
game_rules0(r) <= not game_rules0(r);
end if;
if (cursor_x > 512+56) and (cursor_x < 512+72)
and (cursor_y > 120+r*16) and (cursor_y < 136+r*16) then
game_rules1(r) <= not game_rules1(r);
end if;
end loop;
end if;
end if;
end process;
process(sysclk)
begin
if rising_edge(sysclk) then
vga_line_read2 <= vga_line_read;
if vga_line_read = '1' then
vga_line_empty <= '0';
end if;
if vga_line_read2 = '1' then
game_vga_line <= mem_q;
end if;
if currentX = 3 then
run_x <= run_y;
end if;
if currentY = 4 then
run_y <= '1';
vga_line_empty <= not run_y;
end if;
if (run_x = '1') and (end_of_pixel = '1') then
if run_column = life_columns then
run_x <= '0';
run_column <= 0;
vga_life_background <= '0';
vga_life_pixel <= '0';
else
vga_life_background <= '1';
vga_life_pixel <= game_vga_line(run_column);
run_column <= run_column + 1;
end if;
end if;
if (run_y = '1') and (end_of_line = '1') then
run_row <= run_row + 1;
if run_row = (life_rows-1) then
run_y <= '0';
run_row <= 0;
else
vga_line_empty <= '1';
end if;
end if;
end if;
end process;
end block;
-- -----------------------------------------------------------------------
-- VGA colors
-- -----------------------------------------------------------------------
process(sysclk)
variable x : signed(11 downto 0);
variable y : signed(11 downto 0);
begin
x := signed(currentX);
y := signed(currentY);
if rising_edge(sysclk) then
-- Pipelined pixel out to get some timing slack.
red <= red_reg;
grn <= grn_reg;
blu <= blu_reg;
if end_of_pixel = '1' then
red_reg <= (others => '0');
grn_reg <= (others => '0');
blu_reg <= (others => '0');
--
-- Draw game
if vga_life_background = '1' then
red_reg <= "0" & (currentX(7 downto 4) xor (currentY(9 downto 8) & "10"));
grn_reg <= "0" & (currentX(7 downto 4) xor currentY(7 downto 4));
blu_reg <= "0" & (currentY(8 downto 5) xor (currentX(9 downto 8) & currentY(9 downto 8)));
end if;
if vga_life_pixel = '1' then
red_reg <= (others => '1');
grn_reg <= (others => '1');
blu_reg <= (others => '1');
end if;
if vga_life_menu = '1' then
red_reg <= (others => '1');
grn_reg <= (others => '1');
blu_reg <= (others => '1');
end if;
if vga_life_rules = '1' then
red_reg <= (others => '1');
grn_reg <= (others => '1');
blu_reg <= (others => '1');
end if;
--
-- One pixel border around the screen
if (currentX = 0) or (currentX = 639) or (currentY =0) or (currentY = 479) then
red_reg <= (others => '1');
grn_reg <= (others => '1');
blu_reg <= (others => '1');
end if;
--
-- Draw mouse cursor
if mouse_present = '1' then
if ((abs(x - cursor_x) > 1) and (abs(x - cursor_x) < 7) and (abs(y - cursor_y) = 0))
or ((abs(y - cursor_y) > 1) and (abs(y - cursor_y) < 7) and (abs(x - cursor_x) = 0)) then
red_reg <= (others => '1');
grn_reg <= (others => '1');
blu_reg <= (others => '0');
end if;
end if;
--
-- Never draw pixels outside the visual area
if (currentX >= 640) or (currentY >= 480) then
red_reg <= (others => '0');
grn_reg <= (others => '0');
blu_reg <= (others => '0');
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux5_tb is
end mux5_tb;
architecture TB of mux5_tb is
component mux5
port(
in0 : in std_logic_vector(4 downto 0);
in1 : in std_logic_vector(4 downto 0);
sel : in std_logic;
output : out std_logic_vector(4 downto 0));
end component;
signal in0 : std_logic_vector(4 downto 0);
signal in1 : std_logic_vector(4 downto 0);
signal sel : std_logic := '1';
signal output : std_logic_vector(4 downto 0);
begin -- TB
UUT: entity work.mux5
port map(in0 => in0,
in1 => in1,
sel => sel,
output => output);
process
variable temp : std_logic_vector(5 downto 0);
begin
for i in 0 to 63 loop
in1 <= std_logic_vector(to_unsigned(i,5));
for j in 0 to 63 loop
in0 <= std_logic_vector(to_unsigned(j,5));
sel<= not sel;
wait for 10 ns;
end loop; -- j
end loop; -- i
wait;
report "SIMULATION FINISHED!";
wait;
end process;
end TB;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2203.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02203ent IS
END c07s02b06x00p01n01i02203ent;
ARCHITECTURE c07s02b06x00p01n01i02203arch OF c07s02b06x00p01n01i02203ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 10 * 12; -- a should be 120
BEGIN
assert NOT(a = 120)
report "***PASSED TEST: c07s02b06x00p01n01i02203"
severity NOTE;
assert (a = 120)
report "***FAILED TEST: c07s02b06x00p01n01i02203 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2203.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02203ent IS
END c07s02b06x00p01n01i02203ent;
ARCHITECTURE c07s02b06x00p01n01i02203arch OF c07s02b06x00p01n01i02203ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 10 * 12; -- a should be 120
BEGIN
assert NOT(a = 120)
report "***PASSED TEST: c07s02b06x00p01n01i02203"
severity NOTE;
assert (a = 120)
report "***FAILED TEST: c07s02b06x00p01n01i02203 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02203arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2203.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02203ent IS
END c07s02b06x00p01n01i02203ent;
ARCHITECTURE c07s02b06x00p01n01i02203arch OF c07s02b06x00p01n01i02203ent IS
BEGIN
TESTING: PROCESS
constant a : integer := 10 * 12; -- a should be 120
BEGIN
assert NOT(a = 120)
report "***PASSED TEST: c07s02b06x00p01n01i02203"
severity NOTE;
assert (a = 120)
report "***FAILED TEST: c07s02b06x00p01n01i02203 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02203arch;
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
-- These are the default architecture parameters. A configuration is
-- expected to provide its own configuration for these parameters. As VHDL
-- does not support overriding of constants (or something similar) each
-- testbench in tb_arch provides its own modified copy of this file, and
-- the architecture is compiled from scratch within the tb_arch/xx
-- directory.
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_d_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_d_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:54 wig Exp $
-- $Date: 2004/04/06 10:49:54 $
-- $Log: inst_d_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:54 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_d_e
--
architecture rtl of inst_d_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SIB_mux_pre_FCX is
Port ( -- Scan Interface client --------------
SI : in STD_LOGIC; -- ScanInPort
CE : in STD_LOGIC; -- CaptureEnPort
SE : in STD_LOGIC; -- ShiftEnPort
UE : in STD_LOGIC; -- UpdateEnPort
SEL : in STD_LOGIC; -- SelectPort
RST : in STD_LOGIC; -- ResetPort
TCK : in STD_LOGIC; -- TCKPort
SO : out STD_LOGIC; -- ScanOutPort
toF : out STD_LOGIC; -- To F flag of the upper hierarchical level
toC : out STD_LOGIC; -- To C flag of the upper hierarchical level
-- Scan Interface host ----------------
fromSO : in STD_LOGIC; -- ScanInPort
toCE : out STD_LOGIC; -- ToCaptureEnPort
toSE : out STD_LOGIC; -- ToShiftEnPort
toUE : out STD_LOGIC; -- ToUpdateEnPort
toSEL : out STD_LOGIC; -- ToSelectPort
toRST : out STD_LOGIC; -- ToResetPort
toTCK : out STD_LOGIC; -- ToTCKPort
toSI : out STD_LOGIC; -- ScanOutPort
fromF : in STD_LOGIC; -- From an OR of all F flags in the underlying network segment
fromC : in STD_LOGIC -- From an AND of all C flags in the underlying network segment
);
end SIB_mux_pre_FCX;
architecture SIB_mux_pre_FCX_arch of SIB_mux_pre_FCX is
component ScanRegister_for_SIBFCX is
Generic (Size : positive;
BitOrder : string; -- MSBLSB / LSBMSB
SOSource : natural;
ResetValue : STD_LOGIC_VECTOR);
Port ( SI : in STD_LOGIC;
CE : in STD_LOGIC;
SE : in STD_LOGIC;
UE : in STD_LOGIC;
SEL : in STD_LOGIC;
RST : in STD_LOGIC;
TCK : in STD_LOGIC;
SO : out STD_LOGIC;
CaptureSource : in STD_LOGIC_VECTOR (Size-1 downto 0);
ScanRegister_out : out STD_LOGIC_VECTOR (Size-1 downto 0);
ue_mux_out : out STD_LOGIC_VECTOR (Size-1 downto 0));
end component;
component ScanMux is
Generic (ControlSize : positive);
Port ( ScanMux_in : in STD_LOGIC_VECTOR((2**ControlSize)-1 downto 0);
SelectedBy : in STD_LOGIC_VECTOR(ControlSize-1 downto 0);
ScanMux_out : out STD_LOGIC);
end component;
signal SIBmux_out : STD_LOGIC;
signal SR_so : STD_LOGIC;
signal SR_do : STD_LOGIC_VECTOR (3 downto 0);
signal SR_ci : STD_LOGIC_VECTOR (3 downto 0);
signal sr_update_mux_out : STD_LOGIC_VECTOR (3 downto 0);
signal C_sync, F_sync : STD_LOGIC;
signal C_sync_first, F_sync_first : STD_LOGIC;
signal F_sync_delayed_copy, sticky_f_posedge : STD_LOGIC;
begin
SO <= SR_so; -- Source SR
toCE <= CE;
toSE <= SE;
toUE <= UE;
toSEL <= SEL and SR_do(3); -- SEL & S bit
toRST <= RST;
toTCK <= TCK;
toSI <= SI; -- Source SI
SR_ci(3) <= SR_do(3); -- Sxcf
SR_ci(2) <= SR_do(2); -- sXcf
SR_ci(1) <= C_sync; -- sxCf
SR_ci(0) <= sticky_f_posedge; -- sxcF
toF <= fromF and SR_do(2); -- F flag from lower levels AND X bit
toC <= fromC or not SR_do(2); -- C flag from lower levels OR NOT X bit
f_edge_detector : process (TCK, RST)
begin
if RST = '1' then
sticky_f_posedge <= '0';
elsif TCK'event and TCK = '0' then
if F_sync_delayed_copy = '0' and F_sync = '1' then -- edge detector
sticky_f_posedge <= '1';
elsif UE = '1' and SEL = '1' and sr_update_mux_out(0) = '0' then -- clear sticky F flag when F is updated with 0
sticky_f_posedge <= '0';
end if;
end if;
end process; -- f_edge_detector
synchronizer : process( TCK )
begin
if TCK'event and TCK = '0' then
F_sync_first <= fromF;
F_sync <= F_sync_first;
F_sync_delayed_copy <= F_sync;
C_sync_first <= fromC;
C_sync <= C_sync_first;
end if ;
end process ; -- synchronizer
SR : ScanRegister_for_SIBFCX
Generic map (Size => 4,
BitOrder => "MSBLSB", -- MSBLSB / LSBMSB
SOSource => 0,
ResetValue => "0110") -- ResetValue S=0, X=1, C=1, F=0
Port map ( SI => SIBmux_out, -- ScanInSource SIBmux_out
CE => CE,
SE => SE,
UE => UE,
SEL => SEL,
RST => RST,
TCK => TCK,
SO => SR_so,
CaptureSource => SR_ci, -- CaptureSource SR
ScanRegister_out => SR_do,
ue_mux_out => sr_update_mux_out);
SIBmux : ScanMux
Generic map ( ControlSize => 1)
Port map ( ScanMux_in(0) => SI, -- 1'b0 : SI
ScanMux_in(1) => fromSO, -- 1'b1 : fromSO
SelectedBy => SR_do(3 downto 3), --SelectedBy SR
ScanMux_out => SIBmux_out);
end SIB_mux_pre_FCX_arch; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2015_12", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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sw==
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: RickWare
--
-- Create Date: 07:18:36 11/01/2007
-- Design Name:
-- Module Name: ROM_Gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implementacion de un ROM generico de tamaño: 2^n localidades
-- con cada localidad de m bits
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ROM_Gen is
Generic ( m : integer := 8; --m define el ancho de la memoria
n : integer := 16); --n define el numero de localidades de memoria
Port ( addr : in INTEGER RANGE 0 to n-1;
data : out STD_LOGIC_VECTOR (m-1 downto 0));
end ROM_Gen;
architecture Behavioral of ROM_Gen is
TYPE vector_array IS array (0 to n-1) of STD_LOGIC_VECTOR (m-1 downto 0);
CONSTANT memory: vector_array := (X"AC", X"0F", X"17", X"9E",
X"F0", X"AA", X"69", X"AF",
X"D5", X"42", X"00", X"27",
X"03", X"30", X"1A", X"BB");
begin
data <= memory(addr);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: RickWare
--
-- Create Date: 07:18:36 11/01/2007
-- Design Name:
-- Module Name: ROM_Gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implementacion de un ROM generico de tamaño: 2^n localidades
-- con cada localidad de m bits
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ROM_Gen is
Generic ( m : integer := 8; --m define el ancho de la memoria
n : integer := 16); --n define el numero de localidades de memoria
Port ( addr : in INTEGER RANGE 0 to n-1;
data : out STD_LOGIC_VECTOR (m-1 downto 0));
end ROM_Gen;
architecture Behavioral of ROM_Gen is
TYPE vector_array IS array (0 to n-1) of STD_LOGIC_VECTOR (m-1 downto 0);
CONSTANT memory: vector_array := (X"AC", X"0F", X"17", X"9E",
X"F0", X"AA", X"69", X"AF",
X"D5", X"42", X"00", X"27",
X"03", X"30", X"1A", X"BB");
begin
data <= memory(addr);
end Behavioral;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_cmp_lt
-- VHDL created on Thu Feb 15 17:05:08 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cmp_lt is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end fp_cmp_lt;
architecture normal of fp_cmp_lt is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid6_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid7_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid8_fpCompareTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal exp_x_uid9_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid10_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid11_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid12_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid13_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid14_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid16_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal exp_y_uid23_fpCompareTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal frac_y_uid24_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid25_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid26_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid27_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid28_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid30_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneIsNaN_uid34_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xNotZero_uid39_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal yNotZero_uid40_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXPS_uid41_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracXPS_uid41_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal fracYPS_uid42_fpCompareTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expFracX_uid43_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal expFracY_uid45_fpCompareTest_q : STD_LOGIC_VECTOR (30 downto 0);
signal efxGTefy_uid47_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxGTefy_uid47_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal efxLTefy_uid48_fpCompareTest_a : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_b : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_o : STD_LOGIC_VECTOR (32 downto 0);
signal efxLTefy_uid48_fpCompareTest_c : STD_LOGIC_VECTOR (0 downto 0);
signal signX_uid52_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid53_fpCompareTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal two_uid54_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal concSXSY_uid55_fpCompareTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal sxLTsy_uid56_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xorSigns_uid57_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsy_uid58_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal expFracCompMux_uid59_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal oneNonZero_uid62_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rc2_uid63_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sxEQsyExpFracCompMux_uid64_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal r_uid65_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal rPostExc_uid66_fpCompareTest_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- GND(CONSTANT,0)
GND_q <= "0";
-- cstAllZWE_uid8_fpCompareTest(CONSTANT,7)
cstAllZWE_uid8_fpCompareTest_q <= "00000000";
-- exp_y_uid23_fpCompareTest(BITSELECT,22)@0
exp_y_uid23_fpCompareTest_b <= b(30 downto 23);
-- excZ_y_uid25_fpCompareTest(LOGICAL,24)@0
excZ_y_uid25_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- yNotZero_uid40_fpCompareTest(LOGICAL,39)@0
yNotZero_uid40_fpCompareTest_q <= not (excZ_y_uid25_fpCompareTest_q);
-- exp_x_uid9_fpCompareTest(BITSELECT,8)@0
exp_x_uid9_fpCompareTest_b <= a(30 downto 23);
-- excZ_x_uid11_fpCompareTest(LOGICAL,10)@0
excZ_x_uid11_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllZWE_uid8_fpCompareTest_q ELSE "0";
-- xNotZero_uid39_fpCompareTest(LOGICAL,38)@0
xNotZero_uid39_fpCompareTest_q <= not (excZ_x_uid11_fpCompareTest_q);
-- oneNonZero_uid62_fpCompareTest(LOGICAL,61)@0
oneNonZero_uid62_fpCompareTest_q <= xNotZero_uid39_fpCompareTest_q or yNotZero_uid40_fpCompareTest_q;
-- two_uid54_fpCompareTest(CONSTANT,53)
two_uid54_fpCompareTest_q <= "10";
-- signX_uid52_fpCompareTest(BITSELECT,51)@0
signX_uid52_fpCompareTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signY_uid53_fpCompareTest(BITSELECT,52)@0
signY_uid53_fpCompareTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- concSXSY_uid55_fpCompareTest(BITJOIN,54)@0
concSXSY_uid55_fpCompareTest_q <= signX_uid52_fpCompareTest_b & signY_uid53_fpCompareTest_b;
-- sxLTsy_uid56_fpCompareTest(LOGICAL,55)@0
sxLTsy_uid56_fpCompareTest_q <= "1" WHEN concSXSY_uid55_fpCompareTest_q = two_uid54_fpCompareTest_q ELSE "0";
-- rc2_uid63_fpCompareTest(LOGICAL,62)@0
rc2_uid63_fpCompareTest_q <= sxLTsy_uid56_fpCompareTest_q and oneNonZero_uid62_fpCompareTest_q;
-- frac_x_uid10_fpCompareTest(BITSELECT,9)@0
frac_x_uid10_fpCompareTest_b <= a(22 downto 0);
-- fracXPS_uid41_fpCompareTest(LOGICAL,40)@0
fracXPS_uid41_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => xNotZero_uid39_fpCompareTest_q(0)) & xNotZero_uid39_fpCompareTest_q));
fracXPS_uid41_fpCompareTest_q <= frac_x_uid10_fpCompareTest_b and fracXPS_uid41_fpCompareTest_b;
-- expFracX_uid43_fpCompareTest(BITJOIN,42)@0
expFracX_uid43_fpCompareTest_q <= exp_x_uid9_fpCompareTest_b & fracXPS_uid41_fpCompareTest_q;
-- frac_y_uid24_fpCompareTest(BITSELECT,23)@0
frac_y_uid24_fpCompareTest_b <= b(22 downto 0);
-- fracYPS_uid42_fpCompareTest(LOGICAL,41)@0
fracYPS_uid42_fpCompareTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((22 downto 1 => yNotZero_uid40_fpCompareTest_q(0)) & yNotZero_uid40_fpCompareTest_q));
fracYPS_uid42_fpCompareTest_q <= frac_y_uid24_fpCompareTest_b and fracYPS_uid42_fpCompareTest_b;
-- expFracY_uid45_fpCompareTest(BITJOIN,44)@0
expFracY_uid45_fpCompareTest_q <= exp_y_uid23_fpCompareTest_b & fracYPS_uid42_fpCompareTest_q;
-- efxGTefy_uid47_fpCompareTest(COMPARE,46)@0
efxGTefy_uid47_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxGTefy_uid47_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxGTefy_uid47_fpCompareTest_a) - UNSIGNED(efxGTefy_uid47_fpCompareTest_b));
efxGTefy_uid47_fpCompareTest_c(0) <= efxGTefy_uid47_fpCompareTest_o(32);
-- efxLTefy_uid48_fpCompareTest(COMPARE,47)@0
efxLTefy_uid48_fpCompareTest_a <= STD_LOGIC_VECTOR("00" & expFracX_uid43_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_b <= STD_LOGIC_VECTOR("00" & expFracY_uid45_fpCompareTest_q);
efxLTefy_uid48_fpCompareTest_o <= STD_LOGIC_VECTOR(UNSIGNED(efxLTefy_uid48_fpCompareTest_a) - UNSIGNED(efxLTefy_uid48_fpCompareTest_b));
efxLTefy_uid48_fpCompareTest_c(0) <= efxLTefy_uid48_fpCompareTest_o(32);
-- expFracCompMux_uid59_fpCompareTest(MUX,58)@0
expFracCompMux_uid59_fpCompareTest_s <= signX_uid52_fpCompareTest_b;
expFracCompMux_uid59_fpCompareTest_combproc: PROCESS (expFracCompMux_uid59_fpCompareTest_s, efxLTefy_uid48_fpCompareTest_c, efxGTefy_uid47_fpCompareTest_c)
BEGIN
CASE (expFracCompMux_uid59_fpCompareTest_s) IS
WHEN "0" => expFracCompMux_uid59_fpCompareTest_q <= efxLTefy_uid48_fpCompareTest_c;
WHEN "1" => expFracCompMux_uid59_fpCompareTest_q <= efxGTefy_uid47_fpCompareTest_c;
WHEN OTHERS => expFracCompMux_uid59_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xorSigns_uid57_fpCompareTest(LOGICAL,56)@0
xorSigns_uid57_fpCompareTest_q <= signX_uid52_fpCompareTest_b xor signY_uid53_fpCompareTest_b;
-- sxEQsy_uid58_fpCompareTest(LOGICAL,57)@0
sxEQsy_uid58_fpCompareTest_q <= not (xorSigns_uid57_fpCompareTest_q);
-- sxEQsyExpFracCompMux_uid64_fpCompareTest(LOGICAL,63)@0
sxEQsyExpFracCompMux_uid64_fpCompareTest_q <= sxEQsy_uid58_fpCompareTest_q and expFracCompMux_uid59_fpCompareTest_q;
-- r_uid65_fpCompareTest(LOGICAL,64)@0
r_uid65_fpCompareTest_q <= sxEQsyExpFracCompMux_uid64_fpCompareTest_q or rc2_uid63_fpCompareTest_q;
-- cstZeroWF_uid7_fpCompareTest(CONSTANT,6)
cstZeroWF_uid7_fpCompareTest_q <= "00000000000000000000000";
-- fracXIsZero_uid27_fpCompareTest(LOGICAL,26)@0
fracXIsZero_uid27_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_y_uid24_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid28_fpCompareTest(LOGICAL,27)@0
fracXIsNotZero_uid28_fpCompareTest_q <= not (fracXIsZero_uid27_fpCompareTest_q);
-- cstAllOWE_uid6_fpCompareTest(CONSTANT,5)
cstAllOWE_uid6_fpCompareTest_q <= "11111111";
-- expXIsMax_uid26_fpCompareTest(LOGICAL,25)@0
expXIsMax_uid26_fpCompareTest_q <= "1" WHEN exp_y_uid23_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_y_uid30_fpCompareTest(LOGICAL,29)@0
excN_y_uid30_fpCompareTest_q <= expXIsMax_uid26_fpCompareTest_q and fracXIsNotZero_uid28_fpCompareTest_q;
-- fracXIsZero_uid13_fpCompareTest(LOGICAL,12)@0
fracXIsZero_uid13_fpCompareTest_q <= "1" WHEN cstZeroWF_uid7_fpCompareTest_q = frac_x_uid10_fpCompareTest_b ELSE "0";
-- fracXIsNotZero_uid14_fpCompareTest(LOGICAL,13)@0
fracXIsNotZero_uid14_fpCompareTest_q <= not (fracXIsZero_uid13_fpCompareTest_q);
-- expXIsMax_uid12_fpCompareTest(LOGICAL,11)@0
expXIsMax_uid12_fpCompareTest_q <= "1" WHEN exp_x_uid9_fpCompareTest_b = cstAllOWE_uid6_fpCompareTest_q ELSE "0";
-- excN_x_uid16_fpCompareTest(LOGICAL,15)@0
excN_x_uid16_fpCompareTest_q <= expXIsMax_uid12_fpCompareTest_q and fracXIsNotZero_uid14_fpCompareTest_q;
-- oneIsNaN_uid34_fpCompareTest(LOGICAL,33)@0
oneIsNaN_uid34_fpCompareTest_q <= excN_x_uid16_fpCompareTest_q or excN_y_uid30_fpCompareTest_q;
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- rPostExc_uid66_fpCompareTest(MUX,65)@0
rPostExc_uid66_fpCompareTest_s <= oneIsNaN_uid34_fpCompareTest_q;
rPostExc_uid66_fpCompareTest_combproc: PROCESS (rPostExc_uid66_fpCompareTest_s, r_uid65_fpCompareTest_q, GND_q)
BEGIN
CASE (rPostExc_uid66_fpCompareTest_s) IS
WHEN "0" => rPostExc_uid66_fpCompareTest_q <= r_uid65_fpCompareTest_q;
WHEN "1" => rPostExc_uid66_fpCompareTest_q <= GND_q;
WHEN OTHERS => rPostExc_uid66_fpCompareTest_q <= (others => '0');
END CASE;
END PROCESS;
-- xOut(GPOUT,4)@0
q <= rPostExc_uid66_fpCompareTest_q;
END normal;
|
-- #############################################################################
-- DE0_Nano_top_level.vhd
-- ======================
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
LED : out std_logic_vector(7 downto 0);
-- KEY_N
KEY_N : in std_logic_vector(1 downto 0);
-- SW
SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
EPCS_ASDO : out std_logic;
EPCS_DATA0 : in std_logic;
EPCS_DCLK : out std_logic;
EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
G_SENSOR_CS_N : out std_logic;
G_SENSOR_INT : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- ADC
ADC_CS_N : out std_logic;
ADC_SADDR : out std_logic;
ADC_SCLK : out std_logic;
ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
GPIO_2 : inout std_logic_vector(12 downto 0);
GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0 : inout std_logic_vector(33 downto 0);
GPIO_0_IN : in std_logic_vector(1 downto 0);
-- GPIO_1
GPIO_1 : inout std_logic_vector(33 downto 0);
GPIO_1_IN : in std_logic_vector(1 downto 0)
);
end entity DE0_Nano_top_level;
architecture rtl of DE0_Nano_top_level is
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
use work.rec01_pkg.all;
entity rec01 is
port (inp : myrec;
o : out std_logic);
end rec01;
architecture behav of rec01 is
begin
o <= inp.a or inp.b;
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity slice_number is
Generic(n :natural := 7);
Port ( integerNumber : in std_logic_vector(n downto 0); -- recebe um vetor de bits da interface
receives_input : in std_logic;
MDDreset : in std_logic;
clk : in std_logic;
finish : out std_logic;
unity : out STD_LOGIC_vector(9 downto 0); --retorna o codigo do display do digito presente na unidade
dicker : out STD_LOGIC_vector(9 downto 0); -- retorna o codigo do display do digito presente na dezena
hundred : out STD_LOGIC_vector(9 downto 0) -- retorna o codigo do display do digito presente na centena
);
end slice_number;
architecture Behavioral of slice_number is
----------- #### SINAIS #### --------
signal dividendo : std_logic_vector(n downto 0);
signal dez,cem : std_logic_vector(n downto 0);
signal enable : std_logic;
signal finishDez, finishCem : std_logic;
signal quocienteCem, quocienteDez : std_logic_vector(n downto 0);
signal restoCem, restoDez : std_logic_vector(n downto 0);
----------- #### COMPONENTES #### --------
begin
dividendo <= integerNumber;
enable <= receives_input;
MaquinaDeDividirCentena: entity work.MaquinaDeDividir port map
(clk, dividendo, cem, restoCem, quocienteCem, enable, finishDez, MDDreset);
MaquinaDeDividirDezena : entity work.MaquinaDeDividir port map
(clk, restoCem, dez, restoDez, quocienteDez, finishDez, finishCem, MDDreset);
Dez <= "00001010";
Cem <= "01100100";
finish <= (finishCem and finishDez);
-- quocienteCem <= std_logic_vector(unsigned(quocienteDez)-unsigned(quocienteDez)*10);
process(clk,quocienteCem, quocienteDez, restoDez)
begin
if (rising_edge(clk) and receives_input = '1') then
hundred(9 downto 4) <= "100011";
hundred(3 downto 0) <= quocienteCem(3 downto 0);
dicker(9 downto 4) <= "100011";
dicker(3 downto 0) <= quocienteDez(3 downto 0);
unity(9 downto 4) <= "100011";
unity(3 downto 0) <= restoDez(3 downto 0);
-- hundred <= "100011" & quocienteCem(3 downto 0);
-- dicker <= "100011" & quocienteDez(3 downto 0);
-- unity <= "100011" & restoDez(3 downto 0);
end if;
end process;
end Behavioral;
|
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